mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_flash_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_flash_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
Anna Bridge 186:707f6e361f3e 5 * @brief Header file of Flash HAL Extended module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32L0xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32L0xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
Anna Bridge 186:707f6e361f3e 51 /** @addtogroup FLASHEx
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
Anna Bridge 186:707f6e361f3e 55 /** @addtogroup FLASHEx_Private_Constants
Anna Bridge 186:707f6e361f3e 56 * @{
Anna Bridge 186:707f6e361f3e 57 */
Anna Bridge 186:707f6e361f3e 58 #define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
Anna Bridge 186:707f6e361f3e 59
Anna Bridge 186:707f6e361f3e 60 #define FLASH_NBPAGES_MAX (FLASH_SIZE / FLASH_PAGE_SIZE)
Anna Bridge 186:707f6e361f3e 61
Anna Bridge 186:707f6e361f3e 62 #define WRP_MASK_LOW (0x0000FFFFU)
Anna Bridge 186:707f6e361f3e 63 #define WRP_MASK_HIGH (0xFFFF0000U)
Anna Bridge 186:707f6e361f3e 64
Anna Bridge 186:707f6e361f3e 65 /**
Anna Bridge 186:707f6e361f3e 66 * @}
Anna Bridge 186:707f6e361f3e 67 */
Anna Bridge 186:707f6e361f3e 68
Anna Bridge 186:707f6e361f3e 69 /** @addtogroup FLASHEx_Private_Macros
Anna Bridge 186:707f6e361f3e 70 * @{
Anna Bridge 186:707f6e361f3e 71 */
Anna Bridge 186:707f6e361f3e 72
Anna Bridge 186:707f6e361f3e 73 #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))
Anna Bridge 186:707f6e361f3e 74
Anna Bridge 186:707f6e361f3e 75 #define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | \
Anna Bridge 186:707f6e361f3e 76 OPTIONBYTE_USER | OPTIONBYTE_BOR | OPTIONBYTE_BOOT_BIT1)))
Anna Bridge 186:707f6e361f3e 77
Anna Bridge 186:707f6e361f3e 78 #define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
Anna Bridge 186:707f6e361f3e 79 ((__VALUE__) == OB_WRPSTATE_ENABLE))
Anna Bridge 186:707f6e361f3e 80
Anna Bridge 186:707f6e361f3e 81 #define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U))
Anna Bridge 186:707f6e361f3e 82
Anna Bridge 186:707f6e361f3e 83 #define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
Anna Bridge 186:707f6e361f3e 84 ((__LEVEL__) == OB_RDP_LEVEL_1) ||\
Anna Bridge 186:707f6e361f3e 85 ((__LEVEL__) == OB_RDP_LEVEL_2))
Anna Bridge 186:707f6e361f3e 86
Anna Bridge 186:707f6e361f3e 87 #define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \
Anna Bridge 186:707f6e361f3e 88 ((__LEVEL__) == OB_BOR_LEVEL1) || \
Anna Bridge 186:707f6e361f3e 89 ((__LEVEL__) == OB_BOR_LEVEL2) || \
Anna Bridge 186:707f6e361f3e 90 ((__LEVEL__) == OB_BOR_LEVEL3) || \
Anna Bridge 186:707f6e361f3e 91 ((__LEVEL__) == OB_BOR_LEVEL4) || \
Anna Bridge 186:707f6e361f3e 92 ((__LEVEL__) == OB_BOR_LEVEL5))
Anna Bridge 186:707f6e361f3e 93
Anna Bridge 186:707f6e361f3e 94 #define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
Anna Bridge 186:707f6e361f3e 95
Anna Bridge 186:707f6e361f3e 96 #define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
Anna Bridge 186:707f6e361f3e 97
Anna Bridge 186:707f6e361f3e 98 #define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
Anna Bridge 186:707f6e361f3e 99
Anna Bridge 186:707f6e361f3e 100 #if defined(FLASH_OPTR_WPRMOD) && defined(FLASH_OPTR_BFB2)
Anna Bridge 186:707f6e361f3e 101
Anna Bridge 186:707f6e361f3e 102 #define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG))
Anna Bridge 186:707f6e361f3e 103
Anna Bridge 186:707f6e361f3e 104 #elif defined(FLASH_OPTR_WPRMOD) && !defined(FLASH_OPTR_BFB2)
Anna Bridge 186:707f6e361f3e 105
Anna Bridge 186:707f6e361f3e 106 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP)
Anna Bridge 186:707f6e361f3e 107
Anna Bridge 186:707f6e361f3e 108 #elif !defined(FLASH_OPTR_WPRMOD) && defined(FLASH_OPTR_BFB2)
Anna Bridge 186:707f6e361f3e 109
Anna Bridge 186:707f6e361f3e 110 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)
Anna Bridge 186:707f6e361f3e 111
Anna Bridge 186:707f6e361f3e 112 #endif /* FLASH_OPTR_WPRMOD && FLASH_OPTR_BFB2 */
Anna Bridge 186:707f6e361f3e 113
Anna Bridge 186:707f6e361f3e 114 #if defined(FLASH_OPTR_WPRMOD)
Anna Bridge 186:707f6e361f3e 115
Anna Bridge 186:707f6e361f3e 116 #define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \
Anna Bridge 186:707f6e361f3e 117 ((__VALUE__) == OB_PCROP_STATE_ENABLE))
Anna Bridge 186:707f6e361f3e 118
Anna Bridge 186:707f6e361f3e 119 #define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))
Anna Bridge 186:707f6e361f3e 120 #endif /* FLASH_OPTR_WPRMOD */
Anna Bridge 186:707f6e361f3e 121
Anna Bridge 186:707f6e361f3e 122 #if defined(FLASH_OPTR_BFB2)
Anna Bridge 186:707f6e361f3e 123
Anna Bridge 186:707f6e361f3e 124 #define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
Anna Bridge 186:707f6e361f3e 125
Anna Bridge 186:707f6e361f3e 126 #endif /* FLASH_OPTR_BFB2 */
Anna Bridge 186:707f6e361f3e 127
Anna Bridge 186:707f6e361f3e 128 #define IS_OB_BOOT1(__BOOT_BIT1__) (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET))
Anna Bridge 186:707f6e361f3e 129 #define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
Anna Bridge 186:707f6e361f3e 130 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
Anna Bridge 186:707f6e361f3e 131 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD))
Anna Bridge 186:707f6e361f3e 132
Anna Bridge 186:707f6e361f3e 133
Anna Bridge 186:707f6e361f3e 134 /** @defgroup FLASHEx_Address FLASHEx Address
Anna Bridge 186:707f6e361f3e 135 * @{
Anna Bridge 186:707f6e361f3e 136 */
Anna Bridge 186:707f6e361f3e 137
Anna Bridge 186:707f6e361f3e 138 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
Anna Bridge 186:707f6e361f3e 139
Anna Bridge 186:707f6e361f3e 140 #define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))
Anna Bridge 186:707f6e361f3e 141 #define IS_FLASH_DATA_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK1_END))
Anna Bridge 186:707f6e361f3e 142 #define IS_FLASH_DATA_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BANK2_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END))
Anna Bridge 186:707f6e361f3e 143 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
Anna Bridge 186:707f6e361f3e 144 #define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + (FLASH_SIZE >> 1))))
Anna Bridge 186:707f6e361f3e 145 #define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
Anna Bridge 186:707f6e361f3e 146 #else
Anna Bridge 186:707f6e361f3e 147 #define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_END))
Anna Bridge 186:707f6e361f3e 148 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE)))
Anna Bridge 186:707f6e361f3e 149 #endif
Anna Bridge 186:707f6e361f3e 150
Anna Bridge 186:707f6e361f3e 151 #define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
Anna Bridge 186:707f6e361f3e 152
Anna Bridge 186:707f6e361f3e 153 /**
Anna Bridge 186:707f6e361f3e 154 * @}
Anna Bridge 186:707f6e361f3e 155 */
Anna Bridge 186:707f6e361f3e 156
Anna Bridge 186:707f6e361f3e 157 /**
Anna Bridge 186:707f6e361f3e 158 * @}
Anna Bridge 186:707f6e361f3e 159 */
Anna Bridge 186:707f6e361f3e 160 /* Exported types ------------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 161
<> 144:ef7eb2e8f9f7 162 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /**
Anna Bridge 186:707f6e361f3e 167 * @brief FLASH Erase structure definition
Anna Bridge 186:707f6e361f3e 168 */
Anna Bridge 186:707f6e361f3e 169 typedef struct
Anna Bridge 186:707f6e361f3e 170 {
Anna Bridge 186:707f6e361f3e 171 uint32_t TypeErase; /*!< TypeErase: Page Erase only.
Anna Bridge 186:707f6e361f3e 172 This parameter can be a value of @ref FLASHEx_Type_Erase */
Anna Bridge 186:707f6e361f3e 173
Anna Bridge 186:707f6e361f3e 174 uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
Anna Bridge 186:707f6e361f3e 175 This parameter must be a value belonging to FLASH Programm address (depending on the devices) */
Anna Bridge 186:707f6e361f3e 176
Anna Bridge 186:707f6e361f3e 177 uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
Anna Bridge 186:707f6e361f3e 178 This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
Anna Bridge 186:707f6e361f3e 179
Anna Bridge 186:707f6e361f3e 180 } FLASH_EraseInitTypeDef;
Anna Bridge 186:707f6e361f3e 181
Anna Bridge 186:707f6e361f3e 182 /**
<> 144:ef7eb2e8f9f7 183 * @brief FLASH Option Bytes PROGRAM structure definition
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 typedef struct
<> 144:ef7eb2e8f9f7 186 {
Anna Bridge 186:707f6e361f3e 187 uint32_t OptionType; /*!< OptionType: Option byte to be configured.
Anna Bridge 186:707f6e361f3e 188 This parameter can be a value of @ref FLASHEx_Option_Type */
<> 144:ef7eb2e8f9f7 189
Anna Bridge 186:707f6e361f3e 190 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
Anna Bridge 186:707f6e361f3e 191 This parameter can be a value of @ref FLASHEx_WRP_State */
<> 144:ef7eb2e8f9f7 192
Anna Bridge 186:707f6e361f3e 193 uint32_t WRPSector; /*!< WRPSector: This bitfield specifies the sector (s) which are write protected.
Anna Bridge 186:707f6e361f3e 194 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
Anna Bridge 186:707f6e361f3e 197 uint32_t WRPSector2; /*!< WRPSector2 : This bitfield specifies the sector(s) upper Sector31 which are write protected.
Anna Bridge 186:707f6e361f3e 198 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */
<> 144:ef7eb2e8f9f7 199 #endif
<> 144:ef7eb2e8f9f7 200
Anna Bridge 186:707f6e361f3e 201 uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.
Anna Bridge 186:707f6e361f3e 202 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
<> 144:ef7eb2e8f9f7 203
Anna Bridge 186:707f6e361f3e 204 uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.
Anna Bridge 186:707f6e361f3e 205 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
Anna Bridge 186:707f6e361f3e 206
Anna Bridge 186:707f6e361f3e 207 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
Anna Bridge 186:707f6e361f3e 208 This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog,
Anna Bridge 186:707f6e361f3e 209 @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
Anna Bridge 186:707f6e361f3e 210
Anna Bridge 186:707f6e361f3e 211 uint8_t BOOTBit1Config; /*!< BOOT1Config: Together with input pad Boot0, this bit selects the boot source, flash, ram or system memory
Anna Bridge 186:707f6e361f3e 212 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOTBit1 */
<> 144:ef7eb2e8f9f7 213 } FLASH_OBProgramInitTypeDef;
<> 144:ef7eb2e8f9f7 214
Anna Bridge 186:707f6e361f3e 215 #if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2)
<> 144:ef7eb2e8f9f7 216 /**
<> 144:ef7eb2e8f9f7 217 * @brief FLASH Advanced Option Bytes Program structure definition
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 typedef struct
<> 144:ef7eb2e8f9f7 220 {
Anna Bridge 186:707f6e361f3e 221 uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
Anna Bridge 186:707f6e361f3e 222 This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
Anna Bridge 186:707f6e361f3e 223
Anna Bridge 186:707f6e361f3e 224 #if defined(FLASH_OPTR_WPRMOD)
Anna Bridge 186:707f6e361f3e 225 uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
Anna Bridge 186:707f6e361f3e 226 This parameter can be a value of @ref FLASHEx_PCROP_State */
Anna Bridge 186:707f6e361f3e 227
<> 144:ef7eb2e8f9f7 228 uint32_t PCROPSector; /*!< PCROPSector : This bitfield specifies the sector(s) which are read/write protected.
<> 144:ef7eb2e8f9f7 229 This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 232 uint32_t PCROPSector2; /*!< PCROPSector : This bitfield specifies the sector(s) upper Sector31 which are read/write protected.
<> 144:ef7eb2e8f9f7 233 This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
Anna Bridge 186:707f6e361f3e 234 #endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
Anna Bridge 186:707f6e361f3e 235 #endif /* FLASH_OPTR_WPRMOD */
Anna Bridge 186:707f6e361f3e 236
Anna Bridge 186:707f6e361f3e 237 #if defined(FLASH_OPTR_BFB2)
Anna Bridge 186:707f6e361f3e 238 uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
Anna Bridge 186:707f6e361f3e 239 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
Anna Bridge 186:707f6e361f3e 240 #endif /* FLASH_OPTR_BFB2*/
<> 144:ef7eb2e8f9f7 241 } FLASH_AdvOBProgramInitTypeDef;
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @}
Anna Bridge 186:707f6e361f3e 245 */
Anna Bridge 186:707f6e361f3e 246 #endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */
Anna Bridge 186:707f6e361f3e 247
Anna Bridge 186:707f6e361f3e 248 /* Exported constants --------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 249
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
Anna Bridge 186:707f6e361f3e 255 /** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
<> 144:ef7eb2e8f9f7 256 * @{
Anna Bridge 186:707f6e361f3e 257 */
Anna Bridge 186:707f6e361f3e 258 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!<Page erase only*/
Anna Bridge 186:707f6e361f3e 259
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @}
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263
Anna Bridge 186:707f6e361f3e 264 /** @defgroup FLASHEx_Option_Type FLASHEx Option Type
<> 144:ef7eb2e8f9f7 265 * @{
<> 144:ef7eb2e8f9f7 266 */
Anna Bridge 186:707f6e361f3e 267 #define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!<WRP option byte configuration*/
Anna Bridge 186:707f6e361f3e 268 #define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!<RDP option byte configuration*/
Anna Bridge 186:707f6e361f3e 269 #define OPTIONBYTE_USER ((uint32_t)0x04U) /*!<USER option byte configuration*/
Anna Bridge 186:707f6e361f3e 270 #define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!<BOR option byte configuration*/
Anna Bridge 186:707f6e361f3e 271 #define OPTIONBYTE_BOOT_BIT1 ((uint32_t)0x10U) /*!< BOOT PIN1 option byte configuration*/
Anna Bridge 186:707f6e361f3e 272
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @}
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
Anna Bridge 186:707f6e361f3e 277 /** @defgroup FLASHEx_WRP_State FLASHEx WRP State
<> 144:ef7eb2e8f9f7 278 * @{
<> 144:ef7eb2e8f9f7 279 */
Anna Bridge 186:707f6e361f3e 280 #define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!<Disable the write protection of the desired sectors*/
Anna Bridge 186:707f6e361f3e 281 #define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!<Enable the write protection of the desired sectors*/
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @}
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 #if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx)
<> 144:ef7eb2e8f9f7 288 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
<> 144:ef7eb2e8f9f7 289 * @{
<> 144:ef7eb2e8f9f7 290 */
<> 151:5eaa88a5bcc7 291 #define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */
<> 151:5eaa88a5bcc7 292 #define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */
<> 151:5eaa88a5bcc7 293 #define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */
<> 151:5eaa88a5bcc7 294 #define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */
<> 151:5eaa88a5bcc7 295 #define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */
<> 151:5eaa88a5bcc7 296 #define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */
<> 151:5eaa88a5bcc7 297 #define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */
<> 151:5eaa88a5bcc7 298 #define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */
<> 151:5eaa88a5bcc7 299 #define OB_WRP_AllPages ((uint32_t)0x000000FFU) /*!< Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 #elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx)
<> 144:ef7eb2e8f9f7 304 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
<> 144:ef7eb2e8f9f7 305 * @{
<> 144:ef7eb2e8f9f7 306 */
<> 151:5eaa88a5bcc7 307 #define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */
<> 151:5eaa88a5bcc7 308 #define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */
<> 151:5eaa88a5bcc7 309 #define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */
<> 151:5eaa88a5bcc7 310 #define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */
<> 151:5eaa88a5bcc7 311 #define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */
<> 151:5eaa88a5bcc7 312 #define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */
<> 151:5eaa88a5bcc7 313 #define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */
<> 151:5eaa88a5bcc7 314 #define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */
<> 151:5eaa88a5bcc7 315 #define OB_WRP_Pages256to287 ((uint32_t)0x00000100U) /* Write protection of Sector8 */
<> 151:5eaa88a5bcc7 316 #define OB_WRP_Pages288to319 ((uint32_t)0x00000200U) /* Write protection of Sector9 */
<> 151:5eaa88a5bcc7 317 #define OB_WRP_Pages320to351 ((uint32_t)0x00000400U) /* Write protection of Sector10 */
<> 151:5eaa88a5bcc7 318 #define OB_WRP_Pages352to383 ((uint32_t)0x00000800U) /* Write protection of Sector11 */
<> 151:5eaa88a5bcc7 319 #define OB_WRP_Pages384to415 ((uint32_t)0x00001000U) /* Write protection of Sector12 */
<> 151:5eaa88a5bcc7 320 #define OB_WRP_Pages416to447 ((uint32_t)0x00002000U) /* Write protection of Sector13 */
<> 151:5eaa88a5bcc7 321 #define OB_WRP_Pages448to479 ((uint32_t)0x00004000U) /* Write protection of Sector14 */
<> 151:5eaa88a5bcc7 322 #define OB_WRP_Pages480to511 ((uint32_t)0x00008000U) /* Write protection of Sector15 */
<> 151:5eaa88a5bcc7 323 #define OB_WRP_AllPages ((uint32_t)0x0000FFFFU) /*!< Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 #elif defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 329 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write ProtectionP
<> 144:ef7eb2e8f9f7 330 * @{
<> 144:ef7eb2e8f9f7 331 */
<> 151:5eaa88a5bcc7 332 #define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */
<> 151:5eaa88a5bcc7 333 #define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */
<> 151:5eaa88a5bcc7 334 #define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */
<> 151:5eaa88a5bcc7 335 #define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */
<> 151:5eaa88a5bcc7 336 #define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */
<> 151:5eaa88a5bcc7 337 #define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */
<> 151:5eaa88a5bcc7 338 #define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */
<> 151:5eaa88a5bcc7 339 #define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */
<> 151:5eaa88a5bcc7 340 #define OB_WRP_Pages256to287 ((uint32_t)0x00000100U) /* Write protection of Sector8 */
<> 151:5eaa88a5bcc7 341 #define OB_WRP_Pages288to319 ((uint32_t)0x00000200U) /* Write protection of Sector9 */
<> 151:5eaa88a5bcc7 342 #define OB_WRP_Pages320to351 ((uint32_t)0x00000400U) /* Write protection of Sector10 */
<> 151:5eaa88a5bcc7 343 #define OB_WRP_Pages352to383 ((uint32_t)0x00000800U) /* Write protection of Sector11 */
<> 151:5eaa88a5bcc7 344 #define OB_WRP_Pages384to415 ((uint32_t)0x00001000U) /* Write protection of Sector12 */
<> 151:5eaa88a5bcc7 345 #define OB_WRP_Pages416to447 ((uint32_t)0x00002000U) /* Write protection of Sector13 */
<> 151:5eaa88a5bcc7 346 #define OB_WRP_Pages448to479 ((uint32_t)0x00004000U) /* Write protection of Sector14 */
<> 151:5eaa88a5bcc7 347 #define OB_WRP_Pages480to511 ((uint32_t)0x00008000U) /* Write protection of Sector15 */
<> 151:5eaa88a5bcc7 348 #define OB_WRP_Pages512to543 ((uint32_t)0x00010000U) /* Write protection of Sector16 */
<> 151:5eaa88a5bcc7 349 #define OB_WRP_Pages544to575 ((uint32_t)0x00020000U) /* Write protection of Sector17 */
<> 151:5eaa88a5bcc7 350 #define OB_WRP_Pages576to607 ((uint32_t)0x00040000U) /* Write protection of Sector18 */
<> 151:5eaa88a5bcc7 351 #define OB_WRP_Pages608to639 ((uint32_t)0x00080000U) /* Write protection of Sector19 */
<> 151:5eaa88a5bcc7 352 #define OB_WRP_Pages640to671 ((uint32_t)0x00100000U) /* Write protection of Sector20 */
<> 151:5eaa88a5bcc7 353 #define OB_WRP_Pages672to703 ((uint32_t)0x00200000U) /* Write protection of Sector21 */
<> 151:5eaa88a5bcc7 354 #define OB_WRP_Pages704to735 ((uint32_t)0x00400000U) /* Write protection of Sector22 */
<> 151:5eaa88a5bcc7 355 #define OB_WRP_Pages736to767 ((uint32_t)0x00800000U) /* Write protection of Sector23 */
<> 151:5eaa88a5bcc7 356 #define OB_WRP_Pages768to799 ((uint32_t)0x01000000U) /* Write protection of Sector24 */
<> 151:5eaa88a5bcc7 357 #define OB_WRP_Pages800to831 ((uint32_t)0x02000000U) /* Write protection of Sector25 */
<> 151:5eaa88a5bcc7 358 #define OB_WRP_Pages832to863 ((uint32_t)0x04000000U) /* Write protection of Sector26 */
<> 151:5eaa88a5bcc7 359 #define OB_WRP_Pages864to895 ((uint32_t)0x08000000U) /* Write protection of Sector27 */
<> 151:5eaa88a5bcc7 360 #define OB_WRP_Pages896to927 ((uint32_t)0x10000000U) /* Write protection of Sector28 */
<> 151:5eaa88a5bcc7 361 #define OB_WRP_Pages928to959 ((uint32_t)0x20000000U) /* Write protection of Sector29 */
<> 151:5eaa88a5bcc7 362 #define OB_WRP_Pages960to991 ((uint32_t)0x40000000U) /* Write protection of Sector30 */
<> 151:5eaa88a5bcc7 363 #define OB_WRP_Pages992to1023 ((uint32_t)0x80000000U) /* Write protection of Sector31 */
<> 151:5eaa88a5bcc7 364 #define OB_WRP_AllPages ((uint32_t)0xFFFFFFFFU) /*!<Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 365 /**
<> 144:ef7eb2e8f9f7 366 * @}
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASH Option Bytes Write Protection
<> 144:ef7eb2e8f9f7 370 * @{
<> 144:ef7eb2e8f9f7 371 */
<> 151:5eaa88a5bcc7 372 #define OB_WRP2_Pages1024to1055 ((uint32_t)0x00000001U) /* Write protection of Sector32 */
<> 151:5eaa88a5bcc7 373 #define OB_WRP2_Pages1056to1087 ((uint32_t)0x00000002U) /* Write protection of Sector33 */
<> 151:5eaa88a5bcc7 374 #define OB_WRP2_Pages1088to1119 ((uint32_t)0x00000004U) /* Write protection of Sector34 */
<> 151:5eaa88a5bcc7 375 #define OB_WRP2_Pages1120to1151 ((uint32_t)0x00000008U) /* Write protection of Sector35 */
<> 151:5eaa88a5bcc7 376 #define OB_WRP2_Pages1152to1183 ((uint32_t)0x00000010U) /* Write protection of Sector36 */
<> 151:5eaa88a5bcc7 377 #define OB_WRP2_Pages1184to1215 ((uint32_t)0x00000020U) /* Write protection of Sector37 */
<> 151:5eaa88a5bcc7 378 #define OB_WRP2_Pages1216to1247 ((uint32_t)0x00000040U) /* Write protection of Sector38 */
<> 151:5eaa88a5bcc7 379 #define OB_WRP2_Pages1248to1279 ((uint32_t)0x00000080U) /* Write protection of Sector39 */
<> 151:5eaa88a5bcc7 380 #define OB_WRP2_Pages1280to1311 ((uint32_t)0x00000100U) /* Write protection of Sector40 */
<> 151:5eaa88a5bcc7 381 #define OB_WRP2_Pages1312to1343 ((uint32_t)0x00000200U) /* Write protection of Sector41 */
<> 151:5eaa88a5bcc7 382 #define OB_WRP2_Pages1344to1375 ((uint32_t)0x00000400U) /* Write protection of Sector42 */
<> 151:5eaa88a5bcc7 383 #define OB_WRP2_Pages1376to1407 ((uint32_t)0x00000800U) /* Write protection of Sector43 */
<> 151:5eaa88a5bcc7 384 #define OB_WRP2_Pages1408to1439 ((uint32_t)0x00001000U) /* Write protection of Sector44 */
<> 151:5eaa88a5bcc7 385 #define OB_WRP2_Pages1440to1471 ((uint32_t)0x00002000U) /* Write protection of Sector45 */
<> 151:5eaa88a5bcc7 386 #define OB_WRP2_Pages1472to1503 ((uint32_t)0x00004000U) /* Write protection of Sector46 */
<> 151:5eaa88a5bcc7 387 #define OB_WRP2_Pages1504to1535 ((uint32_t)0x00008000U) /* Write protection of Sector47 */
<> 151:5eaa88a5bcc7 388 #define OB_WRP2_AllPages ((uint32_t)0x0000FFFFU) /*!< Write protection of all Sectors WRP2 */
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @}
<> 144:ef7eb2e8f9f7 391 */
Anna Bridge 186:707f6e361f3e 392 #endif /* STM32L071xx || STM32L072xx || (STM32L073xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */
<> 144:ef7eb2e8f9f7 393
Anna Bridge 186:707f6e361f3e 394 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
<> 144:ef7eb2e8f9f7 395 * @{
<> 144:ef7eb2e8f9f7 396 */
<> 151:5eaa88a5bcc7 397 #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
<> 151:5eaa88a5bcc7 398 #define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
<> 151:5eaa88a5bcc7 399 #define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2
<> 144:ef7eb2e8f9f7 400 it is no more possible to go back to level 1 or 0 */
Anna Bridge 186:707f6e361f3e 401
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @}
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405
Anna Bridge 186:707f6e361f3e 406 /** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
<> 144:ef7eb2e8f9f7 407 * @{
<> 144:ef7eb2e8f9f7 408 */
Anna Bridge 186:707f6e361f3e 409
Anna Bridge 186:707f6e361f3e 410 #define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD
<> 144:ef7eb2e8f9f7 411 power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
Anna Bridge 186:707f6e361f3e 412 #define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
Anna Bridge 186:707f6e361f3e 413 #define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
Anna Bridge 186:707f6e361f3e 414 #define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
Anna Bridge 186:707f6e361f3e 415 #define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
Anna Bridge 186:707f6e361f3e 416 #define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
Anna Bridge 186:707f6e361f3e 417
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @}
<> 144:ef7eb2e8f9f7 420 */
Anna Bridge 186:707f6e361f3e 421
Anna Bridge 186:707f6e361f3e 422 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
<> 144:ef7eb2e8f9f7 423 * @{
<> 144:ef7eb2e8f9f7 424 */
Anna Bridge 186:707f6e361f3e 425
Anna Bridge 186:707f6e361f3e 426 #define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */
Anna Bridge 186:707f6e361f3e 427 #define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */
Anna Bridge 186:707f6e361f3e 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
<> 144:ef7eb2e8f9f7 434 * @{
<> 144:ef7eb2e8f9f7 435 */
Anna Bridge 186:707f6e361f3e 436
Anna Bridge 186:707f6e361f3e 437 #define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */
Anna Bridge 186:707f6e361f3e 438 #define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 439 /**
<> 144:ef7eb2e8f9f7 440 * @}
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442
Anna Bridge 186:707f6e361f3e 443 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
<> 144:ef7eb2e8f9f7 444 * @{
<> 144:ef7eb2e8f9f7 445 */
Anna Bridge 186:707f6e361f3e 446
Anna Bridge 186:707f6e361f3e 447 #define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */
Anna Bridge 186:707f6e361f3e 448 #define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
Anna Bridge 186:707f6e361f3e 449
Anna Bridge 186:707f6e361f3e 450 /**
Anna Bridge 186:707f6e361f3e 451 * @}
Anna Bridge 186:707f6e361f3e 452 */
Anna Bridge 186:707f6e361f3e 453
Anna Bridge 186:707f6e361f3e 454 #if defined(FLASH_OPTR_WPRMOD)
Anna Bridge 186:707f6e361f3e 455
Anna Bridge 186:707f6e361f3e 456 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
Anna Bridge 186:707f6e361f3e 457 * @{
Anna Bridge 186:707f6e361f3e 458 */
Anna Bridge 186:707f6e361f3e 459
Anna Bridge 186:707f6e361f3e 460 #define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!<PCROP option byte configuration*/
Anna Bridge 186:707f6e361f3e 461
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @}
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465
Anna Bridge 186:707f6e361f3e 466 #endif /* FLASH_OPTR_WPRMOD */
<> 144:ef7eb2e8f9f7 467
Anna Bridge 186:707f6e361f3e 468 #if defined(FLASH_OPTR_BFB2)
Anna Bridge 186:707f6e361f3e 469
Anna Bridge 186:707f6e361f3e 470 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
<> 144:ef7eb2e8f9f7 471 * @{
<> 144:ef7eb2e8f9f7 472 */
Anna Bridge 186:707f6e361f3e 473
Anna Bridge 186:707f6e361f3e 474 #define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02U) /*!<BOOTConfig option byte configuration*/
Anna Bridge 186:707f6e361f3e 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @}
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479
Anna Bridge 186:707f6e361f3e 480 #endif /* FLASH_OPTR_BFB2 */
<> 144:ef7eb2e8f9f7 481
Anna Bridge 186:707f6e361f3e 482 #if defined(FLASH_OPTR_WPRMOD)
Anna Bridge 186:707f6e361f3e 483
Anna Bridge 186:707f6e361f3e 484 /** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State
<> 144:ef7eb2e8f9f7 485 * @{
Anna Bridge 186:707f6e361f3e 486 */
Anna Bridge 186:707f6e361f3e 487 #define OB_PCROP_STATE_DISABLE ((uint32_t)0x00U) /*!<Disable PCROP for selected sectors */
Anna Bridge 186:707f6e361f3e 488 #define OB_PCROP_STATE_ENABLE ((uint32_t)0x01U) /*!<Enable PCROP for selected sectors */
Anna Bridge 186:707f6e361f3e 489
<> 144:ef7eb2e8f9f7 490 /**
<> 144:ef7eb2e8f9f7 491 * @}
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493
Anna Bridge 186:707f6e361f3e 494 /** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
Anna Bridge 186:707f6e361f3e 495 * @{
Anna Bridge 186:707f6e361f3e 496 */
Anna Bridge 186:707f6e361f3e 497 #define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
Anna Bridge 186:707f6e361f3e 498 #define OB_PCROP_SELECTED ((uint16_t)FLASH_OPTR_WPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */
Anna Bridge 186:707f6e361f3e 499
Anna Bridge 186:707f6e361f3e 500 /**
Anna Bridge 186:707f6e361f3e 501 * @}
Anna Bridge 186:707f6e361f3e 502 */
Anna Bridge 186:707f6e361f3e 503 #endif /* FLASH_OPTR_WPRMOD */
Anna Bridge 186:707f6e361f3e 504
<> 144:ef7eb2e8f9f7 505 #if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx)
<> 144:ef7eb2e8f9f7 506 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
<> 144:ef7eb2e8f9f7 507 * @{
<> 144:ef7eb2e8f9f7 508 */
<> 151:5eaa88a5bcc7 509 #define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */
<> 151:5eaa88a5bcc7 510 #define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */
<> 151:5eaa88a5bcc7 511 #define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */
<> 151:5eaa88a5bcc7 512 #define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */
<> 151:5eaa88a5bcc7 513 #define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */
<> 151:5eaa88a5bcc7 514 #define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */
<> 151:5eaa88a5bcc7 515 #define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */
<> 151:5eaa88a5bcc7 516 #define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */
<> 151:5eaa88a5bcc7 517 #define OB_PCROP_AllPages ((uint32_t)0x000000FFU) /*!< PC Read/Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @}
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 #elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx)
<> 144:ef7eb2e8f9f7 522 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
<> 144:ef7eb2e8f9f7 523 * @{
<> 144:ef7eb2e8f9f7 524 */
<> 151:5eaa88a5bcc7 525 #define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */
<> 151:5eaa88a5bcc7 526 #define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */
<> 151:5eaa88a5bcc7 527 #define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */
<> 151:5eaa88a5bcc7 528 #define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */
<> 151:5eaa88a5bcc7 529 #define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */
<> 151:5eaa88a5bcc7 530 #define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */
<> 151:5eaa88a5bcc7 531 #define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */
<> 151:5eaa88a5bcc7 532 #define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */
<> 151:5eaa88a5bcc7 533 #define OB_PCROP_Pages256to287 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */
<> 151:5eaa88a5bcc7 534 #define OB_PCROP_Pages288to319 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */
<> 151:5eaa88a5bcc7 535 #define OB_PCROP_Pages320to351 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */
<> 151:5eaa88a5bcc7 536 #define OB_PCROP_Pages352to383 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */
<> 151:5eaa88a5bcc7 537 #define OB_PCROP_Pages384to415 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */
<> 151:5eaa88a5bcc7 538 #define OB_PCROP_Pages416to447 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */
<> 151:5eaa88a5bcc7 539 #define OB_PCROP_Pages448to479 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */
<> 151:5eaa88a5bcc7 540 #define OB_PCROP_Pages480to511 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */
<> 151:5eaa88a5bcc7 541 #define OB_PCROP_AllPages ((uint32_t)0x0000FFFFU) /*!< PC Read/Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 542 /**
<> 144:ef7eb2e8f9f7 543 * @}
<> 144:ef7eb2e8f9f7 544 */
<> 144:ef7eb2e8f9f7 545 #endif
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 548 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC Read/Write Protection
<> 144:ef7eb2e8f9f7 549 * @{
<> 144:ef7eb2e8f9f7 550 */
<> 151:5eaa88a5bcc7 551 #define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */
<> 151:5eaa88a5bcc7 552 #define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */
<> 151:5eaa88a5bcc7 553 #define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */
<> 151:5eaa88a5bcc7 554 #define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */
<> 151:5eaa88a5bcc7 555 #define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */
<> 151:5eaa88a5bcc7 556 #define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */
<> 151:5eaa88a5bcc7 557 #define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */
<> 151:5eaa88a5bcc7 558 #define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */
<> 151:5eaa88a5bcc7 559 #define OB_PCROP_Pages256to287 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */
<> 151:5eaa88a5bcc7 560 #define OB_PCROP_Pages288to319 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */
<> 151:5eaa88a5bcc7 561 #define OB_PCROP_Pages320to351 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */
<> 151:5eaa88a5bcc7 562 #define OB_PCROP_Pages352to383 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */
<> 151:5eaa88a5bcc7 563 #define OB_PCROP_Pages384to415 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */
<> 151:5eaa88a5bcc7 564 #define OB_PCROP_Pages416to447 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */
<> 151:5eaa88a5bcc7 565 #define OB_PCROP_Pages448to479 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */
<> 151:5eaa88a5bcc7 566 #define OB_PCROP_Pages480to511 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */
<> 151:5eaa88a5bcc7 567 #define OB_PCROP_Pages512to543 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector16 */
<> 151:5eaa88a5bcc7 568 #define OB_PCROP_Pages544to575 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector17 */
<> 151:5eaa88a5bcc7 569 #define OB_PCROP_Pages576to607 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector18 */
<> 151:5eaa88a5bcc7 570 #define OB_PCROP_Pages608to639 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector19 */
<> 151:5eaa88a5bcc7 571 #define OB_PCROP_Pages640to671 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector20 */
<> 151:5eaa88a5bcc7 572 #define OB_PCROP_Pages672to703 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector21 */
<> 151:5eaa88a5bcc7 573 #define OB_PCROP_Pages704to735 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector22 */
<> 151:5eaa88a5bcc7 574 #define OB_PCROP_Pages736to767 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector23 */
<> 151:5eaa88a5bcc7 575 #define OB_PCROP_Pages768to799 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector24 */
<> 151:5eaa88a5bcc7 576 #define OB_PCROP_Pages800to831 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector25 */
<> 151:5eaa88a5bcc7 577 #define OB_PCROP_Pages832to863 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector26 */
<> 151:5eaa88a5bcc7 578 #define OB_PCROP_Pages864to895 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector27 */
<> 151:5eaa88a5bcc7 579 #define OB_PCROP_Pages896to927 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector28 */
<> 151:5eaa88a5bcc7 580 #define OB_PCROP_Pages928to959 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector29 */
<> 151:5eaa88a5bcc7 581 #define OB_PCROP_Pages960to991 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector30 */
<> 151:5eaa88a5bcc7 582 #define OB_PCROP_Pages992to1023 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector31 */
<> 151:5eaa88a5bcc7 583 #define OB_PCROP_AllPages ((uint32_t)0xFFFFFFFFU) /*!<PC Read/Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 584 /**
<> 144:ef7eb2e8f9f7 585 * @}
<> 144:ef7eb2e8f9f7 586 */
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASH Option Bytes PC Read/Write Protection (Sector 2)
<> 144:ef7eb2e8f9f7 589 * @{
<> 144:ef7eb2e8f9f7 590 */
<> 151:5eaa88a5bcc7 591 #define OB_PCROP2_Pages1024to1055 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector32 */
<> 151:5eaa88a5bcc7 592 #define OB_PCROP2_Pages1056to1087 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector33 */
<> 151:5eaa88a5bcc7 593 #define OB_PCROP2_Pages1088to1119 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector34 */
<> 151:5eaa88a5bcc7 594 #define OB_PCROP2_Pages1120to1151 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector35 */
<> 151:5eaa88a5bcc7 595 #define OB_PCROP2_Pages1152to1183 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector36 */
<> 151:5eaa88a5bcc7 596 #define OB_PCROP2_Pages1184to1215 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector37 */
<> 151:5eaa88a5bcc7 597 #define OB_PCROP2_Pages1216to1247 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector38 */
<> 151:5eaa88a5bcc7 598 #define OB_PCROP2_Pages1248to1279 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector39 */
<> 151:5eaa88a5bcc7 599 #define OB_PCROP2_Pages1280to1311 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector40 */
<> 151:5eaa88a5bcc7 600 #define OB_PCROP2_Pages1312to1343 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector41 */
<> 151:5eaa88a5bcc7 601 #define OB_PCROP2_Pages1344to1375 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector42 */
<> 151:5eaa88a5bcc7 602 #define OB_PCROP2_Pages1376to1407 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector43 */
<> 151:5eaa88a5bcc7 603 #define OB_PCROP2_Pages1408to1439 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector44 */
<> 151:5eaa88a5bcc7 604 #define OB_PCROP2_Pages1440to1471 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector45 */
<> 151:5eaa88a5bcc7 605 #define OB_PCROP2_Pages1472to1503 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector46 */
<> 151:5eaa88a5bcc7 606 #define OB_PCROP2_Pages1504to1535 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector47 */
<> 151:5eaa88a5bcc7 607 #define OB_PCROP2_AllPages ((uint32_t)0x0000FFFFU) /*!< PC Read/Write protection of all Sectors PCROP2 */
<> 144:ef7eb2e8f9f7 608 /**
<> 144:ef7eb2e8f9f7 609 * @}
<> 144:ef7eb2e8f9f7 610 */
Anna Bridge 186:707f6e361f3e 611 #endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
Anna Bridge 186:707f6e361f3e 612
<> 144:ef7eb2e8f9f7 613 /** @defgroup FLASHEx_Option_Bytes_BOOTBit1 FLASH Option Bytes BOOT Bit1 Setup
<> 144:ef7eb2e8f9f7 614 * @{
<> 144:ef7eb2e8f9f7 615 */
<> 151:5eaa88a5bcc7 616 #define OB_BOOT_BIT1_RESET (uint8_t)(0x00U) /*!< BOOT Bit 1 Reset */
<> 151:5eaa88a5bcc7 617 #define OB_BOOT_BIT1_SET (uint8_t)(0x01U) /*!< BOOT Bit 1 Set */
<> 144:ef7eb2e8f9f7 618 /**
<> 144:ef7eb2e8f9f7 619 * @}
<> 144:ef7eb2e8f9f7 620 */
<> 144:ef7eb2e8f9f7 621
Anna Bridge 186:707f6e361f3e 622 /** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
<> 144:ef7eb2e8f9f7 623 * @{
<> 144:ef7eb2e8f9f7 624 */
Anna Bridge 186:707f6e361f3e 625 #define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00U) /*!<Program byte (8-bit) at a specified address.*/
Anna Bridge 186:707f6e361f3e 626 #define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
Anna Bridge 186:707f6e361f3e 627 #define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /**
<> 144:ef7eb2e8f9f7 630 * @}
<> 144:ef7eb2e8f9f7 631 */
<> 144:ef7eb2e8f9f7 632
Anna Bridge 186:707f6e361f3e 633 #if defined(FLASH_OPTR_BFB2)
Anna Bridge 186:707f6e361f3e 634
Anna Bridge 186:707f6e361f3e 635 /** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
<> 144:ef7eb2e8f9f7 636 * @{
<> 144:ef7eb2e8f9f7 637 */
Anna Bridge 186:707f6e361f3e 638
Anna Bridge 186:707f6e361f3e 639 #define OB_BOOT_BANK1 ((uint8_t)0x00U) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
Anna Bridge 186:707f6e361f3e 640 and this parameter is selected the device will boot from Bank 1 (Default)*/
Anna Bridge 186:707f6e361f3e 641 #define OB_BOOT_BANK2 ((uint8_t)(FLASH_OPTR_BFB2 >> 16)) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
Anna Bridge 186:707f6e361f3e 642 and this parameter is selected the device will boot from Bank 2 */
Anna Bridge 186:707f6e361f3e 643
<> 144:ef7eb2e8f9f7 644 /**
<> 144:ef7eb2e8f9f7 645 * @}
Anna Bridge 186:707f6e361f3e 646 */
Anna Bridge 186:707f6e361f3e 647 #endif /* FLASH_OPTR_BFB2 */
Anna Bridge 186:707f6e361f3e 648
<> 144:ef7eb2e8f9f7 649 /**
<> 144:ef7eb2e8f9f7 650 * @}
<> 144:ef7eb2e8f9f7 651 */
<> 144:ef7eb2e8f9f7 652
Anna Bridge 186:707f6e361f3e 653 /* Exported macro ------------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 654
Anna Bridge 186:707f6e361f3e 655 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
<> 144:ef7eb2e8f9f7 656 * @{
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /**
<> 144:ef7eb2e8f9f7 660 * @brief Set the FLASH Latency.
Anna Bridge 186:707f6e361f3e 661 * @param __LATENCY__ FLASH Latency
Anna Bridge 186:707f6e361f3e 662 * This parameter can be one of the following values:
Anna Bridge 186:707f6e361f3e 663 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
Anna Bridge 186:707f6e361f3e 664 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
<> 144:ef7eb2e8f9f7 665 * @retval none
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
<> 144:ef7eb2e8f9f7 668 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
Anna Bridge 186:707f6e361f3e 671 * @brief Get the FLASH Latency.
Anna Bridge 186:707f6e361f3e 672 * @retval FLASH Latency
Anna Bridge 186:707f6e361f3e 673 * This parameter can be one of the following values:
Anna Bridge 186:707f6e361f3e 674 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
Anna Bridge 186:707f6e361f3e 675 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
Anna Bridge 186:707f6e361f3e 676 */
Anna Bridge 186:707f6e361f3e 677 #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
Anna Bridge 186:707f6e361f3e 680 * @brief Enable the FLASH prefetch buffer.
<> 144:ef7eb2e8f9f7 681 * @retval none
<> 144:ef7eb2e8f9f7 682 */
Anna Bridge 186:707f6e361f3e 683 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
Anna Bridge 186:707f6e361f3e 684
Anna Bridge 186:707f6e361f3e 685 /**
Anna Bridge 186:707f6e361f3e 686 * @brief Disable the FLASH prefetch buffer.
Anna Bridge 186:707f6e361f3e 687 * @retval none
Anna Bridge 186:707f6e361f3e 688 */
Anna Bridge 186:707f6e361f3e 689 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
Anna Bridge 186:707f6e361f3e 690
Anna Bridge 186:707f6e361f3e 691 /**
Anna Bridge 186:707f6e361f3e 692 * @brief Enable the FLASH Buffer cache.
Anna Bridge 186:707f6e361f3e 693 * @retval none
Anna Bridge 186:707f6e361f3e 694 */
Anna Bridge 186:707f6e361f3e 695 #define __HAL_FLASH_BUFFER_CACHE_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /**
Anna Bridge 186:707f6e361f3e 698 * @brief Disable the FLASH Buffer cache.
<> 144:ef7eb2e8f9f7 699 * @retval none
<> 144:ef7eb2e8f9f7 700 */
Anna Bridge 186:707f6e361f3e 701 #define __HAL_FLASH_BUFFER_CACHE_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF)
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /**
Anna Bridge 186:707f6e361f3e 704 * @brief Enable the FLASH preread buffer.
<> 144:ef7eb2e8f9f7 705 * @retval none
<> 144:ef7eb2e8f9f7 706 */
Anna Bridge 186:707f6e361f3e 707 #define __HAL_FLASH_PREREAD_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)
Anna Bridge 186:707f6e361f3e 708
Anna Bridge 186:707f6e361f3e 709 /**
Anna Bridge 186:707f6e361f3e 710 * @brief Disable the FLASH preread buffer.
Anna Bridge 186:707f6e361f3e 711 * @retval none
Anna Bridge 186:707f6e361f3e 712 */
Anna Bridge 186:707f6e361f3e 713 #define __HAL_FLASH_PREREAD_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRE_READ)
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /**
Anna Bridge 186:707f6e361f3e 716 * @brief Enable the FLASH power down during Sleep mode
<> 144:ef7eb2e8f9f7 717 * @retval none
<> 144:ef7eb2e8f9f7 718 */
Anna Bridge 186:707f6e361f3e 719 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
Anna Bridge 186:707f6e361f3e 720
Anna Bridge 186:707f6e361f3e 721 /**
Anna Bridge 186:707f6e361f3e 722 * @brief Disable the FLASH power down during Sleep mode
Anna Bridge 186:707f6e361f3e 723 * @retval none
Anna Bridge 186:707f6e361f3e 724 */
Anna Bridge 186:707f6e361f3e 725 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /**
<> 144:ef7eb2e8f9f7 728 * @brief Enable the Flash Run power down mode.
<> 144:ef7eb2e8f9f7 729 * @note Writing this bit to 0 this bit, automatically the keys are
<> 144:ef7eb2e8f9f7 730 * loss and a new unlock sequence is necessary to re-write it to 1.
<> 144:ef7eb2e8f9f7 731 */
<> 144:ef7eb2e8f9f7 732 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
<> 144:ef7eb2e8f9f7 733 FLASH->PDKEYR = FLASH_PDKEY2; \
<> 144:ef7eb2e8f9f7 734 SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
<> 144:ef7eb2e8f9f7 735 } while (0)
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /**
<> 144:ef7eb2e8f9f7 738 * @brief Disable the Flash Run power down mode.
Anna Bridge 186:707f6e361f3e 739 * @note Writing this bit to 0 this bit, automatically the keys are
<> 144:ef7eb2e8f9f7 740 * loss and a new unlock sequence is necessary to re-write it to 1.
<> 144:ef7eb2e8f9f7 741 */
<> 144:ef7eb2e8f9f7 742 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
<> 144:ef7eb2e8f9f7 743 FLASH->PDKEYR = FLASH_PDKEY2; \
Anna Bridge 186:707f6e361f3e 744 CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
<> 144:ef7eb2e8f9f7 745 } while (0)
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /**
<> 144:ef7eb2e8f9f7 748 * @}
<> 144:ef7eb2e8f9f7 749 */
<> 144:ef7eb2e8f9f7 750
Anna Bridge 186:707f6e361f3e 751 /* Exported functions --------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 752
Anna Bridge 186:707f6e361f3e 753 /** @addtogroup FLASHEx_Exported_Functions
<> 144:ef7eb2e8f9f7 754 * @{
<> 144:ef7eb2e8f9f7 755 */
<> 144:ef7eb2e8f9f7 756
Anna Bridge 186:707f6e361f3e 757 /** @addtogroup FLASHEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 758 * @{
<> 144:ef7eb2e8f9f7 759 */
Anna Bridge 186:707f6e361f3e 760
<> 144:ef7eb2e8f9f7 761 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
<> 144:ef7eb2e8f9f7 762 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
Anna Bridge 186:707f6e361f3e 763
<> 144:ef7eb2e8f9f7 764 /**
<> 144:ef7eb2e8f9f7 765 * @}
<> 144:ef7eb2e8f9f7 766 */
<> 144:ef7eb2e8f9f7 767
Anna Bridge 186:707f6e361f3e 768 /** @addtogroup FLASHEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 769 * @{
<> 144:ef7eb2e8f9f7 770 */
Anna Bridge 186:707f6e361f3e 771
<> 144:ef7eb2e8f9f7 772 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 773 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
Anna Bridge 186:707f6e361f3e 774
Anna Bridge 186:707f6e361f3e 775 #if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2)
Anna Bridge 186:707f6e361f3e 776
<> 144:ef7eb2e8f9f7 777 HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
<> 144:ef7eb2e8f9f7 778 void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
Anna Bridge 186:707f6e361f3e 779
Anna Bridge 186:707f6e361f3e 780 #endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */
Anna Bridge 186:707f6e361f3e 781
Anna Bridge 186:707f6e361f3e 782 #if defined(FLASH_OPTR_WPRMOD)
Anna Bridge 186:707f6e361f3e 783
<> 144:ef7eb2e8f9f7 784 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
<> 144:ef7eb2e8f9f7 785 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
Anna Bridge 186:707f6e361f3e 786
Anna Bridge 186:707f6e361f3e 787 #endif /* FLASH_OPTR_WPRMOD */
Anna Bridge 186:707f6e361f3e 788
<> 144:ef7eb2e8f9f7 789 /**
<> 144:ef7eb2e8f9f7 790 * @}
<> 144:ef7eb2e8f9f7 791 */
<> 144:ef7eb2e8f9f7 792
Anna Bridge 186:707f6e361f3e 793 /** @addtogroup FLASHEx_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 794 * @{
<> 144:ef7eb2e8f9f7 795 */
Anna Bridge 186:707f6e361f3e 796
<> 144:ef7eb2e8f9f7 797 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);
<> 144:ef7eb2e8f9f7 798 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);
Anna Bridge 186:707f6e361f3e 799
<> 144:ef7eb2e8f9f7 800 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address);
<> 144:ef7eb2e8f9f7 801 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
<> 144:ef7eb2e8f9f7 802 void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);
<> 144:ef7eb2e8f9f7 803 void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /**
<> 144:ef7eb2e8f9f7 806 * @}
<> 144:ef7eb2e8f9f7 807 */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /**
<> 144:ef7eb2e8f9f7 810 * @}
<> 144:ef7eb2e8f9f7 811 */
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /**
<> 144:ef7eb2e8f9f7 814 * @}
<> 144:ef7eb2e8f9f7 815 */
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /**
<> 144:ef7eb2e8f9f7 818 * @}
<> 144:ef7eb2e8f9f7 819 */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 822 }
<> 144:ef7eb2e8f9f7 823 #endif
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 #endif /* __STM32L0xx_HAL_FLASH_EX_H */
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/