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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_dma.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of DMA HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32L0xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 38 #define __STM32L0xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @defgroup DMA_Exported_Types DMA Exported Types
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /**
<> 144:ef7eb2e8f9f7 61 * @brief DMA Configuration Structure definition
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63 typedef struct
<> 144:ef7eb2e8f9f7 64 {
<> 144:ef7eb2e8f9f7 65 uint32_t Request; /*!< Specifies the request selected for the specified channel.
<> 144:ef7eb2e8f9f7 66 This parameter can be a value of @ref DMA_request */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<> 144:ef7eb2e8f9f7 69 from memory to memory or from peripheral to memory.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref DMA_Data_transfer_direction */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
<> 144:ef7eb2e8f9f7 73 When Memory to Memory transfer is used, this is the Source Increment mode
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
<> 144:ef7eb2e8f9f7 77 When Memory to Memory transfer is used, this is the Destination Increment mode
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref DMA_Memory_incremented_mode */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
<> 144:ef7eb2e8f9f7 81 When Memory to Memory transfer is used, this is the Source Alignment format
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref DMA_Peripheral_data_size */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
<> 144:ef7eb2e8f9f7 85 When Memory to Memory transfer is used, this is the Destination Alignment format
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref DMA_Memory_data_size */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular).
<> 144:ef7eb2e8f9f7 89 This parameter can be a value of @ref DMA_mode
<> 144:ef7eb2e8f9f7 90 @note The circular buffer mode cannot be used if the memory-to-memory
<> 144:ef7eb2e8f9f7 91 data transfer is configured on the selected Channel */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
<> 144:ef7eb2e8f9f7 94 This parameter can be a value of @ref DMA_Priority_level */
<> 144:ef7eb2e8f9f7 95 } DMA_InitTypeDef;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /**
<> 144:ef7eb2e8f9f7 98 * @brief DMA Configuration enumeration values definition
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100 typedef enum
<> 144:ef7eb2e8f9f7 101 {
<> 151:5eaa88a5bcc7 102 DMA_MODE = 0U, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
<> 151:5eaa88a5bcc7 103 DMA_PRIORITY = 1U, /*!< Control related priority level Parameter in DMA_InitTypeDef */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 } DMA_ControlTypeDef;
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /**
<> 144:ef7eb2e8f9f7 108 * @brief HAL DMA State structures definition
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110 typedef enum
<> 144:ef7eb2e8f9f7 111 {
<> 151:5eaa88a5bcc7 112 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
<> 151:5eaa88a5bcc7 113 HAL_DMA_STATE_READY = 0x01U, /*!< DMA process success and ready for use */
<> 151:5eaa88a5bcc7 114 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
<> 151:5eaa88a5bcc7 115 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
<> 151:5eaa88a5bcc7 116 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
<> 151:5eaa88a5bcc7 117 HAL_DMA_STATE_READY_HALF = 0x05U, /*!< DMA Half process success */
<> 144:ef7eb2e8f9f7 118 }HAL_DMA_StateTypeDef;
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @brief HAL DMA Error Code structure definition
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 typedef enum
<> 144:ef7eb2e8f9f7 124 {
<> 151:5eaa88a5bcc7 125 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
<> 151:5eaa88a5bcc7 126 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 }HAL_DMA_LevelCompleteTypeDef;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @brief DMA handle Structure definition
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134 typedef struct __DMA_HandleTypeDef
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 DMA_Channel_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 DMA_InitTypeDef Init; /*!< DMA communication parameters */
<> 144:ef7eb2e8f9f7 139
<> 153:fa9ff456f731 140 HAL_LockTypeDef Lock; /*!< DMA locking object */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
<> 144:ef7eb2e8f9f7 143
<> 153:fa9ff456f731 144 void *Parent; /*!< Parent object state */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
<> 153:fa9ff456f731 151
<> 153:fa9ff456f731 152 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
<> 153:fa9ff456f731 153
<> 153:fa9ff456f731 154 __IO uint32_t ErrorCode; /*!< DMA Error code */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 } DMA_HandleTypeDef;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @}
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /** @defgroup DMA_Exported_Constants DMA Exported Constants
<> 144:ef7eb2e8f9f7 165 * @{
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /** @defgroup DMA_Error_Code DMA Error Codes
<> 144:ef7eb2e8f9f7 169 * @{
<> 144:ef7eb2e8f9f7 170 */
<> 151:5eaa88a5bcc7 171 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
<> 151:5eaa88a5bcc7 172 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
<> 153:fa9ff456f731 173 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< no ongoing transfer */
<> 151:5eaa88a5bcc7 174 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 #if defined (STM32L011xx) || defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 177 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
<> 144:ef7eb2e8f9f7 178 ((INSTANCE) == DMA1_Channel2) || \
<> 144:ef7eb2e8f9f7 179 ((INSTANCE) == DMA1_Channel3) || \
<> 144:ef7eb2e8f9f7 180 ((INSTANCE) == DMA1_Channel4) || \
<> 144:ef7eb2e8f9f7 181 ((INSTANCE) == DMA1_Channel5))
<> 144:ef7eb2e8f9f7 182 #else
<> 144:ef7eb2e8f9f7 183 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
<> 144:ef7eb2e8f9f7 184 ((INSTANCE) == DMA1_Channel2) || \
<> 144:ef7eb2e8f9f7 185 ((INSTANCE) == DMA1_Channel3) || \
<> 144:ef7eb2e8f9f7 186 ((INSTANCE) == DMA1_Channel4) || \
<> 144:ef7eb2e8f9f7 187 ((INSTANCE) == DMA1_Channel5) || \
<> 144:ef7eb2e8f9f7 188 ((INSTANCE) == DMA1_Channel6) || \
<> 144:ef7eb2e8f9f7 189 ((INSTANCE) == DMA1_Channel7))
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 #endif
<> 144:ef7eb2e8f9f7 192 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1))
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /**
<> 144:ef7eb2e8f9f7 195 * @}
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /** @defgroup DMA_request DMA request defintiions
<> 144:ef7eb2e8f9f7 199 * @{
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 203
<> 151:5eaa88a5bcc7 204 #define DMA_REQUEST_0 ((uint32_t)0x00000000U)
<> 151:5eaa88a5bcc7 205 #define DMA_REQUEST_1 ((uint32_t)0x00000001U)
<> 151:5eaa88a5bcc7 206 #define DMA_REQUEST_2 ((uint32_t)0x00000002U)
<> 151:5eaa88a5bcc7 207 #define DMA_REQUEST_3 ((uint32_t)0x00000003U)
<> 151:5eaa88a5bcc7 208 #define DMA_REQUEST_4 ((uint32_t)0x00000004U)
<> 151:5eaa88a5bcc7 209 #define DMA_REQUEST_5 ((uint32_t)0x00000005U)
<> 151:5eaa88a5bcc7 210 #define DMA_REQUEST_6 ((uint32_t)0x00000006U)
<> 151:5eaa88a5bcc7 211 #define DMA_REQUEST_7 ((uint32_t)0x00000007U)
<> 151:5eaa88a5bcc7 212 #define DMA_REQUEST_8 ((uint32_t)0x00000008U)
<> 151:5eaa88a5bcc7 213 #define DMA_REQUEST_9 ((uint32_t)0x00000009U)
<> 151:5eaa88a5bcc7 214 #define DMA_REQUEST_10 ((uint32_t)0x0000000AU)
<> 151:5eaa88a5bcc7 215 #define DMA_REQUEST_11 ((uint32_t)0x0000000BU)
<> 151:5eaa88a5bcc7 216 #define DMA_REQUEST_12 ((uint32_t)0x0000000CU)
<> 151:5eaa88a5bcc7 217 #define DMA_REQUEST_13 ((uint32_t)0x0000000DU)
<> 151:5eaa88a5bcc7 218 #define DMA_REQUEST_14 ((uint32_t)0x0000000EU)
<> 151:5eaa88a5bcc7 219 #define DMA_REQUEST_15 ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
<> 144:ef7eb2e8f9f7 222 ((REQUEST) == DMA_REQUEST_1) || \
<> 144:ef7eb2e8f9f7 223 ((REQUEST) == DMA_REQUEST_2) || \
<> 144:ef7eb2e8f9f7 224 ((REQUEST) == DMA_REQUEST_3) || \
<> 144:ef7eb2e8f9f7 225 ((REQUEST) == DMA_REQUEST_4) || \
<> 144:ef7eb2e8f9f7 226 ((REQUEST) == DMA_REQUEST_5) || \
<> 144:ef7eb2e8f9f7 227 ((REQUEST) == DMA_REQUEST_6) || \
<> 144:ef7eb2e8f9f7 228 ((REQUEST) == DMA_REQUEST_7) || \
<> 144:ef7eb2e8f9f7 229 ((REQUEST) == DMA_REQUEST_8) || \
<> 144:ef7eb2e8f9f7 230 ((REQUEST) == DMA_REQUEST_9) || \
<> 144:ef7eb2e8f9f7 231 ((REQUEST) == DMA_REQUEST_10) || \
<> 144:ef7eb2e8f9f7 232 ((REQUEST) == DMA_REQUEST_11) || \
<> 144:ef7eb2e8f9f7 233 ((REQUEST) == DMA_REQUEST_12) || \
<> 144:ef7eb2e8f9f7 234 ((REQUEST) == DMA_REQUEST_13) || \
<> 144:ef7eb2e8f9f7 235 ((REQUEST) == DMA_REQUEST_14) || \
<> 144:ef7eb2e8f9f7 236 ((REQUEST) == DMA_REQUEST_15))
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 #else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
<> 144:ef7eb2e8f9f7 239
<> 151:5eaa88a5bcc7 240 #define DMA_REQUEST_0 ((uint32_t)0x00000000U)
<> 151:5eaa88a5bcc7 241 #define DMA_REQUEST_1 ((uint32_t)0x00000001U)
<> 151:5eaa88a5bcc7 242 #define DMA_REQUEST_2 ((uint32_t)0x00000002U)
<> 151:5eaa88a5bcc7 243 #define DMA_REQUEST_3 ((uint32_t)0x00000003U)
<> 151:5eaa88a5bcc7 244 #define DMA_REQUEST_4 ((uint32_t)0x00000004U)
<> 151:5eaa88a5bcc7 245 #define DMA_REQUEST_5 ((uint32_t)0x00000005U)
<> 151:5eaa88a5bcc7 246 #define DMA_REQUEST_6 ((uint32_t)0x00000006U)
<> 151:5eaa88a5bcc7 247 #define DMA_REQUEST_7 ((uint32_t)0x00000007U)
<> 151:5eaa88a5bcc7 248 #define DMA_REQUEST_8 ((uint32_t)0x00000008U)
<> 151:5eaa88a5bcc7 249 #define DMA_REQUEST_9 ((uint32_t)0x00000009U)
<> 151:5eaa88a5bcc7 250 #define DMA_REQUEST_11 ((uint32_t)0x0000000BU)
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
<> 144:ef7eb2e8f9f7 253 ((REQUEST) == DMA_REQUEST_1) || \
<> 144:ef7eb2e8f9f7 254 ((REQUEST) == DMA_REQUEST_2) || \
<> 144:ef7eb2e8f9f7 255 ((REQUEST) == DMA_REQUEST_3) || \
<> 144:ef7eb2e8f9f7 256 ((REQUEST) == DMA_REQUEST_4) || \
<> 144:ef7eb2e8f9f7 257 ((REQUEST) == DMA_REQUEST_5) || \
<> 144:ef7eb2e8f9f7 258 ((REQUEST) == DMA_REQUEST_6) || \
<> 144:ef7eb2e8f9f7 259 ((REQUEST) == DMA_REQUEST_7) || \
<> 144:ef7eb2e8f9f7 260 ((REQUEST) == DMA_REQUEST_8) || \
<> 144:ef7eb2e8f9f7 261 ((REQUEST) == DMA_REQUEST_9) || \
<> 144:ef7eb2e8f9f7 262 ((REQUEST) == DMA_REQUEST_11))
<> 144:ef7eb2e8f9f7 263 #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /**
<> 144:ef7eb2e8f9f7 266 * @}
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
<> 144:ef7eb2e8f9f7 270 * @{
<> 144:ef7eb2e8f9f7 271 */
<> 151:5eaa88a5bcc7 272 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
<> 144:ef7eb2e8f9f7 273 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
<> 144:ef7eb2e8f9f7 274 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
<> 144:ef7eb2e8f9f7 277 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
<> 144:ef7eb2e8f9f7 278 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /** @defgroup DMA_Data_buffer_size DMA Data Buffer Size Check
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral Incremented Mode
<> 144:ef7eb2e8f9f7 292 * @{
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
<> 151:5eaa88a5bcc7 295 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 298 ((STATE) == DMA_PINC_DISABLE))
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @}
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /** @defgroup DMA_Memory_incremented_mode DMA Memory Incremented Mode
<> 144:ef7eb2e8f9f7 304 * @{
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
<> 151:5eaa88a5bcc7 307 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 310 ((STATE) == DMA_MINC_DISABLE))
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @}
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment
<> 144:ef7eb2e8f9f7 316 * @{
<> 144:ef7eb2e8f9f7 317 */
<> 151:5eaa88a5bcc7 318 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */
<> 144:ef7eb2e8f9f7 319 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
<> 144:ef7eb2e8f9f7 320 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 323 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 324 ((SIZE) == DMA_PDATAALIGN_WORD))
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @}
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
<> 151:5eaa88a5bcc7 333 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */
<> 144:ef7eb2e8f9f7 334 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
<> 144:ef7eb2e8f9f7 335 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 338 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 339 ((SIZE) == DMA_MDATAALIGN_WORD ))
<> 144:ef7eb2e8f9f7 340 /**
<> 144:ef7eb2e8f9f7 341 * @}
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /** @defgroup DMA_mode DMA Mode
<> 144:ef7eb2e8f9f7 345 * @{
<> 144:ef7eb2e8f9f7 346 */
<> 151:5eaa88a5bcc7 347 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */
<> 144:ef7eb2e8f9f7 348 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
<> 144:ef7eb2e8f9f7 351 ((MODE) == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 352 /**
<> 144:ef7eb2e8f9f7 353 * @}
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /** @defgroup DMA_Priority_level DMA Priority Level
<> 144:ef7eb2e8f9f7 357 * @{
<> 144:ef7eb2e8f9f7 358 */
<> 151:5eaa88a5bcc7 359 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */
<> 144:ef7eb2e8f9f7 360 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
<> 144:ef7eb2e8f9f7 361 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
<> 144:ef7eb2e8f9f7 362 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
<> 144:ef7eb2e8f9f7 365 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
<> 144:ef7eb2e8f9f7 366 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
<> 144:ef7eb2e8f9f7 367 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
<> 144:ef7eb2e8f9f7 368 /**
<> 144:ef7eb2e8f9f7 369 * @}
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /** @defgroup DMA_interrupt_enable_definitions DMA Interrupt Definitions
<> 144:ef7eb2e8f9f7 374 * @{
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
<> 144:ef7eb2e8f9f7 378 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
<> 144:ef7eb2e8f9f7 379 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @}
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /** @defgroup DMA_flag_definitions DMA Flag Definitions
<> 144:ef7eb2e8f9f7 386 * @{
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388
<> 151:5eaa88a5bcc7 389 #define DMA_FLAG_GL1 ((uint32_t)0x00000001U)
<> 151:5eaa88a5bcc7 390 #define DMA_FLAG_TC1 ((uint32_t)0x00000002U)
<> 151:5eaa88a5bcc7 391 #define DMA_FLAG_HT1 ((uint32_t)0x00000004U)
<> 151:5eaa88a5bcc7 392 #define DMA_FLAG_TE1 ((uint32_t)0x00000008U)
<> 151:5eaa88a5bcc7 393 #define DMA_FLAG_GL2 ((uint32_t)0x00000010U)
<> 151:5eaa88a5bcc7 394 #define DMA_FLAG_TC2 ((uint32_t)0x00000020U)
<> 151:5eaa88a5bcc7 395 #define DMA_FLAG_HT2 ((uint32_t)0x00000040U)
<> 151:5eaa88a5bcc7 396 #define DMA_FLAG_TE2 ((uint32_t)0x00000080U)
<> 151:5eaa88a5bcc7 397 #define DMA_FLAG_GL3 ((uint32_t)0x00000100U)
<> 151:5eaa88a5bcc7 398 #define DMA_FLAG_TC3 ((uint32_t)0x00000200U)
<> 151:5eaa88a5bcc7 399 #define DMA_FLAG_HT3 ((uint32_t)0x00000400U)
<> 151:5eaa88a5bcc7 400 #define DMA_FLAG_TE3 ((uint32_t)0x00000800U)
<> 151:5eaa88a5bcc7 401 #define DMA_FLAG_GL4 ((uint32_t)0x00001000U)
<> 151:5eaa88a5bcc7 402 #define DMA_FLAG_TC4 ((uint32_t)0x00002000U)
<> 151:5eaa88a5bcc7 403 #define DMA_FLAG_HT4 ((uint32_t)0x00004000U)
<> 151:5eaa88a5bcc7 404 #define DMA_FLAG_TE4 ((uint32_t)0x00008000U)
<> 151:5eaa88a5bcc7 405 #define DMA_FLAG_GL5 ((uint32_t)0x00010000U)
<> 151:5eaa88a5bcc7 406 #define DMA_FLAG_TC5 ((uint32_t)0x00020000U)
<> 151:5eaa88a5bcc7 407 #define DMA_FLAG_HT5 ((uint32_t)0x00040000U)
<> 151:5eaa88a5bcc7 408 #define DMA_FLAG_TE5 ((uint32_t)0x00080000U)
<> 151:5eaa88a5bcc7 409 #define DMA_FLAG_GL6 ((uint32_t)0x00100000U)
<> 151:5eaa88a5bcc7 410 #define DMA_FLAG_TC6 ((uint32_t)0x00200000U)
<> 151:5eaa88a5bcc7 411 #define DMA_FLAG_HT6 ((uint32_t)0x00400000U)
<> 151:5eaa88a5bcc7 412 #define DMA_FLAG_TE6 ((uint32_t)0x00800000U)
<> 151:5eaa88a5bcc7 413 #define DMA_FLAG_GL7 ((uint32_t)0x01000000U)
<> 151:5eaa88a5bcc7 414 #define DMA_FLAG_TC7 ((uint32_t)0x02000000U)
<> 151:5eaa88a5bcc7 415 #define DMA_FLAG_HT7 ((uint32_t)0x04000000U)
<> 151:5eaa88a5bcc7 416 #define DMA_FLAG_TE7 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /**
<> 144:ef7eb2e8f9f7 420 * @}
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /**
<> 144:ef7eb2e8f9f7 424 * @}
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /** @defgroup DMA_Exported_Macros DMA Exported Macros
<> 144:ef7eb2e8f9f7 430 * @{
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /** @brief Reset DMA handle state
<> 144:ef7eb2e8f9f7 434 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 435 * @retval None
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /**
<> 144:ef7eb2e8f9f7 440 * @brief Enable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 441 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 442 * @retval None.
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /**
<> 144:ef7eb2e8f9f7 447 * @brief Disable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 448 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 449 * @retval None.
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @brief Returns the current DMA Channel transfer complete flag.
<> 144:ef7eb2e8f9f7 458 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 459 * @retval The specified transfer complete flag index.
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 #if defined (STM32L011xx) || defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 463 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<> 144:ef7eb2e8f9f7 464 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<> 144:ef7eb2e8f9f7 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<> 144:ef7eb2e8f9f7 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<> 144:ef7eb2e8f9f7 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<> 144:ef7eb2e8f9f7 468 DMA_FLAG_TC5)
<> 144:ef7eb2e8f9f7 469 #else
<> 144:ef7eb2e8f9f7 470 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<> 144:ef7eb2e8f9f7 471 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<> 144:ef7eb2e8f9f7 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<> 144:ef7eb2e8f9f7 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<> 144:ef7eb2e8f9f7 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<> 144:ef7eb2e8f9f7 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
<> 144:ef7eb2e8f9f7 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
<> 144:ef7eb2e8f9f7 477 DMA_FLAG_TC7)
<> 144:ef7eb2e8f9f7 478 #endif
<> 144:ef7eb2e8f9f7 479 /**
<> 144:ef7eb2e8f9f7 480 * @brief Returns the current DMA Channel half transfer complete flag.
<> 144:ef7eb2e8f9f7 481 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 482 * @retval The specified half transfer complete flag index.
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484 #if defined (STM32L011xx) || defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 485 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 486 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<> 144:ef7eb2e8f9f7 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<> 144:ef7eb2e8f9f7 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<> 144:ef7eb2e8f9f7 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<> 144:ef7eb2e8f9f7 490 DMA_FLAG_HT5)
<> 144:ef7eb2e8f9f7 491 #else
<> 144:ef7eb2e8f9f7 492 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 493 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<> 144:ef7eb2e8f9f7 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<> 144:ef7eb2e8f9f7 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<> 144:ef7eb2e8f9f7 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<> 144:ef7eb2e8f9f7 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
<> 144:ef7eb2e8f9f7 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
<> 144:ef7eb2e8f9f7 499 DMA_FLAG_HT7)
<> 144:ef7eb2e8f9f7 500 #endif
<> 144:ef7eb2e8f9f7 501 /**
<> 144:ef7eb2e8f9f7 502 * @brief Returns the current DMA Channel transfer error flag.
<> 144:ef7eb2e8f9f7 503 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 504 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 #if defined (STM32L011xx) || defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 507 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 508 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<> 144:ef7eb2e8f9f7 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<> 144:ef7eb2e8f9f7 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<> 144:ef7eb2e8f9f7 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<> 144:ef7eb2e8f9f7 512 DMA_FLAG_TE5)
<> 144:ef7eb2e8f9f7 513 #else
<> 144:ef7eb2e8f9f7 514 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 515 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<> 144:ef7eb2e8f9f7 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<> 144:ef7eb2e8f9f7 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<> 144:ef7eb2e8f9f7 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<> 144:ef7eb2e8f9f7 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
<> 144:ef7eb2e8f9f7 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
<> 144:ef7eb2e8f9f7 521 DMA_FLAG_TE7)
<> 144:ef7eb2e8f9f7 522 #endif
<> 144:ef7eb2e8f9f7 523 /**
<> 144:ef7eb2e8f9f7 524 * @brief Returns the current DMA Channel Global interrupt flag.
<> 144:ef7eb2e8f9f7 525 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 526 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528 #if defined (STM32L011xx) || defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 529 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 530 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
<> 144:ef7eb2e8f9f7 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
<> 144:ef7eb2e8f9f7 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
<> 144:ef7eb2e8f9f7 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
<> 144:ef7eb2e8f9f7 534 DMA_ISR_GIF5)
<> 144:ef7eb2e8f9f7 535 #else
<> 144:ef7eb2e8f9f7 536 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 537 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
<> 144:ef7eb2e8f9f7 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
<> 144:ef7eb2e8f9f7 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
<> 144:ef7eb2e8f9f7 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
<> 144:ef7eb2e8f9f7 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
<> 144:ef7eb2e8f9f7 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
<> 144:ef7eb2e8f9f7 543 DMA_ISR_GIF7)
<> 144:ef7eb2e8f9f7 544 #endif
<> 144:ef7eb2e8f9f7 545 /**
<> 144:ef7eb2e8f9f7 546 * @brief Get the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 547 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 548 * @param __FLAG__: Get the specified flag.
<> 144:ef7eb2e8f9f7 549 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 550 * @arg DMA_FLAG_TCIFx: Transfer complete flag
<> 144:ef7eb2e8f9f7 551 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 552 * @arg DMA_FLAG_TEIFx: Transfer error flag
<> 144:ef7eb2e8f9f7 553 * @arg DMA_ISR_GIFx: Global interrupt flag
<> 144:ef7eb2e8f9f7 554 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 555 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 556 */
<> 144:ef7eb2e8f9f7 557 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /**
<> 144:ef7eb2e8f9f7 560 * @brief Clears the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 561 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 562 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 563 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 564 * @arg DMA_FLAG_TCIFx: Transfer complete flag
<> 144:ef7eb2e8f9f7 565 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 566 * @arg DMA_FLAG_TEIFx: Transfer error flag
<> 144:ef7eb2e8f9f7 567 * @arg DMA_ISR_GIFx: Global interrupt flag
<> 144:ef7eb2e8f9f7 568 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 569 * @retval None
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @brief Enables the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 575 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 576 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 577 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 578 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 579 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 580 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 581 * @retval None
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /**
<> 144:ef7eb2e8f9f7 586 * @brief Disables the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 587 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 588 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 589 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 590 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 591 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 592 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 593 * @retval None
<> 144:ef7eb2e8f9f7 594 */
<> 144:ef7eb2e8f9f7 595 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /**
<> 144:ef7eb2e8f9f7 598 * @brief Checks whether the specified DMA Channel interrupt is enabled or not.
<> 144:ef7eb2e8f9f7 599 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 600 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
<> 144:ef7eb2e8f9f7 601 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 602 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 603 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 604 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 605 * @retval The state of DMA_IT (SET or RESET).
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /**
<> 151:5eaa88a5bcc7 610 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
<> 151:5eaa88a5bcc7 611 * @param __HANDLE__: DMA handle
<> 151:5eaa88a5bcc7 612 *
<> 151:5eaa88a5bcc7 613 * @retval The number of remaining data units in the current DMA Channel transfer.
<> 151:5eaa88a5bcc7 614 */
<> 151:5eaa88a5bcc7 615 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
<> 151:5eaa88a5bcc7 616
<> 151:5eaa88a5bcc7 617 /**
<> 144:ef7eb2e8f9f7 618 * @}
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 624 * @{
<> 144:ef7eb2e8f9f7 625 */
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 628 * @{
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 632 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 633 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /**
<> 144:ef7eb2e8f9f7 636 * @}
<> 144:ef7eb2e8f9f7 637 */
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
<> 144:ef7eb2e8f9f7 640 * @{
<> 144:ef7eb2e8f9f7 641 */
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 644 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 645 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 646 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
<> 153:fa9ff456f731 647 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 648 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 649 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 650 /**
<> 144:ef7eb2e8f9f7 651 * @}
<> 144:ef7eb2e8f9f7 652 */
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
<> 144:ef7eb2e8f9f7 655 * @{
<> 144:ef7eb2e8f9f7 656 */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 659 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 660 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /**
<> 144:ef7eb2e8f9f7 663 * @}
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /**
<> 144:ef7eb2e8f9f7 667 * @}
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669 /* Define the private group ***********************************/
<> 144:ef7eb2e8f9f7 670 /**************************************************************/
<> 144:ef7eb2e8f9f7 671 /** @defgroup DMA_Private DMA Private
<> 144:ef7eb2e8f9f7 672 * @{
<> 144:ef7eb2e8f9f7 673 */
<> 144:ef7eb2e8f9f7 674 /**
<> 144:ef7eb2e8f9f7 675 * @}
<> 144:ef7eb2e8f9f7 676 */
<> 144:ef7eb2e8f9f7 677 /**************************************************************/
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @}
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /**
<> 144:ef7eb2e8f9f7 684 * @}
<> 144:ef7eb2e8f9f7 685 */
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 688 }
<> 144:ef7eb2e8f9f7 689 #endif
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 #endif /* __STM32L0xx_HAL_DMA_H */
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 694