mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dma.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief DMA HAL module driver.
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 9 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 10 * + I/O operation functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 (#) Enable and configure the peripheral to be connected to the DMA Channel
<> 144:ef7eb2e8f9f7 20 (except for internal SRAM / FLASH memories: no initialization is
<> 144:ef7eb2e8f9f7 21 necessary).
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#) For a given Channel, program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 24 Channel request, Transfer Direction, Source and Destination data formats,
<> 144:ef7eb2e8f9f7 25 Circular, Normal or peripheral flow control mode, Channel Priority level,
<> 144:ef7eb2e8f9f7 26 Source and Destination Increment mode using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 29 =================================
<> 144:ef7eb2e8f9f7 30 [..]
<> 144:ef7eb2e8f9f7 31 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 144:ef7eb2e8f9f7 32 address and destination address and the Length of data to be transferred
<> 144:ef7eb2e8f9f7 33 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 144:ef7eb2e8f9f7 34 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 37 ===================================
<> 144:ef7eb2e8f9f7 38 [..]
<> 144:ef7eb2e8f9f7 39 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 40 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 41 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 144:ef7eb2e8f9f7 42 Source address and destination address and the Length of data to be transferred. In this
<> 144:ef7eb2e8f9f7 43 case the DMA interrupt is configured
<> 144:ef7eb2e8f9f7 44 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 45 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 46 add his own function by customization of function pointer XferCpltCallback and
<> 144:ef7eb2e8f9f7 47 XferErrorCallback (i.e a member of DMA handle structure).
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 50 detection.
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 @endverbatim
<> 144:ef7eb2e8f9f7 57 ******************************************************************************
<> 144:ef7eb2e8f9f7 58 * @attention
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 61 *
<> 144:ef7eb2e8f9f7 62 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 63 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 64 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 65 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 66 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 67 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 68 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 69 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 70 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 71 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 76 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 79 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 80 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 81 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 82 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 ******************************************************************************
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 88 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 91 * @{
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /** @addtogroup DMA DMA
<> 144:ef7eb2e8f9f7 96 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101 /** @addtogroup DMA_Private
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 151:5eaa88a5bcc7 105 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000U) /* 1s */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 109 /**
<> 144:ef7eb2e8f9f7 110 * @}
<> 144:ef7eb2e8f9f7 111 */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 114 * @{
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /** @addtogroup DMA_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 118 * @brief Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 119 *
<> 144:ef7eb2e8f9f7 120 @verbatim
<> 144:ef7eb2e8f9f7 121 ===============================================================================
<> 144:ef7eb2e8f9f7 122 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 123 ===============================================================================
<> 144:ef7eb2e8f9f7 124 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 125 (+) Initialize and configure the DMA
<> 144:ef7eb2e8f9f7 126 (+) De-Initialize the DMA
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 @endverbatim
<> 144:ef7eb2e8f9f7 129 * @{
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @brief Initializes the DMA according to the specified
<> 144:ef7eb2e8f9f7 134 * parameters in the DMA_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 135 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 136 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 137 * @retval HAL status
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 140 {
<> 151:5eaa88a5bcc7 141 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* Check the DMA peripheral state */
<> 144:ef7eb2e8f9f7 144 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* Check the parameters */
<> 144:ef7eb2e8f9f7 150 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 151 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
<> 144:ef7eb2e8f9f7 152 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 153 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 154 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 155 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 156 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 157 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 158 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 if(hdma->State == HAL_DMA_STATE_RESET)
<> 144:ef7eb2e8f9f7 161 {
<> 144:ef7eb2e8f9f7 162 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 163 hdma->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 167 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 170 tmp = hdma->Instance->CCR;
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
<> 144:ef7eb2e8f9f7 173 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
<> 144:ef7eb2e8f9f7 174 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
<> 144:ef7eb2e8f9f7 175 DMA_CCR_DIR));
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /* Prepare the DMA Channel configuration */
<> 144:ef7eb2e8f9f7 178 tmp |= hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 179 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 180 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 181 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Write to DMA Channel CR register */
<> 144:ef7eb2e8f9f7 184 hdma->Instance->CCR = tmp;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Write to DMA channel selection register */
<> 144:ef7eb2e8f9f7 187 if (hdma->Instance == DMA1_Channel1)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 /*Reset request selection for DMA1 Channel1*/
<> 144:ef7eb2e8f9f7 190 DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Configure request selection for DMA1 Channel1 */
<> 144:ef7eb2e8f9f7 193 DMA1_CSELR->CSELR |= hdma->Init.Request;
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195 else if (hdma->Instance == DMA1_Channel2)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 /*Reset request selection for DMA1 Channel2*/
<> 144:ef7eb2e8f9f7 198 DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Configure request selection for DMA1 Channel2 */
<> 151:5eaa88a5bcc7 201 DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4U);
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203 else if (hdma->Instance == DMA1_Channel3)
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 /*Reset request selection for DMA1 Channel3*/
<> 144:ef7eb2e8f9f7 206 DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Configure request selection for DMA1 Channel3 */
<> 151:5eaa88a5bcc7 209 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8U);
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211 else if (hdma->Instance == DMA1_Channel4)
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 /*Reset request selection for DMA1 Channel4*/
<> 144:ef7eb2e8f9f7 214 DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Configure request selection for DMA1 Channel4 */
<> 151:5eaa88a5bcc7 217 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12U);
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219 else if (hdma->Instance == DMA1_Channel5)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 /*Reset request selection for DMA1 Channel5*/
<> 144:ef7eb2e8f9f7 222 DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Configure request selection for DMA1 Channel5 */
<> 151:5eaa88a5bcc7 225 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16U);
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227 #if !defined (STM32L011xx) && !defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 228 else if (hdma->Instance == DMA1_Channel6)
<> 144:ef7eb2e8f9f7 229 {
<> 144:ef7eb2e8f9f7 230 /*Reset request selection for DMA1 Channel6*/
<> 144:ef7eb2e8f9f7 231 DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /* Configure request selection for DMA1 Channel6 */
<> 151:5eaa88a5bcc7 234 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20U);
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236 else if (hdma->Instance == DMA1_Channel7)
<> 144:ef7eb2e8f9f7 237 {
<> 144:ef7eb2e8f9f7 238 /*Reset request selection for DMA1 Channel7*/
<> 144:ef7eb2e8f9f7 239 DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* Configure request selection for DMA1 Channel7 */
<> 151:5eaa88a5bcc7 242 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24U);
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244 #endif
<> 144:ef7eb2e8f9f7 245 /* Initialize the DMA state*/
<> 144:ef7eb2e8f9f7 246 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 return HAL_OK;
<> 144:ef7eb2e8f9f7 249 }
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @brief DeInitializes the DMA peripheral
<> 144:ef7eb2e8f9f7 253 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 254 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 255 * @retval HAL status
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 /* Check the DMA peripheral state */
<> 144:ef7eb2e8f9f7 260 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Check the DMA peripheral state */
<> 144:ef7eb2e8f9f7 266 if(hdma->State == HAL_DMA_STATE_BUSY)
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Disable the selected DMA Channelx */
<> 144:ef7eb2e8f9f7 272 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Reset DMA Channel control register */
<> 151:5eaa88a5bcc7 275 hdma->Instance->CCR = 0U;
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Reset DMA Channel Number of Data to Transfer register */
<> 151:5eaa88a5bcc7 278 hdma->Instance->CNDTR = 0U;
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /* Reset DMA Channel peripheral address register */
<> 151:5eaa88a5bcc7 281 hdma->Instance->CPAR = 0U;
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Reset DMA Channel memory address register */
<> 151:5eaa88a5bcc7 284 hdma->Instance->CMAR = 0U;
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Clear all flags */
<> 144:ef7eb2e8f9f7 287 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 288 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 289 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 290 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Reset DMA channel selection register */
<> 144:ef7eb2e8f9f7 293 if (hdma->Instance == DMA1_Channel1)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 /*Reset DMA request*/
<> 144:ef7eb2e8f9f7 296 DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298 else if (hdma->Instance == DMA1_Channel2)
<> 144:ef7eb2e8f9f7 299 {
<> 144:ef7eb2e8f9f7 300 /*Reset DMA request*/
<> 144:ef7eb2e8f9f7 301 DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303 else if (hdma->Instance == DMA1_Channel3)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 /*Reset DMA request*/
<> 144:ef7eb2e8f9f7 306 DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
<> 144:ef7eb2e8f9f7 307 }
<> 144:ef7eb2e8f9f7 308 else if (hdma->Instance == DMA1_Channel4)
<> 144:ef7eb2e8f9f7 309 {
<> 144:ef7eb2e8f9f7 310 /*Reset DMA request*/
<> 144:ef7eb2e8f9f7 311 DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313 else if (hdma->Instance == DMA1_Channel5)
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 /*Reset DMA request*/
<> 144:ef7eb2e8f9f7 316 DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318 #if !defined (STM32L011xx) && !defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 319 else if (hdma->Instance == DMA1_Channel6)
<> 144:ef7eb2e8f9f7 320 {
<> 144:ef7eb2e8f9f7 321 /*Reset DMA request*/
<> 144:ef7eb2e8f9f7 322 DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 else if (hdma->Instance == DMA1_Channel7)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 /*Reset DMA request*/
<> 144:ef7eb2e8f9f7 327 DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329 #endif
<> 144:ef7eb2e8f9f7 330 /* Initialise the error code */
<> 144:ef7eb2e8f9f7 331 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 334 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Release Lock */
<> 144:ef7eb2e8f9f7 337 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 return HAL_OK;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /**
<> 144:ef7eb2e8f9f7 343 * @}
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /** @addtogroup DMA_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 347 * @brief I/O operation functions
<> 144:ef7eb2e8f9f7 348 *
<> 144:ef7eb2e8f9f7 349 @verbatim
<> 144:ef7eb2e8f9f7 350 ===============================================================================
<> 144:ef7eb2e8f9f7 351 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 352 ===============================================================================
<> 144:ef7eb2e8f9f7 353 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 354 (+) Configure the source, destination address and data length and Start DMA transfer
<> 144:ef7eb2e8f9f7 355 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 356 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 357 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 358 (+) Poll for transfer complete
<> 144:ef7eb2e8f9f7 359 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 @endverbatim
<> 144:ef7eb2e8f9f7 362 * @{
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /**
<> 144:ef7eb2e8f9f7 366 * @brief Starts the DMA Transfer.
<> 144:ef7eb2e8f9f7 367 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 368 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 369 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 370 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 371 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 372 * @retval HAL status
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 375 {
<> 144:ef7eb2e8f9f7 376 /* Process locked */
<> 144:ef7eb2e8f9f7 377 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 380 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Check the parameters */
<> 144:ef7eb2e8f9f7 383 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 386 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 389 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 392 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 return HAL_OK;
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /**
<> 144:ef7eb2e8f9f7 398 * @brief Start the DMA Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 399 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 400 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 401 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 402 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 403 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 404 * @retval HAL status
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 /* Process locked */
<> 144:ef7eb2e8f9f7 409 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 412 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /* Check the parameters */
<> 144:ef7eb2e8f9f7 415 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 418 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 421 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Enable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 424 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* Enable the Half transfer complete interrupt */
<> 144:ef7eb2e8f9f7 427 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Enable the transfer Error interrupt */
<> 144:ef7eb2e8f9f7 430 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 433 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 return HAL_OK;
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @brief Aborts the DMA Transfer.
<> 144:ef7eb2e8f9f7 440 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 441 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 442 * @retval HAL status
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 445 {
<> 151:5eaa88a5bcc7 446 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Disable the channel */
<> 144:ef7eb2e8f9f7 449 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Get timeout */
<> 144:ef7eb2e8f9f7 452 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Check if the DMA Channel is effectively disabled */
<> 151:5eaa88a5bcc7 455 while((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 458 if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
<> 144:ef7eb2e8f9f7 459 {
<> 144:ef7eb2e8f9f7 460 /* Update error code */
<> 144:ef7eb2e8f9f7 461 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 464 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 467 hdma->State = HAL_DMA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 473 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* Change the DMA state*/
<> 144:ef7eb2e8f9f7 476 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 return HAL_OK;
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /**
<> 153:fa9ff456f731 482 * @brief Aborts the DMA Transfer in Interrupt mode.
<> 153:fa9ff456f731 483 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 153:fa9ff456f731 484 * the configuration information for the specified DMA Stream.
<> 153:fa9ff456f731 485 * @retval HAL status
<> 153:fa9ff456f731 486 */
<> 153:fa9ff456f731 487 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 153:fa9ff456f731 488 {
<> 153:fa9ff456f731 489 HAL_StatusTypeDef status = HAL_OK;
<> 153:fa9ff456f731 490
<> 153:fa9ff456f731 491 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 153:fa9ff456f731 492 {
<> 153:fa9ff456f731 493 /* no transfer ongoing */
<> 153:fa9ff456f731 494 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 153:fa9ff456f731 495
<> 153:fa9ff456f731 496 status = HAL_ERROR;
<> 153:fa9ff456f731 497 }
<> 153:fa9ff456f731 498 else
<> 153:fa9ff456f731 499 {
<> 153:fa9ff456f731 500 /* Disable DMA IT */
<> 153:fa9ff456f731 501 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 153:fa9ff456f731 502
<> 153:fa9ff456f731 503 /* Disable the channel */
<> 153:fa9ff456f731 504 __HAL_DMA_DISABLE(hdma);
<> 153:fa9ff456f731 505
<> 153:fa9ff456f731 506 /* Clear all flags */
<> 153:fa9ff456f731 507 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
<> 153:fa9ff456f731 508
<> 153:fa9ff456f731 509 /* Change the DMA state */
<> 153:fa9ff456f731 510 hdma->State = HAL_DMA_STATE_READY;
<> 153:fa9ff456f731 511
<> 153:fa9ff456f731 512 /* Process Unlocked */
<> 153:fa9ff456f731 513 __HAL_UNLOCK(hdma);
<> 153:fa9ff456f731 514
<> 153:fa9ff456f731 515 /* Call User Abort callback */
<> 153:fa9ff456f731 516 if(hdma->XferAbortCallback != NULL)
<> 153:fa9ff456f731 517 {
<> 153:fa9ff456f731 518 hdma->XferAbortCallback(hdma);
<> 153:fa9ff456f731 519 }
<> 153:fa9ff456f731 520 }
<> 153:fa9ff456f731 521 return status;
<> 153:fa9ff456f731 522 }
<> 153:fa9ff456f731 523
<> 153:fa9ff456f731 524 /**
<> 144:ef7eb2e8f9f7 525 * @brief Polling for transfer complete.
<> 144:ef7eb2e8f9f7 526 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 527 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 528 * @param CompleteLevel: Specifies the DMA level complete.
<> 144:ef7eb2e8f9f7 529 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 530 * @retval HAL status
<> 144:ef7eb2e8f9f7 531 */
<> 144:ef7eb2e8f9f7 532 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 uint32_t temp;
<> 151:5eaa88a5bcc7 535 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 538 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 /* Transfer Complete flag */
<> 144:ef7eb2e8f9f7 541 temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543 else
<> 144:ef7eb2e8f9f7 544 {
<> 144:ef7eb2e8f9f7 545 /* Half Transfer Complete flag */
<> 144:ef7eb2e8f9f7 546 temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /* Get timeout */
<> 144:ef7eb2e8f9f7 550 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 /* Clear the transfer error flags */
<> 144:ef7eb2e8f9f7 557 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Update error code */
<> 144:ef7eb2e8f9f7 560 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 563 hdma->State= HAL_DMA_STATE_ERROR;
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 566 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 571 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 572 {
<> 151:5eaa88a5bcc7 573 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 /* Update error code */
<> 144:ef7eb2e8f9f7 576 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 579 hdma->State= HAL_DMA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 582 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 592 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 595 all transfers are complete) */
<> 144:ef7eb2e8f9f7 596 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Process unlocked */
<> 144:ef7eb2e8f9f7 599 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601 else
<> 144:ef7eb2e8f9f7 602 {
<> 144:ef7eb2e8f9f7 603 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 604 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 607 all transfers are complete) */
<> 144:ef7eb2e8f9f7 608 hdma->State = HAL_DMA_STATE_READY_HALF;
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Process unlocked */
<> 144:ef7eb2e8f9f7 611 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 612 }
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 return HAL_OK;
<> 144:ef7eb2e8f9f7 615 }
<> 144:ef7eb2e8f9f7 616 /**
<> 144:ef7eb2e8f9f7 617 * @brief Handles DMA interrupt request.
<> 144:ef7eb2e8f9f7 618 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 619 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 620 * @retval None
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 /* Transfer Error Interrupt management ***************************************/
<> 144:ef7eb2e8f9f7 625 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 /* Disable the transfer error interrupt */
<> 144:ef7eb2e8f9f7 630 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Clear the transfer error flag */
<> 144:ef7eb2e8f9f7 633 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Update error code */
<> 144:ef7eb2e8f9f7 636 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 639 hdma->State = HAL_DMA_STATE_ERROR;
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 642 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 if (hdma->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 /* Transfer error callback */
<> 144:ef7eb2e8f9f7 647 hdma->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 648 }
<> 144:ef7eb2e8f9f7 649 }
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* Half Transfer Complete Interrupt management ******************************/
<> 144:ef7eb2e8f9f7 653 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 151:5eaa88a5bcc7 658 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 659 {
<> 144:ef7eb2e8f9f7 660 /* Disable the half transfer interrupt */
<> 144:ef7eb2e8f9f7 661 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 664 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 667 hdma->State = HAL_DMA_STATE_READY_HALF;
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 672 hdma->XferHalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Transfer Complete Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 678 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
<> 144:ef7eb2e8f9f7 681 {
<> 151:5eaa88a5bcc7 682 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 /* Disable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 685 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 688 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* Update error code */
<> 144:ef7eb2e8f9f7 691 hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 694 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 697 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 if(hdma->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 /* Transfer complete callback */
<> 144:ef7eb2e8f9f7 702 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /**
<> 144:ef7eb2e8f9f7 709 * @}
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /** @addtogroup DMA_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 713 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 714 *
<> 144:ef7eb2e8f9f7 715 @verbatim
<> 144:ef7eb2e8f9f7 716 ===============================================================================
<> 144:ef7eb2e8f9f7 717 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 718 ===============================================================================
<> 144:ef7eb2e8f9f7 719 [..]
<> 144:ef7eb2e8f9f7 720 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 721 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 722 (+) Get error code
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 @endverbatim
<> 144:ef7eb2e8f9f7 725 * @{
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /**
<> 144:ef7eb2e8f9f7 729 * @brief Returns the DMA state.
<> 144:ef7eb2e8f9f7 730 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 731 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 732 * @retval HAL state
<> 144:ef7eb2e8f9f7 733 */
<> 144:ef7eb2e8f9f7 734 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 735 {
<> 144:ef7eb2e8f9f7 736 return hdma->State;
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /**
<> 144:ef7eb2e8f9f7 740 * @brief Return the DMA error code
<> 144:ef7eb2e8f9f7 741 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 742 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 743 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 744 */
<> 144:ef7eb2e8f9f7 745 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /**
<> 144:ef7eb2e8f9f7 751 * @}
<> 144:ef7eb2e8f9f7 752 */
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /**
<> 144:ef7eb2e8f9f7 755 * @}
<> 144:ef7eb2e8f9f7 756 */
<> 144:ef7eb2e8f9f7 757 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 758 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 762 /** @addtogroup DMA_Private
<> 144:ef7eb2e8f9f7 763 * @{
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /*
<> 144:ef7eb2e8f9f7 767 * @brief Sets the DMA Transfer parameter.
<> 144:ef7eb2e8f9f7 768 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 769 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 770 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 771 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 772 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 773 * @retval HAL status
<> 144:ef7eb2e8f9f7 774 */
<> 144:ef7eb2e8f9f7 775 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 776 {
<> 144:ef7eb2e8f9f7 777 /* Configure DMA Channel data length */
<> 144:ef7eb2e8f9f7 778 hdma->Instance->CNDTR = DataLength;
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 781 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 784 hdma->Instance->CPAR = DstAddress;
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 787 hdma->Instance->CMAR = SrcAddress;
<> 144:ef7eb2e8f9f7 788 }
<> 144:ef7eb2e8f9f7 789 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 790 else
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 793 hdma->Instance->CPAR = SrcAddress;
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 796 hdma->Instance->CMAR = DstAddress;
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798 }
<> 144:ef7eb2e8f9f7 799 /**
<> 144:ef7eb2e8f9f7 800 * @}
<> 144:ef7eb2e8f9f7 801 */
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /**
<> 144:ef7eb2e8f9f7 804 * @}
<> 144:ef7eb2e8f9f7 805 */
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 808 /**
<> 144:ef7eb2e8f9f7 809 * @}
<> 144:ef7eb2e8f9f7 810 */
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 813