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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_dac.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_dac.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of DAC HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32L0xx_HAL_DAC_H
<> 144:ef7eb2e8f9f7 38 #define __STM32L0xx_HAL_DAC_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @defgroup DAC DAC
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup DAC_Exported_Types DAC Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef enum
<> 144:ef7eb2e8f9f7 67 {
<> 151:5eaa88a5bcc7 68 HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
<> 151:5eaa88a5bcc7 69 HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
<> 151:5eaa88a5bcc7 70 HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
<> 151:5eaa88a5bcc7 71 HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
<> 151:5eaa88a5bcc7 72 HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 }HAL_DAC_StateTypeDef;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @brief DAC handle Structure definition
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 typedef struct
<> 144:ef7eb2e8f9f7 80 {
<> 144:ef7eb2e8f9f7 81 DAC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 HAL_LockTypeDef Lock; /*!< DAC locking object */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 90 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
<> 144:ef7eb2e8f9f7 91 #endif
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 __IO uint32_t ErrorCode; /*!< DAC Error code */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 }DAC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /**
<> 144:ef7eb2e8f9f7 98 * @brief DAC Configuration regular Channel structure definition
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100 typedef struct
<> 144:ef7eb2e8f9f7 101 {
<> 144:ef7eb2e8f9f7 102 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
<> 144:ef7eb2e8f9f7 103 This parameter can be a value of @ref DAC_trigger_selection */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
<> 144:ef7eb2e8f9f7 106 This parameter can be a value of @ref DAC_output_buffer */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 }DAC_ChannelConfTypeDef;
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /**
<> 144:ef7eb2e8f9f7 111 * @}
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /** @defgroup DAC_Exported_Constants DAC Exported Constants
<> 144:ef7eb2e8f9f7 117 * @{
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /** @defgroup DAC_Error_Code DAC Error Code
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 151:5eaa88a5bcc7 123 #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
<> 151:5eaa88a5bcc7 124 #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
<> 144:ef7eb2e8f9f7 125 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 151:5eaa88a5bcc7 126 #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
<> 144:ef7eb2e8f9f7 127 #endif
<> 151:5eaa88a5bcc7 128 #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @}
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup DAC_trigger_selection DAC trigger selection
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 151:5eaa88a5bcc7 136 #define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
<> 144:ef7eb2e8f9f7 137 #define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 138 #define DAC_TRIGGER_T21_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM21 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 139 #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 140 #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 141 #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 144 #define DAC_TRIGGER_T3_TRGO ((uint32_t)( DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 145 #define DAC_TRIGGER_T3_CH3 ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM3 CH3 selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 146 #define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 147 #endif
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 150 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
<> 144:ef7eb2e8f9f7 151 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
<> 144:ef7eb2e8f9f7 152 ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
<> 144:ef7eb2e8f9f7 153 ((TRIGGER) == DAC_TRIGGER_T3_CH3) || \
<> 144:ef7eb2e8f9f7 154 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
<> 144:ef7eb2e8f9f7 155 ((TRIGGER) == DAC_TRIGGER_T21_TRGO) || \
<> 144:ef7eb2e8f9f7 156 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 157 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
<> 144:ef7eb2e8f9f7 158 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
<> 144:ef7eb2e8f9f7 159 #else /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
<> 144:ef7eb2e8f9f7 160 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
<> 144:ef7eb2e8f9f7 161 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
<> 144:ef7eb2e8f9f7 162 ((TRIGGER) == DAC_TRIGGER_T21_TRGO) || \
<> 144:ef7eb2e8f9f7 163 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 164 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
<> 144:ef7eb2e8f9f7 165 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
<> 144:ef7eb2e8f9f7 166 #endif /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @defgroup DAC_output_buffer DAC output buffer
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 151:5eaa88a5bcc7 174 #define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 175 #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
<> 144:ef7eb2e8f9f7 178 ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @}
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /** @defgroup DAC_Channel_selection DAC Channel selection
<> 144:ef7eb2e8f9f7 184 * @{
<> 144:ef7eb2e8f9f7 185 */
<> 151:5eaa88a5bcc7 186 #define DAC_CHANNEL_1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 187 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 151:5eaa88a5bcc7 188 #define DAC_CHANNEL_2 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 189 #endif
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 192 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 193 ((CHANNEL) == DAC_CHANNEL_2))
<> 144:ef7eb2e8f9f7 194 #else
<> 144:ef7eb2e8f9f7 195 #define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 196 #endif
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @}
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /** @defgroup DAC_data_alignement DAC data alignement
<> 144:ef7eb2e8f9f7 202 * @{
<> 144:ef7eb2e8f9f7 203 */
<> 151:5eaa88a5bcc7 204 #define DAC_ALIGN_12B_R ((uint32_t)0x00000000U)
<> 151:5eaa88a5bcc7 205 #define DAC_ALIGN_12B_L ((uint32_t)0x00000004U)
<> 151:5eaa88a5bcc7 206 #define DAC_ALIGN_8B_R ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
<> 144:ef7eb2e8f9f7 209 ((ALIGN) == DAC_ALIGN_12B_L) || \
<> 144:ef7eb2e8f9f7 210 ((ALIGN) == DAC_ALIGN_8B_R))
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @}
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /** @defgroup DAC_data DAC data
<> 144:ef7eb2e8f9f7 216 * @{
<> 144:ef7eb2e8f9f7 217 */
<> 151:5eaa88a5bcc7 218 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
<> 144:ef7eb2e8f9f7 219 /**
<> 144:ef7eb2e8f9f7 220 * @}
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /** @defgroup DAC_flags_definition DAC flags definition
<> 144:ef7eb2e8f9f7 224 * @{
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 144:ef7eb2e8f9f7 227 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 228 #define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 144:ef7eb2e8f9f7 229 #endif
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /**
<> 144:ef7eb2e8f9f7 232 * @}
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /** @defgroup DAC_IT_definition DAC IT definition
<> 144:ef7eb2e8f9f7 236 * @{
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 #define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 144:ef7eb2e8f9f7 239 #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 240 #define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 144:ef7eb2e8f9f7 241 #endif
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @}
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @}
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** @defgroup DAC_Exported_Macros DAC Exported Macros
<> 144:ef7eb2e8f9f7 254 * @{
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /** @brief Reset DAC handle state
<> 144:ef7eb2e8f9f7 258 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 259 * @retval None
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /** @brief Enable the DAC channel
<> 144:ef7eb2e8f9f7 264 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 265 * @param __DAC_CHANNEL__: specifies the DAC channel
<> 144:ef7eb2e8f9f7 266 * @retval None
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \
<> 144:ef7eb2e8f9f7 269 SET_BIT((__HANDLE__)->Instance->CR, (DAC_CR_EN1 << (__DAC_CHANNEL__)))
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /** @brief Disable the DAC channel
<> 144:ef7eb2e8f9f7 272 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 273 * @param __DAC_CHANNEL__: specifies the DAC channel.
<> 144:ef7eb2e8f9f7 274 * @retval None
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \
<> 144:ef7eb2e8f9f7 277 CLEAR_BIT((__HANDLE__)->Instance->CR, (DAC_CR_EN1 << (__DAC_CHANNEL__)))
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
Anna Bridge 186:707f6e361f3e 281 SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /** @brief Disable the DAC interrupt
<> 144:ef7eb2e8f9f7 285 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 286 * @param __INTERRUPT__: specifies the DAC interrupt.
<> 144:ef7eb2e8f9f7 287 * @retval None
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
Anna Bridge 186:707f6e361f3e 290 CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /** @brief Check whether the specified DAC interrupt source is enabled or not.
<> 144:ef7eb2e8f9f7 293 * @param __HANDLE__: DAC handle
<> 144:ef7eb2e8f9f7 294 * @param __INTERRUPT__: DAC interrupt source to check
<> 144:ef7eb2e8f9f7 295 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 296 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 297 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (STM32L072xx STM32L073xx STM32L082xx STM32L083xx only)
<> 144:ef7eb2e8f9f7 298 * @retval State of interruption (SET or RESET)
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 301 (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /** @brief Get the selected DAC's flag status.
<> 144:ef7eb2e8f9f7 304 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 305 * @param __FLAG__: specifies the FLAG.
<> 144:ef7eb2e8f9f7 306 * @retval None
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 309 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /** @brief Clear the DAC's flag.
<> 144:ef7eb2e8f9f7 312 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 313 * @param __FLAG__: specifies the FLAG.
<> 144:ef7eb2e8f9f7 314 * @retval None
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 317 (((__HANDLE__)->Instance->SR) = (__FLAG__))
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /**
<> 144:ef7eb2e8f9f7 320 * @}
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /* Private macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /** @defgroup DAC_Private_Macros DAC Private Macros
<> 144:ef7eb2e8f9f7 326 * @{
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /** @brief Set DHR12R1 alignment
<> 144:ef7eb2e8f9f7 330 * @param __ALIGNEMENT__: specifies the DAC alignement
<> 144:ef7eb2e8f9f7 331 * @retval None
<> 144:ef7eb2e8f9f7 332 */
<> 151:5eaa88a5bcc7 333 #define DAC_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008U) + (__ALIGNEMENT__))
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /** @brief Set DHR12R2 alignment
<> 144:ef7eb2e8f9f7 336 * @param __ALIGNEMENT__: specifies the DAC alignement
<> 144:ef7eb2e8f9f7 337 * @retval None
<> 144:ef7eb2e8f9f7 338 */
<> 151:5eaa88a5bcc7 339 #define DAC_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014U) + (__ALIGNEMENT__))
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /** @brief Set DHR12RD alignment
<> 144:ef7eb2e8f9f7 342 * @param __ALIGNEMENT__: specifies the DAC alignement
<> 144:ef7eb2e8f9f7 343 * @retval None
<> 144:ef7eb2e8f9f7 344 */
<> 151:5eaa88a5bcc7 345 #define DAC_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020U) + (__ALIGNEMENT__))
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /** @brief Enable the DAC interrupt
<> 144:ef7eb2e8f9f7 348 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 349 * @param __INTERRUPT__: specifies the DAC interrupt.
<> 144:ef7eb2e8f9f7 350 * @retval None
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Include DAC HAL Extension module */
<> 144:ef7eb2e8f9f7 359 #include "stm32l0xx_hal_dac_ex.h"
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /** @defgroup DAC_Exported_Functions DAC Exported Functions
<> 144:ef7eb2e8f9f7 364 * @{
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 368 * @{
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 371 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 372 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 373 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 374 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /**
<> 144:ef7eb2e8f9f7 377 * @}
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 381 * @{
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 384 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 385 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 386 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
<> 144:ef7eb2e8f9f7 387 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 388 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
<> 144:ef7eb2e8f9f7 389 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 390 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 391 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 392 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 393 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 394 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /**
<> 144:ef7eb2e8f9f7 397 * @}
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 401 * @{
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 404 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /**
<> 144:ef7eb2e8f9f7 407 * @}
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 411 * @{
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413 /* Peripheral State functions ***************************************************/
<> 144:ef7eb2e8f9f7 414 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 415 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /**
<> 144:ef7eb2e8f9f7 418 * @}
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /**
<> 144:ef7eb2e8f9f7 422 * @}
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /**
<> 144:ef7eb2e8f9f7 426 * @}
<> 144:ef7eb2e8f9f7 427 */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 #endif /* STM32L011xx && STM32L021xx && STM32L031xx && STM32L041xx && STM32L061xx && STM32L071xx && STM32L081xx*/
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437 #endif
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 #endif /*__STM32L0xx_HAL_DAC_H */
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/