mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_cortex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of CORTEX HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32L0xx_HAL_CORTEX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32L0xx_HAL_CORTEX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @defgroup CORTEX CORTEX
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 61 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 uint8_t Enable; /*!< Specifies the status of the region.
<> 144:ef7eb2e8f9f7 69 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
<> 144:ef7eb2e8f9f7 70 uint8_t Number; /*!< Specifies the number of the region to protect.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint8_t Size; /*!< Specifies the size of the region to protect.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
<> 144:ef7eb2e8f9f7 75 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
<> 144:ef7eb2e8f9f7 76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 77 uint8_t TypeExtField; /*!< This parameter is NOT used but is kept to keep API unified through all families*/
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint8_t AccessPermission; /*!< Specifies the region access permission type.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
<> 144:ef7eb2e8f9f7 81 uint8_t DisableExec; /*!< Specifies the instruction access status.
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
<> 144:ef7eb2e8f9f7 83 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
<> 144:ef7eb2e8f9f7 84 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
<> 144:ef7eb2e8f9f7 85 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
<> 144:ef7eb2e8f9f7 87 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
<> 144:ef7eb2e8f9f7 89 }MPU_Region_InitTypeDef;
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @}
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /**
<> 144:ef7eb2e8f9f7 96 * @}
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106
<> 151:5eaa88a5bcc7 107 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4U)
<> 144:ef7eb2e8f9f7 108
<> 151:5eaa88a5bcc7 109 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0)
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source
<> 144:ef7eb2e8f9f7 112 * @{
<> 144:ef7eb2e8f9f7 113 */
<> 151:5eaa88a5bcc7 114 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
<> 151:5eaa88a5bcc7 115 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 116 #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
<> 144:ef7eb2e8f9f7 117 ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @}
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 123 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 151:5eaa88a5bcc7 126 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
<> 151:5eaa88a5bcc7 127 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
<> 151:5eaa88a5bcc7 128 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
<> 151:5eaa88a5bcc7 129 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
<> 144:ef7eb2e8f9f7 130 /**
<> 144:ef7eb2e8f9f7 131 * @}
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 151:5eaa88a5bcc7 137 #define MPU_REGION_ENABLE ((uint8_t)0x01U)
<> 151:5eaa88a5bcc7 138 #define MPU_REGION_DISABLE ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @}
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 151:5eaa88a5bcc7 146 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
<> 151:5eaa88a5bcc7 147 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 148 /**
<> 144:ef7eb2e8f9f7 149 * @}
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 151:5eaa88a5bcc7 155 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
<> 151:5eaa88a5bcc7 156 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @}
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 151:5eaa88a5bcc7 164 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
<> 151:5eaa88a5bcc7 165 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
<> 144:ef7eb2e8f9f7 171 * @{
<> 144:ef7eb2e8f9f7 172 */
<> 151:5eaa88a5bcc7 173 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
<> 151:5eaa88a5bcc7 174 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @}
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 151:5eaa88a5bcc7 182 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
<> 151:5eaa88a5bcc7 183 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
<> 151:5eaa88a5bcc7 184 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
<> 151:5eaa88a5bcc7 185 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
<> 151:5eaa88a5bcc7 186 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
<> 151:5eaa88a5bcc7 187 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
<> 151:5eaa88a5bcc7 188 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
<> 151:5eaa88a5bcc7 189 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
<> 151:5eaa88a5bcc7 190 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
<> 151:5eaa88a5bcc7 191 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
<> 151:5eaa88a5bcc7 192 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
<> 151:5eaa88a5bcc7 193 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
<> 151:5eaa88a5bcc7 194 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
<> 151:5eaa88a5bcc7 195 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
<> 151:5eaa88a5bcc7 196 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
<> 151:5eaa88a5bcc7 197 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
<> 151:5eaa88a5bcc7 198 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
<> 151:5eaa88a5bcc7 199 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
<> 151:5eaa88a5bcc7 200 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
<> 151:5eaa88a5bcc7 201 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
<> 151:5eaa88a5bcc7 202 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
<> 151:5eaa88a5bcc7 203 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
<> 151:5eaa88a5bcc7 204 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
<> 151:5eaa88a5bcc7 205 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
<> 151:5eaa88a5bcc7 206 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
<> 151:5eaa88a5bcc7 207 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
<> 151:5eaa88a5bcc7 208 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
<> 151:5eaa88a5bcc7 209 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
<> 144:ef7eb2e8f9f7 210 /**
<> 144:ef7eb2e8f9f7 211 * @}
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
<> 144:ef7eb2e8f9f7 215 * @{
<> 144:ef7eb2e8f9f7 216 */
<> 151:5eaa88a5bcc7 217 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
<> 151:5eaa88a5bcc7 218 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
<> 151:5eaa88a5bcc7 219 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
<> 151:5eaa88a5bcc7 220 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
<> 151:5eaa88a5bcc7 221 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
<> 151:5eaa88a5bcc7 222 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
<> 144:ef7eb2e8f9f7 228 * @{
<> 144:ef7eb2e8f9f7 229 */
<> 151:5eaa88a5bcc7 230 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
<> 151:5eaa88a5bcc7 231 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
<> 151:5eaa88a5bcc7 232 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
<> 151:5eaa88a5bcc7 233 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
<> 151:5eaa88a5bcc7 234 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
<> 151:5eaa88a5bcc7 235 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
<> 151:5eaa88a5bcc7 236 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
<> 151:5eaa88a5bcc7 237 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
<> 144:ef7eb2e8f9f7 238 /**
<> 144:ef7eb2e8f9f7 239 * @}
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @}
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 249 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
<> 144:ef7eb2e8f9f7 250 * @{
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 254 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 255 * @{
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
<> 144:ef7eb2e8f9f7 258 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 259 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 260 void HAL_NVIC_SystemReset(void);
<> 144:ef7eb2e8f9f7 261 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
<> 144:ef7eb2e8f9f7 262 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @brief Disable the MPU.
<> 144:ef7eb2e8f9f7 265 * @retval None
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 __STATIC_INLINE void HAL_MPU_Disable(void)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /*Data Memory Barrier setup */
<> 144:ef7eb2e8f9f7 271 __DMB();
<> 144:ef7eb2e8f9f7 272 /* Disable the MPU */
<> 144:ef7eb2e8f9f7 273 MPU->CTRL = 0;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @brief Enable the MPU.
<> 144:ef7eb2e8f9f7 278 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
<> 144:ef7eb2e8f9f7 279 * NMI, FAULTMASK and privileged access to the default memory
<> 144:ef7eb2e8f9f7 280 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 281 * @arg MPU_HFNMI_PRIVDEF_NONE
<> 144:ef7eb2e8f9f7 282 * @arg MPU_HARDFAULT_NMI
<> 144:ef7eb2e8f9f7 283 * @arg MPU_PRIVILEGED_DEFAULT
<> 144:ef7eb2e8f9f7 284 * @arg MPU_HFNMI_PRIVDEF
<> 144:ef7eb2e8f9f7 285 * @retval None
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 /* Enable the MPU */
<> 144:ef7eb2e8f9f7 291 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
<> 144:ef7eb2e8f9f7 292 /* Data Synchronization Barrier setup */
<> 144:ef7eb2e8f9f7 293 __DSB();
<> 144:ef7eb2e8f9f7 294 /* Instruction Synchronization Barrier setup */
<> 144:ef7eb2e8f9f7 295 __ISB();
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @}
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 304 * @brief Cortex control functions
<> 144:ef7eb2e8f9f7 305 * @{
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 309 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 310 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 311 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 312 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
<> 144:ef7eb2e8f9f7 313 void HAL_SYSTICK_IRQHandler(void);
<> 144:ef7eb2e8f9f7 314 void HAL_SYSTICK_Callback(void);
<> 144:ef7eb2e8f9f7 315 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 316 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
<> 144:ef7eb2e8f9f7 317 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 318 /**
<> 144:ef7eb2e8f9f7 319 * @}
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 327 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 328 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 329 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 330 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 335 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
<> 144:ef7eb2e8f9f7 336 ((STATE) == MPU_REGION_DISABLE))
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
<> 144:ef7eb2e8f9f7 339 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
<> 144:ef7eb2e8f9f7 342 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
<> 144:ef7eb2e8f9f7 345 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
<> 144:ef7eb2e8f9f7 348 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
<> 144:ef7eb2e8f9f7 351 ((TYPE) == MPU_REGION_PRIV_RW) || \
<> 144:ef7eb2e8f9f7 352 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
<> 144:ef7eb2e8f9f7 353 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
<> 144:ef7eb2e8f9f7 354 ((TYPE) == MPU_REGION_PRIV_RO) || \
<> 144:ef7eb2e8f9f7 355 ((TYPE) == MPU_REGION_PRIV_RO_URO))
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
<> 144:ef7eb2e8f9f7 358 ((NUMBER) == MPU_REGION_NUMBER1) || \
<> 144:ef7eb2e8f9f7 359 ((NUMBER) == MPU_REGION_NUMBER2) || \
<> 144:ef7eb2e8f9f7 360 ((NUMBER) == MPU_REGION_NUMBER3) || \
<> 144:ef7eb2e8f9f7 361 ((NUMBER) == MPU_REGION_NUMBER4) || \
<> 144:ef7eb2e8f9f7 362 ((NUMBER) == MPU_REGION_NUMBER5) || \
<> 144:ef7eb2e8f9f7 363 ((NUMBER) == MPU_REGION_NUMBER6) || \
<> 144:ef7eb2e8f9f7 364 ((NUMBER) == MPU_REGION_NUMBER7))
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \
<> 144:ef7eb2e8f9f7 367 ((SIZE) == MPU_REGION_SIZE_512B) || \
<> 144:ef7eb2e8f9f7 368 ((SIZE) == MPU_REGION_SIZE_1KB) || \
<> 144:ef7eb2e8f9f7 369 ((SIZE) == MPU_REGION_SIZE_2KB) || \
<> 144:ef7eb2e8f9f7 370 ((SIZE) == MPU_REGION_SIZE_4KB) || \
<> 144:ef7eb2e8f9f7 371 ((SIZE) == MPU_REGION_SIZE_8KB) || \
<> 144:ef7eb2e8f9f7 372 ((SIZE) == MPU_REGION_SIZE_16KB) || \
<> 144:ef7eb2e8f9f7 373 ((SIZE) == MPU_REGION_SIZE_32KB) || \
<> 144:ef7eb2e8f9f7 374 ((SIZE) == MPU_REGION_SIZE_64KB) || \
<> 144:ef7eb2e8f9f7 375 ((SIZE) == MPU_REGION_SIZE_128KB) || \
<> 144:ef7eb2e8f9f7 376 ((SIZE) == MPU_REGION_SIZE_256KB) || \
<> 144:ef7eb2e8f9f7 377 ((SIZE) == MPU_REGION_SIZE_512KB) || \
<> 144:ef7eb2e8f9f7 378 ((SIZE) == MPU_REGION_SIZE_1MB) || \
<> 144:ef7eb2e8f9f7 379 ((SIZE) == MPU_REGION_SIZE_2MB) || \
<> 144:ef7eb2e8f9f7 380 ((SIZE) == MPU_REGION_SIZE_4MB) || \
<> 144:ef7eb2e8f9f7 381 ((SIZE) == MPU_REGION_SIZE_8MB) || \
<> 144:ef7eb2e8f9f7 382 ((SIZE) == MPU_REGION_SIZE_16MB) || \
<> 144:ef7eb2e8f9f7 383 ((SIZE) == MPU_REGION_SIZE_32MB) || \
<> 144:ef7eb2e8f9f7 384 ((SIZE) == MPU_REGION_SIZE_64MB) || \
<> 144:ef7eb2e8f9f7 385 ((SIZE) == MPU_REGION_SIZE_128MB) || \
<> 144:ef7eb2e8f9f7 386 ((SIZE) == MPU_REGION_SIZE_256MB) || \
<> 144:ef7eb2e8f9f7 387 ((SIZE) == MPU_REGION_SIZE_512MB) || \
<> 144:ef7eb2e8f9f7 388 ((SIZE) == MPU_REGION_SIZE_1GB) || \
<> 144:ef7eb2e8f9f7 389 ((SIZE) == MPU_REGION_SIZE_2GB) || \
<> 144:ef7eb2e8f9f7 390 ((SIZE) == MPU_REGION_SIZE_4GB))
<> 144:ef7eb2e8f9f7 391
<> 151:5eaa88a5bcc7 392 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
<> 144:ef7eb2e8f9f7 393 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /**
<> 144:ef7eb2e8f9f7 397 * @}
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /**
<> 144:ef7eb2e8f9f7 401 * @}
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /**
<> 144:ef7eb2e8f9f7 405 * @}
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410 #endif
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 #endif /* __STM32L0xx_HAL_CORTEX_H */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 416