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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 186:707f6e361f3e

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l0xx_hal_adc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
Anna Bridge	186:707f6e361f3e	5	* @brief Header file of ADC HAL module.
<>	144:ef7eb2e8f9f7	6	******************************************************************************
<>	144:ef7eb2e8f9f7	7	* @attention
<>	144:ef7eb2e8f9f7	8	*
<>	144:ef7eb2e8f9f7	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	12	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	14	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	17	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	19	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	20	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	21	*
<>	144:ef7eb2e8f9f7	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	32	*
<>	144:ef7eb2e8f9f7	33	******************************************************************************
<>	144:ef7eb2e8f9f7	34	*/
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	/* Define to prevent recursive inclusion -------------------------------------*/
Anna Bridge	186:707f6e361f3e	37	#ifndef __STM32L0xx_HAL_ADC_H
Anna Bridge	186:707f6e361f3e	38	#define __STM32L0xx_HAL_ADC_H
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	41	extern "C" {
<>	144:ef7eb2e8f9f7	42	#endif
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	45	#include "stm32l0xx_hal_def.h"
Anna Bridge	186:707f6e361f3e	46
Anna Bridge	186:707f6e361f3e	47	/* Include low level driver */
Anna Bridge	186:707f6e361f3e	48	#include "stm32l0xx_ll_adc.h"
Anna Bridge	186:707f6e361f3e	49
<>	144:ef7eb2e8f9f7	50	/** @addtogroup STM32L0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	51	* @{
<>	144:ef7eb2e8f9f7	52	*/
<>	144:ef7eb2e8f9f7	53
Anna Bridge	186:707f6e361f3e	54	/** @addtogroup ADC
<>	144:ef7eb2e8f9f7	55	* @{
Anna Bridge	186:707f6e361f3e	56	*/
<>	144:ef7eb2e8f9f7	57
Anna Bridge	186:707f6e361f3e	58	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	59	/** @defgroup ADC_Exported_Types ADC Exported Types
<>	144:ef7eb2e8f9f7	60	* @{
<>	144:ef7eb2e8f9f7	61	*/
<>	144:ef7eb2e8f9f7	62
<>	144:ef7eb2e8f9f7	63	/**
Anna Bridge	186:707f6e361f3e	64	* @brief ADC group regular oversampling structure definition
<>	144:ef7eb2e8f9f7	65	*/
<>	144:ef7eb2e8f9f7	66	typedef struct
<>	144:ef7eb2e8f9f7	67	{
<>	144:ef7eb2e8f9f7	68	uint32_t Ratio; /*!< Configures the oversampling ratio.
<>	144:ef7eb2e8f9f7	69	This parameter can be a value of @ref ADC_Oversampling_Ratio */
Anna Bridge	186:707f6e361f3e	70
<>	144:ef7eb2e8f9f7	71	uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
<>	144:ef7eb2e8f9f7	72	This parameter can be a value of @ref ADC_Right_Bit_Shift */
Anna Bridge	186:707f6e361f3e	73
Anna Bridge	186:707f6e361f3e	74	uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
<>	144:ef7eb2e8f9f7	75	This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
<>	144:ef7eb2e8f9f7	76	}ADC_OversamplingTypeDef;
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78	/**
Anna Bridge	186:707f6e361f3e	79	* @brief Structure definition of ADC instance and ADC group regular.
Anna Bridge	186:707f6e361f3e	80	* @note Parameters of this structure are shared within 2 scopes:
Anna Bridge	186:707f6e361f3e	81	* - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
Anna Bridge	186:707f6e361f3e	82	* ScanConvMode, EOCSelection, LowPowerAutoWait.
Anna Bridge	186:707f6e361f3e	83	* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
Anna Bridge	186:707f6e361f3e	84	* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
Anna Bridge	186:707f6e361f3e	85	* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
Anna Bridge	186:707f6e361f3e	86	* ADC state can be either:
Anna Bridge	186:707f6e361f3e	87	* - For all parameters: ADC disabled
Anna Bridge	186:707f6e361f3e	88	* - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
<>	144:ef7eb2e8f9f7	89	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
Anna Bridge	186:707f6e361f3e	90	* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
Anna Bridge	186:707f6e361f3e	91	* (which fulfills the ADC state condition) on the fly).
<>	144:ef7eb2e8f9f7	92	*/
<>	144:ef7eb2e8f9f7	93	typedef struct
<>	144:ef7eb2e8f9f7	94	{
Anna Bridge	186:707f6e361f3e	95	uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator) and clock prescaler.
Anna Bridge	186:707f6e361f3e	96	This parameter can be a value of @ref ADC_ClockPrescaler.
Anna Bridge	186:707f6e361f3e	97	Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
Anna Bridge	186:707f6e361f3e	98	if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
Anna Bridge	186:707f6e361f3e	99	must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
Anna Bridge	186:707f6e361f3e	100	Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
Anna Bridge	186:707f6e361f3e	101	Note: This parameter can be modified only if the ADC is disabled. */
Anna Bridge	186:707f6e361f3e	102
Anna Bridge	186:707f6e361f3e	103	uint32_t Resolution; /*!< Configure the ADC resolution.
Anna Bridge	186:707f6e361f3e	104	This parameter can be a value of @ref ADC_Resolution */
Anna Bridge	186:707f6e361f3e	105
Anna Bridge	186:707f6e361f3e	106	uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
Anna Bridge	186:707f6e361f3e	107	Refer to reference manual for alignments formats versus resolutions.
Anna Bridge	186:707f6e361f3e	108	This parameter can be a value of @ref ADC_Data_align */
Anna Bridge	186:707f6e361f3e	109
Anna Bridge	186:707f6e361f3e	110	uint32_t ScanConvMode; /*!< Configure the sequencer of regular group.
Anna Bridge	186:707f6e361f3e	111	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
Anna Bridge	186:707f6e361f3e	112	Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
Anna Bridge	186:707f6e361f3e	113	If only 1 channel is set: Conversion is performed in single mode.
Anna Bridge	186:707f6e361f3e	114	If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Anna Bridge	186:707f6e361f3e	115	Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
Anna Bridge	186:707f6e361f3e	116	This parameter can be a value of @ref ADC_Scan_mode */
Anna Bridge	186:707f6e361f3e	117
Anna Bridge	186:707f6e361f3e	118	uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
Anna Bridge	186:707f6e361f3e	119	This parameter can be a value of @ref ADC_EOCSelection. */
Anna Bridge	186:707f6e361f3e	120
Anna Bridge	186:707f6e361f3e	121	uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
Anna Bridge	186:707f6e361f3e	122	conversion (for ADC group regular) has been retrieved by user software,
Anna Bridge	186:707f6e361f3e	123	using function HAL_ADC_GetValue().
Anna Bridge	186:707f6e361f3e	124	This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
Anna Bridge	186:707f6e361f3e	125	for low frequency applications.
Anna Bridge	186:707f6e361f3e	126	This parameter can be set to ENABLE or DISABLE.
Anna Bridge	186:707f6e361f3e	127	Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
Anna Bridge	186:707f6e361f3e	128	to free the IRQ vector sequencer.
Anna Bridge	186:707f6e361f3e	129	Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
Anna Bridge	186:707f6e361f3e	130	use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
Anna Bridge	186:707f6e361f3e	131
Anna Bridge	186:707f6e361f3e	132	uint32_t LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
Anna Bridge	186:707f6e361f3e	133	This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
Anna Bridge	186:707f6e361f3e	134	This parameter can be set to ENABLE or DISABLE.
Anna Bridge	186:707f6e361f3e	135	Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
Anna Bridge	186:707f6e361f3e	136
Anna Bridge	186:707f6e361f3e	137	uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
Anna Bridge	186:707f6e361f3e	138	after the first ADC conversion start trigger occurred (software start or external trigger).
Anna Bridge	186:707f6e361f3e	139	This parameter can be set to ENABLE or DISABLE. */
Anna Bridge	186:707f6e361f3e	140
Anna Bridge	186:707f6e361f3e	141	uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
Anna Bridge	186:707f6e361f3e	142	(main sequence subdivided in successive parts).
Anna Bridge	186:707f6e361f3e	143	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Anna Bridge	186:707f6e361f3e	144	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
Anna Bridge	186:707f6e361f3e	145	This parameter can be set to ENABLE or DISABLE.
Anna Bridge	186:707f6e361f3e	146	Note: On this STM32 serie, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
Anna Bridge	186:707f6e361f3e	147
Anna Bridge	186:707f6e361f3e	148	uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
Anna Bridge	186:707f6e361f3e	149	If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
Anna Bridge	186:707f6e361f3e	150	This parameter can be a value of @ref ADC_regular_external_trigger_source.
Anna Bridge	186:707f6e361f3e	151	Caution: external trigger source is common to all ADC instances. */
Anna Bridge	186:707f6e361f3e	152
Anna Bridge	186:707f6e361f3e	153	uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
Anna Bridge	186:707f6e361f3e	154	If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
Anna Bridge	186:707f6e361f3e	155	This parameter can be a value of @ref ADC_regular_external_trigger_edge */
Anna Bridge	186:707f6e361f3e	156
Anna Bridge	186:707f6e361f3e	157	uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
Anna Bridge	186:707f6e361f3e	158	or in continuous mode (DMA transfer unlimited, whatever number of conversions).
Anna Bridge	186:707f6e361f3e	159	This parameter can be set to ENABLE or DISABLE.
Anna Bridge	186:707f6e361f3e	160	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
Anna Bridge	186:707f6e361f3e	161
Anna Bridge	186:707f6e361f3e	162	uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
Anna Bridge	186:707f6e361f3e	163	This parameter can be a value of @ref ADC_Overrun.
Anna Bridge	186:707f6e361f3e	164	Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
Anna Bridge	186:707f6e361f3e	165	end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
Anna Bridge	186:707f6e361f3e	166	HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
Anna Bridge	186:707f6e361f3e	167	Note: Error reporting with respect to the conversion mode:
Anna Bridge	186:707f6e361f3e	168	- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
Anna Bridge	186:707f6e361f3e	169	overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
Anna Bridge	186:707f6e361f3e	170	- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
Anna Bridge	186:707f6e361f3e	171
Anna Bridge	186:707f6e361f3e	172	uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
Anna Bridge	186:707f6e361f3e	173	it is mandatory to first enable the Low Frequency Mode.
Anna Bridge	186:707f6e361f3e	174	This parameter can be set to ENABLE or DISABLE.
Anna Bridge	186:707f6e361f3e	175	Note: This parameter can be modified only if there is no conversion is ongoing. */
Anna Bridge	186:707f6e361f3e	176
Anna Bridge	186:707f6e361f3e	177
Anna Bridge	186:707f6e361f3e	178	uint32_t SamplingTime; /*!< The sample time common to all channels.
Anna Bridge	186:707f6e361f3e	179	Unit: ADC clock cycles
<>	144:ef7eb2e8f9f7	180	This parameter can be a value of @ref ADC_sampling_times
<>	144:ef7eb2e8f9f7	181	Note: This parameter can be modified only if there is no conversion ongoing. */
Anna Bridge	186:707f6e361f3e	182
Anna Bridge	186:707f6e361f3e	183	uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
Anna Bridge	186:707f6e361f3e	184	This parameter can be set to ENABLE or DISABLE.
Anna Bridge	186:707f6e361f3e	185	Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
Anna Bridge	186:707f6e361f3e	186
Anna Bridge	186:707f6e361f3e	187
Anna Bridge	186:707f6e361f3e	188	ADC_OversamplingTypeDef Oversample; /*!< Specify the Oversampling parameters
Anna Bridge	186:707f6e361f3e	189	Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
<>	144:ef7eb2e8f9f7	190	}ADC_InitTypeDef;
<>	144:ef7eb2e8f9f7	191
Anna Bridge	186:707f6e361f3e	192	/**
Anna Bridge	186:707f6e361f3e	193	* @brief Structure definition of ADC channel for regular group
Anna Bridge	186:707f6e361f3e	194	* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
Anna Bridge	186:707f6e361f3e	195	* ADC state can be either:
Anna Bridge	186:707f6e361f3e	196	* - For all parameters: ADC disabled or enabled without conversion on going on regular group.
Anna Bridge	186:707f6e361f3e	197	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
Anna Bridge	186:707f6e361f3e	198	* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
Anna Bridge	186:707f6e361f3e	199	*/
Anna Bridge	186:707f6e361f3e	200	typedef struct
Anna Bridge	186:707f6e361f3e	201	{
Anna Bridge	186:707f6e361f3e	202	uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
Anna Bridge	186:707f6e361f3e	203	This parameter can be a value of @ref ADC_channels
Anna Bridge	186:707f6e361f3e	204	Note: Depending on devices, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
Anna Bridge	186:707f6e361f3e	205
Anna Bridge	186:707f6e361f3e	206	uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
Anna Bridge	186:707f6e361f3e	207	On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
Anna Bridge	186:707f6e361f3e	208	(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Anna Bridge	186:707f6e361f3e	209	Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
Anna Bridge	186:707f6e361f3e	210	This parameter can be a value of @ref ADC_rank */
Anna Bridge	186:707f6e361f3e	211	}ADC_ChannelConfTypeDef;
Anna Bridge	186:707f6e361f3e	212
Anna Bridge	186:707f6e361f3e	213	/**
Anna Bridge	186:707f6e361f3e	214	* @brief Structure definition of ADC analog watchdog
Anna Bridge	186:707f6e361f3e	215	* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
Anna Bridge	186:707f6e361f3e	216	* ADC state can be either:
Anna Bridge	186:707f6e361f3e	217	* - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC group regular
Anna Bridge	186:707f6e361f3e	218	* - For parameters 'HighThreshold' and 'LowThreshold': ADC enabled with conversion on going on regular group (AWD thresholds can be modify on the fly while ADC conversion is on going)
Anna Bridge	186:707f6e361f3e	219	*/
Anna Bridge	186:707f6e361f3e	220	typedef struct
Anna Bridge	186:707f6e361f3e	221	{
Anna Bridge	186:707f6e361f3e	222	uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all channels.
Anna Bridge	186:707f6e361f3e	223	This parameter can be a value of @ref ADC_analog_watchdog_mode */
Anna Bridge	186:707f6e361f3e	224
Anna Bridge	186:707f6e361f3e	225	uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
Anna Bridge	186:707f6e361f3e	226	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
Anna Bridge	186:707f6e361f3e	227	This parameter can be a value of @ref ADC_channels */
Anna Bridge	186:707f6e361f3e	228
Anna Bridge	186:707f6e361f3e	229	uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
Anna Bridge	186:707f6e361f3e	230	This parameter can be set to ENABLE or DISABLE */
Anna Bridge	186:707f6e361f3e	231	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Anna Bridge	186:707f6e361f3e	232	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
Anna Bridge	186:707f6e361f3e	233	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
Anna Bridge	186:707f6e361f3e	234
Anna Bridge	186:707f6e361f3e	235	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Anna Bridge	186:707f6e361f3e	236	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
Anna Bridge	186:707f6e361f3e	237	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
Anna Bridge	186:707f6e361f3e	238	}ADC_AnalogWDGConfTypeDef;
Anna Bridge	186:707f6e361f3e	239
Anna Bridge	186:707f6e361f3e	240	/**
Anna Bridge	186:707f6e361f3e	241	* @brief HAL ADC state machine: ADC states definition (bitfields)
Anna Bridge	186:707f6e361f3e	242	* @note ADC state machine is managed by bitfields, state must be compared
Anna Bridge	186:707f6e361f3e	243	* with bit by bit.
Anna Bridge	186:707f6e361f3e	244	* For example:
Anna Bridge	186:707f6e361f3e	245	* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
Anna Bridge	186:707f6e361f3e	246	* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
Anna Bridge	186:707f6e361f3e	247	*/
Anna Bridge	186:707f6e361f3e	248	/* States of ADC global scope */
Anna Bridge	186:707f6e361f3e	249	#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /!< ADC not yet initialized or disabled /
Anna Bridge	186:707f6e361f3e	250	#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /!< ADC peripheral ready for use /
Anna Bridge	186:707f6e361f3e	251	#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /!< ADC is busy due to an internal process (initialization, calibration) /
Anna Bridge	186:707f6e361f3e	252	#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /!< TimeOut occurrence /
Anna Bridge	186:707f6e361f3e	253
Anna Bridge	186:707f6e361f3e	254	/* States of ADC errors */
Anna Bridge	186:707f6e361f3e	255	#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /!< Internal error occurrence /
Anna Bridge	186:707f6e361f3e	256	#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /!< Configuration error occurrence /
Anna Bridge	186:707f6e361f3e	257	#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /!< DMA error occurrence /
Anna Bridge	186:707f6e361f3e	258
Anna Bridge	186:707f6e361f3e	259	/* States of ADC group regular */
Anna Bridge	186:707f6e361f3e	260	#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
Anna Bridge	186:707f6e361f3e	261	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
Anna Bridge	186:707f6e361f3e	262	#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /!< Conversion data available on group regular /
Anna Bridge	186:707f6e361f3e	263	#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /!< Overrun occurrence /
Anna Bridge	186:707f6e361f3e	264	#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /!< Not available on this STM32 serie: End Of Sampling flag raised /
Anna Bridge	186:707f6e361f3e	265
Anna Bridge	186:707f6e361f3e	266	/* States of ADC group injected */
Anna Bridge	186:707f6e361f3e	267	#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on this STM32 serie: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
Anna Bridge	186:707f6e361f3e	268	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
Anna Bridge	186:707f6e361f3e	269	#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /!< Not available on this STM32 serie: Conversion data available on group injected /
Anna Bridge	186:707f6e361f3e	270	#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /!< Not available on this STM32 serie: Injected queue overflow occurrence /
Anna Bridge	186:707f6e361f3e	271
Anna Bridge	186:707f6e361f3e	272	/* States of ADC analog watchdogs */
Anna Bridge	186:707f6e361f3e	273	#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /!< Out-of-window occurrence of ADC analog watchdog 1 /
Anna Bridge	186:707f6e361f3e	274	#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 2 /
Anna Bridge	186:707f6e361f3e	275	#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 3 /
Anna Bridge	186:707f6e361f3e	276
Anna Bridge	186:707f6e361f3e	277	/* States of ADC multi-mode */
Anna Bridge	186:707f6e361f3e	278	#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /!< Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available) /
Anna Bridge	186:707f6e361f3e	279
Anna Bridge	186:707f6e361f3e	280
Anna Bridge	186:707f6e361f3e	281
<>	144:ef7eb2e8f9f7	282	/**
Anna Bridge	186:707f6e361f3e	283	* @brief ADC handle Structure definition
Anna Bridge	186:707f6e361f3e	284	*/
<>	144:ef7eb2e8f9f7	285	typedef struct
<>	144:ef7eb2e8f9f7	286	{
<>	144:ef7eb2e8f9f7	287	ADC_TypeDef Instance; /!< Register base address */
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	ADC_InitTypeDef Init; /!< ADC required parameters /
<>	144:ef7eb2e8f9f7	290
<>	144:ef7eb2e8f9f7	291	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	HAL_LockTypeDef Lock; /!< ADC locking object /
<>	144:ef7eb2e8f9f7	294
<>	144:ef7eb2e8f9f7	295	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
<>	144:ef7eb2e8f9f7	296
<>	144:ef7eb2e8f9f7	297	__IO uint32_t ErrorCode; /!< ADC Error code /
<>	144:ef7eb2e8f9f7	298	}ADC_HandleTypeDef;
<>	144:ef7eb2e8f9f7	299	/**
<>	144:ef7eb2e8f9f7	300	* @}
<>	144:ef7eb2e8f9f7	301	*/
<>	144:ef7eb2e8f9f7	302
<>	144:ef7eb2e8f9f7	303
<>	144:ef7eb2e8f9f7	304	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	305
<>	144:ef7eb2e8f9f7	306	/** @defgroup ADC_Exported_Constants ADC Exported Constants
<>	144:ef7eb2e8f9f7	307	* @{
<>	144:ef7eb2e8f9f7	308	*/
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	/** @defgroup ADC_Error_Code ADC Error Code
<>	144:ef7eb2e8f9f7	311	* @{
Anna Bridge	186:707f6e361f3e	312	*/
Anna Bridge	186:707f6e361f3e	313	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /!< No error /
Anna Bridge	186:707f6e361f3e	314	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error (problem of clocking,
Anna Bridge	186:707f6e361f3e	315	enable/disable, erroneous state, ...) */
Anna Bridge	186:707f6e361f3e	316	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /!< Overrun error /
Anna Bridge	186:707f6e361f3e	317	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /!< DMA transfer error /
<>	144:ef7eb2e8f9f7	318	/**
<>	144:ef7eb2e8f9f7	319	* @}
Anna Bridge	186:707f6e361f3e	320	*/
<>	144:ef7eb2e8f9f7	321
<>	144:ef7eb2e8f9f7	322	/** @defgroup ADC_TimeOut_Values ADC TimeOut Values
<>	144:ef7eb2e8f9f7	323	* @{
Anna Bridge	186:707f6e361f3e	324	*/
<>	144:ef7eb2e8f9f7	325
<>	144:ef7eb2e8f9f7	326	/* Fixed timeout values for ADC calibration, enable settling time, disable */
<>	144:ef7eb2e8f9f7	327	/* settling time. */
<>	144:ef7eb2e8f9f7	328	/* Values defined to be higher than worst cases: low clocks freq, */
<>	144:ef7eb2e8f9f7	329	/* maximum prescalers. */
<>	144:ef7eb2e8f9f7	330	/* Unit: ms */
<>	151:5eaa88a5bcc7	331	#define ADC_ENABLE_TIMEOUT 10U
<>	151:5eaa88a5bcc7	332	#define ADC_DISABLE_TIMEOUT 10U
<>	151:5eaa88a5bcc7	333	#define ADC_STOP_CONVERSION_TIMEOUT 10U
<>	144:ef7eb2e8f9f7	334
<>	144:ef7eb2e8f9f7	335	/* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */
<>	144:ef7eb2e8f9f7	336	/* the minimum number of CPU cycles to fulfill this delay */
<>	151:5eaa88a5bcc7	337	#define ADC_DELAY_10US_MIN_CPU_CYCLES 1800U
<>	144:ef7eb2e8f9f7	338	/**
<>	144:ef7eb2e8f9f7	339	* @}
<>	144:ef7eb2e8f9f7	340	*/
<>	144:ef7eb2e8f9f7	341
<>	144:ef7eb2e8f9f7	342	/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
<>	144:ef7eb2e8f9f7	343	* @{
<>	144:ef7eb2e8f9f7	344	*/
<>	151:5eaa88a5bcc7	345	#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /!< ADC Asynchronous clock mode divided by 1 /
<>	144:ef7eb2e8f9f7	346	#define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	347	#define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	348	#define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	349	#define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	350	#define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	351	#define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	352	#define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	353	#define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	354	#define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	355	#define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	356	#define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	357
<>	144:ef7eb2e8f9f7	358	#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1
<>	144:ef7eb2e8f9f7	359	This configuration must be enabled only if PCLK has a 50%
<>	144:ef7eb2e8f9f7	360	duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
<>	144:ef7eb2e8f9f7	361	must by 50% duty cycle)*/
<>	144:ef7eb2e8f9f7	362	#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /!< Synchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	363	#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /!< Synchronous clock mode divided by 4 /
<>	144:ef7eb2e8f9f7	364
<>	144:ef7eb2e8f9f7	365	/**
<>	144:ef7eb2e8f9f7	366	* @}
<>	144:ef7eb2e8f9f7	367	*/
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	/** @defgroup ADC_Resolution ADC Resolution
<>	144:ef7eb2e8f9f7	370	* @{
Anna Bridge	186:707f6e361f3e	371	*/
Anna Bridge	186:707f6e361f3e	372	#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /!< ADC 12-bit resolution /
Anna Bridge	186:707f6e361f3e	373	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /!< ADC 10-bit resolution /
Anna Bridge	186:707f6e361f3e	374	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /!< ADC 8-bit resolution /
Anna Bridge	186:707f6e361f3e	375	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /!< ADC 6-bit resolution /
<>	144:ef7eb2e8f9f7	376	/**
<>	144:ef7eb2e8f9f7	377	* @}
Anna Bridge	186:707f6e361f3e	378	*/
<>	144:ef7eb2e8f9f7	379
Anna Bridge	186:707f6e361f3e	380	/** @defgroup ADC_Data_align ADC conversion data alignment
<>	144:ef7eb2e8f9f7	381	* @{
Anna Bridge	186:707f6e361f3e	382	*/
<>	151:5eaa88a5bcc7	383	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	384	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
<>	144:ef7eb2e8f9f7	385	/**
<>	144:ef7eb2e8f9f7	386	* @}
Anna Bridge	186:707f6e361f3e	387	*/
<>	144:ef7eb2e8f9f7	388
Anna Bridge	186:707f6e361f3e	389	/** @defgroup ADC_regular_external_trigger_edge ADC External Trigger Source Edge for Regular Group
<>	144:ef7eb2e8f9f7	390	* @{
Anna Bridge	186:707f6e361f3e	391	*/
<>	151:5eaa88a5bcc7	392	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	393	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
<>	144:ef7eb2e8f9f7	394	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
<>	144:ef7eb2e8f9f7	395	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
<>	144:ef7eb2e8f9f7	396	/**
<>	144:ef7eb2e8f9f7	397	* @}
<>	144:ef7eb2e8f9f7	398	*/
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	/** @defgroup ADC_EOCSelection ADC EOC Selection
<>	144:ef7eb2e8f9f7	401	* @{
<>	144:ef7eb2e8f9f7	402	*/
<>	144:ef7eb2e8f9f7	403	#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
<>	144:ef7eb2e8f9f7	404	#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
<>	144:ef7eb2e8f9f7	405	#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC \| ADC_ISR_EOS)) /!< reserved for future use /
<>	144:ef7eb2e8f9f7	406	/**
<>	144:ef7eb2e8f9f7	407	* @}
<>	144:ef7eb2e8f9f7	408	*/
<>	144:ef7eb2e8f9f7	409
<>	144:ef7eb2e8f9f7	410	/** @defgroup ADC_Overrun ADC Overrun
<>	144:ef7eb2e8f9f7	411	* @{
<>	144:ef7eb2e8f9f7	412	*/
<>	151:5eaa88a5bcc7	413	#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	414	#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
<>	144:ef7eb2e8f9f7	415	/**
<>	144:ef7eb2e8f9f7	416	* @}
Anna Bridge	186:707f6e361f3e	417	*/
<>	144:ef7eb2e8f9f7	418
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	/** @defgroup ADC_rank ADC rank
<>	144:ef7eb2e8f9f7	421	* @{
Anna Bridge	186:707f6e361f3e	422	*/
<>	151:5eaa88a5bcc7	423	#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000U) /!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) /
<>	151:5eaa88a5bcc7	424	#define ADC_RANK_NONE ((uint32_t)0x00001001U) /!< Disable the selected rank (selected channel) from sequencer /
<>	144:ef7eb2e8f9f7	425	/**
<>	144:ef7eb2e8f9f7	426	* @}
<>	144:ef7eb2e8f9f7	427	*/
<>	144:ef7eb2e8f9f7	428
<>	144:ef7eb2e8f9f7	429
<>	144:ef7eb2e8f9f7	430	/** @defgroup ADC_channels ADC_Channels
<>	144:ef7eb2e8f9f7	431	* @{
<>	144:ef7eb2e8f9f7	432	*/
<>	144:ef7eb2e8f9f7	433	#define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0))
<>	144:ef7eb2e8f9f7	434	#define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) \| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	435	#define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) \| ADC_CFGR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	436	#define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)\| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	437	#define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)\| ADC_CFGR1_AWDCH_2)
<>	144:ef7eb2e8f9f7	438	#define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	439	#define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	440	#define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	441	#define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)\| ADC_CFGR1_AWDCH_3)
<>	144:ef7eb2e8f9f7	442	#define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	443	#define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	444	#define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_1\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	445	#define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2)
<>	144:ef7eb2e8f9f7	446	#define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	447	#define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	448	#define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	449	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
<>	144:ef7eb2e8f9f7	450	#define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)\| ADC_CFGR1_AWDCH_4)
<>	144:ef7eb2e8f9f7	451	#endif
<>	144:ef7eb2e8f9f7	452	#define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)\| ADC_CFGR1_AWDCH_4\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	453	#define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)\| ADC_CFGR1_AWDCH_4\| ADC_CFGR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	454
<>	144:ef7eb2e8f9f7	455	/* Internal channels */
<>	144:ef7eb2e8f9f7	456	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
<>	144:ef7eb2e8f9f7	457	#define ADC_CHANNEL_VLCD ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	458	#endif
<>	144:ef7eb2e8f9f7	459	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	460	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	461	/**
<>	144:ef7eb2e8f9f7	462	* @}
<>	144:ef7eb2e8f9f7	463	*/
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	/** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
<>	144:ef7eb2e8f9f7	466	* @{
<>	144:ef7eb2e8f9f7	467	*/
<>	151:5eaa88a5bcc7	468	#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFFU)
<>	151:5eaa88a5bcc7	469	#define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000U)
<>	144:ef7eb2e8f9f7	470	/**
<>	144:ef7eb2e8f9f7	471	* @}
<>	144:ef7eb2e8f9f7	472	*/
<>	144:ef7eb2e8f9f7	473
<>	144:ef7eb2e8f9f7	474	/** @defgroup ADC_sampling_times ADC Sampling Cycles
<>	144:ef7eb2e8f9f7	475	* @{
<>	144:ef7eb2e8f9f7	476	*/
<>	151:5eaa88a5bcc7	477	#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000U) /!< ADC sampling time 1.5 cycle /
Anna Bridge	186:707f6e361f3e	478	#define ADC_SAMPLETIME_3CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /!< ADC sampling time 3.5 CYCLES /
Anna Bridge	186:707f6e361f3e	479	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /!< ADC sampling time 7.5 CYCLES /
Anna Bridge	186:707f6e361f3e	480	#define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 \| ADC_SMPR_SMPR_0)) /!< ADC sampling time 12.5 CYCLES /
Anna Bridge	186:707f6e361f3e	481	#define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /!< ADC sampling time 19.5 CYCLES /
Anna Bridge	186:707f6e361f3e	482	#define ADC_SAMPLETIME_39CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 \| ADC_SMPR_SMPR_0)) /!< ADC sampling time 39.5 CYCLES /
Anna Bridge	186:707f6e361f3e	483	#define ADC_SAMPLETIME_79CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 \| ADC_SMPR_SMPR_1)) /!< ADC sampling time 79.5 CYCLES /
Anna Bridge	186:707f6e361f3e	484	#define ADC_SAMPLETIME_160CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /!< ADC sampling time 160.5 CYCLES /
<>	144:ef7eb2e8f9f7	485	/**
<>	144:ef7eb2e8f9f7	486	* @}
<>	144:ef7eb2e8f9f7	487	*/
<>	144:ef7eb2e8f9f7	488
<>	144:ef7eb2e8f9f7	489	/** @defgroup ADC_Scan_mode ADC Scan mode
<>	144:ef7eb2e8f9f7	490	* @{
<>	144:ef7eb2e8f9f7	491	*/
<>	144:ef7eb2e8f9f7	492	/* Note: Scan mode values must be compatible with other STM32 devices having */
<>	144:ef7eb2e8f9f7	493	/* a configurable sequencer. */
<>	144:ef7eb2e8f9f7	494	/* Scan direction setting values are defined by taking in account */
<>	144:ef7eb2e8f9f7	495	/* already defined values for other STM32 devices: */
<>	144:ef7eb2e8f9f7	496	/* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */
<>	144:ef7eb2e8f9f7	497	/* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */
<>	144:ef7eb2e8f9f7	498	/* Scan direction forward is considered as default setting equivalent */
<>	144:ef7eb2e8f9f7	499	/* to scan enable. */
<>	144:ef7eb2e8f9f7	500	/* Scan direction backward is considered as additional setting. */
<>	144:ef7eb2e8f9f7	501	/* In case of migration from another STM32 device, the user will be */
<>	144:ef7eb2e8f9f7	502	/* warned of change of setting choices with assert check. */
<>	151:5eaa88a5bcc7	503	#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001U) /!< Scan direction forward: from channel 0 to channel 18 /
<>	151:5eaa88a5bcc7	504	#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002U) /!< Scan direction backward: from channel 18 to channel 0 /
<>	144:ef7eb2e8f9f7	505
<>	144:ef7eb2e8f9f7	506	#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
<>	144:ef7eb2e8f9f7	507	/**
<>	144:ef7eb2e8f9f7	508	* @}
<>	144:ef7eb2e8f9f7	509	*/
<>	144:ef7eb2e8f9f7	510
<>	144:ef7eb2e8f9f7	511	/** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
<>	144:ef7eb2e8f9f7	512	* @{
<>	144:ef7eb2e8f9f7	513	*/
<>	144:ef7eb2e8f9f7	514
<>	151:5eaa88a5bcc7	515	#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000U) /!< ADC Oversampling ratio 2x /
<>	151:5eaa88a5bcc7	516	#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004U) /!< ADC Oversampling ratio 4x /
<>	151:5eaa88a5bcc7	517	#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008U) /!< ADC Oversampling ratio 8x /
<>	151:5eaa88a5bcc7	518	#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000CU) /!< ADC Oversampling ratio 16x /
<>	151:5eaa88a5bcc7	519	#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010U) /!< ADC Oversampling ratio 32x /
<>	151:5eaa88a5bcc7	520	#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014U) /!< ADC Oversampling ratio 64x /
<>	151:5eaa88a5bcc7	521	#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018U) /!< ADC Oversampling ratio 128x /
<>	151:5eaa88a5bcc7	522	#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001CU) /!< ADC Oversampling ratio 256x /
<>	144:ef7eb2e8f9f7	523	/**
<>	144:ef7eb2e8f9f7	524	* @}
<>	144:ef7eb2e8f9f7	525	*/
<>	144:ef7eb2e8f9f7	526
<>	144:ef7eb2e8f9f7	527	/** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
<>	144:ef7eb2e8f9f7	528	* @{
<>	144:ef7eb2e8f9f7	529	*/
<>	151:5eaa88a5bcc7	530	#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000U) /!< ADC No bit shift for oversampling /
<>	151:5eaa88a5bcc7	531	#define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020U) /!< ADC 1 bit shift for oversampling /
<>	151:5eaa88a5bcc7	532	#define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040U) /!< ADC 2 bits shift for oversampling /
<>	151:5eaa88a5bcc7	533	#define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060U) /!< ADC 3 bits shift for oversampling /
<>	151:5eaa88a5bcc7	534	#define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080U) /!< ADC 4 bits shift for oversampling /
<>	151:5eaa88a5bcc7	535	#define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0U) /!< ADC 5 bits shift for oversampling /
<>	151:5eaa88a5bcc7	536	#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0U) /!< ADC 6 bits shift for oversampling /
<>	151:5eaa88a5bcc7	537	#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0U) /!< ADC 7 bits shift for oversampling /
<>	151:5eaa88a5bcc7	538	#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100U) /!< ADC 8 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	539	/**
<>	144:ef7eb2e8f9f7	540	* @}
<>	144:ef7eb2e8f9f7	541	*/
<>	144:ef7eb2e8f9f7	542
<>	144:ef7eb2e8f9f7	543	/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
<>	144:ef7eb2e8f9f7	544	* @{
<>	144:ef7eb2e8f9f7	545	*/
<>	151:5eaa88a5bcc7	546	#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000U) /!< ADC No bit shift for oversampling /
<>	151:5eaa88a5bcc7	547	#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200U) /!< ADC No bit shift for oversampling /
<>	144:ef7eb2e8f9f7	548	/**
<>	144:ef7eb2e8f9f7	549	* @}
<>	144:ef7eb2e8f9f7	550	*/
<>	144:ef7eb2e8f9f7	551
<>	144:ef7eb2e8f9f7	552	/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
<>	144:ef7eb2e8f9f7	553	* @{
<>	144:ef7eb2e8f9f7	554	*/
<>	151:5eaa88a5bcc7	555	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000U)
<>	144:ef7eb2e8f9f7	556	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN))
<>	144:ef7eb2e8f9f7	557	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
<>	144:ef7eb2e8f9f7	558	/**
<>	144:ef7eb2e8f9f7	559	* @}
<>	144:ef7eb2e8f9f7	560	*/
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	/** @defgroup ADC_conversion_type ADC Conversion Group
<>	144:ef7eb2e8f9f7	563	* @{
<>	144:ef7eb2e8f9f7	564	*/
<>	144:ef7eb2e8f9f7	565	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS))
<>	144:ef7eb2e8f9f7	566	/**
<>	144:ef7eb2e8f9f7	567	* @}
<>	144:ef7eb2e8f9f7	568	*/
<>	144:ef7eb2e8f9f7	569
<>	144:ef7eb2e8f9f7	570	/** @defgroup ADC_Event_type ADC Event
<>	144:ef7eb2e8f9f7	571	* @{
Anna Bridge	186:707f6e361f3e	572	*/
<>	144:ef7eb2e8f9f7	573	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
<>	144:ef7eb2e8f9f7	574	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
<>	144:ef7eb2e8f9f7	575	/**
<>	144:ef7eb2e8f9f7	576	* @}
<>	144:ef7eb2e8f9f7	577	*/
<>	144:ef7eb2e8f9f7	578
<>	144:ef7eb2e8f9f7	579	/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
<>	144:ef7eb2e8f9f7	580	* @{
<>	144:ef7eb2e8f9f7	581	*/
<>	144:ef7eb2e8f9f7	582	#define ADC_IT_RDY ADC_IER_ADRDYIE /!< ADC Ready (ADRDY) interrupt source /
<>	144:ef7eb2e8f9f7	583	#define ADC_IT_EOSMP ADC_IER_EOSMPIE /!< ADC End of Sampling interrupt source /
<>	144:ef7eb2e8f9f7	584	#define ADC_IT_EOC ADC_IER_EOCIE /!< ADC End of Regular Conversion interrupt source /
<>	144:ef7eb2e8f9f7	585	#define ADC_IT_EOS ADC_IER_EOSEQIE /!< ADC End of Regular sequence of Conversions interrupt source /
<>	144:ef7eb2e8f9f7	586	#define ADC_IT_OVR ADC_IER_OVRIE /!< ADC overrun interrupt source /
<>	144:ef7eb2e8f9f7	587	#define ADC_IT_AWD ADC_IER_AWDIE /!< ADC Analog watchdog 1 interrupt source /
<>	144:ef7eb2e8f9f7	588	#define ADC_IT_EOCAL ADC_IER_EOCALIE /!< ADC End of Calibration interrupt source /
<>	144:ef7eb2e8f9f7	589	/**
<>	144:ef7eb2e8f9f7	590	* @}
Anna Bridge	186:707f6e361f3e	591	*/
<>	144:ef7eb2e8f9f7	592
Anna Bridge	186:707f6e361f3e	593	/** @defgroup ADC_flags_definition ADC flags definition
<>	144:ef7eb2e8f9f7	594	* @{
<>	144:ef7eb2e8f9f7	595	*/
Anna Bridge	186:707f6e361f3e	596	#define ADC_FLAG_RDY ADC_ISR_ADRDY /!< ADC Ready flag /
<>	144:ef7eb2e8f9f7	597	#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC End of Sampling flag /
<>	144:ef7eb2e8f9f7	598	#define ADC_FLAG_EOC ADC_ISR_EOC /!< ADC End of Regular Conversion flag /
<>	144:ef7eb2e8f9f7	599	#define ADC_FLAG_EOS ADC_ISR_EOSEQ /!< ADC End of Regular sequence of Conversions flag /
<>	144:ef7eb2e8f9f7	600	#define ADC_FLAG_OVR ADC_ISR_OVR /!< ADC overrun flag /
<>	144:ef7eb2e8f9f7	601	#define ADC_FLAG_AWD ADC_ISR_AWD /!< ADC Analog watchdog flag /
<>	144:ef7eb2e8f9f7	602	#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /!< ADC Enf Of Calibration flag /
<>	144:ef7eb2e8f9f7	603
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	#define ADC_FLAG_ALL (ADC_FLAG_RDY \| ADC_FLAG_EOSMP \| ADC_FLAG_EOC \| ADC_FLAG_EOS \| \
<>	144:ef7eb2e8f9f7	606	ADC_FLAG_OVR \| ADC_FLAG_AWD \| ADC_FLAG_EOCAL)
<>	144:ef7eb2e8f9f7	607	/**
<>	144:ef7eb2e8f9f7	608	* @}
<>	144:ef7eb2e8f9f7	609	*/
<>	144:ef7eb2e8f9f7	610
<>	144:ef7eb2e8f9f7	611	/**
<>	144:ef7eb2e8f9f7	612	* @}
<>	144:ef7eb2e8f9f7	613	*/
Anna Bridge	186:707f6e361f3e	614
Anna Bridge	186:707f6e361f3e	615
<>	144:ef7eb2e8f9f7	616	/* Exported macro ------------------------------------------------------------*/
Anna Bridge	186:707f6e361f3e	617
Anna Bridge	186:707f6e361f3e	618	/** @defgroup ADC_Exported_Macros ADC Exported Macros
<>	144:ef7eb2e8f9f7	619	* @{
<>	144:ef7eb2e8f9f7	620	*/
<>	144:ef7eb2e8f9f7	621	/** @brief Reset ADC handle state
<>	144:ef7eb2e8f9f7	622	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	623	* @retval None
<>	144:ef7eb2e8f9f7	624	*/
<>	144:ef7eb2e8f9f7	625	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<>	144:ef7eb2e8f9f7	626
<>	144:ef7eb2e8f9f7	627	/**
<>	144:ef7eb2e8f9f7	628	* @brief Enable the ADC peripheral
<>	144:ef7eb2e8f9f7	629	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	630	* @retval None
<>	144:ef7eb2e8f9f7	631	*/
<>	144:ef7eb2e8f9f7	632	#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= ADC_CR_ADEN)
<>	144:ef7eb2e8f9f7	633
<>	144:ef7eb2e8f9f7	634	/**
<>	144:ef7eb2e8f9f7	635	* @brief Verification of hardware constraints before ADC can be enabled
<>	144:ef7eb2e8f9f7	636	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	637	* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
<>	144:ef7eb2e8f9f7	638	*/
<>	144:ef7eb2e8f9f7	639	#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
<>	144:ef7eb2e8f9f7	640	(( ( ((__HANDLE__)->Instance->CR) & \
<>	144:ef7eb2e8f9f7	641	(ADC_CR_ADCAL \| ADC_CR_ADSTP \| ADC_CR_ADSTART \| \
<>	144:ef7eb2e8f9f7	642	ADC_CR_ADDIS \| ADC_CR_ADEN ) \
<>	144:ef7eb2e8f9f7	643	) == RESET \
<>	144:ef7eb2e8f9f7	644	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	645
<>	144:ef7eb2e8f9f7	646	/**
<>	144:ef7eb2e8f9f7	647	* @brief Disable the ADC peripheral
<>	144:ef7eb2e8f9f7	648	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	649	* @retval None
<>	144:ef7eb2e8f9f7	650	*/
<>	144:ef7eb2e8f9f7	651	#define __HAL_ADC_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	652	do{ \
<>	144:ef7eb2e8f9f7	653	(__HANDLE__)->Instance->CR \|= ADC_CR_ADDIS; \
<>	144:ef7eb2e8f9f7	654	__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP \| ADC_FLAG_RDY)); \
<>	144:ef7eb2e8f9f7	655	} while(0)
<>	144:ef7eb2e8f9f7	656
<>	144:ef7eb2e8f9f7	657	/**
<>	144:ef7eb2e8f9f7	658	* @brief Verification of hardware constraints before ADC can be disabled
<>	144:ef7eb2e8f9f7	659	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	660	* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
<>	144:ef7eb2e8f9f7	661	*/
<>	144:ef7eb2e8f9f7	662	#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
<>	144:ef7eb2e8f9f7	663	(( ( ((__HANDLE__)->Instance->CR) & \
<>	144:ef7eb2e8f9f7	664	(ADC_CR_ADSTART \| ADC_CR_ADEN)) == ADC_CR_ADEN \
<>	144:ef7eb2e8f9f7	665	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	666
<>	144:ef7eb2e8f9f7	667	/**
<>	144:ef7eb2e8f9f7	668	* @brief Verification of ADC state: enabled or disabled
<>	144:ef7eb2e8f9f7	669	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	670	* @retval SET (ADC enabled) or RESET (ADC disabled)
<>	144:ef7eb2e8f9f7	671	*/
<>	144:ef7eb2e8f9f7	672	#define ADC_IS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	673	(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN \| ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
<>	144:ef7eb2e8f9f7	674	((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
<>	144:ef7eb2e8f9f7	675	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	676
<>	144:ef7eb2e8f9f7	677	/**
<>	144:ef7eb2e8f9f7	678	* @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution.
<>	144:ef7eb2e8f9f7	679	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	680	* @retval None
<>	144:ef7eb2e8f9f7	681	*/
<>	144:ef7eb2e8f9f7	682	#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
<>	144:ef7eb2e8f9f7	683	/**
<>	144:ef7eb2e8f9f7	684	* @brief Test if conversion trigger of regular group is software start
<>	144:ef7eb2e8f9f7	685	* or external trigger.
<>	144:ef7eb2e8f9f7	686	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	687	* @retval SET (software start) or RESET (external trigger)
<>	144:ef7eb2e8f9f7	688	*/
<>	144:ef7eb2e8f9f7	689	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<>	144:ef7eb2e8f9f7	690	(((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
<>	144:ef7eb2e8f9f7	691
<>	144:ef7eb2e8f9f7	692
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	/**
<>	144:ef7eb2e8f9f7	695	* @brief Check if no conversion on going on regular group
<>	144:ef7eb2e8f9f7	696	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	697	* @retval SET (conversion is on going) or RESET (no conversion is on going)
<>	144:ef7eb2e8f9f7	698	*/
<>	144:ef7eb2e8f9f7	699	#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
<>	144:ef7eb2e8f9f7	700	(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
<>	144:ef7eb2e8f9f7	701	) ? RESET : SET)
Anna Bridge	186:707f6e361f3e	702
<>	144:ef7eb2e8f9f7	703	/**
<>	144:ef7eb2e8f9f7	704	* @brief Enable ADC continuous conversion mode.
<>	144:ef7eb2e8f9f7	705	* @param _CONTINUOUS_MODE_: Continuous mode.
<>	144:ef7eb2e8f9f7	706	* @retval None
<>	144:ef7eb2e8f9f7	707	*/
<>	151:5eaa88a5bcc7	708	#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
<>	144:ef7eb2e8f9f7	709
<>	144:ef7eb2e8f9f7	710	/**
<>	144:ef7eb2e8f9f7	711	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
<>	144:ef7eb2e8f9f7	712	* @param _SCAN_MODE_: Scan conversion mode.
<>	144:ef7eb2e8f9f7	713	* @retval None
<>	144:ef7eb2e8f9f7	714	*/
<>	144:ef7eb2e8f9f7	715	#define ADC_SCANDIR(_SCAN_MODE_) \
<>	144:ef7eb2e8f9f7	716	( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
<>	151:5eaa88a5bcc7	717	)? (ADC_CFGR1_SCANDIR) : (0x00000000U) \
<>	144:ef7eb2e8f9f7	718	)
<>	144:ef7eb2e8f9f7	719
<>	144:ef7eb2e8f9f7	720	/**
<>	144:ef7eb2e8f9f7	721	* @brief Configures the number of discontinuous conversions for the regular group channels.
<>	144:ef7eb2e8f9f7	722	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
<>	144:ef7eb2e8f9f7	723	* @retval None
<>	144:ef7eb2e8f9f7	724	*/
<>	151:5eaa88a5bcc7	725	#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
<>	144:ef7eb2e8f9f7	726
<>	144:ef7eb2e8f9f7	727	/**
<>	144:ef7eb2e8f9f7	728	* @brief Enable the ADC DMA continuous request.
<>	144:ef7eb2e8f9f7	729	* @param _DMAContReq_MODE_: DMA continuous request mode.
<>	144:ef7eb2e8f9f7	730	* @retval None
<>	144:ef7eb2e8f9f7	731	*/
<>	151:5eaa88a5bcc7	732	#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U)
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	/**
<>	144:ef7eb2e8f9f7	735	* @brief Enable the ADC Auto Delay.
<>	144:ef7eb2e8f9f7	736	* @param _AutoDelay_: Auto delay bit enable or disable.
<>	144:ef7eb2e8f9f7	737	* @retval None
<>	144:ef7eb2e8f9f7	738	*/
<>	151:5eaa88a5bcc7	739	#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U)
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/**
<>	144:ef7eb2e8f9f7	742	* @brief Enable the ADC LowPowerAutoPowerOff.
<>	144:ef7eb2e8f9f7	743	* @param _AUTOFF_: AutoOff bit enable or disable.
<>	144:ef7eb2e8f9f7	744	* @retval None
<>	144:ef7eb2e8f9f7	745	*/
<>	151:5eaa88a5bcc7	746	#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U)
Anna Bridge	186:707f6e361f3e	747
<>	144:ef7eb2e8f9f7	748	/**
<>	144:ef7eb2e8f9f7	749	* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
<>	144:ef7eb2e8f9f7	750	* @param _Threshold_: Threshold value
<>	144:ef7eb2e8f9f7	751	* @retval None
<>	144:ef7eb2e8f9f7	752	*/
<>	151:5eaa88a5bcc7	753	#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
<>	144:ef7eb2e8f9f7	754
<>	144:ef7eb2e8f9f7	755	/**
<>	144:ef7eb2e8f9f7	756	* @brief Enable the ADC Low Frequency mode.
<>	144:ef7eb2e8f9f7	757	* @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
<>	144:ef7eb2e8f9f7	758	* @retval None
<>	144:ef7eb2e8f9f7	759	*/
<>	151:5eaa88a5bcc7	760	#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U)
Anna Bridge	186:707f6e361f3e	761
<>	144:ef7eb2e8f9f7	762	/**
<>	144:ef7eb2e8f9f7	763	* @brief Shift the offset in function of the selected ADC resolution.
<>	144:ef7eb2e8f9f7	764	* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
<>	144:ef7eb2e8f9f7	765	* If resolution 12 bits, no shift.
<>	144:ef7eb2e8f9f7	766	* If resolution 10 bits, shift of 2 ranks on the right.
<>	144:ef7eb2e8f9f7	767	* If resolution 8 bits, shift of 4 ranks on the right.
<>	144:ef7eb2e8f9f7	768	* If resolution 6 bits, shift of 6 ranks on the right.
<>	144:ef7eb2e8f9f7	769	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
<>	144:ef7eb2e8f9f7	770	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	771	* @param _Offset_: Value to be shifted
<>	144:ef7eb2e8f9f7	772	* @retval None
<>	144:ef7eb2e8f9f7	773	*/
<>	144:ef7eb2e8f9f7	774	#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
<>	151:5eaa88a5bcc7	775	((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U))
<>	144:ef7eb2e8f9f7	776
<>	144:ef7eb2e8f9f7	777	/**
<>	144:ef7eb2e8f9f7	778	* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
<>	144:ef7eb2e8f9f7	779	* Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0
<>	144:ef7eb2e8f9f7	780	* If resolution 12 bits, no shift.
<>	144:ef7eb2e8f9f7	781	* If resolution 10 bits, shift of 2 ranks on the right.
<>	144:ef7eb2e8f9f7	782	* If resolution 8 bits, shift of 4 ranks on the right.
<>	144:ef7eb2e8f9f7	783	* If resolution 6 bits, shift of 6 ranks on the right.
<>	144:ef7eb2e8f9f7	784	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
<>	144:ef7eb2e8f9f7	785	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	786	* @param _Threshold_: Value to be shifted
<>	144:ef7eb2e8f9f7	787	* @retval None
<>	144:ef7eb2e8f9f7	788	*/
<>	144:ef7eb2e8f9f7	789	#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
<>	151:5eaa88a5bcc7	790	((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
Anna Bridge	186:707f6e361f3e	791
<>	144:ef7eb2e8f9f7	792	/**
<>	144:ef7eb2e8f9f7	793	* @brief Shift the value on the left, less significant are set to 0.
<>	144:ef7eb2e8f9f7	794	* @param _Value_: Value to be shifted
<>	144:ef7eb2e8f9f7	795	* @param _Shift_: Number of shift to be done
<>	144:ef7eb2e8f9f7	796	* @retval None
<>	144:ef7eb2e8f9f7	797	*/
<>	144:ef7eb2e8f9f7	798	#define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_))
<>	144:ef7eb2e8f9f7	799
<>	144:ef7eb2e8f9f7	800
<>	144:ef7eb2e8f9f7	801	/**
<>	144:ef7eb2e8f9f7	802	* @brief Enable the ADC end of conversion interrupt.
<>	144:ef7eb2e8f9f7	803	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	804	* @param __INTERRUPT__: ADC Interrupt.
<>	144:ef7eb2e8f9f7	805	* @retval None
<>	144:ef7eb2e8f9f7	806	*/
<>	144:ef7eb2e8f9f7	807	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	808	(((__HANDLE__)->Instance->IER) \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	809
<>	144:ef7eb2e8f9f7	810	/**
<>	144:ef7eb2e8f9f7	811	* @brief Disable the ADC end of conversion interrupt.
<>	144:ef7eb2e8f9f7	812	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	813	* @param __INTERRUPT__: ADC interrupt.
<>	144:ef7eb2e8f9f7	814	* @retval None
<>	144:ef7eb2e8f9f7	815	*/
<>	144:ef7eb2e8f9f7	816	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	817	(((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	818
<>	144:ef7eb2e8f9f7	819	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	820	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	821	* @param __INTERRUPT__: ADC interrupt source to check
<>	144:ef7eb2e8f9f7	822	* @arg ...
<>	144:ef7eb2e8f9f7	823	* @arg ...
<>	144:ef7eb2e8f9f7	824	* @retval State of interruption (TRUE or FALSE)
<>	144:ef7eb2e8f9f7	825	*/
<>	144:ef7eb2e8f9f7	826	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	827	(((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829	/**
<>	144:ef7eb2e8f9f7	830	* @brief Clear the ADC's pending flags
<>	144:ef7eb2e8f9f7	831	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	832	* @param __FLAG__: ADC flag.
<>	144:ef7eb2e8f9f7	833	* @retval None
<>	144:ef7eb2e8f9f7	834	*/
<>	144:ef7eb2e8f9f7	835	/* Note: bit cleared bit by writing 1 */
<>	144:ef7eb2e8f9f7	836	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<>	144:ef7eb2e8f9f7	837	(((__HANDLE__)->Instance->ISR) = (__FLAG__))
<>	144:ef7eb2e8f9f7	838
<>	144:ef7eb2e8f9f7	839	/**
<>	144:ef7eb2e8f9f7	840	* @brief Get the selected ADC's flag status.
<>	144:ef7eb2e8f9f7	841	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	842	* @param __FLAG__: ADC flag.
<>	144:ef7eb2e8f9f7	843	* @retval None
<>	144:ef7eb2e8f9f7	844	*/
<>	144:ef7eb2e8f9f7	845	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
<>	144:ef7eb2e8f9f7	846	((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	847
<>	144:ef7eb2e8f9f7	848
<>	144:ef7eb2e8f9f7	849	/**
<>	144:ef7eb2e8f9f7	850	* @brief Simultaneously clears and sets specific bits of the handle State
<>	144:ef7eb2e8f9f7	851	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<>	144:ef7eb2e8f9f7	852	* the first parameter is the ADC handle State, the second parameter is the
<>	144:ef7eb2e8f9f7	853	* bit field to clear, the third and last parameter is the bit field to set.
<>	144:ef7eb2e8f9f7	854	* @retval None
<>	144:ef7eb2e8f9f7	855	*/
<>	144:ef7eb2e8f9f7	856	#define ADC_STATE_CLR_SET MODIFY_REG
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	/**
<>	144:ef7eb2e8f9f7	859	* @brief Clear ADC error code (set it to error code: "no error")
<>	144:ef7eb2e8f9f7	860	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	861	* @retval None
<>	144:ef7eb2e8f9f7	862	*/
<>	144:ef7eb2e8f9f7	863	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	864	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<>	144:ef7eb2e8f9f7	865
<>	144:ef7eb2e8f9f7	866
<>	144:ef7eb2e8f9f7	867	/**
<>	144:ef7eb2e8f9f7	868	* @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
<>	144:ef7eb2e8f9f7	869	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	870	* @retval None
<>	144:ef7eb2e8f9f7	871	*/
<>	144:ef7eb2e8f9f7	872
<>	144:ef7eb2e8f9f7	873	#define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	874	do{ \
<>	144:ef7eb2e8f9f7	875	if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	876	(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	877	(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \
<>	144:ef7eb2e8f9f7	878	{ \
<>	144:ef7eb2e8f9f7	879	(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
<>	144:ef7eb2e8f9f7	880	(__HANDLE__)->Instance->CFGR2 \|= (__HANDLE__)->Init.ClockPrescaler; \
<>	144:ef7eb2e8f9f7	881	} \
<>	144:ef7eb2e8f9f7	882	else \
<>	144:ef7eb2e8f9f7	883	{ \
<>	144:ef7eb2e8f9f7	884	/* CKMOD bits must be reset */ \
<>	144:ef7eb2e8f9f7	885	(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
<>	144:ef7eb2e8f9f7	886	ADC->CCR &= ~(ADC_CCR_PRESC); \
<>	144:ef7eb2e8f9f7	887	ADC->CCR \|= (__HANDLE__)->Init.ClockPrescaler; \
<>	144:ef7eb2e8f9f7	888	} \
<>	144:ef7eb2e8f9f7	889	} while(0)
<>	144:ef7eb2e8f9f7	890
<>	144:ef7eb2e8f9f7	891
<>	144:ef7eb2e8f9f7	892	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) \|\|\
<>	144:ef7eb2e8f9f7	893	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\|\
<>	144:ef7eb2e8f9f7	894	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\|\
<>	144:ef7eb2e8f9f7	895	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) \|\|\
<>	144:ef7eb2e8f9f7	896	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) \|\|\
<>	144:ef7eb2e8f9f7	897	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) \|\|\
<>	144:ef7eb2e8f9f7	898	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) \|\|\
<>	144:ef7eb2e8f9f7	899	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) \|\|\
<>	144:ef7eb2e8f9f7	900	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) \|\|\
<>	144:ef7eb2e8f9f7	901	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) \|\|\
<>	144:ef7eb2e8f9f7	902	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) \|\|\
<>	144:ef7eb2e8f9f7	903	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) \|\|\
<>	144:ef7eb2e8f9f7	904	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) \|\|\
<>	144:ef7eb2e8f9f7	905	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) \|\|\
<>	144:ef7eb2e8f9f7	906	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) \|\|\
<>	144:ef7eb2e8f9f7	907	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) \|\| \
<>	144:ef7eb2e8f9f7	910	((RESOLUTION) == ADC_RESOLUTION_10B) \|\| \
<>	144:ef7eb2e8f9f7	911	((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
<>	144:ef7eb2e8f9f7	912	((RESOLUTION) == ADC_RESOLUTION_6B))
<>	144:ef7eb2e8f9f7	913
<>	144:ef7eb2e8f9f7	914	#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
<>	144:ef7eb2e8f9f7	915	((RESOLUTION) == ADC_RESOLUTION_6B))
<>	144:ef7eb2e8f9f7	916
<>	144:ef7eb2e8f9f7	917	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
<>	144:ef7eb2e8f9f7	918	((ALIGN) == ADC_DATAALIGN_LEFT))
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	921	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
<>	144:ef7eb2e8f9f7	922	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	923	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
<>	144:ef7eb2e8f9f7	924
<>	144:ef7eb2e8f9f7	925	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) \|\| \
<>	144:ef7eb2e8f9f7	926	((EOC_SELECTION) == ADC_EOC_SEQ_CONV) \|\| \
<>	144:ef7eb2e8f9f7	927	((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
<>	144:ef7eb2e8f9f7	928
<>	144:ef7eb2e8f9f7	929	#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) \|\| \
<>	144:ef7eb2e8f9f7	930	((OVR) == ADC_OVR_DATA_OVERWRITTEN))
<>	144:ef7eb2e8f9f7	931
<>	144:ef7eb2e8f9f7	932	#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) \|\| \
<>	144:ef7eb2e8f9f7	933	((WATCHDOG) == ADC_RANK_NONE))
<>	144:ef7eb2e8f9f7	934
<>	144:ef7eb2e8f9f7	935	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
<>	144:ef7eb2e8f9f7	936	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
<>	144:ef7eb2e8f9f7	937	((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	938	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	939	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	940	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	941	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	942	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	943	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	944	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	945	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	946	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	947	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	948	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	949	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	950	((CHANNEL) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	951	((CHANNEL) == ADC_CHANNEL_15) \|\| \
<>	144:ef7eb2e8f9f7	952	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	953	((CHANNEL) == ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	954	((CHANNEL) == ADC_CHANNEL_VLCD))
<>	144:ef7eb2e8f9f7	955	#else
<>	144:ef7eb2e8f9f7	956	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
<>	144:ef7eb2e8f9f7	957	((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	958	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	959	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	960	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	961	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	962	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	963	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	964	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	965	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	966	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	967	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	968	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	969	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	970	((CHANNEL) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	971	((CHANNEL) == ADC_CHANNEL_15) \|\| \
<>	144:ef7eb2e8f9f7	972	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	973	((CHANNEL) == ADC_CHANNEL_VREFINT))
<>	144:ef7eb2e8f9f7	974	#endif
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) \|\| \
Anna Bridge	186:707f6e361f3e	977	((TIME) == ADC_SAMPLETIME_3CYCLES_5 ) \|\| \
<>	144:ef7eb2e8f9f7	978	((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) \|\| \
Anna Bridge	186:707f6e361f3e	979	((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) \|\| \
Anna Bridge	186:707f6e361f3e	980	((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) \|\| \
Anna Bridge	186:707f6e361f3e	981	((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) \|\| \
Anna Bridge	186:707f6e361f3e	982	((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) \|\| \
Anna Bridge	186:707f6e361f3e	983	((TIME) == ADC_SAMPLETIME_160CYCLES_5))
<>	144:ef7eb2e8f9f7	984
<>	144:ef7eb2e8f9f7	985	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) \|\| \
<>	144:ef7eb2e8f9f7	986	((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
<>	144:ef7eb2e8f9f7	987
<>	144:ef7eb2e8f9f7	988	#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) \|\| \
<>	144:ef7eb2e8f9f7	989	((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) \|\| \
<>	144:ef7eb2e8f9f7	990	((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) \|\| \
<>	144:ef7eb2e8f9f7	991	((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) \|\| \
<>	144:ef7eb2e8f9f7	992	((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) \|\| \
<>	144:ef7eb2e8f9f7	993	((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) \|\| \
<>	144:ef7eb2e8f9f7	994	((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) \|\| \
<>	144:ef7eb2e8f9f7	995	((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
<>	144:ef7eb2e8f9f7	996
<>	144:ef7eb2e8f9f7	997	#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) \|\| \
<>	144:ef7eb2e8f9f7	998	((SHIFT) == ADC_RIGHTBITSHIFT_1 ) \|\| \
<>	144:ef7eb2e8f9f7	999	((SHIFT) == ADC_RIGHTBITSHIFT_2 ) \|\| \
<>	144:ef7eb2e8f9f7	1000	((SHIFT) == ADC_RIGHTBITSHIFT_3 ) \|\| \
<>	144:ef7eb2e8f9f7	1001	((SHIFT) == ADC_RIGHTBITSHIFT_4 ) \|\| \
<>	144:ef7eb2e8f9f7	1002	((SHIFT) == ADC_RIGHTBITSHIFT_5 ) \|\| \
<>	144:ef7eb2e8f9f7	1003	((SHIFT) == ADC_RIGHTBITSHIFT_6 ) \|\| \
<>	144:ef7eb2e8f9f7	1004	((SHIFT) == ADC_RIGHTBITSHIFT_7 ) \|\| \
<>	144:ef7eb2e8f9f7	1005	((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
<>	144:ef7eb2e8f9f7	1006
<>	144:ef7eb2e8f9f7	1007	#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	1008	((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
<>	144:ef7eb2e8f9f7	1009
<>	144:ef7eb2e8f9f7	1010	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) \|\| \
<>	144:ef7eb2e8f9f7	1011	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
<>	144:ef7eb2e8f9f7	1012	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
<>	144:ef7eb2e8f9f7	1013
<>	144:ef7eb2e8f9f7	1014	#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
<>	144:ef7eb2e8f9f7	1015
<>	144:ef7eb2e8f9f7	1016	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	1017	((EVENT) == ADC_OVR_EVENT))
<>	144:ef7eb2e8f9f7	1018
<>	144:ef7eb2e8f9f7	1019
<>	144:ef7eb2e8f9f7	1020	/** @defgroup ADC_range_verification ADC Range Verification
<>	144:ef7eb2e8f9f7	1021	* in function of ADC resolution selected (12, 10, 8 or 6 bits)
<>	144:ef7eb2e8f9f7	1022	* @{
Anna Bridge	186:707f6e361f3e	1023	*/
<>	144:ef7eb2e8f9f7	1024	#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
<>	151:5eaa88a5bcc7	1025	((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) \|\| \
<>	151:5eaa88a5bcc7	1026	(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) \|\| \
<>	151:5eaa88a5bcc7	1027	(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) \|\| \
<>	151:5eaa88a5bcc7	1028	(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
<>	144:ef7eb2e8f9f7	1029	/**
<>	144:ef7eb2e8f9f7	1030	* @}
Anna Bridge	186:707f6e361f3e	1031	*/
<>	144:ef7eb2e8f9f7	1032
<>	144:ef7eb2e8f9f7	1033	/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
<>	144:ef7eb2e8f9f7	1034	* @{
Anna Bridge	186:707f6e361f3e	1035	*/
<>	151:5eaa88a5bcc7	1036	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
<>	144:ef7eb2e8f9f7	1037	/**
<>	144:ef7eb2e8f9f7	1038	* @}
<>	144:ef7eb2e8f9f7	1039	*/
Anna Bridge	186:707f6e361f3e	1040
Anna Bridge	186:707f6e361f3e	1041	/**
<>	144:ef7eb2e8f9f7	1042	* @}
<>	144:ef7eb2e8f9f7	1043	*/
Anna Bridge	186:707f6e361f3e	1044
Anna Bridge	186:707f6e361f3e	1045	/* Include ADC HAL Extended module */
<>	144:ef7eb2e8f9f7	1046	#include "stm32l0xx_hal_adc_ex.h"
Anna Bridge	186:707f6e361f3e	1047
Anna Bridge	186:707f6e361f3e	1048	/* Exported functions --------------------------------------------------------*/
Anna Bridge	186:707f6e361f3e	1049	/** @addtogroup ADC_Exported_Functions
<>	144:ef7eb2e8f9f7	1050	* @{
<>	144:ef7eb2e8f9f7	1051	*/
Anna Bridge	186:707f6e361f3e	1052
Anna Bridge	186:707f6e361f3e	1053	/** @addtogroup ADC_Exported_Functions_Group1
Anna Bridge	186:707f6e361f3e	1054	* @brief Initialization and Configuration functions
Anna Bridge	186:707f6e361f3e	1055	* @{
Anna Bridge	186:707f6e361f3e	1056	*/
Anna Bridge	186:707f6e361f3e	1057	/* Initialization and de-initialization functions ****************************/
<>	144:ef7eb2e8f9f7	1058	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1059	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	1060	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1061	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1062	/**
<>	144:ef7eb2e8f9f7	1063	* @}
Anna Bridge	186:707f6e361f3e	1064	*/
<>	144:ef7eb2e8f9f7	1065
Anna Bridge	186:707f6e361f3e	1066	/** @addtogroup ADC_Exported_Functions_Group2
Anna Bridge	186:707f6e361f3e	1067	* @brief IO operation functions
<>	144:ef7eb2e8f9f7	1068	* @{
<>	144:ef7eb2e8f9f7	1069	*/
Anna Bridge	186:707f6e361f3e	1070	/* IO operation functions *****************************************************/
Anna Bridge	186:707f6e361f3e	1071
<>	144:ef7eb2e8f9f7	1072	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1073	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1074	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
Anna Bridge	186:707f6e361f3e	1075	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1076	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
Anna Bridge	186:707f6e361f3e	1077
<>	144:ef7eb2e8f9f7	1078	/* Non-blocking mode: Interruption */
<>	144:ef7eb2e8f9f7	1079	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1080	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
Anna Bridge	186:707f6e361f3e	1081
<>	144:ef7eb2e8f9f7	1082	/* Non-blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1083	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
<>	144:ef7eb2e8f9f7	1084	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
Anna Bridge	186:707f6e361f3e	1085
<>	144:ef7eb2e8f9f7	1086	/* ADC retrieve conversion value intended to be used with polling or interruption */
<>	144:ef7eb2e8f9f7	1087	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
Anna Bridge	186:707f6e361f3e	1088
<>	144:ef7eb2e8f9f7	1089	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
<>	144:ef7eb2e8f9f7	1090	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1091	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1092	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1093	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1094	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	1095	/**
<>	144:ef7eb2e8f9f7	1096	* @}
Anna Bridge	186:707f6e361f3e	1097	*/
<>	144:ef7eb2e8f9f7	1098
Anna Bridge	186:707f6e361f3e	1099	/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
Anna Bridge	186:707f6e361f3e	1100	* @brief Peripheral Control functions
Anna Bridge	186:707f6e361f3e	1101	* @{
Anna Bridge	186:707f6e361f3e	1102	*/
<>	144:ef7eb2e8f9f7	1103	/* Peripheral Control functions ***********************************************/
<>	144:ef7eb2e8f9f7	1104	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
<>	144:ef7eb2e8f9f7	1105	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
<>	144:ef7eb2e8f9f7	1106	/**
<>	144:ef7eb2e8f9f7	1107	* @}
Anna Bridge	186:707f6e361f3e	1108	*/
<>	144:ef7eb2e8f9f7	1109
<>	144:ef7eb2e8f9f7	1110	/* Peripheral State functions *************************************************/
Anna Bridge	186:707f6e361f3e	1111	/** @addtogroup ADC_Exported_Functions_Group4
<>	144:ef7eb2e8f9f7	1112	* @{
<>	144:ef7eb2e8f9f7	1113	*/
<>	144:ef7eb2e8f9f7	1114	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1115	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	1116	/**
<>	144:ef7eb2e8f9f7	1117	* @}
Anna Bridge	186:707f6e361f3e	1118	*/
<>	144:ef7eb2e8f9f7	1119
<>	144:ef7eb2e8f9f7	1120
<>	144:ef7eb2e8f9f7	1121	/**
<>	144:ef7eb2e8f9f7	1122	* @}
Anna Bridge	186:707f6e361f3e	1123	*/
<>	144:ef7eb2e8f9f7	1124
<>	144:ef7eb2e8f9f7	1125	/**
<>	144:ef7eb2e8f9f7	1126	* @}
<>	144:ef7eb2e8f9f7	1127	*/
<>	144:ef7eb2e8f9f7	1128
<>	144:ef7eb2e8f9f7	1129	/**
<>	144:ef7eb2e8f9f7	1130	* @}
<>	144:ef7eb2e8f9f7	1131	*/
<>	144:ef7eb2e8f9f7	1132
<>	144:ef7eb2e8f9f7	1133	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1134	}
<>	144:ef7eb2e8f9f7	1135	#endif
<>	144:ef7eb2e8f9f7	1136
<>	144:ef7eb2e8f9f7	1137
Anna Bridge	186:707f6e361f3e	1138	#endif /__STM32L0xx_HAL_ADC_H /
<>	144:ef7eb2e8f9f7	1139
<>	144:ef7eb2e8f9f7	1140	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/