mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief This file contains all the functions prototypes for the HAL
<> 144:ef7eb2e8f9f7 6 * module driver.
<> 144:ef7eb2e8f9f7 7 ******************************************************************************
<> 144:ef7eb2e8f9f7 8 * @attention
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 13 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 14 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 15 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 18 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 20 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 21 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 33 *
<> 144:ef7eb2e8f9f7 34 ******************************************************************************
<> 144:ef7eb2e8f9f7 35 */
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 38 #ifndef __STM32L0xx_HAL_H
<> 144:ef7eb2e8f9f7 39 #define __STM32L0xx_HAL_H
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 42 extern "C" {
<> 144:ef7eb2e8f9f7 43 #endif
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 46 #include "stm32l0xx_hal_conf.h"
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @defgroup HAL HAL
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55 /** @defgroup HAL_Exported_Constants HAL Exported Constants
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup SYSCFG_BootMode Boot Mode
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 151:5eaa88a5bcc7 62 #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 63 #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0)
<> 144:ef7eb2e8f9f7 64 #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE)
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /**
<> 144:ef7eb2e8f9f7 67 * @}
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration
<> 144:ef7eb2e8f9f7 71 * @{
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73 #define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP
<> 144:ef7eb2e8f9f7 74 #define DBGMCU_STOP DBGMCU_CR_DBG_STOP
<> 144:ef7eb2e8f9f7 75 #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
<> 151:5eaa88a5bcc7 76 #define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U))
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /**
<> 144:ef7eb2e8f9f7 80 * @}
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #if defined (LCD_BASE) /* STM32L0x3xx only */
<> 144:ef7eb2e8f9f7 84 /** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors
<> 144:ef7eb2e8f9f7 85 * @{
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 #define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */
<> 144:ef7eb2e8f9f7 88 #define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */
<> 144:ef7eb2e8f9f7 89 #define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */
<> 151:5eaa88a5bcc7 90 #define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */
<> 144:ef7eb2e8f9f7 91 #if defined (SYSCFG_CFGR2_CAPA_3)
<> 151:5eaa88a5bcc7 92 #define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */
<> 144:ef7eb2e8f9f7 93 #endif
<> 144:ef7eb2e8f9f7 94 #if defined (SYSCFG_CFGR2_CAPA_4)
<> 144:ef7eb2e8f9f7 95 #define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */
<> 144:ef7eb2e8f9f7 96 #endif
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /**
<> 144:ef7eb2e8f9f7 99 * @}
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 #endif
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 151:5eaa88a5bcc7 106 #define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000U) /* no pad connected */
<> 144:ef7eb2e8f9f7 107 #define SYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */
<> 144:ef7eb2e8f9f7 108 #define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */
<> 144:ef7eb2e8f9f7 109 #define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || \
<> 144:ef7eb2e8f9f7 112 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || \
<> 144:ef7eb2e8f9f7 113 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || \
<> 144:ef7eb2e8f9f7 114 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1))
<> 144:ef7eb2e8f9f7 115 /**
<> 144:ef7eb2e8f9f7 116 * @}
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 #define SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 #define IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY))
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133 /** @brief Fast mode Plus driving capability on a specific GPIO
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135 #if defined (SYSCFG_CFGR2_I2C_PB6_FMP)
<> 144:ef7eb2e8f9f7 136 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */
<> 144:ef7eb2e8f9f7 137 #endif
<> 144:ef7eb2e8f9f7 138 #if defined (SYSCFG_CFGR2_I2C_PB7_FMP)
<> 144:ef7eb2e8f9f7 139 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */
<> 144:ef7eb2e8f9f7 140 #endif
<> 144:ef7eb2e8f9f7 141 #if defined (SYSCFG_CFGR2_I2C_PB8_FMP)
<> 144:ef7eb2e8f9f7 142 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */
<> 144:ef7eb2e8f9f7 143 #endif
<> 144:ef7eb2e8f9f7 144 #if defined (SYSCFG_CFGR2_I2C_PB9_FMP)
<> 144:ef7eb2e8f9f7 145 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */
<> 144:ef7eb2e8f9f7 146 #endif
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || \
<> 144:ef7eb2e8f9f7 149 (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || \
<> 144:ef7eb2e8f9f7 150 (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || \
<> 144:ef7eb2e8f9f7 151 (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) )
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @}
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155 /**
<> 144:ef7eb2e8f9f7 156 * @}
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @brief Freeze/Unfreeze Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @brief TIM2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 170 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 171 #endif
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @brief TIM3 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 178 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 179 #endif
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 182 /**
<> 144:ef7eb2e8f9f7 183 * @brief TIM6 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 186 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 187 #endif
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @brief TIM7 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 194 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 195 #endif
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 144:ef7eb2e8f9f7 198 /**
<> 144:ef7eb2e8f9f7 199 * @brief RTC Peripherals Debug mode
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 144:ef7eb2e8f9f7 202 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 144:ef7eb2e8f9f7 203 #endif
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief WWDG Peripherals Debug mode
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 210 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 211 #endif
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @brief IWDG Peripherals Debug mode
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 218 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 219 #endif
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP)
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @brief I2C1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
<> 144:ef7eb2e8f9f7 226 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
<> 144:ef7eb2e8f9f7 227 #endif
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP)
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @brief I2C2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
<> 144:ef7eb2e8f9f7 234 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
<> 144:ef7eb2e8f9f7 235 #endif
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP)
<> 144:ef7eb2e8f9f7 238 /**
<> 144:ef7eb2e8f9f7 239 * @brief I2C3 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
<> 144:ef7eb2e8f9f7 242 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
<> 144:ef7eb2e8f9f7 243 #endif
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 #if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
<> 144:ef7eb2e8f9f7 246 /**
<> 144:ef7eb2e8f9f7 247 * @brief LPTIMER Peripherals Debug mode
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249 #define __HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
<> 144:ef7eb2e8f9f7 250 #define __HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
<> 144:ef7eb2e8f9f7 251 #endif
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 #if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP)
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @brief TIM22 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 #define __HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)
<> 144:ef7eb2e8f9f7 258 #define __HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)
<> 144:ef7eb2e8f9f7 259 #endif
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 #if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP)
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief TIM21 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 #define __HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)
<> 144:ef7eb2e8f9f7 266 #define __HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)
<> 144:ef7eb2e8f9f7 267 #endif
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /** @brief Main Flash memory mapped at 0x00000000
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /** @brief System Flash memory mapped at 0x00000000
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /** @brief Embedded SRAM mapped at 0x00000000
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1)
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /** @brief Configuration of the DBG Low Power mode.
<> 144:ef7eb2e8f9f7 283 * @param __DBGLPMODE__: bit field to indicate in wich Low Power mode DBG is still active.
<> 144:ef7eb2e8f9f7 284 * This parameter can be a value of
<> 144:ef7eb2e8f9f7 285 * - DBGMCU_SLEEP
<> 144:ef7eb2e8f9f7 286 * - DBGMCU_STOP
<> 144:ef7eb2e8f9f7 287 * - DBGMCU_STANDBY
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 #define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \
<> 144:ef7eb2e8f9f7 290 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \
<> 144:ef7eb2e8f9f7 291 } while (0)
<> 151:5eaa88a5bcc7 292
<> 151:5eaa88a5bcc7 293 #if defined (LCD_BASE) /* STM32L0x3xx only */
<> 151:5eaa88a5bcc7 294
<> 151:5eaa88a5bcc7 295 /** @brief Macro to configure the VLCD Decoupling capacitance connection.
<> 151:5eaa88a5bcc7 296 *
<> 151:5eaa88a5bcc7 297 * @param __SYSCFG_VLCD_CAPA__: specifies the decoupling of LCD capacitance for rails connection on GPIO.
<> 151:5eaa88a5bcc7 298 * This parameter can be a combination of following values (when available):
<> 151:5eaa88a5bcc7 299 * @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2
<> 151:5eaa88a5bcc7 300 * @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12
<> 151:5eaa88a5bcc7 301 * @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0
<> 151:5eaa88a5bcc7 302 * @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11
<> 151:5eaa88a5bcc7 303 * @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
<> 151:5eaa88a5bcc7 304 * @retval None
<> 151:5eaa88a5bcc7 305 */
<> 151:5eaa88a5bcc7 306 #define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \
<> 151:5eaa88a5bcc7 307 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__))
<> 151:5eaa88a5bcc7 308
<> 151:5eaa88a5bcc7 309 /**
<> 151:5eaa88a5bcc7 310 * @brief Returns the decoupling of LCD capacitance configured by user.
<> 151:5eaa88a5bcc7 311 * @retval The LCD capacitance connection as configured by user. The returned can be a combination of :
<> 151:5eaa88a5bcc7 312 * SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2
<> 151:5eaa88a5bcc7 313 * SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12
<> 151:5eaa88a5bcc7 314 * SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0
<> 151:5eaa88a5bcc7 315 * SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11
<> 151:5eaa88a5bcc7 316 * SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
<> 151:5eaa88a5bcc7 317 */
<> 151:5eaa88a5bcc7 318 #define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA)
<> 151:5eaa88a5bcc7 319
<> 151:5eaa88a5bcc7 320 #endif
<> 151:5eaa88a5bcc7 321
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @brief Returns the boot mode as configured by user.
<> 144:ef7eb2e8f9f7 324 * @retval The boot mode as configured by user. The returned can be a value of :
<> 144:ef7eb2e8f9f7 325 * - SYSCFG_BOOT_MAINFLASH
<> 144:ef7eb2e8f9f7 326 * - SYSCFG_BOOT_SYSTEMFLASH
<> 144:ef7eb2e8f9f7 327 * - SYSCFG_BOOT_SRAM
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE)
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /** @brief Check whether the specified SYSCFG flag is set or not.
<> 144:ef7eb2e8f9f7 333 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 334 * The only parameter supported is SYSCFG_FLAG_VREFINT_READY
<> 144:ef7eb2e8f9f7 335 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /** @brief Fast mode Plus driving capability enable macro
<> 144:ef7eb2e8f9f7 340 * @param __FASTMODEPLUS__: This parameter can be a value of :
<> 144:ef7eb2e8f9f7 341 * @arg SYSCFG_FASTMODEPLUS_PB6
<> 144:ef7eb2e8f9f7 342 * @arg SYSCFG_FASTMODEPLUS_PB7
<> 144:ef7eb2e8f9f7 343 * @arg SYSCFG_FASTMODEPLUS_PB8
<> 144:ef7eb2e8f9f7 344 * @arg SYSCFG_FASTMODEPLUS_PB9
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
Anna Bridge 186:707f6e361f3e 347 SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
<> 144:ef7eb2e8f9f7 348 }while(0)
<> 144:ef7eb2e8f9f7 349 /** @brief Fast mode Plus driving capability disable macro
<> 144:ef7eb2e8f9f7 350 * @param __FASTMODEPLUS__: This parameter can be a value of :
<> 144:ef7eb2e8f9f7 351 * @arg SYSCFG_FASTMODEPLUS_PB6
<> 144:ef7eb2e8f9f7 352 * @arg SYSCFG_FASTMODEPLUS_PB7
<> 144:ef7eb2e8f9f7 353 * @arg SYSCFG_FASTMODEPLUS_PB8
<> 144:ef7eb2e8f9f7 354 * @arg SYSCFG_FASTMODEPLUS_PB9
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
Anna Bridge 186:707f6e361f3e 357 CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
<> 144:ef7eb2e8f9f7 358 }while(0)
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @defgroup HAL_Exported_Functions HAL Exported Functions
<> 144:ef7eb2e8f9f7 366 * @{
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 369 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 370 * @{
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372 HAL_StatusTypeDef HAL_Init(void);
<> 144:ef7eb2e8f9f7 373 HAL_StatusTypeDef HAL_DeInit(void);
<> 144:ef7eb2e8f9f7 374 void HAL_MspInit(void);
<> 144:ef7eb2e8f9f7 375 void HAL_MspDeInit(void);
<> 144:ef7eb2e8f9f7 376 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @}
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 383 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 384 * @{
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 void HAL_IncTick(void);
<> 144:ef7eb2e8f9f7 387 void HAL_Delay(__IO uint32_t Delay);
<> 144:ef7eb2e8f9f7 388 uint32_t HAL_GetTick(void);
<> 144:ef7eb2e8f9f7 389 void HAL_SuspendTick(void);
<> 144:ef7eb2e8f9f7 390 void HAL_ResumeTick(void);
<> 144:ef7eb2e8f9f7 391 uint32_t HAL_GetHalVersion(void);
<> 144:ef7eb2e8f9f7 392 uint32_t HAL_GetREVID(void);
<> 144:ef7eb2e8f9f7 393 uint32_t HAL_GetDEVID(void);
<> 144:ef7eb2e8f9f7 394 void HAL_DBGMCU_EnableDBGSleepMode(void);
<> 144:ef7eb2e8f9f7 395 void HAL_DBGMCU_DisableDBGSleepMode(void);
<> 144:ef7eb2e8f9f7 396 void HAL_DBGMCU_EnableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 397 void HAL_DBGMCU_DisableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 398 void HAL_DBGMCU_EnableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 399 void HAL_DBGMCU_DisableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 400 void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph);
<> 144:ef7eb2e8f9f7 401 void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph);
<> 144:ef7eb2e8f9f7 402 uint32_t HAL_SYSCFG_GetBootMode(void);
<> 144:ef7eb2e8f9f7 403 void HAL_SYSCFG_Enable_Lock_VREFINT(void);
<> 144:ef7eb2e8f9f7 404 void HAL_SYSCFG_Disable_Lock_VREFINT(void);
<> 144:ef7eb2e8f9f7 405 void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT);
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /**
<> 144:ef7eb2e8f9f7 408 * @}
<> 144:ef7eb2e8f9f7 409 */
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @}
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /* Define the private group ***********************************/
<> 144:ef7eb2e8f9f7 415 /**************************************************************/
<> 144:ef7eb2e8f9f7 416 /** @defgroup HAL_Private HAL Private
<> 144:ef7eb2e8f9f7 417 * @{
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419 /**
<> 144:ef7eb2e8f9f7 420 * @}
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422 /**************************************************************/
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /**
<> 144:ef7eb2e8f9f7 426 * @}
<> 144:ef7eb2e8f9f7 427 */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435 #endif
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 #endif /* __STM32L0xx_HAL_H */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 440