mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_GCC_ARM/startup_stm32l073xx.S@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 186:707f6e361f3e
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file startup_stm32l073xx.s |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @brief STM32L073xx Devices vector table for Atollic TrueSTUDIO toolchain. |
<> | 144:ef7eb2e8f9f7 | 6 | * This module performs: |
<> | 144:ef7eb2e8f9f7 | 7 | * - Set the initial SP |
<> | 144:ef7eb2e8f9f7 | 8 | * - Set the initial PC == Reset_Handler, |
<> | 144:ef7eb2e8f9f7 | 9 | * - Set the vector table entries with the exceptions ISR address |
<> | 144:ef7eb2e8f9f7 | 10 | * - Branches to main in the C library (which eventually |
<> | 144:ef7eb2e8f9f7 | 11 | * calls main()). |
<> | 144:ef7eb2e8f9f7 | 12 | * After Reset the Cortex-M0+ processor is in Thread mode, |
<> | 144:ef7eb2e8f9f7 | 13 | * priority is Privileged, and the Stack is set to Main. |
<> | 144:ef7eb2e8f9f7 | 14 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 15 | * |
<> | 144:ef7eb2e8f9f7 | 16 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 17 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 18 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 19 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 20 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 21 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 22 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 23 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 24 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 25 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 26 | * |
<> | 144:ef7eb2e8f9f7 | 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 28 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 29 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 30 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 31 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 32 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 33 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 34 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 35 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 36 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 37 | * |
<> | 144:ef7eb2e8f9f7 | 38 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 39 | */ |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | .syntax unified |
<> | 144:ef7eb2e8f9f7 | 42 | .cpu cortex-m0plus |
<> | 144:ef7eb2e8f9f7 | 43 | .fpu softvfp |
<> | 144:ef7eb2e8f9f7 | 44 | .thumb |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | .global g_pfnVectors |
<> | 144:ef7eb2e8f9f7 | 47 | .global Default_Handler |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /* start address for the initialization values of the .data section. |
<> | 144:ef7eb2e8f9f7 | 50 | defined in linker script */ |
<> | 144:ef7eb2e8f9f7 | 51 | .word _sidata |
<> | 144:ef7eb2e8f9f7 | 52 | /* start address for the .data section. defined in linker script */ |
<> | 144:ef7eb2e8f9f7 | 53 | .word _sdata |
<> | 144:ef7eb2e8f9f7 | 54 | /* end address for the .data section. defined in linker script */ |
<> | 144:ef7eb2e8f9f7 | 55 | .word _edata |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | .section .text.Reset_Handler |
<> | 144:ef7eb2e8f9f7 | 58 | .weak Reset_Handler |
<> | 144:ef7eb2e8f9f7 | 59 | .type Reset_Handler, %function |
<> | 144:ef7eb2e8f9f7 | 60 | Reset_Handler: |
<> | 144:ef7eb2e8f9f7 | 61 | ldr r0, =_estack |
<> | 144:ef7eb2e8f9f7 | 62 | mov sp, r0 /* set stack pointer */ |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | /* Copy the data segment initializers from flash to SRAM */ |
<> | 144:ef7eb2e8f9f7 | 65 | movs r1, #0 |
<> | 144:ef7eb2e8f9f7 | 66 | b LoopCopyDataInit |
<> | 144:ef7eb2e8f9f7 | 67 | |
<> | 144:ef7eb2e8f9f7 | 68 | CopyDataInit: |
<> | 144:ef7eb2e8f9f7 | 69 | ldr r3, =_sidata |
<> | 144:ef7eb2e8f9f7 | 70 | ldr r3, [r3, r1] |
<> | 144:ef7eb2e8f9f7 | 71 | str r3, [r0, r1] |
<> | 144:ef7eb2e8f9f7 | 72 | adds r1, r1, #4 |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | LoopCopyDataInit: |
<> | 144:ef7eb2e8f9f7 | 75 | ldr r0, =_sdata |
<> | 144:ef7eb2e8f9f7 | 76 | ldr r3, =_edata |
<> | 144:ef7eb2e8f9f7 | 77 | adds r2, r0, r1 |
<> | 144:ef7eb2e8f9f7 | 78 | cmp r2, r3 |
<> | 144:ef7eb2e8f9f7 | 79 | bcc CopyDataInit |
<> | 144:ef7eb2e8f9f7 | 80 | |
<> | 144:ef7eb2e8f9f7 | 81 | /* Call the clock system intitialization function.*/ |
<> | 144:ef7eb2e8f9f7 | 82 | bl SystemInit |
<> | 144:ef7eb2e8f9f7 | 83 | /* Call static constructors */ |
<> | 144:ef7eb2e8f9f7 | 84 | //bl __libc_init_array |
<> | 144:ef7eb2e8f9f7 | 85 | /* Call the application's entry point.*/ |
<> | 144:ef7eb2e8f9f7 | 86 | //bl main |
<> | 144:ef7eb2e8f9f7 | 87 | bl _start |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | LoopForever: |
<> | 144:ef7eb2e8f9f7 | 90 | b LoopForever |
<> | 144:ef7eb2e8f9f7 | 91 | |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | .size Reset_Handler, .-Reset_Handler |
<> | 144:ef7eb2e8f9f7 | 94 | |
<> | 144:ef7eb2e8f9f7 | 95 | /** |
<> | 144:ef7eb2e8f9f7 | 96 | * @brief This is the code that gets called when the processor receives an |
<> | 144:ef7eb2e8f9f7 | 97 | * unexpected interrupt. This simply enters an infinite loop, preserving |
<> | 144:ef7eb2e8f9f7 | 98 | * the system state for examination by a debugger. |
<> | 144:ef7eb2e8f9f7 | 99 | * |
<> | 144:ef7eb2e8f9f7 | 100 | * @param None |
<> | 144:ef7eb2e8f9f7 | 101 | * @retval : None |
<> | 144:ef7eb2e8f9f7 | 102 | */ |
<> | 144:ef7eb2e8f9f7 | 103 | .section .text.Default_Handler,"ax",%progbits |
<> | 144:ef7eb2e8f9f7 | 104 | Default_Handler: |
<> | 144:ef7eb2e8f9f7 | 105 | Infinite_Loop: |
<> | 144:ef7eb2e8f9f7 | 106 | b Infinite_Loop |
<> | 144:ef7eb2e8f9f7 | 107 | .size Default_Handler, .-Default_Handler |
<> | 144:ef7eb2e8f9f7 | 108 | /****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 109 | * |
<> | 144:ef7eb2e8f9f7 | 110 | * The minimal vector table for a Cortex M0. Note that the proper constructs |
<> | 144:ef7eb2e8f9f7 | 111 | * must be placed on this to ensure that it ends up at physical address |
<> | 144:ef7eb2e8f9f7 | 112 | * 0x0000.0000. |
<> | 144:ef7eb2e8f9f7 | 113 | * |
<> | 144:ef7eb2e8f9f7 | 114 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 115 | .section .isr_vector,"a",%progbits |
<> | 144:ef7eb2e8f9f7 | 116 | .type g_pfnVectors, %object |
<> | 144:ef7eb2e8f9f7 | 117 | .size g_pfnVectors, .-g_pfnVectors |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | |
<> | 144:ef7eb2e8f9f7 | 120 | g_pfnVectors: |
<> | 144:ef7eb2e8f9f7 | 121 | .word _estack |
<> | 144:ef7eb2e8f9f7 | 122 | .word Reset_Handler |
<> | 144:ef7eb2e8f9f7 | 123 | .word NMI_Handler |
<> | 144:ef7eb2e8f9f7 | 124 | .word HardFault_Handler |
<> | 144:ef7eb2e8f9f7 | 125 | .word 0 |
<> | 144:ef7eb2e8f9f7 | 126 | .word 0 |
<> | 144:ef7eb2e8f9f7 | 127 | .word 0 |
<> | 144:ef7eb2e8f9f7 | 128 | .word 0 |
<> | 144:ef7eb2e8f9f7 | 129 | .word 0 |
<> | 144:ef7eb2e8f9f7 | 130 | .word 0 |
<> | 144:ef7eb2e8f9f7 | 131 | .word 0 |
<> | 144:ef7eb2e8f9f7 | 132 | .word SVC_Handler |
<> | 144:ef7eb2e8f9f7 | 133 | .word 0 |
<> | 144:ef7eb2e8f9f7 | 134 | .word 0 |
<> | 144:ef7eb2e8f9f7 | 135 | .word PendSV_Handler |
<> | 144:ef7eb2e8f9f7 | 136 | .word SysTick_Handler |
<> | 144:ef7eb2e8f9f7 | 137 | .word WWDG_IRQHandler /* Window WatchDog */ |
<> | 144:ef7eb2e8f9f7 | 138 | .word PVD_IRQHandler /* PVD through EXTI Line detection */ |
<> | 144:ef7eb2e8f9f7 | 139 | .word RTC_IRQHandler /* RTC through the EXTI line */ |
<> | 144:ef7eb2e8f9f7 | 140 | .word FLASH_IRQHandler /* FLASH */ |
<> | 144:ef7eb2e8f9f7 | 141 | .word RCC_CRS_IRQHandler /* RCC and CRS */ |
<> | 144:ef7eb2e8f9f7 | 142 | .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ |
<> | 144:ef7eb2e8f9f7 | 143 | .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ |
<> | 144:ef7eb2e8f9f7 | 144 | .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ |
<> | 144:ef7eb2e8f9f7 | 145 | .word TSC_IRQHandler /* TSC */ |
<> | 144:ef7eb2e8f9f7 | 146 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ |
<> | 144:ef7eb2e8f9f7 | 147 | .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ |
<> | 144:ef7eb2e8f9f7 | 148 | .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/ |
<> | 144:ef7eb2e8f9f7 | 149 | .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ |
<> | 144:ef7eb2e8f9f7 | 150 | .word LPTIM1_IRQHandler /* LPTIM1 */ |
<> | 144:ef7eb2e8f9f7 | 151 | .word USART4_5_IRQHandler /* USART4 and USART 5 */ |
<> | 144:ef7eb2e8f9f7 | 152 | .word TIM2_IRQHandler /* TIM2 */ |
<> | 144:ef7eb2e8f9f7 | 153 | .word TIM3_IRQHandler /* TIM3 */ |
<> | 144:ef7eb2e8f9f7 | 154 | .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ |
<> | 144:ef7eb2e8f9f7 | 155 | .word TIM7_IRQHandler /* TIM7 */ |
<> | 144:ef7eb2e8f9f7 | 156 | .word 0 /* Reserved */ |
<> | 144:ef7eb2e8f9f7 | 157 | .word TIM21_IRQHandler /* TIM21 */ |
<> | 144:ef7eb2e8f9f7 | 158 | .word I2C3_IRQHandler /* I2C3 */ |
<> | 144:ef7eb2e8f9f7 | 159 | .word TIM22_IRQHandler /* TIM22 */ |
<> | 144:ef7eb2e8f9f7 | 160 | .word I2C1_IRQHandler /* I2C1 */ |
<> | 144:ef7eb2e8f9f7 | 161 | .word I2C2_IRQHandler /* I2C2 */ |
<> | 144:ef7eb2e8f9f7 | 162 | .word SPI1_IRQHandler /* SPI1 */ |
<> | 144:ef7eb2e8f9f7 | 163 | .word SPI2_IRQHandler /* SPI2 */ |
<> | 144:ef7eb2e8f9f7 | 164 | .word USART1_IRQHandler /* USART1 */ |
<> | 144:ef7eb2e8f9f7 | 165 | .word USART2_IRQHandler /* USART2 */ |
<> | 144:ef7eb2e8f9f7 | 166 | .word RNG_LPUART1_IRQHandler /* RNG and LPUART1 */ |
<> | 144:ef7eb2e8f9f7 | 167 | .word LCD_IRQHandler /* LCD */ |
<> | 144:ef7eb2e8f9f7 | 168 | .word USB_IRQHandler /* USB */ |
<> | 144:ef7eb2e8f9f7 | 169 | |
<> | 144:ef7eb2e8f9f7 | 170 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 171 | * |
<> | 144:ef7eb2e8f9f7 | 172 | * Provide weak aliases for each Exception handler to the Default_Handler. |
<> | 144:ef7eb2e8f9f7 | 173 | * As they are weak aliases, any function with the same name will override |
<> | 144:ef7eb2e8f9f7 | 174 | * this definition. |
<> | 144:ef7eb2e8f9f7 | 175 | * |
<> | 144:ef7eb2e8f9f7 | 176 | *******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 177 | |
<> | 144:ef7eb2e8f9f7 | 178 | .weak NMI_Handler |
<> | 144:ef7eb2e8f9f7 | 179 | .thumb_set NMI_Handler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | .weak HardFault_Handler |
<> | 144:ef7eb2e8f9f7 | 182 | .thumb_set HardFault_Handler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 183 | |
<> | 144:ef7eb2e8f9f7 | 184 | .weak SVC_Handler |
<> | 144:ef7eb2e8f9f7 | 185 | .thumb_set SVC_Handler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 186 | |
<> | 144:ef7eb2e8f9f7 | 187 | .weak PendSV_Handler |
<> | 144:ef7eb2e8f9f7 | 188 | .thumb_set PendSV_Handler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | .weak SysTick_Handler |
<> | 144:ef7eb2e8f9f7 | 191 | .thumb_set SysTick_Handler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 192 | |
<> | 144:ef7eb2e8f9f7 | 193 | .weak WWDG_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 194 | .thumb_set WWDG_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 195 | |
<> | 144:ef7eb2e8f9f7 | 196 | .weak PVD_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 197 | .thumb_set PVD_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | .weak RTC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 200 | .thumb_set RTC_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 201 | |
<> | 144:ef7eb2e8f9f7 | 202 | .weak FLASH_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 203 | .thumb_set FLASH_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 204 | |
<> | 144:ef7eb2e8f9f7 | 205 | .weak RCC_CRS_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 206 | .thumb_set RCC_CRS_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | .weak EXTI0_1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 209 | .thumb_set EXTI0_1_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 210 | |
<> | 144:ef7eb2e8f9f7 | 211 | .weak EXTI2_3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 212 | .thumb_set EXTI2_3_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 213 | |
<> | 144:ef7eb2e8f9f7 | 214 | .weak EXTI4_15_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 215 | .thumb_set EXTI4_15_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 216 | |
<> | 144:ef7eb2e8f9f7 | 217 | .weak TSC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 218 | .thumb_set TSC_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 219 | |
<> | 144:ef7eb2e8f9f7 | 220 | .weak DMA1_Channel1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 221 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 222 | |
<> | 144:ef7eb2e8f9f7 | 223 | .weak DMA1_Channel2_3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 224 | .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 225 | |
<> | 144:ef7eb2e8f9f7 | 226 | .weak DMA1_Channel4_5_6_7_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 227 | .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | .weak ADC1_COMP_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 230 | .thumb_set ADC1_COMP_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 231 | |
<> | 144:ef7eb2e8f9f7 | 232 | .weak LPTIM1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 233 | .thumb_set LPTIM1_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 234 | |
<> | 144:ef7eb2e8f9f7 | 235 | .weak USART4_5_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 236 | .thumb_set USART4_5_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 237 | |
<> | 144:ef7eb2e8f9f7 | 238 | .weak TIM2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 239 | .thumb_set TIM2_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 240 | |
<> | 144:ef7eb2e8f9f7 | 241 | .weak TIM3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 242 | .thumb_set TIM3_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | .weak TIM6_DAC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 245 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 246 | |
<> | 144:ef7eb2e8f9f7 | 247 | .weak TIM7_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 248 | .thumb_set TIM7_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 249 | |
<> | 144:ef7eb2e8f9f7 | 250 | .weak TIM21_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 251 | .thumb_set TIM21_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 252 | |
<> | 144:ef7eb2e8f9f7 | 253 | .weak I2C3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 254 | .thumb_set I2C3_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 255 | |
<> | 144:ef7eb2e8f9f7 | 256 | .weak TIM22_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 257 | .thumb_set TIM22_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 258 | |
<> | 144:ef7eb2e8f9f7 | 259 | .weak I2C1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 260 | .thumb_set I2C1_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 261 | |
<> | 144:ef7eb2e8f9f7 | 262 | .weak I2C2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 263 | .thumb_set I2C2_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | .weak SPI1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 266 | .thumb_set SPI1_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | .weak SPI2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 269 | .thumb_set SPI2_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 270 | |
<> | 144:ef7eb2e8f9f7 | 271 | .weak USART1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 272 | .thumb_set USART1_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 273 | |
<> | 144:ef7eb2e8f9f7 | 274 | .weak USART2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 275 | .thumb_set USART2_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 276 | |
<> | 144:ef7eb2e8f9f7 | 277 | .weak RNG_LPUART1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 278 | .thumb_set RNG_LPUART1_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 279 | |
<> | 144:ef7eb2e8f9f7 | 280 | .weak LCD_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 281 | .thumb_set LCD_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 282 | |
<> | 144:ef7eb2e8f9f7 | 283 | .weak USB_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 284 | .thumb_set USB_IRQHandler,Default_Handler |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | |
<> | 144:ef7eb2e8f9f7 | 287 | |
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