mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_ARM_STD/startup_stm32l073xx.S@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
<> 144:ef7eb2e8f9f7 2 ;* File Name : startup_stm32l073xx.s
<> 144:ef7eb2e8f9f7 3 ;* Author : MCD Application Team
Anna Bridge 186:707f6e361f3e 4 ;* Version : V1.7.1
Anna Bridge 186:707f6e361f3e 5 ;* Date : 25-November-2016
<> 144:ef7eb2e8f9f7 6 ;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain.
<> 144:ef7eb2e8f9f7 7 ;* This module performs:
<> 144:ef7eb2e8f9f7 8 ;* - Set the initial SP
<> 144:ef7eb2e8f9f7 9 ;* - Set the initial PC == Reset_Handler
<> 144:ef7eb2e8f9f7 10 ;* - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 11 ;* - Branches to __main in the C library (which eventually
<> 144:ef7eb2e8f9f7 12 ;* calls main()).
<> 144:ef7eb2e8f9f7 13 ;* After Reset the Cortex-M0+ processor is in Thread mode,
<> 144:ef7eb2e8f9f7 14 ;* priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 15 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 16 ;*
<> 144:ef7eb2e8f9f7 17 ;* Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 18 ;* are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 19 ;* 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 20 ;* this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 21 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 22 ;* this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 23 ;* and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 24 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 25 ;* may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 26 ;* without specific prior written permission.
<> 144:ef7eb2e8f9f7 27 ;*
<> 144:ef7eb2e8f9f7 28 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 29 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 30 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 31 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 32 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 33 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 34 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 35 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 36 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 37 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 38 ;*
<> 144:ef7eb2e8f9f7 39 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 __initial_sp EQU 0x20005000 ; Top of RAM
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 PRESERVE8
<> 144:ef7eb2e8f9f7 44 THUMB
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 48 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 49 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 50 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 51 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 54 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 55 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 56 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 57 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 58 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 59 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 60 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 61 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 62 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 63 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 64 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 65 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 66 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 67 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 68 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 ; External Interrupts
<> 144:ef7eb2e8f9f7 71 DCD WWDG_IRQHandler ; Window Watchdog
<> 144:ef7eb2e8f9f7 72 DCD PVD_IRQHandler ; PVD through EXTI Line detect
<> 144:ef7eb2e8f9f7 73 DCD RTC_IRQHandler ; RTC through EXTI Line
<> 144:ef7eb2e8f9f7 74 DCD FLASH_IRQHandler ; FLASH
<> 144:ef7eb2e8f9f7 75 DCD RCC_CRS_IRQHandler ; RCC and CRS
<> 144:ef7eb2e8f9f7 76 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
<> 144:ef7eb2e8f9f7 77 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
<> 144:ef7eb2e8f9f7 78 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
<> 144:ef7eb2e8f9f7 79 DCD TSC_IRQHandler ; TSC
<> 144:ef7eb2e8f9f7 80 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
<> 144:ef7eb2e8f9f7 81 DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
<> 144:ef7eb2e8f9f7 82 DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
<> 144:ef7eb2e8f9f7 83 DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
<> 144:ef7eb2e8f9f7 84 DCD LPTIM1_IRQHandler ; LPTIM1
<> 144:ef7eb2e8f9f7 85 DCD USART4_5_IRQHandler ; USART4 and USART5
<> 144:ef7eb2e8f9f7 86 DCD TIM2_IRQHandler ; TIM2
<> 144:ef7eb2e8f9f7 87 DCD TIM3_IRQHandler ; TIM3
<> 144:ef7eb2e8f9f7 88 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
<> 144:ef7eb2e8f9f7 89 DCD TIM7_IRQHandler ; TIM7
<> 144:ef7eb2e8f9f7 90 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 91 DCD TIM21_IRQHandler ; TIM21
<> 144:ef7eb2e8f9f7 92 DCD I2C3_IRQHandler ; I2C3
<> 144:ef7eb2e8f9f7 93 DCD TIM22_IRQHandler ; TIM22
<> 144:ef7eb2e8f9f7 94 DCD I2C1_IRQHandler ; I2C1
<> 144:ef7eb2e8f9f7 95 DCD I2C2_IRQHandler ; I2C2
<> 144:ef7eb2e8f9f7 96 DCD SPI1_IRQHandler ; SPI1
<> 144:ef7eb2e8f9f7 97 DCD SPI2_IRQHandler ; SPI2
<> 144:ef7eb2e8f9f7 98 DCD USART1_IRQHandler ; USART1
<> 144:ef7eb2e8f9f7 99 DCD USART2_IRQHandler ; USART2
<> 144:ef7eb2e8f9f7 100 DCD RNG_LPUART1_IRQHandler ; RNG and LPUART1
<> 144:ef7eb2e8f9f7 101 DCD LCD_IRQHandler ; LCD
<> 144:ef7eb2e8f9f7 102 DCD USB_IRQHandler ; USB
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 __Vectors_End
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 ; Reset handler routine
<> 144:ef7eb2e8f9f7 111 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 112 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 113 IMPORT __main
<> 144:ef7eb2e8f9f7 114 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 115 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 116 BLX R0
<> 144:ef7eb2e8f9f7 117 LDR R0, =__main
<> 144:ef7eb2e8f9f7 118 BX R0
<> 144:ef7eb2e8f9f7 119 ENDP
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 124 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 125 B .
<> 144:ef7eb2e8f9f7 126 ENDP
<> 144:ef7eb2e8f9f7 127 HardFault_Handler\
<> 144:ef7eb2e8f9f7 128 PROC
<> 144:ef7eb2e8f9f7 129 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 130 B .
<> 144:ef7eb2e8f9f7 131 ENDP
<> 144:ef7eb2e8f9f7 132 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 133 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 134 B .
<> 144:ef7eb2e8f9f7 135 ENDP
<> 144:ef7eb2e8f9f7 136 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 137 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 138 B .
<> 144:ef7eb2e8f9f7 139 ENDP
<> 144:ef7eb2e8f9f7 140 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 141 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 142 B .
<> 144:ef7eb2e8f9f7 143 ENDP
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 Default_Handler PROC
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 EXPORT WWDG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 148 EXPORT PVD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 149 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 150 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 151 EXPORT RCC_CRS_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 152 EXPORT EXTI0_1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 153 EXPORT EXTI2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 154 EXPORT EXTI4_15_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 155 EXPORT TSC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 156 EXPORT DMA1_Channel1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 157 EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 158 EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 159 EXPORT ADC1_COMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 160 EXPORT LPTIM1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 161 EXPORT USART4_5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 162 EXPORT TIM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 163 EXPORT TIM3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 164 EXPORT TIM6_DAC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 165 EXPORT TIM7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 166 EXPORT TIM21_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 167 EXPORT TIM22_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 168 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 169 EXPORT I2C2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 170 EXPORT I2C3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 171 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 172 EXPORT SPI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 173 EXPORT USART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 174 EXPORT USART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 175 EXPORT RNG_LPUART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 176 EXPORT LCD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 177 EXPORT USB_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 181 PVD_IRQHandler
<> 144:ef7eb2e8f9f7 182 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 183 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 184 RCC_CRS_IRQHandler
<> 144:ef7eb2e8f9f7 185 EXTI0_1_IRQHandler
<> 144:ef7eb2e8f9f7 186 EXTI2_3_IRQHandler
<> 144:ef7eb2e8f9f7 187 EXTI4_15_IRQHandler
<> 144:ef7eb2e8f9f7 188 TSC_IRQHandler
<> 144:ef7eb2e8f9f7 189 DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 190 DMA1_Channel2_3_IRQHandler
<> 144:ef7eb2e8f9f7 191 DMA1_Channel4_5_6_7_IRQHandler
<> 144:ef7eb2e8f9f7 192 ADC1_COMP_IRQHandler
<> 144:ef7eb2e8f9f7 193 LPTIM1_IRQHandler
<> 144:ef7eb2e8f9f7 194 USART4_5_IRQHandler
<> 144:ef7eb2e8f9f7 195 TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 196 TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 197 TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 198 TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 199 TIM21_IRQHandler
<> 144:ef7eb2e8f9f7 200 TIM22_IRQHandler
<> 144:ef7eb2e8f9f7 201 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 202 I2C2_IRQHandler
<> 144:ef7eb2e8f9f7 203 I2C3_IRQHandler
<> 144:ef7eb2e8f9f7 204 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 205 SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 206 USART1_IRQHandler
<> 144:ef7eb2e8f9f7 207 USART2_IRQHandler
<> 144:ef7eb2e8f9f7 208 RNG_LPUART1_IRQHandler
<> 144:ef7eb2e8f9f7 209 LCD_IRQHandler
<> 144:ef7eb2e8f9f7 210 USB_IRQHandler
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 B .
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 ENDP
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 ALIGN
<> 144:ef7eb2e8f9f7 217 END
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****