mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 114:fe4fe5cfc3a3 1 /**
mbed_official 114:fe4fe5cfc3a3 2 ******************************************************************************
mbed_official 114:fe4fe5cfc3a3 3 * @file stm32l031xx.h
mbed_official 114:fe4fe5cfc3a3 4 * @author MCD Application Team
mbed_official 114:fe4fe5cfc3a3 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
mbed_official 114:fe4fe5cfc3a3 6 * This file contains all the peripheral register's definitions, bits
mbed_official 114:fe4fe5cfc3a3 7 * definitions and memory mapping for stm32l031xx devices.
mbed_official 114:fe4fe5cfc3a3 8 *
mbed_official 114:fe4fe5cfc3a3 9 * This file contains:
mbed_official 114:fe4fe5cfc3a3 10 * - Data structures and the address mapping for all peripherals
mbed_official 114:fe4fe5cfc3a3 11 * - Peripheral's registers declarations and bits definition
mbed_official 114:fe4fe5cfc3a3 12 * - Macros to access peripheral's registers hardware
mbed_official 114:fe4fe5cfc3a3 13 *
mbed_official 114:fe4fe5cfc3a3 14 ******************************************************************************
mbed_official 114:fe4fe5cfc3a3 15 * @attention
mbed_official 114:fe4fe5cfc3a3 16 *
Anna Bridge 186:707f6e361f3e 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
mbed_official 114:fe4fe5cfc3a3 18 *
mbed_official 114:fe4fe5cfc3a3 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 114:fe4fe5cfc3a3 20 * are permitted provided that the following conditions are met:
mbed_official 114:fe4fe5cfc3a3 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 114:fe4fe5cfc3a3 22 * this list of conditions and the following disclaimer.
mbed_official 114:fe4fe5cfc3a3 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 114:fe4fe5cfc3a3 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 114:fe4fe5cfc3a3 25 * and/or other materials provided with the distribution.
mbed_official 114:fe4fe5cfc3a3 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 114:fe4fe5cfc3a3 27 * may be used to endorse or promote products derived from this software
mbed_official 114:fe4fe5cfc3a3 28 * without specific prior written permission.
mbed_official 114:fe4fe5cfc3a3 29 *
mbed_official 114:fe4fe5cfc3a3 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 114:fe4fe5cfc3a3 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 114:fe4fe5cfc3a3 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 114:fe4fe5cfc3a3 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 114:fe4fe5cfc3a3 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 114:fe4fe5cfc3a3 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 114:fe4fe5cfc3a3 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 114:fe4fe5cfc3a3 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 114:fe4fe5cfc3a3 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 114:fe4fe5cfc3a3 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 114:fe4fe5cfc3a3 40 *
mbed_official 114:fe4fe5cfc3a3 41 ******************************************************************************
mbed_official 114:fe4fe5cfc3a3 42 */
mbed_official 114:fe4fe5cfc3a3 43
mbed_official 114:fe4fe5cfc3a3 44 /** @addtogroup CMSIS
mbed_official 114:fe4fe5cfc3a3 45 * @{
mbed_official 114:fe4fe5cfc3a3 46 */
mbed_official 114:fe4fe5cfc3a3 47
mbed_official 114:fe4fe5cfc3a3 48 /** @addtogroup stm32l031xx
mbed_official 114:fe4fe5cfc3a3 49 * @{
mbed_official 114:fe4fe5cfc3a3 50 */
mbed_official 114:fe4fe5cfc3a3 51
mbed_official 114:fe4fe5cfc3a3 52 #ifndef __STM32L031xx_H
mbed_official 114:fe4fe5cfc3a3 53 #define __STM32L031xx_H
mbed_official 114:fe4fe5cfc3a3 54
mbed_official 114:fe4fe5cfc3a3 55 #ifdef __cplusplus
mbed_official 114:fe4fe5cfc3a3 56 extern "C" {
mbed_official 114:fe4fe5cfc3a3 57 #endif
mbed_official 114:fe4fe5cfc3a3 58
mbed_official 114:fe4fe5cfc3a3 59
mbed_official 114:fe4fe5cfc3a3 60 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 114:fe4fe5cfc3a3 61 * @{
mbed_official 114:fe4fe5cfc3a3 62 */
mbed_official 114:fe4fe5cfc3a3 63 /**
mbed_official 114:fe4fe5cfc3a3 64 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
mbed_official 114:fe4fe5cfc3a3 65 */
mbed_official 114:fe4fe5cfc3a3 66 #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
mbed_official 114:fe4fe5cfc3a3 67 #define __MPU_PRESENT 0 /*!< STM32L0xx provides no MPU */
mbed_official 114:fe4fe5cfc3a3 68 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
mbed_official 114:fe4fe5cfc3a3 69 #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
mbed_official 114:fe4fe5cfc3a3 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 114:fe4fe5cfc3a3 71
mbed_official 114:fe4fe5cfc3a3 72 /**
mbed_official 114:fe4fe5cfc3a3 73 * @}
mbed_official 114:fe4fe5cfc3a3 74 */
mbed_official 114:fe4fe5cfc3a3 75
mbed_official 114:fe4fe5cfc3a3 76 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 114:fe4fe5cfc3a3 77 * @{
mbed_official 114:fe4fe5cfc3a3 78 */
mbed_official 114:fe4fe5cfc3a3 79
mbed_official 114:fe4fe5cfc3a3 80 /**
mbed_official 114:fe4fe5cfc3a3 81 * @brief stm32l031xx Interrupt Number Definition, according to the selected device
mbed_official 114:fe4fe5cfc3a3 82 * in @ref Library_configuration_section
mbed_official 114:fe4fe5cfc3a3 83 */
mbed_official 114:fe4fe5cfc3a3 84
mbed_official 114:fe4fe5cfc3a3 85 /*!< Interrupt Number Definition */
mbed_official 114:fe4fe5cfc3a3 86 typedef enum
mbed_official 114:fe4fe5cfc3a3 87 {
mbed_official 114:fe4fe5cfc3a3 88 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
mbed_official 114:fe4fe5cfc3a3 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 114:fe4fe5cfc3a3 90 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
mbed_official 114:fe4fe5cfc3a3 91 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
mbed_official 114:fe4fe5cfc3a3 92 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
mbed_official 114:fe4fe5cfc3a3 93 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
mbed_official 114:fe4fe5cfc3a3 94
mbed_official 114:fe4fe5cfc3a3 95 /****** STM32L-0 specific Interrupt Numbers *********************************************************/
mbed_official 114:fe4fe5cfc3a3 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 114:fe4fe5cfc3a3 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
mbed_official 114:fe4fe5cfc3a3 98 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
mbed_official 114:fe4fe5cfc3a3 99 FLASH_IRQn = 3, /*!< FLASH Interrupt */
mbed_official 114:fe4fe5cfc3a3 100 RCC_IRQn = 4, /*!< RCC Interrupt */
mbed_official 114:fe4fe5cfc3a3 101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
mbed_official 114:fe4fe5cfc3a3 102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
mbed_official 114:fe4fe5cfc3a3 103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
mbed_official 114:fe4fe5cfc3a3 104 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
mbed_official 114:fe4fe5cfc3a3 105 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
mbed_official 114:fe4fe5cfc3a3 106 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
mbed_official 114:fe4fe5cfc3a3 107 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
mbed_official 114:fe4fe5cfc3a3 108 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
mbed_official 114:fe4fe5cfc3a3 109 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
mbed_official 114:fe4fe5cfc3a3 110 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
mbed_official 114:fe4fe5cfc3a3 111 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
mbed_official 114:fe4fe5cfc3a3 112 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
mbed_official 114:fe4fe5cfc3a3 113 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
mbed_official 114:fe4fe5cfc3a3 114 USART2_IRQn = 28, /*!< USART2 Interrupt */
mbed_official 114:fe4fe5cfc3a3 115 LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */
mbed_official 114:fe4fe5cfc3a3 116 } IRQn_Type;
mbed_official 114:fe4fe5cfc3a3 117
mbed_official 114:fe4fe5cfc3a3 118 /**
mbed_official 114:fe4fe5cfc3a3 119 * @}
mbed_official 114:fe4fe5cfc3a3 120 */
mbed_official 114:fe4fe5cfc3a3 121
mbed_official 114:fe4fe5cfc3a3 122 #include "core_cm0plus.h"
mbed_official 114:fe4fe5cfc3a3 123 #include "system_stm32l0xx.h"
mbed_official 114:fe4fe5cfc3a3 124 #include <stdint.h>
mbed_official 114:fe4fe5cfc3a3 125
mbed_official 114:fe4fe5cfc3a3 126 /** @addtogroup Peripheral_registers_structures
mbed_official 114:fe4fe5cfc3a3 127 * @{
mbed_official 114:fe4fe5cfc3a3 128 */
mbed_official 114:fe4fe5cfc3a3 129
mbed_official 114:fe4fe5cfc3a3 130 /**
mbed_official 114:fe4fe5cfc3a3 131 * @brief Analog to Digital Converter
mbed_official 114:fe4fe5cfc3a3 132 */
mbed_official 114:fe4fe5cfc3a3 133
mbed_official 114:fe4fe5cfc3a3 134 typedef struct
mbed_official 114:fe4fe5cfc3a3 135 {
mbed_official 114:fe4fe5cfc3a3 136 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
mbed_official 114:fe4fe5cfc3a3 137 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
mbed_official 114:fe4fe5cfc3a3 138 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
mbed_official 114:fe4fe5cfc3a3 139 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
mbed_official 114:fe4fe5cfc3a3 140 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
mbed_official 114:fe4fe5cfc3a3 141 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
mbed_official 114:fe4fe5cfc3a3 142 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 114:fe4fe5cfc3a3 143 uint32_t RESERVED2; /*!< Reserved, 0x1C */
mbed_official 114:fe4fe5cfc3a3 144 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
mbed_official 114:fe4fe5cfc3a3 145 uint32_t RESERVED3; /*!< Reserved, 0x24 */
mbed_official 114:fe4fe5cfc3a3 146 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
mbed_official 114:fe4fe5cfc3a3 147 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
mbed_official 114:fe4fe5cfc3a3 148 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
mbed_official 114:fe4fe5cfc3a3 149 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
mbed_official 114:fe4fe5cfc3a3 150 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
mbed_official 114:fe4fe5cfc3a3 151 } ADC_TypeDef;
mbed_official 114:fe4fe5cfc3a3 152
mbed_official 114:fe4fe5cfc3a3 153 typedef struct
mbed_official 114:fe4fe5cfc3a3 154 {
mbed_official 114:fe4fe5cfc3a3 155 __IO uint32_t CCR;
mbed_official 114:fe4fe5cfc3a3 156 } ADC_Common_TypeDef;
mbed_official 114:fe4fe5cfc3a3 157
mbed_official 114:fe4fe5cfc3a3 158
mbed_official 114:fe4fe5cfc3a3 159 /**
mbed_official 114:fe4fe5cfc3a3 160 * @brief Comparator
mbed_official 114:fe4fe5cfc3a3 161 */
mbed_official 114:fe4fe5cfc3a3 162
mbed_official 114:fe4fe5cfc3a3 163 typedef struct
mbed_official 114:fe4fe5cfc3a3 164 {
mbed_official 114:fe4fe5cfc3a3 165 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
mbed_official 114:fe4fe5cfc3a3 166 } COMP_TypeDef;
mbed_official 114:fe4fe5cfc3a3 167
mbed_official 114:fe4fe5cfc3a3 168 typedef struct
mbed_official 114:fe4fe5cfc3a3 169 {
mbed_official 114:fe4fe5cfc3a3 170 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 171 } COMP_Common_TypeDef;
mbed_official 114:fe4fe5cfc3a3 172
mbed_official 114:fe4fe5cfc3a3 173
mbed_official 114:fe4fe5cfc3a3 174 /**
mbed_official 114:fe4fe5cfc3a3 175 * @brief CRC calculation unit
mbed_official 114:fe4fe5cfc3a3 176 */
mbed_official 114:fe4fe5cfc3a3 177
mbed_official 114:fe4fe5cfc3a3 178 typedef struct
mbed_official 114:fe4fe5cfc3a3 179 {
mbed_official 114:fe4fe5cfc3a3 180 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 181 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 182 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 114:fe4fe5cfc3a3 183 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 114:fe4fe5cfc3a3 184 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 185 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 114:fe4fe5cfc3a3 186 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 187 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 188 } CRC_TypeDef;
mbed_official 114:fe4fe5cfc3a3 189
mbed_official 114:fe4fe5cfc3a3 190 /**
mbed_official 114:fe4fe5cfc3a3 191 * @brief Debug MCU
mbed_official 114:fe4fe5cfc3a3 192 */
mbed_official 114:fe4fe5cfc3a3 193
mbed_official 114:fe4fe5cfc3a3 194 typedef struct
mbed_official 114:fe4fe5cfc3a3 195 {
mbed_official 114:fe4fe5cfc3a3 196 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 197 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 198 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 199 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 200 }DBGMCU_TypeDef;
mbed_official 114:fe4fe5cfc3a3 201
mbed_official 114:fe4fe5cfc3a3 202 /**
mbed_official 114:fe4fe5cfc3a3 203 * @brief DMA Controller
mbed_official 114:fe4fe5cfc3a3 204 */
mbed_official 114:fe4fe5cfc3a3 205
mbed_official 114:fe4fe5cfc3a3 206 typedef struct
mbed_official 114:fe4fe5cfc3a3 207 {
mbed_official 114:fe4fe5cfc3a3 208 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 114:fe4fe5cfc3a3 209 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 114:fe4fe5cfc3a3 210 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 114:fe4fe5cfc3a3 211 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 114:fe4fe5cfc3a3 212 } DMA_Channel_TypeDef;
mbed_official 114:fe4fe5cfc3a3 213
mbed_official 114:fe4fe5cfc3a3 214 typedef struct
mbed_official 114:fe4fe5cfc3a3 215 {
mbed_official 114:fe4fe5cfc3a3 216 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 217 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 218 } DMA_TypeDef;
mbed_official 114:fe4fe5cfc3a3 219
mbed_official 114:fe4fe5cfc3a3 220 typedef struct
mbed_official 114:fe4fe5cfc3a3 221 {
mbed_official 114:fe4fe5cfc3a3 222 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
mbed_official 114:fe4fe5cfc3a3 223 } DMA_Request_TypeDef;
mbed_official 114:fe4fe5cfc3a3 224
mbed_official 114:fe4fe5cfc3a3 225 /**
mbed_official 114:fe4fe5cfc3a3 226 * @brief External Interrupt/Event Controller
mbed_official 114:fe4fe5cfc3a3 227 */
mbed_official 114:fe4fe5cfc3a3 228
mbed_official 114:fe4fe5cfc3a3 229 typedef struct
mbed_official 114:fe4fe5cfc3a3 230 {
mbed_official 114:fe4fe5cfc3a3 231 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 232 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 233 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 234 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 235 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 236 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 237 }EXTI_TypeDef;
mbed_official 114:fe4fe5cfc3a3 238
mbed_official 114:fe4fe5cfc3a3 239 /**
mbed_official 114:fe4fe5cfc3a3 240 * @brief FLASH Registers
mbed_official 114:fe4fe5cfc3a3 241 */
mbed_official 114:fe4fe5cfc3a3 242 typedef struct
mbed_official 114:fe4fe5cfc3a3 243 {
mbed_official 114:fe4fe5cfc3a3 244 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 245 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 246 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 247 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
mbed_official 114:fe4fe5cfc3a3 248 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 249 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 250 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
mbed_official 114:fe4fe5cfc3a3 251 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
mbed_official 114:fe4fe5cfc3a3 252 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
mbed_official 114:fe4fe5cfc3a3 253 } FLASH_TypeDef;
mbed_official 114:fe4fe5cfc3a3 254
mbed_official 114:fe4fe5cfc3a3 255
mbed_official 114:fe4fe5cfc3a3 256 /**
mbed_official 114:fe4fe5cfc3a3 257 * @brief Option Bytes Registers
mbed_official 114:fe4fe5cfc3a3 258 */
mbed_official 114:fe4fe5cfc3a3 259 typedef struct
mbed_official 114:fe4fe5cfc3a3 260 {
mbed_official 114:fe4fe5cfc3a3 261 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 262 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 263 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 264 } OB_TypeDef;
mbed_official 114:fe4fe5cfc3a3 265
mbed_official 114:fe4fe5cfc3a3 266
mbed_official 114:fe4fe5cfc3a3 267 /**
mbed_official 114:fe4fe5cfc3a3 268 * @brief General Purpose IO
mbed_official 114:fe4fe5cfc3a3 269 */
mbed_official 114:fe4fe5cfc3a3 270
mbed_official 114:fe4fe5cfc3a3 271 typedef struct
mbed_official 114:fe4fe5cfc3a3 272 {
mbed_official 114:fe4fe5cfc3a3 273 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 274 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 275 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 276 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 277 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 278 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 279 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
mbed_official 114:fe4fe5cfc3a3 280 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 114:fe4fe5cfc3a3 281 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
mbed_official 114:fe4fe5cfc3a3 282 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 114:fe4fe5cfc3a3 283 }GPIO_TypeDef;
mbed_official 114:fe4fe5cfc3a3 284
mbed_official 114:fe4fe5cfc3a3 285 /**
mbed_official 114:fe4fe5cfc3a3 286 * @brief LPTIMIMER
mbed_official 114:fe4fe5cfc3a3 287 */
mbed_official 114:fe4fe5cfc3a3 288 typedef struct
mbed_official 114:fe4fe5cfc3a3 289 {
mbed_official 114:fe4fe5cfc3a3 290 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 291 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 292 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 293 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 294 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 295 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 296 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
mbed_official 114:fe4fe5cfc3a3 297 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
mbed_official 114:fe4fe5cfc3a3 298 } LPTIM_TypeDef;
mbed_official 114:fe4fe5cfc3a3 299
mbed_official 114:fe4fe5cfc3a3 300 /**
mbed_official 114:fe4fe5cfc3a3 301 * @brief SysTem Configuration
mbed_official 114:fe4fe5cfc3a3 302 */
mbed_official 114:fe4fe5cfc3a3 303
mbed_official 114:fe4fe5cfc3a3 304 typedef struct
mbed_official 114:fe4fe5cfc3a3 305 {
mbed_official 114:fe4fe5cfc3a3 306 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 307 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 308 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
mbed_official 114:fe4fe5cfc3a3 309 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
mbed_official 114:fe4fe5cfc3a3 310 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
mbed_official 114:fe4fe5cfc3a3 311 } SYSCFG_TypeDef;
mbed_official 114:fe4fe5cfc3a3 312
mbed_official 114:fe4fe5cfc3a3 313
mbed_official 114:fe4fe5cfc3a3 314
mbed_official 114:fe4fe5cfc3a3 315 /**
mbed_official 114:fe4fe5cfc3a3 316 * @brief Inter-integrated Circuit Interface
mbed_official 114:fe4fe5cfc3a3 317 */
mbed_official 114:fe4fe5cfc3a3 318
mbed_official 114:fe4fe5cfc3a3 319 typedef struct
mbed_official 114:fe4fe5cfc3a3 320 {
mbed_official 114:fe4fe5cfc3a3 321 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 322 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 323 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 324 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 325 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 326 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 327 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 114:fe4fe5cfc3a3 328 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 114:fe4fe5cfc3a3 329 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 114:fe4fe5cfc3a3 330 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 114:fe4fe5cfc3a3 331 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 114:fe4fe5cfc3a3 332 }I2C_TypeDef;
mbed_official 114:fe4fe5cfc3a3 333
mbed_official 114:fe4fe5cfc3a3 334
mbed_official 114:fe4fe5cfc3a3 335 /**
mbed_official 114:fe4fe5cfc3a3 336 * @brief Independent WATCHDOG
mbed_official 114:fe4fe5cfc3a3 337 */
mbed_official 114:fe4fe5cfc3a3 338 typedef struct
mbed_official 114:fe4fe5cfc3a3 339 {
mbed_official 114:fe4fe5cfc3a3 340 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 341 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 342 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 343 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 344 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 345 } IWDG_TypeDef;
mbed_official 114:fe4fe5cfc3a3 346
mbed_official 114:fe4fe5cfc3a3 347 /**
mbed_official 114:fe4fe5cfc3a3 348 * @brief Power Control
mbed_official 114:fe4fe5cfc3a3 349 */
mbed_official 114:fe4fe5cfc3a3 350 typedef struct
mbed_official 114:fe4fe5cfc3a3 351 {
mbed_official 114:fe4fe5cfc3a3 352 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 353 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 354 } PWR_TypeDef;
mbed_official 114:fe4fe5cfc3a3 355
mbed_official 114:fe4fe5cfc3a3 356 /**
mbed_official 114:fe4fe5cfc3a3 357 * @brief Reset and Clock Control
mbed_official 114:fe4fe5cfc3a3 358 */
mbed_official 114:fe4fe5cfc3a3 359 typedef struct
mbed_official 114:fe4fe5cfc3a3 360 {
mbed_official 114:fe4fe5cfc3a3 361 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 362 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 363 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 364 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 365 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 366 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 367 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
mbed_official 114:fe4fe5cfc3a3 368 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
mbed_official 114:fe4fe5cfc3a3 369 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
mbed_official 114:fe4fe5cfc3a3 370 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
mbed_official 114:fe4fe5cfc3a3 371 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
mbed_official 114:fe4fe5cfc3a3 372 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
mbed_official 114:fe4fe5cfc3a3 373 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
mbed_official 114:fe4fe5cfc3a3 374 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
mbed_official 114:fe4fe5cfc3a3 375 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
mbed_official 114:fe4fe5cfc3a3 376 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
mbed_official 114:fe4fe5cfc3a3 377 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
mbed_official 114:fe4fe5cfc3a3 378 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
mbed_official 114:fe4fe5cfc3a3 379 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
mbed_official 114:fe4fe5cfc3a3 380 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
mbed_official 114:fe4fe5cfc3a3 381 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
mbed_official 114:fe4fe5cfc3a3 382 } RCC_TypeDef;
mbed_official 114:fe4fe5cfc3a3 383
mbed_official 114:fe4fe5cfc3a3 384 /**
mbed_official 114:fe4fe5cfc3a3 385 * @brief Real-Time Clock
mbed_official 114:fe4fe5cfc3a3 386 */
mbed_official 114:fe4fe5cfc3a3 387 typedef struct
mbed_official 114:fe4fe5cfc3a3 388 {
mbed_official 114:fe4fe5cfc3a3 389 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 390 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 391 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 392 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 393 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 394 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 395 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
mbed_official 114:fe4fe5cfc3a3 396 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 114:fe4fe5cfc3a3 397 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 114:fe4fe5cfc3a3 398 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 114:fe4fe5cfc3a3 399 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 114:fe4fe5cfc3a3 400 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 114:fe4fe5cfc3a3 401 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 114:fe4fe5cfc3a3 402 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 114:fe4fe5cfc3a3 403 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 114:fe4fe5cfc3a3 404 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 114:fe4fe5cfc3a3 405 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
mbed_official 114:fe4fe5cfc3a3 406 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 114:fe4fe5cfc3a3 407 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 114:fe4fe5cfc3a3 408 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
mbed_official 114:fe4fe5cfc3a3 409 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 114:fe4fe5cfc3a3 410 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 114:fe4fe5cfc3a3 411 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 114:fe4fe5cfc3a3 412 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 114:fe4fe5cfc3a3 413 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 114:fe4fe5cfc3a3 414 } RTC_TypeDef;
mbed_official 114:fe4fe5cfc3a3 415
mbed_official 114:fe4fe5cfc3a3 416
mbed_official 114:fe4fe5cfc3a3 417 /**
mbed_official 114:fe4fe5cfc3a3 418 * @brief Serial Peripheral Interface
mbed_official 114:fe4fe5cfc3a3 419 */
mbed_official 114:fe4fe5cfc3a3 420 typedef struct
mbed_official 114:fe4fe5cfc3a3 421 {
mbed_official 114:fe4fe5cfc3a3 422 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 423 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 424 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 425 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 426 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 427 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 428 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
mbed_official 114:fe4fe5cfc3a3 429 } SPI_TypeDef;
mbed_official 114:fe4fe5cfc3a3 430
mbed_official 114:fe4fe5cfc3a3 431 /**
mbed_official 114:fe4fe5cfc3a3 432 * @brief TIM
mbed_official 114:fe4fe5cfc3a3 433 */
mbed_official 114:fe4fe5cfc3a3 434 typedef struct
mbed_official 114:fe4fe5cfc3a3 435 {
mbed_official 114:fe4fe5cfc3a3 436 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 437 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 438 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 439 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 440 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 441 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 442 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 114:fe4fe5cfc3a3 443 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 114:fe4fe5cfc3a3 444 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 114:fe4fe5cfc3a3 445 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 114:fe4fe5cfc3a3 446 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 114:fe4fe5cfc3a3 447 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 114:fe4fe5cfc3a3 448 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
mbed_official 114:fe4fe5cfc3a3 449 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 114:fe4fe5cfc3a3 450 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 114:fe4fe5cfc3a3 451 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 114:fe4fe5cfc3a3 452 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 114:fe4fe5cfc3a3 453 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
mbed_official 114:fe4fe5cfc3a3 454 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 114:fe4fe5cfc3a3 455 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
mbed_official 114:fe4fe5cfc3a3 456 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 114:fe4fe5cfc3a3 457 } TIM_TypeDef;
mbed_official 114:fe4fe5cfc3a3 458
mbed_official 114:fe4fe5cfc3a3 459 /**
mbed_official 114:fe4fe5cfc3a3 460 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 114:fe4fe5cfc3a3 461 */
mbed_official 114:fe4fe5cfc3a3 462 typedef struct
mbed_official 114:fe4fe5cfc3a3 463 {
mbed_official 114:fe4fe5cfc3a3 464 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 465 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 466 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 467 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 114:fe4fe5cfc3a3 468 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 114:fe4fe5cfc3a3 469 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 114:fe4fe5cfc3a3 470 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 114:fe4fe5cfc3a3 471 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 114:fe4fe5cfc3a3 472 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 114:fe4fe5cfc3a3 473 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 114:fe4fe5cfc3a3 474 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 114:fe4fe5cfc3a3 475 } USART_TypeDef;
mbed_official 114:fe4fe5cfc3a3 476
mbed_official 114:fe4fe5cfc3a3 477 /**
mbed_official 114:fe4fe5cfc3a3 478 * @brief Window WATCHDOG
mbed_official 114:fe4fe5cfc3a3 479 */
mbed_official 114:fe4fe5cfc3a3 480 typedef struct
mbed_official 114:fe4fe5cfc3a3 481 {
mbed_official 114:fe4fe5cfc3a3 482 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 114:fe4fe5cfc3a3 483 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 114:fe4fe5cfc3a3 484 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 114:fe4fe5cfc3a3 485 } WWDG_TypeDef;
mbed_official 114:fe4fe5cfc3a3 486
mbed_official 114:fe4fe5cfc3a3 487
mbed_official 114:fe4fe5cfc3a3 488 /**
mbed_official 114:fe4fe5cfc3a3 489 * @}
mbed_official 114:fe4fe5cfc3a3 490 */
mbed_official 114:fe4fe5cfc3a3 491
mbed_official 114:fe4fe5cfc3a3 492 /** @addtogroup Peripheral_memory_map
mbed_official 114:fe4fe5cfc3a3 493 * @{
mbed_official 114:fe4fe5cfc3a3 494 */
mbed_official 114:fe4fe5cfc3a3 495 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
mbed_official 114:fe4fe5cfc3a3 496 #define FLASH_END ((uint32_t)0x08007FFFU) /*!< FLASH end address in the alias region */
mbed_official 114:fe4fe5cfc3a3 497 #define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
mbed_official 114:fe4fe5cfc3a3 498 #define DATA_EEPROM_END ((uint32_t)0x080803FFU) /*!< DATA EEPROM end address in the alias region */
mbed_official 114:fe4fe5cfc3a3 499 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
<> 151:5eaa88a5bcc7 500 #define SRAM_SIZE_MAX ((uint32_t)0x00002000U) /*!< maximum SRAM size (up to 8KBytes) */
<> 151:5eaa88a5bcc7 501
mbed_official 114:fe4fe5cfc3a3 502 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
mbed_official 114:fe4fe5cfc3a3 503
mbed_official 114:fe4fe5cfc3a3 504 /*!< Peripheral memory map */
mbed_official 114:fe4fe5cfc3a3 505 #define APBPERIPH_BASE PERIPH_BASE
<> 151:5eaa88a5bcc7 506 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 151:5eaa88a5bcc7 507 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U)
<> 151:5eaa88a5bcc7 508
<> 151:5eaa88a5bcc7 509 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000U)
<> 151:5eaa88a5bcc7 510 #define RTC_BASE (APBPERIPH_BASE + 0x00002800U)
<> 151:5eaa88a5bcc7 511 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U)
<> 151:5eaa88a5bcc7 512 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000U)
<> 151:5eaa88a5bcc7 513 #define USART2_BASE (APBPERIPH_BASE + 0x00004400U)
<> 151:5eaa88a5bcc7 514 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U)
<> 151:5eaa88a5bcc7 515 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400U)
<> 151:5eaa88a5bcc7 516 #define PWR_BASE (APBPERIPH_BASE + 0x00007000U)
<> 151:5eaa88a5bcc7 517 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U)
<> 151:5eaa88a5bcc7 518
<> 151:5eaa88a5bcc7 519 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U)
<> 151:5eaa88a5bcc7 520 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018U)
<> 151:5eaa88a5bcc7 521 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU)
mbed_official 114:fe4fe5cfc3a3 522 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
<> 151:5eaa88a5bcc7 523 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400U)
<> 151:5eaa88a5bcc7 524 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800U)
<> 151:5eaa88a5bcc7 525 #define TIM22_BASE (APBPERIPH_BASE + 0x00011400U)
<> 151:5eaa88a5bcc7 526 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400U)
<> 151:5eaa88a5bcc7 527 #define ADC_BASE (APBPERIPH_BASE + 0x00012708U)
<> 151:5eaa88a5bcc7 528 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000U)
<> 151:5eaa88a5bcc7 529 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U)
<> 151:5eaa88a5bcc7 530
<> 151:5eaa88a5bcc7 531 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
<> 151:5eaa88a5bcc7 532 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
<> 151:5eaa88a5bcc7 533 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
<> 151:5eaa88a5bcc7 534 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
<> 151:5eaa88a5bcc7 535 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
<> 151:5eaa88a5bcc7 536 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
<> 151:5eaa88a5bcc7 537 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
<> 151:5eaa88a5bcc7 538 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
<> 151:5eaa88a5bcc7 539 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
<> 151:5eaa88a5bcc7 540
<> 151:5eaa88a5bcc7 541
<> 151:5eaa88a5bcc7 542 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
<> 151:5eaa88a5bcc7 543 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
mbed_official 114:fe4fe5cfc3a3 544 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
<> 151:5eaa88a5bcc7 545 #define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */
<> 151:5eaa88a5bcc7 546 #define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */
<> 151:5eaa88a5bcc7 547 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
<> 151:5eaa88a5bcc7 548
<> 151:5eaa88a5bcc7 549 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U)
<> 151:5eaa88a5bcc7 550 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U)
<> 151:5eaa88a5bcc7 551 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U)
<> 151:5eaa88a5bcc7 552 #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U)
mbed_official 114:fe4fe5cfc3a3 553
mbed_official 114:fe4fe5cfc3a3 554 /**
mbed_official 114:fe4fe5cfc3a3 555 * @}
mbed_official 114:fe4fe5cfc3a3 556 */
mbed_official 114:fe4fe5cfc3a3 557
mbed_official 114:fe4fe5cfc3a3 558 /** @addtogroup Peripheral_declaration
mbed_official 114:fe4fe5cfc3a3 559 * @{
mbed_official 114:fe4fe5cfc3a3 560 */
mbed_official 114:fe4fe5cfc3a3 561
mbed_official 114:fe4fe5cfc3a3 562 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 114:fe4fe5cfc3a3 563 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 114:fe4fe5cfc3a3 564 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 114:fe4fe5cfc3a3 565 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 114:fe4fe5cfc3a3 566 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 114:fe4fe5cfc3a3 567 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
mbed_official 114:fe4fe5cfc3a3 568 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 114:fe4fe5cfc3a3 569 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 114:fe4fe5cfc3a3 570 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
mbed_official 114:fe4fe5cfc3a3 571
mbed_official 114:fe4fe5cfc3a3 572 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 114:fe4fe5cfc3a3 573 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
mbed_official 114:fe4fe5cfc3a3 574 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
mbed_official 114:fe4fe5cfc3a3 575 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 114:fe4fe5cfc3a3 576 #define TIM21 ((TIM_TypeDef *) TIM21_BASE)
mbed_official 114:fe4fe5cfc3a3 577 #define TIM22 ((TIM_TypeDef *) TIM22_BASE)
mbed_official 114:fe4fe5cfc3a3 578 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 114:fe4fe5cfc3a3 579 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 114:fe4fe5cfc3a3 580 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 581 #define ADC ADC1_COMMON
mbed_official 114:fe4fe5cfc3a3 582 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 114:fe4fe5cfc3a3 583 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 114:fe4fe5cfc3a3 584
mbed_official 114:fe4fe5cfc3a3 585 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 114:fe4fe5cfc3a3 586 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 114:fe4fe5cfc3a3 587 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 114:fe4fe5cfc3a3 588 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 114:fe4fe5cfc3a3 589 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 114:fe4fe5cfc3a3 590 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 114:fe4fe5cfc3a3 591 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 114:fe4fe5cfc3a3 592 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 114:fe4fe5cfc3a3 593 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
mbed_official 114:fe4fe5cfc3a3 594
mbed_official 114:fe4fe5cfc3a3 595
mbed_official 114:fe4fe5cfc3a3 596 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 114:fe4fe5cfc3a3 597 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 114:fe4fe5cfc3a3 598 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 114:fe4fe5cfc3a3 599 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 114:fe4fe5cfc3a3 600
mbed_official 114:fe4fe5cfc3a3 601 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 114:fe4fe5cfc3a3 602 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 114:fe4fe5cfc3a3 603 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 114:fe4fe5cfc3a3 604 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 114:fe4fe5cfc3a3 605
mbed_official 114:fe4fe5cfc3a3 606 /**
mbed_official 114:fe4fe5cfc3a3 607 * @}
mbed_official 114:fe4fe5cfc3a3 608 */
mbed_official 114:fe4fe5cfc3a3 609
mbed_official 114:fe4fe5cfc3a3 610 /** @addtogroup Exported_constants
mbed_official 114:fe4fe5cfc3a3 611 * @{
mbed_official 114:fe4fe5cfc3a3 612 */
mbed_official 114:fe4fe5cfc3a3 613
mbed_official 114:fe4fe5cfc3a3 614 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 114:fe4fe5cfc3a3 615 * @{
mbed_official 114:fe4fe5cfc3a3 616 */
mbed_official 114:fe4fe5cfc3a3 617
mbed_official 114:fe4fe5cfc3a3 618 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 619 /* Peripheral Registers Bits Definition */
mbed_official 114:fe4fe5cfc3a3 620 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 621 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 622 /* */
mbed_official 114:fe4fe5cfc3a3 623 /* Analog to Digital Converter (ADC) */
mbed_official 114:fe4fe5cfc3a3 624 /* */
mbed_official 114:fe4fe5cfc3a3 625 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 626 /******************** Bits definition for ADC_ISR register ******************/
<> 151:5eaa88a5bcc7 627 #define ADC_ISR_EOCAL_Pos (11U)
<> 151:5eaa88a5bcc7 628 #define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 629 #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
<> 151:5eaa88a5bcc7 630 #define ADC_ISR_AWD_Pos (7U)
<> 151:5eaa88a5bcc7 631 #define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 632 #define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
<> 151:5eaa88a5bcc7 633 #define ADC_ISR_OVR_Pos (4U)
<> 151:5eaa88a5bcc7 634 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 635 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
<> 151:5eaa88a5bcc7 636 #define ADC_ISR_EOSEQ_Pos (3U)
<> 151:5eaa88a5bcc7 637 #define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 638 #define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
<> 151:5eaa88a5bcc7 639 #define ADC_ISR_EOC_Pos (2U)
<> 151:5eaa88a5bcc7 640 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 641 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
<> 151:5eaa88a5bcc7 642 #define ADC_ISR_EOSMP_Pos (1U)
<> 151:5eaa88a5bcc7 643 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 644 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
<> 151:5eaa88a5bcc7 645 #define ADC_ISR_ADRDY_Pos (0U)
<> 151:5eaa88a5bcc7 646 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 647 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
mbed_official 114:fe4fe5cfc3a3 648
mbed_official 114:fe4fe5cfc3a3 649 /* Old EOSEQ bit definition, maintained for legacy purpose */
mbed_official 114:fe4fe5cfc3a3 650 #define ADC_ISR_EOS ADC_ISR_EOSEQ
mbed_official 114:fe4fe5cfc3a3 651
mbed_official 114:fe4fe5cfc3a3 652 /******************** Bits definition for ADC_IER register ******************/
<> 151:5eaa88a5bcc7 653 #define ADC_IER_EOCALIE_Pos (11U)
<> 151:5eaa88a5bcc7 654 #define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 655 #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
<> 151:5eaa88a5bcc7 656 #define ADC_IER_AWDIE_Pos (7U)
<> 151:5eaa88a5bcc7 657 #define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 658 #define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
<> 151:5eaa88a5bcc7 659 #define ADC_IER_OVRIE_Pos (4U)
<> 151:5eaa88a5bcc7 660 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 661 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
<> 151:5eaa88a5bcc7 662 #define ADC_IER_EOSEQIE_Pos (3U)
<> 151:5eaa88a5bcc7 663 #define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 664 #define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
<> 151:5eaa88a5bcc7 665 #define ADC_IER_EOCIE_Pos (2U)
<> 151:5eaa88a5bcc7 666 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 667 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
<> 151:5eaa88a5bcc7 668 #define ADC_IER_EOSMPIE_Pos (1U)
<> 151:5eaa88a5bcc7 669 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 670 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
<> 151:5eaa88a5bcc7 671 #define ADC_IER_ADRDYIE_Pos (0U)
<> 151:5eaa88a5bcc7 672 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 673 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
mbed_official 114:fe4fe5cfc3a3 674
mbed_official 114:fe4fe5cfc3a3 675 /* Old EOSEQIE bit definition, maintained for legacy purpose */
mbed_official 114:fe4fe5cfc3a3 676 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
mbed_official 114:fe4fe5cfc3a3 677
mbed_official 114:fe4fe5cfc3a3 678 /******************** Bits definition for ADC_CR register *******************/
<> 151:5eaa88a5bcc7 679 #define ADC_CR_ADCAL_Pos (31U)
<> 151:5eaa88a5bcc7 680 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 681 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
<> 151:5eaa88a5bcc7 682 #define ADC_CR_ADVREGEN_Pos (28U)
<> 151:5eaa88a5bcc7 683 #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 684 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
<> 151:5eaa88a5bcc7 685 #define ADC_CR_ADSTP_Pos (4U)
<> 151:5eaa88a5bcc7 686 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 687 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
<> 151:5eaa88a5bcc7 688 #define ADC_CR_ADSTART_Pos (2U)
<> 151:5eaa88a5bcc7 689 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 690 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
<> 151:5eaa88a5bcc7 691 #define ADC_CR_ADDIS_Pos (1U)
<> 151:5eaa88a5bcc7 692 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 693 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
<> 151:5eaa88a5bcc7 694 #define ADC_CR_ADEN_Pos (0U)
<> 151:5eaa88a5bcc7 695 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 696 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
mbed_official 114:fe4fe5cfc3a3 697
mbed_official 114:fe4fe5cfc3a3 698 /******************* Bits definition for ADC_CFGR1 register *****************/
<> 151:5eaa88a5bcc7 699 #define ADC_CFGR1_AWDCH_Pos (26U)
<> 151:5eaa88a5bcc7 700 #define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
<> 151:5eaa88a5bcc7 701 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
<> 151:5eaa88a5bcc7 702 #define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 703 #define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 704 #define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 705 #define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 706 #define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 707 #define ADC_CFGR1_AWDEN_Pos (23U)
<> 151:5eaa88a5bcc7 708 #define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 709 #define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
<> 151:5eaa88a5bcc7 710 #define ADC_CFGR1_AWDSGL_Pos (22U)
<> 151:5eaa88a5bcc7 711 #define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 712 #define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
<> 151:5eaa88a5bcc7 713 #define ADC_CFGR1_DISCEN_Pos (16U)
<> 151:5eaa88a5bcc7 714 #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 715 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
<> 151:5eaa88a5bcc7 716 #define ADC_CFGR1_AUTOFF_Pos (15U)
<> 151:5eaa88a5bcc7 717 #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 718 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
<> 151:5eaa88a5bcc7 719 #define ADC_CFGR1_WAIT_Pos (14U)
<> 151:5eaa88a5bcc7 720 #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 721 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
<> 151:5eaa88a5bcc7 722 #define ADC_CFGR1_CONT_Pos (13U)
<> 151:5eaa88a5bcc7 723 #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 724 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
<> 151:5eaa88a5bcc7 725 #define ADC_CFGR1_OVRMOD_Pos (12U)
<> 151:5eaa88a5bcc7 726 #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 727 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
<> 151:5eaa88a5bcc7 728 #define ADC_CFGR1_EXTEN_Pos (10U)
<> 151:5eaa88a5bcc7 729 #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
<> 151:5eaa88a5bcc7 730 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
<> 151:5eaa88a5bcc7 731 #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 732 #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 733 #define ADC_CFGR1_EXTSEL_Pos (6U)
<> 151:5eaa88a5bcc7 734 #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
<> 151:5eaa88a5bcc7 735 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
<> 151:5eaa88a5bcc7 736 #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 737 #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 738 #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 739 #define ADC_CFGR1_ALIGN_Pos (5U)
<> 151:5eaa88a5bcc7 740 #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 741 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
<> 151:5eaa88a5bcc7 742 #define ADC_CFGR1_RES_Pos (3U)
<> 151:5eaa88a5bcc7 743 #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
<> 151:5eaa88a5bcc7 744 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
<> 151:5eaa88a5bcc7 745 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 746 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 747 #define ADC_CFGR1_SCANDIR_Pos (2U)
<> 151:5eaa88a5bcc7 748 #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 749 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
<> 151:5eaa88a5bcc7 750 #define ADC_CFGR1_DMACFG_Pos (1U)
<> 151:5eaa88a5bcc7 751 #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 752 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
<> 151:5eaa88a5bcc7 753 #define ADC_CFGR1_DMAEN_Pos (0U)
<> 151:5eaa88a5bcc7 754 #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 755 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
mbed_official 114:fe4fe5cfc3a3 756
mbed_official 114:fe4fe5cfc3a3 757 /* Old WAIT bit definition, maintained for legacy purpose */
mbed_official 114:fe4fe5cfc3a3 758 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
mbed_official 114:fe4fe5cfc3a3 759
mbed_official 114:fe4fe5cfc3a3 760 /******************* Bits definition for ADC_CFGR2 register *****************/
<> 151:5eaa88a5bcc7 761 #define ADC_CFGR2_TOVS_Pos (9U)
Anna Bridge 186:707f6e361f3e 762 #define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
<> 151:5eaa88a5bcc7 763 #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
<> 151:5eaa88a5bcc7 764 #define ADC_CFGR2_OVSS_Pos (5U)
<> 151:5eaa88a5bcc7 765 #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
<> 151:5eaa88a5bcc7 766 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
<> 151:5eaa88a5bcc7 767 #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 768 #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 769 #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 770 #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 771 #define ADC_CFGR2_OVSR_Pos (2U)
<> 151:5eaa88a5bcc7 772 #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
<> 151:5eaa88a5bcc7 773 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
<> 151:5eaa88a5bcc7 774 #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 775 #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 776 #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 777 #define ADC_CFGR2_OVSE_Pos (0U)
<> 151:5eaa88a5bcc7 778 #define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 779 #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
<> 151:5eaa88a5bcc7 780 #define ADC_CFGR2_CKMODE_Pos (30U)
<> 151:5eaa88a5bcc7 781 #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
<> 151:5eaa88a5bcc7 782 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
<> 151:5eaa88a5bcc7 783 #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 784 #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
mbed_official 114:fe4fe5cfc3a3 785
mbed_official 114:fe4fe5cfc3a3 786
mbed_official 114:fe4fe5cfc3a3 787 /****************** Bit definition for ADC_SMPR register ********************/
<> 151:5eaa88a5bcc7 788 #define ADC_SMPR_SMP_Pos (0U)
<> 151:5eaa88a5bcc7 789 #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
<> 151:5eaa88a5bcc7 790 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
<> 151:5eaa88a5bcc7 791 #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 792 #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 793 #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
mbed_official 114:fe4fe5cfc3a3 794
mbed_official 114:fe4fe5cfc3a3 795 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 796 #define ADC_SMPR_SMPR ADC_SMPR_SMP
mbed_official 114:fe4fe5cfc3a3 797 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
mbed_official 114:fe4fe5cfc3a3 798 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
mbed_official 114:fe4fe5cfc3a3 799 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
mbed_official 114:fe4fe5cfc3a3 800
mbed_official 114:fe4fe5cfc3a3 801 /******************* Bit definition for ADC_TR register ********************/
<> 151:5eaa88a5bcc7 802 #define ADC_TR_HT_Pos (16U)
<> 151:5eaa88a5bcc7 803 #define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
<> 151:5eaa88a5bcc7 804 #define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
<> 151:5eaa88a5bcc7 805 #define ADC_TR_LT_Pos (0U)
<> 151:5eaa88a5bcc7 806 #define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */
<> 151:5eaa88a5bcc7 807 #define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
mbed_official 114:fe4fe5cfc3a3 808
mbed_official 114:fe4fe5cfc3a3 809 /****************** Bit definition for ADC_CHSELR register ******************/
<> 151:5eaa88a5bcc7 810 #define ADC_CHSELR_CHSEL_Pos (0U)
<> 151:5eaa88a5bcc7 811 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
<> 151:5eaa88a5bcc7 812 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
<> 151:5eaa88a5bcc7 813 #define ADC_CHSELR_CHSEL18_Pos (18U)
<> 151:5eaa88a5bcc7 814 #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 815 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
<> 151:5eaa88a5bcc7 816 #define ADC_CHSELR_CHSEL17_Pos (17U)
<> 151:5eaa88a5bcc7 817 #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 818 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
<> 151:5eaa88a5bcc7 819 #define ADC_CHSELR_CHSEL15_Pos (15U)
<> 151:5eaa88a5bcc7 820 #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 821 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
<> 151:5eaa88a5bcc7 822 #define ADC_CHSELR_CHSEL14_Pos (14U)
<> 151:5eaa88a5bcc7 823 #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 824 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
<> 151:5eaa88a5bcc7 825 #define ADC_CHSELR_CHSEL13_Pos (13U)
<> 151:5eaa88a5bcc7 826 #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 827 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
<> 151:5eaa88a5bcc7 828 #define ADC_CHSELR_CHSEL12_Pos (12U)
<> 151:5eaa88a5bcc7 829 #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 830 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
<> 151:5eaa88a5bcc7 831 #define ADC_CHSELR_CHSEL11_Pos (11U)
<> 151:5eaa88a5bcc7 832 #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 833 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
<> 151:5eaa88a5bcc7 834 #define ADC_CHSELR_CHSEL10_Pos (10U)
<> 151:5eaa88a5bcc7 835 #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 836 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
<> 151:5eaa88a5bcc7 837 #define ADC_CHSELR_CHSEL9_Pos (9U)
<> 151:5eaa88a5bcc7 838 #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 839 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
<> 151:5eaa88a5bcc7 840 #define ADC_CHSELR_CHSEL8_Pos (8U)
<> 151:5eaa88a5bcc7 841 #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 842 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
<> 151:5eaa88a5bcc7 843 #define ADC_CHSELR_CHSEL7_Pos (7U)
<> 151:5eaa88a5bcc7 844 #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 845 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
<> 151:5eaa88a5bcc7 846 #define ADC_CHSELR_CHSEL6_Pos (6U)
<> 151:5eaa88a5bcc7 847 #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 848 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
<> 151:5eaa88a5bcc7 849 #define ADC_CHSELR_CHSEL5_Pos (5U)
<> 151:5eaa88a5bcc7 850 #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 851 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
<> 151:5eaa88a5bcc7 852 #define ADC_CHSELR_CHSEL4_Pos (4U)
<> 151:5eaa88a5bcc7 853 #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 854 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
<> 151:5eaa88a5bcc7 855 #define ADC_CHSELR_CHSEL3_Pos (3U)
<> 151:5eaa88a5bcc7 856 #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 857 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
<> 151:5eaa88a5bcc7 858 #define ADC_CHSELR_CHSEL2_Pos (2U)
<> 151:5eaa88a5bcc7 859 #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 860 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
<> 151:5eaa88a5bcc7 861 #define ADC_CHSELR_CHSEL1_Pos (1U)
<> 151:5eaa88a5bcc7 862 #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 863 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
<> 151:5eaa88a5bcc7 864 #define ADC_CHSELR_CHSEL0_Pos (0U)
<> 151:5eaa88a5bcc7 865 #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 866 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
mbed_official 114:fe4fe5cfc3a3 867
mbed_official 114:fe4fe5cfc3a3 868 /******************** Bit definition for ADC_DR register ********************/
<> 151:5eaa88a5bcc7 869 #define ADC_DR_DATA_Pos (0U)
<> 151:5eaa88a5bcc7 870 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 871 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
mbed_official 114:fe4fe5cfc3a3 872
mbed_official 114:fe4fe5cfc3a3 873 /******************** Bit definition for ADC_CALFACT register ********************/
<> 151:5eaa88a5bcc7 874 #define ADC_CALFACT_CALFACT_Pos (0U)
<> 151:5eaa88a5bcc7 875 #define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
<> 151:5eaa88a5bcc7 876 #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
mbed_official 114:fe4fe5cfc3a3 877
mbed_official 114:fe4fe5cfc3a3 878 /******************* Bit definition for ADC_CCR register ********************/
<> 151:5eaa88a5bcc7 879 #define ADC_CCR_LFMEN_Pos (25U)
<> 151:5eaa88a5bcc7 880 #define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 881 #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
<> 151:5eaa88a5bcc7 882 #define ADC_CCR_TSEN_Pos (23U)
<> 151:5eaa88a5bcc7 883 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 884 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
<> 151:5eaa88a5bcc7 885 #define ADC_CCR_VREFEN_Pos (22U)
<> 151:5eaa88a5bcc7 886 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 887 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
<> 151:5eaa88a5bcc7 888 #define ADC_CCR_PRESC_Pos (18U)
<> 151:5eaa88a5bcc7 889 #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
<> 151:5eaa88a5bcc7 890 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
<> 151:5eaa88a5bcc7 891 #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 892 #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 893 #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 894 #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
mbed_official 114:fe4fe5cfc3a3 895
mbed_official 114:fe4fe5cfc3a3 896 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 897 /* */
mbed_official 114:fe4fe5cfc3a3 898 /* Analog Comparators (COMP) */
mbed_official 114:fe4fe5cfc3a3 899 /* */
mbed_official 114:fe4fe5cfc3a3 900 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 901 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
mbed_official 114:fe4fe5cfc3a3 902 /* COMP1 bits definition */
<> 151:5eaa88a5bcc7 903 #define COMP_CSR_COMP1EN_Pos (0U)
<> 151:5eaa88a5bcc7 904 #define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 905 #define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
<> 151:5eaa88a5bcc7 906 #define COMP_CSR_COMP1INNSEL_Pos (4U)
<> 151:5eaa88a5bcc7 907 #define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
<> 151:5eaa88a5bcc7 908 #define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
<> 151:5eaa88a5bcc7 909 #define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 910 #define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 911 #define COMP_CSR_COMP1WM_Pos (8U)
<> 151:5eaa88a5bcc7 912 #define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 913 #define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
<> 151:5eaa88a5bcc7 914 #define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
<> 151:5eaa88a5bcc7 915 #define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 916 #define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
<> 151:5eaa88a5bcc7 917 #define COMP_CSR_COMP1POLARITY_Pos (15U)
<> 151:5eaa88a5bcc7 918 #define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 919 #define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
<> 151:5eaa88a5bcc7 920 #define COMP_CSR_COMP1VALUE_Pos (30U)
<> 151:5eaa88a5bcc7 921 #define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 922 #define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
<> 151:5eaa88a5bcc7 923 #define COMP_CSR_COMP1LOCK_Pos (31U)
<> 151:5eaa88a5bcc7 924 #define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 925 #define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
mbed_official 114:fe4fe5cfc3a3 926 /* COMP2 bits definition */
<> 151:5eaa88a5bcc7 927 #define COMP_CSR_COMP2EN_Pos (0U)
<> 151:5eaa88a5bcc7 928 #define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 929 #define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
<> 151:5eaa88a5bcc7 930 #define COMP_CSR_COMP2SPEED_Pos (3U)
<> 151:5eaa88a5bcc7 931 #define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 932 #define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
<> 151:5eaa88a5bcc7 933 #define COMP_CSR_COMP2INNSEL_Pos (4U)
<> 151:5eaa88a5bcc7 934 #define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
<> 151:5eaa88a5bcc7 935 #define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
<> 151:5eaa88a5bcc7 936 #define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 937 #define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 938 #define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 939 #define COMP_CSR_COMP2INPSEL_Pos (8U)
<> 151:5eaa88a5bcc7 940 #define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
<> 151:5eaa88a5bcc7 941 #define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
<> 151:5eaa88a5bcc7 942 #define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 943 #define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 944 #define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 945 #define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
<> 151:5eaa88a5bcc7 946 #define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 947 #define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
<> 151:5eaa88a5bcc7 948 #define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
<> 151:5eaa88a5bcc7 949 #define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 950 #define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
<> 151:5eaa88a5bcc7 951 #define COMP_CSR_COMP2POLARITY_Pos (15U)
<> 151:5eaa88a5bcc7 952 #define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 953 #define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
<> 151:5eaa88a5bcc7 954 #define COMP_CSR_COMP2VALUE_Pos (30U)
<> 151:5eaa88a5bcc7 955 #define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 956 #define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
<> 151:5eaa88a5bcc7 957 #define COMP_CSR_COMP2LOCK_Pos (31U)
<> 151:5eaa88a5bcc7 958 #define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 959 #define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
mbed_official 114:fe4fe5cfc3a3 960
mbed_official 114:fe4fe5cfc3a3 961 /********************** Bit definition for COMP_CSR register common ****************/
<> 151:5eaa88a5bcc7 962 #define COMP_CSR_COMPxEN_Pos (0U)
<> 151:5eaa88a5bcc7 963 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 964 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
<> 151:5eaa88a5bcc7 965 #define COMP_CSR_COMPxPOLARITY_Pos (15U)
<> 151:5eaa88a5bcc7 966 #define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 967 #define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
<> 151:5eaa88a5bcc7 968 #define COMP_CSR_COMPxOUTVALUE_Pos (30U)
<> 151:5eaa88a5bcc7 969 #define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 970 #define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
<> 151:5eaa88a5bcc7 971 #define COMP_CSR_COMPxLOCK_Pos (31U)
<> 151:5eaa88a5bcc7 972 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 973 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
mbed_official 114:fe4fe5cfc3a3 974
mbed_official 114:fe4fe5cfc3a3 975 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 976 #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
mbed_official 114:fe4fe5cfc3a3 977
mbed_official 114:fe4fe5cfc3a3 978 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 979 /* */
mbed_official 114:fe4fe5cfc3a3 980 /* CRC calculation unit (CRC) */
mbed_official 114:fe4fe5cfc3a3 981 /* */
mbed_official 114:fe4fe5cfc3a3 982 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 983 /******************* Bit definition for CRC_DR register *********************/
<> 151:5eaa88a5bcc7 984 #define CRC_DR_DR_Pos (0U)
<> 151:5eaa88a5bcc7 985 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 986 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
mbed_official 114:fe4fe5cfc3a3 987
mbed_official 114:fe4fe5cfc3a3 988 /******************* Bit definition for CRC_IDR register ********************/
<> 151:5eaa88a5bcc7 989 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
mbed_official 114:fe4fe5cfc3a3 990
mbed_official 114:fe4fe5cfc3a3 991 /******************** Bit definition for CRC_CR register ********************/
<> 151:5eaa88a5bcc7 992 #define CRC_CR_RESET_Pos (0U)
<> 151:5eaa88a5bcc7 993 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 994 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
<> 151:5eaa88a5bcc7 995 #define CRC_CR_POLYSIZE_Pos (3U)
<> 151:5eaa88a5bcc7 996 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
<> 151:5eaa88a5bcc7 997 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
<> 151:5eaa88a5bcc7 998 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 999 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1000 #define CRC_CR_REV_IN_Pos (5U)
<> 151:5eaa88a5bcc7 1001 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
<> 151:5eaa88a5bcc7 1002 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
<> 151:5eaa88a5bcc7 1003 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1004 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1005 #define CRC_CR_REV_OUT_Pos (7U)
<> 151:5eaa88a5bcc7 1006 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 1007 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
mbed_official 114:fe4fe5cfc3a3 1008
mbed_official 114:fe4fe5cfc3a3 1009 /******************* Bit definition for CRC_INIT register *******************/
<> 151:5eaa88a5bcc7 1010 #define CRC_INIT_INIT_Pos (0U)
<> 151:5eaa88a5bcc7 1011 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 1012 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
mbed_official 114:fe4fe5cfc3a3 1013
mbed_official 114:fe4fe5cfc3a3 1014 /******************* Bit definition for CRC_POL register ********************/
<> 151:5eaa88a5bcc7 1015 #define CRC_POL_POL_Pos (0U)
<> 151:5eaa88a5bcc7 1016 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 1017 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
mbed_official 114:fe4fe5cfc3a3 1018
mbed_official 114:fe4fe5cfc3a3 1019 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 1020 /* */
mbed_official 114:fe4fe5cfc3a3 1021 /* Debug MCU (DBGMCU) */
mbed_official 114:fe4fe5cfc3a3 1022 /* */
mbed_official 114:fe4fe5cfc3a3 1023 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 1024
mbed_official 114:fe4fe5cfc3a3 1025 /**************** Bit definition for DBGMCU_IDCODE register *****************/
<> 151:5eaa88a5bcc7 1026 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
<> 151:5eaa88a5bcc7 1027 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
<> 151:5eaa88a5bcc7 1028 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
<> 151:5eaa88a5bcc7 1029
<> 151:5eaa88a5bcc7 1030 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
<> 151:5eaa88a5bcc7 1031 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
<> 151:5eaa88a5bcc7 1032 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
<> 151:5eaa88a5bcc7 1033 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 1034 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 1035 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 1036 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 1037 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 1038 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 1039 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 1040 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 1041 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 1042 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 1043 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 1044 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 1045 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 1046 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 1047 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 1048 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
mbed_official 114:fe4fe5cfc3a3 1049
mbed_official 114:fe4fe5cfc3a3 1050 /****************** Bit definition for DBGMCU_CR register *******************/
<> 151:5eaa88a5bcc7 1051 #define DBGMCU_CR_DBG_Pos (0U)
<> 151:5eaa88a5bcc7 1052 #define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
<> 151:5eaa88a5bcc7 1053 #define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
<> 151:5eaa88a5bcc7 1054 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
<> 151:5eaa88a5bcc7 1055 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1056 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
<> 151:5eaa88a5bcc7 1057 #define DBGMCU_CR_DBG_STOP_Pos (1U)
<> 151:5eaa88a5bcc7 1058 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1059 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
<> 151:5eaa88a5bcc7 1060 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
<> 151:5eaa88a5bcc7 1061 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1062 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
mbed_official 114:fe4fe5cfc3a3 1063
mbed_official 114:fe4fe5cfc3a3 1064 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
<> 151:5eaa88a5bcc7 1065 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
<> 151:5eaa88a5bcc7 1066 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1067 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
<> 151:5eaa88a5bcc7 1068 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
<> 151:5eaa88a5bcc7 1069 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1070 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
<> 151:5eaa88a5bcc7 1071 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
<> 151:5eaa88a5bcc7 1072 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 1073 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
<> 151:5eaa88a5bcc7 1074 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
<> 151:5eaa88a5bcc7 1075 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 1076 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
<> 151:5eaa88a5bcc7 1077 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
<> 151:5eaa88a5bcc7 1078 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 1079 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
<> 151:5eaa88a5bcc7 1080 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
<> 151:5eaa88a5bcc7 1081 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 1082 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
mbed_official 114:fe4fe5cfc3a3 1083 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
<> 151:5eaa88a5bcc7 1084 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
<> 151:5eaa88a5bcc7 1085 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1086 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
<> 151:5eaa88a5bcc7 1087 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
<> 151:5eaa88a5bcc7 1088 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1089 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
mbed_official 114:fe4fe5cfc3a3 1090
mbed_official 114:fe4fe5cfc3a3 1091 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 1092 /* */
mbed_official 114:fe4fe5cfc3a3 1093 /* DMA Controller (DMA) */
mbed_official 114:fe4fe5cfc3a3 1094 /* */
mbed_official 114:fe4fe5cfc3a3 1095 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 1096
mbed_official 114:fe4fe5cfc3a3 1097 /******************* Bit definition for DMA_ISR register ********************/
<> 151:5eaa88a5bcc7 1098 #define DMA_ISR_GIF1_Pos (0U)
<> 151:5eaa88a5bcc7 1099 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1100 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
<> 151:5eaa88a5bcc7 1101 #define DMA_ISR_TCIF1_Pos (1U)
<> 151:5eaa88a5bcc7 1102 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1103 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
<> 151:5eaa88a5bcc7 1104 #define DMA_ISR_HTIF1_Pos (2U)
<> 151:5eaa88a5bcc7 1105 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1106 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
<> 151:5eaa88a5bcc7 1107 #define DMA_ISR_TEIF1_Pos (3U)
<> 151:5eaa88a5bcc7 1108 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1109 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
<> 151:5eaa88a5bcc7 1110 #define DMA_ISR_GIF2_Pos (4U)
<> 151:5eaa88a5bcc7 1111 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1112 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
<> 151:5eaa88a5bcc7 1113 #define DMA_ISR_TCIF2_Pos (5U)
<> 151:5eaa88a5bcc7 1114 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1115 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
<> 151:5eaa88a5bcc7 1116 #define DMA_ISR_HTIF2_Pos (6U)
<> 151:5eaa88a5bcc7 1117 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1118 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
<> 151:5eaa88a5bcc7 1119 #define DMA_ISR_TEIF2_Pos (7U)
<> 151:5eaa88a5bcc7 1120 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 1121 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
<> 151:5eaa88a5bcc7 1122 #define DMA_ISR_GIF3_Pos (8U)
<> 151:5eaa88a5bcc7 1123 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 1124 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
<> 151:5eaa88a5bcc7 1125 #define DMA_ISR_TCIF3_Pos (9U)
<> 151:5eaa88a5bcc7 1126 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 1127 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
<> 151:5eaa88a5bcc7 1128 #define DMA_ISR_HTIF3_Pos (10U)
<> 151:5eaa88a5bcc7 1129 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1130 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
<> 151:5eaa88a5bcc7 1131 #define DMA_ISR_TEIF3_Pos (11U)
<> 151:5eaa88a5bcc7 1132 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 1133 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
<> 151:5eaa88a5bcc7 1134 #define DMA_ISR_GIF4_Pos (12U)
<> 151:5eaa88a5bcc7 1135 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 1136 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
<> 151:5eaa88a5bcc7 1137 #define DMA_ISR_TCIF4_Pos (13U)
<> 151:5eaa88a5bcc7 1138 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 1139 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
<> 151:5eaa88a5bcc7 1140 #define DMA_ISR_HTIF4_Pos (14U)
<> 151:5eaa88a5bcc7 1141 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 1142 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
<> 151:5eaa88a5bcc7 1143 #define DMA_ISR_TEIF4_Pos (15U)
<> 151:5eaa88a5bcc7 1144 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 1145 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
<> 151:5eaa88a5bcc7 1146 #define DMA_ISR_GIF5_Pos (16U)
<> 151:5eaa88a5bcc7 1147 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 1148 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
<> 151:5eaa88a5bcc7 1149 #define DMA_ISR_TCIF5_Pos (17U)
<> 151:5eaa88a5bcc7 1150 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 1151 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
<> 151:5eaa88a5bcc7 1152 #define DMA_ISR_HTIF5_Pos (18U)
<> 151:5eaa88a5bcc7 1153 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 1154 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
<> 151:5eaa88a5bcc7 1155 #define DMA_ISR_TEIF5_Pos (19U)
<> 151:5eaa88a5bcc7 1156 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 1157 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
<> 151:5eaa88a5bcc7 1158 #define DMA_ISR_GIF6_Pos (20U)
<> 151:5eaa88a5bcc7 1159 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 1160 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
<> 151:5eaa88a5bcc7 1161 #define DMA_ISR_TCIF6_Pos (21U)
<> 151:5eaa88a5bcc7 1162 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 1163 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
<> 151:5eaa88a5bcc7 1164 #define DMA_ISR_HTIF6_Pos (22U)
<> 151:5eaa88a5bcc7 1165 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 1166 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
<> 151:5eaa88a5bcc7 1167 #define DMA_ISR_TEIF6_Pos (23U)
<> 151:5eaa88a5bcc7 1168 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 1169 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
<> 151:5eaa88a5bcc7 1170 #define DMA_ISR_GIF7_Pos (24U)
<> 151:5eaa88a5bcc7 1171 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 1172 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
<> 151:5eaa88a5bcc7 1173 #define DMA_ISR_TCIF7_Pos (25U)
<> 151:5eaa88a5bcc7 1174 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 1175 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
<> 151:5eaa88a5bcc7 1176 #define DMA_ISR_HTIF7_Pos (26U)
<> 151:5eaa88a5bcc7 1177 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 1178 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
<> 151:5eaa88a5bcc7 1179 #define DMA_ISR_TEIF7_Pos (27U)
<> 151:5eaa88a5bcc7 1180 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 1181 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
mbed_official 114:fe4fe5cfc3a3 1182
mbed_official 114:fe4fe5cfc3a3 1183 /******************* Bit definition for DMA_IFCR register *******************/
<> 151:5eaa88a5bcc7 1184 #define DMA_IFCR_CGIF1_Pos (0U)
<> 151:5eaa88a5bcc7 1185 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1186 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
<> 151:5eaa88a5bcc7 1187 #define DMA_IFCR_CTCIF1_Pos (1U)
<> 151:5eaa88a5bcc7 1188 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1189 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
<> 151:5eaa88a5bcc7 1190 #define DMA_IFCR_CHTIF1_Pos (2U)
<> 151:5eaa88a5bcc7 1191 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1192 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
<> 151:5eaa88a5bcc7 1193 #define DMA_IFCR_CTEIF1_Pos (3U)
<> 151:5eaa88a5bcc7 1194 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1195 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
<> 151:5eaa88a5bcc7 1196 #define DMA_IFCR_CGIF2_Pos (4U)
<> 151:5eaa88a5bcc7 1197 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1198 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
<> 151:5eaa88a5bcc7 1199 #define DMA_IFCR_CTCIF2_Pos (5U)
<> 151:5eaa88a5bcc7 1200 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1201 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
<> 151:5eaa88a5bcc7 1202 #define DMA_IFCR_CHTIF2_Pos (6U)
<> 151:5eaa88a5bcc7 1203 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1204 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
<> 151:5eaa88a5bcc7 1205 #define DMA_IFCR_CTEIF2_Pos (7U)
<> 151:5eaa88a5bcc7 1206 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 1207 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
<> 151:5eaa88a5bcc7 1208 #define DMA_IFCR_CGIF3_Pos (8U)
<> 151:5eaa88a5bcc7 1209 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 1210 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
<> 151:5eaa88a5bcc7 1211 #define DMA_IFCR_CTCIF3_Pos (9U)
<> 151:5eaa88a5bcc7 1212 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 1213 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
<> 151:5eaa88a5bcc7 1214 #define DMA_IFCR_CHTIF3_Pos (10U)
<> 151:5eaa88a5bcc7 1215 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1216 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
<> 151:5eaa88a5bcc7 1217 #define DMA_IFCR_CTEIF3_Pos (11U)
<> 151:5eaa88a5bcc7 1218 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 1219 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
<> 151:5eaa88a5bcc7 1220 #define DMA_IFCR_CGIF4_Pos (12U)
<> 151:5eaa88a5bcc7 1221 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 1222 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
<> 151:5eaa88a5bcc7 1223 #define DMA_IFCR_CTCIF4_Pos (13U)
<> 151:5eaa88a5bcc7 1224 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 1225 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
<> 151:5eaa88a5bcc7 1226 #define DMA_IFCR_CHTIF4_Pos (14U)
<> 151:5eaa88a5bcc7 1227 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 1228 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
<> 151:5eaa88a5bcc7 1229 #define DMA_IFCR_CTEIF4_Pos (15U)
<> 151:5eaa88a5bcc7 1230 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 1231 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
<> 151:5eaa88a5bcc7 1232 #define DMA_IFCR_CGIF5_Pos (16U)
<> 151:5eaa88a5bcc7 1233 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 1234 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
<> 151:5eaa88a5bcc7 1235 #define DMA_IFCR_CTCIF5_Pos (17U)
<> 151:5eaa88a5bcc7 1236 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 1237 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
<> 151:5eaa88a5bcc7 1238 #define DMA_IFCR_CHTIF5_Pos (18U)
<> 151:5eaa88a5bcc7 1239 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 1240 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
<> 151:5eaa88a5bcc7 1241 #define DMA_IFCR_CTEIF5_Pos (19U)
<> 151:5eaa88a5bcc7 1242 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 1243 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
<> 151:5eaa88a5bcc7 1244 #define DMA_IFCR_CGIF6_Pos (20U)
<> 151:5eaa88a5bcc7 1245 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 1246 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
<> 151:5eaa88a5bcc7 1247 #define DMA_IFCR_CTCIF6_Pos (21U)
<> 151:5eaa88a5bcc7 1248 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 1249 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
<> 151:5eaa88a5bcc7 1250 #define DMA_IFCR_CHTIF6_Pos (22U)
<> 151:5eaa88a5bcc7 1251 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 1252 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
<> 151:5eaa88a5bcc7 1253 #define DMA_IFCR_CTEIF6_Pos (23U)
<> 151:5eaa88a5bcc7 1254 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 1255 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
<> 151:5eaa88a5bcc7 1256 #define DMA_IFCR_CGIF7_Pos (24U)
<> 151:5eaa88a5bcc7 1257 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 1258 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
<> 151:5eaa88a5bcc7 1259 #define DMA_IFCR_CTCIF7_Pos (25U)
<> 151:5eaa88a5bcc7 1260 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 1261 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
<> 151:5eaa88a5bcc7 1262 #define DMA_IFCR_CHTIF7_Pos (26U)
<> 151:5eaa88a5bcc7 1263 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 1264 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
<> 151:5eaa88a5bcc7 1265 #define DMA_IFCR_CTEIF7_Pos (27U)
<> 151:5eaa88a5bcc7 1266 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 1267 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
mbed_official 114:fe4fe5cfc3a3 1268
mbed_official 114:fe4fe5cfc3a3 1269 /******************* Bit definition for DMA_CCR register ********************/
<> 151:5eaa88a5bcc7 1270 #define DMA_CCR_EN_Pos (0U)
<> 151:5eaa88a5bcc7 1271 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1272 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
<> 151:5eaa88a5bcc7 1273 #define DMA_CCR_TCIE_Pos (1U)
<> 151:5eaa88a5bcc7 1274 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1275 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 151:5eaa88a5bcc7 1276 #define DMA_CCR_HTIE_Pos (2U)
<> 151:5eaa88a5bcc7 1277 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1278 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
<> 151:5eaa88a5bcc7 1279 #define DMA_CCR_TEIE_Pos (3U)
<> 151:5eaa88a5bcc7 1280 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1281 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
<> 151:5eaa88a5bcc7 1282 #define DMA_CCR_DIR_Pos (4U)
<> 151:5eaa88a5bcc7 1283 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1284 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
<> 151:5eaa88a5bcc7 1285 #define DMA_CCR_CIRC_Pos (5U)
<> 151:5eaa88a5bcc7 1286 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1287 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
<> 151:5eaa88a5bcc7 1288 #define DMA_CCR_PINC_Pos (6U)
<> 151:5eaa88a5bcc7 1289 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1290 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
<> 151:5eaa88a5bcc7 1291 #define DMA_CCR_MINC_Pos (7U)
<> 151:5eaa88a5bcc7 1292 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 1293 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
<> 151:5eaa88a5bcc7 1294
<> 151:5eaa88a5bcc7 1295 #define DMA_CCR_PSIZE_Pos (8U)
<> 151:5eaa88a5bcc7 1296 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
<> 151:5eaa88a5bcc7 1297 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
<> 151:5eaa88a5bcc7 1298 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 1299 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 1300
<> 151:5eaa88a5bcc7 1301 #define DMA_CCR_MSIZE_Pos (10U)
<> 151:5eaa88a5bcc7 1302 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
<> 151:5eaa88a5bcc7 1303 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
<> 151:5eaa88a5bcc7 1304 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1305 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 1306
<> 151:5eaa88a5bcc7 1307 #define DMA_CCR_PL_Pos (12U)
<> 151:5eaa88a5bcc7 1308 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
<> 151:5eaa88a5bcc7 1309 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
<> 151:5eaa88a5bcc7 1310 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 1311 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 1312
<> 151:5eaa88a5bcc7 1313 #define DMA_CCR_MEM2MEM_Pos (14U)
<> 151:5eaa88a5bcc7 1314 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 1315 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
mbed_official 114:fe4fe5cfc3a3 1316
mbed_official 114:fe4fe5cfc3a3 1317 /****************** Bit definition for DMA_CNDTR register *******************/
<> 151:5eaa88a5bcc7 1318 #define DMA_CNDTR_NDT_Pos (0U)
<> 151:5eaa88a5bcc7 1319 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 1320 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
mbed_official 114:fe4fe5cfc3a3 1321
mbed_official 114:fe4fe5cfc3a3 1322 /****************** Bit definition for DMA_CPAR register ********************/
<> 151:5eaa88a5bcc7 1323 #define DMA_CPAR_PA_Pos (0U)
<> 151:5eaa88a5bcc7 1324 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 1325 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
mbed_official 114:fe4fe5cfc3a3 1326
mbed_official 114:fe4fe5cfc3a3 1327 /****************** Bit definition for DMA_CMAR register ********************/
<> 151:5eaa88a5bcc7 1328 #define DMA_CMAR_MA_Pos (0U)
<> 151:5eaa88a5bcc7 1329 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 1330 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
mbed_official 114:fe4fe5cfc3a3 1331
mbed_official 114:fe4fe5cfc3a3 1332
mbed_official 114:fe4fe5cfc3a3 1333 /******************* Bit definition for DMA_CSELR register *******************/
<> 151:5eaa88a5bcc7 1334 #define DMA_CSELR_C1S_Pos (0U)
<> 151:5eaa88a5bcc7 1335 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 1336 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
<> 151:5eaa88a5bcc7 1337 #define DMA_CSELR_C2S_Pos (4U)
<> 151:5eaa88a5bcc7 1338 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
<> 151:5eaa88a5bcc7 1339 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
<> 151:5eaa88a5bcc7 1340 #define DMA_CSELR_C3S_Pos (8U)
<> 151:5eaa88a5bcc7 1341 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 1342 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
<> 151:5eaa88a5bcc7 1343 #define DMA_CSELR_C4S_Pos (12U)
<> 151:5eaa88a5bcc7 1344 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
<> 151:5eaa88a5bcc7 1345 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
<> 151:5eaa88a5bcc7 1346 #define DMA_CSELR_C5S_Pos (16U)
<> 151:5eaa88a5bcc7 1347 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
<> 151:5eaa88a5bcc7 1348 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
<> 151:5eaa88a5bcc7 1349 #define DMA_CSELR_C6S_Pos (20U)
<> 151:5eaa88a5bcc7 1350 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
<> 151:5eaa88a5bcc7 1351 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
<> 151:5eaa88a5bcc7 1352 #define DMA_CSELR_C7S_Pos (24U)
<> 151:5eaa88a5bcc7 1353 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
<> 151:5eaa88a5bcc7 1354 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
mbed_official 114:fe4fe5cfc3a3 1355
mbed_official 114:fe4fe5cfc3a3 1356 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 1357 /* */
mbed_official 114:fe4fe5cfc3a3 1358 /* External Interrupt/Event Controller (EXTI) */
mbed_official 114:fe4fe5cfc3a3 1359 /* */
mbed_official 114:fe4fe5cfc3a3 1360 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 1361
mbed_official 114:fe4fe5cfc3a3 1362 /******************* Bit definition for EXTI_IMR register *******************/
<> 151:5eaa88a5bcc7 1363 #define EXTI_IMR_IM0_Pos (0U)
<> 151:5eaa88a5bcc7 1364 #define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1365 #define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
<> 151:5eaa88a5bcc7 1366 #define EXTI_IMR_IM1_Pos (1U)
<> 151:5eaa88a5bcc7 1367 #define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1368 #define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
<> 151:5eaa88a5bcc7 1369 #define EXTI_IMR_IM2_Pos (2U)
<> 151:5eaa88a5bcc7 1370 #define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1371 #define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
<> 151:5eaa88a5bcc7 1372 #define EXTI_IMR_IM3_Pos (3U)
<> 151:5eaa88a5bcc7 1373 #define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1374 #define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
<> 151:5eaa88a5bcc7 1375 #define EXTI_IMR_IM4_Pos (4U)
<> 151:5eaa88a5bcc7 1376 #define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1377 #define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
<> 151:5eaa88a5bcc7 1378 #define EXTI_IMR_IM5_Pos (5U)
<> 151:5eaa88a5bcc7 1379 #define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1380 #define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
<> 151:5eaa88a5bcc7 1381 #define EXTI_IMR_IM6_Pos (6U)
<> 151:5eaa88a5bcc7 1382 #define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1383 #define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
<> 151:5eaa88a5bcc7 1384 #define EXTI_IMR_IM7_Pos (7U)
<> 151:5eaa88a5bcc7 1385 #define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 1386 #define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
<> 151:5eaa88a5bcc7 1387 #define EXTI_IMR_IM8_Pos (8U)
<> 151:5eaa88a5bcc7 1388 #define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 1389 #define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
<> 151:5eaa88a5bcc7 1390 #define EXTI_IMR_IM9_Pos (9U)
<> 151:5eaa88a5bcc7 1391 #define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 1392 #define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
<> 151:5eaa88a5bcc7 1393 #define EXTI_IMR_IM10_Pos (10U)
<> 151:5eaa88a5bcc7 1394 #define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1395 #define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
<> 151:5eaa88a5bcc7 1396 #define EXTI_IMR_IM11_Pos (11U)
<> 151:5eaa88a5bcc7 1397 #define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 1398 #define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
<> 151:5eaa88a5bcc7 1399 #define EXTI_IMR_IM12_Pos (12U)
<> 151:5eaa88a5bcc7 1400 #define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 1401 #define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
<> 151:5eaa88a5bcc7 1402 #define EXTI_IMR_IM13_Pos (13U)
<> 151:5eaa88a5bcc7 1403 #define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 1404 #define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
<> 151:5eaa88a5bcc7 1405 #define EXTI_IMR_IM14_Pos (14U)
<> 151:5eaa88a5bcc7 1406 #define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 1407 #define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
<> 151:5eaa88a5bcc7 1408 #define EXTI_IMR_IM15_Pos (15U)
<> 151:5eaa88a5bcc7 1409 #define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 1410 #define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
<> 151:5eaa88a5bcc7 1411 #define EXTI_IMR_IM16_Pos (16U)
<> 151:5eaa88a5bcc7 1412 #define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 1413 #define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
<> 151:5eaa88a5bcc7 1414 #define EXTI_IMR_IM17_Pos (17U)
<> 151:5eaa88a5bcc7 1415 #define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 1416 #define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
<> 151:5eaa88a5bcc7 1417 #define EXTI_IMR_IM18_Pos (18U)
<> 151:5eaa88a5bcc7 1418 #define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 1419 #define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
<> 151:5eaa88a5bcc7 1420 #define EXTI_IMR_IM19_Pos (19U)
<> 151:5eaa88a5bcc7 1421 #define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 1422 #define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
<> 151:5eaa88a5bcc7 1423 #define EXTI_IMR_IM20_Pos (20U)
<> 151:5eaa88a5bcc7 1424 #define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 1425 #define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
<> 151:5eaa88a5bcc7 1426 #define EXTI_IMR_IM21_Pos (21U)
<> 151:5eaa88a5bcc7 1427 #define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 1428 #define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
<> 151:5eaa88a5bcc7 1429 #define EXTI_IMR_IM22_Pos (22U)
<> 151:5eaa88a5bcc7 1430 #define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 1431 #define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
<> 151:5eaa88a5bcc7 1432 #define EXTI_IMR_IM23_Pos (23U)
<> 151:5eaa88a5bcc7 1433 #define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 1434 #define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
<> 151:5eaa88a5bcc7 1435 #define EXTI_IMR_IM25_Pos (25U)
<> 151:5eaa88a5bcc7 1436 #define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 1437 #define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
<> 151:5eaa88a5bcc7 1438 #define EXTI_IMR_IM26_Pos (26U)
<> 151:5eaa88a5bcc7 1439 #define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 1440 #define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
<> 151:5eaa88a5bcc7 1441 #define EXTI_IMR_IM28_Pos (28U)
<> 151:5eaa88a5bcc7 1442 #define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 1443 #define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
<> 151:5eaa88a5bcc7 1444 #define EXTI_IMR_IM29_Pos (29U)
<> 151:5eaa88a5bcc7 1445 #define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 1446 #define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
<> 151:5eaa88a5bcc7 1447
<> 151:5eaa88a5bcc7 1448 #define EXTI_IMR_IM_Pos (0U)
<> 151:5eaa88a5bcc7 1449 #define EXTI_IMR_IM_Msk (0x36FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
<> 151:5eaa88a5bcc7 1450 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
mbed_official 114:fe4fe5cfc3a3 1451
mbed_official 114:fe4fe5cfc3a3 1452 /****************** Bit definition for EXTI_EMR register ********************/
<> 151:5eaa88a5bcc7 1453 #define EXTI_EMR_EM0_Pos (0U)
<> 151:5eaa88a5bcc7 1454 #define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1455 #define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
<> 151:5eaa88a5bcc7 1456 #define EXTI_EMR_EM1_Pos (1U)
<> 151:5eaa88a5bcc7 1457 #define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1458 #define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
<> 151:5eaa88a5bcc7 1459 #define EXTI_EMR_EM2_Pos (2U)
<> 151:5eaa88a5bcc7 1460 #define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1461 #define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
<> 151:5eaa88a5bcc7 1462 #define EXTI_EMR_EM3_Pos (3U)
<> 151:5eaa88a5bcc7 1463 #define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1464 #define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
<> 151:5eaa88a5bcc7 1465 #define EXTI_EMR_EM4_Pos (4U)
<> 151:5eaa88a5bcc7 1466 #define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1467 #define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
<> 151:5eaa88a5bcc7 1468 #define EXTI_EMR_EM5_Pos (5U)
<> 151:5eaa88a5bcc7 1469 #define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1470 #define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
<> 151:5eaa88a5bcc7 1471 #define EXTI_EMR_EM6_Pos (6U)
<> 151:5eaa88a5bcc7 1472 #define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1473 #define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
<> 151:5eaa88a5bcc7 1474 #define EXTI_EMR_EM7_Pos (7U)
<> 151:5eaa88a5bcc7 1475 #define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 1476 #define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
<> 151:5eaa88a5bcc7 1477 #define EXTI_EMR_EM8_Pos (8U)
<> 151:5eaa88a5bcc7 1478 #define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 1479 #define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
<> 151:5eaa88a5bcc7 1480 #define EXTI_EMR_EM9_Pos (9U)
<> 151:5eaa88a5bcc7 1481 #define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 1482 #define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
<> 151:5eaa88a5bcc7 1483 #define EXTI_EMR_EM10_Pos (10U)
<> 151:5eaa88a5bcc7 1484 #define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1485 #define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
<> 151:5eaa88a5bcc7 1486 #define EXTI_EMR_EM11_Pos (11U)
<> 151:5eaa88a5bcc7 1487 #define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 1488 #define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
<> 151:5eaa88a5bcc7 1489 #define EXTI_EMR_EM12_Pos (12U)
<> 151:5eaa88a5bcc7 1490 #define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 1491 #define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
<> 151:5eaa88a5bcc7 1492 #define EXTI_EMR_EM13_Pos (13U)
<> 151:5eaa88a5bcc7 1493 #define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 1494 #define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
<> 151:5eaa88a5bcc7 1495 #define EXTI_EMR_EM14_Pos (14U)
<> 151:5eaa88a5bcc7 1496 #define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 1497 #define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
<> 151:5eaa88a5bcc7 1498 #define EXTI_EMR_EM15_Pos (15U)
<> 151:5eaa88a5bcc7 1499 #define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 1500 #define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
<> 151:5eaa88a5bcc7 1501 #define EXTI_EMR_EM16_Pos (16U)
<> 151:5eaa88a5bcc7 1502 #define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 1503 #define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
<> 151:5eaa88a5bcc7 1504 #define EXTI_EMR_EM17_Pos (17U)
<> 151:5eaa88a5bcc7 1505 #define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 1506 #define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
<> 151:5eaa88a5bcc7 1507 #define EXTI_EMR_EM18_Pos (18U)
<> 151:5eaa88a5bcc7 1508 #define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 1509 #define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
<> 151:5eaa88a5bcc7 1510 #define EXTI_EMR_EM19_Pos (19U)
<> 151:5eaa88a5bcc7 1511 #define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 1512 #define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
<> 151:5eaa88a5bcc7 1513 #define EXTI_EMR_EM20_Pos (20U)
<> 151:5eaa88a5bcc7 1514 #define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 1515 #define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
<> 151:5eaa88a5bcc7 1516 #define EXTI_EMR_EM21_Pos (21U)
<> 151:5eaa88a5bcc7 1517 #define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 1518 #define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
<> 151:5eaa88a5bcc7 1519 #define EXTI_EMR_EM22_Pos (22U)
<> 151:5eaa88a5bcc7 1520 #define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 1521 #define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
<> 151:5eaa88a5bcc7 1522 #define EXTI_EMR_EM23_Pos (23U)
<> 151:5eaa88a5bcc7 1523 #define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 1524 #define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
<> 151:5eaa88a5bcc7 1525 #define EXTI_EMR_EM25_Pos (25U)
<> 151:5eaa88a5bcc7 1526 #define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 1527 #define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
<> 151:5eaa88a5bcc7 1528 #define EXTI_EMR_EM26_Pos (26U)
<> 151:5eaa88a5bcc7 1529 #define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 1530 #define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
<> 151:5eaa88a5bcc7 1531 #define EXTI_EMR_EM28_Pos (28U)
<> 151:5eaa88a5bcc7 1532 #define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 1533 #define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
<> 151:5eaa88a5bcc7 1534 #define EXTI_EMR_EM29_Pos (29U)
<> 151:5eaa88a5bcc7 1535 #define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 1536 #define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
mbed_official 114:fe4fe5cfc3a3 1537
mbed_official 114:fe4fe5cfc3a3 1538 /******************* Bit definition for EXTI_RTSR register ******************/
<> 151:5eaa88a5bcc7 1539 #define EXTI_RTSR_RT0_Pos (0U)
<> 151:5eaa88a5bcc7 1540 #define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1541 #define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
<> 151:5eaa88a5bcc7 1542 #define EXTI_RTSR_RT1_Pos (1U)
<> 151:5eaa88a5bcc7 1543 #define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1544 #define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
<> 151:5eaa88a5bcc7 1545 #define EXTI_RTSR_RT2_Pos (2U)
<> 151:5eaa88a5bcc7 1546 #define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1547 #define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
<> 151:5eaa88a5bcc7 1548 #define EXTI_RTSR_RT3_Pos (3U)
<> 151:5eaa88a5bcc7 1549 #define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1550 #define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
<> 151:5eaa88a5bcc7 1551 #define EXTI_RTSR_RT4_Pos (4U)
<> 151:5eaa88a5bcc7 1552 #define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1553 #define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
<> 151:5eaa88a5bcc7 1554 #define EXTI_RTSR_RT5_Pos (5U)
<> 151:5eaa88a5bcc7 1555 #define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1556 #define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
<> 151:5eaa88a5bcc7 1557 #define EXTI_RTSR_RT6_Pos (6U)
<> 151:5eaa88a5bcc7 1558 #define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1559 #define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
<> 151:5eaa88a5bcc7 1560 #define EXTI_RTSR_RT7_Pos (7U)
<> 151:5eaa88a5bcc7 1561 #define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 1562 #define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
<> 151:5eaa88a5bcc7 1563 #define EXTI_RTSR_RT8_Pos (8U)
<> 151:5eaa88a5bcc7 1564 #define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 1565 #define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
<> 151:5eaa88a5bcc7 1566 #define EXTI_RTSR_RT9_Pos (9U)
<> 151:5eaa88a5bcc7 1567 #define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 1568 #define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
<> 151:5eaa88a5bcc7 1569 #define EXTI_RTSR_RT10_Pos (10U)
<> 151:5eaa88a5bcc7 1570 #define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1571 #define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
<> 151:5eaa88a5bcc7 1572 #define EXTI_RTSR_RT11_Pos (11U)
<> 151:5eaa88a5bcc7 1573 #define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 1574 #define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
<> 151:5eaa88a5bcc7 1575 #define EXTI_RTSR_RT12_Pos (12U)
<> 151:5eaa88a5bcc7 1576 #define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 1577 #define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
<> 151:5eaa88a5bcc7 1578 #define EXTI_RTSR_RT13_Pos (13U)
<> 151:5eaa88a5bcc7 1579 #define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 1580 #define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
<> 151:5eaa88a5bcc7 1581 #define EXTI_RTSR_RT14_Pos (14U)
<> 151:5eaa88a5bcc7 1582 #define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 1583 #define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
<> 151:5eaa88a5bcc7 1584 #define EXTI_RTSR_RT15_Pos (15U)
<> 151:5eaa88a5bcc7 1585 #define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 1586 #define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
<> 151:5eaa88a5bcc7 1587 #define EXTI_RTSR_RT16_Pos (16U)
<> 151:5eaa88a5bcc7 1588 #define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 1589 #define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
<> 151:5eaa88a5bcc7 1590 #define EXTI_RTSR_RT17_Pos (17U)
<> 151:5eaa88a5bcc7 1591 #define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 1592 #define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
<> 151:5eaa88a5bcc7 1593 #define EXTI_RTSR_RT19_Pos (19U)
<> 151:5eaa88a5bcc7 1594 #define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 1595 #define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
<> 151:5eaa88a5bcc7 1596 #define EXTI_RTSR_RT20_Pos (20U)
<> 151:5eaa88a5bcc7 1597 #define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 1598 #define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
<> 151:5eaa88a5bcc7 1599 #define EXTI_RTSR_RT21_Pos (21U)
<> 151:5eaa88a5bcc7 1600 #define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 1601 #define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
<> 151:5eaa88a5bcc7 1602 #define EXTI_RTSR_RT22_Pos (22U)
<> 151:5eaa88a5bcc7 1603 #define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 1604 #define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
mbed_official 114:fe4fe5cfc3a3 1605
mbed_official 114:fe4fe5cfc3a3 1606 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 1607 #define EXTI_RTSR_TR0 EXTI_RTSR_RT0
mbed_official 114:fe4fe5cfc3a3 1608 #define EXTI_RTSR_TR1 EXTI_RTSR_RT1
mbed_official 114:fe4fe5cfc3a3 1609 #define EXTI_RTSR_TR2 EXTI_RTSR_RT2
mbed_official 114:fe4fe5cfc3a3 1610 #define EXTI_RTSR_TR3 EXTI_RTSR_RT3
mbed_official 114:fe4fe5cfc3a3 1611 #define EXTI_RTSR_TR4 EXTI_RTSR_RT4
mbed_official 114:fe4fe5cfc3a3 1612 #define EXTI_RTSR_TR5 EXTI_RTSR_RT5
mbed_official 114:fe4fe5cfc3a3 1613 #define EXTI_RTSR_TR6 EXTI_RTSR_RT6
mbed_official 114:fe4fe5cfc3a3 1614 #define EXTI_RTSR_TR7 EXTI_RTSR_RT7
mbed_official 114:fe4fe5cfc3a3 1615 #define EXTI_RTSR_TR8 EXTI_RTSR_RT8
mbed_official 114:fe4fe5cfc3a3 1616 #define EXTI_RTSR_TR9 EXTI_RTSR_RT9
mbed_official 114:fe4fe5cfc3a3 1617 #define EXTI_RTSR_TR10 EXTI_RTSR_RT10
mbed_official 114:fe4fe5cfc3a3 1618 #define EXTI_RTSR_TR11 EXTI_RTSR_RT11
mbed_official 114:fe4fe5cfc3a3 1619 #define EXTI_RTSR_TR12 EXTI_RTSR_RT12
mbed_official 114:fe4fe5cfc3a3 1620 #define EXTI_RTSR_TR13 EXTI_RTSR_RT13
mbed_official 114:fe4fe5cfc3a3 1621 #define EXTI_RTSR_TR14 EXTI_RTSR_RT14
mbed_official 114:fe4fe5cfc3a3 1622 #define EXTI_RTSR_TR15 EXTI_RTSR_RT15
mbed_official 114:fe4fe5cfc3a3 1623 #define EXTI_RTSR_TR16 EXTI_RTSR_RT16
mbed_official 114:fe4fe5cfc3a3 1624 #define EXTI_RTSR_TR17 EXTI_RTSR_RT17
mbed_official 114:fe4fe5cfc3a3 1625 #define EXTI_RTSR_TR19 EXTI_RTSR_RT19
mbed_official 114:fe4fe5cfc3a3 1626 #define EXTI_RTSR_TR20 EXTI_RTSR_RT20
mbed_official 114:fe4fe5cfc3a3 1627 #define EXTI_RTSR_TR21 EXTI_RTSR_RT21
mbed_official 114:fe4fe5cfc3a3 1628 #define EXTI_RTSR_TR22 EXTI_RTSR_RT22
mbed_official 114:fe4fe5cfc3a3 1629
mbed_official 114:fe4fe5cfc3a3 1630 /******************* Bit definition for EXTI_FTSR register *******************/
<> 151:5eaa88a5bcc7 1631 #define EXTI_FTSR_FT0_Pos (0U)
<> 151:5eaa88a5bcc7 1632 #define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1633 #define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
<> 151:5eaa88a5bcc7 1634 #define EXTI_FTSR_FT1_Pos (1U)
<> 151:5eaa88a5bcc7 1635 #define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1636 #define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
<> 151:5eaa88a5bcc7 1637 #define EXTI_FTSR_FT2_Pos (2U)
<> 151:5eaa88a5bcc7 1638 #define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1639 #define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
<> 151:5eaa88a5bcc7 1640 #define EXTI_FTSR_FT3_Pos (3U)
<> 151:5eaa88a5bcc7 1641 #define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1642 #define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
<> 151:5eaa88a5bcc7 1643 #define EXTI_FTSR_FT4_Pos (4U)
<> 151:5eaa88a5bcc7 1644 #define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1645 #define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
<> 151:5eaa88a5bcc7 1646 #define EXTI_FTSR_FT5_Pos (5U)
<> 151:5eaa88a5bcc7 1647 #define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1648 #define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
<> 151:5eaa88a5bcc7 1649 #define EXTI_FTSR_FT6_Pos (6U)
<> 151:5eaa88a5bcc7 1650 #define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1651 #define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
<> 151:5eaa88a5bcc7 1652 #define EXTI_FTSR_FT7_Pos (7U)
<> 151:5eaa88a5bcc7 1653 #define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 1654 #define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
<> 151:5eaa88a5bcc7 1655 #define EXTI_FTSR_FT8_Pos (8U)
<> 151:5eaa88a5bcc7 1656 #define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 1657 #define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
<> 151:5eaa88a5bcc7 1658 #define EXTI_FTSR_FT9_Pos (9U)
<> 151:5eaa88a5bcc7 1659 #define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 1660 #define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
<> 151:5eaa88a5bcc7 1661 #define EXTI_FTSR_FT10_Pos (10U)
<> 151:5eaa88a5bcc7 1662 #define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1663 #define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
<> 151:5eaa88a5bcc7 1664 #define EXTI_FTSR_FT11_Pos (11U)
<> 151:5eaa88a5bcc7 1665 #define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 1666 #define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
<> 151:5eaa88a5bcc7 1667 #define EXTI_FTSR_FT12_Pos (12U)
<> 151:5eaa88a5bcc7 1668 #define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 1669 #define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
<> 151:5eaa88a5bcc7 1670 #define EXTI_FTSR_FT13_Pos (13U)
<> 151:5eaa88a5bcc7 1671 #define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 1672 #define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
<> 151:5eaa88a5bcc7 1673 #define EXTI_FTSR_FT14_Pos (14U)
<> 151:5eaa88a5bcc7 1674 #define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 1675 #define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
<> 151:5eaa88a5bcc7 1676 #define EXTI_FTSR_FT15_Pos (15U)
<> 151:5eaa88a5bcc7 1677 #define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 1678 #define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
<> 151:5eaa88a5bcc7 1679 #define EXTI_FTSR_FT16_Pos (16U)
<> 151:5eaa88a5bcc7 1680 #define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 1681 #define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
<> 151:5eaa88a5bcc7 1682 #define EXTI_FTSR_FT17_Pos (17U)
<> 151:5eaa88a5bcc7 1683 #define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 1684 #define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
<> 151:5eaa88a5bcc7 1685 #define EXTI_FTSR_FT19_Pos (19U)
<> 151:5eaa88a5bcc7 1686 #define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 1687 #define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
<> 151:5eaa88a5bcc7 1688 #define EXTI_FTSR_FT20_Pos (20U)
<> 151:5eaa88a5bcc7 1689 #define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 1690 #define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
<> 151:5eaa88a5bcc7 1691 #define EXTI_FTSR_FT21_Pos (21U)
<> 151:5eaa88a5bcc7 1692 #define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 1693 #define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
<> 151:5eaa88a5bcc7 1694 #define EXTI_FTSR_FT22_Pos (22U)
<> 151:5eaa88a5bcc7 1695 #define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 1696 #define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
mbed_official 114:fe4fe5cfc3a3 1697
mbed_official 114:fe4fe5cfc3a3 1698 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 1699 #define EXTI_FTSR_TR0 EXTI_FTSR_FT0
mbed_official 114:fe4fe5cfc3a3 1700 #define EXTI_FTSR_TR1 EXTI_FTSR_FT1
mbed_official 114:fe4fe5cfc3a3 1701 #define EXTI_FTSR_TR2 EXTI_FTSR_FT2
mbed_official 114:fe4fe5cfc3a3 1702 #define EXTI_FTSR_TR3 EXTI_FTSR_FT3
mbed_official 114:fe4fe5cfc3a3 1703 #define EXTI_FTSR_TR4 EXTI_FTSR_FT4
mbed_official 114:fe4fe5cfc3a3 1704 #define EXTI_FTSR_TR5 EXTI_FTSR_FT5
mbed_official 114:fe4fe5cfc3a3 1705 #define EXTI_FTSR_TR6 EXTI_FTSR_FT6
mbed_official 114:fe4fe5cfc3a3 1706 #define EXTI_FTSR_TR7 EXTI_FTSR_FT7
mbed_official 114:fe4fe5cfc3a3 1707 #define EXTI_FTSR_TR8 EXTI_FTSR_FT8
mbed_official 114:fe4fe5cfc3a3 1708 #define EXTI_FTSR_TR9 EXTI_FTSR_FT9
mbed_official 114:fe4fe5cfc3a3 1709 #define EXTI_FTSR_TR10 EXTI_FTSR_FT10
mbed_official 114:fe4fe5cfc3a3 1710 #define EXTI_FTSR_TR11 EXTI_FTSR_FT11
mbed_official 114:fe4fe5cfc3a3 1711 #define EXTI_FTSR_TR12 EXTI_FTSR_FT12
mbed_official 114:fe4fe5cfc3a3 1712 #define EXTI_FTSR_TR13 EXTI_FTSR_FT13
mbed_official 114:fe4fe5cfc3a3 1713 #define EXTI_FTSR_TR14 EXTI_FTSR_FT14
mbed_official 114:fe4fe5cfc3a3 1714 #define EXTI_FTSR_TR15 EXTI_FTSR_FT15
mbed_official 114:fe4fe5cfc3a3 1715 #define EXTI_FTSR_TR16 EXTI_FTSR_FT16
mbed_official 114:fe4fe5cfc3a3 1716 #define EXTI_FTSR_TR17 EXTI_FTSR_FT17
mbed_official 114:fe4fe5cfc3a3 1717 #define EXTI_FTSR_TR19 EXTI_FTSR_FT19
mbed_official 114:fe4fe5cfc3a3 1718 #define EXTI_FTSR_TR20 EXTI_FTSR_FT20
mbed_official 114:fe4fe5cfc3a3 1719 #define EXTI_FTSR_TR21 EXTI_FTSR_FT21
mbed_official 114:fe4fe5cfc3a3 1720 #define EXTI_FTSR_TR22 EXTI_FTSR_FT22
mbed_official 114:fe4fe5cfc3a3 1721
mbed_official 114:fe4fe5cfc3a3 1722 /******************* Bit definition for EXTI_SWIER register *******************/
<> 151:5eaa88a5bcc7 1723 #define EXTI_SWIER_SWI0_Pos (0U)
<> 151:5eaa88a5bcc7 1724 #define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1725 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
<> 151:5eaa88a5bcc7 1726 #define EXTI_SWIER_SWI1_Pos (1U)
<> 151:5eaa88a5bcc7 1727 #define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1728 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
<> 151:5eaa88a5bcc7 1729 #define EXTI_SWIER_SWI2_Pos (2U)
<> 151:5eaa88a5bcc7 1730 #define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1731 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
<> 151:5eaa88a5bcc7 1732 #define EXTI_SWIER_SWI3_Pos (3U)
<> 151:5eaa88a5bcc7 1733 #define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1734 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
<> 151:5eaa88a5bcc7 1735 #define EXTI_SWIER_SWI4_Pos (4U)
<> 151:5eaa88a5bcc7 1736 #define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1737 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
<> 151:5eaa88a5bcc7 1738 #define EXTI_SWIER_SWI5_Pos (5U)
<> 151:5eaa88a5bcc7 1739 #define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1740 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
<> 151:5eaa88a5bcc7 1741 #define EXTI_SWIER_SWI6_Pos (6U)
<> 151:5eaa88a5bcc7 1742 #define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1743 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
<> 151:5eaa88a5bcc7 1744 #define EXTI_SWIER_SWI7_Pos (7U)
<> 151:5eaa88a5bcc7 1745 #define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 1746 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
<> 151:5eaa88a5bcc7 1747 #define EXTI_SWIER_SWI8_Pos (8U)
<> 151:5eaa88a5bcc7 1748 #define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 1749 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
<> 151:5eaa88a5bcc7 1750 #define EXTI_SWIER_SWI9_Pos (9U)
<> 151:5eaa88a5bcc7 1751 #define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 1752 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
<> 151:5eaa88a5bcc7 1753 #define EXTI_SWIER_SWI10_Pos (10U)
<> 151:5eaa88a5bcc7 1754 #define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1755 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
<> 151:5eaa88a5bcc7 1756 #define EXTI_SWIER_SWI11_Pos (11U)
<> 151:5eaa88a5bcc7 1757 #define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 1758 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
<> 151:5eaa88a5bcc7 1759 #define EXTI_SWIER_SWI12_Pos (12U)
<> 151:5eaa88a5bcc7 1760 #define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 1761 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
<> 151:5eaa88a5bcc7 1762 #define EXTI_SWIER_SWI13_Pos (13U)
<> 151:5eaa88a5bcc7 1763 #define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 1764 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
<> 151:5eaa88a5bcc7 1765 #define EXTI_SWIER_SWI14_Pos (14U)
<> 151:5eaa88a5bcc7 1766 #define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 1767 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
<> 151:5eaa88a5bcc7 1768 #define EXTI_SWIER_SWI15_Pos (15U)
<> 151:5eaa88a5bcc7 1769 #define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 1770 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
<> 151:5eaa88a5bcc7 1771 #define EXTI_SWIER_SWI16_Pos (16U)
<> 151:5eaa88a5bcc7 1772 #define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 1773 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
<> 151:5eaa88a5bcc7 1774 #define EXTI_SWIER_SWI17_Pos (17U)
<> 151:5eaa88a5bcc7 1775 #define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 1776 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
<> 151:5eaa88a5bcc7 1777 #define EXTI_SWIER_SWI19_Pos (19U)
<> 151:5eaa88a5bcc7 1778 #define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 1779 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
<> 151:5eaa88a5bcc7 1780 #define EXTI_SWIER_SWI20_Pos (20U)
<> 151:5eaa88a5bcc7 1781 #define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 1782 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
<> 151:5eaa88a5bcc7 1783 #define EXTI_SWIER_SWI21_Pos (21U)
<> 151:5eaa88a5bcc7 1784 #define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 1785 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
<> 151:5eaa88a5bcc7 1786 #define EXTI_SWIER_SWI22_Pos (22U)
<> 151:5eaa88a5bcc7 1787 #define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 1788 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
mbed_official 114:fe4fe5cfc3a3 1789
mbed_official 114:fe4fe5cfc3a3 1790 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 1791 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
mbed_official 114:fe4fe5cfc3a3 1792 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
mbed_official 114:fe4fe5cfc3a3 1793 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
mbed_official 114:fe4fe5cfc3a3 1794 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
mbed_official 114:fe4fe5cfc3a3 1795 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
mbed_official 114:fe4fe5cfc3a3 1796 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
mbed_official 114:fe4fe5cfc3a3 1797 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
mbed_official 114:fe4fe5cfc3a3 1798 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
mbed_official 114:fe4fe5cfc3a3 1799 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
mbed_official 114:fe4fe5cfc3a3 1800 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
mbed_official 114:fe4fe5cfc3a3 1801 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
mbed_official 114:fe4fe5cfc3a3 1802 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
mbed_official 114:fe4fe5cfc3a3 1803 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
mbed_official 114:fe4fe5cfc3a3 1804 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
mbed_official 114:fe4fe5cfc3a3 1805 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
mbed_official 114:fe4fe5cfc3a3 1806 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
mbed_official 114:fe4fe5cfc3a3 1807 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
mbed_official 114:fe4fe5cfc3a3 1808 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
mbed_official 114:fe4fe5cfc3a3 1809 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
mbed_official 114:fe4fe5cfc3a3 1810 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
mbed_official 114:fe4fe5cfc3a3 1811 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
mbed_official 114:fe4fe5cfc3a3 1812 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
mbed_official 114:fe4fe5cfc3a3 1813
mbed_official 114:fe4fe5cfc3a3 1814 /****************** Bit definition for EXTI_PR register *********************/
<> 151:5eaa88a5bcc7 1815 #define EXTI_PR_PIF0_Pos (0U)
<> 151:5eaa88a5bcc7 1816 #define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1817 #define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
<> 151:5eaa88a5bcc7 1818 #define EXTI_PR_PIF1_Pos (1U)
<> 151:5eaa88a5bcc7 1819 #define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1820 #define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
<> 151:5eaa88a5bcc7 1821 #define EXTI_PR_PIF2_Pos (2U)
<> 151:5eaa88a5bcc7 1822 #define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1823 #define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
<> 151:5eaa88a5bcc7 1824 #define EXTI_PR_PIF3_Pos (3U)
<> 151:5eaa88a5bcc7 1825 #define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1826 #define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
<> 151:5eaa88a5bcc7 1827 #define EXTI_PR_PIF4_Pos (4U)
<> 151:5eaa88a5bcc7 1828 #define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1829 #define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
<> 151:5eaa88a5bcc7 1830 #define EXTI_PR_PIF5_Pos (5U)
<> 151:5eaa88a5bcc7 1831 #define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1832 #define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
<> 151:5eaa88a5bcc7 1833 #define EXTI_PR_PIF6_Pos (6U)
<> 151:5eaa88a5bcc7 1834 #define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1835 #define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
<> 151:5eaa88a5bcc7 1836 #define EXTI_PR_PIF7_Pos (7U)
<> 151:5eaa88a5bcc7 1837 #define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 1838 #define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
<> 151:5eaa88a5bcc7 1839 #define EXTI_PR_PIF8_Pos (8U)
<> 151:5eaa88a5bcc7 1840 #define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 1841 #define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
<> 151:5eaa88a5bcc7 1842 #define EXTI_PR_PIF9_Pos (9U)
<> 151:5eaa88a5bcc7 1843 #define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 1844 #define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
<> 151:5eaa88a5bcc7 1845 #define EXTI_PR_PIF10_Pos (10U)
<> 151:5eaa88a5bcc7 1846 #define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1847 #define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
<> 151:5eaa88a5bcc7 1848 #define EXTI_PR_PIF11_Pos (11U)
<> 151:5eaa88a5bcc7 1849 #define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 1850 #define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
<> 151:5eaa88a5bcc7 1851 #define EXTI_PR_PIF12_Pos (12U)
<> 151:5eaa88a5bcc7 1852 #define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 1853 #define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
<> 151:5eaa88a5bcc7 1854 #define EXTI_PR_PIF13_Pos (13U)
<> 151:5eaa88a5bcc7 1855 #define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 1856 #define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
<> 151:5eaa88a5bcc7 1857 #define EXTI_PR_PIF14_Pos (14U)
<> 151:5eaa88a5bcc7 1858 #define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 1859 #define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
<> 151:5eaa88a5bcc7 1860 #define EXTI_PR_PIF15_Pos (15U)
<> 151:5eaa88a5bcc7 1861 #define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 1862 #define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
<> 151:5eaa88a5bcc7 1863 #define EXTI_PR_PIF16_Pos (16U)
<> 151:5eaa88a5bcc7 1864 #define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 1865 #define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
<> 151:5eaa88a5bcc7 1866 #define EXTI_PR_PIF17_Pos (17U)
<> 151:5eaa88a5bcc7 1867 #define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 1868 #define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
<> 151:5eaa88a5bcc7 1869 #define EXTI_PR_PIF19_Pos (19U)
<> 151:5eaa88a5bcc7 1870 #define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 1871 #define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
<> 151:5eaa88a5bcc7 1872 #define EXTI_PR_PIF20_Pos (20U)
<> 151:5eaa88a5bcc7 1873 #define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 1874 #define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
<> 151:5eaa88a5bcc7 1875 #define EXTI_PR_PIF21_Pos (21U)
<> 151:5eaa88a5bcc7 1876 #define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 1877 #define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
<> 151:5eaa88a5bcc7 1878 #define EXTI_PR_PIF22_Pos (22U)
<> 151:5eaa88a5bcc7 1879 #define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 1880 #define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
mbed_official 114:fe4fe5cfc3a3 1881
mbed_official 114:fe4fe5cfc3a3 1882 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 1883 #define EXTI_PR_PR0 EXTI_PR_PIF0
mbed_official 114:fe4fe5cfc3a3 1884 #define EXTI_PR_PR1 EXTI_PR_PIF1
mbed_official 114:fe4fe5cfc3a3 1885 #define EXTI_PR_PR2 EXTI_PR_PIF2
mbed_official 114:fe4fe5cfc3a3 1886 #define EXTI_PR_PR3 EXTI_PR_PIF3
mbed_official 114:fe4fe5cfc3a3 1887 #define EXTI_PR_PR4 EXTI_PR_PIF4
mbed_official 114:fe4fe5cfc3a3 1888 #define EXTI_PR_PR5 EXTI_PR_PIF5
mbed_official 114:fe4fe5cfc3a3 1889 #define EXTI_PR_PR6 EXTI_PR_PIF6
mbed_official 114:fe4fe5cfc3a3 1890 #define EXTI_PR_PR7 EXTI_PR_PIF7
mbed_official 114:fe4fe5cfc3a3 1891 #define EXTI_PR_PR8 EXTI_PR_PIF8
mbed_official 114:fe4fe5cfc3a3 1892 #define EXTI_PR_PR9 EXTI_PR_PIF9
mbed_official 114:fe4fe5cfc3a3 1893 #define EXTI_PR_PR10 EXTI_PR_PIF10
mbed_official 114:fe4fe5cfc3a3 1894 #define EXTI_PR_PR11 EXTI_PR_PIF11
mbed_official 114:fe4fe5cfc3a3 1895 #define EXTI_PR_PR12 EXTI_PR_PIF12
mbed_official 114:fe4fe5cfc3a3 1896 #define EXTI_PR_PR13 EXTI_PR_PIF13
mbed_official 114:fe4fe5cfc3a3 1897 #define EXTI_PR_PR14 EXTI_PR_PIF14
mbed_official 114:fe4fe5cfc3a3 1898 #define EXTI_PR_PR15 EXTI_PR_PIF15
mbed_official 114:fe4fe5cfc3a3 1899 #define EXTI_PR_PR16 EXTI_PR_PIF16
mbed_official 114:fe4fe5cfc3a3 1900 #define EXTI_PR_PR17 EXTI_PR_PIF17
mbed_official 114:fe4fe5cfc3a3 1901 #define EXTI_PR_PR19 EXTI_PR_PIF19
mbed_official 114:fe4fe5cfc3a3 1902 #define EXTI_PR_PR20 EXTI_PR_PIF20
mbed_official 114:fe4fe5cfc3a3 1903 #define EXTI_PR_PR21 EXTI_PR_PIF21
mbed_official 114:fe4fe5cfc3a3 1904 #define EXTI_PR_PR22 EXTI_PR_PIF22
mbed_official 114:fe4fe5cfc3a3 1905
mbed_official 114:fe4fe5cfc3a3 1906 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 1907 /* */
mbed_official 114:fe4fe5cfc3a3 1908 /* FLASH and Option Bytes Registers */
mbed_official 114:fe4fe5cfc3a3 1909 /* */
mbed_official 114:fe4fe5cfc3a3 1910 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 1911
mbed_official 114:fe4fe5cfc3a3 1912 /******************* Bit definition for FLASH_ACR register ******************/
<> 151:5eaa88a5bcc7 1913 #define FLASH_ACR_LATENCY_Pos (0U)
<> 151:5eaa88a5bcc7 1914 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1915 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
<> 151:5eaa88a5bcc7 1916 #define FLASH_ACR_PRFTEN_Pos (1U)
<> 151:5eaa88a5bcc7 1917 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1918 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
<> 151:5eaa88a5bcc7 1919 #define FLASH_ACR_SLEEP_PD_Pos (3U)
<> 151:5eaa88a5bcc7 1920 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1921 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
<> 151:5eaa88a5bcc7 1922 #define FLASH_ACR_RUN_PD_Pos (4U)
<> 151:5eaa88a5bcc7 1923 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1924 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
<> 151:5eaa88a5bcc7 1925 #define FLASH_ACR_DISAB_BUF_Pos (5U)
<> 151:5eaa88a5bcc7 1926 #define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 1927 #define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
<> 151:5eaa88a5bcc7 1928 #define FLASH_ACR_PRE_READ_Pos (6U)
<> 151:5eaa88a5bcc7 1929 #define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 1930 #define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
mbed_official 114:fe4fe5cfc3a3 1931
mbed_official 114:fe4fe5cfc3a3 1932 /******************* Bit definition for FLASH_PECR register ******************/
<> 151:5eaa88a5bcc7 1933 #define FLASH_PECR_PELOCK_Pos (0U)
<> 151:5eaa88a5bcc7 1934 #define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1935 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
<> 151:5eaa88a5bcc7 1936 #define FLASH_PECR_PRGLOCK_Pos (1U)
<> 151:5eaa88a5bcc7 1937 #define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1938 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
<> 151:5eaa88a5bcc7 1939 #define FLASH_PECR_OPTLOCK_Pos (2U)
<> 151:5eaa88a5bcc7 1940 #define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1941 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
<> 151:5eaa88a5bcc7 1942 #define FLASH_PECR_PROG_Pos (3U)
<> 151:5eaa88a5bcc7 1943 #define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 1944 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
<> 151:5eaa88a5bcc7 1945 #define FLASH_PECR_DATA_Pos (4U)
<> 151:5eaa88a5bcc7 1946 #define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 1947 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
<> 151:5eaa88a5bcc7 1948 #define FLASH_PECR_FIX_Pos (8U)
<> 151:5eaa88a5bcc7 1949 #define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 1950 #define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
<> 151:5eaa88a5bcc7 1951 #define FLASH_PECR_ERASE_Pos (9U)
<> 151:5eaa88a5bcc7 1952 #define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 1953 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
<> 151:5eaa88a5bcc7 1954 #define FLASH_PECR_FPRG_Pos (10U)
<> 151:5eaa88a5bcc7 1955 #define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 1956 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
<> 151:5eaa88a5bcc7 1957 #define FLASH_PECR_EOPIE_Pos (16U)
<> 151:5eaa88a5bcc7 1958 #define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 1959 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
<> 151:5eaa88a5bcc7 1960 #define FLASH_PECR_ERRIE_Pos (17U)
<> 151:5eaa88a5bcc7 1961 #define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 1962 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
<> 151:5eaa88a5bcc7 1963 #define FLASH_PECR_OBL_LAUNCH_Pos (18U)
<> 151:5eaa88a5bcc7 1964 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 1965 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
<> 151:5eaa88a5bcc7 1966 #define FLASH_PECR_HALF_ARRAY_Pos (19U)
<> 151:5eaa88a5bcc7 1967 #define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 1968 #define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
mbed_official 114:fe4fe5cfc3a3 1969
mbed_official 114:fe4fe5cfc3a3 1970 /****************** Bit definition for FLASH_PDKEYR register ******************/
<> 151:5eaa88a5bcc7 1971 #define FLASH_PDKEYR_PDKEYR_Pos (0U)
<> 151:5eaa88a5bcc7 1972 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 1973 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
mbed_official 114:fe4fe5cfc3a3 1974
mbed_official 114:fe4fe5cfc3a3 1975 /****************** Bit definition for FLASH_PEKEYR register ******************/
<> 151:5eaa88a5bcc7 1976 #define FLASH_PEKEYR_PEKEYR_Pos (0U)
<> 151:5eaa88a5bcc7 1977 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 1978 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
mbed_official 114:fe4fe5cfc3a3 1979
mbed_official 114:fe4fe5cfc3a3 1980 /****************** Bit definition for FLASH_PRGKEYR register ******************/
<> 151:5eaa88a5bcc7 1981 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
<> 151:5eaa88a5bcc7 1982 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 1983 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
mbed_official 114:fe4fe5cfc3a3 1984
mbed_official 114:fe4fe5cfc3a3 1985 /****************** Bit definition for FLASH_OPTKEYR register ******************/
<> 151:5eaa88a5bcc7 1986 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
<> 151:5eaa88a5bcc7 1987 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 1988 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
mbed_official 114:fe4fe5cfc3a3 1989
mbed_official 114:fe4fe5cfc3a3 1990 /****************** Bit definition for FLASH_SR register *******************/
<> 151:5eaa88a5bcc7 1991 #define FLASH_SR_BSY_Pos (0U)
<> 151:5eaa88a5bcc7 1992 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 1993 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
<> 151:5eaa88a5bcc7 1994 #define FLASH_SR_EOP_Pos (1U)
<> 151:5eaa88a5bcc7 1995 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 1996 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
<> 151:5eaa88a5bcc7 1997 #define FLASH_SR_HVOFF_Pos (2U)
<> 151:5eaa88a5bcc7 1998 #define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 1999 #define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
<> 151:5eaa88a5bcc7 2000 #define FLASH_SR_READY_Pos (3U)
<> 151:5eaa88a5bcc7 2001 #define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2002 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
<> 151:5eaa88a5bcc7 2003
<> 151:5eaa88a5bcc7 2004 #define FLASH_SR_WRPERR_Pos (8U)
<> 151:5eaa88a5bcc7 2005 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2006 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
<> 151:5eaa88a5bcc7 2007 #define FLASH_SR_PGAERR_Pos (9U)
<> 151:5eaa88a5bcc7 2008 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 2009 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
<> 151:5eaa88a5bcc7 2010 #define FLASH_SR_SIZERR_Pos (10U)
<> 151:5eaa88a5bcc7 2011 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2012 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
<> 151:5eaa88a5bcc7 2013 #define FLASH_SR_OPTVERR_Pos (11U)
<> 151:5eaa88a5bcc7 2014 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 2015 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
<> 151:5eaa88a5bcc7 2016 #define FLASH_SR_RDERR_Pos (13U)
<> 151:5eaa88a5bcc7 2017 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 2018 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
<> 151:5eaa88a5bcc7 2019 #define FLASH_SR_NOTZEROERR_Pos (16U)
<> 151:5eaa88a5bcc7 2020 #define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 2021 #define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
<> 151:5eaa88a5bcc7 2022 #define FLASH_SR_FWWERR_Pos (17U)
<> 151:5eaa88a5bcc7 2023 #define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 2024 #define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
mbed_official 114:fe4fe5cfc3a3 2025
mbed_official 114:fe4fe5cfc3a3 2026 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 2027 #define FLASH_SR_FWWER FLASH_SR_FWWERR
mbed_official 114:fe4fe5cfc3a3 2028 #define FLASH_SR_ENHV FLASH_SR_HVOFF
mbed_official 114:fe4fe5cfc3a3 2029 #define FLASH_SR_ENDHV FLASH_SR_HVOFF
mbed_official 114:fe4fe5cfc3a3 2030
mbed_official 114:fe4fe5cfc3a3 2031 /****************** Bit definition for FLASH_OPTR register *******************/
<> 151:5eaa88a5bcc7 2032 #define FLASH_OPTR_RDPROT_Pos (0U)
<> 151:5eaa88a5bcc7 2033 #define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
<> 151:5eaa88a5bcc7 2034 #define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
<> 151:5eaa88a5bcc7 2035 #define FLASH_OPTR_WPRMOD_Pos (8U)
<> 151:5eaa88a5bcc7 2036 #define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2037 #define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
<> 151:5eaa88a5bcc7 2038 #define FLASH_OPTR_BOR_LEV_Pos (16U)
<> 151:5eaa88a5bcc7 2039 #define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
<> 151:5eaa88a5bcc7 2040 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
<> 151:5eaa88a5bcc7 2041 #define FLASH_OPTR_IWDG_SW_Pos (20U)
<> 151:5eaa88a5bcc7 2042 #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 2043 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
<> 151:5eaa88a5bcc7 2044 #define FLASH_OPTR_nRST_STOP_Pos (21U)
<> 151:5eaa88a5bcc7 2045 #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 2046 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
<> 151:5eaa88a5bcc7 2047 #define FLASH_OPTR_nRST_STDBY_Pos (22U)
<> 151:5eaa88a5bcc7 2048 #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 2049 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
<> 151:5eaa88a5bcc7 2050 #define FLASH_OPTR_USER_Pos (20U)
<> 151:5eaa88a5bcc7 2051 #define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
<> 151:5eaa88a5bcc7 2052 #define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
<> 151:5eaa88a5bcc7 2053 #define FLASH_OPTR_BOOT1_Pos (31U)
<> 151:5eaa88a5bcc7 2054 #define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 2055 #define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
mbed_official 114:fe4fe5cfc3a3 2056
mbed_official 114:fe4fe5cfc3a3 2057 /****************** Bit definition for FLASH_WRPR register ******************/
<> 151:5eaa88a5bcc7 2058 #define FLASH_WRPR_WRP_Pos (0U)
<> 151:5eaa88a5bcc7 2059 #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 2060 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
mbed_official 114:fe4fe5cfc3a3 2061
mbed_official 114:fe4fe5cfc3a3 2062 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 2063 /* */
mbed_official 114:fe4fe5cfc3a3 2064 /* General Purpose IOs (GPIO) */
mbed_official 114:fe4fe5cfc3a3 2065 /* */
mbed_official 114:fe4fe5cfc3a3 2066 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 2067 /******************* Bit definition for GPIO_MODER register *****************/
<> 151:5eaa88a5bcc7 2068 #define GPIO_MODER_MODE0_Pos (0U)
<> 151:5eaa88a5bcc7 2069 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
<> 151:5eaa88a5bcc7 2070 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
<> 151:5eaa88a5bcc7 2071 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2072 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2073 #define GPIO_MODER_MODE1_Pos (2U)
<> 151:5eaa88a5bcc7 2074 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
<> 151:5eaa88a5bcc7 2075 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
<> 151:5eaa88a5bcc7 2076 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2077 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2078 #define GPIO_MODER_MODE2_Pos (4U)
<> 151:5eaa88a5bcc7 2079 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
<> 151:5eaa88a5bcc7 2080 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
<> 151:5eaa88a5bcc7 2081 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2082 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2083 #define GPIO_MODER_MODE3_Pos (6U)
<> 151:5eaa88a5bcc7 2084 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
<> 151:5eaa88a5bcc7 2085 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
<> 151:5eaa88a5bcc7 2086 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2087 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 2088 #define GPIO_MODER_MODE4_Pos (8U)
<> 151:5eaa88a5bcc7 2089 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
<> 151:5eaa88a5bcc7 2090 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
<> 151:5eaa88a5bcc7 2091 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2092 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 2093 #define GPIO_MODER_MODE5_Pos (10U)
<> 151:5eaa88a5bcc7 2094 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
<> 151:5eaa88a5bcc7 2095 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
<> 151:5eaa88a5bcc7 2096 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2097 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 2098 #define GPIO_MODER_MODE6_Pos (12U)
<> 151:5eaa88a5bcc7 2099 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
<> 151:5eaa88a5bcc7 2100 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
<> 151:5eaa88a5bcc7 2101 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2102 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 2103 #define GPIO_MODER_MODE7_Pos (14U)
<> 151:5eaa88a5bcc7 2104 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
<> 151:5eaa88a5bcc7 2105 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
<> 151:5eaa88a5bcc7 2106 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 2107 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2108 #define GPIO_MODER_MODE8_Pos (16U)
<> 151:5eaa88a5bcc7 2109 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
<> 151:5eaa88a5bcc7 2110 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
<> 151:5eaa88a5bcc7 2111 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 2112 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 2113 #define GPIO_MODER_MODE9_Pos (18U)
<> 151:5eaa88a5bcc7 2114 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
<> 151:5eaa88a5bcc7 2115 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
<> 151:5eaa88a5bcc7 2116 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 2117 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 2118 #define GPIO_MODER_MODE10_Pos (20U)
<> 151:5eaa88a5bcc7 2119 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
<> 151:5eaa88a5bcc7 2120 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
<> 151:5eaa88a5bcc7 2121 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 2122 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 2123 #define GPIO_MODER_MODE11_Pos (22U)
<> 151:5eaa88a5bcc7 2124 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
<> 151:5eaa88a5bcc7 2125 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
<> 151:5eaa88a5bcc7 2126 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 2127 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 2128 #define GPIO_MODER_MODE12_Pos (24U)
<> 151:5eaa88a5bcc7 2129 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
<> 151:5eaa88a5bcc7 2130 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
<> 151:5eaa88a5bcc7 2131 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 2132 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 2133 #define GPIO_MODER_MODE13_Pos (26U)
<> 151:5eaa88a5bcc7 2134 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
<> 151:5eaa88a5bcc7 2135 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
<> 151:5eaa88a5bcc7 2136 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 2137 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 2138 #define GPIO_MODER_MODE14_Pos (28U)
<> 151:5eaa88a5bcc7 2139 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
<> 151:5eaa88a5bcc7 2140 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
<> 151:5eaa88a5bcc7 2141 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 2142 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 2143 #define GPIO_MODER_MODE15_Pos (30U)
<> 151:5eaa88a5bcc7 2144 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
<> 151:5eaa88a5bcc7 2145 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
<> 151:5eaa88a5bcc7 2146 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 2147 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
mbed_official 114:fe4fe5cfc3a3 2148
mbed_official 114:fe4fe5cfc3a3 2149 /****************** Bit definition for GPIO_OTYPER register *****************/
<> 151:5eaa88a5bcc7 2150 #define GPIO_OTYPER_OT_0 (0x00000001U)
<> 151:5eaa88a5bcc7 2151 #define GPIO_OTYPER_OT_1 (0x00000002U)
<> 151:5eaa88a5bcc7 2152 #define GPIO_OTYPER_OT_2 (0x00000004U)
<> 151:5eaa88a5bcc7 2153 #define GPIO_OTYPER_OT_3 (0x00000008U)
<> 151:5eaa88a5bcc7 2154 #define GPIO_OTYPER_OT_4 (0x00000010U)
<> 151:5eaa88a5bcc7 2155 #define GPIO_OTYPER_OT_5 (0x00000020U)
<> 151:5eaa88a5bcc7 2156 #define GPIO_OTYPER_OT_6 (0x00000040U)
<> 151:5eaa88a5bcc7 2157 #define GPIO_OTYPER_OT_7 (0x00000080U)
<> 151:5eaa88a5bcc7 2158 #define GPIO_OTYPER_OT_8 (0x00000100U)
<> 151:5eaa88a5bcc7 2159 #define GPIO_OTYPER_OT_9 (0x00000200U)
<> 151:5eaa88a5bcc7 2160 #define GPIO_OTYPER_OT_10 (0x00000400U)
<> 151:5eaa88a5bcc7 2161 #define GPIO_OTYPER_OT_11 (0x00000800U)
<> 151:5eaa88a5bcc7 2162 #define GPIO_OTYPER_OT_12 (0x00001000U)
<> 151:5eaa88a5bcc7 2163 #define GPIO_OTYPER_OT_13 (0x00002000U)
<> 151:5eaa88a5bcc7 2164 #define GPIO_OTYPER_OT_14 (0x00004000U)
<> 151:5eaa88a5bcc7 2165 #define GPIO_OTYPER_OT_15 (0x00008000U)
mbed_official 114:fe4fe5cfc3a3 2166
mbed_official 114:fe4fe5cfc3a3 2167 /**************** Bit definition for GPIO_OSPEEDR register ******************/
<> 151:5eaa88a5bcc7 2168 #define GPIO_OSPEEDER_OSPEED0_Pos (0U)
<> 151:5eaa88a5bcc7 2169 #define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
<> 151:5eaa88a5bcc7 2170 #define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
<> 151:5eaa88a5bcc7 2171 #define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2172 #define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2173 #define GPIO_OSPEEDER_OSPEED1_Pos (2U)
<> 151:5eaa88a5bcc7 2174 #define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
<> 151:5eaa88a5bcc7 2175 #define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
<> 151:5eaa88a5bcc7 2176 #define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2177 #define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2178 #define GPIO_OSPEEDER_OSPEED2_Pos (4U)
<> 151:5eaa88a5bcc7 2179 #define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
<> 151:5eaa88a5bcc7 2180 #define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
<> 151:5eaa88a5bcc7 2181 #define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2182 #define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2183 #define GPIO_OSPEEDER_OSPEED3_Pos (6U)
<> 151:5eaa88a5bcc7 2184 #define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
<> 151:5eaa88a5bcc7 2185 #define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
<> 151:5eaa88a5bcc7 2186 #define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2187 #define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 2188 #define GPIO_OSPEEDER_OSPEED4_Pos (8U)
<> 151:5eaa88a5bcc7 2189 #define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
<> 151:5eaa88a5bcc7 2190 #define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
<> 151:5eaa88a5bcc7 2191 #define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2192 #define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 2193 #define GPIO_OSPEEDER_OSPEED5_Pos (10U)
<> 151:5eaa88a5bcc7 2194 #define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
<> 151:5eaa88a5bcc7 2195 #define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
<> 151:5eaa88a5bcc7 2196 #define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2197 #define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 2198 #define GPIO_OSPEEDER_OSPEED6_Pos (12U)
<> 151:5eaa88a5bcc7 2199 #define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
<> 151:5eaa88a5bcc7 2200 #define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
<> 151:5eaa88a5bcc7 2201 #define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2202 #define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 2203 #define GPIO_OSPEEDER_OSPEED7_Pos (14U)
<> 151:5eaa88a5bcc7 2204 #define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
<> 151:5eaa88a5bcc7 2205 #define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
<> 151:5eaa88a5bcc7 2206 #define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 2207 #define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2208 #define GPIO_OSPEEDER_OSPEED8_Pos (16U)
<> 151:5eaa88a5bcc7 2209 #define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
<> 151:5eaa88a5bcc7 2210 #define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
<> 151:5eaa88a5bcc7 2211 #define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 2212 #define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 2213 #define GPIO_OSPEEDER_OSPEED9_Pos (18U)
<> 151:5eaa88a5bcc7 2214 #define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
<> 151:5eaa88a5bcc7 2215 #define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
<> 151:5eaa88a5bcc7 2216 #define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 2217 #define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 2218 #define GPIO_OSPEEDER_OSPEED10_Pos (20U)
<> 151:5eaa88a5bcc7 2219 #define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
<> 151:5eaa88a5bcc7 2220 #define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
<> 151:5eaa88a5bcc7 2221 #define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 2222 #define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 2223 #define GPIO_OSPEEDER_OSPEED11_Pos (22U)
<> 151:5eaa88a5bcc7 2224 #define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
<> 151:5eaa88a5bcc7 2225 #define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
<> 151:5eaa88a5bcc7 2226 #define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 2227 #define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 2228 #define GPIO_OSPEEDER_OSPEED12_Pos (24U)
<> 151:5eaa88a5bcc7 2229 #define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
<> 151:5eaa88a5bcc7 2230 #define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
<> 151:5eaa88a5bcc7 2231 #define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 2232 #define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 2233 #define GPIO_OSPEEDER_OSPEED13_Pos (26U)
<> 151:5eaa88a5bcc7 2234 #define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
<> 151:5eaa88a5bcc7 2235 #define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
<> 151:5eaa88a5bcc7 2236 #define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 2237 #define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 2238 #define GPIO_OSPEEDER_OSPEED14_Pos (28U)
<> 151:5eaa88a5bcc7 2239 #define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
<> 151:5eaa88a5bcc7 2240 #define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
<> 151:5eaa88a5bcc7 2241 #define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 2242 #define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 2243 #define GPIO_OSPEEDER_OSPEED15_Pos (30U)
<> 151:5eaa88a5bcc7 2244 #define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
<> 151:5eaa88a5bcc7 2245 #define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
<> 151:5eaa88a5bcc7 2246 #define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 2247 #define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
mbed_official 114:fe4fe5cfc3a3 2248
mbed_official 114:fe4fe5cfc3a3 2249 /******************* Bit definition for GPIO_PUPDR register ******************/
<> 151:5eaa88a5bcc7 2250 #define GPIO_PUPDR_PUPD0_Pos (0U)
<> 151:5eaa88a5bcc7 2251 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
<> 151:5eaa88a5bcc7 2252 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
<> 151:5eaa88a5bcc7 2253 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2254 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2255 #define GPIO_PUPDR_PUPD1_Pos (2U)
<> 151:5eaa88a5bcc7 2256 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
<> 151:5eaa88a5bcc7 2257 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
<> 151:5eaa88a5bcc7 2258 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2259 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2260 #define GPIO_PUPDR_PUPD2_Pos (4U)
<> 151:5eaa88a5bcc7 2261 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
<> 151:5eaa88a5bcc7 2262 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
<> 151:5eaa88a5bcc7 2263 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2264 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2265 #define GPIO_PUPDR_PUPD3_Pos (6U)
<> 151:5eaa88a5bcc7 2266 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
<> 151:5eaa88a5bcc7 2267 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
<> 151:5eaa88a5bcc7 2268 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2269 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 2270 #define GPIO_PUPDR_PUPD4_Pos (8U)
<> 151:5eaa88a5bcc7 2271 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
<> 151:5eaa88a5bcc7 2272 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
<> 151:5eaa88a5bcc7 2273 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2274 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 2275 #define GPIO_PUPDR_PUPD5_Pos (10U)
<> 151:5eaa88a5bcc7 2276 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
<> 151:5eaa88a5bcc7 2277 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
<> 151:5eaa88a5bcc7 2278 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2279 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 2280 #define GPIO_PUPDR_PUPD6_Pos (12U)
<> 151:5eaa88a5bcc7 2281 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
<> 151:5eaa88a5bcc7 2282 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
<> 151:5eaa88a5bcc7 2283 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2284 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 2285 #define GPIO_PUPDR_PUPD7_Pos (14U)
<> 151:5eaa88a5bcc7 2286 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
<> 151:5eaa88a5bcc7 2287 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
<> 151:5eaa88a5bcc7 2288 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 2289 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2290 #define GPIO_PUPDR_PUPD8_Pos (16U)
<> 151:5eaa88a5bcc7 2291 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
<> 151:5eaa88a5bcc7 2292 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
<> 151:5eaa88a5bcc7 2293 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 2294 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 2295 #define GPIO_PUPDR_PUPD9_Pos (18U)
<> 151:5eaa88a5bcc7 2296 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
<> 151:5eaa88a5bcc7 2297 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
<> 151:5eaa88a5bcc7 2298 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 2299 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 2300 #define GPIO_PUPDR_PUPD10_Pos (20U)
<> 151:5eaa88a5bcc7 2301 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
<> 151:5eaa88a5bcc7 2302 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
<> 151:5eaa88a5bcc7 2303 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 2304 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 2305 #define GPIO_PUPDR_PUPD11_Pos (22U)
<> 151:5eaa88a5bcc7 2306 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
<> 151:5eaa88a5bcc7 2307 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
<> 151:5eaa88a5bcc7 2308 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 2309 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 2310 #define GPIO_PUPDR_PUPD12_Pos (24U)
<> 151:5eaa88a5bcc7 2311 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
<> 151:5eaa88a5bcc7 2312 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
<> 151:5eaa88a5bcc7 2313 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 2314 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 2315 #define GPIO_PUPDR_PUPD13_Pos (26U)
<> 151:5eaa88a5bcc7 2316 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
<> 151:5eaa88a5bcc7 2317 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
<> 151:5eaa88a5bcc7 2318 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 2319 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 2320 #define GPIO_PUPDR_PUPD14_Pos (28U)
<> 151:5eaa88a5bcc7 2321 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
<> 151:5eaa88a5bcc7 2322 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
<> 151:5eaa88a5bcc7 2323 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 2324 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 2325 #define GPIO_PUPDR_PUPD15_Pos (30U)
<> 151:5eaa88a5bcc7 2326 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
<> 151:5eaa88a5bcc7 2327 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
<> 151:5eaa88a5bcc7 2328 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 2329 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
mbed_official 114:fe4fe5cfc3a3 2330
mbed_official 114:fe4fe5cfc3a3 2331 /******************* Bit definition for GPIO_IDR register *******************/
<> 151:5eaa88a5bcc7 2332 #define GPIO_IDR_ID0_Pos (0U)
<> 151:5eaa88a5bcc7 2333 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2334 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
<> 151:5eaa88a5bcc7 2335 #define GPIO_IDR_ID1_Pos (1U)
<> 151:5eaa88a5bcc7 2336 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2337 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
<> 151:5eaa88a5bcc7 2338 #define GPIO_IDR_ID2_Pos (2U)
<> 151:5eaa88a5bcc7 2339 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2340 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
<> 151:5eaa88a5bcc7 2341 #define GPIO_IDR_ID3_Pos (3U)
<> 151:5eaa88a5bcc7 2342 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2343 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
<> 151:5eaa88a5bcc7 2344 #define GPIO_IDR_ID4_Pos (4U)
<> 151:5eaa88a5bcc7 2345 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2346 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
<> 151:5eaa88a5bcc7 2347 #define GPIO_IDR_ID5_Pos (5U)
<> 151:5eaa88a5bcc7 2348 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2349 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
<> 151:5eaa88a5bcc7 2350 #define GPIO_IDR_ID6_Pos (6U)
<> 151:5eaa88a5bcc7 2351 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2352 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
<> 151:5eaa88a5bcc7 2353 #define GPIO_IDR_ID7_Pos (7U)
<> 151:5eaa88a5bcc7 2354 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 2355 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
<> 151:5eaa88a5bcc7 2356 #define GPIO_IDR_ID8_Pos (8U)
<> 151:5eaa88a5bcc7 2357 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2358 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
<> 151:5eaa88a5bcc7 2359 #define GPIO_IDR_ID9_Pos (9U)
<> 151:5eaa88a5bcc7 2360 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 2361 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
<> 151:5eaa88a5bcc7 2362 #define GPIO_IDR_ID10_Pos (10U)
<> 151:5eaa88a5bcc7 2363 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2364 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
<> 151:5eaa88a5bcc7 2365 #define GPIO_IDR_ID11_Pos (11U)
<> 151:5eaa88a5bcc7 2366 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 2367 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
<> 151:5eaa88a5bcc7 2368 #define GPIO_IDR_ID12_Pos (12U)
<> 151:5eaa88a5bcc7 2369 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2370 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
<> 151:5eaa88a5bcc7 2371 #define GPIO_IDR_ID13_Pos (13U)
<> 151:5eaa88a5bcc7 2372 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 2373 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
<> 151:5eaa88a5bcc7 2374 #define GPIO_IDR_ID14_Pos (14U)
<> 151:5eaa88a5bcc7 2375 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 2376 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
<> 151:5eaa88a5bcc7 2377 #define GPIO_IDR_ID15_Pos (15U)
<> 151:5eaa88a5bcc7 2378 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2379 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
mbed_official 114:fe4fe5cfc3a3 2380
mbed_official 114:fe4fe5cfc3a3 2381 /****************** Bit definition for GPIO_ODR register ********************/
<> 151:5eaa88a5bcc7 2382 #define GPIO_ODR_OD0_Pos (0U)
<> 151:5eaa88a5bcc7 2383 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2384 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
<> 151:5eaa88a5bcc7 2385 #define GPIO_ODR_OD1_Pos (1U)
<> 151:5eaa88a5bcc7 2386 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2387 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
<> 151:5eaa88a5bcc7 2388 #define GPIO_ODR_OD2_Pos (2U)
<> 151:5eaa88a5bcc7 2389 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2390 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
<> 151:5eaa88a5bcc7 2391 #define GPIO_ODR_OD3_Pos (3U)
<> 151:5eaa88a5bcc7 2392 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2393 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
<> 151:5eaa88a5bcc7 2394 #define GPIO_ODR_OD4_Pos (4U)
<> 151:5eaa88a5bcc7 2395 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2396 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
<> 151:5eaa88a5bcc7 2397 #define GPIO_ODR_OD5_Pos (5U)
<> 151:5eaa88a5bcc7 2398 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2399 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
<> 151:5eaa88a5bcc7 2400 #define GPIO_ODR_OD6_Pos (6U)
<> 151:5eaa88a5bcc7 2401 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2402 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
<> 151:5eaa88a5bcc7 2403 #define GPIO_ODR_OD7_Pos (7U)
<> 151:5eaa88a5bcc7 2404 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 2405 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
<> 151:5eaa88a5bcc7 2406 #define GPIO_ODR_OD8_Pos (8U)
<> 151:5eaa88a5bcc7 2407 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2408 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
<> 151:5eaa88a5bcc7 2409 #define GPIO_ODR_OD9_Pos (9U)
<> 151:5eaa88a5bcc7 2410 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 2411 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
<> 151:5eaa88a5bcc7 2412 #define GPIO_ODR_OD10_Pos (10U)
<> 151:5eaa88a5bcc7 2413 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2414 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
<> 151:5eaa88a5bcc7 2415 #define GPIO_ODR_OD11_Pos (11U)
<> 151:5eaa88a5bcc7 2416 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 2417 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
<> 151:5eaa88a5bcc7 2418 #define GPIO_ODR_OD12_Pos (12U)
<> 151:5eaa88a5bcc7 2419 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2420 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
<> 151:5eaa88a5bcc7 2421 #define GPIO_ODR_OD13_Pos (13U)
<> 151:5eaa88a5bcc7 2422 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 2423 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
<> 151:5eaa88a5bcc7 2424 #define GPIO_ODR_OD14_Pos (14U)
<> 151:5eaa88a5bcc7 2425 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 2426 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
<> 151:5eaa88a5bcc7 2427 #define GPIO_ODR_OD15_Pos (15U)
<> 151:5eaa88a5bcc7 2428 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2429 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
mbed_official 114:fe4fe5cfc3a3 2430
mbed_official 114:fe4fe5cfc3a3 2431 /****************** Bit definition for GPIO_BSRR register ********************/
<> 151:5eaa88a5bcc7 2432 #define GPIO_BSRR_BS_0 (0x00000001U)
<> 151:5eaa88a5bcc7 2433 #define GPIO_BSRR_BS_1 (0x00000002U)
<> 151:5eaa88a5bcc7 2434 #define GPIO_BSRR_BS_2 (0x00000004U)
<> 151:5eaa88a5bcc7 2435 #define GPIO_BSRR_BS_3 (0x00000008U)
<> 151:5eaa88a5bcc7 2436 #define GPIO_BSRR_BS_4 (0x00000010U)
<> 151:5eaa88a5bcc7 2437 #define GPIO_BSRR_BS_5 (0x00000020U)
<> 151:5eaa88a5bcc7 2438 #define GPIO_BSRR_BS_6 (0x00000040U)
<> 151:5eaa88a5bcc7 2439 #define GPIO_BSRR_BS_7 (0x00000080U)
<> 151:5eaa88a5bcc7 2440 #define GPIO_BSRR_BS_8 (0x00000100U)
<> 151:5eaa88a5bcc7 2441 #define GPIO_BSRR_BS_9 (0x00000200U)
<> 151:5eaa88a5bcc7 2442 #define GPIO_BSRR_BS_10 (0x00000400U)
<> 151:5eaa88a5bcc7 2443 #define GPIO_BSRR_BS_11 (0x00000800U)
<> 151:5eaa88a5bcc7 2444 #define GPIO_BSRR_BS_12 (0x00001000U)
<> 151:5eaa88a5bcc7 2445 #define GPIO_BSRR_BS_13 (0x00002000U)
<> 151:5eaa88a5bcc7 2446 #define GPIO_BSRR_BS_14 (0x00004000U)
<> 151:5eaa88a5bcc7 2447 #define GPIO_BSRR_BS_15 (0x00008000U)
<> 151:5eaa88a5bcc7 2448 #define GPIO_BSRR_BR_0 (0x00010000U)
<> 151:5eaa88a5bcc7 2449 #define GPIO_BSRR_BR_1 (0x00020000U)
<> 151:5eaa88a5bcc7 2450 #define GPIO_BSRR_BR_2 (0x00040000U)
<> 151:5eaa88a5bcc7 2451 #define GPIO_BSRR_BR_3 (0x00080000U)
<> 151:5eaa88a5bcc7 2452 #define GPIO_BSRR_BR_4 (0x00100000U)
<> 151:5eaa88a5bcc7 2453 #define GPIO_BSRR_BR_5 (0x00200000U)
<> 151:5eaa88a5bcc7 2454 #define GPIO_BSRR_BR_6 (0x00400000U)
<> 151:5eaa88a5bcc7 2455 #define GPIO_BSRR_BR_7 (0x00800000U)
<> 151:5eaa88a5bcc7 2456 #define GPIO_BSRR_BR_8 (0x01000000U)
<> 151:5eaa88a5bcc7 2457 #define GPIO_BSRR_BR_9 (0x02000000U)
<> 151:5eaa88a5bcc7 2458 #define GPIO_BSRR_BR_10 (0x04000000U)
<> 151:5eaa88a5bcc7 2459 #define GPIO_BSRR_BR_11 (0x08000000U)
<> 151:5eaa88a5bcc7 2460 #define GPIO_BSRR_BR_12 (0x10000000U)
<> 151:5eaa88a5bcc7 2461 #define GPIO_BSRR_BR_13 (0x20000000U)
<> 151:5eaa88a5bcc7 2462 #define GPIO_BSRR_BR_14 (0x40000000U)
<> 151:5eaa88a5bcc7 2463 #define GPIO_BSRR_BR_15 (0x80000000U)
mbed_official 114:fe4fe5cfc3a3 2464
mbed_official 114:fe4fe5cfc3a3 2465 /****************** Bit definition for GPIO_LCKR register ********************/
<> 151:5eaa88a5bcc7 2466 #define GPIO_LCKR_LCK0_Pos (0U)
<> 151:5eaa88a5bcc7 2467 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2468 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
<> 151:5eaa88a5bcc7 2469 #define GPIO_LCKR_LCK1_Pos (1U)
<> 151:5eaa88a5bcc7 2470 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2471 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
<> 151:5eaa88a5bcc7 2472 #define GPIO_LCKR_LCK2_Pos (2U)
<> 151:5eaa88a5bcc7 2473 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2474 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
<> 151:5eaa88a5bcc7 2475 #define GPIO_LCKR_LCK3_Pos (3U)
<> 151:5eaa88a5bcc7 2476 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2477 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
<> 151:5eaa88a5bcc7 2478 #define GPIO_LCKR_LCK4_Pos (4U)
<> 151:5eaa88a5bcc7 2479 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2480 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
<> 151:5eaa88a5bcc7 2481 #define GPIO_LCKR_LCK5_Pos (5U)
<> 151:5eaa88a5bcc7 2482 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2483 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
<> 151:5eaa88a5bcc7 2484 #define GPIO_LCKR_LCK6_Pos (6U)
<> 151:5eaa88a5bcc7 2485 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2486 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
<> 151:5eaa88a5bcc7 2487 #define GPIO_LCKR_LCK7_Pos (7U)
<> 151:5eaa88a5bcc7 2488 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 2489 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
<> 151:5eaa88a5bcc7 2490 #define GPIO_LCKR_LCK8_Pos (8U)
<> 151:5eaa88a5bcc7 2491 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2492 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
<> 151:5eaa88a5bcc7 2493 #define GPIO_LCKR_LCK9_Pos (9U)
<> 151:5eaa88a5bcc7 2494 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 2495 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
<> 151:5eaa88a5bcc7 2496 #define GPIO_LCKR_LCK10_Pos (10U)
<> 151:5eaa88a5bcc7 2497 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2498 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
<> 151:5eaa88a5bcc7 2499 #define GPIO_LCKR_LCK11_Pos (11U)
<> 151:5eaa88a5bcc7 2500 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 2501 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
<> 151:5eaa88a5bcc7 2502 #define GPIO_LCKR_LCK12_Pos (12U)
<> 151:5eaa88a5bcc7 2503 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2504 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
<> 151:5eaa88a5bcc7 2505 #define GPIO_LCKR_LCK13_Pos (13U)
<> 151:5eaa88a5bcc7 2506 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 2507 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
<> 151:5eaa88a5bcc7 2508 #define GPIO_LCKR_LCK14_Pos (14U)
<> 151:5eaa88a5bcc7 2509 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 2510 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
<> 151:5eaa88a5bcc7 2511 #define GPIO_LCKR_LCK15_Pos (15U)
<> 151:5eaa88a5bcc7 2512 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2513 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
<> 151:5eaa88a5bcc7 2514 #define GPIO_LCKR_LCKK_Pos (16U)
<> 151:5eaa88a5bcc7 2515 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 2516 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
mbed_official 114:fe4fe5cfc3a3 2517
mbed_official 114:fe4fe5cfc3a3 2518 /****************** Bit definition for GPIO_AFRL register ********************/
<> 151:5eaa88a5bcc7 2519 #define GPIO_AFRL_AFRL0_Pos (0U)
<> 151:5eaa88a5bcc7 2520 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 2521 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
<> 151:5eaa88a5bcc7 2522 #define GPIO_AFRL_AFRL1_Pos (4U)
<> 151:5eaa88a5bcc7 2523 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
<> 151:5eaa88a5bcc7 2524 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
<> 151:5eaa88a5bcc7 2525 #define GPIO_AFRL_AFRL2_Pos (8U)
<> 151:5eaa88a5bcc7 2526 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 2527 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
<> 151:5eaa88a5bcc7 2528 #define GPIO_AFRL_AFRL3_Pos (12U)
<> 151:5eaa88a5bcc7 2529 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
<> 151:5eaa88a5bcc7 2530 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
<> 151:5eaa88a5bcc7 2531 #define GPIO_AFRL_AFRL4_Pos (16U)
<> 151:5eaa88a5bcc7 2532 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
<> 151:5eaa88a5bcc7 2533 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
<> 151:5eaa88a5bcc7 2534 #define GPIO_AFRL_AFRL5_Pos (20U)
<> 151:5eaa88a5bcc7 2535 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
<> 151:5eaa88a5bcc7 2536 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
<> 151:5eaa88a5bcc7 2537 #define GPIO_AFRL_AFRL6_Pos (24U)
<> 151:5eaa88a5bcc7 2538 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
<> 151:5eaa88a5bcc7 2539 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
<> 151:5eaa88a5bcc7 2540 #define GPIO_AFRL_AFRL7_Pos (28U)
<> 151:5eaa88a5bcc7 2541 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
<> 151:5eaa88a5bcc7 2542 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
mbed_official 114:fe4fe5cfc3a3 2543
mbed_official 114:fe4fe5cfc3a3 2544 /****************** Bit definition for GPIO_AFRH register ********************/
<> 151:5eaa88a5bcc7 2545 #define GPIO_AFRH_AFRH0_Pos (0U)
<> 151:5eaa88a5bcc7 2546 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 2547 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
<> 151:5eaa88a5bcc7 2548 #define GPIO_AFRH_AFRH1_Pos (4U)
<> 151:5eaa88a5bcc7 2549 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
<> 151:5eaa88a5bcc7 2550 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
<> 151:5eaa88a5bcc7 2551 #define GPIO_AFRH_AFRH2_Pos (8U)
<> 151:5eaa88a5bcc7 2552 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 2553 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
<> 151:5eaa88a5bcc7 2554 #define GPIO_AFRH_AFRH3_Pos (12U)
<> 151:5eaa88a5bcc7 2555 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
<> 151:5eaa88a5bcc7 2556 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
<> 151:5eaa88a5bcc7 2557 #define GPIO_AFRH_AFRH4_Pos (16U)
<> 151:5eaa88a5bcc7 2558 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
<> 151:5eaa88a5bcc7 2559 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
<> 151:5eaa88a5bcc7 2560 #define GPIO_AFRH_AFRH5_Pos (20U)
<> 151:5eaa88a5bcc7 2561 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
<> 151:5eaa88a5bcc7 2562 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
<> 151:5eaa88a5bcc7 2563 #define GPIO_AFRH_AFRH6_Pos (24U)
<> 151:5eaa88a5bcc7 2564 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
<> 151:5eaa88a5bcc7 2565 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
<> 151:5eaa88a5bcc7 2566 #define GPIO_AFRH_AFRH7_Pos (28U)
<> 151:5eaa88a5bcc7 2567 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
<> 151:5eaa88a5bcc7 2568 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
mbed_official 114:fe4fe5cfc3a3 2569
mbed_official 114:fe4fe5cfc3a3 2570 /****************** Bit definition for GPIO_BRR register *********************/
<> 151:5eaa88a5bcc7 2571 #define GPIO_BRR_BR_0 (0x00000001U)
<> 151:5eaa88a5bcc7 2572 #define GPIO_BRR_BR_1 (0x00000002U)
<> 151:5eaa88a5bcc7 2573 #define GPIO_BRR_BR_2 (0x00000004U)
<> 151:5eaa88a5bcc7 2574 #define GPIO_BRR_BR_3 (0x00000008U)
<> 151:5eaa88a5bcc7 2575 #define GPIO_BRR_BR_4 (0x00000010U)
<> 151:5eaa88a5bcc7 2576 #define GPIO_BRR_BR_5 (0x00000020U)
<> 151:5eaa88a5bcc7 2577 #define GPIO_BRR_BR_6 (0x00000040U)
<> 151:5eaa88a5bcc7 2578 #define GPIO_BRR_BR_7 (0x00000080U)
<> 151:5eaa88a5bcc7 2579 #define GPIO_BRR_BR_8 (0x00000100U)
<> 151:5eaa88a5bcc7 2580 #define GPIO_BRR_BR_9 (0x00000200U)
<> 151:5eaa88a5bcc7 2581 #define GPIO_BRR_BR_10 (0x00000400U)
<> 151:5eaa88a5bcc7 2582 #define GPIO_BRR_BR_11 (0x00000800U)
<> 151:5eaa88a5bcc7 2583 #define GPIO_BRR_BR_12 (0x00001000U)
<> 151:5eaa88a5bcc7 2584 #define GPIO_BRR_BR_13 (0x00002000U)
<> 151:5eaa88a5bcc7 2585 #define GPIO_BRR_BR_14 (0x00004000U)
<> 151:5eaa88a5bcc7 2586 #define GPIO_BRR_BR_15 (0x00008000U)
mbed_official 114:fe4fe5cfc3a3 2587
mbed_official 114:fe4fe5cfc3a3 2588 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 2589 /* */
mbed_official 114:fe4fe5cfc3a3 2590 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 114:fe4fe5cfc3a3 2591 /* */
mbed_official 114:fe4fe5cfc3a3 2592 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 2593
mbed_official 114:fe4fe5cfc3a3 2594 /******************* Bit definition for I2C_CR1 register *******************/
<> 151:5eaa88a5bcc7 2595 #define I2C_CR1_PE_Pos (0U)
<> 151:5eaa88a5bcc7 2596 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2597 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
<> 151:5eaa88a5bcc7 2598 #define I2C_CR1_TXIE_Pos (1U)
<> 151:5eaa88a5bcc7 2599 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2600 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
<> 151:5eaa88a5bcc7 2601 #define I2C_CR1_RXIE_Pos (2U)
<> 151:5eaa88a5bcc7 2602 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2603 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
<> 151:5eaa88a5bcc7 2604 #define I2C_CR1_ADDRIE_Pos (3U)
<> 151:5eaa88a5bcc7 2605 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2606 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
<> 151:5eaa88a5bcc7 2607 #define I2C_CR1_NACKIE_Pos (4U)
<> 151:5eaa88a5bcc7 2608 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2609 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
<> 151:5eaa88a5bcc7 2610 #define I2C_CR1_STOPIE_Pos (5U)
<> 151:5eaa88a5bcc7 2611 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2612 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
<> 151:5eaa88a5bcc7 2613 #define I2C_CR1_TCIE_Pos (6U)
<> 151:5eaa88a5bcc7 2614 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2615 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 151:5eaa88a5bcc7 2616 #define I2C_CR1_ERRIE_Pos (7U)
<> 151:5eaa88a5bcc7 2617 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 2618 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
<> 151:5eaa88a5bcc7 2619 #define I2C_CR1_DNF_Pos (8U)
<> 151:5eaa88a5bcc7 2620 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 2621 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
<> 151:5eaa88a5bcc7 2622 #define I2C_CR1_ANFOFF_Pos (12U)
<> 151:5eaa88a5bcc7 2623 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2624 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
<> 151:5eaa88a5bcc7 2625 #define I2C_CR1_TXDMAEN_Pos (14U)
<> 151:5eaa88a5bcc7 2626 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 2627 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
<> 151:5eaa88a5bcc7 2628 #define I2C_CR1_RXDMAEN_Pos (15U)
<> 151:5eaa88a5bcc7 2629 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2630 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
<> 151:5eaa88a5bcc7 2631 #define I2C_CR1_SBC_Pos (16U)
<> 151:5eaa88a5bcc7 2632 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 2633 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
<> 151:5eaa88a5bcc7 2634 #define I2C_CR1_NOSTRETCH_Pos (17U)
<> 151:5eaa88a5bcc7 2635 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 2636 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
<> 151:5eaa88a5bcc7 2637 #define I2C_CR1_WUPEN_Pos (18U)
<> 151:5eaa88a5bcc7 2638 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 2639 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
<> 151:5eaa88a5bcc7 2640 #define I2C_CR1_GCEN_Pos (19U)
<> 151:5eaa88a5bcc7 2641 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 2642 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
<> 151:5eaa88a5bcc7 2643 #define I2C_CR1_SMBHEN_Pos (20U)
<> 151:5eaa88a5bcc7 2644 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 2645 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
<> 151:5eaa88a5bcc7 2646 #define I2C_CR1_SMBDEN_Pos (21U)
<> 151:5eaa88a5bcc7 2647 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 2648 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
<> 151:5eaa88a5bcc7 2649 #define I2C_CR1_ALERTEN_Pos (22U)
<> 151:5eaa88a5bcc7 2650 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 2651 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
<> 151:5eaa88a5bcc7 2652 #define I2C_CR1_PECEN_Pos (23U)
<> 151:5eaa88a5bcc7 2653 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 2654 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
mbed_official 114:fe4fe5cfc3a3 2655
mbed_official 114:fe4fe5cfc3a3 2656 /****************** Bit definition for I2C_CR2 register ********************/
<> 151:5eaa88a5bcc7 2657 #define I2C_CR2_SADD_Pos (0U)
<> 151:5eaa88a5bcc7 2658 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
<> 151:5eaa88a5bcc7 2659 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
<> 151:5eaa88a5bcc7 2660 #define I2C_CR2_RD_WRN_Pos (10U)
<> 151:5eaa88a5bcc7 2661 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2662 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
<> 151:5eaa88a5bcc7 2663 #define I2C_CR2_ADD10_Pos (11U)
<> 151:5eaa88a5bcc7 2664 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 2665 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
<> 151:5eaa88a5bcc7 2666 #define I2C_CR2_HEAD10R_Pos (12U)
<> 151:5eaa88a5bcc7 2667 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2668 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
<> 151:5eaa88a5bcc7 2669 #define I2C_CR2_START_Pos (13U)
<> 151:5eaa88a5bcc7 2670 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 2671 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
<> 151:5eaa88a5bcc7 2672 #define I2C_CR2_STOP_Pos (14U)
<> 151:5eaa88a5bcc7 2673 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 2674 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
<> 151:5eaa88a5bcc7 2675 #define I2C_CR2_NACK_Pos (15U)
<> 151:5eaa88a5bcc7 2676 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2677 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
<> 151:5eaa88a5bcc7 2678 #define I2C_CR2_NBYTES_Pos (16U)
<> 151:5eaa88a5bcc7 2679 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
<> 151:5eaa88a5bcc7 2680 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
<> 151:5eaa88a5bcc7 2681 #define I2C_CR2_RELOAD_Pos (24U)
<> 151:5eaa88a5bcc7 2682 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 2683 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
<> 151:5eaa88a5bcc7 2684 #define I2C_CR2_AUTOEND_Pos (25U)
<> 151:5eaa88a5bcc7 2685 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 2686 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
<> 151:5eaa88a5bcc7 2687 #define I2C_CR2_PECBYTE_Pos (26U)
<> 151:5eaa88a5bcc7 2688 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 2689 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
mbed_official 114:fe4fe5cfc3a3 2690
mbed_official 114:fe4fe5cfc3a3 2691 /******************* Bit definition for I2C_OAR1 register ******************/
<> 151:5eaa88a5bcc7 2692 #define I2C_OAR1_OA1_Pos (0U)
<> 151:5eaa88a5bcc7 2693 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
<> 151:5eaa88a5bcc7 2694 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
<> 151:5eaa88a5bcc7 2695 #define I2C_OAR1_OA1MODE_Pos (10U)
<> 151:5eaa88a5bcc7 2696 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2697 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
<> 151:5eaa88a5bcc7 2698 #define I2C_OAR1_OA1EN_Pos (15U)
<> 151:5eaa88a5bcc7 2699 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2700 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
mbed_official 114:fe4fe5cfc3a3 2701
mbed_official 114:fe4fe5cfc3a3 2702 /******************* Bit definition for I2C_OAR2 register ******************/
<> 151:5eaa88a5bcc7 2703 #define I2C_OAR2_OA2_Pos (1U)
<> 151:5eaa88a5bcc7 2704 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
<> 151:5eaa88a5bcc7 2705 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
<> 151:5eaa88a5bcc7 2706 #define I2C_OAR2_OA2MSK_Pos (8U)
<> 151:5eaa88a5bcc7 2707 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
<> 151:5eaa88a5bcc7 2708 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
<> 151:5eaa88a5bcc7 2709 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
<> 151:5eaa88a5bcc7 2710 #define I2C_OAR2_OA2MASK01_Pos (8U)
<> 151:5eaa88a5bcc7 2711 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2712 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
<> 151:5eaa88a5bcc7 2713 #define I2C_OAR2_OA2MASK02_Pos (9U)
<> 151:5eaa88a5bcc7 2714 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 2715 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
<> 151:5eaa88a5bcc7 2716 #define I2C_OAR2_OA2MASK03_Pos (8U)
<> 151:5eaa88a5bcc7 2717 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
<> 151:5eaa88a5bcc7 2718 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
<> 151:5eaa88a5bcc7 2719 #define I2C_OAR2_OA2MASK04_Pos (10U)
<> 151:5eaa88a5bcc7 2720 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2721 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
<> 151:5eaa88a5bcc7 2722 #define I2C_OAR2_OA2MASK05_Pos (8U)
<> 151:5eaa88a5bcc7 2723 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
<> 151:5eaa88a5bcc7 2724 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
<> 151:5eaa88a5bcc7 2725 #define I2C_OAR2_OA2MASK06_Pos (9U)
<> 151:5eaa88a5bcc7 2726 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
<> 151:5eaa88a5bcc7 2727 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
<> 151:5eaa88a5bcc7 2728 #define I2C_OAR2_OA2MASK07_Pos (8U)
<> 151:5eaa88a5bcc7 2729 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
<> 151:5eaa88a5bcc7 2730 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
<> 151:5eaa88a5bcc7 2731 #define I2C_OAR2_OA2EN_Pos (15U)
<> 151:5eaa88a5bcc7 2732 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2733 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
mbed_official 114:fe4fe5cfc3a3 2734
mbed_official 114:fe4fe5cfc3a3 2735 /******************* Bit definition for I2C_TIMINGR register *******************/
<> 151:5eaa88a5bcc7 2736 #define I2C_TIMINGR_SCLL_Pos (0U)
<> 151:5eaa88a5bcc7 2737 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
<> 151:5eaa88a5bcc7 2738 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
<> 151:5eaa88a5bcc7 2739 #define I2C_TIMINGR_SCLH_Pos (8U)
<> 151:5eaa88a5bcc7 2740 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
<> 151:5eaa88a5bcc7 2741 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
<> 151:5eaa88a5bcc7 2742 #define I2C_TIMINGR_SDADEL_Pos (16U)
<> 151:5eaa88a5bcc7 2743 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
<> 151:5eaa88a5bcc7 2744 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
<> 151:5eaa88a5bcc7 2745 #define I2C_TIMINGR_SCLDEL_Pos (20U)
<> 151:5eaa88a5bcc7 2746 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
<> 151:5eaa88a5bcc7 2747 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
<> 151:5eaa88a5bcc7 2748 #define I2C_TIMINGR_PRESC_Pos (28U)
<> 151:5eaa88a5bcc7 2749 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
<> 151:5eaa88a5bcc7 2750 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
mbed_official 114:fe4fe5cfc3a3 2751
mbed_official 114:fe4fe5cfc3a3 2752 /******************* Bit definition for I2C_TIMEOUTR register *******************/
<> 151:5eaa88a5bcc7 2753 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
<> 151:5eaa88a5bcc7 2754 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
<> 151:5eaa88a5bcc7 2755 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
<> 151:5eaa88a5bcc7 2756 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
<> 151:5eaa88a5bcc7 2757 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2758 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
<> 151:5eaa88a5bcc7 2759 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
<> 151:5eaa88a5bcc7 2760 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2761 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
<> 151:5eaa88a5bcc7 2762 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
<> 151:5eaa88a5bcc7 2763 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
<> 151:5eaa88a5bcc7 2764 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
<> 151:5eaa88a5bcc7 2765 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
<> 151:5eaa88a5bcc7 2766 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 2767 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
mbed_official 114:fe4fe5cfc3a3 2768
mbed_official 114:fe4fe5cfc3a3 2769 /****************** Bit definition for I2C_ISR register *********************/
<> 151:5eaa88a5bcc7 2770 #define I2C_ISR_TXE_Pos (0U)
<> 151:5eaa88a5bcc7 2771 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2772 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
<> 151:5eaa88a5bcc7 2773 #define I2C_ISR_TXIS_Pos (1U)
<> 151:5eaa88a5bcc7 2774 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2775 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
<> 151:5eaa88a5bcc7 2776 #define I2C_ISR_RXNE_Pos (2U)
<> 151:5eaa88a5bcc7 2777 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2778 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
<> 151:5eaa88a5bcc7 2779 #define I2C_ISR_ADDR_Pos (3U)
<> 151:5eaa88a5bcc7 2780 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2781 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
<> 151:5eaa88a5bcc7 2782 #define I2C_ISR_NACKF_Pos (4U)
<> 151:5eaa88a5bcc7 2783 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2784 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
<> 151:5eaa88a5bcc7 2785 #define I2C_ISR_STOPF_Pos (5U)
<> 151:5eaa88a5bcc7 2786 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2787 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
<> 151:5eaa88a5bcc7 2788 #define I2C_ISR_TC_Pos (6U)
<> 151:5eaa88a5bcc7 2789 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2790 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
<> 151:5eaa88a5bcc7 2791 #define I2C_ISR_TCR_Pos (7U)
<> 151:5eaa88a5bcc7 2792 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 2793 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
<> 151:5eaa88a5bcc7 2794 #define I2C_ISR_BERR_Pos (8U)
<> 151:5eaa88a5bcc7 2795 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2796 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
<> 151:5eaa88a5bcc7 2797 #define I2C_ISR_ARLO_Pos (9U)
<> 151:5eaa88a5bcc7 2798 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 2799 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
<> 151:5eaa88a5bcc7 2800 #define I2C_ISR_OVR_Pos (10U)
<> 151:5eaa88a5bcc7 2801 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2802 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
<> 151:5eaa88a5bcc7 2803 #define I2C_ISR_PECERR_Pos (11U)
<> 151:5eaa88a5bcc7 2804 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 2805 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
<> 151:5eaa88a5bcc7 2806 #define I2C_ISR_TIMEOUT_Pos (12U)
<> 151:5eaa88a5bcc7 2807 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2808 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
<> 151:5eaa88a5bcc7 2809 #define I2C_ISR_ALERT_Pos (13U)
<> 151:5eaa88a5bcc7 2810 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 2811 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
<> 151:5eaa88a5bcc7 2812 #define I2C_ISR_BUSY_Pos (15U)
<> 151:5eaa88a5bcc7 2813 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 2814 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
<> 151:5eaa88a5bcc7 2815 #define I2C_ISR_DIR_Pos (16U)
<> 151:5eaa88a5bcc7 2816 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 2817 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
<> 151:5eaa88a5bcc7 2818 #define I2C_ISR_ADDCODE_Pos (17U)
<> 151:5eaa88a5bcc7 2819 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
<> 151:5eaa88a5bcc7 2820 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
mbed_official 114:fe4fe5cfc3a3 2821
mbed_official 114:fe4fe5cfc3a3 2822 /****************** Bit definition for I2C_ICR register *********************/
<> 151:5eaa88a5bcc7 2823 #define I2C_ICR_ADDRCF_Pos (3U)
<> 151:5eaa88a5bcc7 2824 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2825 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
<> 151:5eaa88a5bcc7 2826 #define I2C_ICR_NACKCF_Pos (4U)
<> 151:5eaa88a5bcc7 2827 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2828 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
<> 151:5eaa88a5bcc7 2829 #define I2C_ICR_STOPCF_Pos (5U)
<> 151:5eaa88a5bcc7 2830 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2831 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
<> 151:5eaa88a5bcc7 2832 #define I2C_ICR_BERRCF_Pos (8U)
<> 151:5eaa88a5bcc7 2833 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 2834 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
<> 151:5eaa88a5bcc7 2835 #define I2C_ICR_ARLOCF_Pos (9U)
<> 151:5eaa88a5bcc7 2836 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 2837 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
<> 151:5eaa88a5bcc7 2838 #define I2C_ICR_OVRCF_Pos (10U)
<> 151:5eaa88a5bcc7 2839 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 2840 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
<> 151:5eaa88a5bcc7 2841 #define I2C_ICR_PECCF_Pos (11U)
<> 151:5eaa88a5bcc7 2842 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 2843 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
<> 151:5eaa88a5bcc7 2844 #define I2C_ICR_TIMOUTCF_Pos (12U)
<> 151:5eaa88a5bcc7 2845 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 2846 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
<> 151:5eaa88a5bcc7 2847 #define I2C_ICR_ALERTCF_Pos (13U)
<> 151:5eaa88a5bcc7 2848 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 2849 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
mbed_official 114:fe4fe5cfc3a3 2850
mbed_official 114:fe4fe5cfc3a3 2851 /****************** Bit definition for I2C_PECR register *********************/
<> 151:5eaa88a5bcc7 2852 #define I2C_PECR_PEC_Pos (0U)
<> 151:5eaa88a5bcc7 2853 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
<> 151:5eaa88a5bcc7 2854 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
mbed_official 114:fe4fe5cfc3a3 2855
mbed_official 114:fe4fe5cfc3a3 2856 /****************** Bit definition for I2C_RXDR register *********************/
<> 151:5eaa88a5bcc7 2857 #define I2C_RXDR_RXDATA_Pos (0U)
<> 151:5eaa88a5bcc7 2858 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
<> 151:5eaa88a5bcc7 2859 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
mbed_official 114:fe4fe5cfc3a3 2860
mbed_official 114:fe4fe5cfc3a3 2861 /****************** Bit definition for I2C_TXDR register *********************/
<> 151:5eaa88a5bcc7 2862 #define I2C_TXDR_TXDATA_Pos (0U)
<> 151:5eaa88a5bcc7 2863 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
<> 151:5eaa88a5bcc7 2864 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
mbed_official 114:fe4fe5cfc3a3 2865
mbed_official 114:fe4fe5cfc3a3 2866 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 2867 /* */
mbed_official 114:fe4fe5cfc3a3 2868 /* Independent WATCHDOG (IWDG) */
mbed_official 114:fe4fe5cfc3a3 2869 /* */
mbed_official 114:fe4fe5cfc3a3 2870 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 2871 /******************* Bit definition for IWDG_KR register ********************/
<> 151:5eaa88a5bcc7 2872 #define IWDG_KR_KEY_Pos (0U)
<> 151:5eaa88a5bcc7 2873 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 2874 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
mbed_official 114:fe4fe5cfc3a3 2875
mbed_official 114:fe4fe5cfc3a3 2876 /******************* Bit definition for IWDG_PR register ********************/
<> 151:5eaa88a5bcc7 2877 #define IWDG_PR_PR_Pos (0U)
<> 151:5eaa88a5bcc7 2878 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
<> 151:5eaa88a5bcc7 2879 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
<> 151:5eaa88a5bcc7 2880 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2881 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2882 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
mbed_official 114:fe4fe5cfc3a3 2883
mbed_official 114:fe4fe5cfc3a3 2884 /******************* Bit definition for IWDG_RLR register *******************/
<> 151:5eaa88a5bcc7 2885 #define IWDG_RLR_RL_Pos (0U)
<> 151:5eaa88a5bcc7 2886 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
<> 151:5eaa88a5bcc7 2887 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
mbed_official 114:fe4fe5cfc3a3 2888
mbed_official 114:fe4fe5cfc3a3 2889 /******************* Bit definition for IWDG_SR register ********************/
<> 151:5eaa88a5bcc7 2890 #define IWDG_SR_PVU_Pos (0U)
<> 151:5eaa88a5bcc7 2891 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2892 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
<> 151:5eaa88a5bcc7 2893 #define IWDG_SR_RVU_Pos (1U)
<> 151:5eaa88a5bcc7 2894 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2895 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
<> 151:5eaa88a5bcc7 2896 #define IWDG_SR_WVU_Pos (2U)
<> 151:5eaa88a5bcc7 2897 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2898 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
mbed_official 114:fe4fe5cfc3a3 2899
mbed_official 114:fe4fe5cfc3a3 2900 /******************* Bit definition for IWDG_KR register ********************/
<> 151:5eaa88a5bcc7 2901 #define IWDG_WINR_WIN_Pos (0U)
<> 151:5eaa88a5bcc7 2902 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
<> 151:5eaa88a5bcc7 2903 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
mbed_official 114:fe4fe5cfc3a3 2904
mbed_official 114:fe4fe5cfc3a3 2905 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 2906 /* */
mbed_official 114:fe4fe5cfc3a3 2907 /* Low Power Timer (LPTTIM) */
mbed_official 114:fe4fe5cfc3a3 2908 /* */
mbed_official 114:fe4fe5cfc3a3 2909 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 2910 /****************** Bit definition for LPTIM_ISR register *******************/
<> 151:5eaa88a5bcc7 2911 #define LPTIM_ISR_CMPM_Pos (0U)
<> 151:5eaa88a5bcc7 2912 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2913 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
<> 151:5eaa88a5bcc7 2914 #define LPTIM_ISR_ARRM_Pos (1U)
<> 151:5eaa88a5bcc7 2915 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2916 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
<> 151:5eaa88a5bcc7 2917 #define LPTIM_ISR_EXTTRIG_Pos (2U)
<> 151:5eaa88a5bcc7 2918 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2919 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
<> 151:5eaa88a5bcc7 2920 #define LPTIM_ISR_CMPOK_Pos (3U)
<> 151:5eaa88a5bcc7 2921 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2922 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
<> 151:5eaa88a5bcc7 2923 #define LPTIM_ISR_ARROK_Pos (4U)
<> 151:5eaa88a5bcc7 2924 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2925 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
<> 151:5eaa88a5bcc7 2926 #define LPTIM_ISR_UP_Pos (5U)
<> 151:5eaa88a5bcc7 2927 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2928 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
<> 151:5eaa88a5bcc7 2929 #define LPTIM_ISR_DOWN_Pos (6U)
<> 151:5eaa88a5bcc7 2930 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2931 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
mbed_official 114:fe4fe5cfc3a3 2932
mbed_official 114:fe4fe5cfc3a3 2933 /****************** Bit definition for LPTIM_ICR register *******************/
<> 151:5eaa88a5bcc7 2934 #define LPTIM_ICR_CMPMCF_Pos (0U)
<> 151:5eaa88a5bcc7 2935 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2936 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
<> 151:5eaa88a5bcc7 2937 #define LPTIM_ICR_ARRMCF_Pos (1U)
<> 151:5eaa88a5bcc7 2938 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2939 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
<> 151:5eaa88a5bcc7 2940 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
<> 151:5eaa88a5bcc7 2941 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2942 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
<> 151:5eaa88a5bcc7 2943 #define LPTIM_ICR_CMPOKCF_Pos (3U)
<> 151:5eaa88a5bcc7 2944 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2945 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
<> 151:5eaa88a5bcc7 2946 #define LPTIM_ICR_ARROKCF_Pos (4U)
<> 151:5eaa88a5bcc7 2947 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2948 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
<> 151:5eaa88a5bcc7 2949 #define LPTIM_ICR_UPCF_Pos (5U)
<> 151:5eaa88a5bcc7 2950 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2951 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
<> 151:5eaa88a5bcc7 2952 #define LPTIM_ICR_DOWNCF_Pos (6U)
<> 151:5eaa88a5bcc7 2953 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2954 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
mbed_official 114:fe4fe5cfc3a3 2955
mbed_official 114:fe4fe5cfc3a3 2956 /****************** Bit definition for LPTIM_IER register ********************/
<> 151:5eaa88a5bcc7 2957 #define LPTIM_IER_CMPMIE_Pos (0U)
<> 151:5eaa88a5bcc7 2958 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2959 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
<> 151:5eaa88a5bcc7 2960 #define LPTIM_IER_ARRMIE_Pos (1U)
<> 151:5eaa88a5bcc7 2961 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2962 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
<> 151:5eaa88a5bcc7 2963 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
<> 151:5eaa88a5bcc7 2964 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2965 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
<> 151:5eaa88a5bcc7 2966 #define LPTIM_IER_CMPOKIE_Pos (3U)
<> 151:5eaa88a5bcc7 2967 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2968 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
<> 151:5eaa88a5bcc7 2969 #define LPTIM_IER_ARROKIE_Pos (4U)
<> 151:5eaa88a5bcc7 2970 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2971 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
<> 151:5eaa88a5bcc7 2972 #define LPTIM_IER_UPIE_Pos (5U)
<> 151:5eaa88a5bcc7 2973 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 2974 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
<> 151:5eaa88a5bcc7 2975 #define LPTIM_IER_DOWNIE_Pos (6U)
<> 151:5eaa88a5bcc7 2976 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 2977 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
mbed_official 114:fe4fe5cfc3a3 2978
mbed_official 114:fe4fe5cfc3a3 2979 /****************** Bit definition for LPTIM_CFGR register *******************/
<> 151:5eaa88a5bcc7 2980 #define LPTIM_CFGR_CKSEL_Pos (0U)
<> 151:5eaa88a5bcc7 2981 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 2982 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
<> 151:5eaa88a5bcc7 2983
<> 151:5eaa88a5bcc7 2984 #define LPTIM_CFGR_CKPOL_Pos (1U)
<> 151:5eaa88a5bcc7 2985 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
<> 151:5eaa88a5bcc7 2986 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
<> 151:5eaa88a5bcc7 2987 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 2988 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 2989
<> 151:5eaa88a5bcc7 2990 #define LPTIM_CFGR_CKFLT_Pos (3U)
<> 151:5eaa88a5bcc7 2991 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
<> 151:5eaa88a5bcc7 2992 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
<> 151:5eaa88a5bcc7 2993 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 2994 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 2995
<> 151:5eaa88a5bcc7 2996 #define LPTIM_CFGR_TRGFLT_Pos (6U)
<> 151:5eaa88a5bcc7 2997 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
<> 151:5eaa88a5bcc7 2998 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
<> 151:5eaa88a5bcc7 2999 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 3000 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 3001
<> 151:5eaa88a5bcc7 3002 #define LPTIM_CFGR_PRESC_Pos (9U)
<> 151:5eaa88a5bcc7 3003 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
<> 151:5eaa88a5bcc7 3004 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
<> 151:5eaa88a5bcc7 3005 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3006 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 3007 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 3008
<> 151:5eaa88a5bcc7 3009 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
<> 151:5eaa88a5bcc7 3010 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
<> 151:5eaa88a5bcc7 3011 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
<> 151:5eaa88a5bcc7 3012 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 3013 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 3014 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 3015
<> 151:5eaa88a5bcc7 3016 #define LPTIM_CFGR_TRIGEN_Pos (17U)
<> 151:5eaa88a5bcc7 3017 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
<> 151:5eaa88a5bcc7 3018 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
<> 151:5eaa88a5bcc7 3019 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 3020 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 3021
<> 151:5eaa88a5bcc7 3022 #define LPTIM_CFGR_TIMOUT_Pos (19U)
<> 151:5eaa88a5bcc7 3023 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 3024 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
<> 151:5eaa88a5bcc7 3025 #define LPTIM_CFGR_WAVE_Pos (20U)
<> 151:5eaa88a5bcc7 3026 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 3027 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
<> 151:5eaa88a5bcc7 3028 #define LPTIM_CFGR_WAVPOL_Pos (21U)
<> 151:5eaa88a5bcc7 3029 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 3030 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
<> 151:5eaa88a5bcc7 3031 #define LPTIM_CFGR_PRELOAD_Pos (22U)
<> 151:5eaa88a5bcc7 3032 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 3033 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
<> 151:5eaa88a5bcc7 3034 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
<> 151:5eaa88a5bcc7 3035 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 3036 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
<> 151:5eaa88a5bcc7 3037 #define LPTIM_CFGR_ENC_Pos (24U)
<> 151:5eaa88a5bcc7 3038 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 3039 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
mbed_official 114:fe4fe5cfc3a3 3040
mbed_official 114:fe4fe5cfc3a3 3041 /****************** Bit definition for LPTIM_CR register ********************/
<> 151:5eaa88a5bcc7 3042 #define LPTIM_CR_ENABLE_Pos (0U)
<> 151:5eaa88a5bcc7 3043 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3044 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
<> 151:5eaa88a5bcc7 3045 #define LPTIM_CR_SNGSTRT_Pos (1U)
<> 151:5eaa88a5bcc7 3046 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3047 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
<> 151:5eaa88a5bcc7 3048 #define LPTIM_CR_CNTSTRT_Pos (2U)
<> 151:5eaa88a5bcc7 3049 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3050 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
mbed_official 114:fe4fe5cfc3a3 3051
mbed_official 114:fe4fe5cfc3a3 3052 /****************** Bit definition for LPTIM_CMP register *******************/
<> 151:5eaa88a5bcc7 3053 #define LPTIM_CMP_CMP_Pos (0U)
<> 151:5eaa88a5bcc7 3054 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 3055 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
mbed_official 114:fe4fe5cfc3a3 3056
mbed_official 114:fe4fe5cfc3a3 3057 /****************** Bit definition for LPTIM_ARR register *******************/
<> 151:5eaa88a5bcc7 3058 #define LPTIM_ARR_ARR_Pos (0U)
<> 151:5eaa88a5bcc7 3059 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 3060 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
mbed_official 114:fe4fe5cfc3a3 3061
mbed_official 114:fe4fe5cfc3a3 3062 /****************** Bit definition for LPTIM_CNT register *******************/
<> 151:5eaa88a5bcc7 3063 #define LPTIM_CNT_CNT_Pos (0U)
<> 151:5eaa88a5bcc7 3064 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 3065 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
mbed_official 114:fe4fe5cfc3a3 3066
mbed_official 114:fe4fe5cfc3a3 3067 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 3068 /* */
mbed_official 114:fe4fe5cfc3a3 3069 /* Power Control (PWR) */
mbed_official 114:fe4fe5cfc3a3 3070 /* */
mbed_official 114:fe4fe5cfc3a3 3071 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 3072
<> 151:5eaa88a5bcc7 3073 #define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
<> 151:5eaa88a5bcc7 3074
mbed_official 114:fe4fe5cfc3a3 3075 /******************** Bit definition for PWR_CR register ********************/
<> 151:5eaa88a5bcc7 3076 #define PWR_CR_LPSDSR_Pos (0U)
<> 151:5eaa88a5bcc7 3077 #define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3078 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
<> 151:5eaa88a5bcc7 3079 #define PWR_CR_PDDS_Pos (1U)
<> 151:5eaa88a5bcc7 3080 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3081 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
<> 151:5eaa88a5bcc7 3082 #define PWR_CR_CWUF_Pos (2U)
<> 151:5eaa88a5bcc7 3083 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3084 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
<> 151:5eaa88a5bcc7 3085 #define PWR_CR_CSBF_Pos (3U)
<> 151:5eaa88a5bcc7 3086 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 3087 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
<> 151:5eaa88a5bcc7 3088 #define PWR_CR_PVDE_Pos (4U)
<> 151:5eaa88a5bcc7 3089 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 3090 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
<> 151:5eaa88a5bcc7 3091
<> 151:5eaa88a5bcc7 3092 #define PWR_CR_PLS_Pos (5U)
<> 151:5eaa88a5bcc7 3093 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
<> 151:5eaa88a5bcc7 3094 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
<> 151:5eaa88a5bcc7 3095 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3096 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 3097 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
mbed_official 114:fe4fe5cfc3a3 3098
mbed_official 114:fe4fe5cfc3a3 3099 /*!< PVD level configuration */
<> 151:5eaa88a5bcc7 3100 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
<> 151:5eaa88a5bcc7 3101 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
<> 151:5eaa88a5bcc7 3102 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
<> 151:5eaa88a5bcc7 3103 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
<> 151:5eaa88a5bcc7 3104 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
<> 151:5eaa88a5bcc7 3105 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
<> 151:5eaa88a5bcc7 3106 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
<> 151:5eaa88a5bcc7 3107 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
<> 151:5eaa88a5bcc7 3108
<> 151:5eaa88a5bcc7 3109 #define PWR_CR_DBP_Pos (8U)
<> 151:5eaa88a5bcc7 3110 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3111 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
<> 151:5eaa88a5bcc7 3112 #define PWR_CR_ULP_Pos (9U)
<> 151:5eaa88a5bcc7 3113 #define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3114 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
<> 151:5eaa88a5bcc7 3115 #define PWR_CR_FWU_Pos (10U)
<> 151:5eaa88a5bcc7 3116 #define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 3117 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
<> 151:5eaa88a5bcc7 3118
<> 151:5eaa88a5bcc7 3119 #define PWR_CR_VOS_Pos (11U)
<> 151:5eaa88a5bcc7 3120 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */
<> 151:5eaa88a5bcc7 3121 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
<> 151:5eaa88a5bcc7 3122 #define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 3123 #define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3124 #define PWR_CR_DSEEKOFF_Pos (13U)
<> 151:5eaa88a5bcc7 3125 #define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 3126 #define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
<> 151:5eaa88a5bcc7 3127 #define PWR_CR_LPRUN_Pos (14U)
<> 151:5eaa88a5bcc7 3128 #define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 3129 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
mbed_official 114:fe4fe5cfc3a3 3130
mbed_official 114:fe4fe5cfc3a3 3131 /******************* Bit definition for PWR_CSR register ********************/
<> 151:5eaa88a5bcc7 3132 #define PWR_CSR_WUF_Pos (0U)
<> 151:5eaa88a5bcc7 3133 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3134 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
<> 151:5eaa88a5bcc7 3135 #define PWR_CSR_SBF_Pos (1U)
<> 151:5eaa88a5bcc7 3136 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3137 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
<> 151:5eaa88a5bcc7 3138 #define PWR_CSR_PVDO_Pos (2U)
<> 151:5eaa88a5bcc7 3139 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3140 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
<> 151:5eaa88a5bcc7 3141 #define PWR_CSR_VREFINTRDYF_Pos (3U)
<> 151:5eaa88a5bcc7 3142 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 3143 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
<> 151:5eaa88a5bcc7 3144 #define PWR_CSR_VOSF_Pos (4U)
<> 151:5eaa88a5bcc7 3145 #define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 3146 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
<> 151:5eaa88a5bcc7 3147 #define PWR_CSR_REGLPF_Pos (5U)
<> 151:5eaa88a5bcc7 3148 #define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3149 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
<> 151:5eaa88a5bcc7 3150
<> 151:5eaa88a5bcc7 3151 #define PWR_CSR_EWUP1_Pos (8U)
<> 151:5eaa88a5bcc7 3152 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3153 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
<> 151:5eaa88a5bcc7 3154 #define PWR_CSR_EWUP2_Pos (9U)
<> 151:5eaa88a5bcc7 3155 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3156 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
<> 151:5eaa88a5bcc7 3157 #define PWR_CSR_EWUP3_Pos (10U)
<> 151:5eaa88a5bcc7 3158 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 3159 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
mbed_official 114:fe4fe5cfc3a3 3160
mbed_official 114:fe4fe5cfc3a3 3161 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 3162 /* */
mbed_official 114:fe4fe5cfc3a3 3163 /* Reset and Clock Control */
mbed_official 114:fe4fe5cfc3a3 3164 /* */
mbed_official 114:fe4fe5cfc3a3 3165 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 3166
<> 151:5eaa88a5bcc7 3167 #define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
<> 151:5eaa88a5bcc7 3168
mbed_official 114:fe4fe5cfc3a3 3169 /******************** Bit definition for RCC_CR register ********************/
<> 151:5eaa88a5bcc7 3170 #define RCC_CR_HSION_Pos (0U)
<> 151:5eaa88a5bcc7 3171 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3172 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
<> 151:5eaa88a5bcc7 3173 #define RCC_CR_HSIKERON_Pos (1U)
<> 151:5eaa88a5bcc7 3174 #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3175 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
<> 151:5eaa88a5bcc7 3176 #define RCC_CR_HSIRDY_Pos (2U)
<> 151:5eaa88a5bcc7 3177 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3178 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
<> 151:5eaa88a5bcc7 3179 #define RCC_CR_HSIDIVEN_Pos (3U)
<> 151:5eaa88a5bcc7 3180 #define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 3181 #define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
<> 151:5eaa88a5bcc7 3182 #define RCC_CR_HSIDIVF_Pos (4U)
<> 151:5eaa88a5bcc7 3183 #define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 3184 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
<> 151:5eaa88a5bcc7 3185 #define RCC_CR_HSIOUTEN_Pos (5U)
<> 151:5eaa88a5bcc7 3186 #define RCC_CR_HSIOUTEN_Msk (0x1U << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3187 #define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
<> 151:5eaa88a5bcc7 3188 #define RCC_CR_MSION_Pos (8U)
<> 151:5eaa88a5bcc7 3189 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3190 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
<> 151:5eaa88a5bcc7 3191 #define RCC_CR_MSIRDY_Pos (9U)
<> 151:5eaa88a5bcc7 3192 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3193 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
<> 151:5eaa88a5bcc7 3194 #define RCC_CR_HSEON_Pos (16U)
<> 151:5eaa88a5bcc7 3195 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 3196 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
<> 151:5eaa88a5bcc7 3197 #define RCC_CR_HSERDY_Pos (17U)
<> 151:5eaa88a5bcc7 3198 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 3199 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
<> 151:5eaa88a5bcc7 3200 #define RCC_CR_HSEBYP_Pos (18U)
<> 151:5eaa88a5bcc7 3201 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 3202 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
<> 151:5eaa88a5bcc7 3203 #define RCC_CR_CSSHSEON_Pos (19U)
<> 151:5eaa88a5bcc7 3204 #define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 3205 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
<> 151:5eaa88a5bcc7 3206 #define RCC_CR_RTCPRE_Pos (20U)
<> 151:5eaa88a5bcc7 3207 #define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
<> 151:5eaa88a5bcc7 3208 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
<> 151:5eaa88a5bcc7 3209 #define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 3210 #define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 3211 #define RCC_CR_PLLON_Pos (24U)
<> 151:5eaa88a5bcc7 3212 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 3213 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
<> 151:5eaa88a5bcc7 3214 #define RCC_CR_PLLRDY_Pos (25U)
<> 151:5eaa88a5bcc7 3215 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 3216 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
mbed_official 114:fe4fe5cfc3a3 3217
mbed_official 114:fe4fe5cfc3a3 3218 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3219 #define RCC_CR_CSSON RCC_CR_CSSHSEON
mbed_official 114:fe4fe5cfc3a3 3220
mbed_official 114:fe4fe5cfc3a3 3221 /******************** Bit definition for RCC_ICSCR register *****************/
<> 151:5eaa88a5bcc7 3222 #define RCC_ICSCR_HSICAL_Pos (0U)
<> 151:5eaa88a5bcc7 3223 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
<> 151:5eaa88a5bcc7 3224 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
<> 151:5eaa88a5bcc7 3225 #define RCC_ICSCR_HSITRIM_Pos (8U)
<> 151:5eaa88a5bcc7 3226 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
<> 151:5eaa88a5bcc7 3227 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
<> 151:5eaa88a5bcc7 3228
<> 151:5eaa88a5bcc7 3229 #define RCC_ICSCR_MSIRANGE_Pos (13U)
<> 151:5eaa88a5bcc7 3230 #define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
<> 151:5eaa88a5bcc7 3231 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
<> 151:5eaa88a5bcc7 3232 #define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
<> 151:5eaa88a5bcc7 3233 #define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 3234 #define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 3235 #define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
<> 151:5eaa88a5bcc7 3236 #define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 3237 #define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
<> 151:5eaa88a5bcc7 3238 #define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
<> 151:5eaa88a5bcc7 3239 #define RCC_ICSCR_MSICAL_Pos (16U)
<> 151:5eaa88a5bcc7 3240 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
<> 151:5eaa88a5bcc7 3241 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
<> 151:5eaa88a5bcc7 3242 #define RCC_ICSCR_MSITRIM_Pos (24U)
<> 151:5eaa88a5bcc7 3243 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
<> 151:5eaa88a5bcc7 3244 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
mbed_official 114:fe4fe5cfc3a3 3245
mbed_official 114:fe4fe5cfc3a3 3246
mbed_official 114:fe4fe5cfc3a3 3247 /******************* Bit definition for RCC_CFGR register *******************/
mbed_official 114:fe4fe5cfc3a3 3248 /*!< SW configuration */
<> 151:5eaa88a5bcc7 3249 #define RCC_CFGR_SW_Pos (0U)
<> 151:5eaa88a5bcc7 3250 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
<> 151:5eaa88a5bcc7 3251 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
<> 151:5eaa88a5bcc7 3252 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3253 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3254
<> 151:5eaa88a5bcc7 3255 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
<> 151:5eaa88a5bcc7 3256 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
<> 151:5eaa88a5bcc7 3257 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
<> 151:5eaa88a5bcc7 3258 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
mbed_official 114:fe4fe5cfc3a3 3259
mbed_official 114:fe4fe5cfc3a3 3260 /*!< SWS configuration */
<> 151:5eaa88a5bcc7 3261 #define RCC_CFGR_SWS_Pos (2U)
<> 151:5eaa88a5bcc7 3262 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
<> 151:5eaa88a5bcc7 3263 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 151:5eaa88a5bcc7 3264 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3265 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 3266
<> 151:5eaa88a5bcc7 3267 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
<> 151:5eaa88a5bcc7 3268 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
<> 151:5eaa88a5bcc7 3269 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
<> 151:5eaa88a5bcc7 3270 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
mbed_official 114:fe4fe5cfc3a3 3271
mbed_official 114:fe4fe5cfc3a3 3272 /*!< HPRE configuration */
<> 151:5eaa88a5bcc7 3273 #define RCC_CFGR_HPRE_Pos (4U)
<> 151:5eaa88a5bcc7 3274 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
<> 151:5eaa88a5bcc7 3275 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
<> 151:5eaa88a5bcc7 3276 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 3277 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3278 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 3279 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 3280
<> 151:5eaa88a5bcc7 3281 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
<> 151:5eaa88a5bcc7 3282 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
<> 151:5eaa88a5bcc7 3283 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
<> 151:5eaa88a5bcc7 3284 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
<> 151:5eaa88a5bcc7 3285 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
<> 151:5eaa88a5bcc7 3286 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
<> 151:5eaa88a5bcc7 3287 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
<> 151:5eaa88a5bcc7 3288 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
<> 151:5eaa88a5bcc7 3289 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
mbed_official 114:fe4fe5cfc3a3 3290
mbed_official 114:fe4fe5cfc3a3 3291 /*!< PPRE1 configuration */
<> 151:5eaa88a5bcc7 3292 #define RCC_CFGR_PPRE1_Pos (8U)
<> 151:5eaa88a5bcc7 3293 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
<> 151:5eaa88a5bcc7 3294 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 151:5eaa88a5bcc7 3295 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3296 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3297 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 3298
<> 151:5eaa88a5bcc7 3299 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 151:5eaa88a5bcc7 3300 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
<> 151:5eaa88a5bcc7 3301 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
<> 151:5eaa88a5bcc7 3302 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
<> 151:5eaa88a5bcc7 3303 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
mbed_official 114:fe4fe5cfc3a3 3304
mbed_official 114:fe4fe5cfc3a3 3305 /*!< PPRE2 configuration */
<> 151:5eaa88a5bcc7 3306 #define RCC_CFGR_PPRE2_Pos (11U)
<> 151:5eaa88a5bcc7 3307 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
<> 151:5eaa88a5bcc7 3308 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 151:5eaa88a5bcc7 3309 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 3310 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3311 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 3312
<> 151:5eaa88a5bcc7 3313 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 151:5eaa88a5bcc7 3314 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
<> 151:5eaa88a5bcc7 3315 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
<> 151:5eaa88a5bcc7 3316 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
<> 151:5eaa88a5bcc7 3317 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
<> 151:5eaa88a5bcc7 3318
<> 151:5eaa88a5bcc7 3319 #define RCC_CFGR_STOPWUCK_Pos (15U)
<> 151:5eaa88a5bcc7 3320 #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 3321 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
mbed_official 114:fe4fe5cfc3a3 3322
mbed_official 114:fe4fe5cfc3a3 3323 /*!< PLL entry clock source*/
<> 151:5eaa88a5bcc7 3324 #define RCC_CFGR_PLLSRC_Pos (16U)
<> 151:5eaa88a5bcc7 3325 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 3326 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
<> 151:5eaa88a5bcc7 3327
<> 151:5eaa88a5bcc7 3328 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
<> 151:5eaa88a5bcc7 3329 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
mbed_official 114:fe4fe5cfc3a3 3330
mbed_official 114:fe4fe5cfc3a3 3331
mbed_official 114:fe4fe5cfc3a3 3332 /*!< PLLMUL configuration */
<> 151:5eaa88a5bcc7 3333 #define RCC_CFGR_PLLMUL_Pos (18U)
<> 151:5eaa88a5bcc7 3334 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
<> 151:5eaa88a5bcc7 3335 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
<> 151:5eaa88a5bcc7 3336 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 3337 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 3338 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 3339 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 3340
<> 151:5eaa88a5bcc7 3341 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
<> 151:5eaa88a5bcc7 3342 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
<> 151:5eaa88a5bcc7 3343 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
<> 151:5eaa88a5bcc7 3344 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
<> 151:5eaa88a5bcc7 3345 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
<> 151:5eaa88a5bcc7 3346 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
<> 151:5eaa88a5bcc7 3347 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
<> 151:5eaa88a5bcc7 3348 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
<> 151:5eaa88a5bcc7 3349 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
mbed_official 114:fe4fe5cfc3a3 3350
mbed_official 114:fe4fe5cfc3a3 3351 /*!< PLLDIV configuration */
<> 151:5eaa88a5bcc7 3352 #define RCC_CFGR_PLLDIV_Pos (22U)
<> 151:5eaa88a5bcc7 3353 #define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
<> 151:5eaa88a5bcc7 3354 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
<> 151:5eaa88a5bcc7 3355 #define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 3356 #define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 3357
<> 151:5eaa88a5bcc7 3358 #define RCC_CFGR_PLLDIV2_Pos (22U)
<> 151:5eaa88a5bcc7 3359 #define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 3360 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
<> 151:5eaa88a5bcc7 3361 #define RCC_CFGR_PLLDIV3_Pos (23U)
<> 151:5eaa88a5bcc7 3362 #define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 3363 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
<> 151:5eaa88a5bcc7 3364 #define RCC_CFGR_PLLDIV4_Pos (22U)
<> 151:5eaa88a5bcc7 3365 #define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
<> 151:5eaa88a5bcc7 3366 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
mbed_official 114:fe4fe5cfc3a3 3367
mbed_official 114:fe4fe5cfc3a3 3368 /*!< MCO configuration */
<> 151:5eaa88a5bcc7 3369 #define RCC_CFGR_MCOSEL_Pos (24U)
<> 151:5eaa88a5bcc7 3370 #define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
<> 151:5eaa88a5bcc7 3371 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
<> 151:5eaa88a5bcc7 3372 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 3373 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 3374 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 3375 #define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 3376
<> 151:5eaa88a5bcc7 3377 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
<> 151:5eaa88a5bcc7 3378 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
<> 151:5eaa88a5bcc7 3379 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 3380 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
<> 151:5eaa88a5bcc7 3381 #define RCC_CFGR_MCOSEL_HSI_Pos (25U)
<> 151:5eaa88a5bcc7 3382 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 3383 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
<> 151:5eaa88a5bcc7 3384 #define RCC_CFGR_MCOSEL_MSI_Pos (24U)
<> 151:5eaa88a5bcc7 3385 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
<> 151:5eaa88a5bcc7 3386 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
<> 151:5eaa88a5bcc7 3387 #define RCC_CFGR_MCOSEL_HSE_Pos (26U)
<> 151:5eaa88a5bcc7 3388 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 3389 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
<> 151:5eaa88a5bcc7 3390 #define RCC_CFGR_MCOSEL_PLL_Pos (24U)
<> 151:5eaa88a5bcc7 3391 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
<> 151:5eaa88a5bcc7 3392 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
<> 151:5eaa88a5bcc7 3393 #define RCC_CFGR_MCOSEL_LSI_Pos (25U)
<> 151:5eaa88a5bcc7 3394 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
<> 151:5eaa88a5bcc7 3395 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
<> 151:5eaa88a5bcc7 3396 #define RCC_CFGR_MCOSEL_LSE_Pos (24U)
<> 151:5eaa88a5bcc7 3397 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
<> 151:5eaa88a5bcc7 3398 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
<> 151:5eaa88a5bcc7 3399
<> 151:5eaa88a5bcc7 3400 #define RCC_CFGR_MCOPRE_Pos (28U)
<> 151:5eaa88a5bcc7 3401 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
<> 151:5eaa88a5bcc7 3402 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
<> 151:5eaa88a5bcc7 3403 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 3404 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 3405 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 3406
<> 151:5eaa88a5bcc7 3407 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
<> 151:5eaa88a5bcc7 3408 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
<> 151:5eaa88a5bcc7 3409 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
<> 151:5eaa88a5bcc7 3410 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
<> 151:5eaa88a5bcc7 3411 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
mbed_official 114:fe4fe5cfc3a3 3412
mbed_official 114:fe4fe5cfc3a3 3413 /* Legacy defines */
<> 151:5eaa88a5bcc7 3414 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
<> 151:5eaa88a5bcc7 3415 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
<> 151:5eaa88a5bcc7 3416 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
<> 151:5eaa88a5bcc7 3417 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
<> 151:5eaa88a5bcc7 3418 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
<> 151:5eaa88a5bcc7 3419 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
<> 151:5eaa88a5bcc7 3420 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
<> 151:5eaa88a5bcc7 3421 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
<> 151:5eaa88a5bcc7 3422 #ifdef RCC_CFGR_MCOSEL_HSI48
<> 151:5eaa88a5bcc7 3423 #define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
<> 151:5eaa88a5bcc7 3424 #endif
<> 151:5eaa88a5bcc7 3425
mbed_official 114:fe4fe5cfc3a3 3426 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
mbed_official 114:fe4fe5cfc3a3 3427 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
mbed_official 114:fe4fe5cfc3a3 3428 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
mbed_official 114:fe4fe5cfc3a3 3429 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
mbed_official 114:fe4fe5cfc3a3 3430 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
mbed_official 114:fe4fe5cfc3a3 3431 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
mbed_official 114:fe4fe5cfc3a3 3432
mbed_official 114:fe4fe5cfc3a3 3433 /*!<****************** Bit definition for RCC_CIER register ********************/
<> 151:5eaa88a5bcc7 3434 #define RCC_CIER_LSIRDYIE_Pos (0U)
<> 151:5eaa88a5bcc7 3435 #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3436 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
<> 151:5eaa88a5bcc7 3437 #define RCC_CIER_LSERDYIE_Pos (1U)
<> 151:5eaa88a5bcc7 3438 #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3439 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
<> 151:5eaa88a5bcc7 3440 #define RCC_CIER_HSIRDYIE_Pos (2U)
<> 151:5eaa88a5bcc7 3441 #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3442 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
<> 151:5eaa88a5bcc7 3443 #define RCC_CIER_HSERDYIE_Pos (3U)
<> 151:5eaa88a5bcc7 3444 #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 3445 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
<> 151:5eaa88a5bcc7 3446 #define RCC_CIER_PLLRDYIE_Pos (4U)
<> 151:5eaa88a5bcc7 3447 #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 3448 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
<> 151:5eaa88a5bcc7 3449 #define RCC_CIER_MSIRDYIE_Pos (5U)
<> 151:5eaa88a5bcc7 3450 #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3451 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
<> 151:5eaa88a5bcc7 3452 #define RCC_CIER_CSSLSE_Pos (7U)
<> 151:5eaa88a5bcc7 3453 #define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 3454 #define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
mbed_official 114:fe4fe5cfc3a3 3455
mbed_official 114:fe4fe5cfc3a3 3456 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3457 #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
mbed_official 114:fe4fe5cfc3a3 3458
mbed_official 114:fe4fe5cfc3a3 3459 /*!<****************** Bit definition for RCC_CIFR register ********************/
<> 151:5eaa88a5bcc7 3460 #define RCC_CIFR_LSIRDYF_Pos (0U)
<> 151:5eaa88a5bcc7 3461 #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3462 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
<> 151:5eaa88a5bcc7 3463 #define RCC_CIFR_LSERDYF_Pos (1U)
<> 151:5eaa88a5bcc7 3464 #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3465 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
<> 151:5eaa88a5bcc7 3466 #define RCC_CIFR_HSIRDYF_Pos (2U)
<> 151:5eaa88a5bcc7 3467 #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3468 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
<> 151:5eaa88a5bcc7 3469 #define RCC_CIFR_HSERDYF_Pos (3U)
<> 151:5eaa88a5bcc7 3470 #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 3471 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
<> 151:5eaa88a5bcc7 3472 #define RCC_CIFR_PLLRDYF_Pos (4U)
<> 151:5eaa88a5bcc7 3473 #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 3474 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
<> 151:5eaa88a5bcc7 3475 #define RCC_CIFR_MSIRDYF_Pos (5U)
<> 151:5eaa88a5bcc7 3476 #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3477 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
<> 151:5eaa88a5bcc7 3478 #define RCC_CIFR_CSSLSEF_Pos (7U)
<> 151:5eaa88a5bcc7 3479 #define RCC_CIFR_CSSLSEF_Msk (0x1U << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 3480 #define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
<> 151:5eaa88a5bcc7 3481 #define RCC_CIFR_CSSHSEF_Pos (8U)
<> 151:5eaa88a5bcc7 3482 #define RCC_CIFR_CSSHSEF_Msk (0x1U << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3483 #define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
mbed_official 114:fe4fe5cfc3a3 3484
mbed_official 114:fe4fe5cfc3a3 3485 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3486 #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
mbed_official 114:fe4fe5cfc3a3 3487 #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
mbed_official 114:fe4fe5cfc3a3 3488
mbed_official 114:fe4fe5cfc3a3 3489 /*!<****************** Bit definition for RCC_CICR register ********************/
<> 151:5eaa88a5bcc7 3490 #define RCC_CICR_LSIRDYC_Pos (0U)
<> 151:5eaa88a5bcc7 3491 #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3492 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
<> 151:5eaa88a5bcc7 3493 #define RCC_CICR_LSERDYC_Pos (1U)
<> 151:5eaa88a5bcc7 3494 #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3495 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
<> 151:5eaa88a5bcc7 3496 #define RCC_CICR_HSIRDYC_Pos (2U)
<> 151:5eaa88a5bcc7 3497 #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3498 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
<> 151:5eaa88a5bcc7 3499 #define RCC_CICR_HSERDYC_Pos (3U)
<> 151:5eaa88a5bcc7 3500 #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 3501 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
<> 151:5eaa88a5bcc7 3502 #define RCC_CICR_PLLRDYC_Pos (4U)
<> 151:5eaa88a5bcc7 3503 #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 3504 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
<> 151:5eaa88a5bcc7 3505 #define RCC_CICR_MSIRDYC_Pos (5U)
<> 151:5eaa88a5bcc7 3506 #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3507 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
<> 151:5eaa88a5bcc7 3508 #define RCC_CICR_CSSLSEC_Pos (7U)
<> 151:5eaa88a5bcc7 3509 #define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 3510 #define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
<> 151:5eaa88a5bcc7 3511 #define RCC_CICR_CSSHSEC_Pos (8U)
<> 151:5eaa88a5bcc7 3512 #define RCC_CICR_CSSHSEC_Msk (0x1U << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3513 #define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
mbed_official 114:fe4fe5cfc3a3 3514
mbed_official 114:fe4fe5cfc3a3 3515 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3516 #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
mbed_official 114:fe4fe5cfc3a3 3517 #define RCC_CICR_CSSC RCC_CICR_CSSHSEC
mbed_official 114:fe4fe5cfc3a3 3518 /***************** Bit definition for RCC_IOPRSTR register ******************/
<> 151:5eaa88a5bcc7 3519 #define RCC_IOPRSTR_IOPARST_Pos (0U)
<> 151:5eaa88a5bcc7 3520 #define RCC_IOPRSTR_IOPARST_Msk (0x1U << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3521 #define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
<> 151:5eaa88a5bcc7 3522 #define RCC_IOPRSTR_IOPBRST_Pos (1U)
<> 151:5eaa88a5bcc7 3523 #define RCC_IOPRSTR_IOPBRST_Msk (0x1U << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3524 #define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
<> 151:5eaa88a5bcc7 3525 #define RCC_IOPRSTR_IOPCRST_Pos (2U)
<> 151:5eaa88a5bcc7 3526 #define RCC_IOPRSTR_IOPCRST_Msk (0x1U << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3527 #define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
<> 151:5eaa88a5bcc7 3528 #define RCC_IOPRSTR_IOPHRST_Pos (7U)
<> 151:5eaa88a5bcc7 3529 #define RCC_IOPRSTR_IOPHRST_Msk (0x1U << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 3530 #define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
mbed_official 114:fe4fe5cfc3a3 3531
mbed_official 114:fe4fe5cfc3a3 3532 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3533 #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
mbed_official 114:fe4fe5cfc3a3 3534 #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
mbed_official 114:fe4fe5cfc3a3 3535 #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
mbed_official 114:fe4fe5cfc3a3 3536 #define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
mbed_official 114:fe4fe5cfc3a3 3537
mbed_official 114:fe4fe5cfc3a3 3538
mbed_official 114:fe4fe5cfc3a3 3539 /****************** Bit definition for RCC_AHBRST register ******************/
<> 151:5eaa88a5bcc7 3540 #define RCC_AHBRSTR_DMARST_Pos (0U)
<> 151:5eaa88a5bcc7 3541 #define RCC_AHBRSTR_DMARST_Msk (0x1U << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3542 #define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
<> 151:5eaa88a5bcc7 3543 #define RCC_AHBRSTR_MIFRST_Pos (8U)
<> 151:5eaa88a5bcc7 3544 #define RCC_AHBRSTR_MIFRST_Msk (0x1U << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3545 #define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset reset */
<> 151:5eaa88a5bcc7 3546 #define RCC_AHBRSTR_CRCRST_Pos (12U)
<> 151:5eaa88a5bcc7 3547 #define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3548 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
mbed_official 114:fe4fe5cfc3a3 3549
mbed_official 114:fe4fe5cfc3a3 3550 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3551 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
mbed_official 114:fe4fe5cfc3a3 3552
mbed_official 114:fe4fe5cfc3a3 3553 /***************** Bit definition for RCC_APB2RSTR register *****************/
<> 151:5eaa88a5bcc7 3554 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
<> 151:5eaa88a5bcc7 3555 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3556 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */
<> 151:5eaa88a5bcc7 3557 #define RCC_APB2RSTR_TIM21RST_Pos (2U)
<> 151:5eaa88a5bcc7 3558 #define RCC_APB2RSTR_TIM21RST_Msk (0x1U << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3559 #define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 clock reset */
<> 151:5eaa88a5bcc7 3560 #define RCC_APB2RSTR_TIM22RST_Pos (5U)
<> 151:5eaa88a5bcc7 3561 #define RCC_APB2RSTR_TIM22RST_Msk (0x1U << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3562 #define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 clock reset */
<> 151:5eaa88a5bcc7 3563 #define RCC_APB2RSTR_ADCRST_Pos (9U)
<> 151:5eaa88a5bcc7 3564 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3565 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 clock reset */
<> 151:5eaa88a5bcc7 3566 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
<> 151:5eaa88a5bcc7 3567 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3568 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */
<> 151:5eaa88a5bcc7 3569 #define RCC_APB2RSTR_DBGRST_Pos (22U)
<> 151:5eaa88a5bcc7 3570 #define RCC_APB2RSTR_DBGRST_Msk (0x1U << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 3571 #define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU clock reset */
mbed_official 114:fe4fe5cfc3a3 3572
mbed_official 114:fe4fe5cfc3a3 3573 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3574 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */
mbed_official 114:fe4fe5cfc3a3 3575 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */
mbed_official 114:fe4fe5cfc3a3 3576
mbed_official 114:fe4fe5cfc3a3 3577 /***************** Bit definition for RCC_APB1RSTR register *****************/
<> 151:5eaa88a5bcc7 3578 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
<> 151:5eaa88a5bcc7 3579 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3580 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */
<> 151:5eaa88a5bcc7 3581 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
<> 151:5eaa88a5bcc7 3582 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 3583 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */
<> 151:5eaa88a5bcc7 3584 #define RCC_APB1RSTR_USART2RST_Pos (17U)
<> 151:5eaa88a5bcc7 3585 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 3586 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */
<> 151:5eaa88a5bcc7 3587 #define RCC_APB1RSTR_LPUART1RST_Pos (18U)
<> 151:5eaa88a5bcc7 3588 #define RCC_APB1RSTR_LPUART1RST_Msk (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 3589 #define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 clock reset */
<> 151:5eaa88a5bcc7 3590 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
<> 151:5eaa88a5bcc7 3591 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 3592 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */
<> 151:5eaa88a5bcc7 3593 #define RCC_APB1RSTR_PWRRST_Pos (28U)
<> 151:5eaa88a5bcc7 3594 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 3595 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */
<> 151:5eaa88a5bcc7 3596 #define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
<> 151:5eaa88a5bcc7 3597 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 3598 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 clock reset */
mbed_official 114:fe4fe5cfc3a3 3599
mbed_official 114:fe4fe5cfc3a3 3600 /***************** Bit definition for RCC_IOPENR register ******************/
<> 151:5eaa88a5bcc7 3601 #define RCC_IOPENR_IOPAEN_Pos (0U)
<> 151:5eaa88a5bcc7 3602 #define RCC_IOPENR_IOPAEN_Msk (0x1U << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3603 #define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
<> 151:5eaa88a5bcc7 3604 #define RCC_IOPENR_IOPBEN_Pos (1U)
<> 151:5eaa88a5bcc7 3605 #define RCC_IOPENR_IOPBEN_Msk (0x1U << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3606 #define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
<> 151:5eaa88a5bcc7 3607 #define RCC_IOPENR_IOPCEN_Pos (2U)
<> 151:5eaa88a5bcc7 3608 #define RCC_IOPENR_IOPCEN_Msk (0x1U << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3609 #define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
<> 151:5eaa88a5bcc7 3610 #define RCC_IOPENR_IOPHEN_Pos (7U)
<> 151:5eaa88a5bcc7 3611 #define RCC_IOPENR_IOPHEN_Msk (0x1U << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 3612 #define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
mbed_official 114:fe4fe5cfc3a3 3613
mbed_official 114:fe4fe5cfc3a3 3614 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3615 #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
mbed_official 114:fe4fe5cfc3a3 3616 #define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
mbed_official 114:fe4fe5cfc3a3 3617 #define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
mbed_official 114:fe4fe5cfc3a3 3618 #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
mbed_official 114:fe4fe5cfc3a3 3619
mbed_official 114:fe4fe5cfc3a3 3620 /***************** Bit definition for RCC_AHBENR register ******************/
<> 151:5eaa88a5bcc7 3621 #define RCC_AHBENR_DMAEN_Pos (0U)
<> 151:5eaa88a5bcc7 3622 #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3623 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
<> 151:5eaa88a5bcc7 3624 #define RCC_AHBENR_MIFEN_Pos (8U)
<> 151:5eaa88a5bcc7 3625 #define RCC_AHBENR_MIFEN_Msk (0x1U << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3626 #define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
<> 151:5eaa88a5bcc7 3627 #define RCC_AHBENR_CRCEN_Pos (12U)
<> 151:5eaa88a5bcc7 3628 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3629 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
mbed_official 114:fe4fe5cfc3a3 3630
mbed_official 114:fe4fe5cfc3a3 3631 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3632 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
mbed_official 114:fe4fe5cfc3a3 3633
mbed_official 114:fe4fe5cfc3a3 3634 /***************** Bit definition for RCC_APB2ENR register ******************/
<> 151:5eaa88a5bcc7 3635 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
<> 151:5eaa88a5bcc7 3636 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3637 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
<> 151:5eaa88a5bcc7 3638 #define RCC_APB2ENR_TIM21EN_Pos (2U)
<> 151:5eaa88a5bcc7 3639 #define RCC_APB2ENR_TIM21EN_Msk (0x1U << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3640 #define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
<> 151:5eaa88a5bcc7 3641 #define RCC_APB2ENR_TIM22EN_Pos (5U)
<> 151:5eaa88a5bcc7 3642 #define RCC_APB2ENR_TIM22EN_Msk (0x1U << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3643 #define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
<> 151:5eaa88a5bcc7 3644 #define RCC_APB2ENR_FWEN_Pos (7U)
<> 151:5eaa88a5bcc7 3645 #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 3646 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
<> 151:5eaa88a5bcc7 3647 #define RCC_APB2ENR_ADCEN_Pos (9U)
<> 151:5eaa88a5bcc7 3648 #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3649 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
<> 151:5eaa88a5bcc7 3650 #define RCC_APB2ENR_SPI1EN_Pos (12U)
<> 151:5eaa88a5bcc7 3651 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3652 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
<> 151:5eaa88a5bcc7 3653 #define RCC_APB2ENR_DBGEN_Pos (22U)
<> 151:5eaa88a5bcc7 3654 #define RCC_APB2ENR_DBGEN_Msk (0x1U << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 3655 #define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
mbed_official 114:fe4fe5cfc3a3 3656
mbed_official 114:fe4fe5cfc3a3 3657 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3658
mbed_official 114:fe4fe5cfc3a3 3659 #define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
mbed_official 114:fe4fe5cfc3a3 3660 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
mbed_official 114:fe4fe5cfc3a3 3661 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
mbed_official 114:fe4fe5cfc3a3 3662
mbed_official 114:fe4fe5cfc3a3 3663 /***************** Bit definition for RCC_APB1ENR register ******************/
<> 151:5eaa88a5bcc7 3664 #define RCC_APB1ENR_TIM2EN_Pos (0U)
<> 151:5eaa88a5bcc7 3665 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3666 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
<> 151:5eaa88a5bcc7 3667 #define RCC_APB1ENR_WWDGEN_Pos (11U)
<> 151:5eaa88a5bcc7 3668 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 3669 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
<> 151:5eaa88a5bcc7 3670 #define RCC_APB1ENR_USART2EN_Pos (17U)
<> 151:5eaa88a5bcc7 3671 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 3672 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
<> 151:5eaa88a5bcc7 3673 #define RCC_APB1ENR_LPUART1EN_Pos (18U)
<> 151:5eaa88a5bcc7 3674 #define RCC_APB1ENR_LPUART1EN_Msk (0x1U << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 3675 #define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
<> 151:5eaa88a5bcc7 3676 #define RCC_APB1ENR_I2C1EN_Pos (21U)
<> 151:5eaa88a5bcc7 3677 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 3678 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
<> 151:5eaa88a5bcc7 3679 #define RCC_APB1ENR_PWREN_Pos (28U)
<> 151:5eaa88a5bcc7 3680 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 3681 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
<> 151:5eaa88a5bcc7 3682 #define RCC_APB1ENR_LPTIM1EN_Pos (31U)
<> 151:5eaa88a5bcc7 3683 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 3684 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
mbed_official 114:fe4fe5cfc3a3 3685
mbed_official 114:fe4fe5cfc3a3 3686 /****************** Bit definition for RCC_IOPSMENR register ****************/
<> 151:5eaa88a5bcc7 3687 #define RCC_IOPSMENR_IOPASMEN_Pos (0U)
<> 151:5eaa88a5bcc7 3688 #define RCC_IOPSMENR_IOPASMEN_Msk (0x1U << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3689 #define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3690 #define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
<> 151:5eaa88a5bcc7 3691 #define RCC_IOPSMENR_IOPBSMEN_Msk (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3692 #define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3693 #define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
<> 151:5eaa88a5bcc7 3694 #define RCC_IOPSMENR_IOPCSMEN_Msk (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3695 #define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3696 #define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
<> 151:5eaa88a5bcc7 3697 #define RCC_IOPSMENR_IOPHSMEN_Msk (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 3698 #define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3699
mbed_official 114:fe4fe5cfc3a3 3700 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3701 #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3702 #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3703 #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3704 #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3705
mbed_official 114:fe4fe5cfc3a3 3706 /***************** Bit definition for RCC_AHBSMENR register ******************/
<> 151:5eaa88a5bcc7 3707 #define RCC_AHBSMENR_DMASMEN_Pos (0U)
<> 151:5eaa88a5bcc7 3708 #define RCC_AHBSMENR_DMASMEN_Msk (0x1U << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3709 #define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3710 #define RCC_AHBSMENR_MIFSMEN_Pos (8U)
<> 151:5eaa88a5bcc7 3711 #define RCC_AHBSMENR_MIFSMEN_Msk (0x1U << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3712 #define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
<> 151:5eaa88a5bcc7 3713 #define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
<> 151:5eaa88a5bcc7 3714 #define RCC_AHBSMENR_SRAMSMEN_Msk (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3715 #define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3716 #define RCC_AHBSMENR_CRCSMEN_Pos (12U)
<> 151:5eaa88a5bcc7 3717 #define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3718 #define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3719
mbed_official 114:fe4fe5cfc3a3 3720 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3721 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3722
mbed_official 114:fe4fe5cfc3a3 3723 /***************** Bit definition for RCC_APB2SMENR register ******************/
<> 151:5eaa88a5bcc7 3724 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
<> 151:5eaa88a5bcc7 3725 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3726 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3727 #define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
<> 151:5eaa88a5bcc7 3728 #define RCC_APB2SMENR_TIM21SMEN_Msk (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3729 #define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3730 #define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
<> 151:5eaa88a5bcc7 3731 #define RCC_APB2SMENR_TIM22SMEN_Msk (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3732 #define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3733 #define RCC_APB2SMENR_ADCSMEN_Pos (9U)
<> 151:5eaa88a5bcc7 3734 #define RCC_APB2SMENR_ADCSMEN_Msk (0x1U << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3735 #define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3736 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
<> 151:5eaa88a5bcc7 3737 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3738 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3739 #define RCC_APB2SMENR_DBGSMEN_Pos (22U)
<> 151:5eaa88a5bcc7 3740 #define RCC_APB2SMENR_DBGSMEN_Msk (0x1U << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 3741 #define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3742
mbed_official 114:fe4fe5cfc3a3 3743 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3744 #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3745 #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3746
mbed_official 114:fe4fe5cfc3a3 3747 /***************** Bit definition for RCC_APB1SMENR register ******************/
<> 151:5eaa88a5bcc7 3748 #define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
<> 151:5eaa88a5bcc7 3749 #define RCC_APB1SMENR_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3750 #define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3751 #define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
<> 151:5eaa88a5bcc7 3752 #define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 3753 #define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3754 #define RCC_APB1SMENR_USART2SMEN_Pos (17U)
<> 151:5eaa88a5bcc7 3755 #define RCC_APB1SMENR_USART2SMEN_Msk (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 3756 #define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3757 #define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
<> 151:5eaa88a5bcc7 3758 #define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 3759 #define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3760 #define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
<> 151:5eaa88a5bcc7 3761 #define RCC_APB1SMENR_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 3762 #define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3763 #define RCC_APB1SMENR_PWRSMEN_Pos (28U)
<> 151:5eaa88a5bcc7 3764 #define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 3765 #define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
<> 151:5eaa88a5bcc7 3766 #define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
<> 151:5eaa88a5bcc7 3767 #define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 3768 #define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
mbed_official 114:fe4fe5cfc3a3 3769
mbed_official 114:fe4fe5cfc3a3 3770 /*!< USART2 Clock source selection */
<> 151:5eaa88a5bcc7 3771 #define RCC_CCIPR_USART2SEL_Pos (2U)
<> 151:5eaa88a5bcc7 3772 #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
<> 151:5eaa88a5bcc7 3773 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
<> 151:5eaa88a5bcc7 3774 #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3775 #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
mbed_official 114:fe4fe5cfc3a3 3776
mbed_official 114:fe4fe5cfc3a3 3777 /*!< LPUART1 Clock source selection */
<> 151:5eaa88a5bcc7 3778 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
<> 151:5eaa88a5bcc7 3779 #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
<> 151:5eaa88a5bcc7 3780 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
<> 151:5eaa88a5bcc7 3781 #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
<> 151:5eaa88a5bcc7 3782 #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
mbed_official 114:fe4fe5cfc3a3 3783
mbed_official 114:fe4fe5cfc3a3 3784 /*!< I2C1 Clock source selection */
<> 151:5eaa88a5bcc7 3785 #define RCC_CCIPR_I2C1SEL_Pos (12U)
<> 151:5eaa88a5bcc7 3786 #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
<> 151:5eaa88a5bcc7 3787 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
<> 151:5eaa88a5bcc7 3788 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3789 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
mbed_official 114:fe4fe5cfc3a3 3790
mbed_official 114:fe4fe5cfc3a3 3791
mbed_official 114:fe4fe5cfc3a3 3792 /*!< LPTIM1 Clock source selection */
<> 151:5eaa88a5bcc7 3793 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
<> 151:5eaa88a5bcc7 3794 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
<> 151:5eaa88a5bcc7 3795 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
<> 151:5eaa88a5bcc7 3796 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 3797 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
mbed_official 114:fe4fe5cfc3a3 3798
mbed_official 114:fe4fe5cfc3a3 3799 /******************* Bit definition for RCC_CSR register *******************/
<> 151:5eaa88a5bcc7 3800 #define RCC_CSR_LSION_Pos (0U)
<> 151:5eaa88a5bcc7 3801 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3802 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
<> 151:5eaa88a5bcc7 3803 #define RCC_CSR_LSIRDY_Pos (1U)
<> 151:5eaa88a5bcc7 3804 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3805 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
<> 151:5eaa88a5bcc7 3806
<> 151:5eaa88a5bcc7 3807 #define RCC_CSR_LSEON_Pos (8U)
<> 151:5eaa88a5bcc7 3808 #define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3809 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
<> 151:5eaa88a5bcc7 3810 #define RCC_CSR_LSERDY_Pos (9U)
<> 151:5eaa88a5bcc7 3811 #define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3812 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
<> 151:5eaa88a5bcc7 3813 #define RCC_CSR_LSEBYP_Pos (10U)
<> 151:5eaa88a5bcc7 3814 #define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 3815 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
mbed_official 114:fe4fe5cfc3a3 3816
<> 151:5eaa88a5bcc7 3817 #define RCC_CSR_LSEDRV_Pos (11U)
<> 151:5eaa88a5bcc7 3818 #define RCC_CSR_LSEDRV_Msk (0x3U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
<> 151:5eaa88a5bcc7 3819 #define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
<> 151:5eaa88a5bcc7 3820 #define RCC_CSR_LSEDRV_0 (0x1U << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 3821 #define RCC_CSR_LSEDRV_1 (0x2U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
mbed_official 114:fe4fe5cfc3a3 3822
<> 151:5eaa88a5bcc7 3823 #define RCC_CSR_LSECSSON_Pos (13U)
<> 151:5eaa88a5bcc7 3824 #define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 3825 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
<> 151:5eaa88a5bcc7 3826 #define RCC_CSR_LSECSSD_Pos (14U)
<> 151:5eaa88a5bcc7 3827 #define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 3828 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
mbed_official 114:fe4fe5cfc3a3 3829
mbed_official 114:fe4fe5cfc3a3 3830 /*!< RTC congiguration */
<> 151:5eaa88a5bcc7 3831 #define RCC_CSR_RTCSEL_Pos (16U)
<> 151:5eaa88a5bcc7 3832 #define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
<> 151:5eaa88a5bcc7 3833 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
<> 151:5eaa88a5bcc7 3834 #define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 3835 #define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
mbed_official 114:fe4fe5cfc3a3 3836
<> 151:5eaa88a5bcc7 3837 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
<> 151:5eaa88a5bcc7 3838 #define RCC_CSR_RTCSEL_LSE_Pos (16U)
<> 151:5eaa88a5bcc7 3839 #define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 3840 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
<> 151:5eaa88a5bcc7 3841 #define RCC_CSR_RTCSEL_LSI_Pos (17U)
<> 151:5eaa88a5bcc7 3842 #define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 3843 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
<> 151:5eaa88a5bcc7 3844 #define RCC_CSR_RTCSEL_HSE_Pos (16U)
<> 151:5eaa88a5bcc7 3845 #define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
<> 151:5eaa88a5bcc7 3846 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
mbed_official 114:fe4fe5cfc3a3 3847
<> 151:5eaa88a5bcc7 3848 #define RCC_CSR_RTCEN_Pos (18U)
<> 151:5eaa88a5bcc7 3849 #define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 3850 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
<> 151:5eaa88a5bcc7 3851 #define RCC_CSR_RTCRST_Pos (19U)
<> 151:5eaa88a5bcc7 3852 #define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 3853 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
<> 151:5eaa88a5bcc7 3854
<> 151:5eaa88a5bcc7 3855 #define RCC_CSR_RMVF_Pos (23U)
<> 151:5eaa88a5bcc7 3856 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 3857 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
<> 151:5eaa88a5bcc7 3858 #define RCC_CSR_FWRSTF_Pos (24U)
<> 151:5eaa88a5bcc7 3859 #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 3860 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
<> 151:5eaa88a5bcc7 3861 #define RCC_CSR_OBLRSTF_Pos (25U)
<> 151:5eaa88a5bcc7 3862 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 3863 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
<> 151:5eaa88a5bcc7 3864 #define RCC_CSR_PINRSTF_Pos (26U)
<> 151:5eaa88a5bcc7 3865 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 3866 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
<> 151:5eaa88a5bcc7 3867 #define RCC_CSR_PORRSTF_Pos (27U)
<> 151:5eaa88a5bcc7 3868 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 3869 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
<> 151:5eaa88a5bcc7 3870 #define RCC_CSR_SFTRSTF_Pos (28U)
<> 151:5eaa88a5bcc7 3871 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 3872 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
<> 151:5eaa88a5bcc7 3873 #define RCC_CSR_IWDGRSTF_Pos (29U)
<> 151:5eaa88a5bcc7 3874 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 3875 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
<> 151:5eaa88a5bcc7 3876 #define RCC_CSR_WWDGRSTF_Pos (30U)
<> 151:5eaa88a5bcc7 3877 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 3878 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
<> 151:5eaa88a5bcc7 3879 #define RCC_CSR_LPWRRSTF_Pos (31U)
<> 151:5eaa88a5bcc7 3880 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 3881 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
mbed_official 114:fe4fe5cfc3a3 3882
mbed_official 114:fe4fe5cfc3a3 3883 /* Reference defines */
mbed_official 114:fe4fe5cfc3a3 3884 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
mbed_official 114:fe4fe5cfc3a3 3885
mbed_official 114:fe4fe5cfc3a3 3886
mbed_official 114:fe4fe5cfc3a3 3887 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 3888 /* */
mbed_official 114:fe4fe5cfc3a3 3889 /* Real-Time Clock (RTC) */
mbed_official 114:fe4fe5cfc3a3 3890 /* */
mbed_official 114:fe4fe5cfc3a3 3891 /******************************************************************************/
<> 151:5eaa88a5bcc7 3892 /*
<> 151:5eaa88a5bcc7 3893 * @brief Specific device feature definitions
<> 151:5eaa88a5bcc7 3894 */
<> 151:5eaa88a5bcc7 3895 #define RTC_TAMPER1_SUPPORT
<> 151:5eaa88a5bcc7 3896 #define RTC_TAMPER2_SUPPORT
<> 151:5eaa88a5bcc7 3897 #define RTC_TAMPER3_SUPPORT
<> 151:5eaa88a5bcc7 3898 #define RTC_WAKEUP_SUPPORT
<> 151:5eaa88a5bcc7 3899 #define RTC_BACKUP_SUPPORT
<> 151:5eaa88a5bcc7 3900
mbed_official 114:fe4fe5cfc3a3 3901 /******************** Bits definition for RTC_TR register *******************/
<> 151:5eaa88a5bcc7 3902 #define RTC_TR_PM_Pos (22U)
<> 151:5eaa88a5bcc7 3903 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 3904 #define RTC_TR_PM RTC_TR_PM_Msk /*!< */
<> 151:5eaa88a5bcc7 3905 #define RTC_TR_HT_Pos (20U)
<> 151:5eaa88a5bcc7 3906 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
<> 151:5eaa88a5bcc7 3907 #define RTC_TR_HT RTC_TR_HT_Msk /*!< */
<> 151:5eaa88a5bcc7 3908 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 3909 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 3910 #define RTC_TR_HU_Pos (16U)
<> 151:5eaa88a5bcc7 3911 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
<> 151:5eaa88a5bcc7 3912 #define RTC_TR_HU RTC_TR_HU_Msk /*!< */
<> 151:5eaa88a5bcc7 3913 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 3914 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 3915 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 3916 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 3917 #define RTC_TR_MNT_Pos (12U)
<> 151:5eaa88a5bcc7 3918 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
<> 151:5eaa88a5bcc7 3919 #define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
<> 151:5eaa88a5bcc7 3920 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3921 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 3922 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 3923 #define RTC_TR_MNU_Pos (8U)
<> 151:5eaa88a5bcc7 3924 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 3925 #define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
<> 151:5eaa88a5bcc7 3926 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3927 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3928 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 3929 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 3930 #define RTC_TR_ST_Pos (4U)
<> 151:5eaa88a5bcc7 3931 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
<> 151:5eaa88a5bcc7 3932 #define RTC_TR_ST RTC_TR_ST_Msk /*!< */
<> 151:5eaa88a5bcc7 3933 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 3934 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3935 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 3936 #define RTC_TR_SU_Pos (0U)
<> 151:5eaa88a5bcc7 3937 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 3938 #define RTC_TR_SU RTC_TR_SU_Msk /*!< */
<> 151:5eaa88a5bcc7 3939 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3940 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3941 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3942 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
mbed_official 114:fe4fe5cfc3a3 3943
mbed_official 114:fe4fe5cfc3a3 3944 /******************** Bits definition for RTC_DR register *******************/
<> 151:5eaa88a5bcc7 3945 #define RTC_DR_YT_Pos (20U)
<> 151:5eaa88a5bcc7 3946 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
<> 151:5eaa88a5bcc7 3947 #define RTC_DR_YT RTC_DR_YT_Msk /*!< */
<> 151:5eaa88a5bcc7 3948 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 3949 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 3950 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 3951 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 3952 #define RTC_DR_YU_Pos (16U)
<> 151:5eaa88a5bcc7 3953 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
<> 151:5eaa88a5bcc7 3954 #define RTC_DR_YU RTC_DR_YU_Msk /*!< */
<> 151:5eaa88a5bcc7 3955 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 3956 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 3957 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 3958 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 3959 #define RTC_DR_WDU_Pos (13U)
<> 151:5eaa88a5bcc7 3960 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
<> 151:5eaa88a5bcc7 3961 #define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
<> 151:5eaa88a5bcc7 3962 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 3963 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 3964 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 3965 #define RTC_DR_MT_Pos (12U)
<> 151:5eaa88a5bcc7 3966 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 3967 #define RTC_DR_MT RTC_DR_MT_Msk /*!< */
<> 151:5eaa88a5bcc7 3968 #define RTC_DR_MU_Pos (8U)
<> 151:5eaa88a5bcc7 3969 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 3970 #define RTC_DR_MU RTC_DR_MU_Msk /*!< */
<> 151:5eaa88a5bcc7 3971 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 3972 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 3973 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 3974 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 3975 #define RTC_DR_DT_Pos (4U)
<> 151:5eaa88a5bcc7 3976 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
<> 151:5eaa88a5bcc7 3977 #define RTC_DR_DT RTC_DR_DT_Msk /*!< */
<> 151:5eaa88a5bcc7 3978 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 3979 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 3980 #define RTC_DR_DU_Pos (0U)
<> 151:5eaa88a5bcc7 3981 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 3982 #define RTC_DR_DU RTC_DR_DU_Msk /*!< */
<> 151:5eaa88a5bcc7 3983 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 3984 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 3985 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 3986 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
mbed_official 114:fe4fe5cfc3a3 3987
mbed_official 114:fe4fe5cfc3a3 3988 /******************** Bits definition for RTC_CR register *******************/
<> 151:5eaa88a5bcc7 3989 #define RTC_CR_COE_Pos (23U)
<> 151:5eaa88a5bcc7 3990 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 3991 #define RTC_CR_COE RTC_CR_COE_Msk /*!< */
<> 151:5eaa88a5bcc7 3992 #define RTC_CR_OSEL_Pos (21U)
<> 151:5eaa88a5bcc7 3993 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
<> 151:5eaa88a5bcc7 3994 #define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
<> 151:5eaa88a5bcc7 3995 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 3996 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 3997 #define RTC_CR_POL_Pos (20U)
<> 151:5eaa88a5bcc7 3998 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 3999 #define RTC_CR_POL RTC_CR_POL_Msk /*!< */
<> 151:5eaa88a5bcc7 4000 #define RTC_CR_COSEL_Pos (19U)
<> 151:5eaa88a5bcc7 4001 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 4002 #define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
<> 151:5eaa88a5bcc7 4003 #define RTC_CR_BCK_Pos (18U)
<> 151:5eaa88a5bcc7 4004 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 4005 #define RTC_CR_BCK RTC_CR_BCK_Msk /*!< */
<> 151:5eaa88a5bcc7 4006 #define RTC_CR_SUB1H_Pos (17U)
<> 151:5eaa88a5bcc7 4007 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 4008 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
<> 151:5eaa88a5bcc7 4009 #define RTC_CR_ADD1H_Pos (16U)
<> 151:5eaa88a5bcc7 4010 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 4011 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
<> 151:5eaa88a5bcc7 4012 #define RTC_CR_TSIE_Pos (15U)
<> 151:5eaa88a5bcc7 4013 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 4014 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
<> 151:5eaa88a5bcc7 4015 #define RTC_CR_WUTIE_Pos (14U)
<> 151:5eaa88a5bcc7 4016 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 4017 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
<> 151:5eaa88a5bcc7 4018 #define RTC_CR_ALRBIE_Pos (13U)
<> 151:5eaa88a5bcc7 4019 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 4020 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
<> 151:5eaa88a5bcc7 4021 #define RTC_CR_ALRAIE_Pos (12U)
<> 151:5eaa88a5bcc7 4022 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 4023 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
<> 151:5eaa88a5bcc7 4024 #define RTC_CR_TSE_Pos (11U)
<> 151:5eaa88a5bcc7 4025 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 4026 #define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
<> 151:5eaa88a5bcc7 4027 #define RTC_CR_WUTE_Pos (10U)
<> 151:5eaa88a5bcc7 4028 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 4029 #define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
<> 151:5eaa88a5bcc7 4030 #define RTC_CR_ALRBE_Pos (9U)
<> 151:5eaa88a5bcc7 4031 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4032 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
<> 151:5eaa88a5bcc7 4033 #define RTC_CR_ALRAE_Pos (8U)
<> 151:5eaa88a5bcc7 4034 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4035 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
<> 151:5eaa88a5bcc7 4036 #define RTC_CR_FMT_Pos (6U)
<> 151:5eaa88a5bcc7 4037 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4038 #define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
<> 151:5eaa88a5bcc7 4039 #define RTC_CR_BYPSHAD_Pos (5U)
<> 151:5eaa88a5bcc7 4040 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4041 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
<> 151:5eaa88a5bcc7 4042 #define RTC_CR_REFCKON_Pos (4U)
<> 151:5eaa88a5bcc7 4043 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4044 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
<> 151:5eaa88a5bcc7 4045 #define RTC_CR_TSEDGE_Pos (3U)
<> 151:5eaa88a5bcc7 4046 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 4047 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
<> 151:5eaa88a5bcc7 4048 #define RTC_CR_WUCKSEL_Pos (0U)
<> 151:5eaa88a5bcc7 4049 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
<> 151:5eaa88a5bcc7 4050 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
<> 151:5eaa88a5bcc7 4051 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4052 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4053 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
mbed_official 114:fe4fe5cfc3a3 4054
mbed_official 114:fe4fe5cfc3a3 4055 /******************** Bits definition for RTC_ISR register ******************/
<> 151:5eaa88a5bcc7 4056 #define RTC_ISR_RECALPF_Pos (16U)
<> 151:5eaa88a5bcc7 4057 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 4058 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
<> 151:5eaa88a5bcc7 4059 #define RTC_ISR_TAMP3F_Pos (15U)
<> 151:5eaa88a5bcc7 4060 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 4061 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
<> 151:5eaa88a5bcc7 4062 #define RTC_ISR_TAMP2F_Pos (14U)
<> 151:5eaa88a5bcc7 4063 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 4064 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
<> 151:5eaa88a5bcc7 4065 #define RTC_ISR_TAMP1F_Pos (13U)
<> 151:5eaa88a5bcc7 4066 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 4067 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
<> 151:5eaa88a5bcc7 4068 #define RTC_ISR_TSOVF_Pos (12U)
<> 151:5eaa88a5bcc7 4069 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 4070 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
<> 151:5eaa88a5bcc7 4071 #define RTC_ISR_TSF_Pos (11U)
<> 151:5eaa88a5bcc7 4072 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 4073 #define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
<> 151:5eaa88a5bcc7 4074 #define RTC_ISR_WUTF_Pos (10U)
<> 151:5eaa88a5bcc7 4075 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 4076 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
<> 151:5eaa88a5bcc7 4077 #define RTC_ISR_ALRBF_Pos (9U)
<> 151:5eaa88a5bcc7 4078 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4079 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
<> 151:5eaa88a5bcc7 4080 #define RTC_ISR_ALRAF_Pos (8U)
<> 151:5eaa88a5bcc7 4081 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4082 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
<> 151:5eaa88a5bcc7 4083 #define RTC_ISR_INIT_Pos (7U)
<> 151:5eaa88a5bcc7 4084 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4085 #define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
<> 151:5eaa88a5bcc7 4086 #define RTC_ISR_INITF_Pos (6U)
<> 151:5eaa88a5bcc7 4087 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4088 #define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
<> 151:5eaa88a5bcc7 4089 #define RTC_ISR_RSF_Pos (5U)
<> 151:5eaa88a5bcc7 4090 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4091 #define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
<> 151:5eaa88a5bcc7 4092 #define RTC_ISR_INITS_Pos (4U)
<> 151:5eaa88a5bcc7 4093 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4094 #define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
<> 151:5eaa88a5bcc7 4095 #define RTC_ISR_SHPF_Pos (3U)
<> 151:5eaa88a5bcc7 4096 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 4097 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
<> 151:5eaa88a5bcc7 4098 #define RTC_ISR_WUTWF_Pos (2U)
<> 151:5eaa88a5bcc7 4099 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4100 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
<> 151:5eaa88a5bcc7 4101 #define RTC_ISR_ALRBWF_Pos (1U)
<> 151:5eaa88a5bcc7 4102 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4103 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
<> 151:5eaa88a5bcc7 4104 #define RTC_ISR_ALRAWF_Pos (0U)
<> 151:5eaa88a5bcc7 4105 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4106 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4107
mbed_official 114:fe4fe5cfc3a3 4108 /******************** Bits definition for RTC_PRER register *****************/
<> 151:5eaa88a5bcc7 4109 #define RTC_PRER_PREDIV_A_Pos (16U)
<> 151:5eaa88a5bcc7 4110 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
<> 151:5eaa88a5bcc7 4111 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
<> 151:5eaa88a5bcc7 4112 #define RTC_PRER_PREDIV_S_Pos (0U)
<> 151:5eaa88a5bcc7 4113 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
<> 151:5eaa88a5bcc7 4114 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4115
mbed_official 114:fe4fe5cfc3a3 4116 /******************** Bits definition for RTC_WUTR register *****************/
<> 151:5eaa88a5bcc7 4117 #define RTC_WUTR_WUT_Pos (0U)
<> 151:5eaa88a5bcc7 4118 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 4119 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
mbed_official 114:fe4fe5cfc3a3 4120
mbed_official 114:fe4fe5cfc3a3 4121 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 151:5eaa88a5bcc7 4122 #define RTC_ALRMAR_MSK4_Pos (31U)
<> 151:5eaa88a5bcc7 4123 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 4124 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
<> 151:5eaa88a5bcc7 4125 #define RTC_ALRMAR_WDSEL_Pos (30U)
<> 151:5eaa88a5bcc7 4126 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 4127 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
<> 151:5eaa88a5bcc7 4128 #define RTC_ALRMAR_DT_Pos (28U)
<> 151:5eaa88a5bcc7 4129 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
<> 151:5eaa88a5bcc7 4130 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
<> 151:5eaa88a5bcc7 4131 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 4132 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 4133 #define RTC_ALRMAR_DU_Pos (24U)
<> 151:5eaa88a5bcc7 4134 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
<> 151:5eaa88a5bcc7 4135 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
<> 151:5eaa88a5bcc7 4136 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 4137 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 4138 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 4139 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 4140 #define RTC_ALRMAR_MSK3_Pos (23U)
<> 151:5eaa88a5bcc7 4141 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 4142 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
<> 151:5eaa88a5bcc7 4143 #define RTC_ALRMAR_PM_Pos (22U)
<> 151:5eaa88a5bcc7 4144 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 4145 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
<> 151:5eaa88a5bcc7 4146 #define RTC_ALRMAR_HT_Pos (20U)
<> 151:5eaa88a5bcc7 4147 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
<> 151:5eaa88a5bcc7 4148 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
<> 151:5eaa88a5bcc7 4149 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 4150 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 4151 #define RTC_ALRMAR_HU_Pos (16U)
<> 151:5eaa88a5bcc7 4152 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
<> 151:5eaa88a5bcc7 4153 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
<> 151:5eaa88a5bcc7 4154 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 4155 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 4156 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 4157 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 4158 #define RTC_ALRMAR_MSK2_Pos (15U)
<> 151:5eaa88a5bcc7 4159 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 4160 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
<> 151:5eaa88a5bcc7 4161 #define RTC_ALRMAR_MNT_Pos (12U)
<> 151:5eaa88a5bcc7 4162 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
<> 151:5eaa88a5bcc7 4163 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
<> 151:5eaa88a5bcc7 4164 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 4165 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 4166 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 4167 #define RTC_ALRMAR_MNU_Pos (8U)
<> 151:5eaa88a5bcc7 4168 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 4169 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
<> 151:5eaa88a5bcc7 4170 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4171 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4172 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 4173 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 4174 #define RTC_ALRMAR_MSK1_Pos (7U)
<> 151:5eaa88a5bcc7 4175 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4176 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
<> 151:5eaa88a5bcc7 4177 #define RTC_ALRMAR_ST_Pos (4U)
<> 151:5eaa88a5bcc7 4178 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
<> 151:5eaa88a5bcc7 4179 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
<> 151:5eaa88a5bcc7 4180 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4181 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4182 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4183 #define RTC_ALRMAR_SU_Pos (0U)
<> 151:5eaa88a5bcc7 4184 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 4185 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
<> 151:5eaa88a5bcc7 4186 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4187 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4188 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4189 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
mbed_official 114:fe4fe5cfc3a3 4190
mbed_official 114:fe4fe5cfc3a3 4191 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 151:5eaa88a5bcc7 4192 #define RTC_ALRMBR_MSK4_Pos (31U)
<> 151:5eaa88a5bcc7 4193 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 4194 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
<> 151:5eaa88a5bcc7 4195 #define RTC_ALRMBR_WDSEL_Pos (30U)
<> 151:5eaa88a5bcc7 4196 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 4197 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
<> 151:5eaa88a5bcc7 4198 #define RTC_ALRMBR_DT_Pos (28U)
<> 151:5eaa88a5bcc7 4199 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
<> 151:5eaa88a5bcc7 4200 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
<> 151:5eaa88a5bcc7 4201 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 4202 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
<> 151:5eaa88a5bcc7 4203 #define RTC_ALRMBR_DU_Pos (24U)
<> 151:5eaa88a5bcc7 4204 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
<> 151:5eaa88a5bcc7 4205 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
<> 151:5eaa88a5bcc7 4206 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 4207 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 4208 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 4209 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 4210 #define RTC_ALRMBR_MSK3_Pos (23U)
<> 151:5eaa88a5bcc7 4211 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 4212 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
<> 151:5eaa88a5bcc7 4213 #define RTC_ALRMBR_PM_Pos (22U)
<> 151:5eaa88a5bcc7 4214 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 4215 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
<> 151:5eaa88a5bcc7 4216 #define RTC_ALRMBR_HT_Pos (20U)
<> 151:5eaa88a5bcc7 4217 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
<> 151:5eaa88a5bcc7 4218 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
<> 151:5eaa88a5bcc7 4219 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 4220 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 4221 #define RTC_ALRMBR_HU_Pos (16U)
<> 151:5eaa88a5bcc7 4222 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
<> 151:5eaa88a5bcc7 4223 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
<> 151:5eaa88a5bcc7 4224 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 4225 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 4226 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 4227 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 4228 #define RTC_ALRMBR_MSK2_Pos (15U)
<> 151:5eaa88a5bcc7 4229 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 4230 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
<> 151:5eaa88a5bcc7 4231 #define RTC_ALRMBR_MNT_Pos (12U)
<> 151:5eaa88a5bcc7 4232 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
<> 151:5eaa88a5bcc7 4233 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
<> 151:5eaa88a5bcc7 4234 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 4235 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 4236 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 4237 #define RTC_ALRMBR_MNU_Pos (8U)
<> 151:5eaa88a5bcc7 4238 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 4239 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
<> 151:5eaa88a5bcc7 4240 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4241 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4242 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 4243 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 4244 #define RTC_ALRMBR_MSK1_Pos (7U)
<> 151:5eaa88a5bcc7 4245 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4246 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
<> 151:5eaa88a5bcc7 4247 #define RTC_ALRMBR_ST_Pos (4U)
<> 151:5eaa88a5bcc7 4248 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
<> 151:5eaa88a5bcc7 4249 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
<> 151:5eaa88a5bcc7 4250 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4251 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4252 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4253 #define RTC_ALRMBR_SU_Pos (0U)
<> 151:5eaa88a5bcc7 4254 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 4255 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
<> 151:5eaa88a5bcc7 4256 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4257 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4258 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4259 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
mbed_official 114:fe4fe5cfc3a3 4260
mbed_official 114:fe4fe5cfc3a3 4261 /******************** Bits definition for RTC_WPR register ******************/
<> 151:5eaa88a5bcc7 4262 #define RTC_WPR_KEY_Pos (0U)
<> 151:5eaa88a5bcc7 4263 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
<> 151:5eaa88a5bcc7 4264 #define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4265
mbed_official 114:fe4fe5cfc3a3 4266 /******************** Bits definition for RTC_SSR register ******************/
<> 151:5eaa88a5bcc7 4267 #define RTC_SSR_SS_Pos (0U)
<> 151:5eaa88a5bcc7 4268 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 4269 #define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4270
mbed_official 114:fe4fe5cfc3a3 4271 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 151:5eaa88a5bcc7 4272 #define RTC_SHIFTR_SUBFS_Pos (0U)
<> 151:5eaa88a5bcc7 4273 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
<> 151:5eaa88a5bcc7 4274 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
<> 151:5eaa88a5bcc7 4275 #define RTC_SHIFTR_ADD1S_Pos (31U)
<> 151:5eaa88a5bcc7 4276 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 4277 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4278
mbed_official 114:fe4fe5cfc3a3 4279 /******************** Bits definition for RTC_TSTR register *****************/
<> 151:5eaa88a5bcc7 4280 #define RTC_TSTR_PM_Pos (22U)
<> 151:5eaa88a5bcc7 4281 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 4282 #define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
<> 151:5eaa88a5bcc7 4283 #define RTC_TSTR_HT_Pos (20U)
<> 151:5eaa88a5bcc7 4284 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
<> 151:5eaa88a5bcc7 4285 #define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
<> 151:5eaa88a5bcc7 4286 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 4287 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 4288 #define RTC_TSTR_HU_Pos (16U)
<> 151:5eaa88a5bcc7 4289 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
<> 151:5eaa88a5bcc7 4290 #define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
<> 151:5eaa88a5bcc7 4291 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 4292 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 4293 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 4294 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 4295 #define RTC_TSTR_MNT_Pos (12U)
<> 151:5eaa88a5bcc7 4296 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
<> 151:5eaa88a5bcc7 4297 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
<> 151:5eaa88a5bcc7 4298 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 4299 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 4300 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 4301 #define RTC_TSTR_MNU_Pos (8U)
<> 151:5eaa88a5bcc7 4302 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 4303 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
<> 151:5eaa88a5bcc7 4304 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4305 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4306 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 4307 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 4308 #define RTC_TSTR_ST_Pos (4U)
<> 151:5eaa88a5bcc7 4309 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
<> 151:5eaa88a5bcc7 4310 #define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
<> 151:5eaa88a5bcc7 4311 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4312 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4313 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4314 #define RTC_TSTR_SU_Pos (0U)
<> 151:5eaa88a5bcc7 4315 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 4316 #define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
<> 151:5eaa88a5bcc7 4317 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4318 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4319 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4320 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
mbed_official 114:fe4fe5cfc3a3 4321
mbed_official 114:fe4fe5cfc3a3 4322 /******************** Bits definition for RTC_TSDR register *****************/
<> 151:5eaa88a5bcc7 4323 #define RTC_TSDR_WDU_Pos (13U)
<> 151:5eaa88a5bcc7 4324 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
<> 151:5eaa88a5bcc7 4325 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
<> 151:5eaa88a5bcc7 4326 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 4327 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 4328 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 4329 #define RTC_TSDR_MT_Pos (12U)
<> 151:5eaa88a5bcc7 4330 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 4331 #define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
<> 151:5eaa88a5bcc7 4332 #define RTC_TSDR_MU_Pos (8U)
<> 151:5eaa88a5bcc7 4333 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 4334 #define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
<> 151:5eaa88a5bcc7 4335 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4336 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4337 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 4338 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 4339 #define RTC_TSDR_DT_Pos (4U)
<> 151:5eaa88a5bcc7 4340 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
<> 151:5eaa88a5bcc7 4341 #define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
<> 151:5eaa88a5bcc7 4342 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4343 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4344 #define RTC_TSDR_DU_Pos (0U)
<> 151:5eaa88a5bcc7 4345 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 4346 #define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
<> 151:5eaa88a5bcc7 4347 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4348 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4349 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4350 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
mbed_official 114:fe4fe5cfc3a3 4351
mbed_official 114:fe4fe5cfc3a3 4352 /******************** Bits definition for RTC_TSSSR register ****************/
<> 151:5eaa88a5bcc7 4353 #define RTC_TSSSR_SS_Pos (0U)
<> 151:5eaa88a5bcc7 4354 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 4355 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
mbed_official 114:fe4fe5cfc3a3 4356
mbed_official 114:fe4fe5cfc3a3 4357 /******************** Bits definition for RTC_CALR register *****************/
<> 151:5eaa88a5bcc7 4358 #define RTC_CALR_CALP_Pos (15U)
<> 151:5eaa88a5bcc7 4359 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 4360 #define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
<> 151:5eaa88a5bcc7 4361 #define RTC_CALR_CALW8_Pos (14U)
<> 151:5eaa88a5bcc7 4362 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 4363 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
<> 151:5eaa88a5bcc7 4364 #define RTC_CALR_CALW16_Pos (13U)
<> 151:5eaa88a5bcc7 4365 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 4366 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
<> 151:5eaa88a5bcc7 4367 #define RTC_CALR_CALM_Pos (0U)
<> 151:5eaa88a5bcc7 4368 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
<> 151:5eaa88a5bcc7 4369 #define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
<> 151:5eaa88a5bcc7 4370 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4371 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4372 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4373 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 4374 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4375 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4376 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4377 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4378 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
mbed_official 114:fe4fe5cfc3a3 4379
mbed_official 114:fe4fe5cfc3a3 4380 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 4381 #define RTC_CAL_CALP RTC_CALR_CALP
mbed_official 114:fe4fe5cfc3a3 4382 #define RTC_CAL_CALW8 RTC_CALR_CALW8
mbed_official 114:fe4fe5cfc3a3 4383 #define RTC_CAL_CALW16 RTC_CALR_CALW16
mbed_official 114:fe4fe5cfc3a3 4384 #define RTC_CAL_CALM RTC_CALR_CALM
mbed_official 114:fe4fe5cfc3a3 4385 #define RTC_CAL_CALM_0 RTC_CALR_CALM_0
mbed_official 114:fe4fe5cfc3a3 4386 #define RTC_CAL_CALM_1 RTC_CALR_CALM_1
mbed_official 114:fe4fe5cfc3a3 4387 #define RTC_CAL_CALM_2 RTC_CALR_CALM_2
mbed_official 114:fe4fe5cfc3a3 4388 #define RTC_CAL_CALM_3 RTC_CALR_CALM_3
mbed_official 114:fe4fe5cfc3a3 4389 #define RTC_CAL_CALM_4 RTC_CALR_CALM_4
mbed_official 114:fe4fe5cfc3a3 4390 #define RTC_CAL_CALM_5 RTC_CALR_CALM_5
mbed_official 114:fe4fe5cfc3a3 4391 #define RTC_CAL_CALM_6 RTC_CALR_CALM_6
mbed_official 114:fe4fe5cfc3a3 4392 #define RTC_CAL_CALM_7 RTC_CALR_CALM_7
mbed_official 114:fe4fe5cfc3a3 4393 #define RTC_CAL_CALM_8 RTC_CALR_CALM_8
mbed_official 114:fe4fe5cfc3a3 4394
mbed_official 114:fe4fe5cfc3a3 4395 /******************** Bits definition for RTC_TAMPCR register ****************/
<> 151:5eaa88a5bcc7 4396 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
<> 151:5eaa88a5bcc7 4397 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 4398 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
<> 151:5eaa88a5bcc7 4399 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
<> 151:5eaa88a5bcc7 4400 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 4401 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
<> 151:5eaa88a5bcc7 4402 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
<> 151:5eaa88a5bcc7 4403 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 4404 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
<> 151:5eaa88a5bcc7 4405 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
<> 151:5eaa88a5bcc7 4406 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 4407 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
<> 151:5eaa88a5bcc7 4408 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
<> 151:5eaa88a5bcc7 4409 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 4410 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
<> 151:5eaa88a5bcc7 4411 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
<> 151:5eaa88a5bcc7 4412 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 4413 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
<> 151:5eaa88a5bcc7 4414 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
<> 151:5eaa88a5bcc7 4415 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 4416 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
<> 151:5eaa88a5bcc7 4417 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
<> 151:5eaa88a5bcc7 4418 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 4419 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
<> 151:5eaa88a5bcc7 4420 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
<> 151:5eaa88a5bcc7 4421 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 4422 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
<> 151:5eaa88a5bcc7 4423 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
<> 151:5eaa88a5bcc7 4424 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 4425 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
<> 151:5eaa88a5bcc7 4426 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
<> 151:5eaa88a5bcc7 4427 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
<> 151:5eaa88a5bcc7 4428 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
<> 151:5eaa88a5bcc7 4429 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 4430 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 4431 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
<> 151:5eaa88a5bcc7 4432 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
<> 151:5eaa88a5bcc7 4433 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
<> 151:5eaa88a5bcc7 4434 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 4435 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 4436 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
<> 151:5eaa88a5bcc7 4437 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
<> 151:5eaa88a5bcc7 4438 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
<> 151:5eaa88a5bcc7 4439 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4440 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4441 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 4442 #define RTC_TAMPCR_TAMPTS_Pos (7U)
<> 151:5eaa88a5bcc7 4443 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4444 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
<> 151:5eaa88a5bcc7 4445 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
<> 151:5eaa88a5bcc7 4446 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4447 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
<> 151:5eaa88a5bcc7 4448 #define RTC_TAMPCR_TAMP3E_Pos (5U)
<> 151:5eaa88a5bcc7 4449 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4450 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
<> 151:5eaa88a5bcc7 4451 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
<> 151:5eaa88a5bcc7 4452 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4453 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
<> 151:5eaa88a5bcc7 4454 #define RTC_TAMPCR_TAMP2E_Pos (3U)
<> 151:5eaa88a5bcc7 4455 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 4456 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
<> 151:5eaa88a5bcc7 4457 #define RTC_TAMPCR_TAMPIE_Pos (2U)
<> 151:5eaa88a5bcc7 4458 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4459 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
<> 151:5eaa88a5bcc7 4460 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
<> 151:5eaa88a5bcc7 4461 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4462 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
<> 151:5eaa88a5bcc7 4463 #define RTC_TAMPCR_TAMP1E_Pos (0U)
<> 151:5eaa88a5bcc7 4464 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4465 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4466
mbed_official 114:fe4fe5cfc3a3 4467 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 151:5eaa88a5bcc7 4468 #define RTC_ALRMASSR_MASKSS_Pos (24U)
<> 151:5eaa88a5bcc7 4469 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 151:5eaa88a5bcc7 4470 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
<> 151:5eaa88a5bcc7 4471 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 4472 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 4473 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 4474 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 4475 #define RTC_ALRMASSR_SS_Pos (0U)
<> 151:5eaa88a5bcc7 4476 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
<> 151:5eaa88a5bcc7 4477 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
mbed_official 114:fe4fe5cfc3a3 4478
mbed_official 114:fe4fe5cfc3a3 4479 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 151:5eaa88a5bcc7 4480 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
<> 151:5eaa88a5bcc7 4481 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 151:5eaa88a5bcc7 4482 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
<> 151:5eaa88a5bcc7 4483 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 4484 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 4485 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 4486 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 4487 #define RTC_ALRMBSSR_SS_Pos (0U)
<> 151:5eaa88a5bcc7 4488 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
<> 151:5eaa88a5bcc7 4489 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
mbed_official 114:fe4fe5cfc3a3 4490
mbed_official 114:fe4fe5cfc3a3 4491 /******************** Bits definition for RTC_OR register ****************/
<> 151:5eaa88a5bcc7 4492 #define RTC_OR_OUT_RMP_Pos (1U)
<> 151:5eaa88a5bcc7 4493 #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4494 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
<> 151:5eaa88a5bcc7 4495 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
<> 151:5eaa88a5bcc7 4496 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4497 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4498
mbed_official 114:fe4fe5cfc3a3 4499 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 4500 #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
mbed_official 114:fe4fe5cfc3a3 4501
mbed_official 114:fe4fe5cfc3a3 4502 /******************** Bits definition for RTC_BKP0R register ****************/
<> 151:5eaa88a5bcc7 4503 #define RTC_BKP0R_Pos (0U)
<> 151:5eaa88a5bcc7 4504 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 4505 #define RTC_BKP0R RTC_BKP0R_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4506
mbed_official 114:fe4fe5cfc3a3 4507 /******************** Bits definition for RTC_BKP1R register ****************/
<> 151:5eaa88a5bcc7 4508 #define RTC_BKP1R_Pos (0U)
<> 151:5eaa88a5bcc7 4509 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 4510 #define RTC_BKP1R RTC_BKP1R_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4511
mbed_official 114:fe4fe5cfc3a3 4512 /******************** Bits definition for RTC_BKP2R register ****************/
<> 151:5eaa88a5bcc7 4513 #define RTC_BKP2R_Pos (0U)
<> 151:5eaa88a5bcc7 4514 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 4515 #define RTC_BKP2R RTC_BKP2R_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4516
mbed_official 114:fe4fe5cfc3a3 4517 /******************** Bits definition for RTC_BKP3R register ****************/
<> 151:5eaa88a5bcc7 4518 #define RTC_BKP3R_Pos (0U)
<> 151:5eaa88a5bcc7 4519 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 4520 #define RTC_BKP3R RTC_BKP3R_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4521
mbed_official 114:fe4fe5cfc3a3 4522 /******************** Bits definition for RTC_BKP4R register ****************/
<> 151:5eaa88a5bcc7 4523 #define RTC_BKP4R_Pos (0U)
<> 151:5eaa88a5bcc7 4524 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
<> 151:5eaa88a5bcc7 4525 #define RTC_BKP4R RTC_BKP4R_Msk /*!< */
mbed_official 114:fe4fe5cfc3a3 4526
mbed_official 114:fe4fe5cfc3a3 4527 /******************** Number of backup registers ******************************/
<> 151:5eaa88a5bcc7 4528 #define RTC_BKP_NUMBER (0x00000005U) /*!< */
mbed_official 114:fe4fe5cfc3a3 4529
mbed_official 114:fe4fe5cfc3a3 4530 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 4531 /* */
mbed_official 114:fe4fe5cfc3a3 4532 /* Serial Peripheral Interface (SPI) */
mbed_official 114:fe4fe5cfc3a3 4533 /* */
mbed_official 114:fe4fe5cfc3a3 4534 /******************************************************************************/
<> 151:5eaa88a5bcc7 4535
<> 151:5eaa88a5bcc7 4536 /*
<> 151:5eaa88a5bcc7 4537 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
<> 151:5eaa88a5bcc7 4538 */
<> 151:5eaa88a5bcc7 4539 /* Note: No specific macro feature on this device */
<> 151:5eaa88a5bcc7 4540
mbed_official 114:fe4fe5cfc3a3 4541 /******************* Bit definition for SPI_CR1 register ********************/
<> 151:5eaa88a5bcc7 4542 #define SPI_CR1_CPHA_Pos (0U)
<> 151:5eaa88a5bcc7 4543 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4544 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
<> 151:5eaa88a5bcc7 4545 #define SPI_CR1_CPOL_Pos (1U)
<> 151:5eaa88a5bcc7 4546 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4547 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
<> 151:5eaa88a5bcc7 4548 #define SPI_CR1_MSTR_Pos (2U)
<> 151:5eaa88a5bcc7 4549 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4550 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
<> 151:5eaa88a5bcc7 4551 #define SPI_CR1_BR_Pos (3U)
<> 151:5eaa88a5bcc7 4552 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
<> 151:5eaa88a5bcc7 4553 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
<> 151:5eaa88a5bcc7 4554 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 4555 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4556 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4557 #define SPI_CR1_SPE_Pos (6U)
<> 151:5eaa88a5bcc7 4558 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4559 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
<> 151:5eaa88a5bcc7 4560 #define SPI_CR1_LSBFIRST_Pos (7U)
<> 151:5eaa88a5bcc7 4561 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4562 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
<> 151:5eaa88a5bcc7 4563 #define SPI_CR1_SSI_Pos (8U)
<> 151:5eaa88a5bcc7 4564 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4565 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
<> 151:5eaa88a5bcc7 4566 #define SPI_CR1_SSM_Pos (9U)
<> 151:5eaa88a5bcc7 4567 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4568 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
<> 151:5eaa88a5bcc7 4569 #define SPI_CR1_RXONLY_Pos (10U)
<> 151:5eaa88a5bcc7 4570 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 4571 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
<> 151:5eaa88a5bcc7 4572 #define SPI_CR1_DFF_Pos (11U)
<> 151:5eaa88a5bcc7 4573 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 4574 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
<> 151:5eaa88a5bcc7 4575 #define SPI_CR1_CRCNEXT_Pos (12U)
<> 151:5eaa88a5bcc7 4576 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 4577 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
<> 151:5eaa88a5bcc7 4578 #define SPI_CR1_CRCEN_Pos (13U)
<> 151:5eaa88a5bcc7 4579 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 4580 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
<> 151:5eaa88a5bcc7 4581 #define SPI_CR1_BIDIOE_Pos (14U)
<> 151:5eaa88a5bcc7 4582 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 4583 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
<> 151:5eaa88a5bcc7 4584 #define SPI_CR1_BIDIMODE_Pos (15U)
<> 151:5eaa88a5bcc7 4585 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 4586 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
mbed_official 114:fe4fe5cfc3a3 4587
mbed_official 114:fe4fe5cfc3a3 4588 /******************* Bit definition for SPI_CR2 register ********************/
<> 151:5eaa88a5bcc7 4589 #define SPI_CR2_RXDMAEN_Pos (0U)
<> 151:5eaa88a5bcc7 4590 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4591 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
<> 151:5eaa88a5bcc7 4592 #define SPI_CR2_TXDMAEN_Pos (1U)
<> 151:5eaa88a5bcc7 4593 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4594 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
<> 151:5eaa88a5bcc7 4595 #define SPI_CR2_SSOE_Pos (2U)
<> 151:5eaa88a5bcc7 4596 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4597 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
<> 151:5eaa88a5bcc7 4598 #define SPI_CR2_FRF_Pos (4U)
<> 151:5eaa88a5bcc7 4599 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4600 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
<> 151:5eaa88a5bcc7 4601 #define SPI_CR2_ERRIE_Pos (5U)
<> 151:5eaa88a5bcc7 4602 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4603 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
<> 151:5eaa88a5bcc7 4604 #define SPI_CR2_RXNEIE_Pos (6U)
<> 151:5eaa88a5bcc7 4605 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4606 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
<> 151:5eaa88a5bcc7 4607 #define SPI_CR2_TXEIE_Pos (7U)
<> 151:5eaa88a5bcc7 4608 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4609 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
mbed_official 114:fe4fe5cfc3a3 4610
mbed_official 114:fe4fe5cfc3a3 4611 /******************** Bit definition for SPI_SR register ********************/
<> 151:5eaa88a5bcc7 4612 #define SPI_SR_RXNE_Pos (0U)
<> 151:5eaa88a5bcc7 4613 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4614 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
<> 151:5eaa88a5bcc7 4615 #define SPI_SR_TXE_Pos (1U)
<> 151:5eaa88a5bcc7 4616 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4617 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
<> 151:5eaa88a5bcc7 4618 #define SPI_SR_CHSIDE_Pos (2U)
<> 151:5eaa88a5bcc7 4619 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4620 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
<> 151:5eaa88a5bcc7 4621 #define SPI_SR_UDR_Pos (3U)
<> 151:5eaa88a5bcc7 4622 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 4623 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
<> 151:5eaa88a5bcc7 4624 #define SPI_SR_CRCERR_Pos (4U)
<> 151:5eaa88a5bcc7 4625 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4626 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
<> 151:5eaa88a5bcc7 4627 #define SPI_SR_MODF_Pos (5U)
<> 151:5eaa88a5bcc7 4628 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4629 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
<> 151:5eaa88a5bcc7 4630 #define SPI_SR_OVR_Pos (6U)
<> 151:5eaa88a5bcc7 4631 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4632 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
<> 151:5eaa88a5bcc7 4633 #define SPI_SR_BSY_Pos (7U)
<> 151:5eaa88a5bcc7 4634 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4635 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
<> 151:5eaa88a5bcc7 4636 #define SPI_SR_FRE_Pos (8U)
<> 151:5eaa88a5bcc7 4637 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4638 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
mbed_official 114:fe4fe5cfc3a3 4639
mbed_official 114:fe4fe5cfc3a3 4640 /******************** Bit definition for SPI_DR register ********************/
<> 151:5eaa88a5bcc7 4641 #define SPI_DR_DR_Pos (0U)
<> 151:5eaa88a5bcc7 4642 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 4643 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
mbed_official 114:fe4fe5cfc3a3 4644
mbed_official 114:fe4fe5cfc3a3 4645 /******************* Bit definition for SPI_CRCPR register ******************/
<> 151:5eaa88a5bcc7 4646 #define SPI_CRCPR_CRCPOLY_Pos (0U)
<> 151:5eaa88a5bcc7 4647 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 4648 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
mbed_official 114:fe4fe5cfc3a3 4649
mbed_official 114:fe4fe5cfc3a3 4650 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 151:5eaa88a5bcc7 4651 #define SPI_RXCRCR_RXCRC_Pos (0U)
<> 151:5eaa88a5bcc7 4652 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 4653 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
mbed_official 114:fe4fe5cfc3a3 4654
mbed_official 114:fe4fe5cfc3a3 4655 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 151:5eaa88a5bcc7 4656 #define SPI_TXCRCR_TXCRC_Pos (0U)
<> 151:5eaa88a5bcc7 4657 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 4658 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
mbed_official 114:fe4fe5cfc3a3 4659
mbed_official 114:fe4fe5cfc3a3 4660 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 4661 /* */
mbed_official 114:fe4fe5cfc3a3 4662 /* System Configuration (SYSCFG) */
mbed_official 114:fe4fe5cfc3a3 4663 /* */
mbed_official 114:fe4fe5cfc3a3 4664 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 4665 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
<> 151:5eaa88a5bcc7 4666 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
<> 151:5eaa88a5bcc7 4667 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
<> 151:5eaa88a5bcc7 4668 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
<> 151:5eaa88a5bcc7 4669 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4670 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4671 #define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
<> 151:5eaa88a5bcc7 4672 #define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
<> 151:5eaa88a5bcc7 4673 #define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
<> 151:5eaa88a5bcc7 4674 #define SYSCFG_CFGR1_BOOT_MODE_0 (0x1U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4675 #define SYSCFG_CFGR1_BOOT_MODE_1 (0x2U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
mbed_official 114:fe4fe5cfc3a3 4676
mbed_official 114:fe4fe5cfc3a3 4677 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
<> 151:5eaa88a5bcc7 4678 #define SYSCFG_CFGR2_FWDISEN_Pos (0U)
<> 151:5eaa88a5bcc7 4679 #define SYSCFG_CFGR2_FWDISEN_Msk (0x1U << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4680 #define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
<> 151:5eaa88a5bcc7 4681 #define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
<> 151:5eaa88a5bcc7 4682 #define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4683 #define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
<> 151:5eaa88a5bcc7 4684 #define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
<> 151:5eaa88a5bcc7 4685 #define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4686 #define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
<> 151:5eaa88a5bcc7 4687 #define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
<> 151:5eaa88a5bcc7 4688 #define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 4689 #define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
<> 151:5eaa88a5bcc7 4690 #define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
<> 151:5eaa88a5bcc7 4691 #define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 4692 #define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
<> 151:5eaa88a5bcc7 4693 #define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
<> 151:5eaa88a5bcc7 4694 #define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 4695 #define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
mbed_official 114:fe4fe5cfc3a3 4696
mbed_official 114:fe4fe5cfc3a3 4697 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 151:5eaa88a5bcc7 4698 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
<> 151:5eaa88a5bcc7 4699 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 4700 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
<> 151:5eaa88a5bcc7 4701 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
<> 151:5eaa88a5bcc7 4702 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
<> 151:5eaa88a5bcc7 4703 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
<> 151:5eaa88a5bcc7 4704 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
<> 151:5eaa88a5bcc7 4705 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 4706 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
<> 151:5eaa88a5bcc7 4707 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
<> 151:5eaa88a5bcc7 4708 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
<> 151:5eaa88a5bcc7 4709 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
mbed_official 114:fe4fe5cfc3a3 4710
mbed_official 114:fe4fe5cfc3a3 4711 /**
mbed_official 114:fe4fe5cfc3a3 4712 * @brief EXTI0 configuration
mbed_official 114:fe4fe5cfc3a3 4713 */
<> 151:5eaa88a5bcc7 4714 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
<> 151:5eaa88a5bcc7 4715 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
<> 151:5eaa88a5bcc7 4716 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
<> 151:5eaa88a5bcc7 4717 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
mbed_official 114:fe4fe5cfc3a3 4718
mbed_official 114:fe4fe5cfc3a3 4719 /**
mbed_official 114:fe4fe5cfc3a3 4720 * @brief EXTI1 configuration
mbed_official 114:fe4fe5cfc3a3 4721 */
<> 151:5eaa88a5bcc7 4722 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
<> 151:5eaa88a5bcc7 4723 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
<> 151:5eaa88a5bcc7 4724 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
<> 151:5eaa88a5bcc7 4725 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
mbed_official 114:fe4fe5cfc3a3 4726
mbed_official 114:fe4fe5cfc3a3 4727 /**
mbed_official 114:fe4fe5cfc3a3 4728 * @brief EXTI2 configuration
mbed_official 114:fe4fe5cfc3a3 4729 */
<> 151:5eaa88a5bcc7 4730 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
<> 151:5eaa88a5bcc7 4731 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
<> 151:5eaa88a5bcc7 4732 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
<> 151:5eaa88a5bcc7 4733 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
mbed_official 114:fe4fe5cfc3a3 4734
mbed_official 114:fe4fe5cfc3a3 4735 /**
mbed_official 114:fe4fe5cfc3a3 4736 * @brief EXTI3 configuration
mbed_official 114:fe4fe5cfc3a3 4737 */
<> 151:5eaa88a5bcc7 4738 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
<> 151:5eaa88a5bcc7 4739 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
<> 151:5eaa88a5bcc7 4740 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
mbed_official 114:fe4fe5cfc3a3 4741
mbed_official 114:fe4fe5cfc3a3 4742 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
<> 151:5eaa88a5bcc7 4743 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
<> 151:5eaa88a5bcc7 4744 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 4745 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
<> 151:5eaa88a5bcc7 4746 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
<> 151:5eaa88a5bcc7 4747 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
<> 151:5eaa88a5bcc7 4748 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
<> 151:5eaa88a5bcc7 4749 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
<> 151:5eaa88a5bcc7 4750 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 4751 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
<> 151:5eaa88a5bcc7 4752 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
<> 151:5eaa88a5bcc7 4753 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
<> 151:5eaa88a5bcc7 4754 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
mbed_official 114:fe4fe5cfc3a3 4755
mbed_official 114:fe4fe5cfc3a3 4756 /**
mbed_official 114:fe4fe5cfc3a3 4757 * @brief EXTI4 configuration
mbed_official 114:fe4fe5cfc3a3 4758 */
<> 151:5eaa88a5bcc7 4759 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
<> 151:5eaa88a5bcc7 4760 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
<> 151:5eaa88a5bcc7 4761 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
mbed_official 114:fe4fe5cfc3a3 4762
mbed_official 114:fe4fe5cfc3a3 4763 /**
mbed_official 114:fe4fe5cfc3a3 4764 * @brief EXTI5 configuration
mbed_official 114:fe4fe5cfc3a3 4765 */
<> 151:5eaa88a5bcc7 4766 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
<> 151:5eaa88a5bcc7 4767 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
<> 151:5eaa88a5bcc7 4768 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
mbed_official 114:fe4fe5cfc3a3 4769
mbed_official 114:fe4fe5cfc3a3 4770 /**
mbed_official 114:fe4fe5cfc3a3 4771 * @brief EXTI6 configuration
mbed_official 114:fe4fe5cfc3a3 4772 */
<> 151:5eaa88a5bcc7 4773 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
<> 151:5eaa88a5bcc7 4774 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
<> 151:5eaa88a5bcc7 4775 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
mbed_official 114:fe4fe5cfc3a3 4776
mbed_official 114:fe4fe5cfc3a3 4777 /**
mbed_official 114:fe4fe5cfc3a3 4778 * @brief EXTI7 configuration
mbed_official 114:fe4fe5cfc3a3 4779 */
<> 151:5eaa88a5bcc7 4780 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
<> 151:5eaa88a5bcc7 4781 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
<> 151:5eaa88a5bcc7 4782 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
mbed_official 114:fe4fe5cfc3a3 4783
mbed_official 114:fe4fe5cfc3a3 4784 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
<> 151:5eaa88a5bcc7 4785 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
<> 151:5eaa88a5bcc7 4786 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 4787 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
<> 151:5eaa88a5bcc7 4788 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
<> 151:5eaa88a5bcc7 4789 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
<> 151:5eaa88a5bcc7 4790 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
<> 151:5eaa88a5bcc7 4791 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
<> 151:5eaa88a5bcc7 4792 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 4793 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
<> 151:5eaa88a5bcc7 4794 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
<> 151:5eaa88a5bcc7 4795 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
<> 151:5eaa88a5bcc7 4796 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
mbed_official 114:fe4fe5cfc3a3 4797
mbed_official 114:fe4fe5cfc3a3 4798 /**
mbed_official 114:fe4fe5cfc3a3 4799 * @brief EXTI8 configuration
mbed_official 114:fe4fe5cfc3a3 4800 */
<> 151:5eaa88a5bcc7 4801 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
<> 151:5eaa88a5bcc7 4802 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
<> 151:5eaa88a5bcc7 4803 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
mbed_official 114:fe4fe5cfc3a3 4804
mbed_official 114:fe4fe5cfc3a3 4805 /**
mbed_official 114:fe4fe5cfc3a3 4806 * @brief EXTI9 configuration
mbed_official 114:fe4fe5cfc3a3 4807 */
<> 151:5eaa88a5bcc7 4808 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
<> 151:5eaa88a5bcc7 4809 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
<> 151:5eaa88a5bcc7 4810 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
mbed_official 114:fe4fe5cfc3a3 4811
mbed_official 114:fe4fe5cfc3a3 4812 /**
mbed_official 114:fe4fe5cfc3a3 4813 * @brief EXTI10 configuration
mbed_official 114:fe4fe5cfc3a3 4814 */
<> 151:5eaa88a5bcc7 4815 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
<> 151:5eaa88a5bcc7 4816 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
<> 151:5eaa88a5bcc7 4817 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
mbed_official 114:fe4fe5cfc3a3 4818
mbed_official 114:fe4fe5cfc3a3 4819 /**
mbed_official 114:fe4fe5cfc3a3 4820 * @brief EXTI11 configuration
mbed_official 114:fe4fe5cfc3a3 4821 */
<> 151:5eaa88a5bcc7 4822 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
<> 151:5eaa88a5bcc7 4823 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
<> 151:5eaa88a5bcc7 4824 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
mbed_official 114:fe4fe5cfc3a3 4825
mbed_official 114:fe4fe5cfc3a3 4826 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
<> 151:5eaa88a5bcc7 4827 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
<> 151:5eaa88a5bcc7 4828 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 4829 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
<> 151:5eaa88a5bcc7 4830 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
<> 151:5eaa88a5bcc7 4831 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
<> 151:5eaa88a5bcc7 4832 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
<> 151:5eaa88a5bcc7 4833 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
<> 151:5eaa88a5bcc7 4834 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 4835 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
<> 151:5eaa88a5bcc7 4836 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
<> 151:5eaa88a5bcc7 4837 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
<> 151:5eaa88a5bcc7 4838 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
mbed_official 114:fe4fe5cfc3a3 4839
mbed_official 114:fe4fe5cfc3a3 4840 /**
mbed_official 114:fe4fe5cfc3a3 4841 * @brief EXTI12 configuration
mbed_official 114:fe4fe5cfc3a3 4842 */
<> 151:5eaa88a5bcc7 4843 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
<> 151:5eaa88a5bcc7 4844 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
<> 151:5eaa88a5bcc7 4845 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
mbed_official 114:fe4fe5cfc3a3 4846
mbed_official 114:fe4fe5cfc3a3 4847 /**
mbed_official 114:fe4fe5cfc3a3 4848 * @brief EXTI13 configuration
mbed_official 114:fe4fe5cfc3a3 4849 */
<> 151:5eaa88a5bcc7 4850 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
<> 151:5eaa88a5bcc7 4851 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
<> 151:5eaa88a5bcc7 4852 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
mbed_official 114:fe4fe5cfc3a3 4853
mbed_official 114:fe4fe5cfc3a3 4854 /**
mbed_official 114:fe4fe5cfc3a3 4855 * @brief EXTI14 configuration
mbed_official 114:fe4fe5cfc3a3 4856 */
<> 151:5eaa88a5bcc7 4857 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
<> 151:5eaa88a5bcc7 4858 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
<> 151:5eaa88a5bcc7 4859 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
mbed_official 114:fe4fe5cfc3a3 4860
mbed_official 114:fe4fe5cfc3a3 4861 /**
mbed_official 114:fe4fe5cfc3a3 4862 * @brief EXTI15 configuration
mbed_official 114:fe4fe5cfc3a3 4863 */
<> 151:5eaa88a5bcc7 4864 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
<> 151:5eaa88a5bcc7 4865 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
<> 151:5eaa88a5bcc7 4866 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
mbed_official 114:fe4fe5cfc3a3 4867
mbed_official 114:fe4fe5cfc3a3 4868
mbed_official 114:fe4fe5cfc3a3 4869 /***************** Bit definition for SYSCFG_CFGR3 register ****************/
<> 151:5eaa88a5bcc7 4870 #define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
<> 151:5eaa88a5bcc7 4871 #define SYSCFG_CFGR3_VREF_OUT_Msk (0x3U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
<> 151:5eaa88a5bcc7 4872 #define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
<> 151:5eaa88a5bcc7 4873 #define SYSCFG_CFGR3_VREF_OUT_0 (0x1U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4874 #define SYSCFG_CFGR3_VREF_OUT_1 (0x2U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4875 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
<> 151:5eaa88a5bcc7 4876 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4877 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
<> 151:5eaa88a5bcc7 4878 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
<> 151:5eaa88a5bcc7 4879 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4880 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
<> 151:5eaa88a5bcc7 4881 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
<> 151:5eaa88a5bcc7 4882 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 4883 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
<> 151:5eaa88a5bcc7 4884 #define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
<> 151:5eaa88a5bcc7 4885 #define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
<> 151:5eaa88a5bcc7 4886 #define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
<> 151:5eaa88a5bcc7 4887 #define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
<> 151:5eaa88a5bcc7 4888 #define SYSCFG_CFGR3_REF_LOCK_Msk (0x1U << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
<> 151:5eaa88a5bcc7 4889 #define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
mbed_official 114:fe4fe5cfc3a3 4890
mbed_official 114:fe4fe5cfc3a3 4891 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 4892
mbed_official 114:fe4fe5cfc3a3 4893 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
mbed_official 114:fe4fe5cfc3a3 4894 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
<> 151:5eaa88a5bcc7 4895 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
<> 151:5eaa88a5bcc7 4896 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
<> 151:5eaa88a5bcc7 4897 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
<> 151:5eaa88a5bcc7 4898 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
mbed_official 114:fe4fe5cfc3a3 4899
mbed_official 114:fe4fe5cfc3a3 4900 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 4901 /* */
mbed_official 114:fe4fe5cfc3a3 4902 /* Timers (TIM) */
mbed_official 114:fe4fe5cfc3a3 4903 /* */
mbed_official 114:fe4fe5cfc3a3 4904 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 4905 /*
mbed_official 114:fe4fe5cfc3a3 4906 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
mbed_official 114:fe4fe5cfc3a3 4907 */
mbed_official 114:fe4fe5cfc3a3 4908 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
mbed_official 114:fe4fe5cfc3a3 4909 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
mbed_official 114:fe4fe5cfc3a3 4910 #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
mbed_official 114:fe4fe5cfc3a3 4911 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
mbed_official 114:fe4fe5cfc3a3 4912 #else
mbed_official 114:fe4fe5cfc3a3 4913 #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
mbed_official 114:fe4fe5cfc3a3 4914 #endif
mbed_official 114:fe4fe5cfc3a3 4915
mbed_official 114:fe4fe5cfc3a3 4916 /******************* Bit definition for TIM_CR1 register ********************/
<> 151:5eaa88a5bcc7 4917 #define TIM_CR1_CEN_Pos (0U)
<> 151:5eaa88a5bcc7 4918 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4919 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
<> 151:5eaa88a5bcc7 4920 #define TIM_CR1_UDIS_Pos (1U)
<> 151:5eaa88a5bcc7 4921 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4922 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
<> 151:5eaa88a5bcc7 4923 #define TIM_CR1_URS_Pos (2U)
<> 151:5eaa88a5bcc7 4924 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4925 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
<> 151:5eaa88a5bcc7 4926 #define TIM_CR1_OPM_Pos (3U)
<> 151:5eaa88a5bcc7 4927 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 4928 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
<> 151:5eaa88a5bcc7 4929 #define TIM_CR1_DIR_Pos (4U)
<> 151:5eaa88a5bcc7 4930 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4931 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
<> 151:5eaa88a5bcc7 4932
<> 151:5eaa88a5bcc7 4933 #define TIM_CR1_CMS_Pos (5U)
<> 151:5eaa88a5bcc7 4934 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
<> 151:5eaa88a5bcc7 4935 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 151:5eaa88a5bcc7 4936 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4937 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4938
<> 151:5eaa88a5bcc7 4939 #define TIM_CR1_ARPE_Pos (7U)
<> 151:5eaa88a5bcc7 4940 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4941 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
<> 151:5eaa88a5bcc7 4942
<> 151:5eaa88a5bcc7 4943 #define TIM_CR1_CKD_Pos (8U)
<> 151:5eaa88a5bcc7 4944 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
<> 151:5eaa88a5bcc7 4945 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
<> 151:5eaa88a5bcc7 4946 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4947 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
mbed_official 114:fe4fe5cfc3a3 4948
mbed_official 114:fe4fe5cfc3a3 4949 /******************* Bit definition for TIM_CR2 register ********************/
<> 151:5eaa88a5bcc7 4950 #define TIM_CR2_CCDS_Pos (3U)
<> 151:5eaa88a5bcc7 4951 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 4952 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
<> 151:5eaa88a5bcc7 4953
<> 151:5eaa88a5bcc7 4954 #define TIM_CR2_MMS_Pos (4U)
<> 151:5eaa88a5bcc7 4955 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
<> 151:5eaa88a5bcc7 4956 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
<> 151:5eaa88a5bcc7 4957 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4958 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4959 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4960
<> 151:5eaa88a5bcc7 4961 #define TIM_CR2_TI1S_Pos (7U)
<> 151:5eaa88a5bcc7 4962 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4963 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
mbed_official 114:fe4fe5cfc3a3 4964
mbed_official 114:fe4fe5cfc3a3 4965 /******************* Bit definition for TIM_SMCR register *******************/
<> 151:5eaa88a5bcc7 4966 #define TIM_SMCR_SMS_Pos (0U)
<> 151:5eaa88a5bcc7 4967 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
<> 151:5eaa88a5bcc7 4968 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
<> 151:5eaa88a5bcc7 4969 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 4970 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 4971 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 4972
<> 151:5eaa88a5bcc7 4973 #define TIM_SMCR_OCCS_Pos (3U)
<> 151:5eaa88a5bcc7 4974 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 4975 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
<> 151:5eaa88a5bcc7 4976
<> 151:5eaa88a5bcc7 4977 #define TIM_SMCR_TS_Pos (4U)
<> 151:5eaa88a5bcc7 4978 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
<> 151:5eaa88a5bcc7 4979 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
<> 151:5eaa88a5bcc7 4980 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 4981 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 4982 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 4983
<> 151:5eaa88a5bcc7 4984 #define TIM_SMCR_MSM_Pos (7U)
<> 151:5eaa88a5bcc7 4985 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 4986 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
<> 151:5eaa88a5bcc7 4987
<> 151:5eaa88a5bcc7 4988 #define TIM_SMCR_ETF_Pos (8U)
<> 151:5eaa88a5bcc7 4989 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
<> 151:5eaa88a5bcc7 4990 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
<> 151:5eaa88a5bcc7 4991 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 4992 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 4993 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 4994 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 4995
<> 151:5eaa88a5bcc7 4996 #define TIM_SMCR_ETPS_Pos (12U)
<> 151:5eaa88a5bcc7 4997 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
<> 151:5eaa88a5bcc7 4998 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 151:5eaa88a5bcc7 4999 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5000 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 5001
<> 151:5eaa88a5bcc7 5002 #define TIM_SMCR_ECE_Pos (14U)
<> 151:5eaa88a5bcc7 5003 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 5004 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
<> 151:5eaa88a5bcc7 5005 #define TIM_SMCR_ETP_Pos (15U)
<> 151:5eaa88a5bcc7 5006 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 5007 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
mbed_official 114:fe4fe5cfc3a3 5008
mbed_official 114:fe4fe5cfc3a3 5009 /******************* Bit definition for TIM_DIER register *******************/
<> 151:5eaa88a5bcc7 5010 #define TIM_DIER_UIE_Pos (0U)
<> 151:5eaa88a5bcc7 5011 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5012 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
<> 151:5eaa88a5bcc7 5013 #define TIM_DIER_CC1IE_Pos (1U)
<> 151:5eaa88a5bcc7 5014 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5015 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
<> 151:5eaa88a5bcc7 5016 #define TIM_DIER_CC2IE_Pos (2U)
<> 151:5eaa88a5bcc7 5017 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5018 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
<> 151:5eaa88a5bcc7 5019 #define TIM_DIER_CC3IE_Pos (3U)
<> 151:5eaa88a5bcc7 5020 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5021 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
<> 151:5eaa88a5bcc7 5022 #define TIM_DIER_CC4IE_Pos (4U)
<> 151:5eaa88a5bcc7 5023 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5024 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
<> 151:5eaa88a5bcc7 5025 #define TIM_DIER_TIE_Pos (6U)
<> 151:5eaa88a5bcc7 5026 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5027 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
<> 151:5eaa88a5bcc7 5028 #define TIM_DIER_UDE_Pos (8U)
<> 151:5eaa88a5bcc7 5029 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 5030 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
<> 151:5eaa88a5bcc7 5031 #define TIM_DIER_CC1DE_Pos (9U)
<> 151:5eaa88a5bcc7 5032 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5033 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
<> 151:5eaa88a5bcc7 5034 #define TIM_DIER_CC2DE_Pos (10U)
<> 151:5eaa88a5bcc7 5035 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5036 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
<> 151:5eaa88a5bcc7 5037 #define TIM_DIER_CC3DE_Pos (11U)
<> 151:5eaa88a5bcc7 5038 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5039 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
<> 151:5eaa88a5bcc7 5040 #define TIM_DIER_CC4DE_Pos (12U)
<> 151:5eaa88a5bcc7 5041 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5042 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
<> 151:5eaa88a5bcc7 5043 #define TIM_DIER_TDE_Pos (14U)
<> 151:5eaa88a5bcc7 5044 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 5045 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
mbed_official 114:fe4fe5cfc3a3 5046
mbed_official 114:fe4fe5cfc3a3 5047 /******************** Bit definition for TIM_SR register ********************/
<> 151:5eaa88a5bcc7 5048 #define TIM_SR_UIF_Pos (0U)
<> 151:5eaa88a5bcc7 5049 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5050 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
<> 151:5eaa88a5bcc7 5051 #define TIM_SR_CC1IF_Pos (1U)
<> 151:5eaa88a5bcc7 5052 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5053 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
<> 151:5eaa88a5bcc7 5054 #define TIM_SR_CC2IF_Pos (2U)
<> 151:5eaa88a5bcc7 5055 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5056 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
<> 151:5eaa88a5bcc7 5057 #define TIM_SR_CC3IF_Pos (3U)
<> 151:5eaa88a5bcc7 5058 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5059 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
<> 151:5eaa88a5bcc7 5060 #define TIM_SR_CC4IF_Pos (4U)
<> 151:5eaa88a5bcc7 5061 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5062 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
<> 151:5eaa88a5bcc7 5063 #define TIM_SR_TIF_Pos (6U)
<> 151:5eaa88a5bcc7 5064 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5065 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
<> 151:5eaa88a5bcc7 5066 #define TIM_SR_CC1OF_Pos (9U)
<> 151:5eaa88a5bcc7 5067 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5068 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
<> 151:5eaa88a5bcc7 5069 #define TIM_SR_CC2OF_Pos (10U)
<> 151:5eaa88a5bcc7 5070 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5071 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
<> 151:5eaa88a5bcc7 5072 #define TIM_SR_CC3OF_Pos (11U)
<> 151:5eaa88a5bcc7 5073 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5074 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
<> 151:5eaa88a5bcc7 5075 #define TIM_SR_CC4OF_Pos (12U)
<> 151:5eaa88a5bcc7 5076 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5077 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 114:fe4fe5cfc3a3 5078
mbed_official 114:fe4fe5cfc3a3 5079 /******************* Bit definition for TIM_EGR register ********************/
<> 151:5eaa88a5bcc7 5080 #define TIM_EGR_UG_Pos (0U)
<> 151:5eaa88a5bcc7 5081 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5082 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
<> 151:5eaa88a5bcc7 5083 #define TIM_EGR_CC1G_Pos (1U)
<> 151:5eaa88a5bcc7 5084 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5085 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
<> 151:5eaa88a5bcc7 5086 #define TIM_EGR_CC2G_Pos (2U)
<> 151:5eaa88a5bcc7 5087 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5088 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
<> 151:5eaa88a5bcc7 5089 #define TIM_EGR_CC3G_Pos (3U)
<> 151:5eaa88a5bcc7 5090 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5091 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
<> 151:5eaa88a5bcc7 5092 #define TIM_EGR_CC4G_Pos (4U)
<> 151:5eaa88a5bcc7 5093 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5094 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
<> 151:5eaa88a5bcc7 5095 #define TIM_EGR_TG_Pos (6U)
<> 151:5eaa88a5bcc7 5096 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5097 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
mbed_official 114:fe4fe5cfc3a3 5098
mbed_official 114:fe4fe5cfc3a3 5099 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 151:5eaa88a5bcc7 5100 #define TIM_CCMR1_CC1S_Pos (0U)
<> 151:5eaa88a5bcc7 5101 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
<> 151:5eaa88a5bcc7 5102 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 151:5eaa88a5bcc7 5103 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5104 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5105
<> 151:5eaa88a5bcc7 5106 #define TIM_CCMR1_OC1FE_Pos (2U)
<> 151:5eaa88a5bcc7 5107 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5108 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
<> 151:5eaa88a5bcc7 5109 #define TIM_CCMR1_OC1PE_Pos (3U)
<> 151:5eaa88a5bcc7 5110 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5111 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
<> 151:5eaa88a5bcc7 5112
<> 151:5eaa88a5bcc7 5113 #define TIM_CCMR1_OC1M_Pos (4U)
<> 151:5eaa88a5bcc7 5114 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
<> 151:5eaa88a5bcc7 5115 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 151:5eaa88a5bcc7 5116 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5117 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5118 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5119
<> 151:5eaa88a5bcc7 5120 #define TIM_CCMR1_OC1CE_Pos (7U)
<> 151:5eaa88a5bcc7 5121 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 5122 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
<> 151:5eaa88a5bcc7 5123
<> 151:5eaa88a5bcc7 5124 #define TIM_CCMR1_CC2S_Pos (8U)
<> 151:5eaa88a5bcc7 5125 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
<> 151:5eaa88a5bcc7 5126 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 151:5eaa88a5bcc7 5127 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 5128 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5129
<> 151:5eaa88a5bcc7 5130 #define TIM_CCMR1_OC2FE_Pos (10U)
<> 151:5eaa88a5bcc7 5131 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5132 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
<> 151:5eaa88a5bcc7 5133 #define TIM_CCMR1_OC2PE_Pos (11U)
<> 151:5eaa88a5bcc7 5134 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5135 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
<> 151:5eaa88a5bcc7 5136
<> 151:5eaa88a5bcc7 5137 #define TIM_CCMR1_OC2M_Pos (12U)
<> 151:5eaa88a5bcc7 5138 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
<> 151:5eaa88a5bcc7 5139 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 151:5eaa88a5bcc7 5140 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5141 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 5142 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 5143
<> 151:5eaa88a5bcc7 5144 #define TIM_CCMR1_OC2CE_Pos (15U)
<> 151:5eaa88a5bcc7 5145 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 5146 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
mbed_official 114:fe4fe5cfc3a3 5147
mbed_official 114:fe4fe5cfc3a3 5148 /*----------------------------------------------------------------------------*/
mbed_official 114:fe4fe5cfc3a3 5149
<> 151:5eaa88a5bcc7 5150 #define TIM_CCMR1_IC1PSC_Pos (2U)
<> 151:5eaa88a5bcc7 5151 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
<> 151:5eaa88a5bcc7 5152 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 151:5eaa88a5bcc7 5153 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5154 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5155
<> 151:5eaa88a5bcc7 5156 #define TIM_CCMR1_IC1F_Pos (4U)
<> 151:5eaa88a5bcc7 5157 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
<> 151:5eaa88a5bcc7 5158 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 151:5eaa88a5bcc7 5159 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5160 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5161 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5162 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 5163
<> 151:5eaa88a5bcc7 5164 #define TIM_CCMR1_IC2PSC_Pos (10U)
<> 151:5eaa88a5bcc7 5165 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
<> 151:5eaa88a5bcc7 5166 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 151:5eaa88a5bcc7 5167 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5168 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5169
<> 151:5eaa88a5bcc7 5170 #define TIM_CCMR1_IC2F_Pos (12U)
<> 151:5eaa88a5bcc7 5171 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
<> 151:5eaa88a5bcc7 5172 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 151:5eaa88a5bcc7 5173 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5174 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 5175 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 5176 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
mbed_official 114:fe4fe5cfc3a3 5177
mbed_official 114:fe4fe5cfc3a3 5178 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 151:5eaa88a5bcc7 5179 #define TIM_CCMR2_CC3S_Pos (0U)
<> 151:5eaa88a5bcc7 5180 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
<> 151:5eaa88a5bcc7 5181 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 151:5eaa88a5bcc7 5182 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5183 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5184
<> 151:5eaa88a5bcc7 5185 #define TIM_CCMR2_OC3FE_Pos (2U)
<> 151:5eaa88a5bcc7 5186 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5187 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
<> 151:5eaa88a5bcc7 5188 #define TIM_CCMR2_OC3PE_Pos (3U)
<> 151:5eaa88a5bcc7 5189 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5190 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
<> 151:5eaa88a5bcc7 5191
<> 151:5eaa88a5bcc7 5192 #define TIM_CCMR2_OC3M_Pos (4U)
<> 151:5eaa88a5bcc7 5193 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
<> 151:5eaa88a5bcc7 5194 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 151:5eaa88a5bcc7 5195 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5196 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5197 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5198
<> 151:5eaa88a5bcc7 5199 #define TIM_CCMR2_OC3CE_Pos (7U)
<> 151:5eaa88a5bcc7 5200 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 5201 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
<> 151:5eaa88a5bcc7 5202
<> 151:5eaa88a5bcc7 5203 #define TIM_CCMR2_CC4S_Pos (8U)
<> 151:5eaa88a5bcc7 5204 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
<> 151:5eaa88a5bcc7 5205 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 151:5eaa88a5bcc7 5206 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 5207 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5208
<> 151:5eaa88a5bcc7 5209 #define TIM_CCMR2_OC4FE_Pos (10U)
<> 151:5eaa88a5bcc7 5210 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5211 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
<> 151:5eaa88a5bcc7 5212 #define TIM_CCMR2_OC4PE_Pos (11U)
<> 151:5eaa88a5bcc7 5213 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5214 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
<> 151:5eaa88a5bcc7 5215
<> 151:5eaa88a5bcc7 5216 #define TIM_CCMR2_OC4M_Pos (12U)
<> 151:5eaa88a5bcc7 5217 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
<> 151:5eaa88a5bcc7 5218 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 151:5eaa88a5bcc7 5219 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5220 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 5221 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 5222
<> 151:5eaa88a5bcc7 5223 #define TIM_CCMR2_OC4CE_Pos (15U)
<> 151:5eaa88a5bcc7 5224 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 5225 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
mbed_official 114:fe4fe5cfc3a3 5226
mbed_official 114:fe4fe5cfc3a3 5227 /*----------------------------------------------------------------------------*/
mbed_official 114:fe4fe5cfc3a3 5228
<> 151:5eaa88a5bcc7 5229 #define TIM_CCMR2_IC3PSC_Pos (2U)
<> 151:5eaa88a5bcc7 5230 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
<> 151:5eaa88a5bcc7 5231 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 151:5eaa88a5bcc7 5232 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5233 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5234
<> 151:5eaa88a5bcc7 5235 #define TIM_CCMR2_IC3F_Pos (4U)
<> 151:5eaa88a5bcc7 5236 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
<> 151:5eaa88a5bcc7 5237 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 151:5eaa88a5bcc7 5238 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5239 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5240 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5241 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 5242
<> 151:5eaa88a5bcc7 5243 #define TIM_CCMR2_IC4PSC_Pos (10U)
<> 151:5eaa88a5bcc7 5244 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
<> 151:5eaa88a5bcc7 5245 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 151:5eaa88a5bcc7 5246 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5247 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5248
<> 151:5eaa88a5bcc7 5249 #define TIM_CCMR2_IC4F_Pos (12U)
<> 151:5eaa88a5bcc7 5250 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
<> 151:5eaa88a5bcc7 5251 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 151:5eaa88a5bcc7 5252 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5253 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 5254 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 5255 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
mbed_official 114:fe4fe5cfc3a3 5256
mbed_official 114:fe4fe5cfc3a3 5257 /******************* Bit definition for TIM_CCER register *******************/
<> 151:5eaa88a5bcc7 5258 #define TIM_CCER_CC1E_Pos (0U)
<> 151:5eaa88a5bcc7 5259 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5260 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
<> 151:5eaa88a5bcc7 5261 #define TIM_CCER_CC1P_Pos (1U)
<> 151:5eaa88a5bcc7 5262 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5263 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
<> 151:5eaa88a5bcc7 5264 #define TIM_CCER_CC1NP_Pos (3U)
<> 151:5eaa88a5bcc7 5265 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5266 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
<> 151:5eaa88a5bcc7 5267 #define TIM_CCER_CC2E_Pos (4U)
<> 151:5eaa88a5bcc7 5268 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5269 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
<> 151:5eaa88a5bcc7 5270 #define TIM_CCER_CC2P_Pos (5U)
<> 151:5eaa88a5bcc7 5271 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5272 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
<> 151:5eaa88a5bcc7 5273 #define TIM_CCER_CC2NP_Pos (7U)
<> 151:5eaa88a5bcc7 5274 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 5275 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
<> 151:5eaa88a5bcc7 5276 #define TIM_CCER_CC3E_Pos (8U)
<> 151:5eaa88a5bcc7 5277 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 5278 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
<> 151:5eaa88a5bcc7 5279 #define TIM_CCER_CC3P_Pos (9U)
<> 151:5eaa88a5bcc7 5280 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5281 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
<> 151:5eaa88a5bcc7 5282 #define TIM_CCER_CC3NP_Pos (11U)
<> 151:5eaa88a5bcc7 5283 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5284 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
<> 151:5eaa88a5bcc7 5285 #define TIM_CCER_CC4E_Pos (12U)
<> 151:5eaa88a5bcc7 5286 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5287 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
<> 151:5eaa88a5bcc7 5288 #define TIM_CCER_CC4P_Pos (13U)
<> 151:5eaa88a5bcc7 5289 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 5290 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
<> 151:5eaa88a5bcc7 5291 #define TIM_CCER_CC4NP_Pos (15U)
<> 151:5eaa88a5bcc7 5292 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 5293 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 114:fe4fe5cfc3a3 5294
mbed_official 114:fe4fe5cfc3a3 5295 /******************* Bit definition for TIM_CNT register ********************/
<> 151:5eaa88a5bcc7 5296 #define TIM_CNT_CNT_Pos (0U)
<> 151:5eaa88a5bcc7 5297 #define TIM_CNT_CNT_Msk (0xFFFFU << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 5298 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
mbed_official 114:fe4fe5cfc3a3 5299
mbed_official 114:fe4fe5cfc3a3 5300 /******************* Bit definition for TIM_PSC register ********************/
<> 151:5eaa88a5bcc7 5301 #define TIM_PSC_PSC_Pos (0U)
<> 151:5eaa88a5bcc7 5302 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 5303 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
mbed_official 114:fe4fe5cfc3a3 5304
mbed_official 114:fe4fe5cfc3a3 5305 /******************* Bit definition for TIM_ARR register ********************/
<> 151:5eaa88a5bcc7 5306 #define TIM_ARR_ARR_Pos (0U)
<> 151:5eaa88a5bcc7 5307 #define TIM_ARR_ARR_Msk (0xFFFFU << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 5308 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
mbed_official 114:fe4fe5cfc3a3 5309
mbed_official 114:fe4fe5cfc3a3 5310 /******************* Bit definition for TIM_CCR1 register *******************/
<> 151:5eaa88a5bcc7 5311 #define TIM_CCR1_CCR1_Pos (0U)
<> 151:5eaa88a5bcc7 5312 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 5313 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
mbed_official 114:fe4fe5cfc3a3 5314
mbed_official 114:fe4fe5cfc3a3 5315 /******************* Bit definition for TIM_CCR2 register *******************/
<> 151:5eaa88a5bcc7 5316 #define TIM_CCR2_CCR2_Pos (0U)
<> 151:5eaa88a5bcc7 5317 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 5318 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
mbed_official 114:fe4fe5cfc3a3 5319
mbed_official 114:fe4fe5cfc3a3 5320 /******************* Bit definition for TIM_CCR3 register *******************/
<> 151:5eaa88a5bcc7 5321 #define TIM_CCR3_CCR3_Pos (0U)
<> 151:5eaa88a5bcc7 5322 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 5323 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
mbed_official 114:fe4fe5cfc3a3 5324
mbed_official 114:fe4fe5cfc3a3 5325 /******************* Bit definition for TIM_CCR4 register *******************/
<> 151:5eaa88a5bcc7 5326 #define TIM_CCR4_CCR4_Pos (0U)
<> 151:5eaa88a5bcc7 5327 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 5328 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
mbed_official 114:fe4fe5cfc3a3 5329
mbed_official 114:fe4fe5cfc3a3 5330 /******************* Bit definition for TIM_DCR register ********************/
<> 151:5eaa88a5bcc7 5331 #define TIM_DCR_DBA_Pos (0U)
<> 151:5eaa88a5bcc7 5332 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
<> 151:5eaa88a5bcc7 5333 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
<> 151:5eaa88a5bcc7 5334 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5335 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5336 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5337 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5338 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5339
<> 151:5eaa88a5bcc7 5340 #define TIM_DCR_DBL_Pos (8U)
<> 151:5eaa88a5bcc7 5341 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
<> 151:5eaa88a5bcc7 5342 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
<> 151:5eaa88a5bcc7 5343 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 5344 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5345 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5346 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5347 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
mbed_official 114:fe4fe5cfc3a3 5348
mbed_official 114:fe4fe5cfc3a3 5349 /******************* Bit definition for TIM_DMAR register *******************/
<> 151:5eaa88a5bcc7 5350 #define TIM_DMAR_DMAB_Pos (0U)
<> 151:5eaa88a5bcc7 5351 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
<> 151:5eaa88a5bcc7 5352 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
mbed_official 114:fe4fe5cfc3a3 5353
mbed_official 114:fe4fe5cfc3a3 5354 /******************* Bit definition for TIM_OR register *********************/
<> 151:5eaa88a5bcc7 5355 #define TIM2_OR_ETR_RMP_Pos (0U)
<> 151:5eaa88a5bcc7 5356 #define TIM2_OR_ETR_RMP_Msk (0x7U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
<> 151:5eaa88a5bcc7 5357 #define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
<> 151:5eaa88a5bcc7 5358 #define TIM2_OR_ETR_RMP_0 (0x1U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5359 #define TIM2_OR_ETR_RMP_1 (0x2U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5360 #define TIM2_OR_ETR_RMP_2 (0x4U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5361 #define TIM2_OR_TI4_RMP_Pos (3U)
<> 151:5eaa88a5bcc7 5362 #define TIM2_OR_TI4_RMP_Msk (0x3U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
<> 151:5eaa88a5bcc7 5363 #define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
<> 151:5eaa88a5bcc7 5364 #define TIM2_OR_TI4_RMP_0 (0x1U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5365 #define TIM2_OR_TI4_RMP_1 (0x2U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5366
<> 151:5eaa88a5bcc7 5367 #define TIM21_OR_ETR_RMP_Pos (0U)
<> 151:5eaa88a5bcc7 5368 #define TIM21_OR_ETR_RMP_Msk (0x3U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
<> 151:5eaa88a5bcc7 5369 #define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
<> 151:5eaa88a5bcc7 5370 #define TIM21_OR_ETR_RMP_0 (0x1U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5371 #define TIM21_OR_ETR_RMP_1 (0x2U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5372 #define TIM21_OR_TI1_RMP_Pos (2U)
<> 151:5eaa88a5bcc7 5373 #define TIM21_OR_TI1_RMP_Msk (0x7U << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
<> 151:5eaa88a5bcc7 5374 #define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
<> 151:5eaa88a5bcc7 5375 #define TIM21_OR_TI1_RMP_0 (0x1U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5376 #define TIM21_OR_TI1_RMP_1 (0x2U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5377 #define TIM21_OR_TI1_RMP_2 (0x4U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5378 #define TIM21_OR_TI2_RMP_Pos (5U)
<> 151:5eaa88a5bcc7 5379 #define TIM21_OR_TI2_RMP_Msk (0x1U << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5380 #define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
<> 151:5eaa88a5bcc7 5381
<> 151:5eaa88a5bcc7 5382 #define TIM22_OR_ETR_RMP_Pos (0U)
<> 151:5eaa88a5bcc7 5383 #define TIM22_OR_ETR_RMP_Msk (0x3U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
<> 151:5eaa88a5bcc7 5384 #define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
<> 151:5eaa88a5bcc7 5385 #define TIM22_OR_ETR_RMP_0 (0x1U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5386 #define TIM22_OR_ETR_RMP_1 (0x2U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5387 #define TIM22_OR_TI1_RMP_Pos (2U)
<> 151:5eaa88a5bcc7 5388 #define TIM22_OR_TI1_RMP_Msk (0x3U << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
<> 151:5eaa88a5bcc7 5389 #define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
<> 151:5eaa88a5bcc7 5390 #define TIM22_OR_TI1_RMP_0 (0x1U << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5391 #define TIM22_OR_TI1_RMP_1 (0x2U << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
mbed_official 114:fe4fe5cfc3a3 5392
mbed_official 114:fe4fe5cfc3a3 5393
mbed_official 114:fe4fe5cfc3a3 5394 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 5395 /* */
mbed_official 114:fe4fe5cfc3a3 5396 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 114:fe4fe5cfc3a3 5397 /* */
mbed_official 114:fe4fe5cfc3a3 5398 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 5399
mbed_official 114:fe4fe5cfc3a3 5400 /*
mbed_official 114:fe4fe5cfc3a3 5401 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
mbed_official 114:fe4fe5cfc3a3 5402 */
mbed_official 114:fe4fe5cfc3a3 5403 /* Note: No specific macro feature on this device */
mbed_official 114:fe4fe5cfc3a3 5404
mbed_official 114:fe4fe5cfc3a3 5405 /****************** Bit definition for USART_CR1 register *******************/
<> 151:5eaa88a5bcc7 5406 #define USART_CR1_UE_Pos (0U)
<> 151:5eaa88a5bcc7 5407 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5408 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
<> 151:5eaa88a5bcc7 5409 #define USART_CR1_UESM_Pos (1U)
<> 151:5eaa88a5bcc7 5410 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5411 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
<> 151:5eaa88a5bcc7 5412 #define USART_CR1_RE_Pos (2U)
<> 151:5eaa88a5bcc7 5413 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5414 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
<> 151:5eaa88a5bcc7 5415 #define USART_CR1_TE_Pos (3U)
<> 151:5eaa88a5bcc7 5416 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5417 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
<> 151:5eaa88a5bcc7 5418 #define USART_CR1_IDLEIE_Pos (4U)
<> 151:5eaa88a5bcc7 5419 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5420 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
<> 151:5eaa88a5bcc7 5421 #define USART_CR1_RXNEIE_Pos (5U)
<> 151:5eaa88a5bcc7 5422 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5423 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
<> 151:5eaa88a5bcc7 5424 #define USART_CR1_TCIE_Pos (6U)
<> 151:5eaa88a5bcc7 5425 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5426 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
<> 151:5eaa88a5bcc7 5427 #define USART_CR1_TXEIE_Pos (7U)
<> 151:5eaa88a5bcc7 5428 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 5429 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
<> 151:5eaa88a5bcc7 5430 #define USART_CR1_PEIE_Pos (8U)
<> 151:5eaa88a5bcc7 5431 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 5432 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
<> 151:5eaa88a5bcc7 5433 #define USART_CR1_PS_Pos (9U)
<> 151:5eaa88a5bcc7 5434 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5435 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
<> 151:5eaa88a5bcc7 5436 #define USART_CR1_PCE_Pos (10U)
<> 151:5eaa88a5bcc7 5437 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5438 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
<> 151:5eaa88a5bcc7 5439 #define USART_CR1_WAKE_Pos (11U)
<> 151:5eaa88a5bcc7 5440 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5441 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
<> 151:5eaa88a5bcc7 5442 #define USART_CR1_M_Pos (12U)
<> 151:5eaa88a5bcc7 5443 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
<> 151:5eaa88a5bcc7 5444 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
<> 151:5eaa88a5bcc7 5445 #define USART_CR1_M0_Pos (12U)
<> 151:5eaa88a5bcc7 5446 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5447 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
<> 151:5eaa88a5bcc7 5448 #define USART_CR1_MME_Pos (13U)
<> 151:5eaa88a5bcc7 5449 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 5450 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
<> 151:5eaa88a5bcc7 5451 #define USART_CR1_CMIE_Pos (14U)
<> 151:5eaa88a5bcc7 5452 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 5453 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
<> 151:5eaa88a5bcc7 5454 #define USART_CR1_OVER8_Pos (15U)
<> 151:5eaa88a5bcc7 5455 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 5456 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
<> 151:5eaa88a5bcc7 5457 #define USART_CR1_DEDT_Pos (16U)
<> 151:5eaa88a5bcc7 5458 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
<> 151:5eaa88a5bcc7 5459 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
<> 151:5eaa88a5bcc7 5460 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 5461 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 5462 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 5463 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 5464 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 5465 #define USART_CR1_DEAT_Pos (21U)
<> 151:5eaa88a5bcc7 5466 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
<> 151:5eaa88a5bcc7 5467 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
<> 151:5eaa88a5bcc7 5468 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 5469 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 5470 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 5471 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
<> 151:5eaa88a5bcc7 5472 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
<> 151:5eaa88a5bcc7 5473 #define USART_CR1_RTOIE_Pos (26U)
<> 151:5eaa88a5bcc7 5474 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
<> 151:5eaa88a5bcc7 5475 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
<> 151:5eaa88a5bcc7 5476 #define USART_CR1_EOBIE_Pos (27U)
<> 151:5eaa88a5bcc7 5477 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
<> 151:5eaa88a5bcc7 5478 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
<> 151:5eaa88a5bcc7 5479 #define USART_CR1_M1_Pos (28U)
<> 151:5eaa88a5bcc7 5480 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
<> 151:5eaa88a5bcc7 5481 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
mbed_official 114:fe4fe5cfc3a3 5482 /****************** Bit definition for USART_CR2 register *******************/
<> 151:5eaa88a5bcc7 5483 #define USART_CR2_ADDM7_Pos (4U)
<> 151:5eaa88a5bcc7 5484 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5485 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
<> 151:5eaa88a5bcc7 5486 #define USART_CR2_LBDL_Pos (5U)
<> 151:5eaa88a5bcc7 5487 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5488 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
<> 151:5eaa88a5bcc7 5489 #define USART_CR2_LBDIE_Pos (6U)
<> 151:5eaa88a5bcc7 5490 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5491 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
<> 151:5eaa88a5bcc7 5492 #define USART_CR2_LBCL_Pos (8U)
<> 151:5eaa88a5bcc7 5493 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 5494 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
<> 151:5eaa88a5bcc7 5495 #define USART_CR2_CPHA_Pos (9U)
<> 151:5eaa88a5bcc7 5496 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5497 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
<> 151:5eaa88a5bcc7 5498 #define USART_CR2_CPOL_Pos (10U)
<> 151:5eaa88a5bcc7 5499 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5500 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
<> 151:5eaa88a5bcc7 5501 #define USART_CR2_CLKEN_Pos (11U)
<> 151:5eaa88a5bcc7 5502 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5503 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
<> 151:5eaa88a5bcc7 5504 #define USART_CR2_STOP_Pos (12U)
<> 151:5eaa88a5bcc7 5505 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
<> 151:5eaa88a5bcc7 5506 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
<> 151:5eaa88a5bcc7 5507 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5508 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 5509 #define USART_CR2_LINEN_Pos (14U)
<> 151:5eaa88a5bcc7 5510 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 5511 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
<> 151:5eaa88a5bcc7 5512 #define USART_CR2_SWAP_Pos (15U)
<> 151:5eaa88a5bcc7 5513 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 5514 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
<> 151:5eaa88a5bcc7 5515 #define USART_CR2_RXINV_Pos (16U)
<> 151:5eaa88a5bcc7 5516 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 5517 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
<> 151:5eaa88a5bcc7 5518 #define USART_CR2_TXINV_Pos (17U)
<> 151:5eaa88a5bcc7 5519 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 5520 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
<> 151:5eaa88a5bcc7 5521 #define USART_CR2_DATAINV_Pos (18U)
<> 151:5eaa88a5bcc7 5522 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 5523 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
<> 151:5eaa88a5bcc7 5524 #define USART_CR2_MSBFIRST_Pos (19U)
<> 151:5eaa88a5bcc7 5525 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 5526 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
<> 151:5eaa88a5bcc7 5527 #define USART_CR2_ABREN_Pos (20U)
<> 151:5eaa88a5bcc7 5528 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 5529 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
<> 151:5eaa88a5bcc7 5530 #define USART_CR2_ABRMODE_Pos (21U)
<> 151:5eaa88a5bcc7 5531 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
<> 151:5eaa88a5bcc7 5532 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
<> 151:5eaa88a5bcc7 5533 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 5534 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 5535 #define USART_CR2_RTOEN_Pos (23U)
<> 151:5eaa88a5bcc7 5536 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 5537 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
<> 151:5eaa88a5bcc7 5538 #define USART_CR2_ADD_Pos (24U)
<> 151:5eaa88a5bcc7 5539 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
<> 151:5eaa88a5bcc7 5540 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
mbed_official 114:fe4fe5cfc3a3 5541
mbed_official 114:fe4fe5cfc3a3 5542 /****************** Bit definition for USART_CR3 register *******************/
<> 151:5eaa88a5bcc7 5543 #define USART_CR3_EIE_Pos (0U)
<> 151:5eaa88a5bcc7 5544 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5545 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
<> 151:5eaa88a5bcc7 5546 #define USART_CR3_IREN_Pos (1U)
<> 151:5eaa88a5bcc7 5547 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5548 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
<> 151:5eaa88a5bcc7 5549 #define USART_CR3_IRLP_Pos (2U)
<> 151:5eaa88a5bcc7 5550 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5551 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
<> 151:5eaa88a5bcc7 5552 #define USART_CR3_HDSEL_Pos (3U)
<> 151:5eaa88a5bcc7 5553 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5554 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
<> 151:5eaa88a5bcc7 5555 #define USART_CR3_NACK_Pos (4U)
<> 151:5eaa88a5bcc7 5556 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5557 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
<> 151:5eaa88a5bcc7 5558 #define USART_CR3_SCEN_Pos (5U)
<> 151:5eaa88a5bcc7 5559 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5560 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
<> 151:5eaa88a5bcc7 5561 #define USART_CR3_DMAR_Pos (6U)
<> 151:5eaa88a5bcc7 5562 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5563 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
<> 151:5eaa88a5bcc7 5564 #define USART_CR3_DMAT_Pos (7U)
<> 151:5eaa88a5bcc7 5565 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 5566 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
<> 151:5eaa88a5bcc7 5567 #define USART_CR3_RTSE_Pos (8U)
<> 151:5eaa88a5bcc7 5568 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 5569 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
<> 151:5eaa88a5bcc7 5570 #define USART_CR3_CTSE_Pos (9U)
<> 151:5eaa88a5bcc7 5571 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5572 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
<> 151:5eaa88a5bcc7 5573 #define USART_CR3_CTSIE_Pos (10U)
<> 151:5eaa88a5bcc7 5574 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5575 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
<> 151:5eaa88a5bcc7 5576 #define USART_CR3_ONEBIT_Pos (11U)
<> 151:5eaa88a5bcc7 5577 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5578 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
<> 151:5eaa88a5bcc7 5579 #define USART_CR3_OVRDIS_Pos (12U)
<> 151:5eaa88a5bcc7 5580 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5581 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
<> 151:5eaa88a5bcc7 5582 #define USART_CR3_DDRE_Pos (13U)
<> 151:5eaa88a5bcc7 5583 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
<> 151:5eaa88a5bcc7 5584 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
<> 151:5eaa88a5bcc7 5585 #define USART_CR3_DEM_Pos (14U)
<> 151:5eaa88a5bcc7 5586 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 5587 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
<> 151:5eaa88a5bcc7 5588 #define USART_CR3_DEP_Pos (15U)
<> 151:5eaa88a5bcc7 5589 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 5590 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
<> 151:5eaa88a5bcc7 5591 #define USART_CR3_SCARCNT_Pos (17U)
<> 151:5eaa88a5bcc7 5592 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
<> 151:5eaa88a5bcc7 5593 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
<> 151:5eaa88a5bcc7 5594 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 5595 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 5596 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 5597 #define USART_CR3_WUS_Pos (20U)
<> 151:5eaa88a5bcc7 5598 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
<> 151:5eaa88a5bcc7 5599 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
<> 151:5eaa88a5bcc7 5600 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 5601 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 5602 #define USART_CR3_WUFIE_Pos (22U)
<> 151:5eaa88a5bcc7 5603 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 5604 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
<> 151:5eaa88a5bcc7 5605 #define USART_CR3_UCESM_Pos (23U)
<> 151:5eaa88a5bcc7 5606 #define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
<> 151:5eaa88a5bcc7 5607 #define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
mbed_official 114:fe4fe5cfc3a3 5608
mbed_official 114:fe4fe5cfc3a3 5609 /****************** Bit definition for USART_BRR register *******************/
<> 151:5eaa88a5bcc7 5610 #define USART_BRR_DIV_FRACTION_Pos (0U)
<> 151:5eaa88a5bcc7 5611 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
<> 151:5eaa88a5bcc7 5612 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
<> 151:5eaa88a5bcc7 5613 #define USART_BRR_DIV_MANTISSA_Pos (4U)
<> 151:5eaa88a5bcc7 5614 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
<> 151:5eaa88a5bcc7 5615 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
mbed_official 114:fe4fe5cfc3a3 5616
mbed_official 114:fe4fe5cfc3a3 5617 /****************** Bit definition for USART_GTPR register ******************/
<> 151:5eaa88a5bcc7 5618 #define USART_GTPR_PSC_Pos (0U)
<> 151:5eaa88a5bcc7 5619 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
<> 151:5eaa88a5bcc7 5620 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
<> 151:5eaa88a5bcc7 5621 #define USART_GTPR_GT_Pos (8U)
<> 151:5eaa88a5bcc7 5622 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
<> 151:5eaa88a5bcc7 5623 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
mbed_official 114:fe4fe5cfc3a3 5624
mbed_official 114:fe4fe5cfc3a3 5625
mbed_official 114:fe4fe5cfc3a3 5626 /******************* Bit definition for USART_RTOR register *****************/
<> 151:5eaa88a5bcc7 5627 #define USART_RTOR_RTO_Pos (0U)
<> 151:5eaa88a5bcc7 5628 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
<> 151:5eaa88a5bcc7 5629 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
<> 151:5eaa88a5bcc7 5630 #define USART_RTOR_BLEN_Pos (24U)
<> 151:5eaa88a5bcc7 5631 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
<> 151:5eaa88a5bcc7 5632 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
mbed_official 114:fe4fe5cfc3a3 5633
mbed_official 114:fe4fe5cfc3a3 5634 /******************* Bit definition for USART_RQR register ******************/
<> 151:5eaa88a5bcc7 5635 #define USART_RQR_ABRRQ_Pos (0U)
<> 151:5eaa88a5bcc7 5636 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5637 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
<> 151:5eaa88a5bcc7 5638 #define USART_RQR_SBKRQ_Pos (1U)
<> 151:5eaa88a5bcc7 5639 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5640 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
<> 151:5eaa88a5bcc7 5641 #define USART_RQR_MMRQ_Pos (2U)
<> 151:5eaa88a5bcc7 5642 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5643 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
<> 151:5eaa88a5bcc7 5644 #define USART_RQR_RXFRQ_Pos (3U)
<> 151:5eaa88a5bcc7 5645 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5646 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
<> 151:5eaa88a5bcc7 5647 #define USART_RQR_TXFRQ_Pos (4U)
<> 151:5eaa88a5bcc7 5648 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5649 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
mbed_official 114:fe4fe5cfc3a3 5650
mbed_official 114:fe4fe5cfc3a3 5651 /******************* Bit definition for USART_ISR register ******************/
<> 151:5eaa88a5bcc7 5652 #define USART_ISR_PE_Pos (0U)
<> 151:5eaa88a5bcc7 5653 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5654 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
<> 151:5eaa88a5bcc7 5655 #define USART_ISR_FE_Pos (1U)
<> 151:5eaa88a5bcc7 5656 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5657 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
<> 151:5eaa88a5bcc7 5658 #define USART_ISR_NE_Pos (2U)
<> 151:5eaa88a5bcc7 5659 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5660 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
<> 151:5eaa88a5bcc7 5661 #define USART_ISR_ORE_Pos (3U)
<> 151:5eaa88a5bcc7 5662 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5663 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
<> 151:5eaa88a5bcc7 5664 #define USART_ISR_IDLE_Pos (4U)
<> 151:5eaa88a5bcc7 5665 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5666 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
<> 151:5eaa88a5bcc7 5667 #define USART_ISR_RXNE_Pos (5U)
<> 151:5eaa88a5bcc7 5668 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5669 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
<> 151:5eaa88a5bcc7 5670 #define USART_ISR_TC_Pos (6U)
<> 151:5eaa88a5bcc7 5671 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5672 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
<> 151:5eaa88a5bcc7 5673 #define USART_ISR_TXE_Pos (7U)
<> 151:5eaa88a5bcc7 5674 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 5675 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
<> 151:5eaa88a5bcc7 5676 #define USART_ISR_LBDF_Pos (8U)
<> 151:5eaa88a5bcc7 5677 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 5678 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
<> 151:5eaa88a5bcc7 5679 #define USART_ISR_CTSIF_Pos (9U)
<> 151:5eaa88a5bcc7 5680 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5681 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
<> 151:5eaa88a5bcc7 5682 #define USART_ISR_CTS_Pos (10U)
<> 151:5eaa88a5bcc7 5683 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
<> 151:5eaa88a5bcc7 5684 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
<> 151:5eaa88a5bcc7 5685 #define USART_ISR_RTOF_Pos (11U)
<> 151:5eaa88a5bcc7 5686 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5687 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
<> 151:5eaa88a5bcc7 5688 #define USART_ISR_EOBF_Pos (12U)
<> 151:5eaa88a5bcc7 5689 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5690 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
<> 151:5eaa88a5bcc7 5691 #define USART_ISR_ABRE_Pos (14U)
<> 151:5eaa88a5bcc7 5692 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
<> 151:5eaa88a5bcc7 5693 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
<> 151:5eaa88a5bcc7 5694 #define USART_ISR_ABRF_Pos (15U)
<> 151:5eaa88a5bcc7 5695 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
<> 151:5eaa88a5bcc7 5696 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
<> 151:5eaa88a5bcc7 5697 #define USART_ISR_BUSY_Pos (16U)
<> 151:5eaa88a5bcc7 5698 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
<> 151:5eaa88a5bcc7 5699 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
<> 151:5eaa88a5bcc7 5700 #define USART_ISR_CMF_Pos (17U)
<> 151:5eaa88a5bcc7 5701 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 5702 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
<> 151:5eaa88a5bcc7 5703 #define USART_ISR_SBKF_Pos (18U)
<> 151:5eaa88a5bcc7 5704 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
<> 151:5eaa88a5bcc7 5705 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
<> 151:5eaa88a5bcc7 5706 #define USART_ISR_RWU_Pos (19U)
<> 151:5eaa88a5bcc7 5707 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
<> 151:5eaa88a5bcc7 5708 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
<> 151:5eaa88a5bcc7 5709 #define USART_ISR_WUF_Pos (20U)
<> 151:5eaa88a5bcc7 5710 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 5711 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
<> 151:5eaa88a5bcc7 5712 #define USART_ISR_TEACK_Pos (21U)
<> 151:5eaa88a5bcc7 5713 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
<> 151:5eaa88a5bcc7 5714 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
<> 151:5eaa88a5bcc7 5715 #define USART_ISR_REACK_Pos (22U)
<> 151:5eaa88a5bcc7 5716 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
<> 151:5eaa88a5bcc7 5717 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
mbed_official 114:fe4fe5cfc3a3 5718
mbed_official 114:fe4fe5cfc3a3 5719 /******************* Bit definition for USART_ICR register ******************/
<> 151:5eaa88a5bcc7 5720 #define USART_ICR_PECF_Pos (0U)
<> 151:5eaa88a5bcc7 5721 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5722 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
<> 151:5eaa88a5bcc7 5723 #define USART_ICR_FECF_Pos (1U)
<> 151:5eaa88a5bcc7 5724 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5725 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
<> 151:5eaa88a5bcc7 5726 #define USART_ICR_NCF_Pos (2U)
<> 151:5eaa88a5bcc7 5727 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5728 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
<> 151:5eaa88a5bcc7 5729 #define USART_ICR_ORECF_Pos (3U)
<> 151:5eaa88a5bcc7 5730 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5731 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
<> 151:5eaa88a5bcc7 5732 #define USART_ICR_IDLECF_Pos (4U)
<> 151:5eaa88a5bcc7 5733 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5734 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
<> 151:5eaa88a5bcc7 5735 #define USART_ICR_TCCF_Pos (6U)
<> 151:5eaa88a5bcc7 5736 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
<> 151:5eaa88a5bcc7 5737 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
<> 151:5eaa88a5bcc7 5738 #define USART_ICR_LBDCF_Pos (8U)
<> 151:5eaa88a5bcc7 5739 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
<> 151:5eaa88a5bcc7 5740 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
<> 151:5eaa88a5bcc7 5741 #define USART_ICR_CTSCF_Pos (9U)
<> 151:5eaa88a5bcc7 5742 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5743 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
<> 151:5eaa88a5bcc7 5744 #define USART_ICR_RTOCF_Pos (11U)
<> 151:5eaa88a5bcc7 5745 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
<> 151:5eaa88a5bcc7 5746 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
<> 151:5eaa88a5bcc7 5747 #define USART_ICR_EOBCF_Pos (12U)
<> 151:5eaa88a5bcc7 5748 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
<> 151:5eaa88a5bcc7 5749 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
<> 151:5eaa88a5bcc7 5750 #define USART_ICR_CMCF_Pos (17U)
<> 151:5eaa88a5bcc7 5751 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
<> 151:5eaa88a5bcc7 5752 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
<> 151:5eaa88a5bcc7 5753 #define USART_ICR_WUCF_Pos (20U)
<> 151:5eaa88a5bcc7 5754 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
<> 151:5eaa88a5bcc7 5755 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
mbed_official 114:fe4fe5cfc3a3 5756
mbed_official 114:fe4fe5cfc3a3 5757 /******************* Bit definition for USART_RDR register ******************/
<> 151:5eaa88a5bcc7 5758 #define USART_RDR_RDR_Pos (0U)
<> 151:5eaa88a5bcc7 5759 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
<> 151:5eaa88a5bcc7 5760 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 114:fe4fe5cfc3a3 5761
mbed_official 114:fe4fe5cfc3a3 5762 /******************* Bit definition for USART_TDR register ******************/
<> 151:5eaa88a5bcc7 5763 #define USART_TDR_TDR_Pos (0U)
<> 151:5eaa88a5bcc7 5764 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
<> 151:5eaa88a5bcc7 5765 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 114:fe4fe5cfc3a3 5766
mbed_official 114:fe4fe5cfc3a3 5767 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 5768 /* */
mbed_official 114:fe4fe5cfc3a3 5769 /* Window WATCHDOG (WWDG) */
mbed_official 114:fe4fe5cfc3a3 5770 /* */
mbed_official 114:fe4fe5cfc3a3 5771 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 5772
mbed_official 114:fe4fe5cfc3a3 5773 /******************* Bit definition for WWDG_CR register ********************/
<> 151:5eaa88a5bcc7 5774 #define WWDG_CR_T_Pos (0U)
<> 151:5eaa88a5bcc7 5775 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
<> 151:5eaa88a5bcc7 5776 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 151:5eaa88a5bcc7 5777 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5778 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5779 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5780 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5781 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5782 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5783 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
mbed_official 114:fe4fe5cfc3a3 5784
mbed_official 114:fe4fe5cfc3a3 5785 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 5786 #define WWDG_CR_T0 WWDG_CR_T_0
mbed_official 114:fe4fe5cfc3a3 5787 #define WWDG_CR_T1 WWDG_CR_T_1
mbed_official 114:fe4fe5cfc3a3 5788 #define WWDG_CR_T2 WWDG_CR_T_2
mbed_official 114:fe4fe5cfc3a3 5789 #define WWDG_CR_T3 WWDG_CR_T_3
mbed_official 114:fe4fe5cfc3a3 5790 #define WWDG_CR_T4 WWDG_CR_T_4
mbed_official 114:fe4fe5cfc3a3 5791 #define WWDG_CR_T5 WWDG_CR_T_5
mbed_official 114:fe4fe5cfc3a3 5792 #define WWDG_CR_T6 WWDG_CR_T_6
mbed_official 114:fe4fe5cfc3a3 5793
<> 151:5eaa88a5bcc7 5794 #define WWDG_CR_WDGA_Pos (7U)
<> 151:5eaa88a5bcc7 5795 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 5796 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
mbed_official 114:fe4fe5cfc3a3 5797
mbed_official 114:fe4fe5cfc3a3 5798 /******************* Bit definition for WWDG_CFR register *******************/
<> 151:5eaa88a5bcc7 5799 #define WWDG_CFR_W_Pos (0U)
<> 151:5eaa88a5bcc7 5800 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
<> 151:5eaa88a5bcc7 5801 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
<> 151:5eaa88a5bcc7 5802 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5803 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
<> 151:5eaa88a5bcc7 5804 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
<> 151:5eaa88a5bcc7 5805 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
<> 151:5eaa88a5bcc7 5806 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
<> 151:5eaa88a5bcc7 5807 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
<> 151:5eaa88a5bcc7 5808 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
mbed_official 114:fe4fe5cfc3a3 5809
mbed_official 114:fe4fe5cfc3a3 5810 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 5811 #define WWDG_CFR_W0 WWDG_CFR_W_0
mbed_official 114:fe4fe5cfc3a3 5812 #define WWDG_CFR_W1 WWDG_CFR_W_1
mbed_official 114:fe4fe5cfc3a3 5813 #define WWDG_CFR_W2 WWDG_CFR_W_2
mbed_official 114:fe4fe5cfc3a3 5814 #define WWDG_CFR_W3 WWDG_CFR_W_3
mbed_official 114:fe4fe5cfc3a3 5815 #define WWDG_CFR_W4 WWDG_CFR_W_4
mbed_official 114:fe4fe5cfc3a3 5816 #define WWDG_CFR_W5 WWDG_CFR_W_5
mbed_official 114:fe4fe5cfc3a3 5817 #define WWDG_CFR_W6 WWDG_CFR_W_6
mbed_official 114:fe4fe5cfc3a3 5818
<> 151:5eaa88a5bcc7 5819 #define WWDG_CFR_WDGTB_Pos (7U)
<> 151:5eaa88a5bcc7 5820 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
<> 151:5eaa88a5bcc7 5821 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
<> 151:5eaa88a5bcc7 5822 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
<> 151:5eaa88a5bcc7 5823 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
mbed_official 114:fe4fe5cfc3a3 5824
mbed_official 114:fe4fe5cfc3a3 5825 /* Legacy defines */
mbed_official 114:fe4fe5cfc3a3 5826 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
mbed_official 114:fe4fe5cfc3a3 5827 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
mbed_official 114:fe4fe5cfc3a3 5828
<> 151:5eaa88a5bcc7 5829 #define WWDG_CFR_EWI_Pos (9U)
<> 151:5eaa88a5bcc7 5830 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
<> 151:5eaa88a5bcc7 5831 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
mbed_official 114:fe4fe5cfc3a3 5832
mbed_official 114:fe4fe5cfc3a3 5833 /******************* Bit definition for WWDG_SR register ********************/
<> 151:5eaa88a5bcc7 5834 #define WWDG_SR_EWIF_Pos (0U)
<> 151:5eaa88a5bcc7 5835 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
<> 151:5eaa88a5bcc7 5836 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
mbed_official 114:fe4fe5cfc3a3 5837
mbed_official 114:fe4fe5cfc3a3 5838 /**
mbed_official 114:fe4fe5cfc3a3 5839 * @}
mbed_official 114:fe4fe5cfc3a3 5840 */
mbed_official 114:fe4fe5cfc3a3 5841
mbed_official 114:fe4fe5cfc3a3 5842 /**
mbed_official 114:fe4fe5cfc3a3 5843 * @}
mbed_official 114:fe4fe5cfc3a3 5844 */
mbed_official 114:fe4fe5cfc3a3 5845
mbed_official 114:fe4fe5cfc3a3 5846 /** @addtogroup Exported_macros
mbed_official 114:fe4fe5cfc3a3 5847 * @{
mbed_official 114:fe4fe5cfc3a3 5848 */
mbed_official 114:fe4fe5cfc3a3 5849
mbed_official 114:fe4fe5cfc3a3 5850 /******************************* ADC Instances ********************************/
mbed_official 114:fe4fe5cfc3a3 5851 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
<> 151:5eaa88a5bcc7 5852 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
mbed_official 114:fe4fe5cfc3a3 5853
mbed_official 114:fe4fe5cfc3a3 5854 /******************************* COMP Instances *******************************/
mbed_official 114:fe4fe5cfc3a3 5855 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
mbed_official 114:fe4fe5cfc3a3 5856 ((INSTANCE) == COMP2))
mbed_official 114:fe4fe5cfc3a3 5857
Anna Bridge 186:707f6e361f3e 5858 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
mbed_official 114:fe4fe5cfc3a3 5859
mbed_official 114:fe4fe5cfc3a3 5860 /******************************* CRC Instances ********************************/
mbed_official 114:fe4fe5cfc3a3 5861 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 114:fe4fe5cfc3a3 5862
mbed_official 114:fe4fe5cfc3a3 5863 /******************************* DMA Instances *********************************/
<> 151:5eaa88a5bcc7 5864 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
<> 151:5eaa88a5bcc7 5865 ((INSTANCE) == DMA1_Channel2) || \
<> 151:5eaa88a5bcc7 5866 ((INSTANCE) == DMA1_Channel3) || \
<> 151:5eaa88a5bcc7 5867 ((INSTANCE) == DMA1_Channel4) || \
<> 151:5eaa88a5bcc7 5868 ((INSTANCE) == DMA1_Channel5) || \
<> 151:5eaa88a5bcc7 5869 ((INSTANCE) == DMA1_Channel6) || \
<> 151:5eaa88a5bcc7 5870 ((INSTANCE) == DMA1_Channel7))
mbed_official 114:fe4fe5cfc3a3 5871
mbed_official 114:fe4fe5cfc3a3 5872 /******************************* GPIO Instances *******************************/
mbed_official 114:fe4fe5cfc3a3 5873 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 114:fe4fe5cfc3a3 5874 ((INSTANCE) == GPIOB) || \
mbed_official 114:fe4fe5cfc3a3 5875 ((INSTANCE) == GPIOC) || \
mbed_official 114:fe4fe5cfc3a3 5876 ((INSTANCE) == GPIOH))
mbed_official 114:fe4fe5cfc3a3 5877
mbed_official 114:fe4fe5cfc3a3 5878 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 114:fe4fe5cfc3a3 5879 ((INSTANCE) == GPIOB) || \
mbed_official 114:fe4fe5cfc3a3 5880 ((INSTANCE) == GPIOC))
mbed_official 114:fe4fe5cfc3a3 5881
mbed_official 114:fe4fe5cfc3a3 5882 /******************************** I2C Instances *******************************/
mbed_official 114:fe4fe5cfc3a3 5883 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official 114:fe4fe5cfc3a3 5884
<> 151:5eaa88a5bcc7 5885 /****************** I2C Instances : wakeup capability from stop modes *********/
<> 151:5eaa88a5bcc7 5886 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
<> 151:5eaa88a5bcc7 5887
<> 151:5eaa88a5bcc7 5888
mbed_official 114:fe4fe5cfc3a3 5889
mbed_official 114:fe4fe5cfc3a3 5890
mbed_official 114:fe4fe5cfc3a3 5891 /****************************** RTC Instances *********************************/
mbed_official 114:fe4fe5cfc3a3 5892 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 114:fe4fe5cfc3a3 5893
mbed_official 114:fe4fe5cfc3a3 5894 /******************************** SMBUS Instances *****************************/
mbed_official 114:fe4fe5cfc3a3 5895 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official 114:fe4fe5cfc3a3 5896
mbed_official 114:fe4fe5cfc3a3 5897 /******************************** SPI Instances *******************************/
mbed_official 114:fe4fe5cfc3a3 5898 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
mbed_official 114:fe4fe5cfc3a3 5899
mbed_official 114:fe4fe5cfc3a3 5900 /****************** LPTIM Instances : All supported instances *****************/
mbed_official 114:fe4fe5cfc3a3 5901 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
mbed_official 114:fe4fe5cfc3a3 5902
mbed_official 114:fe4fe5cfc3a3 5903 /****************** TIM Instances : All supported instances *******************/
mbed_official 114:fe4fe5cfc3a3 5904 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5905 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5906 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5907
mbed_official 114:fe4fe5cfc3a3 5908 /****************** TIM Instances : supporting counting mode selection ********/
mbed_official 114:fe4fe5cfc3a3 5909 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5910 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5911 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5912
mbed_official 114:fe4fe5cfc3a3 5913 /****************** TIM Instances : supporting clock division *****************/
mbed_official 114:fe4fe5cfc3a3 5914 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5915 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5916 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5917
mbed_official 114:fe4fe5cfc3a3 5918 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
mbed_official 114:fe4fe5cfc3a3 5919 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5920 ((INSTANCE) == TIM21))
mbed_official 114:fe4fe5cfc3a3 5921
mbed_official 114:fe4fe5cfc3a3 5922 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
mbed_official 114:fe4fe5cfc3a3 5923
mbed_official 114:fe4fe5cfc3a3 5924 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
mbed_official 114:fe4fe5cfc3a3 5925 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5926 ((INSTANCE) == TIM21))
mbed_official 114:fe4fe5cfc3a3 5927
mbed_official 114:fe4fe5cfc3a3 5928 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
mbed_official 114:fe4fe5cfc3a3 5929 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5930 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5931 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5932
mbed_official 114:fe4fe5cfc3a3 5933 /************* TIM Instances : at least 1 capture/compare channel *************/
mbed_official 114:fe4fe5cfc3a3 5934 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5935 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5936 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5937
mbed_official 114:fe4fe5cfc3a3 5938 /************ TIM Instances : at least 2 capture/compare channels *************/
mbed_official 114:fe4fe5cfc3a3 5939 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5940 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5941 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5942
mbed_official 114:fe4fe5cfc3a3 5943 /************ TIM Instances : at least 3 capture/compare channels *************/
mbed_official 114:fe4fe5cfc3a3 5944 #define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official 114:fe4fe5cfc3a3 5945
mbed_official 114:fe4fe5cfc3a3 5946 /************ TIM Instances : at least 4 capture/compare channels *************/
mbed_official 114:fe4fe5cfc3a3 5947 #define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official 114:fe4fe5cfc3a3 5948
mbed_official 114:fe4fe5cfc3a3 5949 /******************** TIM Instances : Advanced-control timers *****************/
mbed_official 114:fe4fe5cfc3a3 5950
mbed_official 114:fe4fe5cfc3a3 5951 /******************* TIM Instances : Timer input XOR function *****************/
mbed_official 114:fe4fe5cfc3a3 5952 #define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official 114:fe4fe5cfc3a3 5953
mbed_official 114:fe4fe5cfc3a3 5954 /****************** TIM Instances : DMA requests generation (UDE) *************/
mbed_official 114:fe4fe5cfc3a3 5955 #define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official 114:fe4fe5cfc3a3 5956
mbed_official 114:fe4fe5cfc3a3 5957 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
mbed_official 114:fe4fe5cfc3a3 5958 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official 114:fe4fe5cfc3a3 5959
mbed_official 114:fe4fe5cfc3a3 5960 /************ TIM Instances : DMA requests generation (COMDE) *****************/
mbed_official 114:fe4fe5cfc3a3 5961 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official 114:fe4fe5cfc3a3 5962
mbed_official 114:fe4fe5cfc3a3 5963 /******************** TIM Instances : DMA burst feature ***********************/
mbed_official 114:fe4fe5cfc3a3 5964 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official 114:fe4fe5cfc3a3 5965
mbed_official 114:fe4fe5cfc3a3 5966 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
mbed_official 114:fe4fe5cfc3a3 5967 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5968 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5969 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5970
mbed_official 114:fe4fe5cfc3a3 5971 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
mbed_official 114:fe4fe5cfc3a3 5972 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5973 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5974 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5975
mbed_official 114:fe4fe5cfc3a3 5976 /********************** TIM Instances : 32 bit Counter ************************/
mbed_official 114:fe4fe5cfc3a3 5977
mbed_official 114:fe4fe5cfc3a3 5978 /***************** TIM Instances : external trigger input availabe ************/
mbed_official 114:fe4fe5cfc3a3 5979 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5980 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5981 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5982
mbed_official 114:fe4fe5cfc3a3 5983 /****************** TIM Instances : remapping capability **********************/
mbed_official 114:fe4fe5cfc3a3 5984 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5985 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5986 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5987
mbed_official 114:fe4fe5cfc3a3 5988 /****************** TIM Instances : supporting encoder interface **************/
mbed_official 114:fe4fe5cfc3a3 5989 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 114:fe4fe5cfc3a3 5990 ((INSTANCE) == TIM21) || \
mbed_official 114:fe4fe5cfc3a3 5991 ((INSTANCE) == TIM22))
mbed_official 114:fe4fe5cfc3a3 5992
mbed_official 114:fe4fe5cfc3a3 5993 /******************* TIM Instances : output(s) OCXEC register *****************/
mbed_official 114:fe4fe5cfc3a3 5994 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official 114:fe4fe5cfc3a3 5995
mbed_official 114:fe4fe5cfc3a3 5996 /******************* TIM Instances : output(s) available **********************/
mbed_official 114:fe4fe5cfc3a3 5997 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 114:fe4fe5cfc3a3 5998 ((((INSTANCE) == TIM2) && \
mbed_official 114:fe4fe5cfc3a3 5999 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 114:fe4fe5cfc3a3 6000 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 114:fe4fe5cfc3a3 6001 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 114:fe4fe5cfc3a3 6002 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 114:fe4fe5cfc3a3 6003 || \
mbed_official 114:fe4fe5cfc3a3 6004 (((INSTANCE) == TIM21) && \
mbed_official 114:fe4fe5cfc3a3 6005 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 114:fe4fe5cfc3a3 6006 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 114:fe4fe5cfc3a3 6007 || \
mbed_official 114:fe4fe5cfc3a3 6008 (((INSTANCE) == TIM22) && \
mbed_official 114:fe4fe5cfc3a3 6009 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 114:fe4fe5cfc3a3 6010 ((CHANNEL) == TIM_CHANNEL_2))))
mbed_official 114:fe4fe5cfc3a3 6011
mbed_official 114:fe4fe5cfc3a3 6012 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 114:fe4fe5cfc3a3 6013 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
mbed_official 114:fe4fe5cfc3a3 6014 ((INSTANCE) == LPUART1))
mbed_official 114:fe4fe5cfc3a3 6015
mbed_official 114:fe4fe5cfc3a3 6016 /******************** USART Instances : Synchronous mode **********************/
mbed_official 114:fe4fe5cfc3a3 6017 #define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
mbed_official 114:fe4fe5cfc3a3 6018
mbed_official 114:fe4fe5cfc3a3 6019 /****************** USART Instances : Auto Baud Rate detection ****************/
mbed_official 114:fe4fe5cfc3a3 6020
mbed_official 114:fe4fe5cfc3a3 6021 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
mbed_official 114:fe4fe5cfc3a3 6022
mbed_official 114:fe4fe5cfc3a3 6023 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 114:fe4fe5cfc3a3 6024 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
mbed_official 114:fe4fe5cfc3a3 6025 ((INSTANCE) == LPUART1))
mbed_official 114:fe4fe5cfc3a3 6026
mbed_official 114:fe4fe5cfc3a3 6027 /******************** UART Instances : LIN mode **********************/
mbed_official 114:fe4fe5cfc3a3 6028 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
mbed_official 114:fe4fe5cfc3a3 6029
mbed_official 114:fe4fe5cfc3a3 6030 /******************** UART Instances : Wake-up from Stop mode **********************/
mbed_official 114:fe4fe5cfc3a3 6031 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
mbed_official 114:fe4fe5cfc3a3 6032 ((INSTANCE) == LPUART1))
mbed_official 114:fe4fe5cfc3a3 6033 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 114:fe4fe5cfc3a3 6034 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
mbed_official 114:fe4fe5cfc3a3 6035 ((INSTANCE) == LPUART1))
mbed_official 114:fe4fe5cfc3a3 6036
mbed_official 114:fe4fe5cfc3a3 6037 /********************* UART Instances : Smard card mode ***********************/
mbed_official 114:fe4fe5cfc3a3 6038 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
mbed_official 114:fe4fe5cfc3a3 6039
mbed_official 114:fe4fe5cfc3a3 6040 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 114:fe4fe5cfc3a3 6041 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
mbed_official 114:fe4fe5cfc3a3 6042
<> 151:5eaa88a5bcc7 6043 /******************** LPUART Instance *****************************************/
<> 151:5eaa88a5bcc7 6044 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
<> 151:5eaa88a5bcc7 6045
mbed_official 114:fe4fe5cfc3a3 6046 /****************************** IWDG Instances ********************************/
mbed_official 114:fe4fe5cfc3a3 6047 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 114:fe4fe5cfc3a3 6048
mbed_official 114:fe4fe5cfc3a3 6049 /****************************** WWDG Instances ********************************/
mbed_official 114:fe4fe5cfc3a3 6050 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 114:fe4fe5cfc3a3 6051
mbed_official 114:fe4fe5cfc3a3 6052 /**
mbed_official 114:fe4fe5cfc3a3 6053 * @}
mbed_official 114:fe4fe5cfc3a3 6054 */
mbed_official 114:fe4fe5cfc3a3 6055
mbed_official 114:fe4fe5cfc3a3 6056 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 6057 /* For a painless codes migration between the STM32L0xx device product */
mbed_official 114:fe4fe5cfc3a3 6058 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 114:fe4fe5cfc3a3 6059 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 114:fe4fe5cfc3a3 6060 /* No need to update developed interrupt code when moving across */
mbed_official 114:fe4fe5cfc3a3 6061 /* product lines within the same STM32L0 Family */
mbed_official 114:fe4fe5cfc3a3 6062 /******************************************************************************/
mbed_official 114:fe4fe5cfc3a3 6063
mbed_official 114:fe4fe5cfc3a3 6064 /* Aliases for __IRQn */
mbed_official 114:fe4fe5cfc3a3 6065
mbed_official 114:fe4fe5cfc3a3 6066 #define RNG_LPUART1_IRQn LPUART1_IRQn
mbed_official 114:fe4fe5cfc3a3 6067 #define AES_LPUART1_IRQn LPUART1_IRQn
mbed_official 114:fe4fe5cfc3a3 6068 #define AES_RNG_LPUART1_IRQn LPUART1_IRQn
mbed_official 114:fe4fe5cfc3a3 6069 #define RCC_CRS_IRQn RCC_IRQn
mbed_official 114:fe4fe5cfc3a3 6070
mbed_official 114:fe4fe5cfc3a3 6071 /* Aliases for __IRQHandler */
mbed_official 114:fe4fe5cfc3a3 6072 #define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
mbed_official 114:fe4fe5cfc3a3 6073 #define AES_LPUART1_IRQHandler LPUART1_IRQHandler
mbed_official 114:fe4fe5cfc3a3 6074 #define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
mbed_official 114:fe4fe5cfc3a3 6075 #define TIM6_DAC_IRQHandler TIM6_IRQHandler
mbed_official 114:fe4fe5cfc3a3 6076 #define RCC_CRS_IRQHandler RCC_IRQHandler
mbed_official 114:fe4fe5cfc3a3 6077
mbed_official 114:fe4fe5cfc3a3 6078 /**
mbed_official 114:fe4fe5cfc3a3 6079 * @}
mbed_official 114:fe4fe5cfc3a3 6080 */
mbed_official 114:fe4fe5cfc3a3 6081
mbed_official 114:fe4fe5cfc3a3 6082 /**
mbed_official 114:fe4fe5cfc3a3 6083 * @}
mbed_official 114:fe4fe5cfc3a3 6084 */
mbed_official 114:fe4fe5cfc3a3 6085
mbed_official 114:fe4fe5cfc3a3 6086 #ifdef __cplusplus
mbed_official 114:fe4fe5cfc3a3 6087 }
mbed_official 114:fe4fe5cfc3a3 6088 #endif /* __cplusplus */
mbed_official 114:fe4fe5cfc3a3 6089
mbed_official 114:fe4fe5cfc3a3 6090 #endif /* __STM32L031xx_H */
mbed_official 114:fe4fe5cfc3a3 6091
mbed_official 114:fe4fe5cfc3a3 6092
mbed_official 114:fe4fe5cfc3a3 6093
mbed_official 114:fe4fe5cfc3a3 6094 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/