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targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_utils.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32h7xx_ll_utils.c |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief UTILS LL module driver. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
| AnnaBridge | 189:f392fc9709a3 | 10 | * All rights reserved.</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 11 | * |
| AnnaBridge | 189:f392fc9709a3 | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| AnnaBridge | 189:f392fc9709a3 | 13 | * the "License"; You may not use this file except in compliance with the |
| AnnaBridge | 189:f392fc9709a3 | 14 | * License. You may obtain a copy of the License at: |
| AnnaBridge | 189:f392fc9709a3 | 15 | * opensource.org/licenses/BSD-3-Clause |
| AnnaBridge | 189:f392fc9709a3 | 16 | * |
| AnnaBridge | 189:f392fc9709a3 | 17 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 18 | */ |
| AnnaBridge | 189:f392fc9709a3 | 19 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 20 | #include "stm32h7xx_ll_utils.h" |
| AnnaBridge | 189:f392fc9709a3 | 21 | #include "stm32h7xx_ll_rcc.h" |
| AnnaBridge | 189:f392fc9709a3 | 22 | #include "stm32h7xx_ll_pwr.h" |
| AnnaBridge | 189:f392fc9709a3 | 23 | |
| AnnaBridge | 189:f392fc9709a3 | 24 | #ifdef USE_FULL_ASSERT |
| AnnaBridge | 189:f392fc9709a3 | 25 | #include "stm32_assert.h" |
| AnnaBridge | 189:f392fc9709a3 | 26 | #else |
| AnnaBridge | 189:f392fc9709a3 | 27 | #define assert_param(expr) ((void)0U) |
| AnnaBridge | 189:f392fc9709a3 | 28 | #endif /* USE_FULL_ASSERT */ |
| AnnaBridge | 189:f392fc9709a3 | 29 | |
| AnnaBridge | 189:f392fc9709a3 | 30 | /** @addtogroup STM32H7xx_LL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 31 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 32 | */ |
| AnnaBridge | 189:f392fc9709a3 | 33 | |
| AnnaBridge | 189:f392fc9709a3 | 34 | /** @addtogroup UTILS_LL |
| AnnaBridge | 189:f392fc9709a3 | 35 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 36 | */ |
| AnnaBridge | 189:f392fc9709a3 | 37 | |
| AnnaBridge | 189:f392fc9709a3 | 38 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 39 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 40 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 41 | /** @addtogroup UTILS_LL_Private_Constants |
| AnnaBridge | 189:f392fc9709a3 | 42 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 43 | */ |
| AnnaBridge | 189:f392fc9709a3 | 44 | #define UTILS_MAX_FREQUENCY_SCALE1 400000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #define UTILS_MAX_FREQUENCY_SCALE2 300000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 46 | #define UTILS_MAX_FREQUENCY_SCALE3 200000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 47 | |
| AnnaBridge | 189:f392fc9709a3 | 48 | /* Defines used for PLL range */ |
| AnnaBridge | 189:f392fc9709a3 | 49 | #define UTILS_PLLVCO_INPUT_MIN1 1000000U /*!< Frequency min for the low range PLLVCO input, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | #define UTILS_PLLVCO_INPUT_MAX1 2000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 51 | #define UTILS_PLLVCO_INPUT_MIN2 2000000U /*!< Frequency min for the low range PLLVCO input, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 52 | #define UTILS_PLLVCO_INPUT_MAX2 4000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 53 | #define UTILS_PLLVCO_INPUT_MIN3 4000000U /*!< Frequency min for the low range PLLVCO input, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 54 | #define UTILS_PLLVCO_INPUT_MAX3 8000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 55 | #define UTILS_PLLVCO_INPUT_MIN4 8000000U /*!< Frequency min for the low range PLLVCO input, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 56 | #define UTILS_PLLVCO_INPUT_MAX4 16000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 57 | |
| AnnaBridge | 189:f392fc9709a3 | 58 | #define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U /*!< Frequency min for the medium range PLLVCO output, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 59 | #define UTILS_PLLVCO_WIDE_OUTPUT_MIN 192000000U /*!< Frequency min for the wide range PLLVCO output, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 60 | #define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U /*!< Frequency max for the wide range PLLVCO output, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 61 | #define UTILS_PLLVCO_WIDE_OUTPUT_MAX 836000000U /*!< Frequency max for the wide range PLLVCO output, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 62 | |
| AnnaBridge | 189:f392fc9709a3 | 63 | /* Defines used for HSE range */ |
| AnnaBridge | 189:f392fc9709a3 | 64 | #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 65 | #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 66 | |
| AnnaBridge | 189:f392fc9709a3 | 67 | /* Defines used for FLASH latency according to HCLK Frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | #define UTILS_SCALE1_LATENCY0_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 69 | #define UTILS_SCALE1_LATENCY1_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 70 | #define UTILS_SCALE1_LATENCY2_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | |
| AnnaBridge | 189:f392fc9709a3 | 72 | #define UTILS_SCALE2_LATENCY0_FREQ 55000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | #define UTILS_SCALE2_LATENCY1_FREQ 110000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 74 | #define UTILS_SCALE2_LATENCY2_FREQ 165000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 75 | #define UTILS_SCALE2_LATENCY3_FREQ 220000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ |
| AnnaBridge | 189:f392fc9709a3 | 76 | |
| AnnaBridge | 189:f392fc9709a3 | 77 | #define UTILS_SCALE3_LATENCY0_FREQ 45000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 78 | #define UTILS_SCALE3_LATENCY1_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 79 | #define UTILS_SCALE3_LATENCY2_FREQ 135000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 80 | #define UTILS_SCALE3_LATENCY3_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 81 | #define UTILS_SCALE3_LATENCY4_FREQ 225000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 82 | /** |
| AnnaBridge | 189:f392fc9709a3 | 83 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 84 | */ |
| AnnaBridge | 189:f392fc9709a3 | 85 | |
| AnnaBridge | 189:f392fc9709a3 | 86 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 87 | /** @addtogroup UTILS_LL_Private_Macros |
| AnnaBridge | 189:f392fc9709a3 | 88 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 89 | */ |
| AnnaBridge | 189:f392fc9709a3 | 90 | #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ |
| AnnaBridge | 189:f392fc9709a3 | 91 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ |
| AnnaBridge | 189:f392fc9709a3 | 92 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ |
| AnnaBridge | 189:f392fc9709a3 | 93 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ |
| AnnaBridge | 189:f392fc9709a3 | 94 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ |
| AnnaBridge | 189:f392fc9709a3 | 95 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ |
| AnnaBridge | 189:f392fc9709a3 | 96 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ |
| AnnaBridge | 189:f392fc9709a3 | 97 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ |
| AnnaBridge | 189:f392fc9709a3 | 98 | || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) |
| AnnaBridge | 189:f392fc9709a3 | 99 | |
| AnnaBridge | 189:f392fc9709a3 | 100 | #define IS_LL_UTILS_AHB_DIV(__VALUE__) (((__VALUE__) == LL_RCC_AHB_DIV_1) \ |
| AnnaBridge | 189:f392fc9709a3 | 101 | || ((__VALUE__) == LL_RCC_AHB_DIV_2) \ |
| AnnaBridge | 189:f392fc9709a3 | 102 | || ((__VALUE__) == LL_RCC_AHB_DIV_4) \ |
| AnnaBridge | 189:f392fc9709a3 | 103 | || ((__VALUE__) == LL_RCC_AHB_DIV_8) \ |
| AnnaBridge | 189:f392fc9709a3 | 104 | || ((__VALUE__) == LL_RCC_AHB_DIV_16) \ |
| AnnaBridge | 189:f392fc9709a3 | 105 | || ((__VALUE__) == LL_RCC_AHB_DIV_64) \ |
| AnnaBridge | 189:f392fc9709a3 | 106 | || ((__VALUE__) == LL_RCC_AHB_DIV_128) \ |
| AnnaBridge | 189:f392fc9709a3 | 107 | || ((__VALUE__) == LL_RCC_AHB_DIV_256) \ |
| AnnaBridge | 189:f392fc9709a3 | 108 | || ((__VALUE__) == LL_RCC_AHB_DIV_512)) |
| AnnaBridge | 189:f392fc9709a3 | 109 | |
| AnnaBridge | 189:f392fc9709a3 | 110 | #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ |
| AnnaBridge | 189:f392fc9709a3 | 111 | || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ |
| AnnaBridge | 189:f392fc9709a3 | 112 | || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ |
| AnnaBridge | 189:f392fc9709a3 | 113 | || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ |
| AnnaBridge | 189:f392fc9709a3 | 114 | || ((__VALUE__) == LL_RCC_APB1_DIV_16)) |
| AnnaBridge | 189:f392fc9709a3 | 115 | |
| AnnaBridge | 189:f392fc9709a3 | 116 | #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ |
| AnnaBridge | 189:f392fc9709a3 | 117 | || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ |
| AnnaBridge | 189:f392fc9709a3 | 118 | || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ |
| AnnaBridge | 189:f392fc9709a3 | 119 | || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ |
| AnnaBridge | 189:f392fc9709a3 | 120 | || ((__VALUE__) == LL_RCC_APB2_DIV_16)) |
| AnnaBridge | 189:f392fc9709a3 | 121 | |
| AnnaBridge | 189:f392fc9709a3 | 122 | #define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \ |
| AnnaBridge | 189:f392fc9709a3 | 123 | || ((__VALUE__) == LL_RCC_APB3_DIV_2) \ |
| AnnaBridge | 189:f392fc9709a3 | 124 | || ((__VALUE__) == LL_RCC_APB3_DIV_4) \ |
| AnnaBridge | 189:f392fc9709a3 | 125 | || ((__VALUE__) == LL_RCC_APB3_DIV_8) \ |
| AnnaBridge | 189:f392fc9709a3 | 126 | || ((__VALUE__) == LL_RCC_APB3_DIV_16)) |
| AnnaBridge | 189:f392fc9709a3 | 127 | |
| AnnaBridge | 189:f392fc9709a3 | 128 | #define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \ |
| AnnaBridge | 189:f392fc9709a3 | 129 | || ((__VALUE__) == LL_RCC_APB4_DIV_2) \ |
| AnnaBridge | 189:f392fc9709a3 | 130 | || ((__VALUE__) == LL_RCC_APB4_DIV_4) \ |
| AnnaBridge | 189:f392fc9709a3 | 131 | || ((__VALUE__) == LL_RCC_APB4_DIV_8) \ |
| AnnaBridge | 189:f392fc9709a3 | 132 | || ((__VALUE__) == LL_RCC_APB4_DIV_16)) |
| AnnaBridge | 189:f392fc9709a3 | 133 | |
| AnnaBridge | 189:f392fc9709a3 | 134 | #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U)) |
| AnnaBridge | 189:f392fc9709a3 | 135 | |
| AnnaBridge | 189:f392fc9709a3 | 136 | #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U)) |
| AnnaBridge | 189:f392fc9709a3 | 137 | |
| AnnaBridge | 189:f392fc9709a3 | 138 | #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) |
| AnnaBridge | 189:f392fc9709a3 | 139 | |
| AnnaBridge | 189:f392fc9709a3 | 140 | #define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU) |
| AnnaBridge | 189:f392fc9709a3 | 141 | |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__) ( \ |
| AnnaBridge | 189:f392fc9709a3 | 143 | (((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \ |
| AnnaBridge | 189:f392fc9709a3 | 144 | (((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \ |
| AnnaBridge | 189:f392fc9709a3 | 145 | (((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \ |
| AnnaBridge | 189:f392fc9709a3 | 146 | (((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4))) |
| AnnaBridge | 189:f392fc9709a3 | 147 | |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) ( \ |
| AnnaBridge | 189:f392fc9709a3 | 149 | (((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \ |
| AnnaBridge | 189:f392fc9709a3 | 150 | (((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX))) |
| AnnaBridge | 189:f392fc9709a3 | 151 | |
| AnnaBridge | 189:f392fc9709a3 | 152 | #define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) ( \ |
| AnnaBridge | 189:f392fc9709a3 | 153 | (((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \ |
| AnnaBridge | 189:f392fc9709a3 | 154 | (((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE))) |
| AnnaBridge | 189:f392fc9709a3 | 155 | |
| AnnaBridge | 189:f392fc9709a3 | 156 | #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ |
| AnnaBridge | 189:f392fc9709a3 | 157 | (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ |
| AnnaBridge | 189:f392fc9709a3 | 158 | ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) |
| AnnaBridge | 189:f392fc9709a3 | 159 | |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ |
| AnnaBridge | 189:f392fc9709a3 | 161 | || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) |
| AnnaBridge | 189:f392fc9709a3 | 162 | |
| AnnaBridge | 189:f392fc9709a3 | 163 | #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) |
| AnnaBridge | 189:f392fc9709a3 | 164 | /** |
| AnnaBridge | 189:f392fc9709a3 | 165 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 166 | */ |
| AnnaBridge | 189:f392fc9709a3 | 167 | /* Private function prototypes -----------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 168 | /** @defgroup UTILS_LL_Private_Functions UTILS Private functions |
| AnnaBridge | 189:f392fc9709a3 | 169 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 170 | */ |
| AnnaBridge | 189:f392fc9709a3 | 171 | static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 172 | static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency); |
| AnnaBridge | 189:f392fc9709a3 | 173 | static ErrorStatus UTILS_SetFlashLatency(uint32_t latency); |
| AnnaBridge | 189:f392fc9709a3 | 174 | static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 175 | static ErrorStatus UTILS_IsPLLsReady(void); |
| AnnaBridge | 189:f392fc9709a3 | 176 | /** |
| AnnaBridge | 189:f392fc9709a3 | 177 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 178 | */ |
| AnnaBridge | 189:f392fc9709a3 | 179 | |
| AnnaBridge | 189:f392fc9709a3 | 180 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 181 | /** @addtogroup UTILS_LL_Exported_Functions |
| AnnaBridge | 189:f392fc9709a3 | 182 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 183 | */ |
| AnnaBridge | 189:f392fc9709a3 | 184 | |
| AnnaBridge | 189:f392fc9709a3 | 185 | /** @addtogroup UTILS_LL_EF_DELAY |
| AnnaBridge | 189:f392fc9709a3 | 186 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 187 | */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | |
| AnnaBridge | 189:f392fc9709a3 | 189 | /** |
| AnnaBridge | 189:f392fc9709a3 | 190 | * @brief This function configures the Cortex-M SysTick source to have 1ms time base. |
| AnnaBridge | 189:f392fc9709a3 | 191 | * @note When a RTOS is used, it is recommended to avoid changing the Systick |
| AnnaBridge | 189:f392fc9709a3 | 192 | * configuration by calling this function, for a delay use rather osDelay RTOS service. |
| AnnaBridge | 189:f392fc9709a3 | 193 | * @param CPU_Frequency Core frequency in Hz |
| AnnaBridge | 189:f392fc9709a3 | 194 | * @note CPU_Frequency can be calculated thanks to RCC helper macro or function |
| AnnaBridge | 189:f392fc9709a3 | 195 | * @ref LL_RCC_GetSystemClocksFreq |
| AnnaBridge | 189:f392fc9709a3 | 196 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 197 | */ |
| AnnaBridge | 189:f392fc9709a3 | 198 | void LL_Init1msTick(uint32_t CPU_Frequency) |
| AnnaBridge | 189:f392fc9709a3 | 199 | { |
| AnnaBridge | 189:f392fc9709a3 | 200 | /* Use frequency provided in argument */ |
| AnnaBridge | 189:f392fc9709a3 | 201 | LL_InitTick(CPU_Frequency, 1000U); |
| AnnaBridge | 189:f392fc9709a3 | 202 | } |
| AnnaBridge | 189:f392fc9709a3 | 203 | |
| AnnaBridge | 189:f392fc9709a3 | 204 | |
| AnnaBridge | 189:f392fc9709a3 | 205 | /** |
| AnnaBridge | 189:f392fc9709a3 | 206 | * @brief This function provides accurate delay (in milliseconds) based |
| AnnaBridge | 189:f392fc9709a3 | 207 | * on SysTick counter flag |
| AnnaBridge | 189:f392fc9709a3 | 208 | * @note When a RTOS is used, it is recommended to avoid using blocking delay |
| AnnaBridge | 189:f392fc9709a3 | 209 | * and use rather osDelay service. |
| AnnaBridge | 189:f392fc9709a3 | 210 | * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which |
| AnnaBridge | 189:f392fc9709a3 | 211 | * will configure Systick to 1ms |
| AnnaBridge | 189:f392fc9709a3 | 212 | * @param Delay specifies the delay time length, in milliseconds. |
| AnnaBridge | 189:f392fc9709a3 | 213 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 214 | */ |
| AnnaBridge | 189:f392fc9709a3 | 215 | void LL_mDelay(uint32_t Delay) |
| AnnaBridge | 189:f392fc9709a3 | 216 | { |
| AnnaBridge | 189:f392fc9709a3 | 217 | uint32_t count = Delay; |
| AnnaBridge | 189:f392fc9709a3 | 218 | __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ |
| AnnaBridge | 189:f392fc9709a3 | 219 | /* Add this code to indicate that local variable is not used */ |
| AnnaBridge | 189:f392fc9709a3 | 220 | ((void)tmp); |
| AnnaBridge | 189:f392fc9709a3 | 221 | |
| AnnaBridge | 189:f392fc9709a3 | 222 | /* Add a period to guaranty minimum wait */ |
| AnnaBridge | 189:f392fc9709a3 | 223 | if(count < LL_MAX_DELAY) |
| AnnaBridge | 189:f392fc9709a3 | 224 | { |
| AnnaBridge | 189:f392fc9709a3 | 225 | count++; |
| AnnaBridge | 189:f392fc9709a3 | 226 | } |
| AnnaBridge | 189:f392fc9709a3 | 227 | |
| AnnaBridge | 189:f392fc9709a3 | 228 | while (count != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 229 | { |
| AnnaBridge | 189:f392fc9709a3 | 230 | if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 231 | { |
| AnnaBridge | 189:f392fc9709a3 | 232 | count--; |
| AnnaBridge | 189:f392fc9709a3 | 233 | } |
| AnnaBridge | 189:f392fc9709a3 | 234 | } |
| AnnaBridge | 189:f392fc9709a3 | 235 | } |
| AnnaBridge | 189:f392fc9709a3 | 236 | |
| AnnaBridge | 189:f392fc9709a3 | 237 | /** |
| AnnaBridge | 189:f392fc9709a3 | 238 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 239 | */ |
| AnnaBridge | 189:f392fc9709a3 | 240 | |
| AnnaBridge | 189:f392fc9709a3 | 241 | /** @addtogroup UTILS_EF_SYSTEM |
| AnnaBridge | 189:f392fc9709a3 | 242 | * @brief System Configuration functions |
| AnnaBridge | 189:f392fc9709a3 | 243 | * |
| AnnaBridge | 189:f392fc9709a3 | 244 | @verbatim |
| AnnaBridge | 189:f392fc9709a3 | 245 | =============================================================================== |
| AnnaBridge | 189:f392fc9709a3 | 246 | ##### System Configuration functions ##### |
| AnnaBridge | 189:f392fc9709a3 | 247 | =============================================================================== |
| AnnaBridge | 189:f392fc9709a3 | 248 | [..] |
| AnnaBridge | 189:f392fc9709a3 | 249 | System, AHB and APB buses clocks configuration |
| AnnaBridge | 189:f392fc9709a3 | 250 | |
| AnnaBridge | 189:f392fc9709a3 | 251 | (+) The maximum frequency of the SYSCLK is 400 MHz and HCLK is 200 MHz. |
| AnnaBridge | 189:f392fc9709a3 | 252 | (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 100 MHz. |
| AnnaBridge | 189:f392fc9709a3 | 253 | @endverbatim |
| AnnaBridge | 189:f392fc9709a3 | 254 | @internal |
| AnnaBridge | 189:f392fc9709a3 | 255 | Depending on the device voltage range, the maximum frequency should be |
| AnnaBridge | 189:f392fc9709a3 | 256 | adapted accordingly: |
| AnnaBridge | 189:f392fc9709a3 | 257 | (++) +----------------------------------------------------------------------------+ |
| AnnaBridge | 189:f392fc9709a3 | 258 | (++) | Wait states | HCLK clock frequency (MHz) | |
| AnnaBridge | 189:f392fc9709a3 | 259 | (++) | |-----------------------------------------------------------| |
| AnnaBridge | 189:f392fc9709a3 | 260 | (++) | (Latency) | voltage range 1 | voltage range 2 | voltage range 3 | |
| AnnaBridge | 189:f392fc9709a3 | 261 | (++) | | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V | |
| AnnaBridge | 189:f392fc9709a3 | 262 | (++) |----------------|-------------------|-------------------|-------------------| |
| AnnaBridge | 189:f392fc9709a3 | 263 | (++) |0WS(1CPU cycle) | 0 < HCLK <= 70 | 0 < HCLK <= 55 | 0 < HCLK <= 45 | |
| AnnaBridge | 189:f392fc9709a3 | 264 | (++) |----------------|-------------------|-------------------|-------------------| |
| AnnaBridge | 189:f392fc9709a3 | 265 | (++) |1WS(2CPU cycle) | 70 < HCLK <= 140 | 55 < HCLK <= 110 | 45 < HCLK <= 90 | |
| AnnaBridge | 189:f392fc9709a3 | 266 | (++) |----------------|-------------------|-------------------|-------------------| |
| AnnaBridge | 189:f392fc9709a3 | 267 | (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 110 < HCLK <= 165 | 90 < HCLK <= 135 | |
| AnnaBridge | 189:f392fc9709a3 | 268 | (++) |----------------|-------------------|-------------------|-------------------| |
| AnnaBridge | 189:f392fc9709a3 | 269 | (++) |3WS(4CPU cycle) | -- | 165 < HCLK <= 220 | 135 < HCLK <= 180 | |
| AnnaBridge | 189:f392fc9709a3 | 270 | (++) |----------------|-------------------|-------------------|-------------------| |
| AnnaBridge | 189:f392fc9709a3 | 271 | (++) |4WS(5CPU cycle) | -- | -- | 180 < HCLK <= 225 | |
| AnnaBridge | 189:f392fc9709a3 | 272 | (++) +----------------------------------------------------------------------------+ |
| AnnaBridge | 189:f392fc9709a3 | 273 | |
| AnnaBridge | 189:f392fc9709a3 | 274 | @endinternal |
| AnnaBridge | 189:f392fc9709a3 | 275 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 276 | */ |
| AnnaBridge | 189:f392fc9709a3 | 277 | |
| AnnaBridge | 189:f392fc9709a3 | 278 | /** |
| AnnaBridge | 189:f392fc9709a3 | 279 | * @brief This function sets directly SystemCoreClock CMSIS variable. |
| AnnaBridge | 189:f392fc9709a3 | 280 | * @note Variable can be calculated also through SystemCoreClockUpdate function. |
| AnnaBridge | 189:f392fc9709a3 | 281 | * @param CPU_Frequency Core frequency in Hz |
| AnnaBridge | 189:f392fc9709a3 | 282 | * @note CPU_Frequency can be calculated thanks to RCC helper macro or function |
| AnnaBridge | 189:f392fc9709a3 | 283 | * @ref LL_RCC_GetSystemClocksFreq |
| AnnaBridge | 189:f392fc9709a3 | 284 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 285 | */ |
| AnnaBridge | 189:f392fc9709a3 | 286 | void LL_SetSystemCoreClock(uint32_t CPU_Frequency) |
| AnnaBridge | 189:f392fc9709a3 | 287 | { |
| AnnaBridge | 189:f392fc9709a3 | 288 | /* HCLK clock frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 289 | SystemCoreClock = CPU_Frequency; |
| AnnaBridge | 189:f392fc9709a3 | 290 | } |
| AnnaBridge | 189:f392fc9709a3 | 291 | |
| AnnaBridge | 189:f392fc9709a3 | 292 | /** |
| AnnaBridge | 189:f392fc9709a3 | 293 | * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL |
| AnnaBridge | 189:f392fc9709a3 | 294 | * @note The application need to ensure that PLL is disabled. |
| AnnaBridge | 189:f392fc9709a3 | 295 | * @note Function is based on the following formula: |
| AnnaBridge | 189:f392fc9709a3 | 296 | * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) |
| AnnaBridge | 189:f392fc9709a3 | 297 | * - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM) |
| AnnaBridge | 189:f392fc9709a3 | 298 | * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN) |
| AnnaBridge | 189:f392fc9709a3 | 299 | * - PLLP: ensure that max frequency at 400000000 Hz is reach (PLLVCO_output / PLLP) |
| AnnaBridge | 189:f392fc9709a3 | 300 | * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
| AnnaBridge | 189:f392fc9709a3 | 301 | * the configuration information for the PLL. |
| AnnaBridge | 189:f392fc9709a3 | 302 | * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
| AnnaBridge | 189:f392fc9709a3 | 303 | * the configuration information for the BUS prescalers. |
| AnnaBridge | 189:f392fc9709a3 | 304 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 189:f392fc9709a3 | 305 | * - SUCCESS: Max frequency configuration done |
| AnnaBridge | 189:f392fc9709a3 | 306 | * - ERROR: Max frequency configuration not done |
| AnnaBridge | 189:f392fc9709a3 | 307 | */ |
| AnnaBridge | 189:f392fc9709a3 | 308 | ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, |
| AnnaBridge | 189:f392fc9709a3 | 309 | LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
| AnnaBridge | 189:f392fc9709a3 | 310 | { |
| AnnaBridge | 189:f392fc9709a3 | 311 | ErrorStatus status; |
| AnnaBridge | 189:f392fc9709a3 | 312 | #ifdef USE_FULL_ASSERT |
| AnnaBridge | 189:f392fc9709a3 | 313 | uint32_t vcoinput_freq, vcooutput_freq; |
| AnnaBridge | 189:f392fc9709a3 | 314 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 315 | uint32_t pllfreq, hsi_clk; |
| AnnaBridge | 189:f392fc9709a3 | 316 | |
| AnnaBridge | 189:f392fc9709a3 | 317 | /* Check the parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 318 | assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); |
| AnnaBridge | 189:f392fc9709a3 | 319 | assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); |
| AnnaBridge | 189:f392fc9709a3 | 320 | assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); |
| AnnaBridge | 189:f392fc9709a3 | 321 | assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN)); |
| AnnaBridge | 189:f392fc9709a3 | 322 | |
| AnnaBridge | 189:f392fc9709a3 | 323 | hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos)); |
| AnnaBridge | 189:f392fc9709a3 | 324 | |
| AnnaBridge | 189:f392fc9709a3 | 325 | /* Check VCO Input frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 326 | #ifdef USE_FULL_ASSERT |
| AnnaBridge | 189:f392fc9709a3 | 327 | vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM; |
| AnnaBridge | 189:f392fc9709a3 | 328 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 329 | assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input)); |
| AnnaBridge | 189:f392fc9709a3 | 330 | |
| AnnaBridge | 189:f392fc9709a3 | 331 | /* Check VCO Output frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 332 | #ifdef USE_FULL_ASSERT |
| AnnaBridge | 189:f392fc9709a3 | 333 | vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL); |
| AnnaBridge | 189:f392fc9709a3 | 334 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 335 | assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output)); |
| AnnaBridge | 189:f392fc9709a3 | 336 | |
| AnnaBridge | 189:f392fc9709a3 | 337 | /* Check VCO Input ranges */ |
| AnnaBridge | 189:f392fc9709a3 | 338 | assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output)); |
| AnnaBridge | 189:f392fc9709a3 | 339 | |
| AnnaBridge | 189:f392fc9709a3 | 340 | /* Check if one of the PLL is enabled */ |
| AnnaBridge | 189:f392fc9709a3 | 341 | if(UTILS_IsPLLsReady() == SUCCESS) |
| AnnaBridge | 189:f392fc9709a3 | 342 | { |
| AnnaBridge | 189:f392fc9709a3 | 343 | /* Calculate the new PLL output frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 344 | pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 345 | |
| AnnaBridge | 189:f392fc9709a3 | 346 | /* Enable HSI if not enabled */ |
| AnnaBridge | 189:f392fc9709a3 | 347 | if(LL_RCC_HSI_IsReady() != 1U) |
| AnnaBridge | 189:f392fc9709a3 | 348 | { |
| AnnaBridge | 189:f392fc9709a3 | 349 | LL_RCC_HSI_Enable(); |
| AnnaBridge | 189:f392fc9709a3 | 350 | while (LL_RCC_HSI_IsReady() != 1U) |
| AnnaBridge | 189:f392fc9709a3 | 351 | { |
| AnnaBridge | 189:f392fc9709a3 | 352 | /* Wait for HSI ready */ |
| AnnaBridge | 189:f392fc9709a3 | 353 | } |
| AnnaBridge | 189:f392fc9709a3 | 354 | } |
| AnnaBridge | 189:f392fc9709a3 | 355 | |
| AnnaBridge | 189:f392fc9709a3 | 356 | /* Configure PLL */ |
| AnnaBridge | 189:f392fc9709a3 | 357 | LL_RCC_PLL1P_Enable(); |
| AnnaBridge | 189:f392fc9709a3 | 358 | LL_RCC_PLL1FRACN_Enable(); |
| AnnaBridge | 189:f392fc9709a3 | 359 | LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI); |
| AnnaBridge | 189:f392fc9709a3 | 360 | LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input); |
| AnnaBridge | 189:f392fc9709a3 | 361 | LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output); |
| AnnaBridge | 189:f392fc9709a3 | 362 | LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM); |
| AnnaBridge | 189:f392fc9709a3 | 363 | LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN); |
| AnnaBridge | 189:f392fc9709a3 | 364 | LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP); |
| AnnaBridge | 189:f392fc9709a3 | 365 | LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN); |
| AnnaBridge | 189:f392fc9709a3 | 366 | |
| AnnaBridge | 189:f392fc9709a3 | 367 | /* Enable PLL and switch system clock to PLL */ |
| AnnaBridge | 189:f392fc9709a3 | 368 | status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 369 | } |
| AnnaBridge | 189:f392fc9709a3 | 370 | else |
| AnnaBridge | 189:f392fc9709a3 | 371 | { |
| AnnaBridge | 189:f392fc9709a3 | 372 | /* Current PLL configuration cannot be modified */ |
| AnnaBridge | 189:f392fc9709a3 | 373 | status = ERROR; |
| AnnaBridge | 189:f392fc9709a3 | 374 | } |
| AnnaBridge | 189:f392fc9709a3 | 375 | |
| AnnaBridge | 189:f392fc9709a3 | 376 | return status; |
| AnnaBridge | 189:f392fc9709a3 | 377 | } |
| AnnaBridge | 189:f392fc9709a3 | 378 | |
| AnnaBridge | 189:f392fc9709a3 | 379 | /** |
| AnnaBridge | 189:f392fc9709a3 | 380 | * @brief This function configures system clock with HSE as clock source of the PLL |
| AnnaBridge | 189:f392fc9709a3 | 381 | * @note The application need to ensure that PLL is disabled. |
| AnnaBridge | 189:f392fc9709a3 | 382 | * @note Function is based on the following formula: |
| AnnaBridge | 189:f392fc9709a3 | 383 | * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP) |
| AnnaBridge | 189:f392fc9709a3 | 384 | * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM) |
| AnnaBridge | 189:f392fc9709a3 | 385 | * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN) |
| AnnaBridge | 189:f392fc9709a3 | 386 | * - PLLP: ensure that max frequency at 400000000 Hz is reached (PLLVCO_output / PLLP) |
| AnnaBridge | 189:f392fc9709a3 | 387 | * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000 |
| AnnaBridge | 189:f392fc9709a3 | 388 | * @param HSEBypass This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 389 | * @arg @ref LL_UTILS_HSEBYPASS_ON |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @arg @ref LL_UTILS_HSEBYPASS_OFF |
| AnnaBridge | 189:f392fc9709a3 | 391 | * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
| AnnaBridge | 189:f392fc9709a3 | 392 | * the configuration information for the PLL. |
| AnnaBridge | 189:f392fc9709a3 | 393 | * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
| AnnaBridge | 189:f392fc9709a3 | 394 | * the configuration information for the BUS prescalers. |
| AnnaBridge | 189:f392fc9709a3 | 395 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 189:f392fc9709a3 | 396 | * - SUCCESS: Max frequency configuration done |
| AnnaBridge | 189:f392fc9709a3 | 397 | * - ERROR: Max frequency configuration not done |
| AnnaBridge | 189:f392fc9709a3 | 398 | */ |
| AnnaBridge | 189:f392fc9709a3 | 399 | ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, |
| AnnaBridge | 189:f392fc9709a3 | 400 | LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
| AnnaBridge | 189:f392fc9709a3 | 401 | { |
| AnnaBridge | 189:f392fc9709a3 | 402 | ErrorStatus status; |
| AnnaBridge | 189:f392fc9709a3 | 403 | #ifdef USE_FULL_ASSERT |
| AnnaBridge | 189:f392fc9709a3 | 404 | uint32_t vcoinput_freq, vcooutput_freq; |
| AnnaBridge | 189:f392fc9709a3 | 405 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 406 | uint32_t pllfreq; |
| AnnaBridge | 189:f392fc9709a3 | 407 | |
| AnnaBridge | 189:f392fc9709a3 | 408 | /* Check the parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 409 | assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); |
| AnnaBridge | 189:f392fc9709a3 | 410 | assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); |
| AnnaBridge | 189:f392fc9709a3 | 411 | assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); |
| AnnaBridge | 189:f392fc9709a3 | 412 | assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN)); |
| AnnaBridge | 189:f392fc9709a3 | 413 | assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); |
| AnnaBridge | 189:f392fc9709a3 | 414 | assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); |
| AnnaBridge | 189:f392fc9709a3 | 415 | |
| AnnaBridge | 189:f392fc9709a3 | 416 | /* Check VCO Input frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 417 | #ifdef USE_FULL_ASSERT |
| AnnaBridge | 189:f392fc9709a3 | 418 | vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM; |
| AnnaBridge | 189:f392fc9709a3 | 419 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 420 | assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input)); |
| AnnaBridge | 189:f392fc9709a3 | 421 | |
| AnnaBridge | 189:f392fc9709a3 | 422 | /* Check VCO output frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 423 | #ifdef USE_FULL_ASSERT |
| AnnaBridge | 189:f392fc9709a3 | 424 | vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U); |
| AnnaBridge | 189:f392fc9709a3 | 425 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 426 | assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output)); |
| AnnaBridge | 189:f392fc9709a3 | 427 | |
| AnnaBridge | 189:f392fc9709a3 | 428 | /* Check VCO Input/output ranges compatibility */ |
| AnnaBridge | 189:f392fc9709a3 | 429 | assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output)); |
| AnnaBridge | 189:f392fc9709a3 | 430 | |
| AnnaBridge | 189:f392fc9709a3 | 431 | /* Check if one of the PLL is enabled */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | if(UTILS_IsPLLsReady() == SUCCESS) |
| AnnaBridge | 189:f392fc9709a3 | 433 | { |
| AnnaBridge | 189:f392fc9709a3 | 434 | /* Calculate the new PLL output frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 435 | pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 436 | |
| AnnaBridge | 189:f392fc9709a3 | 437 | /* Enable HSE if not enabled */ |
| AnnaBridge | 189:f392fc9709a3 | 438 | if(LL_RCC_HSE_IsReady() != 1U) |
| AnnaBridge | 189:f392fc9709a3 | 439 | { |
| AnnaBridge | 189:f392fc9709a3 | 440 | /* Check if need to enable HSE bypass feature or not */ |
| AnnaBridge | 189:f392fc9709a3 | 441 | if(HSEBypass == LL_UTILS_HSEBYPASS_ON) |
| AnnaBridge | 189:f392fc9709a3 | 442 | { |
| AnnaBridge | 189:f392fc9709a3 | 443 | LL_RCC_HSE_EnableBypass(); |
| AnnaBridge | 189:f392fc9709a3 | 444 | } |
| AnnaBridge | 189:f392fc9709a3 | 445 | else |
| AnnaBridge | 189:f392fc9709a3 | 446 | { |
| AnnaBridge | 189:f392fc9709a3 | 447 | LL_RCC_HSE_DisableBypass(); |
| AnnaBridge | 189:f392fc9709a3 | 448 | } |
| AnnaBridge | 189:f392fc9709a3 | 449 | |
| AnnaBridge | 189:f392fc9709a3 | 450 | /* Enable HSE */ |
| AnnaBridge | 189:f392fc9709a3 | 451 | LL_RCC_HSE_Enable(); |
| AnnaBridge | 189:f392fc9709a3 | 452 | while (LL_RCC_HSE_IsReady() != 1U) |
| AnnaBridge | 189:f392fc9709a3 | 453 | { |
| AnnaBridge | 189:f392fc9709a3 | 454 | /* Wait for HSE ready */ |
| AnnaBridge | 189:f392fc9709a3 | 455 | } |
| AnnaBridge | 189:f392fc9709a3 | 456 | } |
| AnnaBridge | 189:f392fc9709a3 | 457 | |
| AnnaBridge | 189:f392fc9709a3 | 458 | /* Configure PLL */ |
| AnnaBridge | 189:f392fc9709a3 | 459 | LL_RCC_PLL1P_Enable(); |
| AnnaBridge | 189:f392fc9709a3 | 460 | LL_RCC_PLL1FRACN_Enable(); |
| AnnaBridge | 189:f392fc9709a3 | 461 | LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE); |
| AnnaBridge | 189:f392fc9709a3 | 462 | LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input); |
| AnnaBridge | 189:f392fc9709a3 | 463 | LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output); |
| AnnaBridge | 189:f392fc9709a3 | 464 | LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM); |
| AnnaBridge | 189:f392fc9709a3 | 465 | LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN); |
| AnnaBridge | 189:f392fc9709a3 | 466 | LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP); |
| AnnaBridge | 189:f392fc9709a3 | 467 | LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN); |
| AnnaBridge | 189:f392fc9709a3 | 468 | |
| AnnaBridge | 189:f392fc9709a3 | 469 | /* Enable PLL and switch system clock to PLL */ |
| AnnaBridge | 189:f392fc9709a3 | 470 | status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 471 | } |
| AnnaBridge | 189:f392fc9709a3 | 472 | else |
| AnnaBridge | 189:f392fc9709a3 | 473 | { |
| AnnaBridge | 189:f392fc9709a3 | 474 | /* Current PLL configuration cannot be modified */ |
| AnnaBridge | 189:f392fc9709a3 | 475 | status = ERROR; |
| AnnaBridge | 189:f392fc9709a3 | 476 | } |
| AnnaBridge | 189:f392fc9709a3 | 477 | |
| AnnaBridge | 189:f392fc9709a3 | 478 | return status; |
| AnnaBridge | 189:f392fc9709a3 | 479 | } |
| AnnaBridge | 189:f392fc9709a3 | 480 | |
| AnnaBridge | 189:f392fc9709a3 | 481 | /** |
| AnnaBridge | 189:f392fc9709a3 | 482 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 483 | */ |
| AnnaBridge | 189:f392fc9709a3 | 484 | |
| AnnaBridge | 189:f392fc9709a3 | 485 | /** |
| AnnaBridge | 189:f392fc9709a3 | 486 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 487 | */ |
| AnnaBridge | 189:f392fc9709a3 | 488 | |
| AnnaBridge | 189:f392fc9709a3 | 489 | /** @addtogroup UTILS_LL_Private_Functions |
| AnnaBridge | 189:f392fc9709a3 | 490 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 491 | */ |
| AnnaBridge | 189:f392fc9709a3 | 492 | |
| AnnaBridge | 189:f392fc9709a3 | 493 | /** |
| AnnaBridge | 189:f392fc9709a3 | 494 | * @brief Calculate and check the Flash wait states number according to the |
| AnnaBridge | 189:f392fc9709a3 | 495 | new HCLK frequency and current voltage range. |
| AnnaBridge | 189:f392fc9709a3 | 496 | * @param HCLK_Frequency HCLK frequency |
| AnnaBridge | 189:f392fc9709a3 | 497 | * @param latency This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 498 | * @arg @ref LL_FLASH_LATENCY_0 |
| AnnaBridge | 189:f392fc9709a3 | 499 | * @arg @ref LL_FLASH_LATENCY_1 |
| AnnaBridge | 189:f392fc9709a3 | 500 | * @arg @ref LL_FLASH_LATENCY_2 |
| AnnaBridge | 189:f392fc9709a3 | 501 | * @arg @ref LL_FLASH_LATENCY_3 |
| AnnaBridge | 189:f392fc9709a3 | 502 | * @arg @ref LL_FLASH_LATENCY_4 |
| AnnaBridge | 189:f392fc9709a3 | 503 | * @arg @ref LL_FLASH_LATENCY_5 |
| AnnaBridge | 189:f392fc9709a3 | 504 | * @arg @ref LL_FLASH_LATENCY_6 |
| AnnaBridge | 189:f392fc9709a3 | 505 | * @arg @ref LL_FLASH_LATENCY_7 |
| AnnaBridge | 189:f392fc9709a3 | 506 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 189:f392fc9709a3 | 507 | * - SUCCESS: Latency has been modified |
| AnnaBridge | 189:f392fc9709a3 | 508 | * - ERROR: Latency cannot be modified |
| AnnaBridge | 189:f392fc9709a3 | 509 | */ |
| AnnaBridge | 189:f392fc9709a3 | 510 | static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency) |
| AnnaBridge | 189:f392fc9709a3 | 511 | { |
| AnnaBridge | 189:f392fc9709a3 | 512 | ErrorStatus status = SUCCESS; |
| AnnaBridge | 189:f392fc9709a3 | 513 | |
| AnnaBridge | 189:f392fc9709a3 | 514 | /* Frequency cannot be equal to 0 */ |
| AnnaBridge | 189:f392fc9709a3 | 515 | if(HCLK_Frequency == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 516 | { |
| AnnaBridge | 189:f392fc9709a3 | 517 | status = ERROR; |
| AnnaBridge | 189:f392fc9709a3 | 518 | } |
| AnnaBridge | 189:f392fc9709a3 | 519 | else |
| AnnaBridge | 189:f392fc9709a3 | 520 | { |
| AnnaBridge | 189:f392fc9709a3 | 521 | if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) |
| AnnaBridge | 189:f392fc9709a3 | 522 | { |
| AnnaBridge | 189:f392fc9709a3 | 523 | if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ)) |
| AnnaBridge | 189:f392fc9709a3 | 524 | { |
| AnnaBridge | 189:f392fc9709a3 | 525 | /* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 526 | *latency = LL_FLASH_LATENCY_2; |
| AnnaBridge | 189:f392fc9709a3 | 527 | } |
| AnnaBridge | 189:f392fc9709a3 | 528 | else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ)) |
| AnnaBridge | 189:f392fc9709a3 | 529 | { |
| AnnaBridge | 189:f392fc9709a3 | 530 | /* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 531 | *latency = LL_FLASH_LATENCY_1; |
| AnnaBridge | 189:f392fc9709a3 | 532 | } |
| AnnaBridge | 189:f392fc9709a3 | 533 | else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ) |
| AnnaBridge | 189:f392fc9709a3 | 534 | { |
| AnnaBridge | 189:f392fc9709a3 | 535 | /* HCLK <= 70 => 0WS (1 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 536 | *latency = LL_FLASH_LATENCY_0; |
| AnnaBridge | 189:f392fc9709a3 | 537 | } |
| AnnaBridge | 189:f392fc9709a3 | 538 | else |
| AnnaBridge | 189:f392fc9709a3 | 539 | { |
| AnnaBridge | 189:f392fc9709a3 | 540 | status = ERROR; |
| AnnaBridge | 189:f392fc9709a3 | 541 | } |
| AnnaBridge | 189:f392fc9709a3 | 542 | } |
| AnnaBridge | 189:f392fc9709a3 | 543 | else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) |
| AnnaBridge | 189:f392fc9709a3 | 544 | { |
| AnnaBridge | 189:f392fc9709a3 | 545 | if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ)) |
| AnnaBridge | 189:f392fc9709a3 | 546 | { |
| AnnaBridge | 189:f392fc9709a3 | 547 | /* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 548 | *latency = LL_FLASH_LATENCY_3; |
| AnnaBridge | 189:f392fc9709a3 | 549 | } |
| AnnaBridge | 189:f392fc9709a3 | 550 | else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ)) |
| AnnaBridge | 189:f392fc9709a3 | 551 | { |
| AnnaBridge | 189:f392fc9709a3 | 552 | /* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 553 | *latency = LL_FLASH_LATENCY_2; |
| AnnaBridge | 189:f392fc9709a3 | 554 | } |
| AnnaBridge | 189:f392fc9709a3 | 555 | else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ)) |
| AnnaBridge | 189:f392fc9709a3 | 556 | { |
| AnnaBridge | 189:f392fc9709a3 | 557 | /* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 558 | *latency = LL_FLASH_LATENCY_1; |
| AnnaBridge | 189:f392fc9709a3 | 559 | } |
| AnnaBridge | 189:f392fc9709a3 | 560 | else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ) |
| AnnaBridge | 189:f392fc9709a3 | 561 | { |
| AnnaBridge | 189:f392fc9709a3 | 562 | /* HCLK <= 55 => 0WS (1 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 563 | *latency = LL_FLASH_LATENCY_0; |
| AnnaBridge | 189:f392fc9709a3 | 564 | } |
| AnnaBridge | 189:f392fc9709a3 | 565 | else |
| AnnaBridge | 189:f392fc9709a3 | 566 | { |
| AnnaBridge | 189:f392fc9709a3 | 567 | status = ERROR; |
| AnnaBridge | 189:f392fc9709a3 | 568 | } |
| AnnaBridge | 189:f392fc9709a3 | 569 | } |
| AnnaBridge | 189:f392fc9709a3 | 570 | else /* Scale 3 */ |
| AnnaBridge | 189:f392fc9709a3 | 571 | { |
| AnnaBridge | 189:f392fc9709a3 | 572 | if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ)) |
| AnnaBridge | 189:f392fc9709a3 | 573 | { |
| AnnaBridge | 189:f392fc9709a3 | 574 | /* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 575 | *latency = LL_FLASH_LATENCY_4; |
| AnnaBridge | 189:f392fc9709a3 | 576 | } |
| AnnaBridge | 189:f392fc9709a3 | 577 | else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ)) |
| AnnaBridge | 189:f392fc9709a3 | 578 | { |
| AnnaBridge | 189:f392fc9709a3 | 579 | /* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 580 | *latency = LL_FLASH_LATENCY_3; |
| AnnaBridge | 189:f392fc9709a3 | 581 | } |
| AnnaBridge | 189:f392fc9709a3 | 582 | else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ)) |
| AnnaBridge | 189:f392fc9709a3 | 583 | { |
| AnnaBridge | 189:f392fc9709a3 | 584 | /* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 585 | *latency = LL_FLASH_LATENCY_2; |
| AnnaBridge | 189:f392fc9709a3 | 586 | } |
| AnnaBridge | 189:f392fc9709a3 | 587 | else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ)) |
| AnnaBridge | 189:f392fc9709a3 | 588 | { |
| AnnaBridge | 189:f392fc9709a3 | 589 | /* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 590 | *latency = LL_FLASH_LATENCY_1; |
| AnnaBridge | 189:f392fc9709a3 | 591 | } |
| AnnaBridge | 189:f392fc9709a3 | 592 | else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ) |
| AnnaBridge | 189:f392fc9709a3 | 593 | { |
| AnnaBridge | 189:f392fc9709a3 | 594 | /* HCLK <= 45 => 0WS (1 CPU cycles) */ |
| AnnaBridge | 189:f392fc9709a3 | 595 | *latency = LL_FLASH_LATENCY_0; |
| AnnaBridge | 189:f392fc9709a3 | 596 | } |
| AnnaBridge | 189:f392fc9709a3 | 597 | else |
| AnnaBridge | 189:f392fc9709a3 | 598 | { |
| AnnaBridge | 189:f392fc9709a3 | 599 | status = ERROR; |
| AnnaBridge | 189:f392fc9709a3 | 600 | } |
| AnnaBridge | 189:f392fc9709a3 | 601 | } |
| AnnaBridge | 189:f392fc9709a3 | 602 | } |
| AnnaBridge | 189:f392fc9709a3 | 603 | |
| AnnaBridge | 189:f392fc9709a3 | 604 | return status; |
| AnnaBridge | 189:f392fc9709a3 | 605 | } |
| AnnaBridge | 189:f392fc9709a3 | 606 | |
| AnnaBridge | 189:f392fc9709a3 | 607 | /** |
| AnnaBridge | 189:f392fc9709a3 | 608 | * @brief Update number of Flash wait states |
| AnnaBridge | 189:f392fc9709a3 | 609 | * @param latency Flash Latency |
| AnnaBridge | 189:f392fc9709a3 | 610 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 189:f392fc9709a3 | 611 | * - SUCCESS: Latency has been modified |
| AnnaBridge | 189:f392fc9709a3 | 612 | * - ERROR: Latency cannot be modified |
| AnnaBridge | 189:f392fc9709a3 | 613 | */ |
| AnnaBridge | 189:f392fc9709a3 | 614 | static ErrorStatus UTILS_SetFlashLatency(uint32_t latency) |
| AnnaBridge | 189:f392fc9709a3 | 615 | { |
| AnnaBridge | 189:f392fc9709a3 | 616 | ErrorStatus status = SUCCESS; |
| AnnaBridge | 189:f392fc9709a3 | 617 | |
| AnnaBridge | 189:f392fc9709a3 | 618 | LL_FLASH_SetLatency(latency); |
| AnnaBridge | 189:f392fc9709a3 | 619 | |
| AnnaBridge | 189:f392fc9709a3 | 620 | /* Check that the new number of wait states is taken into account to access the Flash |
| AnnaBridge | 189:f392fc9709a3 | 621 | memory by reading the FLASH_ACR register */ |
| AnnaBridge | 189:f392fc9709a3 | 622 | if(LL_FLASH_GetLatency() != latency) |
| AnnaBridge | 189:f392fc9709a3 | 623 | { |
| AnnaBridge | 189:f392fc9709a3 | 624 | status = ERROR; |
| AnnaBridge | 189:f392fc9709a3 | 625 | } |
| AnnaBridge | 189:f392fc9709a3 | 626 | |
| AnnaBridge | 189:f392fc9709a3 | 627 | return status; |
| AnnaBridge | 189:f392fc9709a3 | 628 | } |
| AnnaBridge | 189:f392fc9709a3 | 629 | |
| AnnaBridge | 189:f392fc9709a3 | 630 | /** |
| AnnaBridge | 189:f392fc9709a3 | 631 | * @brief Function to check that PLL can be modified |
| AnnaBridge | 189:f392fc9709a3 | 632 | * @param PLL_InputFrequency PLL input frequency (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 633 | * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains |
| AnnaBridge | 189:f392fc9709a3 | 634 | * the configuration information for the PLL. |
| AnnaBridge | 189:f392fc9709a3 | 635 | * @retval PLL output frequency (in Hz) |
| AnnaBridge | 189:f392fc9709a3 | 636 | */ |
| AnnaBridge | 189:f392fc9709a3 | 637 | static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) |
| AnnaBridge | 189:f392fc9709a3 | 638 | { |
| AnnaBridge | 189:f392fc9709a3 | 639 | uint32_t pllfreq; |
| AnnaBridge | 189:f392fc9709a3 | 640 | |
| AnnaBridge | 189:f392fc9709a3 | 641 | /* Check the parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 642 | assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); |
| AnnaBridge | 189:f392fc9709a3 | 643 | assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); |
| AnnaBridge | 189:f392fc9709a3 | 644 | assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); |
| AnnaBridge | 189:f392fc9709a3 | 645 | assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN)); |
| AnnaBridge | 189:f392fc9709a3 | 646 | |
| AnnaBridge | 189:f392fc9709a3 | 647 | pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP); |
| AnnaBridge | 189:f392fc9709a3 | 648 | |
| AnnaBridge | 189:f392fc9709a3 | 649 | return pllfreq; |
| AnnaBridge | 189:f392fc9709a3 | 650 | } |
| AnnaBridge | 189:f392fc9709a3 | 651 | |
| AnnaBridge | 189:f392fc9709a3 | 652 | /** |
| AnnaBridge | 189:f392fc9709a3 | 653 | * @brief Check that all PLLs are ready therefore configuration can be done |
| AnnaBridge | 189:f392fc9709a3 | 654 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 189:f392fc9709a3 | 655 | * - SUCCESS: All PLLs are ready so configuration can be done |
| AnnaBridge | 189:f392fc9709a3 | 656 | * - ERROR: One PLL at least is busy |
| AnnaBridge | 189:f392fc9709a3 | 657 | */ |
| AnnaBridge | 189:f392fc9709a3 | 658 | static ErrorStatus UTILS_IsPLLsReady(void) |
| AnnaBridge | 189:f392fc9709a3 | 659 | { |
| AnnaBridge | 189:f392fc9709a3 | 660 | ErrorStatus status = SUCCESS; |
| AnnaBridge | 189:f392fc9709a3 | 661 | |
| AnnaBridge | 189:f392fc9709a3 | 662 | /* Check if one of the PLL1 is busy */ |
| AnnaBridge | 189:f392fc9709a3 | 663 | if(LL_RCC_PLL1_IsReady() != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 664 | { |
| AnnaBridge | 189:f392fc9709a3 | 665 | /* PLL1 configuration cannot be done */ |
| AnnaBridge | 189:f392fc9709a3 | 666 | status = ERROR; |
| AnnaBridge | 189:f392fc9709a3 | 667 | } |
| AnnaBridge | 189:f392fc9709a3 | 668 | |
| AnnaBridge | 189:f392fc9709a3 | 669 | /* Check if one of the PLL2 is busy */ |
| AnnaBridge | 189:f392fc9709a3 | 670 | if(LL_RCC_PLL2_IsReady() != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 671 | { |
| AnnaBridge | 189:f392fc9709a3 | 672 | /* PLL2 configuration cannot be done */ |
| AnnaBridge | 189:f392fc9709a3 | 673 | status = ERROR; |
| AnnaBridge | 189:f392fc9709a3 | 674 | } |
| AnnaBridge | 189:f392fc9709a3 | 675 | |
| AnnaBridge | 189:f392fc9709a3 | 676 | /* Check if one of the PLL3 is busy */ |
| AnnaBridge | 189:f392fc9709a3 | 677 | if(LL_RCC_PLL3_IsReady() != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 678 | { |
| AnnaBridge | 189:f392fc9709a3 | 679 | /* PLL3 configuration cannot be done */ |
| AnnaBridge | 189:f392fc9709a3 | 680 | status = ERROR; |
| AnnaBridge | 189:f392fc9709a3 | 681 | } |
| AnnaBridge | 189:f392fc9709a3 | 682 | |
| AnnaBridge | 189:f392fc9709a3 | 683 | return status; |
| AnnaBridge | 189:f392fc9709a3 | 684 | } |
| AnnaBridge | 189:f392fc9709a3 | 685 | |
| AnnaBridge | 189:f392fc9709a3 | 686 | /** |
| AnnaBridge | 189:f392fc9709a3 | 687 | * @brief Function to enable PLL and switch system clock to PLL |
| AnnaBridge | 189:f392fc9709a3 | 688 | * @param SYSCLK_Frequency SYSCLK frequency |
| AnnaBridge | 189:f392fc9709a3 | 689 | * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains |
| AnnaBridge | 189:f392fc9709a3 | 690 | * the configuration information for the BUS prescalers. |
| AnnaBridge | 189:f392fc9709a3 | 691 | * @retval An ErrorStatus enumeration value: |
| AnnaBridge | 189:f392fc9709a3 | 692 | * - SUCCESS: No problem to switch system to PLL |
| AnnaBridge | 189:f392fc9709a3 | 693 | * - ERROR: Problem to switch system to PLL |
| AnnaBridge | 189:f392fc9709a3 | 694 | */ |
| AnnaBridge | 189:f392fc9709a3 | 695 | static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) |
| AnnaBridge | 189:f392fc9709a3 | 696 | { |
| AnnaBridge | 189:f392fc9709a3 | 697 | ErrorStatus status; |
| AnnaBridge | 189:f392fc9709a3 | 698 | uint32_t new_hclk_frequency, new_latency; |
| AnnaBridge | 189:f392fc9709a3 | 699 | |
| AnnaBridge | 189:f392fc9709a3 | 700 | assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider)); |
| AnnaBridge | 189:f392fc9709a3 | 701 | assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); |
| AnnaBridge | 189:f392fc9709a3 | 702 | assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); |
| AnnaBridge | 189:f392fc9709a3 | 703 | assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); |
| AnnaBridge | 189:f392fc9709a3 | 704 | assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider)); |
| AnnaBridge | 189:f392fc9709a3 | 705 | assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider)); |
| AnnaBridge | 189:f392fc9709a3 | 706 | |
| AnnaBridge | 189:f392fc9709a3 | 707 | /* Calculate the new HCLK frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 708 | new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); |
| AnnaBridge | 189:f392fc9709a3 | 709 | |
| AnnaBridge | 189:f392fc9709a3 | 710 | /* Calculate the new FLASH latency according to the new HCLK frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 711 | status = UTILS_CalculateFlashLatency(new_hclk_frequency, &new_latency); |
| AnnaBridge | 189:f392fc9709a3 | 712 | |
| AnnaBridge | 189:f392fc9709a3 | 713 | if(status == SUCCESS) |
| AnnaBridge | 189:f392fc9709a3 | 714 | { |
| AnnaBridge | 189:f392fc9709a3 | 715 | /* Increasing the number of wait states because of higher CPU frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 716 | if(LL_FLASH_GetLatency() < new_latency) |
| AnnaBridge | 189:f392fc9709a3 | 717 | { |
| AnnaBridge | 189:f392fc9709a3 | 718 | status = UTILS_SetFlashLatency(new_latency); |
| AnnaBridge | 189:f392fc9709a3 | 719 | } |
| AnnaBridge | 189:f392fc9709a3 | 720 | |
| AnnaBridge | 189:f392fc9709a3 | 721 | /* Update system clock configuration */ |
| AnnaBridge | 189:f392fc9709a3 | 722 | if(status == SUCCESS) |
| AnnaBridge | 189:f392fc9709a3 | 723 | { |
| AnnaBridge | 189:f392fc9709a3 | 724 | /* Enable PLL */ |
| AnnaBridge | 189:f392fc9709a3 | 725 | LL_RCC_PLL1_Enable(); |
| AnnaBridge | 189:f392fc9709a3 | 726 | while (LL_RCC_PLL1_IsReady() != 1U) |
| AnnaBridge | 189:f392fc9709a3 | 727 | { |
| AnnaBridge | 189:f392fc9709a3 | 728 | /* Wait for PLL ready */ |
| AnnaBridge | 189:f392fc9709a3 | 729 | } |
| AnnaBridge | 189:f392fc9709a3 | 730 | |
| AnnaBridge | 189:f392fc9709a3 | 731 | /* Set All APBxPrescaler to the Highest Divider */ |
| AnnaBridge | 189:f392fc9709a3 | 732 | LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16); |
| AnnaBridge | 189:f392fc9709a3 | 733 | LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16); |
| AnnaBridge | 189:f392fc9709a3 | 734 | LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16); |
| AnnaBridge | 189:f392fc9709a3 | 735 | LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16); |
| AnnaBridge | 189:f392fc9709a3 | 736 | |
| AnnaBridge | 189:f392fc9709a3 | 737 | /* Set SYS prescaler*/ |
| AnnaBridge | 189:f392fc9709a3 | 738 | LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider); |
| AnnaBridge | 189:f392fc9709a3 | 739 | |
| AnnaBridge | 189:f392fc9709a3 | 740 | /* Set AHB prescaler*/ |
| AnnaBridge | 189:f392fc9709a3 | 741 | LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); |
| AnnaBridge | 189:f392fc9709a3 | 742 | |
| AnnaBridge | 189:f392fc9709a3 | 743 | /* Sysclk activation on the main PLL */ |
| AnnaBridge | 189:f392fc9709a3 | 744 | LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1); |
| AnnaBridge | 189:f392fc9709a3 | 745 | while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) |
| AnnaBridge | 189:f392fc9709a3 | 746 | { |
| AnnaBridge | 189:f392fc9709a3 | 747 | /* Wait for system clock switch to PLL */ |
| AnnaBridge | 189:f392fc9709a3 | 748 | } |
| AnnaBridge | 189:f392fc9709a3 | 749 | |
| AnnaBridge | 189:f392fc9709a3 | 750 | /* Set APBn prescaler*/ |
| AnnaBridge | 189:f392fc9709a3 | 751 | LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); |
| AnnaBridge | 189:f392fc9709a3 | 752 | LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); |
| AnnaBridge | 189:f392fc9709a3 | 753 | LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider); |
| AnnaBridge | 189:f392fc9709a3 | 754 | LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider); |
| AnnaBridge | 189:f392fc9709a3 | 755 | |
| AnnaBridge | 189:f392fc9709a3 | 756 | /* Update SystemCoreClock variable */ |
| AnnaBridge | 189:f392fc9709a3 | 757 | LL_SetSystemCoreClock(SYSCLK_Frequency); |
| AnnaBridge | 189:f392fc9709a3 | 758 | } |
| AnnaBridge | 189:f392fc9709a3 | 759 | |
| AnnaBridge | 189:f392fc9709a3 | 760 | /* Decreasing the number of wait states because of lower CPU frequency */ |
| AnnaBridge | 189:f392fc9709a3 | 761 | if(LL_FLASH_GetLatency() > new_latency) |
| AnnaBridge | 189:f392fc9709a3 | 762 | { |
| AnnaBridge | 189:f392fc9709a3 | 763 | status = UTILS_SetFlashLatency(new_latency); |
| AnnaBridge | 189:f392fc9709a3 | 764 | } |
| AnnaBridge | 189:f392fc9709a3 | 765 | } |
| AnnaBridge | 189:f392fc9709a3 | 766 | |
| AnnaBridge | 189:f392fc9709a3 | 767 | return status; |
| AnnaBridge | 189:f392fc9709a3 | 768 | } |
| AnnaBridge | 189:f392fc9709a3 | 769 | |
| AnnaBridge | 189:f392fc9709a3 | 770 | /** |
| AnnaBridge | 189:f392fc9709a3 | 771 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 772 | */ |
| AnnaBridge | 189:f392fc9709a3 | 773 | |
| AnnaBridge | 189:f392fc9709a3 | 774 | /** |
| AnnaBridge | 189:f392fc9709a3 | 775 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 776 | */ |
| AnnaBridge | 189:f392fc9709a3 | 777 | |
| AnnaBridge | 189:f392fc9709a3 | 778 | /** |
| AnnaBridge | 189:f392fc9709a3 | 779 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 780 | */ |
| AnnaBridge | 189:f392fc9709a3 | 781 | |
| AnnaBridge | 189:f392fc9709a3 | 782 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
