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targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_rcc.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32h7xx_ll_rcc.c
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief RCC LL module driver.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge	189:f392fc9709a3	10	* All rights reserved.</center></h2>
AnnaBridge	189:f392fc9709a3	11	*
AnnaBridge	189:f392fc9709a3	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	189:f392fc9709a3	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	189:f392fc9709a3	14	* License. You may obtain a copy of the License at:
AnnaBridge	189:f392fc9709a3	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	189:f392fc9709a3	16	*
AnnaBridge	189:f392fc9709a3	17	******************************************************************************
AnnaBridge	189:f392fc9709a3	18	*/
AnnaBridge	189:f392fc9709a3	19	#if 1 // MBED PATCH defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	20
AnnaBridge	189:f392fc9709a3	21	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	22	#include "stm32h7xx_ll_rcc.h"
AnnaBridge	189:f392fc9709a3	23	#include "stm32h7xx_ll_bus.h"
AnnaBridge	189:f392fc9709a3	24	#ifdef USE_FULL_ASSERT
AnnaBridge	189:f392fc9709a3	25	#include "stm32_assert.h"
AnnaBridge	189:f392fc9709a3	26	#else
AnnaBridge	189:f392fc9709a3	27	#define assert_param(expr) ((void)0U)
AnnaBridge	189:f392fc9709a3	28	#endif
AnnaBridge	189:f392fc9709a3	29
AnnaBridge	189:f392fc9709a3	30	/** @addtogroup STM32H7xx_LL_Driver
AnnaBridge	189:f392fc9709a3	31	* @{
AnnaBridge	189:f392fc9709a3	32	*/
AnnaBridge	189:f392fc9709a3	33
AnnaBridge	189:f392fc9709a3	34	#if defined(RCC)
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/** @addtogroup RCC_LL
AnnaBridge	189:f392fc9709a3	37	* @{
AnnaBridge	189:f392fc9709a3	38	*/
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	41	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	42	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	43	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	44	/** @addtogroup RCC_LL_Private_Macros
AnnaBridge	189:f392fc9709a3	45	* @{
AnnaBridge	189:f392fc9709a3	46	*/
AnnaBridge	189:f392fc9709a3	47	#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART16_CLKSOURCE) \
AnnaBridge	189:f392fc9709a3	48	\|\| ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE))
AnnaBridge	189:f392fc9709a3	49
AnnaBridge	189:f392fc9709a3	50
AnnaBridge	189:f392fc9709a3	51	#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C123_CLKSOURCE) \
AnnaBridge	189:f392fc9709a3	52	\|\| ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
AnnaBridge	189:f392fc9709a3	53
AnnaBridge	189:f392fc9709a3	54	#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
AnnaBridge	189:f392fc9709a3	55	\|\| ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
AnnaBridge	189:f392fc9709a3	56	\|\| ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))
AnnaBridge	189:f392fc9709a3	57
AnnaBridge	189:f392fc9709a3	58	#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
AnnaBridge	189:f392fc9709a3	59	\|\| ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \
AnnaBridge	189:f392fc9709a3	60	\|\| ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
AnnaBridge	189:f392fc9709a3	61	\|\| ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
AnnaBridge	189:f392fc9709a3	62
AnnaBridge	189:f392fc9709a3	63	#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
AnnaBridge	189:f392fc9709a3	64	\|\| ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
AnnaBridge	189:f392fc9709a3	65	\|\| ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
AnnaBridge	189:f392fc9709a3	66
AnnaBridge	189:f392fc9709a3	67	/**
AnnaBridge	189:f392fc9709a3	68	* @}
AnnaBridge	189:f392fc9709a3	69	*/
AnnaBridge	189:f392fc9709a3	70
AnnaBridge	189:f392fc9709a3	71	/* Private function prototypes -----------------------------------------------*/
AnnaBridge	189:f392fc9709a3	72	/** @defgroup RCC_LL_Private_Functions RCC Private functions
AnnaBridge	189:f392fc9709a3	73	* @{
AnnaBridge	189:f392fc9709a3	74	*/
AnnaBridge	189:f392fc9709a3	75	uint32_t RCC_GetSystemClockFreq(void);
AnnaBridge	189:f392fc9709a3	76	uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
AnnaBridge	189:f392fc9709a3	77	uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
AnnaBridge	189:f392fc9709a3	78	uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
AnnaBridge	189:f392fc9709a3	79	uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
AnnaBridge	189:f392fc9709a3	80	uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
AnnaBridge	189:f392fc9709a3	81
AnnaBridge	189:f392fc9709a3	82	/**
AnnaBridge	189:f392fc9709a3	83	* @}
AnnaBridge	189:f392fc9709a3	84	*/
AnnaBridge	189:f392fc9709a3	85
AnnaBridge	189:f392fc9709a3	86
AnnaBridge	189:f392fc9709a3	87	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	88	/** @addtogroup RCC_LL_Exported_Functions
AnnaBridge	189:f392fc9709a3	89	* @{
AnnaBridge	189:f392fc9709a3	90	*/
AnnaBridge	189:f392fc9709a3	91
AnnaBridge	189:f392fc9709a3	92	/** @addtogroup RCC_LL_EF_Init
AnnaBridge	189:f392fc9709a3	93	* @{
AnnaBridge	189:f392fc9709a3	94	*/
AnnaBridge	189:f392fc9709a3	95
AnnaBridge	189:f392fc9709a3	96	/**
AnnaBridge	189:f392fc9709a3	97	* @brief Resets the RCC clock configuration to the default reset state.
AnnaBridge	189:f392fc9709a3	98	* @note The default reset state of the clock configuration is given below:
AnnaBridge	189:f392fc9709a3	99	* - HSI ON and used as system clock source
AnnaBridge	189:f392fc9709a3	100	* - HSE, PLL1, PLL2 and PLL3 OFF
AnnaBridge	189:f392fc9709a3	101	* - AHB, APB Bus pre-scaler set to 1.
AnnaBridge	189:f392fc9709a3	102	* - CSS, MCO1 and MCO2 OFF
AnnaBridge	189:f392fc9709a3	103	* - All interrupts disabled
AnnaBridge	189:f392fc9709a3	104	* @note This function doesn't modify the configuration of the
AnnaBridge	189:f392fc9709a3	105	* - Peripheral clocks
AnnaBridge	189:f392fc9709a3	106	* - LSI, LSE and RTC clocks
AnnaBridge	189:f392fc9709a3	107	* @retval None
AnnaBridge	189:f392fc9709a3	108	*/
AnnaBridge	189:f392fc9709a3	109	void LL_RCC_DeInit(void)
AnnaBridge	189:f392fc9709a3	110	{
AnnaBridge	189:f392fc9709a3	111	/* Set HSION bit */
AnnaBridge	189:f392fc9709a3	112	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	189:f392fc9709a3	113
AnnaBridge	189:f392fc9709a3	114	/* Wait for HSI READY bit */
AnnaBridge	189:f392fc9709a3	115	while(LL_RCC_HSI_IsReady() == 0U)
AnnaBridge	189:f392fc9709a3	116	{}
AnnaBridge	189:f392fc9709a3	117
AnnaBridge	189:f392fc9709a3	118	/* Reset CFGR register */
AnnaBridge	189:f392fc9709a3	119	CLEAR_REG(RCC->CFGR);
AnnaBridge	189:f392fc9709a3	120
AnnaBridge	189:f392fc9709a3	121	/* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
AnnaBridge	189:f392fc9709a3	122	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_HSIKERON\| RCC_CR_HSIDIV\| RCC_CR_HSIDIVF\| RCC_CR_CSION \| RCC_CR_CSIKERON \| RCC_CR_HSI48ON \
AnnaBridge	189:f392fc9709a3	123	\|RCC_CR_CSSHSEON \| RCC_CR_PLL1ON \| RCC_CR_PLL2ON \| RCC_CR_PLL3ON);
AnnaBridge	189:f392fc9709a3	124
AnnaBridge	189:f392fc9709a3	125	/* Wait for PLL1 READY bit to be reset */
AnnaBridge	189:f392fc9709a3	126	while(LL_RCC_PLL1_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	127	{}
AnnaBridge	189:f392fc9709a3	128
AnnaBridge	189:f392fc9709a3	129	/* Wait for PLL2 READY bit to be reset */
AnnaBridge	189:f392fc9709a3	130	while(LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	131	{}
AnnaBridge	189:f392fc9709a3	132
AnnaBridge	189:f392fc9709a3	133	/* Wait for PLL3 READY bit to be reset */
AnnaBridge	189:f392fc9709a3	134	while(LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	135	{}
AnnaBridge	189:f392fc9709a3	136
AnnaBridge	189:f392fc9709a3	137	/* Reset D1CFGR register */
AnnaBridge	189:f392fc9709a3	138	CLEAR_REG(RCC->D1CFGR);
AnnaBridge	189:f392fc9709a3	139
AnnaBridge	189:f392fc9709a3	140	/* Reset D2CFGR register */
AnnaBridge	189:f392fc9709a3	141	CLEAR_REG(RCC->D2CFGR);
AnnaBridge	189:f392fc9709a3	142
AnnaBridge	189:f392fc9709a3	143	/* Reset D3CFGR register */
AnnaBridge	189:f392fc9709a3	144	CLEAR_REG(RCC->D3CFGR);
AnnaBridge	189:f392fc9709a3	145
AnnaBridge	189:f392fc9709a3	146	/* Reset PLLCKSELR register */
AnnaBridge	189:f392fc9709a3	147	CLEAR_REG(RCC->PLLCKSELR);
AnnaBridge	189:f392fc9709a3	148
AnnaBridge	189:f392fc9709a3	149	/* Reset PLLCFGR register */
AnnaBridge	189:f392fc9709a3	150	CLEAR_REG(RCC->PLLCFGR);
AnnaBridge	189:f392fc9709a3	151
AnnaBridge	189:f392fc9709a3	152	/* Reset PLL1DIVR register */
AnnaBridge	189:f392fc9709a3	153	CLEAR_REG(RCC->PLL1DIVR);
AnnaBridge	189:f392fc9709a3	154
AnnaBridge	189:f392fc9709a3	155	/* Reset PLL1FRACR register */
AnnaBridge	189:f392fc9709a3	156	CLEAR_REG(RCC->PLL1FRACR);
AnnaBridge	189:f392fc9709a3	157
AnnaBridge	189:f392fc9709a3	158	/* Reset PLL2DIVR register */
AnnaBridge	189:f392fc9709a3	159	CLEAR_REG(RCC->PLL2DIVR);
AnnaBridge	189:f392fc9709a3	160
AnnaBridge	189:f392fc9709a3	161	/* Reset PLL2FRACR register */
AnnaBridge	189:f392fc9709a3	162	CLEAR_REG(RCC->PLL2FRACR);
AnnaBridge	189:f392fc9709a3	163
AnnaBridge	189:f392fc9709a3	164	/* Reset PLL3DIVR register */
AnnaBridge	189:f392fc9709a3	165	CLEAR_REG(RCC->PLL3DIVR);
AnnaBridge	189:f392fc9709a3	166
AnnaBridge	189:f392fc9709a3	167	/* Reset PLL3FRACR register */
AnnaBridge	189:f392fc9709a3	168	CLEAR_REG(RCC->PLL3FRACR);
AnnaBridge	189:f392fc9709a3	169
AnnaBridge	189:f392fc9709a3	170	/* Reset HSEBYP bit */
AnnaBridge	189:f392fc9709a3	171	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	189:f392fc9709a3	172
AnnaBridge	189:f392fc9709a3	173	/* Disable all interrupts */
AnnaBridge	189:f392fc9709a3	174	CLEAR_REG(RCC->CIER);
AnnaBridge	189:f392fc9709a3	175
AnnaBridge	189:f392fc9709a3	176	/* Clear all interrupts */
AnnaBridge	189:f392fc9709a3	177	SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC \| RCC_CICR_LSERDYC \| RCC_CICR_HSIRDYC \| RCC_CICR_HSERDYC
AnnaBridge	189:f392fc9709a3	178	\| RCC_CICR_CSIRDYC \| RCC_CICR_HSI48RDYC \| RCC_CICR_PLLRDYC \| RCC_CICR_PLL2RDYC
AnnaBridge	189:f392fc9709a3	179	\| RCC_CICR_PLL3RDYC \| RCC_CICR_LSECSSC \| RCC_CICR_HSECSSC);
AnnaBridge	189:f392fc9709a3	180
AnnaBridge	189:f392fc9709a3	181	/* Clear reset source flags */
AnnaBridge	189:f392fc9709a3	182	SET_BIT(RCC->RSR, RCC_RSR_RMVF);
AnnaBridge	189:f392fc9709a3	183	}
AnnaBridge	189:f392fc9709a3	184
AnnaBridge	189:f392fc9709a3	185	/**
AnnaBridge	189:f392fc9709a3	186	* @}
AnnaBridge	189:f392fc9709a3	187	*/
AnnaBridge	189:f392fc9709a3	188
AnnaBridge	189:f392fc9709a3	189	/** @addtogroup RCC_LL_EF_Get_Freq
AnnaBridge	189:f392fc9709a3	190	* @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
AnnaBridge	189:f392fc9709a3	191	* and different peripheral clocks available on the device.
AnnaBridge	189:f392fc9709a3	192	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
AnnaBridge	189:f392fc9709a3	193	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
AnnaBridge	189:f392fc9709a3	194	* @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(***)
AnnaBridge	189:f392fc9709a3	195	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
AnnaBridge	189:f392fc9709a3	196	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
AnnaBridge	189:f392fc9709a3	197	* @note (*) HSI_VALUE is a constant defined in header file (default value
AnnaBridge	189:f392fc9709a3	198	* 64 MHz) divider by HSIDIV, but the real value may vary depending on
AnnaBridge	189:f392fc9709a3	199	* on the variations in voltage and temperature.
AnnaBridge	189:f392fc9709a3	200	* @note (**) HSE_VALUE is a constant defined in header file (default value
AnnaBridge	189:f392fc9709a3	201	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
AnnaBridge	189:f392fc9709a3	202	* frequency of the crystal used. Otherwise, this function may
AnnaBridge	189:f392fc9709a3	203	* have wrong result.
AnnaBridge	189:f392fc9709a3	204	* @note (***) CSI_VALUE is a constant defined in header file (default value
AnnaBridge	189:f392fc9709a3	205	* 4 MHz) but the real value may vary depending on the variations
AnnaBridge	189:f392fc9709a3	206	* in voltage and temperature.
AnnaBridge	189:f392fc9709a3	207	* @note The result of this function could be incorrect when using fractional
AnnaBridge	189:f392fc9709a3	208	* value for HSE crystal.
AnnaBridge	189:f392fc9709a3	209	* @note This function can be used by the user application to compute the
AnnaBridge	189:f392fc9709a3	210	* baud-rate for the communication peripherals or configure other parameters.
AnnaBridge	189:f392fc9709a3	211	* @{
AnnaBridge	189:f392fc9709a3	212	*/
AnnaBridge	189:f392fc9709a3	213
AnnaBridge	189:f392fc9709a3	214	/**
AnnaBridge	189:f392fc9709a3	215	* @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
AnnaBridge	189:f392fc9709a3	216	* @note Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK3 and/or PCLK4 clock changes, this function
AnnaBridge	189:f392fc9709a3	217	* must be called to update structure fields. Otherwise, any
AnnaBridge	189:f392fc9709a3	218	* configuration based on this function will be incorrect.
AnnaBridge	189:f392fc9709a3	219	* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
AnnaBridge	189:f392fc9709a3	220	* @retval None
AnnaBridge	189:f392fc9709a3	221	*/
AnnaBridge	189:f392fc9709a3	222	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
AnnaBridge	189:f392fc9709a3	223	{
AnnaBridge	189:f392fc9709a3	224	/* Get SYSCLK frequency */
AnnaBridge	189:f392fc9709a3	225	RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
AnnaBridge	189:f392fc9709a3	226
AnnaBridge	189:f392fc9709a3	227	/* HCLK clock frequency */
AnnaBridge	189:f392fc9709a3	228	RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
AnnaBridge	189:f392fc9709a3	229
AnnaBridge	189:f392fc9709a3	230	/* PCLK1 clock frequency */
AnnaBridge	189:f392fc9709a3	231	RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
AnnaBridge	189:f392fc9709a3	232
AnnaBridge	189:f392fc9709a3	233	/* PCLK2 clock frequency */
AnnaBridge	189:f392fc9709a3	234	RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
AnnaBridge	189:f392fc9709a3	235
AnnaBridge	189:f392fc9709a3	236	/* PCLK3 clock frequency */
AnnaBridge	189:f392fc9709a3	237	RCC_Clocks->PCLK3_Frequency = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency);
AnnaBridge	189:f392fc9709a3	238
AnnaBridge	189:f392fc9709a3	239	/* PCLK4 clock frequency */
AnnaBridge	189:f392fc9709a3	240	RCC_Clocks->PCLK4_Frequency = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
AnnaBridge	189:f392fc9709a3	241	}
AnnaBridge	189:f392fc9709a3	242
AnnaBridge	189:f392fc9709a3	243	/**
AnnaBridge	189:f392fc9709a3	244	* @brief Return PLL1 clocks frequencies
AnnaBridge	189:f392fc9709a3	245	* @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
AnnaBridge	189:f392fc9709a3	246	* @retval None
AnnaBridge	189:f392fc9709a3	247	*/
AnnaBridge	189:f392fc9709a3	248	void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
AnnaBridge	189:f392fc9709a3	249	{
AnnaBridge	189:f392fc9709a3	250	uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
AnnaBridge	189:f392fc9709a3	251	uint32_t m, n, fracn = 0U;
AnnaBridge	189:f392fc9709a3	252
AnnaBridge	189:f392fc9709a3	253	/* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
AnnaBridge	189:f392fc9709a3	254	SYSCLK = PLL_VCO / PLLP
AnnaBridge	189:f392fc9709a3	255	*/
AnnaBridge	189:f392fc9709a3	256	pllsource = LL_RCC_PLL_GetSource();
AnnaBridge	189:f392fc9709a3	257
AnnaBridge	189:f392fc9709a3	258	switch (pllsource)
AnnaBridge	189:f392fc9709a3	259	{
AnnaBridge	189:f392fc9709a3	260	case LL_RCC_PLLSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	261	if (LL_RCC_HSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	262	{
AnnaBridge	189:f392fc9709a3	263	pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	264	}
AnnaBridge	189:f392fc9709a3	265	break;
AnnaBridge	189:f392fc9709a3	266
AnnaBridge	189:f392fc9709a3	267	case LL_RCC_PLLSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	268	if (LL_RCC_CSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	269	{
AnnaBridge	189:f392fc9709a3	270	pllinputfreq = CSI_VALUE;
AnnaBridge	189:f392fc9709a3	271	}
AnnaBridge	189:f392fc9709a3	272	break;
AnnaBridge	189:f392fc9709a3	273
AnnaBridge	189:f392fc9709a3	274	case LL_RCC_PLLSOURCE_HSE:
AnnaBridge	189:f392fc9709a3	275	if (LL_RCC_HSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	276	{
AnnaBridge	189:f392fc9709a3	277	pllinputfreq = HSE_VALUE;
AnnaBridge	189:f392fc9709a3	278	}
AnnaBridge	189:f392fc9709a3	279	break;
AnnaBridge	189:f392fc9709a3	280
AnnaBridge	189:f392fc9709a3	281	case LL_RCC_PLLSOURCE_NONE:
AnnaBridge	189:f392fc9709a3	282	default:
AnnaBridge	189:f392fc9709a3	283	/* PLL clock disabled */
AnnaBridge	189:f392fc9709a3	284	break;
AnnaBridge	189:f392fc9709a3	285	}
AnnaBridge	189:f392fc9709a3	286
AnnaBridge	189:f392fc9709a3	287	PLL_Clocks->PLL_P_Frequency = 0U;
AnnaBridge	189:f392fc9709a3	288	PLL_Clocks->PLL_Q_Frequency = 0U;
AnnaBridge	189:f392fc9709a3	289	PLL_Clocks->PLL_R_Frequency = 0U;
AnnaBridge	189:f392fc9709a3	290
AnnaBridge	189:f392fc9709a3	291	m = LL_RCC_PLL1_GetM();
AnnaBridge	189:f392fc9709a3	292	n = LL_RCC_PLL1_GetN();
AnnaBridge	189:f392fc9709a3	293	if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	294	{
AnnaBridge	189:f392fc9709a3	295	fracn = LL_RCC_PLL1_GetFRACN();
AnnaBridge	189:f392fc9709a3	296	}
AnnaBridge	189:f392fc9709a3	297
AnnaBridge	189:f392fc9709a3	298	if (m != 0U)
AnnaBridge	189:f392fc9709a3	299	{
AnnaBridge	189:f392fc9709a3	300	if (LL_RCC_PLL1P_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	301	{
AnnaBridge	189:f392fc9709a3	302	PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP());
AnnaBridge	189:f392fc9709a3	303	}
AnnaBridge	189:f392fc9709a3	304
AnnaBridge	189:f392fc9709a3	305	if (LL_RCC_PLL1Q_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	306	{
AnnaBridge	189:f392fc9709a3	307	PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ());
AnnaBridge	189:f392fc9709a3	308	}
AnnaBridge	189:f392fc9709a3	309
AnnaBridge	189:f392fc9709a3	310	if (LL_RCC_PLL1R_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	311	{
AnnaBridge	189:f392fc9709a3	312	PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR());
AnnaBridge	189:f392fc9709a3	313	}
AnnaBridge	189:f392fc9709a3	314	}
AnnaBridge	189:f392fc9709a3	315	}
AnnaBridge	189:f392fc9709a3	316
AnnaBridge	189:f392fc9709a3	317	/**
AnnaBridge	189:f392fc9709a3	318	* @brief Return PLL2 clocks frequencies
AnnaBridge	189:f392fc9709a3	319	* @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
AnnaBridge	189:f392fc9709a3	320	* @retval None
AnnaBridge	189:f392fc9709a3	321	*/
AnnaBridge	189:f392fc9709a3	322	void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
AnnaBridge	189:f392fc9709a3	323	{
AnnaBridge	189:f392fc9709a3	324	uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
AnnaBridge	189:f392fc9709a3	325	uint32_t m, n, fracn = 0U;
AnnaBridge	189:f392fc9709a3	326
AnnaBridge	189:f392fc9709a3	327	/* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
AnnaBridge	189:f392fc9709a3	328	SYSCLK = PLL_VCO / PLLP
AnnaBridge	189:f392fc9709a3	329	*/
AnnaBridge	189:f392fc9709a3	330	pllsource = LL_RCC_PLL_GetSource();
AnnaBridge	189:f392fc9709a3	331
AnnaBridge	189:f392fc9709a3	332	switch (pllsource)
AnnaBridge	189:f392fc9709a3	333	{
AnnaBridge	189:f392fc9709a3	334	case LL_RCC_PLLSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	335	if (LL_RCC_HSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	336	{
AnnaBridge	189:f392fc9709a3	337	pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	338	}
AnnaBridge	189:f392fc9709a3	339	break;
AnnaBridge	189:f392fc9709a3	340
AnnaBridge	189:f392fc9709a3	341	case LL_RCC_PLLSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	342	if (LL_RCC_CSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	343	{
AnnaBridge	189:f392fc9709a3	344	pllinputfreq = CSI_VALUE;
AnnaBridge	189:f392fc9709a3	345	}
AnnaBridge	189:f392fc9709a3	346	break;
AnnaBridge	189:f392fc9709a3	347
AnnaBridge	189:f392fc9709a3	348	case LL_RCC_PLLSOURCE_HSE:
AnnaBridge	189:f392fc9709a3	349	if (LL_RCC_HSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	350	{
AnnaBridge	189:f392fc9709a3	351	pllinputfreq = HSE_VALUE;
AnnaBridge	189:f392fc9709a3	352	}
AnnaBridge	189:f392fc9709a3	353	break;
AnnaBridge	189:f392fc9709a3	354
AnnaBridge	189:f392fc9709a3	355	case LL_RCC_PLLSOURCE_NONE:
AnnaBridge	189:f392fc9709a3	356	default:
AnnaBridge	189:f392fc9709a3	357	/* PLL clock disabled */
AnnaBridge	189:f392fc9709a3	358	break;
AnnaBridge	189:f392fc9709a3	359	}
AnnaBridge	189:f392fc9709a3	360
AnnaBridge	189:f392fc9709a3	361	PLL_Clocks->PLL_P_Frequency = 0U;
AnnaBridge	189:f392fc9709a3	362	PLL_Clocks->PLL_Q_Frequency = 0U;
AnnaBridge	189:f392fc9709a3	363	PLL_Clocks->PLL_R_Frequency = 0U;
AnnaBridge	189:f392fc9709a3	364
AnnaBridge	189:f392fc9709a3	365	m = LL_RCC_PLL2_GetM();
AnnaBridge	189:f392fc9709a3	366	n = LL_RCC_PLL2_GetN();
AnnaBridge	189:f392fc9709a3	367	if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	368	{
AnnaBridge	189:f392fc9709a3	369	fracn = LL_RCC_PLL2_GetFRACN();
AnnaBridge	189:f392fc9709a3	370	}
AnnaBridge	189:f392fc9709a3	371
AnnaBridge	189:f392fc9709a3	372	if (m != 0U)
AnnaBridge	189:f392fc9709a3	373	{
AnnaBridge	189:f392fc9709a3	374	if (LL_RCC_PLL2P_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	375	{
AnnaBridge	189:f392fc9709a3	376	PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP());
AnnaBridge	189:f392fc9709a3	377	}
AnnaBridge	189:f392fc9709a3	378
AnnaBridge	189:f392fc9709a3	379	if (LL_RCC_PLL2Q_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	380	{
AnnaBridge	189:f392fc9709a3	381	PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ());
AnnaBridge	189:f392fc9709a3	382	}
AnnaBridge	189:f392fc9709a3	383
AnnaBridge	189:f392fc9709a3	384	if (LL_RCC_PLL2R_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	385	{
AnnaBridge	189:f392fc9709a3	386	PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR());
AnnaBridge	189:f392fc9709a3	387	}
AnnaBridge	189:f392fc9709a3	388	}
AnnaBridge	189:f392fc9709a3	389	}
AnnaBridge	189:f392fc9709a3	390
AnnaBridge	189:f392fc9709a3	391	/**
AnnaBridge	189:f392fc9709a3	392	* @brief Return PLL3 clocks frequencies
AnnaBridge	189:f392fc9709a3	393	* @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
AnnaBridge	189:f392fc9709a3	394	* @retval None
AnnaBridge	189:f392fc9709a3	395	*/
AnnaBridge	189:f392fc9709a3	396	void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
AnnaBridge	189:f392fc9709a3	397	{
AnnaBridge	189:f392fc9709a3	398	uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
AnnaBridge	189:f392fc9709a3	399	uint32_t m, n, fracn = 0U;
AnnaBridge	189:f392fc9709a3	400
AnnaBridge	189:f392fc9709a3	401	/* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
AnnaBridge	189:f392fc9709a3	402	SYSCLK = PLL_VCO / PLLP
AnnaBridge	189:f392fc9709a3	403	*/
AnnaBridge	189:f392fc9709a3	404	pllsource = LL_RCC_PLL_GetSource();
AnnaBridge	189:f392fc9709a3	405
AnnaBridge	189:f392fc9709a3	406	switch (pllsource)
AnnaBridge	189:f392fc9709a3	407	{
AnnaBridge	189:f392fc9709a3	408	case LL_RCC_PLLSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	409	if (LL_RCC_HSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	410	{
AnnaBridge	189:f392fc9709a3	411	pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	412	}
AnnaBridge	189:f392fc9709a3	413	break;
AnnaBridge	189:f392fc9709a3	414
AnnaBridge	189:f392fc9709a3	415	case LL_RCC_PLLSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	416	if (LL_RCC_CSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	417	{
AnnaBridge	189:f392fc9709a3	418	pllinputfreq = CSI_VALUE;
AnnaBridge	189:f392fc9709a3	419	}
AnnaBridge	189:f392fc9709a3	420	break;
AnnaBridge	189:f392fc9709a3	421
AnnaBridge	189:f392fc9709a3	422	case LL_RCC_PLLSOURCE_HSE:
AnnaBridge	189:f392fc9709a3	423	if (LL_RCC_HSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	424	{
AnnaBridge	189:f392fc9709a3	425	pllinputfreq = HSE_VALUE;
AnnaBridge	189:f392fc9709a3	426	}
AnnaBridge	189:f392fc9709a3	427	break;
AnnaBridge	189:f392fc9709a3	428
AnnaBridge	189:f392fc9709a3	429	case LL_RCC_PLLSOURCE_NONE:
AnnaBridge	189:f392fc9709a3	430	default:
AnnaBridge	189:f392fc9709a3	431	/* PLL clock disabled */
AnnaBridge	189:f392fc9709a3	432	break;
AnnaBridge	189:f392fc9709a3	433	}
AnnaBridge	189:f392fc9709a3	434
AnnaBridge	189:f392fc9709a3	435	PLL_Clocks->PLL_P_Frequency = 0U;
AnnaBridge	189:f392fc9709a3	436	PLL_Clocks->PLL_Q_Frequency = 0U;
AnnaBridge	189:f392fc9709a3	437	PLL_Clocks->PLL_R_Frequency = 0U;
AnnaBridge	189:f392fc9709a3	438
AnnaBridge	189:f392fc9709a3	439	m = LL_RCC_PLL3_GetM();
AnnaBridge	189:f392fc9709a3	440	n = LL_RCC_PLL3_GetN();
AnnaBridge	189:f392fc9709a3	441	if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	442	{
AnnaBridge	189:f392fc9709a3	443	fracn = LL_RCC_PLL3_GetFRACN();
AnnaBridge	189:f392fc9709a3	444	}
AnnaBridge	189:f392fc9709a3	445
AnnaBridge	189:f392fc9709a3	446	if ((m != 0U) && (pllinputfreq != 0U))
AnnaBridge	189:f392fc9709a3	447	{
AnnaBridge	189:f392fc9709a3	448	if (LL_RCC_PLL3P_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	449	{
AnnaBridge	189:f392fc9709a3	450	PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP());
AnnaBridge	189:f392fc9709a3	451	}
AnnaBridge	189:f392fc9709a3	452
AnnaBridge	189:f392fc9709a3	453	if (LL_RCC_PLL3Q_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	454	{
AnnaBridge	189:f392fc9709a3	455	PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ());
AnnaBridge	189:f392fc9709a3	456	}
AnnaBridge	189:f392fc9709a3	457
AnnaBridge	189:f392fc9709a3	458	if (LL_RCC_PLL3R_IsEnabled() != 0U)
AnnaBridge	189:f392fc9709a3	459	{
AnnaBridge	189:f392fc9709a3	460	PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR());
AnnaBridge	189:f392fc9709a3	461	}
AnnaBridge	189:f392fc9709a3	462	}
AnnaBridge	189:f392fc9709a3	463	}
AnnaBridge	189:f392fc9709a3	464
AnnaBridge	189:f392fc9709a3	465	/**
AnnaBridge	189:f392fc9709a3	466	* @brief Helper function to calculate the PLL frequency output
AnnaBridge	189:f392fc9709a3	467	* @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
AnnaBridge	189:f392fc9709a3	468	* @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
AnnaBridge	189:f392fc9709a3	469	* @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
AnnaBridge	189:f392fc9709a3	470	* @param M Between 1 and 63
AnnaBridge	189:f392fc9709a3	471	* @param N Between 4 and 512
AnnaBridge	189:f392fc9709a3	472	* @param FRACN Between 0 and 0x1FFF
AnnaBridge	189:f392fc9709a3	473	* @param PQR VCO output divider (P, Q or R)
AnnaBridge	189:f392fc9709a3	474	* Between 1 and 128, except for PLL1P Odd value not allowed
AnnaBridge	189:f392fc9709a3	475	* @retval PLL1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	476	*/
AnnaBridge	189:f392fc9709a3	477	uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
AnnaBridge	189:f392fc9709a3	478	{
AnnaBridge	189:f392fc9709a3	479	float_t freq;
AnnaBridge	189:f392fc9709a3	480
AnnaBridge	189:f392fc9709a3	481	freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN/(float_t)0x2000));
AnnaBridge	189:f392fc9709a3	482
AnnaBridge	189:f392fc9709a3	483	freq = freq/(float_t)PQR;
AnnaBridge	189:f392fc9709a3	484
AnnaBridge	189:f392fc9709a3	485	return (uint32_t)freq;
AnnaBridge	189:f392fc9709a3	486	}
AnnaBridge	189:f392fc9709a3	487
AnnaBridge	189:f392fc9709a3	488	/**
AnnaBridge	189:f392fc9709a3	489	* @brief Return USARTx clock frequency
AnnaBridge	189:f392fc9709a3	490	* @param USARTxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	491	* @arg @ref LL_RCC_USART16_CLKSOURCE
AnnaBridge	189:f392fc9709a3	492	* @arg @ref LL_RCC_USART234578_CLKSOURCE
AnnaBridge	189:f392fc9709a3	493	* @retval USART clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	494	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	495	*/
AnnaBridge	189:f392fc9709a3	496	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
AnnaBridge	189:f392fc9709a3	497	{
AnnaBridge	189:f392fc9709a3	498	uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	499	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	500
AnnaBridge	189:f392fc9709a3	501	/* Check parameter */
AnnaBridge	189:f392fc9709a3	502	assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
AnnaBridge	189:f392fc9709a3	503
AnnaBridge	189:f392fc9709a3	504	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
AnnaBridge	189:f392fc9709a3	505	{
AnnaBridge	189:f392fc9709a3	506	case LL_RCC_USART16_CLKSOURCE_PCLK2:
AnnaBridge	189:f392fc9709a3	507	usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	508	break;
AnnaBridge	189:f392fc9709a3	509
AnnaBridge	189:f392fc9709a3	510	case LL_RCC_USART234578_CLKSOURCE_PCLK1:
AnnaBridge	189:f392fc9709a3	511	usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	512	break;
AnnaBridge	189:f392fc9709a3	513
AnnaBridge	189:f392fc9709a3	514	case LL_RCC_USART16_CLKSOURCE_PLL2Q:
AnnaBridge	189:f392fc9709a3	515	case LL_RCC_USART234578_CLKSOURCE_PLL2Q:
AnnaBridge	189:f392fc9709a3	516	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	517	{
AnnaBridge	189:f392fc9709a3	518	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	519	usart_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	520	}
AnnaBridge	189:f392fc9709a3	521	break;
AnnaBridge	189:f392fc9709a3	522
AnnaBridge	189:f392fc9709a3	523	case LL_RCC_USART16_CLKSOURCE_PLL3Q:
AnnaBridge	189:f392fc9709a3	524	case LL_RCC_USART234578_CLKSOURCE_PLL3Q:
AnnaBridge	189:f392fc9709a3	525	if (LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	526	{
AnnaBridge	189:f392fc9709a3	527	LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	528	usart_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	529	}
AnnaBridge	189:f392fc9709a3	530	break;
AnnaBridge	189:f392fc9709a3	531
AnnaBridge	189:f392fc9709a3	532	case LL_RCC_USART16_CLKSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	533	case LL_RCC_USART234578_CLKSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	534	if (LL_RCC_HSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	535	{
AnnaBridge	189:f392fc9709a3	536	usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	537	}
AnnaBridge	189:f392fc9709a3	538	break;
AnnaBridge	189:f392fc9709a3	539
AnnaBridge	189:f392fc9709a3	540	case LL_RCC_USART16_CLKSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	541	case LL_RCC_USART234578_CLKSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	542	if (LL_RCC_CSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	543	{
AnnaBridge	189:f392fc9709a3	544	usart_frequency = CSI_VALUE;
AnnaBridge	189:f392fc9709a3	545	}
AnnaBridge	189:f392fc9709a3	546	break;
AnnaBridge	189:f392fc9709a3	547
AnnaBridge	189:f392fc9709a3	548	case LL_RCC_USART16_CLKSOURCE_LSE:
AnnaBridge	189:f392fc9709a3	549	case LL_RCC_USART234578_CLKSOURCE_LSE:
AnnaBridge	189:f392fc9709a3	550	if (LL_RCC_LSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	551	{
AnnaBridge	189:f392fc9709a3	552	usart_frequency = LSE_VALUE;
AnnaBridge	189:f392fc9709a3	553	}
AnnaBridge	189:f392fc9709a3	554	break;
AnnaBridge	189:f392fc9709a3	555
AnnaBridge	189:f392fc9709a3	556	default:
AnnaBridge	189:f392fc9709a3	557	/* Kernel clock disabled */
AnnaBridge	189:f392fc9709a3	558	break;
AnnaBridge	189:f392fc9709a3	559	}
AnnaBridge	189:f392fc9709a3	560
AnnaBridge	189:f392fc9709a3	561	return usart_frequency;
AnnaBridge	189:f392fc9709a3	562	}
AnnaBridge	189:f392fc9709a3	563
AnnaBridge	189:f392fc9709a3	564	/**
AnnaBridge	189:f392fc9709a3	565	* @brief Return LPUART clock frequency
AnnaBridge	189:f392fc9709a3	566	* @param LPUARTxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	567	* @arg @ref LL_RCC_LPUART1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	568	* @retval LPUART clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	569	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	570	*/
AnnaBridge	189:f392fc9709a3	571	uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
AnnaBridge	189:f392fc9709a3	572	{
AnnaBridge	189:f392fc9709a3	573	uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	574	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	575
AnnaBridge	189:f392fc9709a3	576	switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
AnnaBridge	189:f392fc9709a3	577	{
AnnaBridge	189:f392fc9709a3	578	case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
AnnaBridge	189:f392fc9709a3	579	lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	580	break;
AnnaBridge	189:f392fc9709a3	581
AnnaBridge	189:f392fc9709a3	582	case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
AnnaBridge	189:f392fc9709a3	583	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	584	{
AnnaBridge	189:f392fc9709a3	585	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	586	lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	587	}
AnnaBridge	189:f392fc9709a3	588	break;
AnnaBridge	189:f392fc9709a3	589
AnnaBridge	189:f392fc9709a3	590	case LL_RCC_LPUART1_CLKSOURCE_PLL3Q:
AnnaBridge	189:f392fc9709a3	591	if (LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	592	{
AnnaBridge	189:f392fc9709a3	593	LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	594	lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	595	}
AnnaBridge	189:f392fc9709a3	596	break;
AnnaBridge	189:f392fc9709a3	597
AnnaBridge	189:f392fc9709a3	598	case LL_RCC_LPUART1_CLKSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	599	if (LL_RCC_HSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	600	{
AnnaBridge	189:f392fc9709a3	601	lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	602	}
AnnaBridge	189:f392fc9709a3	603	break;
AnnaBridge	189:f392fc9709a3	604
AnnaBridge	189:f392fc9709a3	605	case LL_RCC_LPUART1_CLKSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	606	if (LL_RCC_CSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	607	{
AnnaBridge	189:f392fc9709a3	608	lpuart_frequency = CSI_VALUE;
AnnaBridge	189:f392fc9709a3	609	}
AnnaBridge	189:f392fc9709a3	610	break;
AnnaBridge	189:f392fc9709a3	611
AnnaBridge	189:f392fc9709a3	612	case LL_RCC_LPUART1_CLKSOURCE_LSE:
AnnaBridge	189:f392fc9709a3	613	if (LL_RCC_LSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	614	{
AnnaBridge	189:f392fc9709a3	615	lpuart_frequency = LSE_VALUE;
AnnaBridge	189:f392fc9709a3	616	}
AnnaBridge	189:f392fc9709a3	617	break;
AnnaBridge	189:f392fc9709a3	618
AnnaBridge	189:f392fc9709a3	619	default:
AnnaBridge	189:f392fc9709a3	620	/* Kernel clock disabled */
AnnaBridge	189:f392fc9709a3	621	break;
AnnaBridge	189:f392fc9709a3	622	}
AnnaBridge	189:f392fc9709a3	623
AnnaBridge	189:f392fc9709a3	624	return lpuart_frequency;
AnnaBridge	189:f392fc9709a3	625	}
AnnaBridge	189:f392fc9709a3	626
AnnaBridge	189:f392fc9709a3	627	/**
AnnaBridge	189:f392fc9709a3	628	* @brief Return I2Cx clock frequency
AnnaBridge	189:f392fc9709a3	629	* @param I2CxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	630	* @arg @ref LL_RCC_I2C123_CLKSOURCE
AnnaBridge	189:f392fc9709a3	631	* @arg @ref LL_RCC_I2C4_CLKSOURCE
AnnaBridge	189:f392fc9709a3	632	* @retval I2C clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	633	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	634	*/
AnnaBridge	189:f392fc9709a3	635	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
AnnaBridge	189:f392fc9709a3	636	{
AnnaBridge	189:f392fc9709a3	637	uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	638	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	639
AnnaBridge	189:f392fc9709a3	640	/* Check parameter */
AnnaBridge	189:f392fc9709a3	641	assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
AnnaBridge	189:f392fc9709a3	642
AnnaBridge	189:f392fc9709a3	643	switch (LL_RCC_GetI2CClockSource(I2CxSource))
AnnaBridge	189:f392fc9709a3	644	{
AnnaBridge	189:f392fc9709a3	645	case LL_RCC_I2C123_CLKSOURCE_PCLK1:
AnnaBridge	189:f392fc9709a3	646	i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	647	break;
AnnaBridge	189:f392fc9709a3	648
AnnaBridge	189:f392fc9709a3	649	case LL_RCC_I2C4_CLKSOURCE_PCLK4:
AnnaBridge	189:f392fc9709a3	650	i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	651	break;
AnnaBridge	189:f392fc9709a3	652
AnnaBridge	189:f392fc9709a3	653	case LL_RCC_I2C123_CLKSOURCE_PLL3R:
AnnaBridge	189:f392fc9709a3	654	case LL_RCC_I2C4_CLKSOURCE_PLL3R:
AnnaBridge	189:f392fc9709a3	655	if (LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	656	{
AnnaBridge	189:f392fc9709a3	657	LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	658	i2c_frequency = PLL_Clocks.PLL_R_Frequency;
AnnaBridge	189:f392fc9709a3	659	}
AnnaBridge	189:f392fc9709a3	660	break;
AnnaBridge	189:f392fc9709a3	661
AnnaBridge	189:f392fc9709a3	662	case LL_RCC_I2C123_CLKSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	663	case LL_RCC_I2C4_CLKSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	664	if (LL_RCC_HSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	665	{
AnnaBridge	189:f392fc9709a3	666	i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	667	}
AnnaBridge	189:f392fc9709a3	668	break;
AnnaBridge	189:f392fc9709a3	669
AnnaBridge	189:f392fc9709a3	670	case LL_RCC_I2C123_CLKSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	671	case LL_RCC_I2C4_CLKSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	672	if (LL_RCC_CSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	673	{
AnnaBridge	189:f392fc9709a3	674	i2c_frequency = CSI_VALUE;
AnnaBridge	189:f392fc9709a3	675	}
AnnaBridge	189:f392fc9709a3	676	break;
AnnaBridge	189:f392fc9709a3	677
AnnaBridge	189:f392fc9709a3	678	default:
AnnaBridge	189:f392fc9709a3	679	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	680	break;
AnnaBridge	189:f392fc9709a3	681	}
AnnaBridge	189:f392fc9709a3	682
AnnaBridge	189:f392fc9709a3	683	return i2c_frequency;
AnnaBridge	189:f392fc9709a3	684	}
AnnaBridge	189:f392fc9709a3	685
AnnaBridge	189:f392fc9709a3	686	/**
AnnaBridge	189:f392fc9709a3	687	* @brief Return LPTIMx clock frequency
AnnaBridge	189:f392fc9709a3	688	* @param LPTIMxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	689	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	690	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE
AnnaBridge	189:f392fc9709a3	691	* @arg @ref LL_RCC_LPTIM345_CLKSOURCE
AnnaBridge	189:f392fc9709a3	692	* @retval LPTIM clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	693	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	694	*/
AnnaBridge	189:f392fc9709a3	695	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
AnnaBridge	189:f392fc9709a3	696	{
AnnaBridge	189:f392fc9709a3	697	uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	698	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	699
AnnaBridge	189:f392fc9709a3	700	/* Check parameter */
AnnaBridge	189:f392fc9709a3	701	assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
AnnaBridge	189:f392fc9709a3	702
AnnaBridge	189:f392fc9709a3	703	switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
AnnaBridge	189:f392fc9709a3	704	{
AnnaBridge	189:f392fc9709a3	705	case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
AnnaBridge	189:f392fc9709a3	706	lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	707	break;
AnnaBridge	189:f392fc9709a3	708
AnnaBridge	189:f392fc9709a3	709	case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
AnnaBridge	189:f392fc9709a3	710	case LL_RCC_LPTIM345_CLKSOURCE_PCLK4:
AnnaBridge	189:f392fc9709a3	711	lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	712	break;
AnnaBridge	189:f392fc9709a3	713
AnnaBridge	189:f392fc9709a3	714	case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
AnnaBridge	189:f392fc9709a3	715	case LL_RCC_LPTIM2_CLKSOURCE_PLL2P:
AnnaBridge	189:f392fc9709a3	716	case LL_RCC_LPTIM345_CLKSOURCE_PLL2P:
AnnaBridge	189:f392fc9709a3	717	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	718	{
AnnaBridge	189:f392fc9709a3	719	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	720	lptim_frequency = PLL_Clocks.PLL_P_Frequency;
AnnaBridge	189:f392fc9709a3	721	}
AnnaBridge	189:f392fc9709a3	722	break;
AnnaBridge	189:f392fc9709a3	723
AnnaBridge	189:f392fc9709a3	724	case LL_RCC_LPTIM1_CLKSOURCE_PLL3R:
AnnaBridge	189:f392fc9709a3	725	case LL_RCC_LPTIM2_CLKSOURCE_PLL3R:
AnnaBridge	189:f392fc9709a3	726	case LL_RCC_LPTIM345_CLKSOURCE_PLL3R:
AnnaBridge	189:f392fc9709a3	727	if (LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	728	{
AnnaBridge	189:f392fc9709a3	729	LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	730	lptim_frequency = PLL_Clocks.PLL_R_Frequency;
AnnaBridge	189:f392fc9709a3	731	}
AnnaBridge	189:f392fc9709a3	732	break;
AnnaBridge	189:f392fc9709a3	733
AnnaBridge	189:f392fc9709a3	734	case LL_RCC_LPTIM1_CLKSOURCE_LSE:
AnnaBridge	189:f392fc9709a3	735	case LL_RCC_LPTIM2_CLKSOURCE_LSE:
AnnaBridge	189:f392fc9709a3	736	case LL_RCC_LPTIM345_CLKSOURCE_LSE:
AnnaBridge	189:f392fc9709a3	737	if (LL_RCC_LSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	738	{
AnnaBridge	189:f392fc9709a3	739	lptim_frequency = LSE_VALUE;
AnnaBridge	189:f392fc9709a3	740	}
AnnaBridge	189:f392fc9709a3	741	break;
AnnaBridge	189:f392fc9709a3	742
AnnaBridge	189:f392fc9709a3	743	case LL_RCC_LPTIM1_CLKSOURCE_LSI:
AnnaBridge	189:f392fc9709a3	744	case LL_RCC_LPTIM2_CLKSOURCE_LSI:
AnnaBridge	189:f392fc9709a3	745	case LL_RCC_LPTIM345_CLKSOURCE_LSI:
AnnaBridge	189:f392fc9709a3	746	if (LL_RCC_LSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	747	{
AnnaBridge	189:f392fc9709a3	748	lptim_frequency = LSI_VALUE;
AnnaBridge	189:f392fc9709a3	749	}
AnnaBridge	189:f392fc9709a3	750	break;
AnnaBridge	189:f392fc9709a3	751
AnnaBridge	189:f392fc9709a3	752	case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	753	case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	754	case LL_RCC_LPTIM345_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	755	lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
AnnaBridge	189:f392fc9709a3	756	break;
AnnaBridge	189:f392fc9709a3	757
AnnaBridge	189:f392fc9709a3	758	default:
AnnaBridge	189:f392fc9709a3	759	/* Kernel clock disabled */
AnnaBridge	189:f392fc9709a3	760	break;
AnnaBridge	189:f392fc9709a3	761	}
AnnaBridge	189:f392fc9709a3	762
AnnaBridge	189:f392fc9709a3	763	return lptim_frequency;
AnnaBridge	189:f392fc9709a3	764	}
AnnaBridge	189:f392fc9709a3	765
AnnaBridge	189:f392fc9709a3	766	/**
AnnaBridge	189:f392fc9709a3	767	* @brief Return SAIx clock frequency
AnnaBridge	189:f392fc9709a3	768	* @param SAIxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	769	* @arg @ref LL_RCC_SAI1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	770	* @arg @ref LL_RCC_SAI23_CLKSOURCE
AnnaBridge	189:f392fc9709a3	771	* @arg @ref LL_RCC_SAI4A_CLKSOURCE
AnnaBridge	189:f392fc9709a3	772	* @arg @ref LL_RCC_SAI4B_CLKSOURCE
AnnaBridge	189:f392fc9709a3	773	* @retval SAI clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	774	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	775	*/
AnnaBridge	189:f392fc9709a3	776	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
AnnaBridge	189:f392fc9709a3	777	{
AnnaBridge	189:f392fc9709a3	778	uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	779	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	780
AnnaBridge	189:f392fc9709a3	781	/* Check parameter */
AnnaBridge	189:f392fc9709a3	782	assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
AnnaBridge	189:f392fc9709a3	783
AnnaBridge	189:f392fc9709a3	784	switch (LL_RCC_GetSAIClockSource(SAIxSource))
AnnaBridge	189:f392fc9709a3	785	{
AnnaBridge	189:f392fc9709a3	786	case LL_RCC_SAI1_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	787	case LL_RCC_SAI23_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	788	case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	789	case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	790	if (LL_RCC_PLL1_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	791	{
AnnaBridge	189:f392fc9709a3	792	LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	793	sai_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	794	}
AnnaBridge	189:f392fc9709a3	795	break;
AnnaBridge	189:f392fc9709a3	796
AnnaBridge	189:f392fc9709a3	797	case LL_RCC_SAI1_CLKSOURCE_PLL2P:
AnnaBridge	189:f392fc9709a3	798	case LL_RCC_SAI23_CLKSOURCE_PLL2P:
AnnaBridge	189:f392fc9709a3	799	case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
AnnaBridge	189:f392fc9709a3	800	case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
AnnaBridge	189:f392fc9709a3	801	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	802	{
AnnaBridge	189:f392fc9709a3	803	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	804	sai_frequency = PLL_Clocks.PLL_P_Frequency;
AnnaBridge	189:f392fc9709a3	805	}
AnnaBridge	189:f392fc9709a3	806	break;
AnnaBridge	189:f392fc9709a3	807
AnnaBridge	189:f392fc9709a3	808	case LL_RCC_SAI1_CLKSOURCE_PLL3P:
AnnaBridge	189:f392fc9709a3	809	case LL_RCC_SAI23_CLKSOURCE_PLL3P:
AnnaBridge	189:f392fc9709a3	810	case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
AnnaBridge	189:f392fc9709a3	811	case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
AnnaBridge	189:f392fc9709a3	812	if (LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	813	{
AnnaBridge	189:f392fc9709a3	814	LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	815	sai_frequency = PLL_Clocks.PLL_P_Frequency;
AnnaBridge	189:f392fc9709a3	816	}
AnnaBridge	189:f392fc9709a3	817	break;
AnnaBridge	189:f392fc9709a3	818
AnnaBridge	189:f392fc9709a3	819	case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
AnnaBridge	189:f392fc9709a3	820	case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN:
AnnaBridge	189:f392fc9709a3	821	case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
AnnaBridge	189:f392fc9709a3	822	case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
AnnaBridge	189:f392fc9709a3	823	sai_frequency = EXTERNAL_CLOCK_VALUE;
AnnaBridge	189:f392fc9709a3	824	break;
AnnaBridge	189:f392fc9709a3	825
AnnaBridge	189:f392fc9709a3	826	case LL_RCC_SAI1_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	827	case LL_RCC_SAI23_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	828	case LL_RCC_SAI4A_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	829	case LL_RCC_SAI4B_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	830	sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
AnnaBridge	189:f392fc9709a3	831	break;
AnnaBridge	189:f392fc9709a3	832	default:
AnnaBridge	189:f392fc9709a3	833	/* Kernel clock disabled */
AnnaBridge	189:f392fc9709a3	834	break;
AnnaBridge	189:f392fc9709a3	835	}
AnnaBridge	189:f392fc9709a3	836
AnnaBridge	189:f392fc9709a3	837	return sai_frequency;
AnnaBridge	189:f392fc9709a3	838	}
AnnaBridge	189:f392fc9709a3	839
AnnaBridge	189:f392fc9709a3	840	/**
AnnaBridge	189:f392fc9709a3	841	* @brief Return ADC clock frequency
AnnaBridge	189:f392fc9709a3	842	* @param ADCxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	843	* @arg @ref LL_RCC_ADC_CLKSOURCE
AnnaBridge	189:f392fc9709a3	844	* @retval ADC clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	845	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	846	*/
AnnaBridge	189:f392fc9709a3	847	uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
AnnaBridge	189:f392fc9709a3	848	{
AnnaBridge	189:f392fc9709a3	849	uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	850	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	851
AnnaBridge	189:f392fc9709a3	852	switch (LL_RCC_GetADCClockSource(ADCxSource))
AnnaBridge	189:f392fc9709a3	853	{
AnnaBridge	189:f392fc9709a3	854	case LL_RCC_ADC_CLKSOURCE_PLL2P:
AnnaBridge	189:f392fc9709a3	855	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	856	{
AnnaBridge	189:f392fc9709a3	857	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	858	adc_frequency = PLL_Clocks.PLL_P_Frequency;
AnnaBridge	189:f392fc9709a3	859	}
AnnaBridge	189:f392fc9709a3	860	break;
AnnaBridge	189:f392fc9709a3	861
AnnaBridge	189:f392fc9709a3	862	case LL_RCC_ADC_CLKSOURCE_PLL3R:
AnnaBridge	189:f392fc9709a3	863	if (LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	864	{
AnnaBridge	189:f392fc9709a3	865	LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	866	adc_frequency = PLL_Clocks.PLL_R_Frequency;
AnnaBridge	189:f392fc9709a3	867	}
AnnaBridge	189:f392fc9709a3	868	break;
AnnaBridge	189:f392fc9709a3	869
AnnaBridge	189:f392fc9709a3	870	case LL_RCC_ADC_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	871	adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
AnnaBridge	189:f392fc9709a3	872	break;
AnnaBridge	189:f392fc9709a3	873
AnnaBridge	189:f392fc9709a3	874	default:
AnnaBridge	189:f392fc9709a3	875	/* Kernel clock disabled */
AnnaBridge	189:f392fc9709a3	876	break;
AnnaBridge	189:f392fc9709a3	877	}
AnnaBridge	189:f392fc9709a3	878
AnnaBridge	189:f392fc9709a3	879	return adc_frequency;
AnnaBridge	189:f392fc9709a3	880	}
AnnaBridge	189:f392fc9709a3	881
AnnaBridge	189:f392fc9709a3	882	/**
AnnaBridge	189:f392fc9709a3	883	* @brief Return SDMMC clock frequency
AnnaBridge	189:f392fc9709a3	884	* @param SDMMCxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	885	* @arg @ref LL_RCC_SDMMC_CLKSOURCE
AnnaBridge	189:f392fc9709a3	886	* @retval SDMMC clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	887	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	888	*/
AnnaBridge	189:f392fc9709a3	889	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
AnnaBridge	189:f392fc9709a3	890	{
AnnaBridge	189:f392fc9709a3	891	uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	892	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	893
AnnaBridge	189:f392fc9709a3	894	switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
AnnaBridge	189:f392fc9709a3	895	{
AnnaBridge	189:f392fc9709a3	896	case LL_RCC_SDMMC_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	897	if (LL_RCC_PLL1_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	898	{
AnnaBridge	189:f392fc9709a3	899	LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	900	sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	901	}
AnnaBridge	189:f392fc9709a3	902	break;
AnnaBridge	189:f392fc9709a3	903
AnnaBridge	189:f392fc9709a3	904	case LL_RCC_SDMMC_CLKSOURCE_PLL2R:
AnnaBridge	189:f392fc9709a3	905	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	906	{
AnnaBridge	189:f392fc9709a3	907	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	908	sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
AnnaBridge	189:f392fc9709a3	909	}
AnnaBridge	189:f392fc9709a3	910	break;
AnnaBridge	189:f392fc9709a3	911
AnnaBridge	189:f392fc9709a3	912	default:
AnnaBridge	189:f392fc9709a3	913	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	914	break;
AnnaBridge	189:f392fc9709a3	915	}
AnnaBridge	189:f392fc9709a3	916
AnnaBridge	189:f392fc9709a3	917	return sdmmc_frequency;
AnnaBridge	189:f392fc9709a3	918	}
AnnaBridge	189:f392fc9709a3	919
AnnaBridge	189:f392fc9709a3	920	/**
AnnaBridge	189:f392fc9709a3	921	* @brief Return RNG clock frequency
AnnaBridge	189:f392fc9709a3	922	* @param RNGxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	923	* @arg @ref LL_RCC_RNG_CLKSOURCE
AnnaBridge	189:f392fc9709a3	924	* @retval RNG clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	925	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	926	*/
AnnaBridge	189:f392fc9709a3	927	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
AnnaBridge	189:f392fc9709a3	928	{
AnnaBridge	189:f392fc9709a3	929	uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	930	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	931
AnnaBridge	189:f392fc9709a3	932	switch (LL_RCC_GetRNGClockSource(RNGxSource))
AnnaBridge	189:f392fc9709a3	933	{
AnnaBridge	189:f392fc9709a3	934	case LL_RCC_RNG_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	935	if (LL_RCC_PLL1_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	936	{
AnnaBridge	189:f392fc9709a3	937	LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	938	rng_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	939	}
AnnaBridge	189:f392fc9709a3	940	break;
AnnaBridge	189:f392fc9709a3	941
AnnaBridge	189:f392fc9709a3	942	case LL_RCC_RNG_CLKSOURCE_HSI48:
AnnaBridge	189:f392fc9709a3	943	if (LL_RCC_HSI48_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	944	{
AnnaBridge	189:f392fc9709a3	945	rng_frequency = 48000000U;
AnnaBridge	189:f392fc9709a3	946	}
AnnaBridge	189:f392fc9709a3	947	break;
AnnaBridge	189:f392fc9709a3	948
AnnaBridge	189:f392fc9709a3	949	case LL_RCC_RNG_CLKSOURCE_LSE:
AnnaBridge	189:f392fc9709a3	950	if (LL_RCC_LSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	951	{
AnnaBridge	189:f392fc9709a3	952	rng_frequency = LSE_VALUE;
AnnaBridge	189:f392fc9709a3	953	}
AnnaBridge	189:f392fc9709a3	954	break;
AnnaBridge	189:f392fc9709a3	955
AnnaBridge	189:f392fc9709a3	956	case LL_RCC_RNG_CLKSOURCE_LSI:
AnnaBridge	189:f392fc9709a3	957	if (LL_RCC_LSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	958	{
AnnaBridge	189:f392fc9709a3	959	rng_frequency = LSI_VALUE;
AnnaBridge	189:f392fc9709a3	960	}
AnnaBridge	189:f392fc9709a3	961	break;
AnnaBridge	189:f392fc9709a3	962
AnnaBridge	189:f392fc9709a3	963	default:
AnnaBridge	189:f392fc9709a3	964	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	965	break;
AnnaBridge	189:f392fc9709a3	966	}
AnnaBridge	189:f392fc9709a3	967
AnnaBridge	189:f392fc9709a3	968	return rng_frequency;
AnnaBridge	189:f392fc9709a3	969	}
AnnaBridge	189:f392fc9709a3	970
AnnaBridge	189:f392fc9709a3	971	/**
AnnaBridge	189:f392fc9709a3	972	* @brief Return CEC clock frequency
AnnaBridge	189:f392fc9709a3	973	* @param CECxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	974	* @arg @ref LL_RCC_RNG_CLKSOURCE
AnnaBridge	189:f392fc9709a3	975	* @retval CEC clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	976	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	977	*/
AnnaBridge	189:f392fc9709a3	978	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
AnnaBridge	189:f392fc9709a3	979	{
AnnaBridge	189:f392fc9709a3	980	uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	981
AnnaBridge	189:f392fc9709a3	982	switch (LL_RCC_GetCECClockSource(CECxSource))
AnnaBridge	189:f392fc9709a3	983	{
AnnaBridge	189:f392fc9709a3	984	case LL_RCC_CEC_CLKSOURCE_LSE:
AnnaBridge	189:f392fc9709a3	985	if (LL_RCC_LSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	986	{
AnnaBridge	189:f392fc9709a3	987	cec_frequency = LSE_VALUE;
AnnaBridge	189:f392fc9709a3	988	}
AnnaBridge	189:f392fc9709a3	989	break;
AnnaBridge	189:f392fc9709a3	990
AnnaBridge	189:f392fc9709a3	991	case LL_RCC_CEC_CLKSOURCE_LSI:
AnnaBridge	189:f392fc9709a3	992	if (LL_RCC_LSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	993	{
AnnaBridge	189:f392fc9709a3	994	cec_frequency = LSI_VALUE;
AnnaBridge	189:f392fc9709a3	995	}
AnnaBridge	189:f392fc9709a3	996	break;
AnnaBridge	189:f392fc9709a3	997
AnnaBridge	189:f392fc9709a3	998	case LL_RCC_CEC_CLKSOURCE_CSI_DIV122:
AnnaBridge	189:f392fc9709a3	999	if (LL_RCC_CSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1000	{
AnnaBridge	189:f392fc9709a3	1001	cec_frequency = CSI_VALUE / 122U;
AnnaBridge	189:f392fc9709a3	1002	}
AnnaBridge	189:f392fc9709a3	1003	break;
AnnaBridge	189:f392fc9709a3	1004
AnnaBridge	189:f392fc9709a3	1005	default:
AnnaBridge	189:f392fc9709a3	1006	/* Kernel clock disabled */
AnnaBridge	189:f392fc9709a3	1007	break;
AnnaBridge	189:f392fc9709a3	1008	}
AnnaBridge	189:f392fc9709a3	1009
AnnaBridge	189:f392fc9709a3	1010	return cec_frequency;
AnnaBridge	189:f392fc9709a3	1011	}
AnnaBridge	189:f392fc9709a3	1012
AnnaBridge	189:f392fc9709a3	1013	/**
AnnaBridge	189:f392fc9709a3	1014	* @brief Return USB clock frequency
AnnaBridge	189:f392fc9709a3	1015	* @param USBxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1016	* @arg @ref LL_RCC_USB_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1017	* @retval USB clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1018	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
AnnaBridge	189:f392fc9709a3	1019	*/
AnnaBridge	189:f392fc9709a3	1020	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
AnnaBridge	189:f392fc9709a3	1021	{
AnnaBridge	189:f392fc9709a3	1022	uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	1023	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	1024
AnnaBridge	189:f392fc9709a3	1025	switch (LL_RCC_GetUSBClockSource(USBxSource))
AnnaBridge	189:f392fc9709a3	1026	{
AnnaBridge	189:f392fc9709a3	1027	case LL_RCC_USB_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	1028	if (LL_RCC_PLL1_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1029	{
AnnaBridge	189:f392fc9709a3	1030	LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1031	usb_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	1032	}
AnnaBridge	189:f392fc9709a3	1033	break;
AnnaBridge	189:f392fc9709a3	1034
AnnaBridge	189:f392fc9709a3	1035	case LL_RCC_USB_CLKSOURCE_PLL3Q:
AnnaBridge	189:f392fc9709a3	1036	if (LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1037	{
AnnaBridge	189:f392fc9709a3	1038	LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1039	usb_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	1040	}
AnnaBridge	189:f392fc9709a3	1041	break;
AnnaBridge	189:f392fc9709a3	1042
AnnaBridge	189:f392fc9709a3	1043	case LL_RCC_USB_CLKSOURCE_HSI48:
AnnaBridge	189:f392fc9709a3	1044	if (LL_RCC_HSI48_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1045	{
AnnaBridge	189:f392fc9709a3	1046	usb_frequency = 48000000U;
AnnaBridge	189:f392fc9709a3	1047	}
AnnaBridge	189:f392fc9709a3	1048	break;
AnnaBridge	189:f392fc9709a3	1049
AnnaBridge	189:f392fc9709a3	1050	case LL_RCC_USB_CLKSOURCE_DISABLE:
AnnaBridge	189:f392fc9709a3	1051	usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	1052	break;
AnnaBridge	189:f392fc9709a3	1053
AnnaBridge	189:f392fc9709a3	1054	default:
AnnaBridge	189:f392fc9709a3	1055	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	1056	break;
AnnaBridge	189:f392fc9709a3	1057	}
AnnaBridge	189:f392fc9709a3	1058
AnnaBridge	189:f392fc9709a3	1059	return usb_frequency;
AnnaBridge	189:f392fc9709a3	1060	}
AnnaBridge	189:f392fc9709a3	1061
AnnaBridge	189:f392fc9709a3	1062	/**
AnnaBridge	189:f392fc9709a3	1063	* @brief Return DFSDM clock frequency
AnnaBridge	189:f392fc9709a3	1064	* @param DFSDMxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1065	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1066	* @retval DFSDM clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1067	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	1068	*/
AnnaBridge	189:f392fc9709a3	1069	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
AnnaBridge	189:f392fc9709a3	1070	{
AnnaBridge	189:f392fc9709a3	1071	uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	1072
AnnaBridge	189:f392fc9709a3	1073	switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
AnnaBridge	189:f392fc9709a3	1074	{
AnnaBridge	189:f392fc9709a3	1075	case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:
AnnaBridge	189:f392fc9709a3	1076	dfsdm_frequency = RCC_GetSystemClockFreq();
AnnaBridge	189:f392fc9709a3	1077	break;
AnnaBridge	189:f392fc9709a3	1078
AnnaBridge	189:f392fc9709a3	1079	case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:
AnnaBridge	189:f392fc9709a3	1080	dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	1081	break;
AnnaBridge	189:f392fc9709a3	1082
AnnaBridge	189:f392fc9709a3	1083	default:
AnnaBridge	189:f392fc9709a3	1084	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	1085	break;
AnnaBridge	189:f392fc9709a3	1086	}
AnnaBridge	189:f392fc9709a3	1087
AnnaBridge	189:f392fc9709a3	1088	return dfsdm_frequency;
AnnaBridge	189:f392fc9709a3	1089	}
AnnaBridge	189:f392fc9709a3	1090
AnnaBridge	189:f392fc9709a3	1091	/**
AnnaBridge	189:f392fc9709a3	1092	* @brief Return SPDIF clock frequency
AnnaBridge	189:f392fc9709a3	1093	* @param SPDIFxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1094	* @arg @ref LL_RCC_SPDIF_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1095	* @retval SPDIF clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1096	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	1097	*/
AnnaBridge	189:f392fc9709a3	1098	uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)
AnnaBridge	189:f392fc9709a3	1099	{
AnnaBridge	189:f392fc9709a3	1100	uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	1101	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	1102
AnnaBridge	189:f392fc9709a3	1103	switch (LL_RCC_GetSPDIFClockSource(SPDIFxSource))
AnnaBridge	189:f392fc9709a3	1104	{
AnnaBridge	189:f392fc9709a3	1105	case LL_RCC_SPDIF_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	1106	if (LL_RCC_PLL1_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1107	{
AnnaBridge	189:f392fc9709a3	1108	LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1109	spdif_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	1110	}
AnnaBridge	189:f392fc9709a3	1111	break;
AnnaBridge	189:f392fc9709a3	1112
AnnaBridge	189:f392fc9709a3	1113	case LL_RCC_SPDIF_CLKSOURCE_PLL2R:
AnnaBridge	189:f392fc9709a3	1114	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1115	{
AnnaBridge	189:f392fc9709a3	1116	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1117	spdif_frequency = PLL_Clocks.PLL_R_Frequency;
AnnaBridge	189:f392fc9709a3	1118	}
AnnaBridge	189:f392fc9709a3	1119	break;
AnnaBridge	189:f392fc9709a3	1120
AnnaBridge	189:f392fc9709a3	1121	case LL_RCC_SPDIF_CLKSOURCE_PLL3R:
AnnaBridge	189:f392fc9709a3	1122	if (LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1123	{
AnnaBridge	189:f392fc9709a3	1124	LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1125	spdif_frequency = PLL_Clocks.PLL_R_Frequency;
AnnaBridge	189:f392fc9709a3	1126	}
AnnaBridge	189:f392fc9709a3	1127	break;
AnnaBridge	189:f392fc9709a3	1128
AnnaBridge	189:f392fc9709a3	1129	case LL_RCC_SPDIF_CLKSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	1130	if (LL_RCC_HSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1131	{
AnnaBridge	189:f392fc9709a3	1132	spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	1133	}
AnnaBridge	189:f392fc9709a3	1134	break;
AnnaBridge	189:f392fc9709a3	1135
AnnaBridge	189:f392fc9709a3	1136	default:
AnnaBridge	189:f392fc9709a3	1137	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	1138	break;
AnnaBridge	189:f392fc9709a3	1139	}
AnnaBridge	189:f392fc9709a3	1140
AnnaBridge	189:f392fc9709a3	1141	return spdif_frequency;
AnnaBridge	189:f392fc9709a3	1142	}
AnnaBridge	189:f392fc9709a3	1143
AnnaBridge	189:f392fc9709a3	1144	/**
AnnaBridge	189:f392fc9709a3	1145	* @brief Return SPIx clock frequency
AnnaBridge	189:f392fc9709a3	1146	* @param SPIxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1147	* @arg @ref LL_RCC_SPI123_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1148	* @arg @ref LL_RCC_SPI45_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1149	* @arg @ref LL_RCC_SPI6_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1150	* @retval SPI clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1151	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	1152	*/
AnnaBridge	189:f392fc9709a3	1153	uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
AnnaBridge	189:f392fc9709a3	1154	{
AnnaBridge	189:f392fc9709a3	1155	uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	1156	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	1157
AnnaBridge	189:f392fc9709a3	1158	/* Check parameter */
AnnaBridge	189:f392fc9709a3	1159	assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
AnnaBridge	189:f392fc9709a3	1160
AnnaBridge	189:f392fc9709a3	1161	switch (LL_RCC_GetSPIClockSource(SPIxSource))
AnnaBridge	189:f392fc9709a3	1162	{
AnnaBridge	189:f392fc9709a3	1163	case LL_RCC_SPI123_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	1164	if (LL_RCC_PLL1_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1165	{
AnnaBridge	189:f392fc9709a3	1166	LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1167	spi_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	1168	}
AnnaBridge	189:f392fc9709a3	1169	break;
AnnaBridge	189:f392fc9709a3	1170
AnnaBridge	189:f392fc9709a3	1171	case LL_RCC_SPI123_CLKSOURCE_PLL2P:
AnnaBridge	189:f392fc9709a3	1172	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1173	{
AnnaBridge	189:f392fc9709a3	1174	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1175	spi_frequency = PLL_Clocks.PLL_P_Frequency;
AnnaBridge	189:f392fc9709a3	1176	}
AnnaBridge	189:f392fc9709a3	1177	break;
AnnaBridge	189:f392fc9709a3	1178
AnnaBridge	189:f392fc9709a3	1179	case LL_RCC_SPI123_CLKSOURCE_PLL3P:
AnnaBridge	189:f392fc9709a3	1180	if (LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1181	{
AnnaBridge	189:f392fc9709a3	1182	LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1183	spi_frequency = PLL_Clocks.PLL_P_Frequency;
AnnaBridge	189:f392fc9709a3	1184	}
AnnaBridge	189:f392fc9709a3	1185	break;
AnnaBridge	189:f392fc9709a3	1186
AnnaBridge	189:f392fc9709a3	1187	case LL_RCC_SPI123_CLKSOURCE_I2S_CKIN:
AnnaBridge	189:f392fc9709a3	1188	spi_frequency = EXTERNAL_CLOCK_VALUE;
AnnaBridge	189:f392fc9709a3	1189	break;
AnnaBridge	189:f392fc9709a3	1190
AnnaBridge	189:f392fc9709a3	1191	case LL_RCC_SPI123_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	1192	spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
AnnaBridge	189:f392fc9709a3	1193	break;
AnnaBridge	189:f392fc9709a3	1194
AnnaBridge	189:f392fc9709a3	1195	case LL_RCC_SPI45_CLKSOURCE_PCLK2:
AnnaBridge	189:f392fc9709a3	1196	spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	1197	break;
AnnaBridge	189:f392fc9709a3	1198
AnnaBridge	189:f392fc9709a3	1199	case LL_RCC_SPI6_CLKSOURCE_PCLK4:
AnnaBridge	189:f392fc9709a3	1200	spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	1201	break;
AnnaBridge	189:f392fc9709a3	1202
AnnaBridge	189:f392fc9709a3	1203	case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
AnnaBridge	189:f392fc9709a3	1204	case LL_RCC_SPI6_CLKSOURCE_PLL2Q:
AnnaBridge	189:f392fc9709a3	1205	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1206	{
AnnaBridge	189:f392fc9709a3	1207	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1208	spi_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	1209	}
AnnaBridge	189:f392fc9709a3	1210	break;
AnnaBridge	189:f392fc9709a3	1211
AnnaBridge	189:f392fc9709a3	1212	case LL_RCC_SPI45_CLKSOURCE_PLL3Q:
AnnaBridge	189:f392fc9709a3	1213	case LL_RCC_SPI6_CLKSOURCE_PLL3Q:
AnnaBridge	189:f392fc9709a3	1214	if (LL_RCC_PLL3_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1215	{
AnnaBridge	189:f392fc9709a3	1216	LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1217	spi_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	1218	}
AnnaBridge	189:f392fc9709a3	1219	break;
AnnaBridge	189:f392fc9709a3	1220
AnnaBridge	189:f392fc9709a3	1221	case LL_RCC_SPI45_CLKSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	1222	case LL_RCC_SPI6_CLKSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	1223	if (LL_RCC_HSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1224	{
AnnaBridge	189:f392fc9709a3	1225	spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	1226	}
AnnaBridge	189:f392fc9709a3	1227	break;
AnnaBridge	189:f392fc9709a3	1228
AnnaBridge	189:f392fc9709a3	1229	case LL_RCC_SPI45_CLKSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	1230	case LL_RCC_SPI6_CLKSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	1231	if (LL_RCC_CSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1232	{
AnnaBridge	189:f392fc9709a3	1233	spi_frequency = CSI_VALUE;
AnnaBridge	189:f392fc9709a3	1234	}
AnnaBridge	189:f392fc9709a3	1235	break;
AnnaBridge	189:f392fc9709a3	1236
AnnaBridge	189:f392fc9709a3	1237	case LL_RCC_SPI45_CLKSOURCE_HSE:
AnnaBridge	189:f392fc9709a3	1238	case LL_RCC_SPI6_CLKSOURCE_HSE:
AnnaBridge	189:f392fc9709a3	1239	if (LL_RCC_HSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1240	{
AnnaBridge	189:f392fc9709a3	1241	spi_frequency = HSE_VALUE;
AnnaBridge	189:f392fc9709a3	1242	}
AnnaBridge	189:f392fc9709a3	1243	break;
AnnaBridge	189:f392fc9709a3	1244
AnnaBridge	189:f392fc9709a3	1245	default:
AnnaBridge	189:f392fc9709a3	1246	/* Kernel clock disabled */
AnnaBridge	189:f392fc9709a3	1247	break;
AnnaBridge	189:f392fc9709a3	1248	}
AnnaBridge	189:f392fc9709a3	1249
AnnaBridge	189:f392fc9709a3	1250	return spi_frequency;
AnnaBridge	189:f392fc9709a3	1251	}
AnnaBridge	189:f392fc9709a3	1252
AnnaBridge	189:f392fc9709a3	1253	/**
AnnaBridge	189:f392fc9709a3	1254	* @brief Return SWP clock frequency
AnnaBridge	189:f392fc9709a3	1255	* @param SWPxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1256	* @arg @ref LL_RCC_SWP_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1257	* @retval SWP clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1258	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	1259	*/
AnnaBridge	189:f392fc9709a3	1260	uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)
AnnaBridge	189:f392fc9709a3	1261	{
AnnaBridge	189:f392fc9709a3	1262	uint32_t swp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	1263
AnnaBridge	189:f392fc9709a3	1264	switch (LL_RCC_GetSWPClockSource(SWPxSource))
AnnaBridge	189:f392fc9709a3	1265	{
AnnaBridge	189:f392fc9709a3	1266	case LL_RCC_SWP_CLKSOURCE_PCLK1:
AnnaBridge	189:f392fc9709a3	1267	swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
AnnaBridge	189:f392fc9709a3	1268	break;
AnnaBridge	189:f392fc9709a3	1269
AnnaBridge	189:f392fc9709a3	1270	case LL_RCC_SWP_CLKSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	1271	if (LL_RCC_HSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1272	{
AnnaBridge	189:f392fc9709a3	1273	swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	1274	}
AnnaBridge	189:f392fc9709a3	1275	break;
AnnaBridge	189:f392fc9709a3	1276
AnnaBridge	189:f392fc9709a3	1277	default:
AnnaBridge	189:f392fc9709a3	1278	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	1279	break;
AnnaBridge	189:f392fc9709a3	1280	}
AnnaBridge	189:f392fc9709a3	1281
AnnaBridge	189:f392fc9709a3	1282	return swp_frequency;
AnnaBridge	189:f392fc9709a3	1283	}
AnnaBridge	189:f392fc9709a3	1284
AnnaBridge	189:f392fc9709a3	1285	/**
AnnaBridge	189:f392fc9709a3	1286	* @brief Return FDCAN clock frequency
AnnaBridge	189:f392fc9709a3	1287	* @param FDCANxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1288	* @arg @ref LL_RCC_FDCAN_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1289	* @retval FDCAN clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1290	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	1291	*/
AnnaBridge	189:f392fc9709a3	1292	uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
AnnaBridge	189:f392fc9709a3	1293	{
AnnaBridge	189:f392fc9709a3	1294	uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	1295	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	1296
AnnaBridge	189:f392fc9709a3	1297	switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
AnnaBridge	189:f392fc9709a3	1298	{
AnnaBridge	189:f392fc9709a3	1299	case LL_RCC_FDCAN_CLKSOURCE_HSE:
AnnaBridge	189:f392fc9709a3	1300	if (LL_RCC_HSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1301	{
AnnaBridge	189:f392fc9709a3	1302	fdcan_frequency = HSE_VALUE;
AnnaBridge	189:f392fc9709a3	1303	}
AnnaBridge	189:f392fc9709a3	1304	break;
AnnaBridge	189:f392fc9709a3	1305
AnnaBridge	189:f392fc9709a3	1306	case LL_RCC_FDCAN_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	1307	if (LL_RCC_PLL1_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1308	{
AnnaBridge	189:f392fc9709a3	1309	LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1310	fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	1311	}
AnnaBridge	189:f392fc9709a3	1312	break;
AnnaBridge	189:f392fc9709a3	1313
AnnaBridge	189:f392fc9709a3	1314	case LL_RCC_FDCAN_CLKSOURCE_PLL2Q:
AnnaBridge	189:f392fc9709a3	1315	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1316	{
AnnaBridge	189:f392fc9709a3	1317	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1318	fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	1319	}
AnnaBridge	189:f392fc9709a3	1320	break;
AnnaBridge	189:f392fc9709a3	1321
AnnaBridge	189:f392fc9709a3	1322	default:
AnnaBridge	189:f392fc9709a3	1323	/* Kernel clock disabled */
AnnaBridge	189:f392fc9709a3	1324	break;
AnnaBridge	189:f392fc9709a3	1325	}
AnnaBridge	189:f392fc9709a3	1326
AnnaBridge	189:f392fc9709a3	1327	return fdcan_frequency;
AnnaBridge	189:f392fc9709a3	1328	}
AnnaBridge	189:f392fc9709a3	1329
AnnaBridge	189:f392fc9709a3	1330	/**
AnnaBridge	189:f392fc9709a3	1331	* @brief Return FMC clock frequency
AnnaBridge	189:f392fc9709a3	1332	* @param FMCxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1333	* @arg @ref LL_RCC_FMC_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1334	* @retval FMC clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1335	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	1336	*/
AnnaBridge	189:f392fc9709a3	1337	uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
AnnaBridge	189:f392fc9709a3	1338	{
AnnaBridge	189:f392fc9709a3	1339	uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	1340	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	1341
AnnaBridge	189:f392fc9709a3	1342	switch (LL_RCC_GetFMCClockSource(FMCxSource))
AnnaBridge	189:f392fc9709a3	1343	{
AnnaBridge	189:f392fc9709a3	1344	case LL_RCC_FMC_CLKSOURCE_HCLK:
AnnaBridge	189:f392fc9709a3	1345	fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
AnnaBridge	189:f392fc9709a3	1346	break;
AnnaBridge	189:f392fc9709a3	1347
AnnaBridge	189:f392fc9709a3	1348	case LL_RCC_FMC_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	1349	if (LL_RCC_PLL1_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1350	{
AnnaBridge	189:f392fc9709a3	1351	LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1352	fmc_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	1353	}
AnnaBridge	189:f392fc9709a3	1354	break;
AnnaBridge	189:f392fc9709a3	1355
AnnaBridge	189:f392fc9709a3	1356	case LL_RCC_FMC_CLKSOURCE_PLL2R:
AnnaBridge	189:f392fc9709a3	1357	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1358	{
AnnaBridge	189:f392fc9709a3	1359	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1360	fmc_frequency = PLL_Clocks.PLL_R_Frequency;
AnnaBridge	189:f392fc9709a3	1361	}
AnnaBridge	189:f392fc9709a3	1362	break;
AnnaBridge	189:f392fc9709a3	1363
AnnaBridge	189:f392fc9709a3	1364	case LL_RCC_FMC_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	1365	fmc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
AnnaBridge	189:f392fc9709a3	1366	break;
AnnaBridge	189:f392fc9709a3	1367
AnnaBridge	189:f392fc9709a3	1368	default:
AnnaBridge	189:f392fc9709a3	1369	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	1370	break;
AnnaBridge	189:f392fc9709a3	1371	}
AnnaBridge	189:f392fc9709a3	1372
AnnaBridge	189:f392fc9709a3	1373	return fmc_frequency;
AnnaBridge	189:f392fc9709a3	1374	}
AnnaBridge	189:f392fc9709a3	1375
AnnaBridge	189:f392fc9709a3	1376	/**
AnnaBridge	189:f392fc9709a3	1377	* @brief Return QSPI clock frequency
AnnaBridge	189:f392fc9709a3	1378	* @param QSPIxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1379	* @arg @ref LL_RCC_QSPI_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1380	* @retval QSPI clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1381	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	1382	*/
AnnaBridge	189:f392fc9709a3	1383	uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
AnnaBridge	189:f392fc9709a3	1384	{
AnnaBridge	189:f392fc9709a3	1385	uint32_t qspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	1386	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	1387
AnnaBridge	189:f392fc9709a3	1388	switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
AnnaBridge	189:f392fc9709a3	1389	{
AnnaBridge	189:f392fc9709a3	1390	case LL_RCC_QSPI_CLKSOURCE_HCLK:
AnnaBridge	189:f392fc9709a3	1391	qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
AnnaBridge	189:f392fc9709a3	1392	break;
AnnaBridge	189:f392fc9709a3	1393
AnnaBridge	189:f392fc9709a3	1394	case LL_RCC_QSPI_CLKSOURCE_PLL1Q:
AnnaBridge	189:f392fc9709a3	1395	if (LL_RCC_PLL1_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1396	{
AnnaBridge	189:f392fc9709a3	1397	LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1398	qspi_frequency = PLL_Clocks.PLL_Q_Frequency;
AnnaBridge	189:f392fc9709a3	1399	}
AnnaBridge	189:f392fc9709a3	1400	break;
AnnaBridge	189:f392fc9709a3	1401
AnnaBridge	189:f392fc9709a3	1402	case LL_RCC_QSPI_CLKSOURCE_PLL2R:
AnnaBridge	189:f392fc9709a3	1403	if (LL_RCC_PLL2_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1404	{
AnnaBridge	189:f392fc9709a3	1405	LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1406	qspi_frequency = PLL_Clocks.PLL_R_Frequency;
AnnaBridge	189:f392fc9709a3	1407	}
AnnaBridge	189:f392fc9709a3	1408	break;
AnnaBridge	189:f392fc9709a3	1409
AnnaBridge	189:f392fc9709a3	1410	case LL_RCC_QSPI_CLKSOURCE_CLKP:
AnnaBridge	189:f392fc9709a3	1411	qspi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
AnnaBridge	189:f392fc9709a3	1412	break;
AnnaBridge	189:f392fc9709a3	1413
AnnaBridge	189:f392fc9709a3	1414	default:
AnnaBridge	189:f392fc9709a3	1415	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	1416	break;
AnnaBridge	189:f392fc9709a3	1417	}
AnnaBridge	189:f392fc9709a3	1418
AnnaBridge	189:f392fc9709a3	1419	return qspi_frequency;
AnnaBridge	189:f392fc9709a3	1420	}
AnnaBridge	189:f392fc9709a3	1421
AnnaBridge	189:f392fc9709a3	1422	/**
AnnaBridge	189:f392fc9709a3	1423	* @brief Return CLKP clock frequency
AnnaBridge	189:f392fc9709a3	1424	* @param CLKPxSource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1425	* @arg @ref LL_RCC_CLKP_CLKSOURCE
AnnaBridge	189:f392fc9709a3	1426	* @retval CLKP clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1427	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
AnnaBridge	189:f392fc9709a3	1428	*/
AnnaBridge	189:f392fc9709a3	1429	uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
AnnaBridge	189:f392fc9709a3	1430	{
AnnaBridge	189:f392fc9709a3	1431	uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
AnnaBridge	189:f392fc9709a3	1432
AnnaBridge	189:f392fc9709a3	1433	switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
AnnaBridge	189:f392fc9709a3	1434	{
AnnaBridge	189:f392fc9709a3	1435	case LL_RCC_CLKP_CLKSOURCE_HSI:
AnnaBridge	189:f392fc9709a3	1436	if (LL_RCC_HSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1437	{
AnnaBridge	189:f392fc9709a3	1438	clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	1439	}
AnnaBridge	189:f392fc9709a3	1440	break;
AnnaBridge	189:f392fc9709a3	1441
AnnaBridge	189:f392fc9709a3	1442	case LL_RCC_CLKP_CLKSOURCE_CSI:
AnnaBridge	189:f392fc9709a3	1443	if (LL_RCC_CSI_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1444	{
AnnaBridge	189:f392fc9709a3	1445	clkp_frequency = CSI_VALUE;
AnnaBridge	189:f392fc9709a3	1446	}
AnnaBridge	189:f392fc9709a3	1447	break;
AnnaBridge	189:f392fc9709a3	1448
AnnaBridge	189:f392fc9709a3	1449	case LL_RCC_CLKP_CLKSOURCE_HSE:
AnnaBridge	189:f392fc9709a3	1450	if (LL_RCC_HSE_IsReady() != 0U)
AnnaBridge	189:f392fc9709a3	1451	{
AnnaBridge	189:f392fc9709a3	1452	clkp_frequency = HSE_VALUE;
AnnaBridge	189:f392fc9709a3	1453	}
AnnaBridge	189:f392fc9709a3	1454	break;
AnnaBridge	189:f392fc9709a3	1455
AnnaBridge	189:f392fc9709a3	1456	default:
AnnaBridge	189:f392fc9709a3	1457	/* CLKP clock disabled */
AnnaBridge	189:f392fc9709a3	1458	break;
AnnaBridge	189:f392fc9709a3	1459	}
AnnaBridge	189:f392fc9709a3	1460
AnnaBridge	189:f392fc9709a3	1461	return clkp_frequency;
AnnaBridge	189:f392fc9709a3	1462	}
AnnaBridge	189:f392fc9709a3	1463
AnnaBridge	189:f392fc9709a3	1464	/**
AnnaBridge	189:f392fc9709a3	1465	* @}
AnnaBridge	189:f392fc9709a3	1466	*/
AnnaBridge	189:f392fc9709a3	1467
AnnaBridge	189:f392fc9709a3	1468	/**
AnnaBridge	189:f392fc9709a3	1469	* @}
AnnaBridge	189:f392fc9709a3	1470	*/
AnnaBridge	189:f392fc9709a3	1471
AnnaBridge	189:f392fc9709a3	1472	/** @addtogroup RCC_LL_Private_Functions
AnnaBridge	189:f392fc9709a3	1473	* @{
AnnaBridge	189:f392fc9709a3	1474	*/
AnnaBridge	189:f392fc9709a3	1475
AnnaBridge	189:f392fc9709a3	1476	/**
AnnaBridge	189:f392fc9709a3	1477	* @brief Return SYSTEM clock frequency
AnnaBridge	189:f392fc9709a3	1478	* @retval SYSTEM clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1479	*/
AnnaBridge	189:f392fc9709a3	1480	uint32_t RCC_GetSystemClockFreq(void)
AnnaBridge	189:f392fc9709a3	1481	{
AnnaBridge	189:f392fc9709a3	1482	uint32_t frequency = 0U;
AnnaBridge	189:f392fc9709a3	1483	LL_PLL_ClocksTypeDef PLL_Clocks;
AnnaBridge	189:f392fc9709a3	1484
AnnaBridge	189:f392fc9709a3	1485	/* Get SYSCLK source -------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1486	switch (LL_RCC_GetSysClkSource())
AnnaBridge	189:f392fc9709a3	1487	{
AnnaBridge	189:f392fc9709a3	1488	/* No check on Ready: Won't be selected by hardware if not */
AnnaBridge	189:f392fc9709a3	1489	case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
AnnaBridge	189:f392fc9709a3	1490	frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
AnnaBridge	189:f392fc9709a3	1491	break;
AnnaBridge	189:f392fc9709a3	1492
AnnaBridge	189:f392fc9709a3	1493	case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
AnnaBridge	189:f392fc9709a3	1494	frequency = CSI_VALUE;
AnnaBridge	189:f392fc9709a3	1495	break;
AnnaBridge	189:f392fc9709a3	1496
AnnaBridge	189:f392fc9709a3	1497	case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
AnnaBridge	189:f392fc9709a3	1498	frequency = HSE_VALUE;
AnnaBridge	189:f392fc9709a3	1499	break;
AnnaBridge	189:f392fc9709a3	1500
AnnaBridge	189:f392fc9709a3	1501	case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
AnnaBridge	189:f392fc9709a3	1502	LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
AnnaBridge	189:f392fc9709a3	1503	frequency = PLL_Clocks.PLL_P_Frequency;
AnnaBridge	189:f392fc9709a3	1504	break;
AnnaBridge	189:f392fc9709a3	1505
AnnaBridge	189:f392fc9709a3	1506	default:
AnnaBridge	189:f392fc9709a3	1507	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	1508	break;
AnnaBridge	189:f392fc9709a3	1509	}
AnnaBridge	189:f392fc9709a3	1510
AnnaBridge	189:f392fc9709a3	1511	return frequency;
AnnaBridge	189:f392fc9709a3	1512	}
AnnaBridge	189:f392fc9709a3	1513
AnnaBridge	189:f392fc9709a3	1514	/**
AnnaBridge	189:f392fc9709a3	1515	* @brief Return HCLK clock frequency
AnnaBridge	189:f392fc9709a3	1516	* @param SYSCLK_Frequency SYSCLK clock frequency
AnnaBridge	189:f392fc9709a3	1517	* @retval HCLK clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1518	*/
AnnaBridge	189:f392fc9709a3	1519	uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
AnnaBridge	189:f392fc9709a3	1520	{
AnnaBridge	189:f392fc9709a3	1521	/* HCLK clock frequency */
AnnaBridge	189:f392fc9709a3	1522	return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
AnnaBridge	189:f392fc9709a3	1523	}
AnnaBridge	189:f392fc9709a3	1524
AnnaBridge	189:f392fc9709a3	1525	/**
AnnaBridge	189:f392fc9709a3	1526	* @brief Return PCLK1 clock frequency
AnnaBridge	189:f392fc9709a3	1527	* @param HCLK_Frequency HCLK clock frequency
AnnaBridge	189:f392fc9709a3	1528	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1529	*/
AnnaBridge	189:f392fc9709a3	1530	uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
AnnaBridge	189:f392fc9709a3	1531	{
AnnaBridge	189:f392fc9709a3	1532	/* PCLK1 clock frequency */
AnnaBridge	189:f392fc9709a3	1533	return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
AnnaBridge	189:f392fc9709a3	1534	}
AnnaBridge	189:f392fc9709a3	1535
AnnaBridge	189:f392fc9709a3	1536	/**
AnnaBridge	189:f392fc9709a3	1537	* @brief Return PCLK2 clock frequency
AnnaBridge	189:f392fc9709a3	1538	* @param HCLK_Frequency HCLK clock frequency
AnnaBridge	189:f392fc9709a3	1539	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1540	*/
AnnaBridge	189:f392fc9709a3	1541	uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
AnnaBridge	189:f392fc9709a3	1542	{
AnnaBridge	189:f392fc9709a3	1543	/* PCLK2 clock frequency */
AnnaBridge	189:f392fc9709a3	1544	return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
AnnaBridge	189:f392fc9709a3	1545	}
AnnaBridge	189:f392fc9709a3	1546
AnnaBridge	189:f392fc9709a3	1547	/**
AnnaBridge	189:f392fc9709a3	1548	* @brief Return PCLK3 clock frequency
AnnaBridge	189:f392fc9709a3	1549	* @param HCLK_Frequency HCLK clock frequency
AnnaBridge	189:f392fc9709a3	1550	* @retval PCLK3 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1551	*/
AnnaBridge	189:f392fc9709a3	1552	uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
AnnaBridge	189:f392fc9709a3	1553	{
AnnaBridge	189:f392fc9709a3	1554	/* PCLK3 clock frequency */
AnnaBridge	189:f392fc9709a3	1555	return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
AnnaBridge	189:f392fc9709a3	1556	}
AnnaBridge	189:f392fc9709a3	1557
AnnaBridge	189:f392fc9709a3	1558	/**
AnnaBridge	189:f392fc9709a3	1559	* @brief Return PCLK4 clock frequency
AnnaBridge	189:f392fc9709a3	1560	* @param HCLK_Frequency HCLK clock frequency
AnnaBridge	189:f392fc9709a3	1561	* @retval PCLK4 clock frequency (in Hz)
AnnaBridge	189:f392fc9709a3	1562	*/
AnnaBridge	189:f392fc9709a3	1563	uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
AnnaBridge	189:f392fc9709a3	1564	{
AnnaBridge	189:f392fc9709a3	1565	/* PCLK4 clock frequency */
AnnaBridge	189:f392fc9709a3	1566	return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
AnnaBridge	189:f392fc9709a3	1567	}
AnnaBridge	189:f392fc9709a3	1568
AnnaBridge	189:f392fc9709a3	1569	/**
AnnaBridge	189:f392fc9709a3	1570	* @}
AnnaBridge	189:f392fc9709a3	1571	*/
AnnaBridge	189:f392fc9709a3	1572
AnnaBridge	189:f392fc9709a3	1573	/**
AnnaBridge	189:f392fc9709a3	1574	* @}
AnnaBridge	189:f392fc9709a3	1575	*/
AnnaBridge	189:f392fc9709a3	1576
AnnaBridge	189:f392fc9709a3	1577	#endif /* defined(RCC) */
AnnaBridge	189:f392fc9709a3	1578
AnnaBridge	189:f392fc9709a3	1579	/**
AnnaBridge	189:f392fc9709a3	1580	* @}
AnnaBridge	189:f392fc9709a3	1581	*/
AnnaBridge	189:f392fc9709a3	1582
AnnaBridge	189:f392fc9709a3	1583	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	1584
AnnaBridge	189:f392fc9709a3	1585	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/