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targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_pwr.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32h7xx_ll_pwr.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of PWR LL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge	189:f392fc9709a3	10	* All rights reserved.</center></h2>
AnnaBridge	189:f392fc9709a3	11	*
AnnaBridge	189:f392fc9709a3	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	189:f392fc9709a3	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	189:f392fc9709a3	14	* License. You may obtain a copy of the License at:
AnnaBridge	189:f392fc9709a3	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	189:f392fc9709a3	16	*
AnnaBridge	189:f392fc9709a3	17	******************************************************************************
AnnaBridge	189:f392fc9709a3	18	*/
AnnaBridge	189:f392fc9709a3	19
AnnaBridge	189:f392fc9709a3	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	21	#ifndef STM32H7xx_LL_PWR_H
AnnaBridge	189:f392fc9709a3	22	#define STM32H7xx_LL_PWR_H
AnnaBridge	189:f392fc9709a3	23
AnnaBridge	189:f392fc9709a3	24	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	25	extern "C" {
AnnaBridge	189:f392fc9709a3	26	#endif
AnnaBridge	189:f392fc9709a3	27
AnnaBridge	189:f392fc9709a3	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	29	#include "stm32h7xx.h"
AnnaBridge	189:f392fc9709a3	30
AnnaBridge	189:f392fc9709a3	31	/** @addtogroup STM32H7xx_LL_Driver
AnnaBridge	189:f392fc9709a3	32	* @{
AnnaBridge	189:f392fc9709a3	33	*/
AnnaBridge	189:f392fc9709a3	34
AnnaBridge	189:f392fc9709a3	35	#if defined(PWR)
AnnaBridge	189:f392fc9709a3	36
AnnaBridge	189:f392fc9709a3	37	/** @defgroup PWR_LL PWR
AnnaBridge	189:f392fc9709a3	38	* @{
AnnaBridge	189:f392fc9709a3	39	*/
AnnaBridge	189:f392fc9709a3	40
AnnaBridge	189:f392fc9709a3	41	/* Private types -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	42	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	43	/* Private constants ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	44	/** @defgroup PWR_LL_Private_Constants PWR Private Constants
AnnaBridge	189:f392fc9709a3	45	* @{
AnnaBridge	189:f392fc9709a3	46	*/
AnnaBridge	189:f392fc9709a3	47
AnnaBridge	189:f392fc9709a3	48	/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
AnnaBridge	189:f392fc9709a3	49	* @brief Flags defines which can be used with LL_PWR_WriteReg function
AnnaBridge	189:f392fc9709a3	50	* @{
AnnaBridge	189:f392fc9709a3	51	*/
AnnaBridge	189:f392fc9709a3	52	/* Wake-Up Pins PWR register offsets */
AnnaBridge	189:f392fc9709a3	53	#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL
AnnaBridge	189:f392fc9709a3	54	#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU
AnnaBridge	189:f392fc9709a3	55	/**
AnnaBridge	189:f392fc9709a3	56	* @}
AnnaBridge	189:f392fc9709a3	57	*/
AnnaBridge	189:f392fc9709a3	58	/**
AnnaBridge	189:f392fc9709a3	59	* @}
AnnaBridge	189:f392fc9709a3	60	*/
AnnaBridge	189:f392fc9709a3	61	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	62	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	63	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	64	/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
AnnaBridge	189:f392fc9709a3	65	* @{
AnnaBridge	189:f392fc9709a3	66	*/
AnnaBridge	189:f392fc9709a3	67
AnnaBridge	189:f392fc9709a3	68	/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	189:f392fc9709a3	69	* @brief Flags defines which can be used with LL_PWR_WriteReg function
AnnaBridge	189:f392fc9709a3	70	* @{
AnnaBridge	189:f392fc9709a3	71	*/
AnnaBridge	189:f392fc9709a3	72	#define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /!< Clear CPU STANDBY, STOP and HOLD flags /
AnnaBridge	189:f392fc9709a3	73	#define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /!< Clear WKUP pin 6 /
AnnaBridge	189:f392fc9709a3	74	#define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /!< Clear WKUP pin 5 /
AnnaBridge	189:f392fc9709a3	75	#define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /!< Clear WKUP pin 4 /
AnnaBridge	189:f392fc9709a3	76	#define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /!< Clear WKUP pin 3 /
AnnaBridge	189:f392fc9709a3	77	#define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /!< Clear WKUP pin 2 /
AnnaBridge	189:f392fc9709a3	78	#define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /!< Clear WKUP pin 1 /
AnnaBridge	189:f392fc9709a3	79	/**
AnnaBridge	189:f392fc9709a3	80	* @}
AnnaBridge	189:f392fc9709a3	81	*/
AnnaBridge	189:f392fc9709a3	82
AnnaBridge	189:f392fc9709a3	83	/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	189:f392fc9709a3	84	* @brief Flags defines which can be used with LL_PWR_ReadReg function
AnnaBridge	189:f392fc9709a3	85	* @{
AnnaBridge	189:f392fc9709a3	86	*/
AnnaBridge	189:f392fc9709a3	87	#define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /!< Analog Voltage Detect Output /
AnnaBridge	189:f392fc9709a3	88	#define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /!< Power voltage detector output flag /
AnnaBridge	189:f392fc9709a3	89	#define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS /!< Current actual used VOS for VDD11 Voltage Scaling /
AnnaBridge	189:f392fc9709a3	90	#define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY /!< Ready bit for current actual used VOS for VDD11 Voltage Scaling /
AnnaBridge	189:f392fc9709a3	91
AnnaBridge	189:f392fc9709a3	92	#define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /!< Temperature high threshold flag /
AnnaBridge	189:f392fc9709a3	93	#define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /!< Temperature low threshold flag /
AnnaBridge	189:f392fc9709a3	94	#define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /!< VBAT high threshold flag /
AnnaBridge	189:f392fc9709a3	95	#define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /!< VBAT low threshold flag /
AnnaBridge	189:f392fc9709a3	96	#define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /!< Backup Regulator ready flag /
AnnaBridge	189:f392fc9709a3	97
AnnaBridge	189:f392fc9709a3	98	#define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /!< USB supply ready flag /
AnnaBridge	189:f392fc9709a3	99
AnnaBridge	189:f392fc9709a3	100	#define LL_PWR_FLAG_CPU_SBF_D2 PWR_CPUCR_SBF_D2 /!< D2 domain DSTANDBY Flag /
AnnaBridge	189:f392fc9709a3	101	#define LL_PWR_FLAG_CPU_SBF_D1 PWR_CPUCR_SBF_D1 /!< D1 domain DSTANDBY Flag /
AnnaBridge	189:f392fc9709a3	102	#define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF /!< System STANDBY Flag /
AnnaBridge	189:f392fc9709a3	103	#define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF /!< STOP Flag /
AnnaBridge	189:f392fc9709a3	104
AnnaBridge	189:f392fc9709a3	105	#define LL_PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY /!< Voltage scaling ready flag /
AnnaBridge	189:f392fc9709a3	106
AnnaBridge	189:f392fc9709a3	107	#define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /!< Wakeup Pin Flag 6 /
AnnaBridge	189:f392fc9709a3	108	#define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /!< Wakeup Pin Flag 5 /
AnnaBridge	189:f392fc9709a3	109	#define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /!< Wakeup Pin Flag 4 /
AnnaBridge	189:f392fc9709a3	110	#define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /!< Wakeup Pin Flag 3 /
AnnaBridge	189:f392fc9709a3	111	#define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /!< Wakeup Pin Flag 2 /
AnnaBridge	189:f392fc9709a3	112	#define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /!< Wakeup Pin Flag 1 /
AnnaBridge	189:f392fc9709a3	113	/**
AnnaBridge	189:f392fc9709a3	114	* @}
AnnaBridge	189:f392fc9709a3	115	*/
AnnaBridge	189:f392fc9709a3	116
AnnaBridge	189:f392fc9709a3	117	/** @defgroup PWR_LL_EC_MODE_PWR Power mode
AnnaBridge	189:f392fc9709a3	118	* @{
AnnaBridge	189:f392fc9709a3	119	*/
AnnaBridge	189:f392fc9709a3	120	#define LL_PWR_CPU_MODE_D1STOP 0x00000000U /!< Enter D1 domain to Stop mode when the CPU enters deepsleep /
AnnaBridge	189:f392fc9709a3	121	#define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /!< Enter D1 domain to Standby mode when the CPU enters deepsleep /
AnnaBridge	189:f392fc9709a3	122	#define LL_PWR_CPU_MODE_D2STOP 0x00000000U /!< Enter Stop mode when the CPU enters deepsleep /
AnnaBridge	189:f392fc9709a3	123	#define LL_PWR_CPU_MODE_D2STANDBY PWR_CPUCR_PDDS_D2 /!< Enter D3 domain to Standby mode when the CPU enters deepsleep /
AnnaBridge	189:f392fc9709a3	124	#define LL_PWR_CPU_MODE_D3STOP 0x00000000U /!< Enter Stop mode when the CPU enters deepsleep /
AnnaBridge	189:f392fc9709a3	125	#define LL_PWR_CPU_MODE_D3STANDBY PWR_CPUCR_PDDS_D3 /!< Enter D3 domain to Standby mode when the CPU enter deepsleep /
AnnaBridge	189:f392fc9709a3	126	#define LL_PWR_CPU_MODE_D3RUN PWR_CPUCR_RUN_D3 /!< Keep system D3 domain in RUN mode when the CPU enter deepsleep /
AnnaBridge	189:f392fc9709a3	127	/**
AnnaBridge	189:f392fc9709a3	128	* @}
AnnaBridge	189:f392fc9709a3	129	*/
AnnaBridge	189:f392fc9709a3	130
AnnaBridge	189:f392fc9709a3	131	/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
AnnaBridge	189:f392fc9709a3	132	* @{
AnnaBridge	189:f392fc9709a3	133	*/
AnnaBridge	189:f392fc9709a3	134	#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /* Select voltage scale 3 */
AnnaBridge	189:f392fc9709a3	135	#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /* Select voltage scale 2 */
AnnaBridge	189:f392fc9709a3	136	#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 \| PWR_D3CR_VOS_1) /* Select voltage scale 1 */
AnnaBridge	189:f392fc9709a3	137	/**
AnnaBridge	189:f392fc9709a3	138	* @}
AnnaBridge	189:f392fc9709a3	139	*/
AnnaBridge	189:f392fc9709a3	140
AnnaBridge	189:f392fc9709a3	141	/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
AnnaBridge	189:f392fc9709a3	142	* @{
AnnaBridge	189:f392fc9709a3	143	*/
AnnaBridge	189:f392fc9709a3	144	#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0 /* Select voltage scale 5 when system enters STOP mode */
AnnaBridge	189:f392fc9709a3	145	#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1 /* Select voltage scale 4 when system enters STOP mode */
AnnaBridge	189:f392fc9709a3	146	#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 \| PWR_CR1_SVOS_1) /* Select voltage scale 3 when system enters STOP mode */
AnnaBridge	189:f392fc9709a3	147	/**
AnnaBridge	189:f392fc9709a3	148	* @}
AnnaBridge	189:f392fc9709a3	149	*/
AnnaBridge	189:f392fc9709a3	150
AnnaBridge	189:f392fc9709a3	151	/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
AnnaBridge	189:f392fc9709a3	152	* @{
AnnaBridge	189:f392fc9709a3	153	*/
AnnaBridge	189:f392fc9709a3	154	#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /!< Voltage Regulator in main mode during deepsleep mode /
AnnaBridge	189:f392fc9709a3	155	#define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /!< Voltage Regulator in low-power mode during deepsleep mode /
AnnaBridge	189:f392fc9709a3	156	/**
AnnaBridge	189:f392fc9709a3	157	* @}
AnnaBridge	189:f392fc9709a3	158	*/
AnnaBridge	189:f392fc9709a3	159
AnnaBridge	189:f392fc9709a3	160	/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
AnnaBridge	189:f392fc9709a3	161	* @{
AnnaBridge	189:f392fc9709a3	162	*/
AnnaBridge	189:f392fc9709a3	163	#define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /!< Voltage threshold detected by PVD 1.95 V /
AnnaBridge	189:f392fc9709a3	164	#define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /!< Voltage threshold detected by PVD 2.1 V /
AnnaBridge	189:f392fc9709a3	165	#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /!< Voltage threshold detected by PVD 2.25 V /
AnnaBridge	189:f392fc9709a3	166	#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /!< Voltage threshold detected by PVD 2.4 V /
AnnaBridge	189:f392fc9709a3	167	#define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /!< Voltage threshold detected by PVD 2.55 V /
AnnaBridge	189:f392fc9709a3	168	#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /!< Voltage threshold detected by PVD 2.7 V /
AnnaBridge	189:f392fc9709a3	169	#define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /!< Voltage threshold detected by PVD 2.85 V /
AnnaBridge	189:f392fc9709a3	170	#define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /!< External voltage level on PVD_IN pin, compared to internal VREFINT level. /
AnnaBridge	189:f392fc9709a3	171	/**
AnnaBridge	189:f392fc9709a3	172	* @}
AnnaBridge	189:f392fc9709a3	173	*/
AnnaBridge	189:f392fc9709a3	174
AnnaBridge	189:f392fc9709a3	175	/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
AnnaBridge	189:f392fc9709a3	176	* @{
AnnaBridge	189:f392fc9709a3	177	*/
AnnaBridge	189:f392fc9709a3	178	#define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /!< Analog Voltage threshold detected by AVD 1.7 V /
AnnaBridge	189:f392fc9709a3	179	#define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /!< Analog Voltage threshold detected by AVD 2.1 V /
AnnaBridge	189:f392fc9709a3	180	#define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /!< Analog Voltage threshold detected by AVD 2.5 V /
AnnaBridge	189:f392fc9709a3	181	#define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /!< Analog Voltage threshold detected by AVD 2.8 V /
AnnaBridge	189:f392fc9709a3	182
AnnaBridge	189:f392fc9709a3	183	/**
AnnaBridge	189:f392fc9709a3	184	* @}
AnnaBridge	189:f392fc9709a3	185	*/
AnnaBridge	189:f392fc9709a3	186
AnnaBridge	189:f392fc9709a3	187	/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
AnnaBridge	189:f392fc9709a3	188	* @{
AnnaBridge	189:f392fc9709a3	189	*/
AnnaBridge	189:f392fc9709a3	190	#define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /!< Charge the Battery through a 5 kO resistor /
AnnaBridge	189:f392fc9709a3	191	#define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /!< Charge the Battery through a 1.5 kO resistor /
AnnaBridge	189:f392fc9709a3	192	/**
AnnaBridge	189:f392fc9709a3	193	* @}
AnnaBridge	189:f392fc9709a3	194	*/
AnnaBridge	189:f392fc9709a3	195
AnnaBridge	189:f392fc9709a3	196	/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
AnnaBridge	189:f392fc9709a3	197	* @{
AnnaBridge	189:f392fc9709a3	198	*/
AnnaBridge	189:f392fc9709a3	199	#define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /!< Wake-Up pin 1 : PA0 /
AnnaBridge	189:f392fc9709a3	200	#define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /!< Wake-Up pin 2 : PA2 /
AnnaBridge	189:f392fc9709a3	201	#define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /!< Wake-Up pin 3 : PC1 /
AnnaBridge	189:f392fc9709a3	202	#define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /!< Wake-Up pin 4 : PC13 /
AnnaBridge	189:f392fc9709a3	203	#define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /!< Wake-Up pin 5 : PI8 /
AnnaBridge	189:f392fc9709a3	204	#define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /!< Wake-Up pin 6 : PI11 /
AnnaBridge	189:f392fc9709a3	205	/**
AnnaBridge	189:f392fc9709a3	206	* @}
AnnaBridge	189:f392fc9709a3	207	*/
AnnaBridge	189:f392fc9709a3	208
AnnaBridge	189:f392fc9709a3	209	/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration
AnnaBridge	189:f392fc9709a3	210	* @{
AnnaBridge	189:f392fc9709a3	211	*/
AnnaBridge	189:f392fc9709a3	212	#define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /!< Configure Wake-Up pin in no pull /
AnnaBridge	189:f392fc9709a3	213	#define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /!< Configure Wake-Up pin in pull Up /
AnnaBridge	189:f392fc9709a3	214	#define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /!< Configure Wake-Up pin in pull Down /
AnnaBridge	189:f392fc9709a3	215	/**
AnnaBridge	189:f392fc9709a3	216	* @}
AnnaBridge	189:f392fc9709a3	217	*/
AnnaBridge	189:f392fc9709a3	218
AnnaBridge	189:f392fc9709a3	219	/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
AnnaBridge	189:f392fc9709a3	220	* @{
AnnaBridge	189:f392fc9709a3	221	*/
AnnaBridge	189:f392fc9709a3	222	#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /* Core domains are suppplied from the LDO */
AnnaBridge	189:f392fc9709a3	223	#define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /* LDO Bypassed. The Core domain is supplied from an external source */
AnnaBridge	189:f392fc9709a3	224	/**
AnnaBridge	189:f392fc9709a3	225	* @}
AnnaBridge	189:f392fc9709a3	226	*/
AnnaBridge	189:f392fc9709a3	227
AnnaBridge	189:f392fc9709a3	228	/**
AnnaBridge	189:f392fc9709a3	229	* @}
AnnaBridge	189:f392fc9709a3	230	*/
AnnaBridge	189:f392fc9709a3	231	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	232	/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
AnnaBridge	189:f392fc9709a3	233	* @{
AnnaBridge	189:f392fc9709a3	234	*/
AnnaBridge	189:f392fc9709a3	235
AnnaBridge	189:f392fc9709a3	236	/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
AnnaBridge	189:f392fc9709a3	237	* @{
AnnaBridge	189:f392fc9709a3	238	*/
AnnaBridge	189:f392fc9709a3	239
AnnaBridge	189:f392fc9709a3	240	/**
AnnaBridge	189:f392fc9709a3	241	* @brief Write a value in PWR register
AnnaBridge	189:f392fc9709a3	242	* @param __REG__ Register to be written
AnnaBridge	189:f392fc9709a3	243	* @param __VALUE__ Value to be written in the register
AnnaBridge	189:f392fc9709a3	244	* @retval None
AnnaBridge	189:f392fc9709a3	245	*/
AnnaBridge	189:f392fc9709a3	246	#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
AnnaBridge	189:f392fc9709a3	247
AnnaBridge	189:f392fc9709a3	248	/**
AnnaBridge	189:f392fc9709a3	249	* @brief Read a value in PWR register
AnnaBridge	189:f392fc9709a3	250	* @param __REG__ Register to be read
AnnaBridge	189:f392fc9709a3	251	* @retval Register value
AnnaBridge	189:f392fc9709a3	252	*/
AnnaBridge	189:f392fc9709a3	253	#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
AnnaBridge	189:f392fc9709a3	254	/**
AnnaBridge	189:f392fc9709a3	255	* @}
AnnaBridge	189:f392fc9709a3	256	*/
AnnaBridge	189:f392fc9709a3	257
AnnaBridge	189:f392fc9709a3	258	/**
AnnaBridge	189:f392fc9709a3	259	* @}
AnnaBridge	189:f392fc9709a3	260	*/
AnnaBridge	189:f392fc9709a3	261	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	262	/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
AnnaBridge	189:f392fc9709a3	263	* @{
AnnaBridge	189:f392fc9709a3	264	*/
AnnaBridge	189:f392fc9709a3	265
AnnaBridge	189:f392fc9709a3	266	/** @defgroup PWR_LL_EF_Configuration Configuration
AnnaBridge	189:f392fc9709a3	267	* @{
AnnaBridge	189:f392fc9709a3	268	*/
AnnaBridge	189:f392fc9709a3	269
AnnaBridge	189:f392fc9709a3	270	/**
AnnaBridge	189:f392fc9709a3	271	* @brief Set the voltage Regulator mode during deep sleep mode
AnnaBridge	189:f392fc9709a3	272	* @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS
AnnaBridge	189:f392fc9709a3	273	* @param RegulMode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	274	* @arg @ref LL_PWR_REGU_DSMODE_MAIN
AnnaBridge	189:f392fc9709a3	275	* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
AnnaBridge	189:f392fc9709a3	276	* @retval None
AnnaBridge	189:f392fc9709a3	277	*/
AnnaBridge	189:f392fc9709a3	278	__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
AnnaBridge	189:f392fc9709a3	279	{
AnnaBridge	189:f392fc9709a3	280	MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
AnnaBridge	189:f392fc9709a3	281	}
AnnaBridge	189:f392fc9709a3	282
AnnaBridge	189:f392fc9709a3	283	/**
AnnaBridge	189:f392fc9709a3	284	* @brief Get the voltage Regulator mode during deep sleep mode
AnnaBridge	189:f392fc9709a3	285	* @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS
AnnaBridge	189:f392fc9709a3	286	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	287	* @arg @ref LL_PWR_REGU_DSMODE_MAIN
AnnaBridge	189:f392fc9709a3	288	* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
AnnaBridge	189:f392fc9709a3	289	*/
AnnaBridge	189:f392fc9709a3	290	__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
AnnaBridge	189:f392fc9709a3	291	{
AnnaBridge	189:f392fc9709a3	292	return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
AnnaBridge	189:f392fc9709a3	293	}
AnnaBridge	189:f392fc9709a3	294
AnnaBridge	189:f392fc9709a3	295	/**
AnnaBridge	189:f392fc9709a3	296	* @brief Enable Power Voltage Detector
AnnaBridge	189:f392fc9709a3	297	* @rmtoll CR1 PVDEN LL_PWR_EnablePVD
AnnaBridge	189:f392fc9709a3	298	* @retval None
AnnaBridge	189:f392fc9709a3	299	*/
AnnaBridge	189:f392fc9709a3	300	__STATIC_INLINE void LL_PWR_EnablePVD(void)
AnnaBridge	189:f392fc9709a3	301	{
AnnaBridge	189:f392fc9709a3	302	SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
AnnaBridge	189:f392fc9709a3	303	}
AnnaBridge	189:f392fc9709a3	304
AnnaBridge	189:f392fc9709a3	305	/**
AnnaBridge	189:f392fc9709a3	306	* @brief Disable Power Voltage Detector
AnnaBridge	189:f392fc9709a3	307	* @rmtoll CR1 PVDEN LL_PWR_DisablePVD
AnnaBridge	189:f392fc9709a3	308	* @retval None
AnnaBridge	189:f392fc9709a3	309	*/
AnnaBridge	189:f392fc9709a3	310	__STATIC_INLINE void LL_PWR_DisablePVD(void)
AnnaBridge	189:f392fc9709a3	311	{
AnnaBridge	189:f392fc9709a3	312	CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
AnnaBridge	189:f392fc9709a3	313	}
AnnaBridge	189:f392fc9709a3	314
AnnaBridge	189:f392fc9709a3	315	/**
AnnaBridge	189:f392fc9709a3	316	* @brief Check if Power Voltage Detector is enabled
AnnaBridge	189:f392fc9709a3	317	* @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD
AnnaBridge	189:f392fc9709a3	318	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	319	*/
AnnaBridge	189:f392fc9709a3	320	__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
AnnaBridge	189:f392fc9709a3	321	{
AnnaBridge	189:f392fc9709a3	322	return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	323	}
AnnaBridge	189:f392fc9709a3	324
AnnaBridge	189:f392fc9709a3	325	/**
AnnaBridge	189:f392fc9709a3	326	* @brief Configure the voltage threshold detected by the Power Voltage Detector
AnnaBridge	189:f392fc9709a3	327	* @rmtoll CR1 PLS LL_PWR_SetPVDLevel
AnnaBridge	189:f392fc9709a3	328	* @param PVDLevel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	329	* @arg @ref LL_PWR_PVDLEVEL_0
AnnaBridge	189:f392fc9709a3	330	* @arg @ref LL_PWR_PVDLEVEL_1
AnnaBridge	189:f392fc9709a3	331	* @arg @ref LL_PWR_PVDLEVEL_2
AnnaBridge	189:f392fc9709a3	332	* @arg @ref LL_PWR_PVDLEVEL_3
AnnaBridge	189:f392fc9709a3	333	* @arg @ref LL_PWR_PVDLEVEL_4
AnnaBridge	189:f392fc9709a3	334	* @arg @ref LL_PWR_PVDLEVEL_5
AnnaBridge	189:f392fc9709a3	335	* @arg @ref LL_PWR_PVDLEVEL_6
AnnaBridge	189:f392fc9709a3	336	* @arg @ref LL_PWR_PVDLEVEL_7
AnnaBridge	189:f392fc9709a3	337	* @retval None
AnnaBridge	189:f392fc9709a3	338	*/
AnnaBridge	189:f392fc9709a3	339	__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
AnnaBridge	189:f392fc9709a3	340	{
AnnaBridge	189:f392fc9709a3	341	MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
AnnaBridge	189:f392fc9709a3	342	}
AnnaBridge	189:f392fc9709a3	343
AnnaBridge	189:f392fc9709a3	344	/**
AnnaBridge	189:f392fc9709a3	345	* @brief Get the voltage threshold detection
AnnaBridge	189:f392fc9709a3	346	* @rmtoll CR1 PLS LL_PWR_GetPVDLevel
AnnaBridge	189:f392fc9709a3	347	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	348	* @arg @ref LL_PWR_PVDLEVEL_0
AnnaBridge	189:f392fc9709a3	349	* @arg @ref LL_PWR_PVDLEVEL_1
AnnaBridge	189:f392fc9709a3	350	* @arg @ref LL_PWR_PVDLEVEL_2
AnnaBridge	189:f392fc9709a3	351	* @arg @ref LL_PWR_PVDLEVEL_3
AnnaBridge	189:f392fc9709a3	352	* @arg @ref LL_PWR_PVDLEVEL_4
AnnaBridge	189:f392fc9709a3	353	* @arg @ref LL_PWR_PVDLEVEL_5
AnnaBridge	189:f392fc9709a3	354	* @arg @ref LL_PWR_PVDLEVEL_6
AnnaBridge	189:f392fc9709a3	355	* @arg @ref LL_PWR_PVDLEVEL_7
AnnaBridge	189:f392fc9709a3	356	*/
AnnaBridge	189:f392fc9709a3	357	__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
AnnaBridge	189:f392fc9709a3	358	{
AnnaBridge	189:f392fc9709a3	359	return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
AnnaBridge	189:f392fc9709a3	360	}
AnnaBridge	189:f392fc9709a3	361
AnnaBridge	189:f392fc9709a3	362	/**
AnnaBridge	189:f392fc9709a3	363	* @brief Enable access to the backup domain
AnnaBridge	189:f392fc9709a3	364	* @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
AnnaBridge	189:f392fc9709a3	365	* @retval None
AnnaBridge	189:f392fc9709a3	366	*/
AnnaBridge	189:f392fc9709a3	367	__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
AnnaBridge	189:f392fc9709a3	368	{
AnnaBridge	189:f392fc9709a3	369	SET_BIT(PWR->CR1, PWR_CR1_DBP);
AnnaBridge	189:f392fc9709a3	370	}
AnnaBridge	189:f392fc9709a3	371
AnnaBridge	189:f392fc9709a3	372	/**
AnnaBridge	189:f392fc9709a3	373	* @brief Disable access to the backup domain
AnnaBridge	189:f392fc9709a3	374	* @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
AnnaBridge	189:f392fc9709a3	375	* @retval None
AnnaBridge	189:f392fc9709a3	376	*/
AnnaBridge	189:f392fc9709a3	377	__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
AnnaBridge	189:f392fc9709a3	378	{
AnnaBridge	189:f392fc9709a3	379	CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
AnnaBridge	189:f392fc9709a3	380	}
AnnaBridge	189:f392fc9709a3	381
AnnaBridge	189:f392fc9709a3	382	/**
AnnaBridge	189:f392fc9709a3	383	* @brief Check if the backup domain is enabled
AnnaBridge	189:f392fc9709a3	384	* @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
AnnaBridge	189:f392fc9709a3	385	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	386	*/
AnnaBridge	189:f392fc9709a3	387	__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
AnnaBridge	189:f392fc9709a3	388	{
AnnaBridge	189:f392fc9709a3	389	return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	390	}
AnnaBridge	189:f392fc9709a3	391
AnnaBridge	189:f392fc9709a3	392	/**
AnnaBridge	189:f392fc9709a3	393	* @brief Enable the Flash Power Down in Stop Mode
AnnaBridge	189:f392fc9709a3	394	* @rmtoll CR1 FLPS LL_PWR_EnableFlashPowerDown
AnnaBridge	189:f392fc9709a3	395	* @retval None
AnnaBridge	189:f392fc9709a3	396	*/
AnnaBridge	189:f392fc9709a3	397	__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
AnnaBridge	189:f392fc9709a3	398	{
AnnaBridge	189:f392fc9709a3	399	SET_BIT(PWR->CR1, PWR_CR1_FLPS);
AnnaBridge	189:f392fc9709a3	400	}
AnnaBridge	189:f392fc9709a3	401
AnnaBridge	189:f392fc9709a3	402	/**
AnnaBridge	189:f392fc9709a3	403	* @brief Disable the Flash Power Down in Stop Mode
AnnaBridge	189:f392fc9709a3	404	* @rmtoll CR1 FLPS LL_PWR_DisableFlashPowerDown
AnnaBridge	189:f392fc9709a3	405	* @retval None
AnnaBridge	189:f392fc9709a3	406	*/
AnnaBridge	189:f392fc9709a3	407	__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
AnnaBridge	189:f392fc9709a3	408	{
AnnaBridge	189:f392fc9709a3	409	CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
AnnaBridge	189:f392fc9709a3	410	}
AnnaBridge	189:f392fc9709a3	411
AnnaBridge	189:f392fc9709a3	412	/**
AnnaBridge	189:f392fc9709a3	413	* @brief Check if the Flash Power Down in Stop Mode is enabled
AnnaBridge	189:f392fc9709a3	414	* @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashPowerDown
AnnaBridge	189:f392fc9709a3	415	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	416	*/
AnnaBridge	189:f392fc9709a3	417	__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
AnnaBridge	189:f392fc9709a3	418	{
AnnaBridge	189:f392fc9709a3	419	return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	420	}
AnnaBridge	189:f392fc9709a3	421
AnnaBridge	189:f392fc9709a3	422	/**
AnnaBridge	189:f392fc9709a3	423	* @brief Set the internal Regulator output voltage in STOP mode
AnnaBridge	189:f392fc9709a3	424	* @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling
AnnaBridge	189:f392fc9709a3	425	* @param VoltageScaling This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	426	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
AnnaBridge	189:f392fc9709a3	427	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
AnnaBridge	189:f392fc9709a3	428	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
AnnaBridge	189:f392fc9709a3	429	* @retval None
AnnaBridge	189:f392fc9709a3	430	*/
AnnaBridge	189:f392fc9709a3	431	__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
AnnaBridge	189:f392fc9709a3	432	{
AnnaBridge	189:f392fc9709a3	433	MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
AnnaBridge	189:f392fc9709a3	434	}
AnnaBridge	189:f392fc9709a3	435
AnnaBridge	189:f392fc9709a3	436	/**
AnnaBridge	189:f392fc9709a3	437	* @brief Get the internal Regulator output voltage in STOP mode
AnnaBridge	189:f392fc9709a3	438	* @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling
AnnaBridge	189:f392fc9709a3	439	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	440	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
AnnaBridge	189:f392fc9709a3	441	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
AnnaBridge	189:f392fc9709a3	442	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
AnnaBridge	189:f392fc9709a3	443	*/
AnnaBridge	189:f392fc9709a3	444	__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
AnnaBridge	189:f392fc9709a3	445	{
AnnaBridge	189:f392fc9709a3	446	return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
AnnaBridge	189:f392fc9709a3	447	}
AnnaBridge	189:f392fc9709a3	448
AnnaBridge	189:f392fc9709a3	449	/**
AnnaBridge	189:f392fc9709a3	450	* @brief Enable Analog Power Voltage Detector
AnnaBridge	189:f392fc9709a3	451	* @rmtoll CR1 AVDEN LL_PWR_EnableAVD
AnnaBridge	189:f392fc9709a3	452	* @retval None
AnnaBridge	189:f392fc9709a3	453	*/
AnnaBridge	189:f392fc9709a3	454	__STATIC_INLINE void LL_PWR_EnableAVD(void)
AnnaBridge	189:f392fc9709a3	455	{
AnnaBridge	189:f392fc9709a3	456	SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
AnnaBridge	189:f392fc9709a3	457	}
AnnaBridge	189:f392fc9709a3	458
AnnaBridge	189:f392fc9709a3	459	/**
AnnaBridge	189:f392fc9709a3	460	* @brief Disable Analog Power Voltage Detector
AnnaBridge	189:f392fc9709a3	461	* @rmtoll CR1 AVDEN LL_PWR_DisableAVD
AnnaBridge	189:f392fc9709a3	462	* @retval None
AnnaBridge	189:f392fc9709a3	463	*/
AnnaBridge	189:f392fc9709a3	464	__STATIC_INLINE void LL_PWR_DisableAVD(void)
AnnaBridge	189:f392fc9709a3	465	{
AnnaBridge	189:f392fc9709a3	466	CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
AnnaBridge	189:f392fc9709a3	467	}
AnnaBridge	189:f392fc9709a3	468
AnnaBridge	189:f392fc9709a3	469	/**
AnnaBridge	189:f392fc9709a3	470	* @brief Check if Analog Power Voltage Detector is enabled
AnnaBridge	189:f392fc9709a3	471	* @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD
AnnaBridge	189:f392fc9709a3	472	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	473	*/
AnnaBridge	189:f392fc9709a3	474	__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
AnnaBridge	189:f392fc9709a3	475	{
AnnaBridge	189:f392fc9709a3	476	return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	477	}
AnnaBridge	189:f392fc9709a3	478
AnnaBridge	189:f392fc9709a3	479	/**
AnnaBridge	189:f392fc9709a3	480	* @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector
AnnaBridge	189:f392fc9709a3	481	* @rmtoll CR1 ALS LL_PWR_SetAVDLevel
AnnaBridge	189:f392fc9709a3	482	* @param AVDLevel This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	483	* @arg @ref LL_PWR_AVDLEVEL_0
AnnaBridge	189:f392fc9709a3	484	* @arg @ref LL_PWR_AVDLEVEL_1
AnnaBridge	189:f392fc9709a3	485	* @arg @ref LL_PWR_AVDLEVEL_2
AnnaBridge	189:f392fc9709a3	486	* @arg @ref LL_PWR_AVDLEVEL_3
AnnaBridge	189:f392fc9709a3	487	* @retval None
AnnaBridge	189:f392fc9709a3	488	*/
AnnaBridge	189:f392fc9709a3	489	__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
AnnaBridge	189:f392fc9709a3	490	{
AnnaBridge	189:f392fc9709a3	491	MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
AnnaBridge	189:f392fc9709a3	492	}
AnnaBridge	189:f392fc9709a3	493
AnnaBridge	189:f392fc9709a3	494	/**
AnnaBridge	189:f392fc9709a3	495	* @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
AnnaBridge	189:f392fc9709a3	496	* @rmtoll CR1 ALS LL_PWR_GetAVDLevel
AnnaBridge	189:f392fc9709a3	497	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	498	* @arg @ref LL_PWR_AVDLEVEL_0
AnnaBridge	189:f392fc9709a3	499	* @arg @ref LL_PWR_AVDLEVEL_1
AnnaBridge	189:f392fc9709a3	500	* @arg @ref LL_PWR_AVDLEVEL_2
AnnaBridge	189:f392fc9709a3	501	* @arg @ref LL_PWR_AVDLEVEL_3
AnnaBridge	189:f392fc9709a3	502	*/
AnnaBridge	189:f392fc9709a3	503	__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
AnnaBridge	189:f392fc9709a3	504	{
AnnaBridge	189:f392fc9709a3	505	return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
AnnaBridge	189:f392fc9709a3	506	}
AnnaBridge	189:f392fc9709a3	507
AnnaBridge	189:f392fc9709a3	508	/**
AnnaBridge	189:f392fc9709a3	509	* @brief Enable Backup Regulator
AnnaBridge	189:f392fc9709a3	510	* @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator
AnnaBridge	189:f392fc9709a3	511	* @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
AnnaBridge	189:f392fc9709a3	512	* VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
AnnaBridge	189:f392fc9709a3	513	* SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
AnnaBridge	189:f392fc9709a3	514	* the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
AnnaBridge	189:f392fc9709a3	515	* the data written into the RAM will be maintained in the Standby and VBAT modes.
AnnaBridge	189:f392fc9709a3	516	* @retval None
AnnaBridge	189:f392fc9709a3	517	*/
AnnaBridge	189:f392fc9709a3	518	__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
AnnaBridge	189:f392fc9709a3	519	{
AnnaBridge	189:f392fc9709a3	520	SET_BIT(PWR->CR2, PWR_CR2_BREN);
AnnaBridge	189:f392fc9709a3	521	}
AnnaBridge	189:f392fc9709a3	522
AnnaBridge	189:f392fc9709a3	523	/**
AnnaBridge	189:f392fc9709a3	524	* @brief Disable Backup Regulator
AnnaBridge	189:f392fc9709a3	525	* @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator
AnnaBridge	189:f392fc9709a3	526	* @retval None
AnnaBridge	189:f392fc9709a3	527	*/
AnnaBridge	189:f392fc9709a3	528	__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
AnnaBridge	189:f392fc9709a3	529	{
AnnaBridge	189:f392fc9709a3	530	CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
AnnaBridge	189:f392fc9709a3	531	}
AnnaBridge	189:f392fc9709a3	532
AnnaBridge	189:f392fc9709a3	533	/**
AnnaBridge	189:f392fc9709a3	534	* @brief Check if the backup Regulator is enabled
AnnaBridge	189:f392fc9709a3	535	* @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator
AnnaBridge	189:f392fc9709a3	536	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	537	*/
AnnaBridge	189:f392fc9709a3	538	__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
AnnaBridge	189:f392fc9709a3	539	{
AnnaBridge	189:f392fc9709a3	540	return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	541	}
AnnaBridge	189:f392fc9709a3	542
AnnaBridge	189:f392fc9709a3	543	/**
AnnaBridge	189:f392fc9709a3	544	* @brief Enable VBAT and Temperature monitoring
AnnaBridge	189:f392fc9709a3	545	* @rmtoll CR2 MONEN LL_PWR_EnableMonitoring
AnnaBridge	189:f392fc9709a3	546	* @retval None
AnnaBridge	189:f392fc9709a3	547	*/
AnnaBridge	189:f392fc9709a3	548	__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
AnnaBridge	189:f392fc9709a3	549	{
AnnaBridge	189:f392fc9709a3	550	SET_BIT(PWR->CR2, PWR_CR2_MONEN);
AnnaBridge	189:f392fc9709a3	551	}
AnnaBridge	189:f392fc9709a3	552
AnnaBridge	189:f392fc9709a3	553	/**
AnnaBridge	189:f392fc9709a3	554	* @brief Disable VBAT and Temperature monitoring
AnnaBridge	189:f392fc9709a3	555	* @rmtoll CR2 MONEN LL_PWR_DisableMonitoring
AnnaBridge	189:f392fc9709a3	556	* @retval None
AnnaBridge	189:f392fc9709a3	557	*/
AnnaBridge	189:f392fc9709a3	558	__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
AnnaBridge	189:f392fc9709a3	559	{
AnnaBridge	189:f392fc9709a3	560	CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
AnnaBridge	189:f392fc9709a3	561	}
AnnaBridge	189:f392fc9709a3	562
AnnaBridge	189:f392fc9709a3	563	/**
AnnaBridge	189:f392fc9709a3	564	* @brief Check if the VBAT and Temperature monitoring is enabled
AnnaBridge	189:f392fc9709a3	565	* @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring
AnnaBridge	189:f392fc9709a3	566	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	567	*/
AnnaBridge	189:f392fc9709a3	568	__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
AnnaBridge	189:f392fc9709a3	569	{
AnnaBridge	189:f392fc9709a3	570	return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	571	}
AnnaBridge	189:f392fc9709a3	572
AnnaBridge	189:f392fc9709a3	573	/**
AnnaBridge	189:f392fc9709a3	574	* @brief Configure the PWR supply
AnnaBridge	189:f392fc9709a3	575	* @rmtoll CR3 BYPASS LL_PWR_ConfigSupply
AnnaBridge	189:f392fc9709a3	576	* @rmtoll CR3 LDOEN LL_PWR_ConfigSupply
AnnaBridge	189:f392fc9709a3	577	* @rmtoll CR3 SCUEN LL_PWR_ConfigSupply
AnnaBridge	189:f392fc9709a3	578	* @param SupplySource This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	579	* @arg @ref LL_PWR_LDO_SUPPLY
AnnaBridge	189:f392fc9709a3	580	* @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
AnnaBridge	189:f392fc9709a3	581	* @retval None
AnnaBridge	189:f392fc9709a3	582	*/
AnnaBridge	189:f392fc9709a3	583	__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
AnnaBridge	189:f392fc9709a3	584	{
AnnaBridge	189:f392fc9709a3	585	/* Set the power supply configuration */
AnnaBridge	189:f392fc9709a3	586	MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN \| PWR_CR3_LDOEN \| PWR_CR3_BYPASS), SupplySource);
AnnaBridge	189:f392fc9709a3	587	}
AnnaBridge	189:f392fc9709a3	588
AnnaBridge	189:f392fc9709a3	589	/**
AnnaBridge	189:f392fc9709a3	590	* @brief Get the PWR supply
AnnaBridge	189:f392fc9709a3	591	* @rmtoll CR3 BYPASS LL_PWR_GetSupply
AnnaBridge	189:f392fc9709a3	592	* @rmtoll CR3 LDOEN LL_PWR_GetSupply
AnnaBridge	189:f392fc9709a3	593	* @rmtoll CR3 SCUEN LL_PWR_GetSupply
AnnaBridge	189:f392fc9709a3	594	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	595	* @arg @ref LL_PWR_LDO_SUPPLY
AnnaBridge	189:f392fc9709a3	596	* @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
AnnaBridge	189:f392fc9709a3	597	*/
AnnaBridge	189:f392fc9709a3	598	__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
AnnaBridge	189:f392fc9709a3	599	{
AnnaBridge	189:f392fc9709a3	600	/* Get the power supply configuration */
AnnaBridge	189:f392fc9709a3	601	return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN \| PWR_CR3_LDOEN \| PWR_CR3_BYPASS)));
AnnaBridge	189:f392fc9709a3	602	}
AnnaBridge	189:f392fc9709a3	603
AnnaBridge	189:f392fc9709a3	604	/**
AnnaBridge	189:f392fc9709a3	605	* @brief Enable battery charging
AnnaBridge	189:f392fc9709a3	606	* @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging
AnnaBridge	189:f392fc9709a3	607	* @retval None
AnnaBridge	189:f392fc9709a3	608	*/
AnnaBridge	189:f392fc9709a3	609	__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
AnnaBridge	189:f392fc9709a3	610	{
AnnaBridge	189:f392fc9709a3	611	SET_BIT(PWR->CR3, PWR_CR3_VBE);
AnnaBridge	189:f392fc9709a3	612	}
AnnaBridge	189:f392fc9709a3	613
AnnaBridge	189:f392fc9709a3	614	/**
AnnaBridge	189:f392fc9709a3	615	* @brief Disable battery charging
AnnaBridge	189:f392fc9709a3	616	* @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging
AnnaBridge	189:f392fc9709a3	617	* @retval None
AnnaBridge	189:f392fc9709a3	618	*/
AnnaBridge	189:f392fc9709a3	619	__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
AnnaBridge	189:f392fc9709a3	620	{
AnnaBridge	189:f392fc9709a3	621	CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
AnnaBridge	189:f392fc9709a3	622	}
AnnaBridge	189:f392fc9709a3	623
AnnaBridge	189:f392fc9709a3	624	/**
AnnaBridge	189:f392fc9709a3	625	* @brief Check if battery charging is enabled
AnnaBridge	189:f392fc9709a3	626	* @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging
AnnaBridge	189:f392fc9709a3	627	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	628	*/
AnnaBridge	189:f392fc9709a3	629	__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
AnnaBridge	189:f392fc9709a3	630	{
AnnaBridge	189:f392fc9709a3	631	return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	632	}
AnnaBridge	189:f392fc9709a3	633
AnnaBridge	189:f392fc9709a3	634	/**
AnnaBridge	189:f392fc9709a3	635	* @brief Set the Battery charge resistor impedance
AnnaBridge	189:f392fc9709a3	636	* @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor
AnnaBridge	189:f392fc9709a3	637	* @param Resistor This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	638	* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
AnnaBridge	189:f392fc9709a3	639	* @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
AnnaBridge	189:f392fc9709a3	640	* @retval None
AnnaBridge	189:f392fc9709a3	641	*/
AnnaBridge	189:f392fc9709a3	642	__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
AnnaBridge	189:f392fc9709a3	643	{
AnnaBridge	189:f392fc9709a3	644	MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
AnnaBridge	189:f392fc9709a3	645	}
AnnaBridge	189:f392fc9709a3	646
AnnaBridge	189:f392fc9709a3	647	/**
AnnaBridge	189:f392fc9709a3	648	* @brief Get the Battery charge resistor impedance
AnnaBridge	189:f392fc9709a3	649	* @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor
AnnaBridge	189:f392fc9709a3	650	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	651	* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
AnnaBridge	189:f392fc9709a3	652	* @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
AnnaBridge	189:f392fc9709a3	653	*/
AnnaBridge	189:f392fc9709a3	654	__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
AnnaBridge	189:f392fc9709a3	655	{
AnnaBridge	189:f392fc9709a3	656	return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
AnnaBridge	189:f392fc9709a3	657	}
AnnaBridge	189:f392fc9709a3	658
AnnaBridge	189:f392fc9709a3	659	/**
AnnaBridge	189:f392fc9709a3	660	* @brief Enable the USB regulator
AnnaBridge	189:f392fc9709a3	661	* @rmtoll CR3 USBREGEN LL_PWR_EnableUSBReg
AnnaBridge	189:f392fc9709a3	662	* @retval None
AnnaBridge	189:f392fc9709a3	663	*/
AnnaBridge	189:f392fc9709a3	664	__STATIC_INLINE void LL_PWR_EnableUSBReg(void)
AnnaBridge	189:f392fc9709a3	665	{
AnnaBridge	189:f392fc9709a3	666	SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
AnnaBridge	189:f392fc9709a3	667	}
AnnaBridge	189:f392fc9709a3	668
AnnaBridge	189:f392fc9709a3	669	/**
AnnaBridge	189:f392fc9709a3	670	* @brief Disable the USB regulator
AnnaBridge	189:f392fc9709a3	671	* @rmtoll CR3 USBREGEN LL_PWR_DisableUSBReg
AnnaBridge	189:f392fc9709a3	672	* @retval None
AnnaBridge	189:f392fc9709a3	673	*/
AnnaBridge	189:f392fc9709a3	674	__STATIC_INLINE void LL_PWR_DisableUSBReg(void)
AnnaBridge	189:f392fc9709a3	675	{
AnnaBridge	189:f392fc9709a3	676	CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
AnnaBridge	189:f392fc9709a3	677	}
AnnaBridge	189:f392fc9709a3	678
AnnaBridge	189:f392fc9709a3	679	/**
AnnaBridge	189:f392fc9709a3	680	* @brief Check if the USB regulator is enabled
AnnaBridge	189:f392fc9709a3	681	* @rmtoll CR3 USBREGEN LL_PWR_IsEnabledUSBReg
AnnaBridge	189:f392fc9709a3	682	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	683	*/
AnnaBridge	189:f392fc9709a3	684	__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
AnnaBridge	189:f392fc9709a3	685	{
AnnaBridge	189:f392fc9709a3	686	return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	687	}
AnnaBridge	189:f392fc9709a3	688
AnnaBridge	189:f392fc9709a3	689	/**
AnnaBridge	189:f392fc9709a3	690	* @brief Enable the USB voltage detector
AnnaBridge	189:f392fc9709a3	691	* @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector
AnnaBridge	189:f392fc9709a3	692	* @retval None
AnnaBridge	189:f392fc9709a3	693	*/
AnnaBridge	189:f392fc9709a3	694	__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
AnnaBridge	189:f392fc9709a3	695	{
AnnaBridge	189:f392fc9709a3	696	SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
AnnaBridge	189:f392fc9709a3	697	}
AnnaBridge	189:f392fc9709a3	698
AnnaBridge	189:f392fc9709a3	699	/**
AnnaBridge	189:f392fc9709a3	700	* @brief Disable the USB voltage detector
AnnaBridge	189:f392fc9709a3	701	* @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector
AnnaBridge	189:f392fc9709a3	702	* @retval None
AnnaBridge	189:f392fc9709a3	703	*/
AnnaBridge	189:f392fc9709a3	704	__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
AnnaBridge	189:f392fc9709a3	705	{
AnnaBridge	189:f392fc9709a3	706	CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
AnnaBridge	189:f392fc9709a3	707	}
AnnaBridge	189:f392fc9709a3	708
AnnaBridge	189:f392fc9709a3	709	/**
AnnaBridge	189:f392fc9709a3	710	* @brief Check if the USB voltage detector is enabled
AnnaBridge	189:f392fc9709a3	711	* @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector
AnnaBridge	189:f392fc9709a3	712	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	713	*/
AnnaBridge	189:f392fc9709a3	714	__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
AnnaBridge	189:f392fc9709a3	715	{
AnnaBridge	189:f392fc9709a3	716	return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	717	}
AnnaBridge	189:f392fc9709a3	718
AnnaBridge	189:f392fc9709a3	719	/**
AnnaBridge	189:f392fc9709a3	720	* @brief Set the D1 domain Power Down mode when the CPU enters deepsleep
AnnaBridge	189:f392fc9709a3	721	* @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_SetD1PowerMode\n
AnnaBridge	189:f392fc9709a3	722	* @param PDMode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	723	* @arg @ref LL_PWR_CPU_MODE_D1STOP
AnnaBridge	189:f392fc9709a3	724	* @arg @ref LL_PWR_CPU_MODE_D1STANDBY
AnnaBridge	189:f392fc9709a3	725	* @retval None
AnnaBridge	189:f392fc9709a3	726	*/
AnnaBridge	189:f392fc9709a3	727	__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
AnnaBridge	189:f392fc9709a3	728	{
AnnaBridge	189:f392fc9709a3	729	MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
AnnaBridge	189:f392fc9709a3	730	}
AnnaBridge	189:f392fc9709a3	731
AnnaBridge	189:f392fc9709a3	732	/**
AnnaBridge	189:f392fc9709a3	733	* @brief Get the D1 Domain Power Down mode when the CPU enters deepsleep
AnnaBridge	189:f392fc9709a3	734	* @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_GetD1PowerMode\n
AnnaBridge	189:f392fc9709a3	735	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	736	* @arg @ref LL_PWR_CPU_MODE_D1STOP
AnnaBridge	189:f392fc9709a3	737	* @arg @ref LL_PWR_CPU_MODE_D1STANDBY
AnnaBridge	189:f392fc9709a3	738	*/
AnnaBridge	189:f392fc9709a3	739	__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
AnnaBridge	189:f392fc9709a3	740	{
AnnaBridge	189:f392fc9709a3	741	return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
AnnaBridge	189:f392fc9709a3	742	}
AnnaBridge	189:f392fc9709a3	743
AnnaBridge	189:f392fc9709a3	744	/**
AnnaBridge	189:f392fc9709a3	745	* @brief Set the D2 domain Power Down mode when the CPU enters deepsleep
AnnaBridge	189:f392fc9709a3	746	* @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_SetD2PowerMode\n
AnnaBridge	189:f392fc9709a3	747	* @param PDMode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	748	* @arg @ref LL_PWR_CPU_MODE_D2STOP
AnnaBridge	189:f392fc9709a3	749	* @arg @ref LL_PWR_CPU_MODE_D2STANDBY
AnnaBridge	189:f392fc9709a3	750	* @retval None
AnnaBridge	189:f392fc9709a3	751	*/
AnnaBridge	189:f392fc9709a3	752	__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
AnnaBridge	189:f392fc9709a3	753	{
AnnaBridge	189:f392fc9709a3	754	MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
AnnaBridge	189:f392fc9709a3	755	}
AnnaBridge	189:f392fc9709a3	756
AnnaBridge	189:f392fc9709a3	757	/**
AnnaBridge	189:f392fc9709a3	758	* @brief Get the D2 Domain Power Down mode when the CPU enters deepsleep
AnnaBridge	189:f392fc9709a3	759	* @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_GetD2PowerMode\n
AnnaBridge	189:f392fc9709a3	760	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	761	* @arg @ref LL_PWR_CPU_MODE_D2STOP
AnnaBridge	189:f392fc9709a3	762	* @arg @ref LL_PWR_CPU_MODE_D2STANDBY
AnnaBridge	189:f392fc9709a3	763	*/
AnnaBridge	189:f392fc9709a3	764	__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
AnnaBridge	189:f392fc9709a3	765	{
AnnaBridge	189:f392fc9709a3	766	return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
AnnaBridge	189:f392fc9709a3	767	}
AnnaBridge	189:f392fc9709a3	768
AnnaBridge	189:f392fc9709a3	769	/**
AnnaBridge	189:f392fc9709a3	770	* @brief Set the D3 domain Power Down mode when the CPU enters deepsleep
AnnaBridge	189:f392fc9709a3	771	* @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_SetD3PowerMode\n
AnnaBridge	189:f392fc9709a3	772	* @param PDMode This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	773	* @arg @ref LL_PWR_CPU_MODE_D3STOP
AnnaBridge	189:f392fc9709a3	774	* @arg @ref LL_PWR_CPU_MODE_D3STANDBY
AnnaBridge	189:f392fc9709a3	775	* @retval None
AnnaBridge	189:f392fc9709a3	776	*/
AnnaBridge	189:f392fc9709a3	777	__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
AnnaBridge	189:f392fc9709a3	778	{
AnnaBridge	189:f392fc9709a3	779	MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
AnnaBridge	189:f392fc9709a3	780	}
AnnaBridge	189:f392fc9709a3	781
AnnaBridge	189:f392fc9709a3	782	/**
AnnaBridge	189:f392fc9709a3	783	* @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep
AnnaBridge	189:f392fc9709a3	784	* @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode\n
AnnaBridge	189:f392fc9709a3	785	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	786	* @arg @ref LL_PWR_CPU_MODE_D3STOP
AnnaBridge	189:f392fc9709a3	787	* @arg @ref LL_PWR_CPU_MODE_D3STANDBY
AnnaBridge	189:f392fc9709a3	788	*/
AnnaBridge	189:f392fc9709a3	789	__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
AnnaBridge	189:f392fc9709a3	790	{
AnnaBridge	189:f392fc9709a3	791	return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
AnnaBridge	189:f392fc9709a3	792	}
AnnaBridge	189:f392fc9709a3	793
AnnaBridge	189:f392fc9709a3	794	/**
AnnaBridge	189:f392fc9709a3	795	* @brief D3 domain remains in Run mode regardless of CPU subsystem modes
AnnaBridge	189:f392fc9709a3	796	* @rmtoll CPUCR RUN_D3 LL_PWR_CPU_EnableD3RunInLowPowerMode\n
AnnaBridge	189:f392fc9709a3	797	* @retval None
AnnaBridge	189:f392fc9709a3	798	*/
AnnaBridge	189:f392fc9709a3	799	__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
AnnaBridge	189:f392fc9709a3	800	{
AnnaBridge	189:f392fc9709a3	801	SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
AnnaBridge	189:f392fc9709a3	802	}
AnnaBridge	189:f392fc9709a3	803
AnnaBridge	189:f392fc9709a3	804	/**
AnnaBridge	189:f392fc9709a3	805	* @brief D3 domain follows CPU subsystem modes
AnnaBridge	189:f392fc9709a3	806	* @rmtoll CPUCR RUN_D3 LL_PWR_CPU_DisableD3RunInLowPowerMode\n
AnnaBridge	189:f392fc9709a3	807	* @retval None
AnnaBridge	189:f392fc9709a3	808	*/
AnnaBridge	189:f392fc9709a3	809	__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
AnnaBridge	189:f392fc9709a3	810	{
AnnaBridge	189:f392fc9709a3	811	CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
AnnaBridge	189:f392fc9709a3	812	}
AnnaBridge	189:f392fc9709a3	813
AnnaBridge	189:f392fc9709a3	814	/**
AnnaBridge	189:f392fc9709a3	815	* @brief Check if D3 is kept in Run mode when CPU enters low power mode
AnnaBridge	189:f392fc9709a3	816	* @rmtoll CPUCR RUN_D3 LL_PWR_CPU_IsEnabledD3RunInLowPowerMode\n
AnnaBridge	189:f392fc9709a3	817	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	818	*/
AnnaBridge	189:f392fc9709a3	819	__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
AnnaBridge	189:f392fc9709a3	820	{
AnnaBridge	189:f392fc9709a3	821	return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	822	}
AnnaBridge	189:f392fc9709a3	823
AnnaBridge	189:f392fc9709a3	824	/**
AnnaBridge	189:f392fc9709a3	825	* @brief Set the main internal Regulator output voltage
AnnaBridge	189:f392fc9709a3	826	* @rmtoll D3CR VOS LL_PWR_SetRegulVoltageScaling
AnnaBridge	189:f392fc9709a3	827	* @param VoltageScaling This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	828	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
AnnaBridge	189:f392fc9709a3	829	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
AnnaBridge	189:f392fc9709a3	830	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
AnnaBridge	189:f392fc9709a3	831	* @retval None
AnnaBridge	189:f392fc9709a3	832	*/
AnnaBridge	189:f392fc9709a3	833	__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
AnnaBridge	189:f392fc9709a3	834	{
AnnaBridge	189:f392fc9709a3	835	MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
AnnaBridge	189:f392fc9709a3	836	}
AnnaBridge	189:f392fc9709a3	837
AnnaBridge	189:f392fc9709a3	838	/**
AnnaBridge	189:f392fc9709a3	839	* @brief Get the main internal Regulator output voltage
AnnaBridge	189:f392fc9709a3	840	* @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling
AnnaBridge	189:f392fc9709a3	841	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	842	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
AnnaBridge	189:f392fc9709a3	843	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
AnnaBridge	189:f392fc9709a3	844	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
AnnaBridge	189:f392fc9709a3	845	*/
AnnaBridge	189:f392fc9709a3	846	__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
AnnaBridge	189:f392fc9709a3	847	{
AnnaBridge	189:f392fc9709a3	848	return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
AnnaBridge	189:f392fc9709a3	849	}
AnnaBridge	189:f392fc9709a3	850
AnnaBridge	189:f392fc9709a3	851	/**
AnnaBridge	189:f392fc9709a3	852	* @brief Enable the WakeUp PINx functionality
AnnaBridge	189:f392fc9709a3	853	* @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n
AnnaBridge	189:f392fc9709a3	854	* WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n
AnnaBridge	189:f392fc9709a3	855	* WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n
AnnaBridge	189:f392fc9709a3	856	* WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin\n
AnnaBridge	189:f392fc9709a3	857	* WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin\n
AnnaBridge	189:f392fc9709a3	858	* WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin
AnnaBridge	189:f392fc9709a3	859	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	860	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	189:f392fc9709a3	861	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	189:f392fc9709a3	862	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	189:f392fc9709a3	863	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	189:f392fc9709a3	864	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	189:f392fc9709a3	865	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	189:f392fc9709a3	866	* @retval None
AnnaBridge	189:f392fc9709a3	867	*/
AnnaBridge	189:f392fc9709a3	868	__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
AnnaBridge	189:f392fc9709a3	869	{
AnnaBridge	189:f392fc9709a3	870	SET_BIT(PWR->WKUPEPR, WakeUpPin);
AnnaBridge	189:f392fc9709a3	871	}
AnnaBridge	189:f392fc9709a3	872
AnnaBridge	189:f392fc9709a3	873	/**
AnnaBridge	189:f392fc9709a3	874	* @brief Disable the WakeUp PINx functionality
AnnaBridge	189:f392fc9709a3	875	* @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n
AnnaBridge	189:f392fc9709a3	876	* WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n
AnnaBridge	189:f392fc9709a3	877	* WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n
AnnaBridge	189:f392fc9709a3	878	* WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin\n
AnnaBridge	189:f392fc9709a3	879	* WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin\n
AnnaBridge	189:f392fc9709a3	880	* WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin
AnnaBridge	189:f392fc9709a3	881	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	882	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	189:f392fc9709a3	883	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	189:f392fc9709a3	884	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	189:f392fc9709a3	885	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	189:f392fc9709a3	886	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	189:f392fc9709a3	887	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	189:f392fc9709a3	888	* @retval None
AnnaBridge	189:f392fc9709a3	889	*/
AnnaBridge	189:f392fc9709a3	890	__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
AnnaBridge	189:f392fc9709a3	891	{
AnnaBridge	189:f392fc9709a3	892	CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
AnnaBridge	189:f392fc9709a3	893	}
AnnaBridge	189:f392fc9709a3	894
AnnaBridge	189:f392fc9709a3	895	/**
AnnaBridge	189:f392fc9709a3	896	* @brief Check if the WakeUp PINx functionality is enabled
AnnaBridge	189:f392fc9709a3	897	* @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	189:f392fc9709a3	898	* WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	189:f392fc9709a3	899	* WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	189:f392fc9709a3	900	* WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	189:f392fc9709a3	901	* WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	189:f392fc9709a3	902	* WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin
AnnaBridge	189:f392fc9709a3	903	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	904	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	189:f392fc9709a3	905	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	189:f392fc9709a3	906	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	189:f392fc9709a3	907	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	189:f392fc9709a3	908	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	189:f392fc9709a3	909	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	189:f392fc9709a3	910	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	911	*/
AnnaBridge	189:f392fc9709a3	912	__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
AnnaBridge	189:f392fc9709a3	913	{
AnnaBridge	189:f392fc9709a3	914	return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	915	}
AnnaBridge	189:f392fc9709a3	916
AnnaBridge	189:f392fc9709a3	917	/**
AnnaBridge	189:f392fc9709a3	918	* @brief Set the Wake-Up pin polarity low for the event detection
AnnaBridge	189:f392fc9709a3	919	* @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge	189:f392fc9709a3	920	* WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge	189:f392fc9709a3	921	* WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge	189:f392fc9709a3	922	* WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge	189:f392fc9709a3	923	* WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge	189:f392fc9709a3	924	* WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow
AnnaBridge	189:f392fc9709a3	925	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	926	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	189:f392fc9709a3	927	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	189:f392fc9709a3	928	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	189:f392fc9709a3	929	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	189:f392fc9709a3	930	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	189:f392fc9709a3	931	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	189:f392fc9709a3	932	* @retval None
AnnaBridge	189:f392fc9709a3	933	*/
AnnaBridge	189:f392fc9709a3	934	__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
AnnaBridge	189:f392fc9709a3	935	{
AnnaBridge	189:f392fc9709a3	936	SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
AnnaBridge	189:f392fc9709a3	937	}
AnnaBridge	189:f392fc9709a3	938
AnnaBridge	189:f392fc9709a3	939	/**
AnnaBridge	189:f392fc9709a3	940	* @brief Set the Wake-Up pin polarity high for the event detection
AnnaBridge	189:f392fc9709a3	941	* @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge	189:f392fc9709a3	942	* WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge	189:f392fc9709a3	943	* WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge	189:f392fc9709a3	944	* WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge	189:f392fc9709a3	945	* WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge	189:f392fc9709a3	946	* WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh
AnnaBridge	189:f392fc9709a3	947	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	948	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	189:f392fc9709a3	949	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	189:f392fc9709a3	950	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	189:f392fc9709a3	951	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	189:f392fc9709a3	952	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	189:f392fc9709a3	953	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	189:f392fc9709a3	954	* @retval None
AnnaBridge	189:f392fc9709a3	955	*/
AnnaBridge	189:f392fc9709a3	956	__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
AnnaBridge	189:f392fc9709a3	957	{
AnnaBridge	189:f392fc9709a3	958	CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
AnnaBridge	189:f392fc9709a3	959	}
AnnaBridge	189:f392fc9709a3	960
AnnaBridge	189:f392fc9709a3	961	/**
AnnaBridge	189:f392fc9709a3	962	* @brief Get the Wake-Up pin polarity for the event detection
AnnaBridge	189:f392fc9709a3	963	* @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge	189:f392fc9709a3	964	* WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge	189:f392fc9709a3	965	* WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge	189:f392fc9709a3	966	* WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge	189:f392fc9709a3	967	* WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge	189:f392fc9709a3	968	* WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow
AnnaBridge	189:f392fc9709a3	969	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	970	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	189:f392fc9709a3	971	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	189:f392fc9709a3	972	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	189:f392fc9709a3	973	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	189:f392fc9709a3	974	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	189:f392fc9709a3	975	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	189:f392fc9709a3	976	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	977	*/
AnnaBridge	189:f392fc9709a3	978	__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
AnnaBridge	189:f392fc9709a3	979	{
AnnaBridge	189:f392fc9709a3	980	return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	981	}
AnnaBridge	189:f392fc9709a3	982
AnnaBridge	189:f392fc9709a3	983	/**
AnnaBridge	189:f392fc9709a3	984	* @brief Set the Wake-Up pin Pull None
AnnaBridge	189:f392fc9709a3	985	* @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n
AnnaBridge	189:f392fc9709a3	986	* WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n
AnnaBridge	189:f392fc9709a3	987	* WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n
AnnaBridge	189:f392fc9709a3	988	* WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n
AnnaBridge	189:f392fc9709a3	989	* WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n
AnnaBridge	189:f392fc9709a3	990	* WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone
AnnaBridge	189:f392fc9709a3	991	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	992	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	189:f392fc9709a3	993	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	189:f392fc9709a3	994	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	189:f392fc9709a3	995	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	189:f392fc9709a3	996	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	189:f392fc9709a3	997	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	189:f392fc9709a3	998	* @retval None
AnnaBridge	189:f392fc9709a3	999	*/
AnnaBridge	189:f392fc9709a3	1000	__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
AnnaBridge	189:f392fc9709a3	1001	{
AnnaBridge	189:f392fc9709a3	1002	MODIFY_REG(PWR->WKUPEPR, \
AnnaBridge	189:f392fc9709a3	1003	(PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
AnnaBridge	189:f392fc9709a3	1004	(LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
AnnaBridge	189:f392fc9709a3	1005	}
AnnaBridge	189:f392fc9709a3	1006
AnnaBridge	189:f392fc9709a3	1007	/**
AnnaBridge	189:f392fc9709a3	1008	* @brief Set the Wake-Up pin Pull Up
AnnaBridge	189:f392fc9709a3	1009	* @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n
AnnaBridge	189:f392fc9709a3	1010	* WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n
AnnaBridge	189:f392fc9709a3	1011	* WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n
AnnaBridge	189:f392fc9709a3	1012	* WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n
AnnaBridge	189:f392fc9709a3	1013	* WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n
AnnaBridge	189:f392fc9709a3	1014	* WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp
AnnaBridge	189:f392fc9709a3	1015	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1016	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	189:f392fc9709a3	1017	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	189:f392fc9709a3	1018	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	189:f392fc9709a3	1019	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	189:f392fc9709a3	1020	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	189:f392fc9709a3	1021	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	189:f392fc9709a3	1022	* @retval None
AnnaBridge	189:f392fc9709a3	1023	*/
AnnaBridge	189:f392fc9709a3	1024	__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
AnnaBridge	189:f392fc9709a3	1025	{
AnnaBridge	189:f392fc9709a3	1026	MODIFY_REG(PWR->WKUPEPR, \
AnnaBridge	189:f392fc9709a3	1027	(PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
AnnaBridge	189:f392fc9709a3	1028	(LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
AnnaBridge	189:f392fc9709a3	1029	}
AnnaBridge	189:f392fc9709a3	1030
AnnaBridge	189:f392fc9709a3	1031	/**
AnnaBridge	189:f392fc9709a3	1032	* @brief Set the Wake-Up pin Pull Down
AnnaBridge	189:f392fc9709a3	1033	* @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n
AnnaBridge	189:f392fc9709a3	1034	* WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n
AnnaBridge	189:f392fc9709a3	1035	* WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n
AnnaBridge	189:f392fc9709a3	1036	* WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n
AnnaBridge	189:f392fc9709a3	1037	* WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n
AnnaBridge	189:f392fc9709a3	1038	* WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown
AnnaBridge	189:f392fc9709a3	1039	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1040	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	189:f392fc9709a3	1041	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	189:f392fc9709a3	1042	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	189:f392fc9709a3	1043	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	189:f392fc9709a3	1044	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	189:f392fc9709a3	1045	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	189:f392fc9709a3	1046	* @retval None
AnnaBridge	189:f392fc9709a3	1047	*/
AnnaBridge	189:f392fc9709a3	1048	__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
AnnaBridge	189:f392fc9709a3	1049	{
AnnaBridge	189:f392fc9709a3	1050	MODIFY_REG(PWR->WKUPEPR, \
AnnaBridge	189:f392fc9709a3	1051	(PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
AnnaBridge	189:f392fc9709a3	1052	(LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
AnnaBridge	189:f392fc9709a3	1053	}
AnnaBridge	189:f392fc9709a3	1054
AnnaBridge	189:f392fc9709a3	1055	/**
AnnaBridge	189:f392fc9709a3	1056	* @brief Get the Wake-Up pin pull
AnnaBridge	189:f392fc9709a3	1057	* @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n
AnnaBridge	189:f392fc9709a3	1058	* WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n
AnnaBridge	189:f392fc9709a3	1059	* WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n
AnnaBridge	189:f392fc9709a3	1060	* WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n
AnnaBridge	189:f392fc9709a3	1061	* WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n
AnnaBridge	189:f392fc9709a3	1062	* WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull
AnnaBridge	189:f392fc9709a3	1063	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1064	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	189:f392fc9709a3	1065	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	189:f392fc9709a3	1066	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	189:f392fc9709a3	1067	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	189:f392fc9709a3	1068	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	189:f392fc9709a3	1069	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	189:f392fc9709a3	1070	* @retval Returned value can be one of the following values:
AnnaBridge	189:f392fc9709a3	1071	* @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
AnnaBridge	189:f392fc9709a3	1072	* @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
AnnaBridge	189:f392fc9709a3	1073	* @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
AnnaBridge	189:f392fc9709a3	1074	*/
AnnaBridge	189:f392fc9709a3	1075	__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
AnnaBridge	189:f392fc9709a3	1076	{
AnnaBridge	189:f392fc9709a3	1077	register uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
AnnaBridge	189:f392fc9709a3	1078
AnnaBridge	189:f392fc9709a3	1079	return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
AnnaBridge	189:f392fc9709a3	1080	}
AnnaBridge	189:f392fc9709a3	1081
AnnaBridge	189:f392fc9709a3	1082	/**
AnnaBridge	189:f392fc9709a3	1083	* @}
AnnaBridge	189:f392fc9709a3	1084	*/
AnnaBridge	189:f392fc9709a3	1085
AnnaBridge	189:f392fc9709a3	1086	/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	189:f392fc9709a3	1087	* @{
AnnaBridge	189:f392fc9709a3	1088	*/
AnnaBridge	189:f392fc9709a3	1089
AnnaBridge	189:f392fc9709a3	1090	/**
AnnaBridge	189:f392fc9709a3	1091	* @brief Indicate whether VDD voltage is below the selected PVD threshold
AnnaBridge	189:f392fc9709a3	1092	* @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO
AnnaBridge	189:f392fc9709a3	1093	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1094	*/
AnnaBridge	189:f392fc9709a3	1095	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
AnnaBridge	189:f392fc9709a3	1096	{
AnnaBridge	189:f392fc9709a3	1097	return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1098	}
AnnaBridge	189:f392fc9709a3	1099
AnnaBridge	189:f392fc9709a3	1100	/**
AnnaBridge	189:f392fc9709a3	1101	* @brief Indicate whether the voltage level is ready for current actual used VOS
AnnaBridge	189:f392fc9709a3	1102	* @rmtoll CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
AnnaBridge	189:f392fc9709a3	1103	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1104	*/
AnnaBridge	189:f392fc9709a3	1105	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
AnnaBridge	189:f392fc9709a3	1106	{
AnnaBridge	189:f392fc9709a3	1107	return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1108	}
AnnaBridge	189:f392fc9709a3	1109
AnnaBridge	189:f392fc9709a3	1110	/**
AnnaBridge	189:f392fc9709a3	1111	* @brief Indicate whether VDDA voltage is below the selected AVD threshold
AnnaBridge	189:f392fc9709a3	1112	* @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO
AnnaBridge	189:f392fc9709a3	1113	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1114	*/
AnnaBridge	189:f392fc9709a3	1115	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
AnnaBridge	189:f392fc9709a3	1116	{
AnnaBridge	189:f392fc9709a3	1117	return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1118	}
AnnaBridge	189:f392fc9709a3	1119
AnnaBridge	189:f392fc9709a3	1120	/**
AnnaBridge	189:f392fc9709a3	1121	* @brief Get Backup Regulator ready Flag
AnnaBridge	189:f392fc9709a3	1122	* @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR
AnnaBridge	189:f392fc9709a3	1123	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1124	*/
AnnaBridge	189:f392fc9709a3	1125	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
AnnaBridge	189:f392fc9709a3	1126	{
AnnaBridge	189:f392fc9709a3	1127	return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1128	}
AnnaBridge	189:f392fc9709a3	1129
AnnaBridge	189:f392fc9709a3	1130	/**
AnnaBridge	189:f392fc9709a3	1131	* @brief Indicate whether the VBAT level is above or below low threshold
AnnaBridge	189:f392fc9709a3	1132	* @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL
AnnaBridge	189:f392fc9709a3	1133	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1134	*/
AnnaBridge	189:f392fc9709a3	1135	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
AnnaBridge	189:f392fc9709a3	1136	{
AnnaBridge	189:f392fc9709a3	1137	return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1138	}
AnnaBridge	189:f392fc9709a3	1139
AnnaBridge	189:f392fc9709a3	1140	/**
AnnaBridge	189:f392fc9709a3	1141	* @brief Indicate whether the VBAT level is above or below high threshold
AnnaBridge	189:f392fc9709a3	1142	* @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH
AnnaBridge	189:f392fc9709a3	1143	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1144	*/
AnnaBridge	189:f392fc9709a3	1145	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
AnnaBridge	189:f392fc9709a3	1146	{
AnnaBridge	189:f392fc9709a3	1147	return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1148	}
AnnaBridge	189:f392fc9709a3	1149
AnnaBridge	189:f392fc9709a3	1150	/**
AnnaBridge	189:f392fc9709a3	1151	* @brief Indicate whether the CPU temperature level is above or below low threshold
AnnaBridge	189:f392fc9709a3	1152	* @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL
AnnaBridge	189:f392fc9709a3	1153	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1154	*/
AnnaBridge	189:f392fc9709a3	1155	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
AnnaBridge	189:f392fc9709a3	1156	{
AnnaBridge	189:f392fc9709a3	1157	return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1158	}
AnnaBridge	189:f392fc9709a3	1159
AnnaBridge	189:f392fc9709a3	1160	/**
AnnaBridge	189:f392fc9709a3	1161	* @brief Indicate whether the CPU temperature level is above or below high threshold
AnnaBridge	189:f392fc9709a3	1162	* @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH
AnnaBridge	189:f392fc9709a3	1163	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1164	*/
AnnaBridge	189:f392fc9709a3	1165	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
AnnaBridge	189:f392fc9709a3	1166	{
AnnaBridge	189:f392fc9709a3	1167	return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1168	}
AnnaBridge	189:f392fc9709a3	1169
AnnaBridge	189:f392fc9709a3	1170	/**
AnnaBridge	189:f392fc9709a3	1171	* @brief Indicate whether the USB supply is ready or not
AnnaBridge	189:f392fc9709a3	1172	* @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB
AnnaBridge	189:f392fc9709a3	1173	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1174	*/
AnnaBridge	189:f392fc9709a3	1175	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
AnnaBridge	189:f392fc9709a3	1176	{
AnnaBridge	189:f392fc9709a3	1177	return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1178	}
AnnaBridge	189:f392fc9709a3	1179
AnnaBridge	189:f392fc9709a3	1180	/**
AnnaBridge	189:f392fc9709a3	1181	* @brief Get CPU System Stop Flag
AnnaBridge	189:f392fc9709a3	1182	* @rmtoll CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP
AnnaBridge	189:f392fc9709a3	1183	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1184	*/
AnnaBridge	189:f392fc9709a3	1185	__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
AnnaBridge	189:f392fc9709a3	1186	{
AnnaBridge	189:f392fc9709a3	1187	return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1188	}
AnnaBridge	189:f392fc9709a3	1189
AnnaBridge	189:f392fc9709a3	1190	/**
AnnaBridge	189:f392fc9709a3	1191	* @brief Get CPU System Standby Flag
AnnaBridge	189:f392fc9709a3	1192	* @rmtoll CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB
AnnaBridge	189:f392fc9709a3	1193	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1194	*/
AnnaBridge	189:f392fc9709a3	1195	__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
AnnaBridge	189:f392fc9709a3	1196	{
AnnaBridge	189:f392fc9709a3	1197	return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1198	}
AnnaBridge	189:f392fc9709a3	1199
AnnaBridge	189:f392fc9709a3	1200	/**
AnnaBridge	189:f392fc9709a3	1201	* @brief Get CPU D1 Domain Standby Flag
AnnaBridge	189:f392fc9709a3	1202	* @rmtoll CPUCR SBF_D1 LL_PWR_CPU_IsActiveFlag_SB_D1
AnnaBridge	189:f392fc9709a3	1203	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1204	*/
AnnaBridge	189:f392fc9709a3	1205	__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
AnnaBridge	189:f392fc9709a3	1206	{
AnnaBridge	189:f392fc9709a3	1207	return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1208	}
AnnaBridge	189:f392fc9709a3	1209
AnnaBridge	189:f392fc9709a3	1210	/**
AnnaBridge	189:f392fc9709a3	1211	* @brief Get CPU D2 Domain Standby Flag
AnnaBridge	189:f392fc9709a3	1212	* @rmtoll CPUCR SBF_D2 LL_PWR_CPU_IsActiveFlag_SB_D2
AnnaBridge	189:f392fc9709a3	1213	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1214	*/
AnnaBridge	189:f392fc9709a3	1215	__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
AnnaBridge	189:f392fc9709a3	1216	{
AnnaBridge	189:f392fc9709a3	1217	return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1218	}
AnnaBridge	189:f392fc9709a3	1219
AnnaBridge	189:f392fc9709a3	1220	/**
AnnaBridge	189:f392fc9709a3	1221	* @brief Indicate whether the Regulator is ready in the selected voltage range
AnnaBridge	189:f392fc9709a3	1222	* or if its output voltage is still changing to the required voltage level
AnnaBridge	189:f392fc9709a3	1223	* @rmtoll D3CR VOSRDY LL_PWR_IsActiveFlag_VOS
AnnaBridge	189:f392fc9709a3	1224	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1225	*/
AnnaBridge	189:f392fc9709a3	1226	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
AnnaBridge	189:f392fc9709a3	1227	{
AnnaBridge	189:f392fc9709a3	1228	return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1229	}
AnnaBridge	189:f392fc9709a3	1230
AnnaBridge	189:f392fc9709a3	1231	/**
AnnaBridge	189:f392fc9709a3	1232	* @brief Get Wake-up Flag 6
AnnaBridge	189:f392fc9709a3	1233	* @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6
AnnaBridge	189:f392fc9709a3	1234	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1235	*/
AnnaBridge	189:f392fc9709a3	1236	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
AnnaBridge	189:f392fc9709a3	1237	{
AnnaBridge	189:f392fc9709a3	1238	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1239	}
AnnaBridge	189:f392fc9709a3	1240
AnnaBridge	189:f392fc9709a3	1241	/**
AnnaBridge	189:f392fc9709a3	1242	* @brief Get Wake-up Flag 5
AnnaBridge	189:f392fc9709a3	1243	* @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5
AnnaBridge	189:f392fc9709a3	1244	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1245	*/
AnnaBridge	189:f392fc9709a3	1246	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
AnnaBridge	189:f392fc9709a3	1247	{
AnnaBridge	189:f392fc9709a3	1248	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1249	}
AnnaBridge	189:f392fc9709a3	1250
AnnaBridge	189:f392fc9709a3	1251	/**
AnnaBridge	189:f392fc9709a3	1252	* @brief Get Wake-up Flag 4
AnnaBridge	189:f392fc9709a3	1253	* @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4
AnnaBridge	189:f392fc9709a3	1254	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1255	*/
AnnaBridge	189:f392fc9709a3	1256	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
AnnaBridge	189:f392fc9709a3	1257	{
AnnaBridge	189:f392fc9709a3	1258	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1259	}
AnnaBridge	189:f392fc9709a3	1260
AnnaBridge	189:f392fc9709a3	1261	/**
AnnaBridge	189:f392fc9709a3	1262	* @brief Get Wake-up Flag 3
AnnaBridge	189:f392fc9709a3	1263	* @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3
AnnaBridge	189:f392fc9709a3	1264	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1265	*/
AnnaBridge	189:f392fc9709a3	1266	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
AnnaBridge	189:f392fc9709a3	1267	{
AnnaBridge	189:f392fc9709a3	1268	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1269	}
AnnaBridge	189:f392fc9709a3	1270
AnnaBridge	189:f392fc9709a3	1271	/**
AnnaBridge	189:f392fc9709a3	1272	* @brief Get Wake-up Flag 2
AnnaBridge	189:f392fc9709a3	1273	* @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2
AnnaBridge	189:f392fc9709a3	1274	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1275	*/
AnnaBridge	189:f392fc9709a3	1276	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
AnnaBridge	189:f392fc9709a3	1277	{
AnnaBridge	189:f392fc9709a3	1278	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1279	}
AnnaBridge	189:f392fc9709a3	1280
AnnaBridge	189:f392fc9709a3	1281	/**
AnnaBridge	189:f392fc9709a3	1282	* @brief Get Wake-up Flag 1
AnnaBridge	189:f392fc9709a3	1283	* @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1
AnnaBridge	189:f392fc9709a3	1284	* @retval State of bit (1 or 0).
AnnaBridge	189:f392fc9709a3	1285	*/
AnnaBridge	189:f392fc9709a3	1286	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
AnnaBridge	189:f392fc9709a3	1287	{
AnnaBridge	189:f392fc9709a3	1288	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
AnnaBridge	189:f392fc9709a3	1289	}
AnnaBridge	189:f392fc9709a3	1290
AnnaBridge	189:f392fc9709a3	1291	/**
AnnaBridge	189:f392fc9709a3	1292	* @brief Clear CPU STANDBY, STOP and HOLD flags
AnnaBridge	189:f392fc9709a3	1293	* @rmtoll CPUCR CSSF LL_PWR_ClearFlag_CPU
AnnaBridge	189:f392fc9709a3	1294	* @retval None
AnnaBridge	189:f392fc9709a3	1295	*/
AnnaBridge	189:f392fc9709a3	1296	__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
AnnaBridge	189:f392fc9709a3	1297	{
AnnaBridge	189:f392fc9709a3	1298	SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
AnnaBridge	189:f392fc9709a3	1299	}
AnnaBridge	189:f392fc9709a3	1300
AnnaBridge	189:f392fc9709a3	1301	/**
AnnaBridge	189:f392fc9709a3	1302	* @brief Clear Wake-up Flag 6
AnnaBridge	189:f392fc9709a3	1303	* @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6
AnnaBridge	189:f392fc9709a3	1304	* @retval None
AnnaBridge	189:f392fc9709a3	1305	*/
AnnaBridge	189:f392fc9709a3	1306	__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
AnnaBridge	189:f392fc9709a3	1307	{
AnnaBridge	189:f392fc9709a3	1308	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
AnnaBridge	189:f392fc9709a3	1309	}
AnnaBridge	189:f392fc9709a3	1310
AnnaBridge	189:f392fc9709a3	1311	/**
AnnaBridge	189:f392fc9709a3	1312	* @brief Clear Wake-up Flag 5
AnnaBridge	189:f392fc9709a3	1313	* @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5
AnnaBridge	189:f392fc9709a3	1314	* @retval None
AnnaBridge	189:f392fc9709a3	1315	*/
AnnaBridge	189:f392fc9709a3	1316	__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
AnnaBridge	189:f392fc9709a3	1317	{
AnnaBridge	189:f392fc9709a3	1318	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
AnnaBridge	189:f392fc9709a3	1319	}
AnnaBridge	189:f392fc9709a3	1320
AnnaBridge	189:f392fc9709a3	1321	/**
AnnaBridge	189:f392fc9709a3	1322	* @brief Clear Wake-up Flag 4
AnnaBridge	189:f392fc9709a3	1323	* @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4
AnnaBridge	189:f392fc9709a3	1324	* @retval None
AnnaBridge	189:f392fc9709a3	1325	*/
AnnaBridge	189:f392fc9709a3	1326	__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
AnnaBridge	189:f392fc9709a3	1327	{
AnnaBridge	189:f392fc9709a3	1328	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
AnnaBridge	189:f392fc9709a3	1329	}
AnnaBridge	189:f392fc9709a3	1330
AnnaBridge	189:f392fc9709a3	1331	/**
AnnaBridge	189:f392fc9709a3	1332	* @brief Clear Wake-up Flag 3
AnnaBridge	189:f392fc9709a3	1333	* @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3
AnnaBridge	189:f392fc9709a3	1334	* @retval None
AnnaBridge	189:f392fc9709a3	1335	*/
AnnaBridge	189:f392fc9709a3	1336	__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
AnnaBridge	189:f392fc9709a3	1337	{
AnnaBridge	189:f392fc9709a3	1338	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
AnnaBridge	189:f392fc9709a3	1339	}
AnnaBridge	189:f392fc9709a3	1340
AnnaBridge	189:f392fc9709a3	1341	/**
AnnaBridge	189:f392fc9709a3	1342	* @brief Clear Wake-up Flag 2
AnnaBridge	189:f392fc9709a3	1343	* @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2
AnnaBridge	189:f392fc9709a3	1344	* @retval None
AnnaBridge	189:f392fc9709a3	1345	*/
AnnaBridge	189:f392fc9709a3	1346	__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
AnnaBridge	189:f392fc9709a3	1347	{
AnnaBridge	189:f392fc9709a3	1348	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
AnnaBridge	189:f392fc9709a3	1349	}
AnnaBridge	189:f392fc9709a3	1350
AnnaBridge	189:f392fc9709a3	1351	/**
AnnaBridge	189:f392fc9709a3	1352	* @brief Clear Wake-up Flag 1
AnnaBridge	189:f392fc9709a3	1353	* @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1
AnnaBridge	189:f392fc9709a3	1354	* @retval None
AnnaBridge	189:f392fc9709a3	1355	*/
AnnaBridge	189:f392fc9709a3	1356	__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
AnnaBridge	189:f392fc9709a3	1357	{
AnnaBridge	189:f392fc9709a3	1358	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
AnnaBridge	189:f392fc9709a3	1359	}
AnnaBridge	189:f392fc9709a3	1360
AnnaBridge	189:f392fc9709a3	1361	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	189:f392fc9709a3	1362	/** @defgroup PWR_LL_EF_Init De-initialization function
AnnaBridge	189:f392fc9709a3	1363	* @{
AnnaBridge	189:f392fc9709a3	1364	*/
AnnaBridge	189:f392fc9709a3	1365	ErrorStatus LL_PWR_DeInit(void);
AnnaBridge	189:f392fc9709a3	1366	/**
AnnaBridge	189:f392fc9709a3	1367	* @}
AnnaBridge	189:f392fc9709a3	1368	*/
AnnaBridge	189:f392fc9709a3	1369	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	189:f392fc9709a3	1370
AnnaBridge	189:f392fc9709a3	1371
AnnaBridge	189:f392fc9709a3	1372	/**
AnnaBridge	189:f392fc9709a3	1373	* @}
AnnaBridge	189:f392fc9709a3	1374	*/
AnnaBridge	189:f392fc9709a3	1375
AnnaBridge	189:f392fc9709a3	1376	/**
AnnaBridge	189:f392fc9709a3	1377	* @}
AnnaBridge	189:f392fc9709a3	1378	*/
AnnaBridge	189:f392fc9709a3	1379
AnnaBridge	189:f392fc9709a3	1380	/**
AnnaBridge	189:f392fc9709a3	1381	* @}
AnnaBridge	189:f392fc9709a3	1382	*/
AnnaBridge	189:f392fc9709a3	1383
AnnaBridge	189:f392fc9709a3	1384	#endif /* defined(PWR) */
AnnaBridge	189:f392fc9709a3	1385
AnnaBridge	189:f392fc9709a3	1386	/**
AnnaBridge	189:f392fc9709a3	1387	* @}
AnnaBridge	189:f392fc9709a3	1388	*/
AnnaBridge	189:f392fc9709a3	1389
AnnaBridge	189:f392fc9709a3	1390	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	1391	}
AnnaBridge	189:f392fc9709a3	1392	#endif
AnnaBridge	189:f392fc9709a3	1393
AnnaBridge	189:f392fc9709a3	1394	#endif /* STM32H7xx_LL_PWR_H */
AnnaBridge	189:f392fc9709a3	1395
AnnaBridge	189:f392fc9709a3	1396	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/