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targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32h7xx_hal_tim_ex.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of TIM HAL Extended module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
| AnnaBridge | 189:f392fc9709a3 | 10 | * All rights reserved.</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 11 | * |
| AnnaBridge | 189:f392fc9709a3 | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| AnnaBridge | 189:f392fc9709a3 | 13 | * the "License"; You may not use this file except in compliance with the |
| AnnaBridge | 189:f392fc9709a3 | 14 | * License. You may obtain a copy of the License at: |
| AnnaBridge | 189:f392fc9709a3 | 15 | * opensource.org/licenses/BSD-3-Clause |
| AnnaBridge | 189:f392fc9709a3 | 16 | * |
| AnnaBridge | 189:f392fc9709a3 | 17 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 18 | */ |
| AnnaBridge | 189:f392fc9709a3 | 19 | |
| AnnaBridge | 189:f392fc9709a3 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 21 | #ifndef STM32H7xx_HAL_TIM_EX_H |
| AnnaBridge | 189:f392fc9709a3 | 22 | #define STM32H7xx_HAL_TIM_EX_H |
| AnnaBridge | 189:f392fc9709a3 | 23 | |
| AnnaBridge | 189:f392fc9709a3 | 24 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 25 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 26 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 27 | |
| AnnaBridge | 189:f392fc9709a3 | 28 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 29 | #include "stm32h7xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 30 | |
| AnnaBridge | 189:f392fc9709a3 | 31 | /** @addtogroup STM32H7xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 32 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 33 | */ |
| AnnaBridge | 189:f392fc9709a3 | 34 | |
| AnnaBridge | 189:f392fc9709a3 | 35 | /** @addtogroup TIMEx |
| AnnaBridge | 189:f392fc9709a3 | 36 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 37 | */ |
| AnnaBridge | 189:f392fc9709a3 | 38 | |
| AnnaBridge | 189:f392fc9709a3 | 39 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 40 | /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 41 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 42 | */ |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /** |
| AnnaBridge | 189:f392fc9709a3 | 45 | * @brief TIM Hall sensor Configuration Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 46 | */ |
| AnnaBridge | 189:f392fc9709a3 | 47 | |
| AnnaBridge | 189:f392fc9709a3 | 48 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 49 | { |
| AnnaBridge | 189:f392fc9709a3 | 50 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
| AnnaBridge | 189:f392fc9709a3 | 51 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
| AnnaBridge | 189:f392fc9709a3 | 54 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| AnnaBridge | 189:f392fc9709a3 | 55 | |
| AnnaBridge | 189:f392fc9709a3 | 56 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
| AnnaBridge | 189:f392fc9709a3 | 57 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| AnnaBridge | 189:f392fc9709a3 | 58 | |
| AnnaBridge | 189:f392fc9709a3 | 59 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
| AnnaBridge | 189:f392fc9709a3 | 60 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
| AnnaBridge | 189:f392fc9709a3 | 61 | } TIM_HallSensor_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 62 | #if defined(TIM_BREAK_INPUT_SUPPORT) |
| AnnaBridge | 189:f392fc9709a3 | 63 | |
| AnnaBridge | 189:f392fc9709a3 | 64 | /** |
| AnnaBridge | 189:f392fc9709a3 | 65 | * @brief TIM Break/Break2 input configuration |
| AnnaBridge | 189:f392fc9709a3 | 66 | */ |
| AnnaBridge | 189:f392fc9709a3 | 67 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 68 | { |
| AnnaBridge | 189:f392fc9709a3 | 69 | uint32_t Source; /*!< Specifies the source of the timer break input. |
| AnnaBridge | 189:f392fc9709a3 | 70 | This parameter can be a value of @ref TIMEx_Break_Input_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. |
| AnnaBridge | 189:f392fc9709a3 | 72 | This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | uint32_t Polarity; /*!< Specifies the break input source polarity. |
| AnnaBridge | 189:f392fc9709a3 | 74 | This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity |
| AnnaBridge | 189:f392fc9709a3 | 75 | Not relevant when analog watchdog output of the DFSDM1 used as break input source */ |
| AnnaBridge | 189:f392fc9709a3 | 76 | } |
| AnnaBridge | 189:f392fc9709a3 | 77 | TIMEx_BreakInputConfigTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 78 | |
| AnnaBridge | 189:f392fc9709a3 | 79 | #endif /* TIM_BREAK_INPUT_SUPPORT */ |
| AnnaBridge | 189:f392fc9709a3 | 80 | /** |
| AnnaBridge | 189:f392fc9709a3 | 81 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 82 | */ |
| AnnaBridge | 189:f392fc9709a3 | 83 | /* End of exported types -----------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 84 | |
| AnnaBridge | 189:f392fc9709a3 | 85 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 86 | /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 87 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 88 | */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | |
| AnnaBridge | 189:f392fc9709a3 | 90 | /** @defgroup TIMEx_Remap TIM Extended Remapping |
| AnnaBridge | 189:f392fc9709a3 | 91 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 92 | */ |
| AnnaBridge | 189:f392fc9709a3 | 93 | #define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 94 | #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 96 | #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ |
| AnnaBridge | 189:f392fc9709a3 | 97 | #define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */ |
| AnnaBridge | 189:f392fc9709a3 | 98 | #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | #define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */ |
| AnnaBridge | 189:f392fc9709a3 | 100 | #define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | #define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | |
| AnnaBridge | 189:f392fc9709a3 | 103 | #define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | #define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 105 | #define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 106 | #define TIM_TIM8_ETR_ADC1_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD1 */ |
| AnnaBridge | 189:f392fc9709a3 | 107 | #define TIM_TIM8_ETR_ADC1_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC1 AWD2 */ |
| AnnaBridge | 189:f392fc9709a3 | 108 | #define TIM_TIM8_ETR_ADC1_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD3 */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | #define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | #define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */ |
| AnnaBridge | 189:f392fc9709a3 | 111 | #define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | |
| AnnaBridge | 189:f392fc9709a3 | 113 | #define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | #define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 115 | #define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 116 | #define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 117 | #define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | #define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */ |
| AnnaBridge | 189:f392fc9709a3 | 119 | |
| AnnaBridge | 189:f392fc9709a3 | 120 | #define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | #define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | |
| AnnaBridge | 189:f392fc9709a3 | 123 | #define TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 124 | #define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | #define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */ |
| AnnaBridge | 189:f392fc9709a3 | 126 | /** |
| AnnaBridge | 189:f392fc9709a3 | 127 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 128 | */ |
| AnnaBridge | 189:f392fc9709a3 | 129 | #if defined(TIM_BREAK_INPUT_SUPPORT) |
| AnnaBridge | 189:f392fc9709a3 | 130 | |
| AnnaBridge | 189:f392fc9709a3 | 131 | /** @defgroup TIMEx_Break_Input TIM Extended Break input |
| AnnaBridge | 189:f392fc9709a3 | 132 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 133 | */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | #define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ |
| AnnaBridge | 189:f392fc9709a3 | 135 | #define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | /** |
| AnnaBridge | 189:f392fc9709a3 | 137 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 138 | */ |
| AnnaBridge | 189:f392fc9709a3 | 139 | |
| AnnaBridge | 189:f392fc9709a3 | 140 | /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source |
| AnnaBridge | 189:f392fc9709a3 | 141 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 142 | */ |
| AnnaBridge | 189:f392fc9709a3 | 143 | #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ |
| AnnaBridge | 189:f392fc9709a3 | 146 | #define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | /** |
| AnnaBridge | 189:f392fc9709a3 | 148 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 149 | */ |
| AnnaBridge | 189:f392fc9709a3 | 150 | |
| AnnaBridge | 189:f392fc9709a3 | 151 | /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling |
| AnnaBridge | 189:f392fc9709a3 | 152 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 153 | */ |
| AnnaBridge | 189:f392fc9709a3 | 154 | #define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | #define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | /** |
| AnnaBridge | 189:f392fc9709a3 | 157 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 158 | */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | |
| AnnaBridge | 189:f392fc9709a3 | 160 | /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity |
| AnnaBridge | 189:f392fc9709a3 | 161 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 162 | */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | #define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ |
| AnnaBridge | 189:f392fc9709a3 | 164 | #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ |
| AnnaBridge | 189:f392fc9709a3 | 165 | /** |
| AnnaBridge | 189:f392fc9709a3 | 166 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 167 | */ |
| AnnaBridge | 189:f392fc9709a3 | 168 | #endif /* TIM_BREAK_INPUT_SUPPORT */ |
| AnnaBridge | 189:f392fc9709a3 | 169 | |
| AnnaBridge | 189:f392fc9709a3 | 170 | /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection |
| AnnaBridge | 189:f392fc9709a3 | 171 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 172 | */ |
| AnnaBridge | 189:f392fc9709a3 | 173 | #define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 174 | #define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1_TI1 is connected to COMP1 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 175 | |
| AnnaBridge | 189:f392fc9709a3 | 176 | #define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8_TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8_TI1 is connected to COMP2 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 178 | |
| AnnaBridge | 189:f392fc9709a3 | 179 | #define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | #define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2_TI4 is connected to COMP1 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 181 | #define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2_TI4 is connected to COMP2 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | #define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 183 | |
| AnnaBridge | 189:f392fc9709a3 | 184 | #define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 185 | #define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3_TI1 is connected to COMP1 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3_TI1 is connected to COMP2 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */ |
| AnnaBridge | 189:f392fc9709a3 | 188 | |
| AnnaBridge | 189:f392fc9709a3 | 189 | #define TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 190 | #define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */ |
| AnnaBridge | 189:f392fc9709a3 | 191 | #define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */ |
| AnnaBridge | 189:f392fc9709a3 | 192 | |
| AnnaBridge | 189:f392fc9709a3 | 193 | #define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 194 | #define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | #define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */ |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_3) /* !< TIM15_TI1 is connected to RCC LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 198 | #define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */ |
| AnnaBridge | 189:f392fc9709a3 | 199 | #define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | |
| AnnaBridge | 189:f392fc9709a3 | 201 | #define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 202 | #define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */ |
| AnnaBridge | 189:f392fc9709a3 | 203 | #define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM3 CH2 */ |
| AnnaBridge | 189:f392fc9709a3 | 204 | #define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */ |
| AnnaBridge | 189:f392fc9709a3 | 205 | |
| AnnaBridge | 189:f392fc9709a3 | 206 | #define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 TI1 is connected to RCC LSI */ |
| AnnaBridge | 189:f392fc9709a3 | 208 | #define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 TI1 is connected to RCC LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 209 | #define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | |
| AnnaBridge | 189:f392fc9709a3 | 211 | #define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */ |
| AnnaBridge | 189:f392fc9709a3 | 212 | #define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to RCC LSI */ |
| AnnaBridge | 189:f392fc9709a3 | 213 | #define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC LSE */ |
| AnnaBridge | 189:f392fc9709a3 | 214 | #define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */ |
| AnnaBridge | 189:f392fc9709a3 | 215 | /** |
| AnnaBridge | 189:f392fc9709a3 | 216 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 217 | */ |
| AnnaBridge | 189:f392fc9709a3 | 218 | |
| AnnaBridge | 189:f392fc9709a3 | 219 | /** |
| AnnaBridge | 189:f392fc9709a3 | 220 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 221 | */ |
| AnnaBridge | 189:f392fc9709a3 | 222 | /* End of exported constants -------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 223 | |
| AnnaBridge | 189:f392fc9709a3 | 224 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 225 | /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 226 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 227 | */ |
| AnnaBridge | 189:f392fc9709a3 | 228 | |
| AnnaBridge | 189:f392fc9709a3 | 229 | /** |
| AnnaBridge | 189:f392fc9709a3 | 230 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 231 | */ |
| AnnaBridge | 189:f392fc9709a3 | 232 | /* End of exported macro -----------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 233 | |
| AnnaBridge | 189:f392fc9709a3 | 234 | /* Private macro -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 235 | /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 236 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 237 | */ |
| AnnaBridge | 189:f392fc9709a3 | 238 | #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ |
| AnnaBridge | 189:f392fc9709a3 | 239 | ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) |
| AnnaBridge | 189:f392fc9709a3 | 240 | |
| AnnaBridge | 189:f392fc9709a3 | 241 | #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ |
| AnnaBridge | 189:f392fc9709a3 | 242 | ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ |
| AnnaBridge | 189:f392fc9709a3 | 243 | ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 244 | ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1)) |
| AnnaBridge | 189:f392fc9709a3 | 245 | |
| AnnaBridge | 189:f392fc9709a3 | 246 | #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 247 | ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 248 | |
| AnnaBridge | 189:f392fc9709a3 | 249 | #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ |
| AnnaBridge | 189:f392fc9709a3 | 250 | ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) |
| AnnaBridge | 189:f392fc9709a3 | 251 | |
| AnnaBridge | 189:f392fc9709a3 | 252 | #define IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 253 | ((__TISEL__) == TIM_TIM1_TI1_COMP1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 254 | ((__TISEL__) == TIM_TIM8_TI1_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 255 | ((__TISEL__) == TIM_TIM8_TI1_COMP2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 256 | ((__TISEL__) == TIM_TIM2_TI4_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 257 | ((__TISEL__) == TIM_TIM2_TI4_COMP1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 258 | ((__TISEL__) == TIM_TIM2_TI4_COMP2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 259 | ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 260 | ((__TISEL__) == TIM_TIM3_TI1_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 261 | ((__TISEL__) == TIM_TIM3_TI1_COMP1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 262 | ((__TISEL__) == TIM_TIM3_TI1_COMP2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 263 | ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 264 | ((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 265 | ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 266 | ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 267 | ((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 268 | ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 269 | ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 270 | ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 271 | ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 272 | ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 273 | ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 274 | ((__TISEL__) == TIM_TIM15_TI2_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 275 | ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 276 | ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 277 | ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 278 | ((__TISEL__) == TIM_TIM16_TI1_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 279 | ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 280 | ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 281 | ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 282 | ((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 283 | ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 284 | ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 285 | ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1)) |
| AnnaBridge | 189:f392fc9709a3 | 286 | |
| AnnaBridge | 189:f392fc9709a3 | 287 | #define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 288 | ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 289 | ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 290 | ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 291 | ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 292 | ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 293 | ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 294 | ((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 295 | ((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 296 | ((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 297 | ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 298 | ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 299 | ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD3) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 300 | ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 301 | ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 302 | ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 303 | ((__RREMAP__) == TIM_TIM8_ETR_COMP1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 304 | ((__RREMAP__) == TIM_TIM8_ETR_COMP2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 305 | ((__RREMAP__) == TIM_TIM2_ETR_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 306 | ((__RREMAP__) == TIM_TIM2_ETR_COMP1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 307 | ((__RREMAP__) == TIM_TIM2_ETR_COMP2) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 308 | ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 309 | ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 310 | ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 311 | ((__RREMAP__) == TIM_TIM3_ETR_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 312 | ((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 313 | ((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 314 | ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\ |
| AnnaBridge | 189:f392fc9709a3 | 315 | ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB)) |
| AnnaBridge | 189:f392fc9709a3 | 316 | |
| AnnaBridge | 189:f392fc9709a3 | 317 | |
| AnnaBridge | 189:f392fc9709a3 | 318 | /** |
| AnnaBridge | 189:f392fc9709a3 | 319 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 320 | */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | /* End of private macro ------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 322 | |
| AnnaBridge | 189:f392fc9709a3 | 323 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 324 | /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions |
| AnnaBridge | 189:f392fc9709a3 | 325 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 326 | */ |
| AnnaBridge | 189:f392fc9709a3 | 327 | |
| AnnaBridge | 189:f392fc9709a3 | 328 | /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions |
| AnnaBridge | 189:f392fc9709a3 | 329 | * @brief Timer Hall Sensor functions |
| AnnaBridge | 189:f392fc9709a3 | 330 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 331 | */ |
| AnnaBridge | 189:f392fc9709a3 | 332 | /* Timer Hall Sensor functions **********************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 333 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); |
| AnnaBridge | 189:f392fc9709a3 | 334 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 335 | |
| AnnaBridge | 189:f392fc9709a3 | 336 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 337 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 338 | |
| AnnaBridge | 189:f392fc9709a3 | 339 | /* Blocking mode: Polling */ |
| AnnaBridge | 189:f392fc9709a3 | 340 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 341 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 342 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 343 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 344 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 345 | /* Non-Blocking mode: DMA */ |
| AnnaBridge | 189:f392fc9709a3 | 346 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
| AnnaBridge | 189:f392fc9709a3 | 347 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 348 | /** |
| AnnaBridge | 189:f392fc9709a3 | 349 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 350 | */ |
| AnnaBridge | 189:f392fc9709a3 | 351 | |
| AnnaBridge | 189:f392fc9709a3 | 352 | /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions |
| AnnaBridge | 189:f392fc9709a3 | 353 | * @brief Timer Complementary Output Compare functions |
| AnnaBridge | 189:f392fc9709a3 | 354 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 355 | */ |
| AnnaBridge | 189:f392fc9709a3 | 356 | /* Timer Complementary Output Compare functions *****************************/ |
| AnnaBridge | 189:f392fc9709a3 | 357 | /* Blocking mode: Polling */ |
| AnnaBridge | 189:f392fc9709a3 | 358 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 359 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 360 | |
| AnnaBridge | 189:f392fc9709a3 | 361 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 362 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 363 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 364 | |
| AnnaBridge | 189:f392fc9709a3 | 365 | /* Non-Blocking mode: DMA */ |
| AnnaBridge | 189:f392fc9709a3 | 366 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
| AnnaBridge | 189:f392fc9709a3 | 367 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 368 | /** |
| AnnaBridge | 189:f392fc9709a3 | 369 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 370 | */ |
| AnnaBridge | 189:f392fc9709a3 | 371 | |
| AnnaBridge | 189:f392fc9709a3 | 372 | /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions |
| AnnaBridge | 189:f392fc9709a3 | 373 | * @brief Timer Complementary PWM functions |
| AnnaBridge | 189:f392fc9709a3 | 374 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 375 | */ |
| AnnaBridge | 189:f392fc9709a3 | 376 | /* Timer Complementary PWM functions ****************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 377 | /* Blocking mode: Polling */ |
| AnnaBridge | 189:f392fc9709a3 | 378 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 379 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 380 | |
| AnnaBridge | 189:f392fc9709a3 | 381 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 382 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 383 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 384 | /* Non-Blocking mode: DMA */ |
| AnnaBridge | 189:f392fc9709a3 | 385 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
| AnnaBridge | 189:f392fc9709a3 | 386 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 387 | /** |
| AnnaBridge | 189:f392fc9709a3 | 388 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 389 | */ |
| AnnaBridge | 189:f392fc9709a3 | 390 | |
| AnnaBridge | 189:f392fc9709a3 | 391 | /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions |
| AnnaBridge | 189:f392fc9709a3 | 392 | * @brief Timer Complementary One Pulse functions |
| AnnaBridge | 189:f392fc9709a3 | 393 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 394 | */ |
| AnnaBridge | 189:f392fc9709a3 | 395 | /* Timer Complementary One Pulse functions **********************************/ |
| AnnaBridge | 189:f392fc9709a3 | 396 | /* Blocking mode: Polling */ |
| AnnaBridge | 189:f392fc9709a3 | 397 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| AnnaBridge | 189:f392fc9709a3 | 398 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| AnnaBridge | 189:f392fc9709a3 | 399 | |
| AnnaBridge | 189:f392fc9709a3 | 400 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 189:f392fc9709a3 | 401 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| AnnaBridge | 189:f392fc9709a3 | 402 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| AnnaBridge | 189:f392fc9709a3 | 403 | /** |
| AnnaBridge | 189:f392fc9709a3 | 404 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 405 | */ |
| AnnaBridge | 189:f392fc9709a3 | 406 | |
| AnnaBridge | 189:f392fc9709a3 | 407 | /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 408 | * @brief Peripheral Control functions |
| AnnaBridge | 189:f392fc9709a3 | 409 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 410 | */ |
| AnnaBridge | 189:f392fc9709a3 | 411 | /* Extended Control functions ************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 412 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| AnnaBridge | 189:f392fc9709a3 | 413 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| AnnaBridge | 189:f392fc9709a3 | 414 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| AnnaBridge | 189:f392fc9709a3 | 415 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); |
| AnnaBridge | 189:f392fc9709a3 | 416 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); |
| AnnaBridge | 189:f392fc9709a3 | 417 | #if defined(TIM_BREAK_INPUT_SUPPORT) |
| AnnaBridge | 189:f392fc9709a3 | 418 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); |
| AnnaBridge | 189:f392fc9709a3 | 419 | #endif /* TIM_BREAK_INPUT_SUPPORT */ |
| AnnaBridge | 189:f392fc9709a3 | 420 | HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); |
| AnnaBridge | 189:f392fc9709a3 | 421 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); |
| AnnaBridge | 189:f392fc9709a3 | 422 | HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); |
| AnnaBridge | 189:f392fc9709a3 | 423 | /** |
| AnnaBridge | 189:f392fc9709a3 | 424 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 425 | */ |
| AnnaBridge | 189:f392fc9709a3 | 426 | |
| AnnaBridge | 189:f392fc9709a3 | 427 | /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions |
| AnnaBridge | 189:f392fc9709a3 | 428 | * @brief Extended Callbacks functions |
| AnnaBridge | 189:f392fc9709a3 | 429 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 430 | */ |
| AnnaBridge | 189:f392fc9709a3 | 431 | /* Extended Callback **********************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 432 | void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 433 | void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 434 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 435 | void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 436 | /** |
| AnnaBridge | 189:f392fc9709a3 | 437 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 438 | */ |
| AnnaBridge | 189:f392fc9709a3 | 439 | |
| AnnaBridge | 189:f392fc9709a3 | 440 | /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions |
| AnnaBridge | 189:f392fc9709a3 | 441 | * @brief Extended Peripheral State functions |
| AnnaBridge | 189:f392fc9709a3 | 442 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 443 | */ |
| AnnaBridge | 189:f392fc9709a3 | 444 | /* Extended Peripheral State functions ***************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 445 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); |
| AnnaBridge | 189:f392fc9709a3 | 446 | /** |
| AnnaBridge | 189:f392fc9709a3 | 447 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 448 | */ |
| AnnaBridge | 189:f392fc9709a3 | 449 | |
| AnnaBridge | 189:f392fc9709a3 | 450 | /** |
| AnnaBridge | 189:f392fc9709a3 | 451 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 452 | */ |
| AnnaBridge | 189:f392fc9709a3 | 453 | /* End of exported functions -------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 454 | |
| AnnaBridge | 189:f392fc9709a3 | 455 | /* Private functions----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 456 | /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions |
| AnnaBridge | 189:f392fc9709a3 | 457 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 458 | */ |
| AnnaBridge | 189:f392fc9709a3 | 459 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 189:f392fc9709a3 | 460 | void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 189:f392fc9709a3 | 461 | /** |
| AnnaBridge | 189:f392fc9709a3 | 462 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 463 | */ |
| AnnaBridge | 189:f392fc9709a3 | 464 | /* End of private functions --------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 465 | |
| AnnaBridge | 189:f392fc9709a3 | 466 | /** |
| AnnaBridge | 189:f392fc9709a3 | 467 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 468 | */ |
| AnnaBridge | 189:f392fc9709a3 | 469 | |
| AnnaBridge | 189:f392fc9709a3 | 470 | /** |
| AnnaBridge | 189:f392fc9709a3 | 471 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 472 | */ |
| AnnaBridge | 189:f392fc9709a3 | 473 | |
| AnnaBridge | 189:f392fc9709a3 | 474 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 475 | } |
| AnnaBridge | 189:f392fc9709a3 | 476 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 477 | |
| AnnaBridge | 189:f392fc9709a3 | 478 | |
| AnnaBridge | 189:f392fc9709a3 | 479 | #endif /* STM32H7xx_HAL_TIM_EX_H */ |
| AnnaBridge | 189:f392fc9709a3 | 480 | |
| AnnaBridge | 189:f392fc9709a3 | 481 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
