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targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sram.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 ******************************************************************************
AnnaBridge 189:f392fc9709a3 3 * @file stm32h7xx_hal_sram.c
AnnaBridge 189:f392fc9709a3 4 * @author MCD Application Team
AnnaBridge 189:f392fc9709a3 5 * @brief SRAM HAL module driver.
AnnaBridge 189:f392fc9709a3 6 * This file provides a generic firmware to drive SRAM memories
AnnaBridge 189:f392fc9709a3 7 * mounted as external device.
AnnaBridge 189:f392fc9709a3 8 *
AnnaBridge 189:f392fc9709a3 9 @verbatim
AnnaBridge 189:f392fc9709a3 10 ==============================================================================
AnnaBridge 189:f392fc9709a3 11 ##### How to use this driver #####
AnnaBridge 189:f392fc9709a3 12 ==============================================================================
AnnaBridge 189:f392fc9709a3 13 [..]
AnnaBridge 189:f392fc9709a3 14 This driver is a generic layered driver which contains a set of APIs used to
AnnaBridge 189:f392fc9709a3 15 control SRAM memories. It uses the FMC layer functions to interface
AnnaBridge 189:f392fc9709a3 16 with SRAM devices.
AnnaBridge 189:f392fc9709a3 17 The following sequence should be followed to configure the FMC to interface
AnnaBridge 189:f392fc9709a3 18 with SRAM/PSRAM memories:
AnnaBridge 189:f392fc9709a3 19
AnnaBridge 189:f392fc9709a3 20 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
AnnaBridge 189:f392fc9709a3 21 SRAM_HandleTypeDef hsram; and:
AnnaBridge 189:f392fc9709a3 22
AnnaBridge 189:f392fc9709a3 23 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
AnnaBridge 189:f392fc9709a3 24 values of the structure member.
AnnaBridge 189:f392fc9709a3 25
AnnaBridge 189:f392fc9709a3 26 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
AnnaBridge 189:f392fc9709a3 27 base register instance for NOR or SRAM device
AnnaBridge 189:f392fc9709a3 28
AnnaBridge 189:f392fc9709a3 29 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
AnnaBridge 189:f392fc9709a3 30 base register instance for NOR or SRAM extended mode
AnnaBridge 189:f392fc9709a3 31
AnnaBridge 189:f392fc9709a3 32 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
AnnaBridge 189:f392fc9709a3 33 mode timings; for example:
AnnaBridge 189:f392fc9709a3 34 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
AnnaBridge 189:f392fc9709a3 35 and fill its fields with the allowed values of the structure member.
AnnaBridge 189:f392fc9709a3 36
AnnaBridge 189:f392fc9709a3 37 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
AnnaBridge 189:f392fc9709a3 38 performs the following sequence:
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
AnnaBridge 189:f392fc9709a3 41 (##) Control register configuration using the FMC NORSRAM interface function
AnnaBridge 189:f392fc9709a3 42 FMC_NORSRAM_Init()
AnnaBridge 189:f392fc9709a3 43 (##) Timing register configuration using the FMC NORSRAM interface function
AnnaBridge 189:f392fc9709a3 44 FMC_NORSRAM_Timing_Init()
AnnaBridge 189:f392fc9709a3 45 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
AnnaBridge 189:f392fc9709a3 46 FMC_NORSRAM_Extended_Timing_Init()
AnnaBridge 189:f392fc9709a3 47 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
AnnaBridge 189:f392fc9709a3 48
AnnaBridge 189:f392fc9709a3 49 (#) At this stage you can perform read/write accesses from/to the memory connected
AnnaBridge 189:f392fc9709a3 50 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
AnnaBridge 189:f392fc9709a3 51 following APIs:
AnnaBridge 189:f392fc9709a3 52 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
AnnaBridge 189:f392fc9709a3 53 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
AnnaBridge 189:f392fc9709a3 56 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
AnnaBridge 189:f392fc9709a3 57
AnnaBridge 189:f392fc9709a3 58 (#) You can continuously monitor the SRAM device HAL state by calling the function
AnnaBridge 189:f392fc9709a3 59 HAL_SRAM_GetState()
AnnaBridge 189:f392fc9709a3 60
AnnaBridge 189:f392fc9709a3 61 *** Callback registration ***
AnnaBridge 189:f392fc9709a3 62 =============================================
AnnaBridge 189:f392fc9709a3 63 [..]
AnnaBridge 189:f392fc9709a3 64 The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
AnnaBridge 189:f392fc9709a3 65 allows the user to configure dynamically the driver callbacks.
AnnaBridge 189:f392fc9709a3 66
AnnaBridge 189:f392fc9709a3 67 Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
AnnaBridge 189:f392fc9709a3 68 it allows to register following callbacks:
AnnaBridge 189:f392fc9709a3 69 (+) MspInitCallback : SRAM MspInit.
AnnaBridge 189:f392fc9709a3 70 (+) MspDeInitCallback : SRAM MspDeInit.
AnnaBridge 189:f392fc9709a3 71 This function takes as parameters the HAL peripheral handle, the Callback ID
AnnaBridge 189:f392fc9709a3 72 and a pointer to the user callback function.
AnnaBridge 189:f392fc9709a3 73
AnnaBridge 189:f392fc9709a3 74 Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
AnnaBridge 189:f392fc9709a3 75 weak (surcharged) function. It allows to reset following callbacks:
AnnaBridge 189:f392fc9709a3 76 (+) MspInitCallback : SRAM MspInit.
AnnaBridge 189:f392fc9709a3 77 (+) MspDeInitCallback : SRAM MspDeInit.
AnnaBridge 189:f392fc9709a3 78 This function) takes as parameters the HAL peripheral handle and the Callback ID.
AnnaBridge 189:f392fc9709a3 79
AnnaBridge 189:f392fc9709a3 80 By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
AnnaBridge 189:f392fc9709a3 81 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
AnnaBridge 189:f392fc9709a3 82 Exception done for MspInit and MspDeInit callbacks that are respectively
AnnaBridge 189:f392fc9709a3 83 reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
AnnaBridge 189:f392fc9709a3 84 and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
AnnaBridge 189:f392fc9709a3 85 If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
AnnaBridge 189:f392fc9709a3 86 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
AnnaBridge 189:f392fc9709a3 87
AnnaBridge 189:f392fc9709a3 88 Callbacks can be registered/unregistered in READY state only.
AnnaBridge 189:f392fc9709a3 89 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
AnnaBridge 189:f392fc9709a3 90 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
AnnaBridge 189:f392fc9709a3 91 during the Init/DeInit.
AnnaBridge 189:f392fc9709a3 92 In that case first register the MspInit/MspDeInit user callbacks
AnnaBridge 189:f392fc9709a3 93 using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
AnnaBridge 189:f392fc9709a3 94 or @ref HAL_SRAM_Init function.
AnnaBridge 189:f392fc9709a3 95
AnnaBridge 189:f392fc9709a3 96 When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
AnnaBridge 189:f392fc9709a3 97 not defined, the callback registering feature is not available
AnnaBridge 189:f392fc9709a3 98 and weak (surcharged) callbacks are used.
AnnaBridge 189:f392fc9709a3 99
AnnaBridge 189:f392fc9709a3 100 @endverbatim
AnnaBridge 189:f392fc9709a3 101 ******************************************************************************
AnnaBridge 189:f392fc9709a3 102 * @attention
AnnaBridge 189:f392fc9709a3 103 *
AnnaBridge 189:f392fc9709a3 104 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 189:f392fc9709a3 105 *
AnnaBridge 189:f392fc9709a3 106 * This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge 189:f392fc9709a3 107 * the "License"; You may not use this file except in compliance with the
AnnaBridge 189:f392fc9709a3 108 * License. You may obtain a copy of the License at:
AnnaBridge 189:f392fc9709a3 109 * opensource.org/licenses/BSD-3-Clause
AnnaBridge 189:f392fc9709a3 110 *
AnnaBridge 189:f392fc9709a3 111 ******************************************************************************
AnnaBridge 189:f392fc9709a3 112 */
AnnaBridge 189:f392fc9709a3 113
AnnaBridge 189:f392fc9709a3 114 /* Includes ------------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 115 #include "stm32h7xx_hal.h"
AnnaBridge 189:f392fc9709a3 116
AnnaBridge 189:f392fc9709a3 117
AnnaBridge 189:f392fc9709a3 118 /** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge 189:f392fc9709a3 119 * @{
AnnaBridge 189:f392fc9709a3 120 */
AnnaBridge 189:f392fc9709a3 121
AnnaBridge 189:f392fc9709a3 122 #ifdef HAL_SRAM_MODULE_ENABLED
AnnaBridge 189:f392fc9709a3 123
AnnaBridge 189:f392fc9709a3 124 /** @defgroup SRAM SRAM
AnnaBridge 189:f392fc9709a3 125 * @brief SRAM driver modules
AnnaBridge 189:f392fc9709a3 126 * @{
AnnaBridge 189:f392fc9709a3 127 */
AnnaBridge 189:f392fc9709a3 128
AnnaBridge 189:f392fc9709a3 129 /**
AnnaBridge 189:f392fc9709a3 130 @cond 0
AnnaBridge 189:f392fc9709a3 131 */
AnnaBridge 189:f392fc9709a3 132 /* Private typedef -----------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 133 /* Private define ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 134 /* Private macro -------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 135 /* Private variables ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 136 /* Private function prototypes -----------------------------------------------*/
AnnaBridge 189:f392fc9709a3 137 static void SRAM_DMACplt (MDMA_HandleTypeDef *hmdma);
AnnaBridge 189:f392fc9709a3 138 static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
AnnaBridge 189:f392fc9709a3 139 static void SRAM_DMAError (MDMA_HandleTypeDef *hmdma);
AnnaBridge 189:f392fc9709a3 140 /**
AnnaBridge 189:f392fc9709a3 141 @endcond
AnnaBridge 189:f392fc9709a3 142 */
AnnaBridge 189:f392fc9709a3 143
AnnaBridge 189:f392fc9709a3 144 /* Exported functions --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 145
AnnaBridge 189:f392fc9709a3 146 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
AnnaBridge 189:f392fc9709a3 147 * @{
AnnaBridge 189:f392fc9709a3 148 */
AnnaBridge 189:f392fc9709a3 149
AnnaBridge 189:f392fc9709a3 150 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 189:f392fc9709a3 151 * @brief Initialization and Configuration functions.
AnnaBridge 189:f392fc9709a3 152 *
AnnaBridge 189:f392fc9709a3 153 @verbatim
AnnaBridge 189:f392fc9709a3 154 ==============================================================================
AnnaBridge 189:f392fc9709a3 155 ##### SRAM Initialization and de_initialization functions #####
AnnaBridge 189:f392fc9709a3 156 ==============================================================================
AnnaBridge 189:f392fc9709a3 157 [..] This section provides functions allowing to initialize/de-initialize
AnnaBridge 189:f392fc9709a3 158 the SRAM memory
AnnaBridge 189:f392fc9709a3 159
AnnaBridge 189:f392fc9709a3 160 @endverbatim
AnnaBridge 189:f392fc9709a3 161 * @{
AnnaBridge 189:f392fc9709a3 162 */
AnnaBridge 189:f392fc9709a3 163
AnnaBridge 189:f392fc9709a3 164 /**
AnnaBridge 189:f392fc9709a3 165 * @brief Performs the SRAM device initialization sequence
AnnaBridge 189:f392fc9709a3 166 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 167 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 168 * @param Timing Pointer to SRAM control timing structure
AnnaBridge 189:f392fc9709a3 169 * @param ExtTiming Pointer to SRAM extended mode timing structure
AnnaBridge 189:f392fc9709a3 170 * @retval HAL status
AnnaBridge 189:f392fc9709a3 171 */
AnnaBridge 189:f392fc9709a3 172 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
AnnaBridge 189:f392fc9709a3 173 {
AnnaBridge 189:f392fc9709a3 174 /* Check the SRAM handle parameter */
AnnaBridge 189:f392fc9709a3 175 if (hsram == NULL)
AnnaBridge 189:f392fc9709a3 176 {
AnnaBridge 189:f392fc9709a3 177 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 178 }
AnnaBridge 189:f392fc9709a3 179
AnnaBridge 189:f392fc9709a3 180 if (hsram->State == HAL_SRAM_STATE_RESET)
AnnaBridge 189:f392fc9709a3 181 {
AnnaBridge 189:f392fc9709a3 182 /* Allocate lock resource and initialize it */
AnnaBridge 189:f392fc9709a3 183 hsram->Lock = HAL_UNLOCKED;
AnnaBridge 189:f392fc9709a3 184
AnnaBridge 189:f392fc9709a3 185 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 189:f392fc9709a3 186 if(hsram->MspInitCallback == NULL)
AnnaBridge 189:f392fc9709a3 187 {
AnnaBridge 189:f392fc9709a3 188 hsram->MspInitCallback = HAL_SRAM_MspInit;
AnnaBridge 189:f392fc9709a3 189 }
AnnaBridge 189:f392fc9709a3 190 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
AnnaBridge 189:f392fc9709a3 191 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
AnnaBridge 189:f392fc9709a3 192
AnnaBridge 189:f392fc9709a3 193 /* Init the low level hardware */
AnnaBridge 189:f392fc9709a3 194 hsram->MspInitCallback(hsram);
AnnaBridge 189:f392fc9709a3 195 #else
AnnaBridge 189:f392fc9709a3 196 /* Initialize the low level hardware (MSP) */
AnnaBridge 189:f392fc9709a3 197 HAL_SRAM_MspInit(hsram);
AnnaBridge 189:f392fc9709a3 198 #endif
AnnaBridge 189:f392fc9709a3 199 }
AnnaBridge 189:f392fc9709a3 200
AnnaBridge 189:f392fc9709a3 201 /* Initialize SRAM control Interface */
AnnaBridge 189:f392fc9709a3 202 (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
AnnaBridge 189:f392fc9709a3 203
AnnaBridge 189:f392fc9709a3 204 /* Initialize SRAM timing Interface */
AnnaBridge 189:f392fc9709a3 205 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
AnnaBridge 189:f392fc9709a3 206
AnnaBridge 189:f392fc9709a3 207 /* Initialize SRAM extended mode timing Interface */
AnnaBridge 189:f392fc9709a3 208 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
AnnaBridge 189:f392fc9709a3 209
AnnaBridge 189:f392fc9709a3 210 /* Enable the NORSRAM device */
AnnaBridge 189:f392fc9709a3 211 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
AnnaBridge 189:f392fc9709a3 212
AnnaBridge 189:f392fc9709a3 213 /* Enable FMC Peripheral */
AnnaBridge 189:f392fc9709a3 214 __FMC_ENABLE();
AnnaBridge 189:f392fc9709a3 215
AnnaBridge 189:f392fc9709a3 216 /* Initialize the SRAM controller state */
AnnaBridge 189:f392fc9709a3 217 hsram->State = HAL_SRAM_STATE_READY;
AnnaBridge 189:f392fc9709a3 218
AnnaBridge 189:f392fc9709a3 219 return HAL_OK;
AnnaBridge 189:f392fc9709a3 220 }
AnnaBridge 189:f392fc9709a3 221
AnnaBridge 189:f392fc9709a3 222 /**
AnnaBridge 189:f392fc9709a3 223 * @brief Performs the SRAM device De-initialization sequence.
AnnaBridge 189:f392fc9709a3 224 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 225 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 226 * @retval HAL status
AnnaBridge 189:f392fc9709a3 227 */
AnnaBridge 189:f392fc9709a3 228 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
AnnaBridge 189:f392fc9709a3 229 {
AnnaBridge 189:f392fc9709a3 230 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 189:f392fc9709a3 231 if(hsram->MspDeInitCallback == NULL)
AnnaBridge 189:f392fc9709a3 232 {
AnnaBridge 189:f392fc9709a3 233 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
AnnaBridge 189:f392fc9709a3 234 }
AnnaBridge 189:f392fc9709a3 235
AnnaBridge 189:f392fc9709a3 236 /* DeInit the low level hardware */
AnnaBridge 189:f392fc9709a3 237 hsram->MspDeInitCallback(hsram);
AnnaBridge 189:f392fc9709a3 238 #else
AnnaBridge 189:f392fc9709a3 239 /* De-Initialize the low level hardware (MSP) */
AnnaBridge 189:f392fc9709a3 240 HAL_SRAM_MspDeInit(hsram);
AnnaBridge 189:f392fc9709a3 241 #endif
AnnaBridge 189:f392fc9709a3 242
AnnaBridge 189:f392fc9709a3 243 /* Configure the SRAM registers with their reset values */
AnnaBridge 189:f392fc9709a3 244 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
AnnaBridge 189:f392fc9709a3 245
AnnaBridge 189:f392fc9709a3 246 /* Reset the SRAM controller state */
AnnaBridge 189:f392fc9709a3 247 hsram->State = HAL_SRAM_STATE_RESET;
AnnaBridge 189:f392fc9709a3 248
AnnaBridge 189:f392fc9709a3 249 /* Release Lock */
AnnaBridge 189:f392fc9709a3 250 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 251
AnnaBridge 189:f392fc9709a3 252 return HAL_OK;
AnnaBridge 189:f392fc9709a3 253 }
AnnaBridge 189:f392fc9709a3 254
AnnaBridge 189:f392fc9709a3 255 /**
AnnaBridge 189:f392fc9709a3 256 * @brief SRAM MSP Init.
AnnaBridge 189:f392fc9709a3 257 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 258 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 259 * @retval None
AnnaBridge 189:f392fc9709a3 260 */
AnnaBridge 189:f392fc9709a3 261 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
AnnaBridge 189:f392fc9709a3 262 {
AnnaBridge 189:f392fc9709a3 263 /* Prevent unused argument(s) compilation warning */
AnnaBridge 189:f392fc9709a3 264 UNUSED(hsram);
AnnaBridge 189:f392fc9709a3 265
AnnaBridge 189:f392fc9709a3 266 /* NOTE : This function Should not be modified, when the callback is needed,
AnnaBridge 189:f392fc9709a3 267 the HAL_SRAM_MspInit could be implemented in the user file
AnnaBridge 189:f392fc9709a3 268 */
AnnaBridge 189:f392fc9709a3 269 }
AnnaBridge 189:f392fc9709a3 270
AnnaBridge 189:f392fc9709a3 271 /**
AnnaBridge 189:f392fc9709a3 272 * @brief SRAM MSP DeInit.
AnnaBridge 189:f392fc9709a3 273 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 274 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 275 * @retval None
AnnaBridge 189:f392fc9709a3 276 */
AnnaBridge 189:f392fc9709a3 277 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
AnnaBridge 189:f392fc9709a3 278 {
AnnaBridge 189:f392fc9709a3 279 /* Prevent unused argument(s) compilation warning */
AnnaBridge 189:f392fc9709a3 280 UNUSED(hsram);
AnnaBridge 189:f392fc9709a3 281
AnnaBridge 189:f392fc9709a3 282 /* NOTE : This function Should not be modified, when the callback is needed,
AnnaBridge 189:f392fc9709a3 283 the HAL_SRAM_MspDeInit could be implemented in the user file
AnnaBridge 189:f392fc9709a3 284 */
AnnaBridge 189:f392fc9709a3 285 }
AnnaBridge 189:f392fc9709a3 286
AnnaBridge 189:f392fc9709a3 287 /**
AnnaBridge 189:f392fc9709a3 288 * @brief DMA transfer complete callback.
AnnaBridge 189:f392fc9709a3 289 * @param hmdma pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 290 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 291 * @retval None
AnnaBridge 189:f392fc9709a3 292 */
AnnaBridge 189:f392fc9709a3 293 __weak void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
AnnaBridge 189:f392fc9709a3 294 {
AnnaBridge 189:f392fc9709a3 295 /* Prevent unused argument(s) compilation warning */
AnnaBridge 189:f392fc9709a3 296 UNUSED(hmdma);
AnnaBridge 189:f392fc9709a3 297
AnnaBridge 189:f392fc9709a3 298 /* NOTE : This function Should not be modified, when the callback is needed,
AnnaBridge 189:f392fc9709a3 299 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
AnnaBridge 189:f392fc9709a3 300 */
AnnaBridge 189:f392fc9709a3 301 }
AnnaBridge 189:f392fc9709a3 302
AnnaBridge 189:f392fc9709a3 303 /**
AnnaBridge 189:f392fc9709a3 304 * @brief DMA transfer complete error callback.
AnnaBridge 189:f392fc9709a3 305 * @param hmdma pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 306 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 307 * @retval None
AnnaBridge 189:f392fc9709a3 308 */
AnnaBridge 189:f392fc9709a3 309 __weak void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
AnnaBridge 189:f392fc9709a3 310 {
AnnaBridge 189:f392fc9709a3 311 /* Prevent unused argument(s) compilation warning */
AnnaBridge 189:f392fc9709a3 312 UNUSED(hmdma);
AnnaBridge 189:f392fc9709a3 313
AnnaBridge 189:f392fc9709a3 314 /* NOTE : This function Should not be modified, when the callback is needed,
AnnaBridge 189:f392fc9709a3 315 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
AnnaBridge 189:f392fc9709a3 316 */
AnnaBridge 189:f392fc9709a3 317 }
AnnaBridge 189:f392fc9709a3 318
AnnaBridge 189:f392fc9709a3 319 /**
AnnaBridge 189:f392fc9709a3 320 * @}
AnnaBridge 189:f392fc9709a3 321 */
AnnaBridge 189:f392fc9709a3 322
AnnaBridge 189:f392fc9709a3 323 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
AnnaBridge 189:f392fc9709a3 324 * @brief Input Output and memory control functions
AnnaBridge 189:f392fc9709a3 325 *
AnnaBridge 189:f392fc9709a3 326 @verbatim
AnnaBridge 189:f392fc9709a3 327 ==============================================================================
AnnaBridge 189:f392fc9709a3 328 ##### SRAM Input and Output functions #####
AnnaBridge 189:f392fc9709a3 329 ==============================================================================
AnnaBridge 189:f392fc9709a3 330 [..]
AnnaBridge 189:f392fc9709a3 331 This section provides functions allowing to use and control the SRAM memory
AnnaBridge 189:f392fc9709a3 332
AnnaBridge 189:f392fc9709a3 333 @endverbatim
AnnaBridge 189:f392fc9709a3 334 * @{
AnnaBridge 189:f392fc9709a3 335 */
AnnaBridge 189:f392fc9709a3 336
AnnaBridge 189:f392fc9709a3 337 /**
AnnaBridge 189:f392fc9709a3 338 * @brief Reads 8-bit buffer from SRAM memory.
AnnaBridge 189:f392fc9709a3 339 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 340 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 341 * @param pAddress Pointer to read start address
AnnaBridge 189:f392fc9709a3 342 * @param pDstBuffer Pointer to destination buffer
AnnaBridge 189:f392fc9709a3 343 * @param BufferSize Size of the buffer to read from memory
AnnaBridge 189:f392fc9709a3 344 * @retval HAL status
AnnaBridge 189:f392fc9709a3 345 */
AnnaBridge 189:f392fc9709a3 346 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
AnnaBridge 189:f392fc9709a3 347 {
AnnaBridge 189:f392fc9709a3 348 uint32_t size;
AnnaBridge 189:f392fc9709a3 349 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
AnnaBridge 189:f392fc9709a3 350 uint8_t * pdestbuff = pDstBuffer;
AnnaBridge 189:f392fc9709a3 351 HAL_SRAM_StateTypeDef state = hsram->State;
AnnaBridge 189:f392fc9709a3 352
AnnaBridge 189:f392fc9709a3 353 /* Check the SRAM controller state */
AnnaBridge 189:f392fc9709a3 354 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
AnnaBridge 189:f392fc9709a3 355 {
AnnaBridge 189:f392fc9709a3 356 /* Process Locked */
AnnaBridge 189:f392fc9709a3 357 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 358
AnnaBridge 189:f392fc9709a3 359 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 360 hsram->State = HAL_SRAM_STATE_BUSY;
AnnaBridge 189:f392fc9709a3 361
AnnaBridge 189:f392fc9709a3 362 /* Read data from memory */
AnnaBridge 189:f392fc9709a3 363 for (size = BufferSize; size != 0U; size--)
AnnaBridge 189:f392fc9709a3 364 {
AnnaBridge 189:f392fc9709a3 365 *pdestbuff = *psramaddress;
AnnaBridge 189:f392fc9709a3 366 pdestbuff++;
AnnaBridge 189:f392fc9709a3 367 psramaddress++;
AnnaBridge 189:f392fc9709a3 368 }
AnnaBridge 189:f392fc9709a3 369
AnnaBridge 189:f392fc9709a3 370 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 371 hsram->State = state;
AnnaBridge 189:f392fc9709a3 372
AnnaBridge 189:f392fc9709a3 373 /* Process unlocked */
AnnaBridge 189:f392fc9709a3 374 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 375 }
AnnaBridge 189:f392fc9709a3 376 else
AnnaBridge 189:f392fc9709a3 377 {
AnnaBridge 189:f392fc9709a3 378 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 379 }
AnnaBridge 189:f392fc9709a3 380
AnnaBridge 189:f392fc9709a3 381 return HAL_OK;
AnnaBridge 189:f392fc9709a3 382 }
AnnaBridge 189:f392fc9709a3 383
AnnaBridge 189:f392fc9709a3 384 /**
AnnaBridge 189:f392fc9709a3 385 * @brief Writes 8-bit buffer to SRAM memory.
AnnaBridge 189:f392fc9709a3 386 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 387 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 388 * @param pAddress Pointer to write start address
AnnaBridge 189:f392fc9709a3 389 * @param pSrcBuffer Pointer to source buffer to write
AnnaBridge 189:f392fc9709a3 390 * @param BufferSize Size of the buffer to write to memory
AnnaBridge 189:f392fc9709a3 391 * @retval HAL status
AnnaBridge 189:f392fc9709a3 392 */
AnnaBridge 189:f392fc9709a3 393 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
AnnaBridge 189:f392fc9709a3 394 {
AnnaBridge 189:f392fc9709a3 395 uint32_t size;
AnnaBridge 189:f392fc9709a3 396 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
AnnaBridge 189:f392fc9709a3 397 uint8_t * psrcbuff = pSrcBuffer;
AnnaBridge 189:f392fc9709a3 398
AnnaBridge 189:f392fc9709a3 399 /* Check the SRAM controller state */
AnnaBridge 189:f392fc9709a3 400 if (hsram->State == HAL_SRAM_STATE_READY)
AnnaBridge 189:f392fc9709a3 401 {
AnnaBridge 189:f392fc9709a3 402 /* Process Locked */
AnnaBridge 189:f392fc9709a3 403 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 404
AnnaBridge 189:f392fc9709a3 405 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 406 hsram->State = HAL_SRAM_STATE_BUSY;
AnnaBridge 189:f392fc9709a3 407
AnnaBridge 189:f392fc9709a3 408 /* Write data to memory */
AnnaBridge 189:f392fc9709a3 409 for (size = BufferSize; size != 0U; size--)
AnnaBridge 189:f392fc9709a3 410 {
AnnaBridge 189:f392fc9709a3 411 *psramaddress = *psrcbuff;
AnnaBridge 189:f392fc9709a3 412 psrcbuff++;
AnnaBridge 189:f392fc9709a3 413 psramaddress++;
AnnaBridge 189:f392fc9709a3 414 }
AnnaBridge 189:f392fc9709a3 415
AnnaBridge 189:f392fc9709a3 416 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 417 hsram->State = HAL_SRAM_STATE_READY;
AnnaBridge 189:f392fc9709a3 418
AnnaBridge 189:f392fc9709a3 419 /* Process unlocked */
AnnaBridge 189:f392fc9709a3 420 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 421 }
AnnaBridge 189:f392fc9709a3 422 else
AnnaBridge 189:f392fc9709a3 423 {
AnnaBridge 189:f392fc9709a3 424 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 425 }
AnnaBridge 189:f392fc9709a3 426
AnnaBridge 189:f392fc9709a3 427 return HAL_OK;
AnnaBridge 189:f392fc9709a3 428 }
AnnaBridge 189:f392fc9709a3 429
AnnaBridge 189:f392fc9709a3 430 /**
AnnaBridge 189:f392fc9709a3 431 * @brief Reads 16-bit buffer from SRAM memory.
AnnaBridge 189:f392fc9709a3 432 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 433 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 434 * @param pAddress Pointer to read start address
AnnaBridge 189:f392fc9709a3 435 * @param pDstBuffer Pointer to destination buffer
AnnaBridge 189:f392fc9709a3 436 * @param BufferSize Size of the buffer to read from memory
AnnaBridge 189:f392fc9709a3 437 * @retval HAL status
AnnaBridge 189:f392fc9709a3 438 */
AnnaBridge 189:f392fc9709a3 439 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
AnnaBridge 189:f392fc9709a3 440 {
AnnaBridge 189:f392fc9709a3 441 uint32_t size;
AnnaBridge 189:f392fc9709a3 442 __IO uint32_t *psramaddress = pAddress;
AnnaBridge 189:f392fc9709a3 443 uint16_t *pdestbuff = pDstBuffer;
AnnaBridge 189:f392fc9709a3 444 uint8_t limit;
AnnaBridge 189:f392fc9709a3 445 HAL_SRAM_StateTypeDef state = hsram->State;
AnnaBridge 189:f392fc9709a3 446
AnnaBridge 189:f392fc9709a3 447 /* Check the SRAM controller state */
AnnaBridge 189:f392fc9709a3 448 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
AnnaBridge 189:f392fc9709a3 449 {
AnnaBridge 189:f392fc9709a3 450 /* Process Locked */
AnnaBridge 189:f392fc9709a3 451 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 452
AnnaBridge 189:f392fc9709a3 453 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 454 hsram->State = HAL_SRAM_STATE_BUSY;
AnnaBridge 189:f392fc9709a3 455
AnnaBridge 189:f392fc9709a3 456 /* Check if the size is a 32-bits mulitple */
AnnaBridge 189:f392fc9709a3 457 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
AnnaBridge 189:f392fc9709a3 458
AnnaBridge 189:f392fc9709a3 459 /* Read data from memory */
AnnaBridge 189:f392fc9709a3 460 for (size = BufferSize; size != limit; size-=2U)
AnnaBridge 189:f392fc9709a3 461 {
AnnaBridge 189:f392fc9709a3 462 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
AnnaBridge 189:f392fc9709a3 463 pdestbuff++;
AnnaBridge 189:f392fc9709a3 464 *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
AnnaBridge 189:f392fc9709a3 465 pdestbuff++;
AnnaBridge 189:f392fc9709a3 466 psramaddress++;
AnnaBridge 189:f392fc9709a3 467 }
AnnaBridge 189:f392fc9709a3 468
AnnaBridge 189:f392fc9709a3 469 /* Read last 16-bits if size is not 32-bits multiple */
AnnaBridge 189:f392fc9709a3 470 if (limit != 0U)
AnnaBridge 189:f392fc9709a3 471 {
AnnaBridge 189:f392fc9709a3 472 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
AnnaBridge 189:f392fc9709a3 473 }
AnnaBridge 189:f392fc9709a3 474
AnnaBridge 189:f392fc9709a3 475 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 476 hsram->State = state;
AnnaBridge 189:f392fc9709a3 477
AnnaBridge 189:f392fc9709a3 478 /* Process unlocked */
AnnaBridge 189:f392fc9709a3 479 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 480 }
AnnaBridge 189:f392fc9709a3 481 else
AnnaBridge 189:f392fc9709a3 482 {
AnnaBridge 189:f392fc9709a3 483 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 484 }
AnnaBridge 189:f392fc9709a3 485
AnnaBridge 189:f392fc9709a3 486 return HAL_OK;
AnnaBridge 189:f392fc9709a3 487 }
AnnaBridge 189:f392fc9709a3 488
AnnaBridge 189:f392fc9709a3 489 /**
AnnaBridge 189:f392fc9709a3 490 * @brief Writes 16-bit buffer to SRAM memory.
AnnaBridge 189:f392fc9709a3 491 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 492 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 493 * @param pAddress Pointer to write start address
AnnaBridge 189:f392fc9709a3 494 * @param pSrcBuffer Pointer to source buffer to write
AnnaBridge 189:f392fc9709a3 495 * @param BufferSize Size of the buffer to write to memory
AnnaBridge 189:f392fc9709a3 496 * @retval HAL status
AnnaBridge 189:f392fc9709a3 497 */
AnnaBridge 189:f392fc9709a3 498 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
AnnaBridge 189:f392fc9709a3 499 {
AnnaBridge 189:f392fc9709a3 500 uint32_t size;
AnnaBridge 189:f392fc9709a3 501 __IO uint32_t *psramaddress = pAddress;
AnnaBridge 189:f392fc9709a3 502 uint16_t * psrcbuff = pSrcBuffer;
AnnaBridge 189:f392fc9709a3 503 uint8_t limit;
AnnaBridge 189:f392fc9709a3 504
AnnaBridge 189:f392fc9709a3 505 /* Check the SRAM controller state */
AnnaBridge 189:f392fc9709a3 506 if (hsram->State == HAL_SRAM_STATE_READY)
AnnaBridge 189:f392fc9709a3 507 {
AnnaBridge 189:f392fc9709a3 508 /* Process Locked */
AnnaBridge 189:f392fc9709a3 509 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 510
AnnaBridge 189:f392fc9709a3 511 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 512 hsram->State = HAL_SRAM_STATE_BUSY;
AnnaBridge 189:f392fc9709a3 513
AnnaBridge 189:f392fc9709a3 514 /* Check if the size is a 32-bits mulitple */
AnnaBridge 189:f392fc9709a3 515 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
AnnaBridge 189:f392fc9709a3 516
AnnaBridge 189:f392fc9709a3 517 /* Write data to memory */
AnnaBridge 189:f392fc9709a3 518 for (size = BufferSize; size != limit; size-=2U)
AnnaBridge 189:f392fc9709a3 519 {
AnnaBridge 189:f392fc9709a3 520 *psramaddress = (uint32_t)(*psrcbuff);
AnnaBridge 189:f392fc9709a3 521 psrcbuff++;
AnnaBridge 189:f392fc9709a3 522 *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
AnnaBridge 189:f392fc9709a3 523 psrcbuff++;
AnnaBridge 189:f392fc9709a3 524 psramaddress++;
AnnaBridge 189:f392fc9709a3 525 }
AnnaBridge 189:f392fc9709a3 526
AnnaBridge 189:f392fc9709a3 527 /* Write last 16-bits if size is not 32-bits multiple */
AnnaBridge 189:f392fc9709a3 528 if (limit != 0U)
AnnaBridge 189:f392fc9709a3 529 {
AnnaBridge 189:f392fc9709a3 530 *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
AnnaBridge 189:f392fc9709a3 531 }
AnnaBridge 189:f392fc9709a3 532
AnnaBridge 189:f392fc9709a3 533 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 534 hsram->State = HAL_SRAM_STATE_READY;
AnnaBridge 189:f392fc9709a3 535
AnnaBridge 189:f392fc9709a3 536 /* Process unlocked */
AnnaBridge 189:f392fc9709a3 537 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 538 }
AnnaBridge 189:f392fc9709a3 539 else
AnnaBridge 189:f392fc9709a3 540 {
AnnaBridge 189:f392fc9709a3 541 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 542 }
AnnaBridge 189:f392fc9709a3 543
AnnaBridge 189:f392fc9709a3 544 return HAL_OK;
AnnaBridge 189:f392fc9709a3 545 }
AnnaBridge 189:f392fc9709a3 546
AnnaBridge 189:f392fc9709a3 547 /**
AnnaBridge 189:f392fc9709a3 548 * @brief Reads 32-bit buffer from SRAM memory.
AnnaBridge 189:f392fc9709a3 549 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 550 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 551 * @param pAddress Pointer to read start address
AnnaBridge 189:f392fc9709a3 552 * @param pDstBuffer Pointer to destination buffer
AnnaBridge 189:f392fc9709a3 553 * @param BufferSize Size of the buffer to read from memory
AnnaBridge 189:f392fc9709a3 554 * @retval HAL status
AnnaBridge 189:f392fc9709a3 555 */
AnnaBridge 189:f392fc9709a3 556 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
AnnaBridge 189:f392fc9709a3 557 {
AnnaBridge 189:f392fc9709a3 558 uint32_t size;
AnnaBridge 189:f392fc9709a3 559 __IO uint32_t * psramaddress = pAddress;
AnnaBridge 189:f392fc9709a3 560 uint32_t * pdestbuff = pDstBuffer;
AnnaBridge 189:f392fc9709a3 561 HAL_SRAM_StateTypeDef state = hsram->State;
AnnaBridge 189:f392fc9709a3 562
AnnaBridge 189:f392fc9709a3 563 /* Check the SRAM controller state */
AnnaBridge 189:f392fc9709a3 564 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
AnnaBridge 189:f392fc9709a3 565 {
AnnaBridge 189:f392fc9709a3 566 /* Process Locked */
AnnaBridge 189:f392fc9709a3 567 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 568
AnnaBridge 189:f392fc9709a3 569 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 570 hsram->State = HAL_SRAM_STATE_BUSY;
AnnaBridge 189:f392fc9709a3 571
AnnaBridge 189:f392fc9709a3 572 /* Read data from memory */
AnnaBridge 189:f392fc9709a3 573 for (size = BufferSize; size != 0U; size--)
AnnaBridge 189:f392fc9709a3 574 {
AnnaBridge 189:f392fc9709a3 575 *pdestbuff = *psramaddress;
AnnaBridge 189:f392fc9709a3 576 pdestbuff++;
AnnaBridge 189:f392fc9709a3 577 psramaddress++;
AnnaBridge 189:f392fc9709a3 578 }
AnnaBridge 189:f392fc9709a3 579
AnnaBridge 189:f392fc9709a3 580 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 581 hsram->State = state;
AnnaBridge 189:f392fc9709a3 582
AnnaBridge 189:f392fc9709a3 583 /* Process unlocked */
AnnaBridge 189:f392fc9709a3 584 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 585 }
AnnaBridge 189:f392fc9709a3 586 else
AnnaBridge 189:f392fc9709a3 587 {
AnnaBridge 189:f392fc9709a3 588 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 589 }
AnnaBridge 189:f392fc9709a3 590
AnnaBridge 189:f392fc9709a3 591 return HAL_OK;
AnnaBridge 189:f392fc9709a3 592 }
AnnaBridge 189:f392fc9709a3 593
AnnaBridge 189:f392fc9709a3 594 /**
AnnaBridge 189:f392fc9709a3 595 * @brief Writes 32-bit buffer to SRAM memory.
AnnaBridge 189:f392fc9709a3 596 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 597 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 598 * @param pAddress Pointer to write start address
AnnaBridge 189:f392fc9709a3 599 * @param pSrcBuffer Pointer to source buffer to write
AnnaBridge 189:f392fc9709a3 600 * @param BufferSize Size of the buffer to write to memory
AnnaBridge 189:f392fc9709a3 601 * @retval HAL status
AnnaBridge 189:f392fc9709a3 602 */
AnnaBridge 189:f392fc9709a3 603 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
AnnaBridge 189:f392fc9709a3 604 {
AnnaBridge 189:f392fc9709a3 605 uint32_t size;
AnnaBridge 189:f392fc9709a3 606 __IO uint32_t * psramaddress = pAddress;
AnnaBridge 189:f392fc9709a3 607 uint32_t * psrcbuff = pSrcBuffer;
AnnaBridge 189:f392fc9709a3 608
AnnaBridge 189:f392fc9709a3 609 /* Check the SRAM controller state */
AnnaBridge 189:f392fc9709a3 610 if (hsram->State == HAL_SRAM_STATE_READY)
AnnaBridge 189:f392fc9709a3 611 {
AnnaBridge 189:f392fc9709a3 612 /* Process Locked */
AnnaBridge 189:f392fc9709a3 613 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 614
AnnaBridge 189:f392fc9709a3 615 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 616 hsram->State = HAL_SRAM_STATE_BUSY;
AnnaBridge 189:f392fc9709a3 617
AnnaBridge 189:f392fc9709a3 618 /* Write data to memory */
AnnaBridge 189:f392fc9709a3 619 for (size = BufferSize; size != 0U; size--)
AnnaBridge 189:f392fc9709a3 620 {
AnnaBridge 189:f392fc9709a3 621 *psramaddress = *psrcbuff;
AnnaBridge 189:f392fc9709a3 622 psrcbuff++;
AnnaBridge 189:f392fc9709a3 623 psramaddress++;
AnnaBridge 189:f392fc9709a3 624 }
AnnaBridge 189:f392fc9709a3 625
AnnaBridge 189:f392fc9709a3 626 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 627 hsram->State = HAL_SRAM_STATE_READY;
AnnaBridge 189:f392fc9709a3 628
AnnaBridge 189:f392fc9709a3 629 /* Process unlocked */
AnnaBridge 189:f392fc9709a3 630 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 631 }
AnnaBridge 189:f392fc9709a3 632 else
AnnaBridge 189:f392fc9709a3 633 {
AnnaBridge 189:f392fc9709a3 634 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 635 }
AnnaBridge 189:f392fc9709a3 636
AnnaBridge 189:f392fc9709a3 637 return HAL_OK;
AnnaBridge 189:f392fc9709a3 638 }
AnnaBridge 189:f392fc9709a3 639
AnnaBridge 189:f392fc9709a3 640 /**
AnnaBridge 189:f392fc9709a3 641 * @brief Reads a Words data from the SRAM memory using DMA transfer.
AnnaBridge 189:f392fc9709a3 642 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 643 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 644 * @param pAddress Pointer to read start address
AnnaBridge 189:f392fc9709a3 645 * @param pDstBuffer Pointer to destination buffer
AnnaBridge 189:f392fc9709a3 646 * @param BufferSize Size of the buffer to read from memory
AnnaBridge 189:f392fc9709a3 647 * @retval HAL status
AnnaBridge 189:f392fc9709a3 648 */
AnnaBridge 189:f392fc9709a3 649 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
AnnaBridge 189:f392fc9709a3 650 {
AnnaBridge 189:f392fc9709a3 651 HAL_StatusTypeDef status;
AnnaBridge 189:f392fc9709a3 652 HAL_SRAM_StateTypeDef state = hsram->State;
AnnaBridge 189:f392fc9709a3 653
AnnaBridge 189:f392fc9709a3 654 /* Check the SRAM controller state */
AnnaBridge 189:f392fc9709a3 655 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
AnnaBridge 189:f392fc9709a3 656 {
AnnaBridge 189:f392fc9709a3 657 /* Process Locked */
AnnaBridge 189:f392fc9709a3 658 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 659
AnnaBridge 189:f392fc9709a3 660 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 661 hsram->State = HAL_SRAM_STATE_BUSY;
AnnaBridge 189:f392fc9709a3 662
AnnaBridge 189:f392fc9709a3 663 /* Configure DMA user callbacks */
AnnaBridge 189:f392fc9709a3 664 if (state == HAL_SRAM_STATE_READY)
AnnaBridge 189:f392fc9709a3 665 {
AnnaBridge 189:f392fc9709a3 666 hsram->hmdma->XferCpltCallback = SRAM_DMACplt;
AnnaBridge 189:f392fc9709a3 667 }
AnnaBridge 189:f392fc9709a3 668 else
AnnaBridge 189:f392fc9709a3 669 {
AnnaBridge 189:f392fc9709a3 670 hsram->hmdma->XferCpltCallback = SRAM_DMACpltProt;
AnnaBridge 189:f392fc9709a3 671 }
AnnaBridge 189:f392fc9709a3 672 hsram->hmdma->XferErrorCallback = SRAM_DMAError;
AnnaBridge 189:f392fc9709a3 673
AnnaBridge 189:f392fc9709a3 674 /* Enable the DMA Stream */
AnnaBridge 189:f392fc9709a3 675 status = HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1);
AnnaBridge 189:f392fc9709a3 676
AnnaBridge 189:f392fc9709a3 677 /* Process unlocked */
AnnaBridge 189:f392fc9709a3 678 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 679 }
AnnaBridge 189:f392fc9709a3 680 else
AnnaBridge 189:f392fc9709a3 681 {
AnnaBridge 189:f392fc9709a3 682 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 683 }
AnnaBridge 189:f392fc9709a3 684
AnnaBridge 189:f392fc9709a3 685 return status;
AnnaBridge 189:f392fc9709a3 686 }
AnnaBridge 189:f392fc9709a3 687
AnnaBridge 189:f392fc9709a3 688 /**
AnnaBridge 189:f392fc9709a3 689 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
AnnaBridge 189:f392fc9709a3 690 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 691 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 692 * @param pAddress Pointer to write start address
AnnaBridge 189:f392fc9709a3 693 * @param pSrcBuffer Pointer to source buffer to write
AnnaBridge 189:f392fc9709a3 694 * @param BufferSize Size of the buffer to write to memory
AnnaBridge 189:f392fc9709a3 695 * @retval HAL status
AnnaBridge 189:f392fc9709a3 696 */
AnnaBridge 189:f392fc9709a3 697 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
AnnaBridge 189:f392fc9709a3 698 {
AnnaBridge 189:f392fc9709a3 699 HAL_StatusTypeDef status;
AnnaBridge 189:f392fc9709a3 700
AnnaBridge 189:f392fc9709a3 701 /* Check the SRAM controller state */
AnnaBridge 189:f392fc9709a3 702 if (hsram->State == HAL_SRAM_STATE_READY)
AnnaBridge 189:f392fc9709a3 703 {
AnnaBridge 189:f392fc9709a3 704 /* Process Locked */
AnnaBridge 189:f392fc9709a3 705 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 706
AnnaBridge 189:f392fc9709a3 707 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 708 hsram->State = HAL_SRAM_STATE_BUSY;
AnnaBridge 189:f392fc9709a3 709
AnnaBridge 189:f392fc9709a3 710 /* Configure DMA user callbacks */
AnnaBridge 189:f392fc9709a3 711 hsram->hmdma->XferCpltCallback = SRAM_DMACplt;
AnnaBridge 189:f392fc9709a3 712 hsram->hmdma->XferErrorCallback = SRAM_DMAError;
AnnaBridge 189:f392fc9709a3 713
AnnaBridge 189:f392fc9709a3 714 /* Enable the DMA Stream */
AnnaBridge 189:f392fc9709a3 715 status = HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1);
AnnaBridge 189:f392fc9709a3 716
AnnaBridge 189:f392fc9709a3 717 /* Process unlocked */
AnnaBridge 189:f392fc9709a3 718 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 719 }
AnnaBridge 189:f392fc9709a3 720 else
AnnaBridge 189:f392fc9709a3 721 {
AnnaBridge 189:f392fc9709a3 722 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 723 }
AnnaBridge 189:f392fc9709a3 724
AnnaBridge 189:f392fc9709a3 725 return status;
AnnaBridge 189:f392fc9709a3 726 }
AnnaBridge 189:f392fc9709a3 727
AnnaBridge 189:f392fc9709a3 728 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 189:f392fc9709a3 729 /**
AnnaBridge 189:f392fc9709a3 730 * @brief Register a User SRAM Callback
AnnaBridge 189:f392fc9709a3 731 * To be used instead of the weak (surcharged) predefined callback
AnnaBridge 189:f392fc9709a3 732 * @param hsram : SRAM handle
AnnaBridge 189:f392fc9709a3 733 * @param CallbackId : ID of the callback to be registered
AnnaBridge 189:f392fc9709a3 734 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 735 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
AnnaBridge 189:f392fc9709a3 736 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
AnnaBridge 189:f392fc9709a3 737 * @param pCallback : pointer to the Callback function
AnnaBridge 189:f392fc9709a3 738 * @retval status
AnnaBridge 189:f392fc9709a3 739 */
AnnaBridge 189:f392fc9709a3 740 HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
AnnaBridge 189:f392fc9709a3 741 {
AnnaBridge 189:f392fc9709a3 742 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 189:f392fc9709a3 743 HAL_SRAM_StateTypeDef state;
AnnaBridge 189:f392fc9709a3 744
AnnaBridge 189:f392fc9709a3 745 if(pCallback == NULL)
AnnaBridge 189:f392fc9709a3 746 {
AnnaBridge 189:f392fc9709a3 747 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 748 }
AnnaBridge 189:f392fc9709a3 749
AnnaBridge 189:f392fc9709a3 750 /* Process locked */
AnnaBridge 189:f392fc9709a3 751 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 752
AnnaBridge 189:f392fc9709a3 753 state = hsram->State;
AnnaBridge 189:f392fc9709a3 754 if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
AnnaBridge 189:f392fc9709a3 755 {
AnnaBridge 189:f392fc9709a3 756 switch (CallbackId)
AnnaBridge 189:f392fc9709a3 757 {
AnnaBridge 189:f392fc9709a3 758 case HAL_SRAM_MSP_INIT_CB_ID :
AnnaBridge 189:f392fc9709a3 759 hsram->MspInitCallback = pCallback;
AnnaBridge 189:f392fc9709a3 760 break;
AnnaBridge 189:f392fc9709a3 761 case HAL_SRAM_MSP_DEINIT_CB_ID :
AnnaBridge 189:f392fc9709a3 762 hsram->MspDeInitCallback = pCallback;
AnnaBridge 189:f392fc9709a3 763 break;
AnnaBridge 189:f392fc9709a3 764 default :
AnnaBridge 189:f392fc9709a3 765 /* update return status */
AnnaBridge 189:f392fc9709a3 766 status = HAL_ERROR;
AnnaBridge 189:f392fc9709a3 767 break;
AnnaBridge 189:f392fc9709a3 768 }
AnnaBridge 189:f392fc9709a3 769 }
AnnaBridge 189:f392fc9709a3 770 else
AnnaBridge 189:f392fc9709a3 771 {
AnnaBridge 189:f392fc9709a3 772 /* update return status */
AnnaBridge 189:f392fc9709a3 773 status = HAL_ERROR;
AnnaBridge 189:f392fc9709a3 774 }
AnnaBridge 189:f392fc9709a3 775
AnnaBridge 189:f392fc9709a3 776 /* Release Lock */
AnnaBridge 189:f392fc9709a3 777 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 778 return status;
AnnaBridge 189:f392fc9709a3 779 }
AnnaBridge 189:f392fc9709a3 780
AnnaBridge 189:f392fc9709a3 781 /**
AnnaBridge 189:f392fc9709a3 782 * @brief Unregister a User SRAM Callback
AnnaBridge 189:f392fc9709a3 783 * SRAM Callback is redirected to the weak (surcharged) predefined callback
AnnaBridge 189:f392fc9709a3 784 * @param hsram : SRAM handle
AnnaBridge 189:f392fc9709a3 785 * @param CallbackId : ID of the callback to be unregistered
AnnaBridge 189:f392fc9709a3 786 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 787 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
AnnaBridge 189:f392fc9709a3 788 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
AnnaBridge 189:f392fc9709a3 789 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
AnnaBridge 189:f392fc9709a3 790 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
AnnaBridge 189:f392fc9709a3 791 * @retval status
AnnaBridge 189:f392fc9709a3 792 */
AnnaBridge 189:f392fc9709a3 793 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
AnnaBridge 189:f392fc9709a3 794 {
AnnaBridge 189:f392fc9709a3 795 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 189:f392fc9709a3 796 HAL_SRAM_StateTypeDef state;
AnnaBridge 189:f392fc9709a3 797
AnnaBridge 189:f392fc9709a3 798 /* Process locked */
AnnaBridge 189:f392fc9709a3 799 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 800
AnnaBridge 189:f392fc9709a3 801 state = hsram->State;
AnnaBridge 189:f392fc9709a3 802 if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
AnnaBridge 189:f392fc9709a3 803 {
AnnaBridge 189:f392fc9709a3 804 switch (CallbackId)
AnnaBridge 189:f392fc9709a3 805 {
AnnaBridge 189:f392fc9709a3 806 case HAL_SRAM_MSP_INIT_CB_ID :
AnnaBridge 189:f392fc9709a3 807 hsram->MspInitCallback = HAL_SRAM_MspInit;
AnnaBridge 189:f392fc9709a3 808 break;
AnnaBridge 189:f392fc9709a3 809 case HAL_SRAM_MSP_DEINIT_CB_ID :
AnnaBridge 189:f392fc9709a3 810 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
AnnaBridge 189:f392fc9709a3 811 break;
AnnaBridge 189:f392fc9709a3 812 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
AnnaBridge 189:f392fc9709a3 813 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
AnnaBridge 189:f392fc9709a3 814 break;
AnnaBridge 189:f392fc9709a3 815 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
AnnaBridge 189:f392fc9709a3 816 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
AnnaBridge 189:f392fc9709a3 817 break;
AnnaBridge 189:f392fc9709a3 818 default :
AnnaBridge 189:f392fc9709a3 819 /* update return status */
AnnaBridge 189:f392fc9709a3 820 status = HAL_ERROR;
AnnaBridge 189:f392fc9709a3 821 break;
AnnaBridge 189:f392fc9709a3 822 }
AnnaBridge 189:f392fc9709a3 823 }
AnnaBridge 189:f392fc9709a3 824 else if(state == HAL_SRAM_STATE_RESET)
AnnaBridge 189:f392fc9709a3 825 {
AnnaBridge 189:f392fc9709a3 826 switch (CallbackId)
AnnaBridge 189:f392fc9709a3 827 {
AnnaBridge 189:f392fc9709a3 828 case HAL_SRAM_MSP_INIT_CB_ID :
AnnaBridge 189:f392fc9709a3 829 hsram->MspInitCallback = HAL_SRAM_MspInit;
AnnaBridge 189:f392fc9709a3 830 break;
AnnaBridge 189:f392fc9709a3 831 case HAL_SRAM_MSP_DEINIT_CB_ID :
AnnaBridge 189:f392fc9709a3 832 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
AnnaBridge 189:f392fc9709a3 833 break;
AnnaBridge 189:f392fc9709a3 834 default :
AnnaBridge 189:f392fc9709a3 835 /* update return status */
AnnaBridge 189:f392fc9709a3 836 status = HAL_ERROR;
AnnaBridge 189:f392fc9709a3 837 break;
AnnaBridge 189:f392fc9709a3 838 }
AnnaBridge 189:f392fc9709a3 839 }
AnnaBridge 189:f392fc9709a3 840 else
AnnaBridge 189:f392fc9709a3 841 {
AnnaBridge 189:f392fc9709a3 842 /* update return status */
AnnaBridge 189:f392fc9709a3 843 status = HAL_ERROR;
AnnaBridge 189:f392fc9709a3 844 }
AnnaBridge 189:f392fc9709a3 845
AnnaBridge 189:f392fc9709a3 846 /* Release Lock */
AnnaBridge 189:f392fc9709a3 847 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 848 return status;
AnnaBridge 189:f392fc9709a3 849 }
AnnaBridge 189:f392fc9709a3 850
AnnaBridge 189:f392fc9709a3 851 /**
AnnaBridge 189:f392fc9709a3 852 * @brief Register a User SRAM Callback for DMA transfers
AnnaBridge 189:f392fc9709a3 853 * To be used instead of the weak (surcharged) predefined callback
AnnaBridge 189:f392fc9709a3 854 * @param hsram : SRAM handle
AnnaBridge 189:f392fc9709a3 855 * @param CallbackId : ID of the callback to be registered
AnnaBridge 189:f392fc9709a3 856 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 857 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
AnnaBridge 189:f392fc9709a3 858 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
AnnaBridge 189:f392fc9709a3 859 * @param pCallback : pointer to the Callback function
AnnaBridge 189:f392fc9709a3 860 * @retval status
AnnaBridge 189:f392fc9709a3 861 */
AnnaBridge 189:f392fc9709a3 862 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
AnnaBridge 189:f392fc9709a3 863 {
AnnaBridge 189:f392fc9709a3 864 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 189:f392fc9709a3 865 HAL_SRAM_StateTypeDef state;
AnnaBridge 189:f392fc9709a3 866
AnnaBridge 189:f392fc9709a3 867 if(pCallback == NULL)
AnnaBridge 189:f392fc9709a3 868 {
AnnaBridge 189:f392fc9709a3 869 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 870 }
AnnaBridge 189:f392fc9709a3 871
AnnaBridge 189:f392fc9709a3 872 /* Process locked */
AnnaBridge 189:f392fc9709a3 873 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 874
AnnaBridge 189:f392fc9709a3 875 state = hsram->State;
AnnaBridge 189:f392fc9709a3 876 if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
AnnaBridge 189:f392fc9709a3 877 {
AnnaBridge 189:f392fc9709a3 878 switch (CallbackId)
AnnaBridge 189:f392fc9709a3 879 {
AnnaBridge 189:f392fc9709a3 880 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
AnnaBridge 189:f392fc9709a3 881 hsram->DmaXferCpltCallback = pCallback;
AnnaBridge 189:f392fc9709a3 882 break;
AnnaBridge 189:f392fc9709a3 883 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
AnnaBridge 189:f392fc9709a3 884 hsram->DmaXferErrorCallback = pCallback;
AnnaBridge 189:f392fc9709a3 885 break;
AnnaBridge 189:f392fc9709a3 886 default :
AnnaBridge 189:f392fc9709a3 887 /* update return status */
AnnaBridge 189:f392fc9709a3 888 status = HAL_ERROR;
AnnaBridge 189:f392fc9709a3 889 break;
AnnaBridge 189:f392fc9709a3 890 }
AnnaBridge 189:f392fc9709a3 891 }
AnnaBridge 189:f392fc9709a3 892 else
AnnaBridge 189:f392fc9709a3 893 {
AnnaBridge 189:f392fc9709a3 894 /* update return status */
AnnaBridge 189:f392fc9709a3 895 status = HAL_ERROR;
AnnaBridge 189:f392fc9709a3 896 }
AnnaBridge 189:f392fc9709a3 897
AnnaBridge 189:f392fc9709a3 898 /* Release Lock */
AnnaBridge 189:f392fc9709a3 899 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 900 return status;
AnnaBridge 189:f392fc9709a3 901 }
AnnaBridge 189:f392fc9709a3 902 #endif
AnnaBridge 189:f392fc9709a3 903
AnnaBridge 189:f392fc9709a3 904 /**
AnnaBridge 189:f392fc9709a3 905 * @}
AnnaBridge 189:f392fc9709a3 906 */
AnnaBridge 189:f392fc9709a3 907
AnnaBridge 189:f392fc9709a3 908 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
AnnaBridge 189:f392fc9709a3 909 * @brief Control functions
AnnaBridge 189:f392fc9709a3 910 *
AnnaBridge 189:f392fc9709a3 911 @verbatim
AnnaBridge 189:f392fc9709a3 912 ==============================================================================
AnnaBridge 189:f392fc9709a3 913 ##### SRAM Control functions #####
AnnaBridge 189:f392fc9709a3 914 ==============================================================================
AnnaBridge 189:f392fc9709a3 915 [..]
AnnaBridge 189:f392fc9709a3 916 This subsection provides a set of functions allowing to control dynamically
AnnaBridge 189:f392fc9709a3 917 the SRAM interface.
AnnaBridge 189:f392fc9709a3 918
AnnaBridge 189:f392fc9709a3 919 @endverbatim
AnnaBridge 189:f392fc9709a3 920 * @{
AnnaBridge 189:f392fc9709a3 921 */
AnnaBridge 189:f392fc9709a3 922
AnnaBridge 189:f392fc9709a3 923 /**
AnnaBridge 189:f392fc9709a3 924 * @brief Enables dynamically SRAM write operation.
AnnaBridge 189:f392fc9709a3 925 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 926 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 927 * @retval HAL status
AnnaBridge 189:f392fc9709a3 928 */
AnnaBridge 189:f392fc9709a3 929 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
AnnaBridge 189:f392fc9709a3 930 {
AnnaBridge 189:f392fc9709a3 931 /* Check the SRAM controller state */
AnnaBridge 189:f392fc9709a3 932 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
AnnaBridge 189:f392fc9709a3 933 {
AnnaBridge 189:f392fc9709a3 934 /* Process Locked */
AnnaBridge 189:f392fc9709a3 935 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 936
AnnaBridge 189:f392fc9709a3 937 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 938 hsram->State = HAL_SRAM_STATE_BUSY;
AnnaBridge 189:f392fc9709a3 939
AnnaBridge 189:f392fc9709a3 940 /* Enable write operation */
AnnaBridge 189:f392fc9709a3 941 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
AnnaBridge 189:f392fc9709a3 942
AnnaBridge 189:f392fc9709a3 943 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 944 hsram->State = HAL_SRAM_STATE_READY;
AnnaBridge 189:f392fc9709a3 945
AnnaBridge 189:f392fc9709a3 946 /* Process unlocked */
AnnaBridge 189:f392fc9709a3 947 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 948 }
AnnaBridge 189:f392fc9709a3 949 else
AnnaBridge 189:f392fc9709a3 950 {
AnnaBridge 189:f392fc9709a3 951 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 952 }
AnnaBridge 189:f392fc9709a3 953
AnnaBridge 189:f392fc9709a3 954 return HAL_OK;
AnnaBridge 189:f392fc9709a3 955 }
AnnaBridge 189:f392fc9709a3 956
AnnaBridge 189:f392fc9709a3 957 /**
AnnaBridge 189:f392fc9709a3 958 * @brief Disables dynamically SRAM write operation.
AnnaBridge 189:f392fc9709a3 959 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 960 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 961 * @retval HAL status
AnnaBridge 189:f392fc9709a3 962 */
AnnaBridge 189:f392fc9709a3 963 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
AnnaBridge 189:f392fc9709a3 964 {
AnnaBridge 189:f392fc9709a3 965 /* Check the SRAM controller state */
AnnaBridge 189:f392fc9709a3 966 if(hsram->State == HAL_SRAM_STATE_READY)
AnnaBridge 189:f392fc9709a3 967 {
AnnaBridge 189:f392fc9709a3 968 /* Process Locked */
AnnaBridge 189:f392fc9709a3 969 __HAL_LOCK(hsram);
AnnaBridge 189:f392fc9709a3 970
AnnaBridge 189:f392fc9709a3 971 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 972 hsram->State = HAL_SRAM_STATE_BUSY;
AnnaBridge 189:f392fc9709a3 973
AnnaBridge 189:f392fc9709a3 974 /* Disable write operation */
AnnaBridge 189:f392fc9709a3 975 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
AnnaBridge 189:f392fc9709a3 976
AnnaBridge 189:f392fc9709a3 977 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 978 hsram->State = HAL_SRAM_STATE_PROTECTED;
AnnaBridge 189:f392fc9709a3 979
AnnaBridge 189:f392fc9709a3 980 /* Process unlocked */
AnnaBridge 189:f392fc9709a3 981 __HAL_UNLOCK(hsram);
AnnaBridge 189:f392fc9709a3 982 }
AnnaBridge 189:f392fc9709a3 983 else
AnnaBridge 189:f392fc9709a3 984 {
AnnaBridge 189:f392fc9709a3 985 return HAL_ERROR;
AnnaBridge 189:f392fc9709a3 986 }
AnnaBridge 189:f392fc9709a3 987
AnnaBridge 189:f392fc9709a3 988 return HAL_OK;
AnnaBridge 189:f392fc9709a3 989 }
AnnaBridge 189:f392fc9709a3 990
AnnaBridge 189:f392fc9709a3 991 /**
AnnaBridge 189:f392fc9709a3 992 * @}
AnnaBridge 189:f392fc9709a3 993 */
AnnaBridge 189:f392fc9709a3 994
AnnaBridge 189:f392fc9709a3 995 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
AnnaBridge 189:f392fc9709a3 996 * @brief Peripheral State functions
AnnaBridge 189:f392fc9709a3 997 *
AnnaBridge 189:f392fc9709a3 998 @verbatim
AnnaBridge 189:f392fc9709a3 999 ==============================================================================
AnnaBridge 189:f392fc9709a3 1000 ##### SRAM State functions #####
AnnaBridge 189:f392fc9709a3 1001 ==============================================================================
AnnaBridge 189:f392fc9709a3 1002 [..]
AnnaBridge 189:f392fc9709a3 1003 This subsection permits to get in run-time the status of the SRAM controller
AnnaBridge 189:f392fc9709a3 1004 and the data flow.
AnnaBridge 189:f392fc9709a3 1005
AnnaBridge 189:f392fc9709a3 1006 @endverbatim
AnnaBridge 189:f392fc9709a3 1007 * @{
AnnaBridge 189:f392fc9709a3 1008 */
AnnaBridge 189:f392fc9709a3 1009
AnnaBridge 189:f392fc9709a3 1010 /**
AnnaBridge 189:f392fc9709a3 1011 * @brief Returns the SRAM controller state
AnnaBridge 189:f392fc9709a3 1012 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
AnnaBridge 189:f392fc9709a3 1013 * the configuration information for SRAM module.
AnnaBridge 189:f392fc9709a3 1014 * @retval HAL state
AnnaBridge 189:f392fc9709a3 1015 */
AnnaBridge 189:f392fc9709a3 1016 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
AnnaBridge 189:f392fc9709a3 1017 {
AnnaBridge 189:f392fc9709a3 1018 return hsram->State;
AnnaBridge 189:f392fc9709a3 1019 }
AnnaBridge 189:f392fc9709a3 1020
AnnaBridge 189:f392fc9709a3 1021 /**
AnnaBridge 189:f392fc9709a3 1022 * @}
AnnaBridge 189:f392fc9709a3 1023 */
AnnaBridge 189:f392fc9709a3 1024
AnnaBridge 189:f392fc9709a3 1025 /**
AnnaBridge 189:f392fc9709a3 1026 * @}
AnnaBridge 189:f392fc9709a3 1027 */
AnnaBridge 189:f392fc9709a3 1028
AnnaBridge 189:f392fc9709a3 1029 /**
AnnaBridge 189:f392fc9709a3 1030 @cond 0
AnnaBridge 189:f392fc9709a3 1031 */
AnnaBridge 189:f392fc9709a3 1032 /**
AnnaBridge 189:f392fc9709a3 1033 * @brief MDMA SRAM process complete callback.
AnnaBridge 189:f392fc9709a3 1034 * @param hmdma : MDMA handle
AnnaBridge 189:f392fc9709a3 1035 * @retval None
AnnaBridge 189:f392fc9709a3 1036 */
AnnaBridge 189:f392fc9709a3 1037 static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma)
AnnaBridge 189:f392fc9709a3 1038 {
AnnaBridge 189:f392fc9709a3 1039 SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
AnnaBridge 189:f392fc9709a3 1040
AnnaBridge 189:f392fc9709a3 1041 /* Disable the MDMA channel */
AnnaBridge 189:f392fc9709a3 1042 __HAL_MDMA_DISABLE(hmdma);
AnnaBridge 189:f392fc9709a3 1043
AnnaBridge 189:f392fc9709a3 1044 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 1045 hsram->State = HAL_SRAM_STATE_READY;
AnnaBridge 189:f392fc9709a3 1046
AnnaBridge 189:f392fc9709a3 1047 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 189:f392fc9709a3 1048 hsram->DmaXferCpltCallback(hmdma);
AnnaBridge 189:f392fc9709a3 1049 #else
AnnaBridge 189:f392fc9709a3 1050 HAL_SRAM_DMA_XferCpltCallback(hmdma);
AnnaBridge 189:f392fc9709a3 1051 #endif
AnnaBridge 189:f392fc9709a3 1052 }
AnnaBridge 189:f392fc9709a3 1053
AnnaBridge 189:f392fc9709a3 1054 /**
AnnaBridge 189:f392fc9709a3 1055 * @brief MDMA SRAM process complete callback.
AnnaBridge 189:f392fc9709a3 1056 * @param hmdma : MDMA handle
AnnaBridge 189:f392fc9709a3 1057 * @retval None
AnnaBridge 189:f392fc9709a3 1058 */
AnnaBridge 189:f392fc9709a3 1059 static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma)
AnnaBridge 189:f392fc9709a3 1060 {
AnnaBridge 189:f392fc9709a3 1061 SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
AnnaBridge 189:f392fc9709a3 1062
AnnaBridge 189:f392fc9709a3 1063 /* Disable the MDMA channel */
AnnaBridge 189:f392fc9709a3 1064 __HAL_MDMA_DISABLE(hmdma);
AnnaBridge 189:f392fc9709a3 1065
AnnaBridge 189:f392fc9709a3 1066 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 1067 hsram->State = HAL_SRAM_STATE_PROTECTED;
AnnaBridge 189:f392fc9709a3 1068
AnnaBridge 189:f392fc9709a3 1069 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 189:f392fc9709a3 1070 hsram->DmaXferCpltCallback(hmdma);
AnnaBridge 189:f392fc9709a3 1071 #else
AnnaBridge 189:f392fc9709a3 1072 HAL_SRAM_DMA_XferCpltCallback(hmdma);
AnnaBridge 189:f392fc9709a3 1073 #endif
AnnaBridge 189:f392fc9709a3 1074 }
AnnaBridge 189:f392fc9709a3 1075
AnnaBridge 189:f392fc9709a3 1076 /**
AnnaBridge 189:f392fc9709a3 1077 * @brief MDMA SRAM error callback.
AnnaBridge 189:f392fc9709a3 1078 * @param hmdma : MDMA handle
AnnaBridge 189:f392fc9709a3 1079 * @retval None
AnnaBridge 189:f392fc9709a3 1080 */
AnnaBridge 189:f392fc9709a3 1081 static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma)
AnnaBridge 189:f392fc9709a3 1082 {
AnnaBridge 189:f392fc9709a3 1083 SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
AnnaBridge 189:f392fc9709a3 1084
AnnaBridge 189:f392fc9709a3 1085 /* Disable the MDMA channel */
AnnaBridge 189:f392fc9709a3 1086 __HAL_MDMA_DISABLE(hmdma);
AnnaBridge 189:f392fc9709a3 1087
AnnaBridge 189:f392fc9709a3 1088 /* Update the SRAM controller state */
AnnaBridge 189:f392fc9709a3 1089 hsram->State = HAL_SRAM_STATE_ERROR;
AnnaBridge 189:f392fc9709a3 1090
AnnaBridge 189:f392fc9709a3 1091 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 189:f392fc9709a3 1092 hsram->DmaXferErrorCallback(hmdma);
AnnaBridge 189:f392fc9709a3 1093 #else
AnnaBridge 189:f392fc9709a3 1094 HAL_SRAM_DMA_XferErrorCallback(hmdma);
AnnaBridge 189:f392fc9709a3 1095 #endif
AnnaBridge 189:f392fc9709a3 1096 }
AnnaBridge 189:f392fc9709a3 1097 /**
AnnaBridge 189:f392fc9709a3 1098 @endcond
AnnaBridge 189:f392fc9709a3 1099 */
AnnaBridge 189:f392fc9709a3 1100
AnnaBridge 189:f392fc9709a3 1101 /**
AnnaBridge 189:f392fc9709a3 1102 * @}
AnnaBridge 189:f392fc9709a3 1103 */
AnnaBridge 189:f392fc9709a3 1104
AnnaBridge 189:f392fc9709a3 1105 #endif /* HAL_SRAM_MODULE_ENABLED */
AnnaBridge 189:f392fc9709a3 1106
AnnaBridge 189:f392fc9709a3 1107 /**
AnnaBridge 189:f392fc9709a3 1108 * @}
AnnaBridge 189:f392fc9709a3 1109 */
AnnaBridge 189:f392fc9709a3 1110
AnnaBridge 189:f392fc9709a3 1111
AnnaBridge 189:f392fc9709a3 1112 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/