mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32h7xx_hal_rcc_ex.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of RCC HAL Extension module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge	189:f392fc9709a3	10	* All rights reserved.</center></h2>
AnnaBridge	189:f392fc9709a3	11	*
AnnaBridge	189:f392fc9709a3	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	189:f392fc9709a3	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	189:f392fc9709a3	14	* License. You may obtain a copy of the License at:
AnnaBridge	189:f392fc9709a3	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	189:f392fc9709a3	16	*
AnnaBridge	189:f392fc9709a3	17	******************************************************************************
AnnaBridge	189:f392fc9709a3	18	*/
AnnaBridge	189:f392fc9709a3	19
AnnaBridge	189:f392fc9709a3	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	21	#ifndef STM32H7xx_HAL_RCC_EX_H
AnnaBridge	189:f392fc9709a3	22	#define STM32H7xx_HAL_RCC_EX_H
AnnaBridge	189:f392fc9709a3	23
AnnaBridge	189:f392fc9709a3	24	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	25	extern "C" {
AnnaBridge	189:f392fc9709a3	26	#endif
AnnaBridge	189:f392fc9709a3	27
AnnaBridge	189:f392fc9709a3	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	29	#include "stm32h7xx_hal_def.h"
AnnaBridge	189:f392fc9709a3	30
AnnaBridge	189:f392fc9709a3	31	/** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge	189:f392fc9709a3	32	* @{
AnnaBridge	189:f392fc9709a3	33	*/
AnnaBridge	189:f392fc9709a3	34
AnnaBridge	189:f392fc9709a3	35	/** @addtogroup RCCEx
AnnaBridge	189:f392fc9709a3	36	* @{
AnnaBridge	189:f392fc9709a3	37	*/
AnnaBridge	189:f392fc9709a3	38
AnnaBridge	189:f392fc9709a3	39	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	40	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge	189:f392fc9709a3	41	* @{
AnnaBridge	189:f392fc9709a3	42	*/
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	/**
AnnaBridge	189:f392fc9709a3	45	* @brief PLL2 Clock structure definition
AnnaBridge	189:f392fc9709a3	46	*/
AnnaBridge	189:f392fc9709a3	47	typedef struct
AnnaBridge	189:f392fc9709a3	48	{
AnnaBridge	189:f392fc9709a3	49
AnnaBridge	189:f392fc9709a3	50	uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock.
AnnaBridge	189:f392fc9709a3	51	This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
AnnaBridge	189:f392fc9709a3	52
AnnaBridge	189:f392fc9709a3	53	uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
AnnaBridge	189:f392fc9709a3	54	This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
AnnaBridge	189:f392fc9709a3	55
AnnaBridge	189:f392fc9709a3	56	uint32_t PLL2P; /*!< PLL2P: Division factor for system clock.
AnnaBridge	189:f392fc9709a3	57	This parameter must be a number between Min_Data = 2 and Max_Data = 128
AnnaBridge	189:f392fc9709a3	58	odd division factors are not allowed */
AnnaBridge	189:f392fc9709a3	59
AnnaBridge	189:f392fc9709a3	60	uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks.
AnnaBridge	189:f392fc9709a3	61	This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
AnnaBridge	189:f392fc9709a3	62
AnnaBridge	189:f392fc9709a3	63	uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks.
AnnaBridge	189:f392fc9709a3	64	This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
AnnaBridge	189:f392fc9709a3	65	uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range
AnnaBridge	189:f392fc9709a3	66	This parameter must be a value of @ref RCC_PLL2_VCI_Range */
AnnaBridge	189:f392fc9709a3	67	uint32_t PLL2VCOSEL; /*!<PLL2VCOSEL: PLL2 clock Output range
AnnaBridge	189:f392fc9709a3	68	This parameter must be a value of @ref RCC_PLL2_VCO_Range */
AnnaBridge	189:f392fc9709a3	69
AnnaBridge	189:f392fc9709a3	70	uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
AnnaBridge	189:f392fc9709a3	71	PLL2 VCO It should be a value between 0 and 8191 */
AnnaBridge	189:f392fc9709a3	72	}RCC_PLL2InitTypeDef;
AnnaBridge	189:f392fc9709a3	73
AnnaBridge	189:f392fc9709a3	74
AnnaBridge	189:f392fc9709a3	75	/**
AnnaBridge	189:f392fc9709a3	76	* @brief PLL3 Clock structure definition
AnnaBridge	189:f392fc9709a3	77	*/
AnnaBridge	189:f392fc9709a3	78	typedef struct
AnnaBridge	189:f392fc9709a3	79	{
AnnaBridge	189:f392fc9709a3	80
AnnaBridge	189:f392fc9709a3	81	uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock.
AnnaBridge	189:f392fc9709a3	82	This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
AnnaBridge	189:f392fc9709a3	83
AnnaBridge	189:f392fc9709a3	84	uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.
AnnaBridge	189:f392fc9709a3	85	This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
AnnaBridge	189:f392fc9709a3	86
AnnaBridge	189:f392fc9709a3	87	uint32_t PLL3P; /*!< PLL3P: Division factor for system clock.
AnnaBridge	189:f392fc9709a3	88	This parameter must be a number between Min_Data = 2 and Max_Data = 128
AnnaBridge	189:f392fc9709a3	89	odd division factors are not allowed */
AnnaBridge	189:f392fc9709a3	90
AnnaBridge	189:f392fc9709a3	91	uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks.
AnnaBridge	189:f392fc9709a3	92	This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
AnnaBridge	189:f392fc9709a3	93
AnnaBridge	189:f392fc9709a3	94	uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks.
AnnaBridge	189:f392fc9709a3	95	This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
AnnaBridge	189:f392fc9709a3	96	uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range
AnnaBridge	189:f392fc9709a3	97	This parameter must be a value of @ref RCC_PLL3_VCI_Range */
AnnaBridge	189:f392fc9709a3	98	uint32_t PLL3VCOSEL; /*!<PLL3VCOSEL: PLL3 clock Output range
AnnaBridge	189:f392fc9709a3	99	This parameter must be a value of @ref RCC_PLL3_VCO_Range */
AnnaBridge	189:f392fc9709a3	100
AnnaBridge	189:f392fc9709a3	101	uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
AnnaBridge	189:f392fc9709a3	102	PLL3 VCO It should be a value between 0 and 8191 */
AnnaBridge	189:f392fc9709a3	103	}RCC_PLL3InitTypeDef;
AnnaBridge	189:f392fc9709a3	104
AnnaBridge	189:f392fc9709a3	105	/**
AnnaBridge	189:f392fc9709a3	106	* @brief RCC PLL1 Clocks structure definition
AnnaBridge	189:f392fc9709a3	107	*/
AnnaBridge	189:f392fc9709a3	108	typedef struct
AnnaBridge	189:f392fc9709a3	109	{
AnnaBridge	189:f392fc9709a3	110	uint32_t PLL1_P_Frequency;
AnnaBridge	189:f392fc9709a3	111	uint32_t PLL1_Q_Frequency;
AnnaBridge	189:f392fc9709a3	112	uint32_t PLL1_R_Frequency;
AnnaBridge	189:f392fc9709a3	113	}PLL1_ClocksTypeDef;
AnnaBridge	189:f392fc9709a3	114
AnnaBridge	189:f392fc9709a3	115	/**
AnnaBridge	189:f392fc9709a3	116	* @brief RCC PLL2 Clocks structure definition
AnnaBridge	189:f392fc9709a3	117	*/
AnnaBridge	189:f392fc9709a3	118	typedef struct
AnnaBridge	189:f392fc9709a3	119	{
AnnaBridge	189:f392fc9709a3	120	uint32_t PLL2_P_Frequency;
AnnaBridge	189:f392fc9709a3	121	uint32_t PLL2_Q_Frequency;
AnnaBridge	189:f392fc9709a3	122	uint32_t PLL2_R_Frequency;
AnnaBridge	189:f392fc9709a3	123	}PLL2_ClocksTypeDef;
AnnaBridge	189:f392fc9709a3	124
AnnaBridge	189:f392fc9709a3	125	/**
AnnaBridge	189:f392fc9709a3	126	* @brief RCC PLL3 Clocks structure definition
AnnaBridge	189:f392fc9709a3	127	*/
AnnaBridge	189:f392fc9709a3	128	typedef struct
AnnaBridge	189:f392fc9709a3	129	{
AnnaBridge	189:f392fc9709a3	130	uint32_t PLL3_P_Frequency;
AnnaBridge	189:f392fc9709a3	131	uint32_t PLL3_Q_Frequency;
AnnaBridge	189:f392fc9709a3	132	uint32_t PLL3_R_Frequency;
AnnaBridge	189:f392fc9709a3	133	}PLL3_ClocksTypeDef;
AnnaBridge	189:f392fc9709a3	134
AnnaBridge	189:f392fc9709a3	135
AnnaBridge	189:f392fc9709a3	136	/**
AnnaBridge	189:f392fc9709a3	137	* @brief RCC extended clocks structure definition
AnnaBridge	189:f392fc9709a3	138	*/
AnnaBridge	189:f392fc9709a3	139	typedef struct
AnnaBridge	189:f392fc9709a3	140	{
AnnaBridge	189:f392fc9709a3	141	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	189:f392fc9709a3	142	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	189:f392fc9709a3	143
AnnaBridge	189:f392fc9709a3	144	RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters.
AnnaBridge	189:f392fc9709a3	145	This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
AnnaBridge	189:f392fc9709a3	146
AnnaBridge	189:f392fc9709a3	147	RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters.
AnnaBridge	189:f392fc9709a3	148	This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
AnnaBridge	189:f392fc9709a3	149
AnnaBridge	189:f392fc9709a3	150	uint32_t FmcClockSelection; /*!< Specifies FMC clock source
AnnaBridge	189:f392fc9709a3	151	This parameter can be a value of @ref RCCEx_FMC_Clock_Source */
AnnaBridge	189:f392fc9709a3	152
AnnaBridge	189:f392fc9709a3	153	uint32_t QspiClockSelection; /*!< Specifies QSPI clock source
AnnaBridge	189:f392fc9709a3	154	This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */
AnnaBridge	189:f392fc9709a3	155
AnnaBridge	189:f392fc9709a3	156	uint32_t SdmmcClockSelection; /*!< Specifies SDMMC clock source
AnnaBridge	189:f392fc9709a3	157	This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */
AnnaBridge	189:f392fc9709a3	158
AnnaBridge	189:f392fc9709a3	159	uint32_t CkperClockSelection; /*!< Specifies CKPER clock source
AnnaBridge	189:f392fc9709a3	160	This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */
AnnaBridge	189:f392fc9709a3	161
AnnaBridge	189:f392fc9709a3	162	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source
AnnaBridge	189:f392fc9709a3	163	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
AnnaBridge	189:f392fc9709a3	164
AnnaBridge	189:f392fc9709a3	165	uint32_t Sai23ClockSelection; /*!< Specifies SAI2/3 clock source
AnnaBridge	189:f392fc9709a3	166	This parameter can be a value of @ref RCCEx_SAI23_Clock_Source */
AnnaBridge	189:f392fc9709a3	167
AnnaBridge	189:f392fc9709a3	168	uint32_t Spi123ClockSelection; /*!< Specifies SPI1/2/3 clock source
AnnaBridge	189:f392fc9709a3	169	This parameter can be a value of @ref RCCEx_SPI123_Clock_Source */
AnnaBridge	189:f392fc9709a3	170
AnnaBridge	189:f392fc9709a3	171	uint32_t Spi45ClockSelection; /*!< Specifies SPI4/5 clock source
AnnaBridge	189:f392fc9709a3	172	This parameter can be a value of @ref RCCEx_SPI45_Clock_Source */
AnnaBridge	189:f392fc9709a3	173
AnnaBridge	189:f392fc9709a3	174	uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source
AnnaBridge	189:f392fc9709a3	175	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
AnnaBridge	189:f392fc9709a3	176
AnnaBridge	189:f392fc9709a3	177	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock clock source
AnnaBridge	189:f392fc9709a3	178	This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
AnnaBridge	189:f392fc9709a3	179	#if defined(FDCAN1) \|\| defined(FDCAN2)
AnnaBridge	189:f392fc9709a3	180	uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source
AnnaBridge	189:f392fc9709a3	181	This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */
AnnaBridge	189:f392fc9709a3	182	#endif /FDCAN1 \|\| FDCAN2/
AnnaBridge	189:f392fc9709a3	183
AnnaBridge	189:f392fc9709a3	184	uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 Clock clock source
AnnaBridge	189:f392fc9709a3	185	This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
AnnaBridge	189:f392fc9709a3	186
AnnaBridge	189:f392fc9709a3	187	uint32_t Usart234578ClockSelection; /*!< Specifies USART2/3/4/5/7/8 clock source
AnnaBridge	189:f392fc9709a3	188	This parameter can be a value of @ref RCCEx_USART234578_Clock_Source */
AnnaBridge	189:f392fc9709a3	189
AnnaBridge	189:f392fc9709a3	190	uint32_t Usart16ClockSelection; /*!< Specifies USART1/6 clock source
AnnaBridge	189:f392fc9709a3	191	This parameter can be a value of @ref RCCEx_USART16_Clock_Source */
AnnaBridge	189:f392fc9709a3	192
AnnaBridge	189:f392fc9709a3	193	uint32_t RngClockSelection; /*!< Specifies RNG clock source
AnnaBridge	189:f392fc9709a3	194	This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
AnnaBridge	189:f392fc9709a3	195
AnnaBridge	189:f392fc9709a3	196	uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source
AnnaBridge	189:f392fc9709a3	197	This parameter can be a value of @ref RCCEx_I2C123_Clock_Source */
AnnaBridge	189:f392fc9709a3	198
AnnaBridge	189:f392fc9709a3	199	uint32_t UsbClockSelection; /*!< Specifies USB clock source
AnnaBridge	189:f392fc9709a3	200	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	189:f392fc9709a3	201
AnnaBridge	189:f392fc9709a3	202	uint32_t CecClockSelection; /*!< Specifies CEC clock source
AnnaBridge	189:f392fc9709a3	203	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	189:f392fc9709a3	204
AnnaBridge	189:f392fc9709a3	205	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
AnnaBridge	189:f392fc9709a3	206	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge	189:f392fc9709a3	207
AnnaBridge	189:f392fc9709a3	208	uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source
AnnaBridge	189:f392fc9709a3	209	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
AnnaBridge	189:f392fc9709a3	210
AnnaBridge	189:f392fc9709a3	211	uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source
AnnaBridge	189:f392fc9709a3	212	This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
AnnaBridge	189:f392fc9709a3	213
AnnaBridge	189:f392fc9709a3	214	uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source
AnnaBridge	189:f392fc9709a3	215	This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
AnnaBridge	189:f392fc9709a3	216
AnnaBridge	189:f392fc9709a3	217	uint32_t Lptim345ClockSelection; /*!< Specifies LPTIM3/4/5 clock source
AnnaBridge	189:f392fc9709a3	218	This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source */
AnnaBridge	189:f392fc9709a3	219
AnnaBridge	189:f392fc9709a3	220	uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source
AnnaBridge	189:f392fc9709a3	221	This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
AnnaBridge	189:f392fc9709a3	222
AnnaBridge	189:f392fc9709a3	223	uint32_t Sai4AClockSelection; /*!< Specifies SAI4A clock source
AnnaBridge	189:f392fc9709a3	224	This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source */
AnnaBridge	189:f392fc9709a3	225
AnnaBridge	189:f392fc9709a3	226	uint32_t Sai4BClockSelection; /*!< Specifies SAI4B clock source
AnnaBridge	189:f392fc9709a3	227	This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source */
AnnaBridge	189:f392fc9709a3	228
AnnaBridge	189:f392fc9709a3	229	uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source
AnnaBridge	189:f392fc9709a3	230	This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */
AnnaBridge	189:f392fc9709a3	231
AnnaBridge	189:f392fc9709a3	232	uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source
AnnaBridge	189:f392fc9709a3	233	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	189:f392fc9709a3	234
AnnaBridge	189:f392fc9709a3	235	uint32_t Hrtim1ClockSelection; /*!< Specifies HRTIM1 Clock clock source
AnnaBridge	189:f392fc9709a3	236	This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
AnnaBridge	189:f392fc9709a3	237	uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
AnnaBridge	189:f392fc9709a3	238	This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
AnnaBridge	189:f392fc9709a3	239	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	189:f392fc9709a3	240
AnnaBridge	189:f392fc9709a3	241
AnnaBridge	189:f392fc9709a3	242	/**
AnnaBridge	189:f392fc9709a3	243	* @brief RCC_CRS Init structure definition
AnnaBridge	189:f392fc9709a3	244	*/
AnnaBridge	189:f392fc9709a3	245	typedef struct
AnnaBridge	189:f392fc9709a3	246	{
AnnaBridge	189:f392fc9709a3	247	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
AnnaBridge	189:f392fc9709a3	248	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
AnnaBridge	189:f392fc9709a3	249
AnnaBridge	189:f392fc9709a3	250	uint32_t Source; /*!< Specifies the SYNC signal source.
AnnaBridge	189:f392fc9709a3	251	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
AnnaBridge	189:f392fc9709a3	252
AnnaBridge	189:f392fc9709a3	253	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
AnnaBridge	189:f392fc9709a3	254	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
AnnaBridge	189:f392fc9709a3	255
AnnaBridge	189:f392fc9709a3	256	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
AnnaBridge	189:f392fc9709a3	257	It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
AnnaBridge	189:f392fc9709a3	258	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
AnnaBridge	189:f392fc9709a3	259
AnnaBridge	189:f392fc9709a3	260	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
AnnaBridge	189:f392fc9709a3	261	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
AnnaBridge	189:f392fc9709a3	262
AnnaBridge	189:f392fc9709a3	263	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
AnnaBridge	189:f392fc9709a3	264	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
AnnaBridge	189:f392fc9709a3	265
AnnaBridge	189:f392fc9709a3	266	}RCC_CRSInitTypeDef;
AnnaBridge	189:f392fc9709a3	267
AnnaBridge	189:f392fc9709a3	268	/**
AnnaBridge	189:f392fc9709a3	269	* @brief RCC_CRS Synchronization structure definition
AnnaBridge	189:f392fc9709a3	270	*/
AnnaBridge	189:f392fc9709a3	271	typedef struct
AnnaBridge	189:f392fc9709a3	272	{
AnnaBridge	189:f392fc9709a3	273	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
AnnaBridge	189:f392fc9709a3	274	This parameter must be a number between 0 and 0xFFFF */
AnnaBridge	189:f392fc9709a3	275
AnnaBridge	189:f392fc9709a3	276	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
AnnaBridge	189:f392fc9709a3	277	This parameter must be a number between 0 and 0x3F */
AnnaBridge	189:f392fc9709a3	278
AnnaBridge	189:f392fc9709a3	279	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
AnnaBridge	189:f392fc9709a3	280	value latched in the time of the last SYNC event.
AnnaBridge	189:f392fc9709a3	281	This parameter must be a number between 0 and 0xFFFF */
AnnaBridge	189:f392fc9709a3	282
AnnaBridge	189:f392fc9709a3	283	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
AnnaBridge	189:f392fc9709a3	284	frequency error counter latched in the time of the last SYNC event.
AnnaBridge	189:f392fc9709a3	285	It shows whether the actual frequency is below or above the target.
AnnaBridge	189:f392fc9709a3	286	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
AnnaBridge	189:f392fc9709a3	287
AnnaBridge	189:f392fc9709a3	288	}RCC_CRSSynchroInfoTypeDef;
AnnaBridge	189:f392fc9709a3	289
AnnaBridge	189:f392fc9709a3	290	/**
AnnaBridge	189:f392fc9709a3	291	* @}
AnnaBridge	189:f392fc9709a3	292	*/
AnnaBridge	189:f392fc9709a3	293
AnnaBridge	189:f392fc9709a3	294
AnnaBridge	189:f392fc9709a3	295	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	296	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge	189:f392fc9709a3	297	* @{
AnnaBridge	189:f392fc9709a3	298	*/
AnnaBridge	189:f392fc9709a3	299
AnnaBridge	189:f392fc9709a3	300	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
AnnaBridge	189:f392fc9709a3	301	* @{
AnnaBridge	189:f392fc9709a3	302	*/
AnnaBridge	189:f392fc9709a3	303
AnnaBridge	189:f392fc9709a3	304	#define RCC_PERIPHCLK_USART16 (0x00000001U)
AnnaBridge	189:f392fc9709a3	305	#define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16
AnnaBridge	189:f392fc9709a3	306	#define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16
AnnaBridge	189:f392fc9709a3	307	#define RCC_PERIPHCLK_USART234578 (0x00000002U)
AnnaBridge	189:f392fc9709a3	308	#define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578
AnnaBridge	189:f392fc9709a3	309	#define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578
AnnaBridge	189:f392fc9709a3	310	#define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578
AnnaBridge	189:f392fc9709a3	311	#define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578
AnnaBridge	189:f392fc9709a3	312	#define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578
AnnaBridge	189:f392fc9709a3	313	#define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578
AnnaBridge	189:f392fc9709a3	314	#define RCC_PERIPHCLK_LPUART1 (0x00000004U)
AnnaBridge	189:f392fc9709a3	315	#define RCC_PERIPHCLK_I2C123 (0x00000008U)
AnnaBridge	189:f392fc9709a3	316	#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123
AnnaBridge	189:f392fc9709a3	317	#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123
AnnaBridge	189:f392fc9709a3	318	#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123
AnnaBridge	189:f392fc9709a3	319	#define RCC_PERIPHCLK_I2C4 (0x00000010U)
AnnaBridge	189:f392fc9709a3	320	#define RCC_PERIPHCLK_LPTIM1 (0x00000020U)
AnnaBridge	189:f392fc9709a3	321	#define RCC_PERIPHCLK_LPTIM2 (0x00000040U)
AnnaBridge	189:f392fc9709a3	322	#define RCC_PERIPHCLK_LPTIM345 (0x00000080U)
AnnaBridge	189:f392fc9709a3	323	#define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345
AnnaBridge	189:f392fc9709a3	324	#define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345
AnnaBridge	189:f392fc9709a3	325	#define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345
AnnaBridge	189:f392fc9709a3	326	#define RCC_PERIPHCLK_SAI1 (0x00000100U)
AnnaBridge	189:f392fc9709a3	327	#define RCC_PERIPHCLK_SAI23 (0x00000200U)
AnnaBridge	189:f392fc9709a3	328	#define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23
AnnaBridge	189:f392fc9709a3	329	#define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23
AnnaBridge	189:f392fc9709a3	330	#define RCC_PERIPHCLK_SAI4A (0x00000400U)
AnnaBridge	189:f392fc9709a3	331	#define RCC_PERIPHCLK_SAI4B (0x00000800U)
AnnaBridge	189:f392fc9709a3	332	#define RCC_PERIPHCLK_SPI123 (0x00001000U)
AnnaBridge	189:f392fc9709a3	333	#define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123
AnnaBridge	189:f392fc9709a3	334	#define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123
AnnaBridge	189:f392fc9709a3	335	#define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123
AnnaBridge	189:f392fc9709a3	336	#define RCC_PERIPHCLK_SPI45 (0x00002000U)
AnnaBridge	189:f392fc9709a3	337	#define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45
AnnaBridge	189:f392fc9709a3	338	#define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45
AnnaBridge	189:f392fc9709a3	339	#define RCC_PERIPHCLK_SPI6 (0x00004000U)
AnnaBridge	189:f392fc9709a3	340	#define RCC_PERIPHCLK_FDCAN (0x00008000U)
AnnaBridge	189:f392fc9709a3	341	#define RCC_PERIPHCLK_SDMMC (0x00010000U)
AnnaBridge	189:f392fc9709a3	342	#define RCC_PERIPHCLK_RNG (0x00020000U)
AnnaBridge	189:f392fc9709a3	343	#define RCC_PERIPHCLK_USB (0x00040000U)
AnnaBridge	189:f392fc9709a3	344	#define RCC_PERIPHCLK_ADC (0x00080000U)
AnnaBridge	189:f392fc9709a3	345	#define RCC_PERIPHCLK_SWPMI1 (0x00100000U)
AnnaBridge	189:f392fc9709a3	346	#define RCC_PERIPHCLK_DFSDM1 (0x00200000U)
AnnaBridge	189:f392fc9709a3	347	#define RCC_PERIPHCLK_RTC (0x00400000U)
AnnaBridge	189:f392fc9709a3	348	#define RCC_PERIPHCLK_CEC (0x00800000U)
AnnaBridge	189:f392fc9709a3	349	#define RCC_PERIPHCLK_FMC (0x01000000U)
AnnaBridge	189:f392fc9709a3	350	#define RCC_PERIPHCLK_QSPI (0x02000000U)
AnnaBridge	189:f392fc9709a3	351	#define RCC_PERIPHCLK_SPDIFRX (0x08000000U)
AnnaBridge	189:f392fc9709a3	352	#define RCC_PERIPHCLK_HRTIM1 (0x10000000U)
AnnaBridge	189:f392fc9709a3	353	#define RCC_PERIPHCLK_LTDC (0x20000000U)
AnnaBridge	189:f392fc9709a3	354	#define RCC_PERIPHCLK_TIM (0x40000000U)
AnnaBridge	189:f392fc9709a3	355	#define RCC_PERIPHCLK_CKPER (0x80000000U)
AnnaBridge	189:f392fc9709a3	356
AnnaBridge	189:f392fc9709a3	357	/**
AnnaBridge	189:f392fc9709a3	358	* @}
AnnaBridge	189:f392fc9709a3	359	*/
AnnaBridge	189:f392fc9709a3	360
AnnaBridge	189:f392fc9709a3	361
AnnaBridge	189:f392fc9709a3	362	/** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output
AnnaBridge	189:f392fc9709a3	363	* @{
AnnaBridge	189:f392fc9709a3	364	*/
AnnaBridge	189:f392fc9709a3	365	#define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN
AnnaBridge	189:f392fc9709a3	366	#define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN
AnnaBridge	189:f392fc9709a3	367	#define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN
AnnaBridge	189:f392fc9709a3	368
AnnaBridge	189:f392fc9709a3	369	/**
AnnaBridge	189:f392fc9709a3	370	* @}
AnnaBridge	189:f392fc9709a3	371	*/
AnnaBridge	189:f392fc9709a3	372
AnnaBridge	189:f392fc9709a3	373	/** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output
AnnaBridge	189:f392fc9709a3	374	* @{
AnnaBridge	189:f392fc9709a3	375	*/
AnnaBridge	189:f392fc9709a3	376	#define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN
AnnaBridge	189:f392fc9709a3	377	#define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN
AnnaBridge	189:f392fc9709a3	378	#define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN
AnnaBridge	189:f392fc9709a3	379
AnnaBridge	189:f392fc9709a3	380	/**
AnnaBridge	189:f392fc9709a3	381	* @}
AnnaBridge	189:f392fc9709a3	382	*/
AnnaBridge	189:f392fc9709a3	383
AnnaBridge	189:f392fc9709a3	384	/** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range
AnnaBridge	189:f392fc9709a3	385	* @{
AnnaBridge	189:f392fc9709a3	386	*/
AnnaBridge	189:f392fc9709a3	387	#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
AnnaBridge	189:f392fc9709a3	388	#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
AnnaBridge	189:f392fc9709a3	389	#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
AnnaBridge	189:f392fc9709a3	390	#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3
AnnaBridge	189:f392fc9709a3	391
AnnaBridge	189:f392fc9709a3	392	/**
AnnaBridge	189:f392fc9709a3	393	* @}
AnnaBridge	189:f392fc9709a3	394	*/
AnnaBridge	189:f392fc9709a3	395
AnnaBridge	189:f392fc9709a3	396
AnnaBridge	189:f392fc9709a3	397	/** @defgroup RCC_PLL2_VCO_Range RCC PLL2 VCO Range
AnnaBridge	189:f392fc9709a3	398	* @{
AnnaBridge	189:f392fc9709a3	399	*/
AnnaBridge	189:f392fc9709a3	400	#define RCC_PLL2VCOWIDE (0x00000000U)
AnnaBridge	189:f392fc9709a3	401	#define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL
AnnaBridge	189:f392fc9709a3	402
AnnaBridge	189:f392fc9709a3	403	/**
AnnaBridge	189:f392fc9709a3	404	* @}
AnnaBridge	189:f392fc9709a3	405	*/
AnnaBridge	189:f392fc9709a3	406
AnnaBridge	189:f392fc9709a3	407	/** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range
AnnaBridge	189:f392fc9709a3	408	* @{
AnnaBridge	189:f392fc9709a3	409	*/
AnnaBridge	189:f392fc9709a3	410	#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
AnnaBridge	189:f392fc9709a3	411	#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
AnnaBridge	189:f392fc9709a3	412	#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
AnnaBridge	189:f392fc9709a3	413	#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3
AnnaBridge	189:f392fc9709a3	414
AnnaBridge	189:f392fc9709a3	415	/**
AnnaBridge	189:f392fc9709a3	416	* @}
AnnaBridge	189:f392fc9709a3	417	*/
AnnaBridge	189:f392fc9709a3	418
AnnaBridge	189:f392fc9709a3	419
AnnaBridge	189:f392fc9709a3	420	/** @defgroup RCC_PLL3_VCO_Range RCC PLL3 VCO Range
AnnaBridge	189:f392fc9709a3	421	* @{
AnnaBridge	189:f392fc9709a3	422	*/
AnnaBridge	189:f392fc9709a3	423	#define RCC_PLL3VCOWIDE (0x00000000U)
AnnaBridge	189:f392fc9709a3	424	#define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL
AnnaBridge	189:f392fc9709a3	425
AnnaBridge	189:f392fc9709a3	426	/**
AnnaBridge	189:f392fc9709a3	427	* @}
AnnaBridge	189:f392fc9709a3	428	*/
AnnaBridge	189:f392fc9709a3	429
AnnaBridge	189:f392fc9709a3	430	/** @defgroup RCCEx_USART16_Clock_Source RCCEx USART1/6 Clock Source
AnnaBridge	189:f392fc9709a3	431	* @{
AnnaBridge	189:f392fc9709a3	432	*/
AnnaBridge	189:f392fc9709a3	433	#define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U)
AnnaBridge	189:f392fc9709a3	434	#define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0
AnnaBridge	189:f392fc9709a3	435	#define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1
AnnaBridge	189:f392fc9709a3	436	#define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 \| RCC_D2CCIP2R_USART16SEL_1)
AnnaBridge	189:f392fc9709a3	437	#define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2
AnnaBridge	189:f392fc9709a3	438	#define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 \| RCC_D2CCIP2R_USART16SEL_2)
AnnaBridge	189:f392fc9709a3	439	/**
AnnaBridge	189:f392fc9709a3	440	* @}
AnnaBridge	189:f392fc9709a3	441	*/
AnnaBridge	189:f392fc9709a3	442
AnnaBridge	189:f392fc9709a3	443	/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
AnnaBridge	189:f392fc9709a3	444	* @{
AnnaBridge	189:f392fc9709a3	445	*/
AnnaBridge	189:f392fc9709a3	446	#define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
AnnaBridge	189:f392fc9709a3	447	#define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	448	#define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	449	#define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	450	#define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	451	#define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	452	/**
AnnaBridge	189:f392fc9709a3	453	* @}
AnnaBridge	189:f392fc9709a3	454	*/
AnnaBridge	189:f392fc9709a3	455
AnnaBridge	189:f392fc9709a3	456	/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
AnnaBridge	189:f392fc9709a3	457	* @{
AnnaBridge	189:f392fc9709a3	458	*/
AnnaBridge	189:f392fc9709a3	459	#define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
AnnaBridge	189:f392fc9709a3	460	#define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	461	#define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	462	#define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	463	#define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	464	#define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	465
AnnaBridge	189:f392fc9709a3	466	/**
AnnaBridge	189:f392fc9709a3	467	* @}
AnnaBridge	189:f392fc9709a3	468	*/
AnnaBridge	189:f392fc9709a3	469
AnnaBridge	189:f392fc9709a3	470	/** @defgroup RCCEx_USART234578_Clock_Source RCCEx USART2/3/4/5/7/8 Clock Source
AnnaBridge	189:f392fc9709a3	471	* @{
AnnaBridge	189:f392fc9709a3	472	*/
AnnaBridge	189:f392fc9709a3	473	#define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	474	#define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
AnnaBridge	189:f392fc9709a3	475	#define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
AnnaBridge	189:f392fc9709a3	476	#define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 \| RCC_D2CCIP2R_USART28SEL_1)
AnnaBridge	189:f392fc9709a3	477	#define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
AnnaBridge	189:f392fc9709a3	478	#define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 \| RCC_D2CCIP2R_USART28SEL_2)
AnnaBridge	189:f392fc9709a3	479
AnnaBridge	189:f392fc9709a3	480	/**
AnnaBridge	189:f392fc9709a3	481	* @}
AnnaBridge	189:f392fc9709a3	482	*/
AnnaBridge	189:f392fc9709a3	483
AnnaBridge	189:f392fc9709a3	484	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
AnnaBridge	189:f392fc9709a3	485	* @{
AnnaBridge	189:f392fc9709a3	486	*/
AnnaBridge	189:f392fc9709a3	487	#define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	488	#define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	489	#define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	490	#define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	491	#define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	492	#define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	493
AnnaBridge	189:f392fc9709a3	494	/**
AnnaBridge	189:f392fc9709a3	495	* @}
AnnaBridge	189:f392fc9709a3	496	*/
AnnaBridge	189:f392fc9709a3	497
AnnaBridge	189:f392fc9709a3	498	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
AnnaBridge	189:f392fc9709a3	499	* @{
AnnaBridge	189:f392fc9709a3	500	*/
AnnaBridge	189:f392fc9709a3	501	#define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	502	#define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	503	#define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	504	#define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	505	#define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	506	#define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	507
AnnaBridge	189:f392fc9709a3	508	/**
AnnaBridge	189:f392fc9709a3	509	* @}
AnnaBridge	189:f392fc9709a3	510	*/
AnnaBridge	189:f392fc9709a3	511
AnnaBridge	189:f392fc9709a3	512	/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
AnnaBridge	189:f392fc9709a3	513	* @{
AnnaBridge	189:f392fc9709a3	514	*/
AnnaBridge	189:f392fc9709a3	515	#define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	516	#define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	517	#define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	518	#define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	519	#define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	520	#define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	521
AnnaBridge	189:f392fc9709a3	522	/**
AnnaBridge	189:f392fc9709a3	523	* @}
AnnaBridge	189:f392fc9709a3	524	*/
AnnaBridge	189:f392fc9709a3	525
AnnaBridge	189:f392fc9709a3	526	/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
AnnaBridge	189:f392fc9709a3	527	* @{
AnnaBridge	189:f392fc9709a3	528	*/
AnnaBridge	189:f392fc9709a3	529	#define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	530	#define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	531	#define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	532	#define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	533	#define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	534	#define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	535
AnnaBridge	189:f392fc9709a3	536	/**
AnnaBridge	189:f392fc9709a3	537	* @}
AnnaBridge	189:f392fc9709a3	538	*/
AnnaBridge	189:f392fc9709a3	539
AnnaBridge	189:f392fc9709a3	540	/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
AnnaBridge	189:f392fc9709a3	541	* @{
AnnaBridge	189:f392fc9709a3	542	*/
AnnaBridge	189:f392fc9709a3	543	#define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	544	#define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	545	#define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	546	#define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	547	#define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	548	#define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	549
AnnaBridge	189:f392fc9709a3	550	/**
AnnaBridge	189:f392fc9709a3	551	* @}
AnnaBridge	189:f392fc9709a3	552	*/
AnnaBridge	189:f392fc9709a3	553
AnnaBridge	189:f392fc9709a3	554	/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
AnnaBridge	189:f392fc9709a3	555	* @{
AnnaBridge	189:f392fc9709a3	556	*/
AnnaBridge	189:f392fc9709a3	557	#define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	558	#define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	559	#define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	560	#define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	561	#define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	562	#define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	563
AnnaBridge	189:f392fc9709a3	564	/**
AnnaBridge	189:f392fc9709a3	565	* @}
AnnaBridge	189:f392fc9709a3	566	*/
AnnaBridge	189:f392fc9709a3	567
AnnaBridge	189:f392fc9709a3	568	/** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source
AnnaBridge	189:f392fc9709a3	569	* @{
AnnaBridge	189:f392fc9709a3	570	*/
AnnaBridge	189:f392fc9709a3	571	#define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	572	#define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0
AnnaBridge	189:f392fc9709a3	573	#define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1
AnnaBridge	189:f392fc9709a3	574	#define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 \| RCC_D3CCIPR_LPUART1SEL_1)
AnnaBridge	189:f392fc9709a3	575	#define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2
AnnaBridge	189:f392fc9709a3	576	#define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 \| RCC_D3CCIPR_LPUART1SEL_0)
AnnaBridge	189:f392fc9709a3	577
AnnaBridge	189:f392fc9709a3	578	/**
AnnaBridge	189:f392fc9709a3	579	* @}
AnnaBridge	189:f392fc9709a3	580	*/
AnnaBridge	189:f392fc9709a3	581
AnnaBridge	189:f392fc9709a3	582	/** @defgroup RCCEx_I2C123_Clock_Source RCCEx I2C1/2/3 Clock Source
AnnaBridge	189:f392fc9709a3	583	* @{
AnnaBridge	189:f392fc9709a3	584	*/
AnnaBridge	189:f392fc9709a3	585	#define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	586	#define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
AnnaBridge	189:f392fc9709a3	587	#define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
AnnaBridge	189:f392fc9709a3	588	#define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 \| RCC_D2CCIP2R_I2C123SEL_1)
AnnaBridge	189:f392fc9709a3	589
AnnaBridge	189:f392fc9709a3	590	/**
AnnaBridge	189:f392fc9709a3	591	* @}
AnnaBridge	189:f392fc9709a3	592	*/
AnnaBridge	189:f392fc9709a3	593
AnnaBridge	189:f392fc9709a3	594	/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
AnnaBridge	189:f392fc9709a3	595	* @{
AnnaBridge	189:f392fc9709a3	596	*/
AnnaBridge	189:f392fc9709a3	597	#define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	598	#define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	599	#define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	600	#define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	601
AnnaBridge	189:f392fc9709a3	602
AnnaBridge	189:f392fc9709a3	603	/**
AnnaBridge	189:f392fc9709a3	604	* @}
AnnaBridge	189:f392fc9709a3	605	*/
AnnaBridge	189:f392fc9709a3	606
AnnaBridge	189:f392fc9709a3	607	/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
AnnaBridge	189:f392fc9709a3	608	* @{
AnnaBridge	189:f392fc9709a3	609	*/
AnnaBridge	189:f392fc9709a3	610	#define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	611	#define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	612	#define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	613	#define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	614
AnnaBridge	189:f392fc9709a3	615	/**
AnnaBridge	189:f392fc9709a3	616	* @}
AnnaBridge	189:f392fc9709a3	617	*/
AnnaBridge	189:f392fc9709a3	618
AnnaBridge	189:f392fc9709a3	619	/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
AnnaBridge	189:f392fc9709a3	620	* @{
AnnaBridge	189:f392fc9709a3	621	*/
AnnaBridge	189:f392fc9709a3	622	#define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	623	#define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	624	#define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	625	#define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	626
AnnaBridge	189:f392fc9709a3	627	/**
AnnaBridge	189:f392fc9709a3	628	* @}
AnnaBridge	189:f392fc9709a3	629	*/
AnnaBridge	189:f392fc9709a3	630
AnnaBridge	189:f392fc9709a3	631	/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
AnnaBridge	189:f392fc9709a3	632	* @{
AnnaBridge	189:f392fc9709a3	633	*/
AnnaBridge	189:f392fc9709a3	634	#define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	635	#define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0
AnnaBridge	189:f392fc9709a3	636	#define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1
AnnaBridge	189:f392fc9709a3	637	#define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 \| RCC_D3CCIPR_I2C4SEL_1)
AnnaBridge	189:f392fc9709a3	638
AnnaBridge	189:f392fc9709a3	639
AnnaBridge	189:f392fc9709a3	640	/**
AnnaBridge	189:f392fc9709a3	641	* @}
AnnaBridge	189:f392fc9709a3	642	*/
AnnaBridge	189:f392fc9709a3	643
AnnaBridge	189:f392fc9709a3	644	/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source
AnnaBridge	189:f392fc9709a3	645	* @{
AnnaBridge	189:f392fc9709a3	646	*/
AnnaBridge	189:f392fc9709a3	647	#define RCC_RNGCLKSOURCE_HSI48 (0x00000000U)
AnnaBridge	189:f392fc9709a3	648	#define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0
AnnaBridge	189:f392fc9709a3	649	#define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1
AnnaBridge	189:f392fc9709a3	650	#define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL
AnnaBridge	189:f392fc9709a3	651
AnnaBridge	189:f392fc9709a3	652
AnnaBridge	189:f392fc9709a3	653	/**
AnnaBridge	189:f392fc9709a3	654	* @}
AnnaBridge	189:f392fc9709a3	655	*/
AnnaBridge	189:f392fc9709a3	656
AnnaBridge	189:f392fc9709a3	657	/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
AnnaBridge	189:f392fc9709a3	658	* @{
AnnaBridge	189:f392fc9709a3	659	*/
AnnaBridge	189:f392fc9709a3	660	#define RCC_HRTIM1CLK_TIMCLK (0x00000000U)
AnnaBridge	189:f392fc9709a3	661	#define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL
AnnaBridge	189:f392fc9709a3	662
AnnaBridge	189:f392fc9709a3	663	/**
AnnaBridge	189:f392fc9709a3	664	* @}
AnnaBridge	189:f392fc9709a3	665	*/
AnnaBridge	189:f392fc9709a3	666
AnnaBridge	189:f392fc9709a3	667	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
AnnaBridge	189:f392fc9709a3	668	* @{
AnnaBridge	189:f392fc9709a3	669	*/
AnnaBridge	189:f392fc9709a3	670	#define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0
AnnaBridge	189:f392fc9709a3	671	#define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1
AnnaBridge	189:f392fc9709a3	672	#define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL
AnnaBridge	189:f392fc9709a3	673
AnnaBridge	189:f392fc9709a3	674	/**
AnnaBridge	189:f392fc9709a3	675	* @}
AnnaBridge	189:f392fc9709a3	676	*/
AnnaBridge	189:f392fc9709a3	677
AnnaBridge	189:f392fc9709a3	678	/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
AnnaBridge	189:f392fc9709a3	679	* @{
AnnaBridge	189:f392fc9709a3	680	*/
AnnaBridge	189:f392fc9709a3	681	#define RCC_SAI1CLKSOURCE_PLL (0x00000000U)
AnnaBridge	189:f392fc9709a3	682	#define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0
AnnaBridge	189:f392fc9709a3	683	#define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1
AnnaBridge	189:f392fc9709a3	684	#define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 \| RCC_D2CCIP1R_SAI1SEL_1)
AnnaBridge	189:f392fc9709a3	685	#define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2
AnnaBridge	189:f392fc9709a3	686
AnnaBridge	189:f392fc9709a3	687	/**
AnnaBridge	189:f392fc9709a3	688	* @}
AnnaBridge	189:f392fc9709a3	689	*/
AnnaBridge	189:f392fc9709a3	690
AnnaBridge	189:f392fc9709a3	691
AnnaBridge	189:f392fc9709a3	692
AnnaBridge	189:f392fc9709a3	693	/** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source
AnnaBridge	189:f392fc9709a3	694	* @{
AnnaBridge	189:f392fc9709a3	695	*/
AnnaBridge	189:f392fc9709a3	696	#define RCC_SAI23CLKSOURCE_PLL (0x00000000U)
AnnaBridge	189:f392fc9709a3	697	#define RCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0
AnnaBridge	189:f392fc9709a3	698	#define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1
AnnaBridge	189:f392fc9709a3	699	#define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 \| RCC_D2CCIP1R_SAI23SEL_1)
AnnaBridge	189:f392fc9709a3	700	#define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2
AnnaBridge	189:f392fc9709a3	701
AnnaBridge	189:f392fc9709a3	702	/**
AnnaBridge	189:f392fc9709a3	703	* @}
AnnaBridge	189:f392fc9709a3	704	*/
AnnaBridge	189:f392fc9709a3	705
AnnaBridge	189:f392fc9709a3	706	/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
AnnaBridge	189:f392fc9709a3	707	* @{
AnnaBridge	189:f392fc9709a3	708	*/
AnnaBridge	189:f392fc9709a3	709	#define RCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	710	#define RCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	711	#define RCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	712	#define RCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN
AnnaBridge	189:f392fc9709a3	713	#define RCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP
AnnaBridge	189:f392fc9709a3	714
AnnaBridge	189:f392fc9709a3	715	/**
AnnaBridge	189:f392fc9709a3	716	* @}
AnnaBridge	189:f392fc9709a3	717	*/
AnnaBridge	189:f392fc9709a3	718
AnnaBridge	189:f392fc9709a3	719	/** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
AnnaBridge	189:f392fc9709a3	720	* @{
AnnaBridge	189:f392fc9709a3	721	*/
AnnaBridge	189:f392fc9709a3	722	#define RCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	723	#define RCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	724	#define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	725	#define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN
AnnaBridge	189:f392fc9709a3	726	#define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP
AnnaBridge	189:f392fc9709a3	727
AnnaBridge	189:f392fc9709a3	728	/**
AnnaBridge	189:f392fc9709a3	729	* @}
AnnaBridge	189:f392fc9709a3	730	*/
AnnaBridge	189:f392fc9709a3	731
AnnaBridge	189:f392fc9709a3	732	/** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source
AnnaBridge	189:f392fc9709a3	733	* @{
AnnaBridge	189:f392fc9709a3	734	*/
AnnaBridge	189:f392fc9709a3	735	#define RCC_SPI123CLKSOURCE_PLL (0x00000000U)
AnnaBridge	189:f392fc9709a3	736	#define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0
AnnaBridge	189:f392fc9709a3	737	#define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
AnnaBridge	189:f392fc9709a3	738	#define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 \| RCC_D2CCIP1R_SPI123SEL_1)
AnnaBridge	189:f392fc9709a3	739	#define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2
AnnaBridge	189:f392fc9709a3	740
AnnaBridge	189:f392fc9709a3	741	/**
AnnaBridge	189:f392fc9709a3	742	* @}
AnnaBridge	189:f392fc9709a3	743	*/
AnnaBridge	189:f392fc9709a3	744
AnnaBridge	189:f392fc9709a3	745	/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source
AnnaBridge	189:f392fc9709a3	746	* @{
AnnaBridge	189:f392fc9709a3	747	*/
AnnaBridge	189:f392fc9709a3	748	#define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	749	#define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	750	#define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	751	#define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
AnnaBridge	189:f392fc9709a3	752	#define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
AnnaBridge	189:f392fc9709a3	753
AnnaBridge	189:f392fc9709a3	754	/**
AnnaBridge	189:f392fc9709a3	755	* @}
AnnaBridge	189:f392fc9709a3	756	*/
AnnaBridge	189:f392fc9709a3	757
AnnaBridge	189:f392fc9709a3	758	/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source
AnnaBridge	189:f392fc9709a3	759	* @{
AnnaBridge	189:f392fc9709a3	760	*/
AnnaBridge	189:f392fc9709a3	761	#define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	762	#define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	763	#define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	764	#define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
AnnaBridge	189:f392fc9709a3	765	#define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
AnnaBridge	189:f392fc9709a3	766
AnnaBridge	189:f392fc9709a3	767	/**
AnnaBridge	189:f392fc9709a3	768	* @}
AnnaBridge	189:f392fc9709a3	769	*/
AnnaBridge	189:f392fc9709a3	770
AnnaBridge	189:f392fc9709a3	771	/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source
AnnaBridge	189:f392fc9709a3	772	* @{
AnnaBridge	189:f392fc9709a3	773	*/
AnnaBridge	189:f392fc9709a3	774	#define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
AnnaBridge	189:f392fc9709a3	775	#define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	776	#define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	777	#define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
AnnaBridge	189:f392fc9709a3	778	#define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
AnnaBridge	189:f392fc9709a3	779
AnnaBridge	189:f392fc9709a3	780	/**
AnnaBridge	189:f392fc9709a3	781	* @}
AnnaBridge	189:f392fc9709a3	782	*/
AnnaBridge	189:f392fc9709a3	783
AnnaBridge	189:f392fc9709a3	784	/** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source
AnnaBridge	189:f392fc9709a3	785	* @{
AnnaBridge	189:f392fc9709a3	786	*/
AnnaBridge	189:f392fc9709a3	787	#define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	788	#define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0
AnnaBridge	189:f392fc9709a3	789	#define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1
AnnaBridge	189:f392fc9709a3	790	#define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 \| RCC_D2CCIP1R_SPI45SEL_1)
AnnaBridge	189:f392fc9709a3	791	#define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2
AnnaBridge	189:f392fc9709a3	792	#define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 \| RCC_D2CCIP1R_SPI45SEL_2)
AnnaBridge	189:f392fc9709a3	793
AnnaBridge	189:f392fc9709a3	794	/**
AnnaBridge	189:f392fc9709a3	795	* @}
AnnaBridge	189:f392fc9709a3	796	*/
AnnaBridge	189:f392fc9709a3	797
AnnaBridge	189:f392fc9709a3	798	/** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source
AnnaBridge	189:f392fc9709a3	799	* @{
AnnaBridge	189:f392fc9709a3	800	*/
AnnaBridge	189:f392fc9709a3	801	#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	802	#define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	803	#define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	804	#define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	805	#define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	806	#define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
AnnaBridge	189:f392fc9709a3	807
AnnaBridge	189:f392fc9709a3	808	/**
AnnaBridge	189:f392fc9709a3	809	* @}
AnnaBridge	189:f392fc9709a3	810	*/
AnnaBridge	189:f392fc9709a3	811
AnnaBridge	189:f392fc9709a3	812	/** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source
AnnaBridge	189:f392fc9709a3	813	* @{
AnnaBridge	189:f392fc9709a3	814	*/
AnnaBridge	189:f392fc9709a3	815	#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
AnnaBridge	189:f392fc9709a3	816	#define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	817	#define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	818	#define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
AnnaBridge	189:f392fc9709a3	819	#define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
AnnaBridge	189:f392fc9709a3	820	#define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
AnnaBridge	189:f392fc9709a3	821
AnnaBridge	189:f392fc9709a3	822	/**
AnnaBridge	189:f392fc9709a3	823	* @}
AnnaBridge	189:f392fc9709a3	824	*/
AnnaBridge	189:f392fc9709a3	825
AnnaBridge	189:f392fc9709a3	826	/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
AnnaBridge	189:f392fc9709a3	827	* @{
AnnaBridge	189:f392fc9709a3	828	*/
AnnaBridge	189:f392fc9709a3	829	#define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	830	#define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0
AnnaBridge	189:f392fc9709a3	831	#define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1
AnnaBridge	189:f392fc9709a3	832	#define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 \| RCC_D3CCIPR_SPI6SEL_1)
AnnaBridge	189:f392fc9709a3	833	#define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2
AnnaBridge	189:f392fc9709a3	834	#define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 \| RCC_D3CCIPR_SPI6SEL_2)
AnnaBridge	189:f392fc9709a3	835
AnnaBridge	189:f392fc9709a3	836
AnnaBridge	189:f392fc9709a3	837	/**
AnnaBridge	189:f392fc9709a3	838	* @}
AnnaBridge	189:f392fc9709a3	839	*/
AnnaBridge	189:f392fc9709a3	840
AnnaBridge	189:f392fc9709a3	841
AnnaBridge	189:f392fc9709a3	842	/** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source
AnnaBridge	189:f392fc9709a3	843	* @{
AnnaBridge	189:f392fc9709a3	844	*/
AnnaBridge	189:f392fc9709a3	845	#define RCC_SAI4ACLKSOURCE_PLL (0x00000000U)
AnnaBridge	189:f392fc9709a3	846	#define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0
AnnaBridge	189:f392fc9709a3	847	#define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1
AnnaBridge	189:f392fc9709a3	848	#define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 \| RCC_D3CCIPR_SAI4ASEL_1)
AnnaBridge	189:f392fc9709a3	849	#define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2
AnnaBridge	189:f392fc9709a3	850
AnnaBridge	189:f392fc9709a3	851
AnnaBridge	189:f392fc9709a3	852	/**
AnnaBridge	189:f392fc9709a3	853	* @}
AnnaBridge	189:f392fc9709a3	854	*/
AnnaBridge	189:f392fc9709a3	855
AnnaBridge	189:f392fc9709a3	856
AnnaBridge	189:f392fc9709a3	857	/** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source
AnnaBridge	189:f392fc9709a3	858	* @{
AnnaBridge	189:f392fc9709a3	859	*/
AnnaBridge	189:f392fc9709a3	860	#define RCC_SAI4BCLKSOURCE_PLL (0x00000000U)
AnnaBridge	189:f392fc9709a3	861	#define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0
AnnaBridge	189:f392fc9709a3	862	#define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1
AnnaBridge	189:f392fc9709a3	863	#define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 \| RCC_D3CCIPR_SAI4BSEL_1)
AnnaBridge	189:f392fc9709a3	864	#define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2
AnnaBridge	189:f392fc9709a3	865
AnnaBridge	189:f392fc9709a3	866	/**
AnnaBridge	189:f392fc9709a3	867	* @}
AnnaBridge	189:f392fc9709a3	868	*/
AnnaBridge	189:f392fc9709a3	869
AnnaBridge	189:f392fc9709a3	870
AnnaBridge	189:f392fc9709a3	871	/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
AnnaBridge	189:f392fc9709a3	872	* @{
AnnaBridge	189:f392fc9709a3	873	*/
AnnaBridge	189:f392fc9709a3	874	#define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	875	#define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0
AnnaBridge	189:f392fc9709a3	876	#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1
AnnaBridge	189:f392fc9709a3	877	#define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 \| RCC_D2CCIP2R_LPTIM1SEL_1)
AnnaBridge	189:f392fc9709a3	878	#define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2
AnnaBridge	189:f392fc9709a3	879	#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 \| RCC_D2CCIP2R_LPTIM1SEL_2)
AnnaBridge	189:f392fc9709a3	880
AnnaBridge	189:f392fc9709a3	881
AnnaBridge	189:f392fc9709a3	882	/**
AnnaBridge	189:f392fc9709a3	883	* @}
AnnaBridge	189:f392fc9709a3	884	*/
AnnaBridge	189:f392fc9709a3	885
AnnaBridge	189:f392fc9709a3	886	/** @defgroup RCCEx_LPTIM2_Clock_Source RCCEx LPTIM2 Clock Source
AnnaBridge	189:f392fc9709a3	887	* @{
AnnaBridge	189:f392fc9709a3	888	*/
AnnaBridge	189:f392fc9709a3	889	#define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	890	#define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0
AnnaBridge	189:f392fc9709a3	891	#define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1
AnnaBridge	189:f392fc9709a3	892	#define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 \| RCC_D3CCIPR_LPTIM2SEL_1)
AnnaBridge	189:f392fc9709a3	893	#define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2
AnnaBridge	189:f392fc9709a3	894	#define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 \| RCC_D3CCIPR_LPTIM2SEL_2)
AnnaBridge	189:f392fc9709a3	895
AnnaBridge	189:f392fc9709a3	896	/**
AnnaBridge	189:f392fc9709a3	897	* @}
AnnaBridge	189:f392fc9709a3	898	*/
AnnaBridge	189:f392fc9709a3	899
AnnaBridge	189:f392fc9709a3	900	/** @defgroup RCCEx_LPTIM345_Clock_Source RCCEx LPTIM3/4/5 Clock Source
AnnaBridge	189:f392fc9709a3	901	* @{
AnnaBridge	189:f392fc9709a3	902	*/
AnnaBridge	189:f392fc9709a3	903	#define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	904	#define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
AnnaBridge	189:f392fc9709a3	905	#define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
AnnaBridge	189:f392fc9709a3	906	#define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 \| RCC_D3CCIPR_LPTIM345SEL_1)
AnnaBridge	189:f392fc9709a3	907	#define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
AnnaBridge	189:f392fc9709a3	908	#define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 \| RCC_D3CCIPR_LPTIM345SEL_2)
AnnaBridge	189:f392fc9709a3	909
AnnaBridge	189:f392fc9709a3	910	/**
AnnaBridge	189:f392fc9709a3	911	* @}
AnnaBridge	189:f392fc9709a3	912	*/
AnnaBridge	189:f392fc9709a3	913
AnnaBridge	189:f392fc9709a3	914	/** @defgroup RCCEx_LPTIM3_Clock_Source RCCEx LPTIM3 Clock Source
AnnaBridge	189:f392fc9709a3	915	* @{
AnnaBridge	189:f392fc9709a3	916	*/
AnnaBridge	189:f392fc9709a3	917	#define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
AnnaBridge	189:f392fc9709a3	918	#define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	919	#define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	920	#define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	921	#define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	922	#define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
AnnaBridge	189:f392fc9709a3	923
AnnaBridge	189:f392fc9709a3	924	/**
AnnaBridge	189:f392fc9709a3	925	* @}
AnnaBridge	189:f392fc9709a3	926	*/
AnnaBridge	189:f392fc9709a3	927
AnnaBridge	189:f392fc9709a3	928	/** @defgroup RCCEx_LPTIM4_Clock_Source RCCEx LPTIM4 Clock Source
AnnaBridge	189:f392fc9709a3	929	* @{
AnnaBridge	189:f392fc9709a3	930	*/
AnnaBridge	189:f392fc9709a3	931	#define RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
AnnaBridge	189:f392fc9709a3	932	#define RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	933	#define RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	934	#define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	935	#define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	936	#define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
AnnaBridge	189:f392fc9709a3	937
AnnaBridge	189:f392fc9709a3	938	/**
AnnaBridge	189:f392fc9709a3	939	* @}
AnnaBridge	189:f392fc9709a3	940	*/
AnnaBridge	189:f392fc9709a3	941
AnnaBridge	189:f392fc9709a3	942	/** @defgroup RCCEx_LPTIM5_Clock_Source RCCEx LPTIM5 Clock Source
AnnaBridge	189:f392fc9709a3	943	* @{
AnnaBridge	189:f392fc9709a3	944	*/
AnnaBridge	189:f392fc9709a3	945	#define RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
AnnaBridge	189:f392fc9709a3	946	#define RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
AnnaBridge	189:f392fc9709a3	947	#define RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
AnnaBridge	189:f392fc9709a3	948	#define RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
AnnaBridge	189:f392fc9709a3	949	#define RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
AnnaBridge	189:f392fc9709a3	950	#define RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
AnnaBridge	189:f392fc9709a3	951
AnnaBridge	189:f392fc9709a3	952	/**
AnnaBridge	189:f392fc9709a3	953	* @}
AnnaBridge	189:f392fc9709a3	954	*/
AnnaBridge	189:f392fc9709a3	955
AnnaBridge	189:f392fc9709a3	956	/** @defgroup RCCEx_QSPI_Clock_Source RCCEx QSPI Clock Source
AnnaBridge	189:f392fc9709a3	957	* @{
AnnaBridge	189:f392fc9709a3	958	*/
AnnaBridge	189:f392fc9709a3	959	#define RCC_QSPICLKSOURCE_D1HCLK (0x00000000U)
AnnaBridge	189:f392fc9709a3	960	#define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0
AnnaBridge	189:f392fc9709a3	961	#define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1
AnnaBridge	189:f392fc9709a3	962	#define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL
AnnaBridge	189:f392fc9709a3	963
AnnaBridge	189:f392fc9709a3	964
AnnaBridge	189:f392fc9709a3	965
AnnaBridge	189:f392fc9709a3	966	/**
AnnaBridge	189:f392fc9709a3	967	* @}
AnnaBridge	189:f392fc9709a3	968	*/
AnnaBridge	189:f392fc9709a3	969
AnnaBridge	189:f392fc9709a3	970	/** @defgroup RCCEx_FMC_Clock_Source RCCEx FMC Clock Source
AnnaBridge	189:f392fc9709a3	971	* @{
AnnaBridge	189:f392fc9709a3	972	*/
AnnaBridge	189:f392fc9709a3	973	#define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U)
AnnaBridge	189:f392fc9709a3	974	#define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0
AnnaBridge	189:f392fc9709a3	975	#define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1
AnnaBridge	189:f392fc9709a3	976	#define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL
AnnaBridge	189:f392fc9709a3	977
AnnaBridge	189:f392fc9709a3	978	/**
AnnaBridge	189:f392fc9709a3	979	* @}
AnnaBridge	189:f392fc9709a3	980	*/
AnnaBridge	189:f392fc9709a3	981
AnnaBridge	189:f392fc9709a3	982	#if defined(FDCAN1) \|\| defined(FDCAN2)
AnnaBridge	189:f392fc9709a3	983	/** @defgroup RCCEx_FDCAN_Clock_Source RCCEx FDCAN Clock Source
AnnaBridge	189:f392fc9709a3	984	* @{
AnnaBridge	189:f392fc9709a3	985	*/
AnnaBridge	189:f392fc9709a3	986
AnnaBridge	189:f392fc9709a3	987	#define RCC_FDCANCLKSOURCE_HSE (0x00000000U)
AnnaBridge	189:f392fc9709a3	988	#define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0
AnnaBridge	189:f392fc9709a3	989	#define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1
AnnaBridge	189:f392fc9709a3	990
AnnaBridge	189:f392fc9709a3	991	/**
AnnaBridge	189:f392fc9709a3	992	* @}
AnnaBridge	189:f392fc9709a3	993	*/
AnnaBridge	189:f392fc9709a3	994	#endif /FDCAN1 \|\| FDCAN2/
AnnaBridge	189:f392fc9709a3	995
AnnaBridge	189:f392fc9709a3	996
AnnaBridge	189:f392fc9709a3	997	/** @defgroup RCCEx_SDMMC_Clock_Source RCCEx SDMMC Clock Source
AnnaBridge	189:f392fc9709a3	998	* @{
AnnaBridge	189:f392fc9709a3	999	*/
AnnaBridge	189:f392fc9709a3	1000
AnnaBridge	189:f392fc9709a3	1001	#define RCC_SDMMCCLKSOURCE_PLL (0x00000000U)
AnnaBridge	189:f392fc9709a3	1002	#define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL
AnnaBridge	189:f392fc9709a3	1003
AnnaBridge	189:f392fc9709a3	1004	/**
AnnaBridge	189:f392fc9709a3	1005	* @}
AnnaBridge	189:f392fc9709a3	1006	*/
AnnaBridge	189:f392fc9709a3	1007
AnnaBridge	189:f392fc9709a3	1008
AnnaBridge	189:f392fc9709a3	1009	/** @defgroup RCCEx_ADC_Clock_Source RCCEx ADC Clock Source
AnnaBridge	189:f392fc9709a3	1010	* @{
AnnaBridge	189:f392fc9709a3	1011	*/
AnnaBridge	189:f392fc9709a3	1012	#define RCC_ADCCLKSOURCE_PLL2 (0x00000000U)
AnnaBridge	189:f392fc9709a3	1013	#define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0
AnnaBridge	189:f392fc9709a3	1014	#define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1
AnnaBridge	189:f392fc9709a3	1015
AnnaBridge	189:f392fc9709a3	1016	/**
AnnaBridge	189:f392fc9709a3	1017	* @}
AnnaBridge	189:f392fc9709a3	1018	*/
AnnaBridge	189:f392fc9709a3	1019
AnnaBridge	189:f392fc9709a3	1020
AnnaBridge	189:f392fc9709a3	1021
AnnaBridge	189:f392fc9709a3	1022
AnnaBridge	189:f392fc9709a3	1023
AnnaBridge	189:f392fc9709a3	1024	/** @defgroup RCCEx_SWPMI1_Clock_Source RCCEx SWPMI1 Clock Source
AnnaBridge	189:f392fc9709a3	1025	* @{
AnnaBridge	189:f392fc9709a3	1026	*/
AnnaBridge	189:f392fc9709a3	1027	#define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	1028	#define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL
AnnaBridge	189:f392fc9709a3	1029
AnnaBridge	189:f392fc9709a3	1030	/**
AnnaBridge	189:f392fc9709a3	1031	* @}
AnnaBridge	189:f392fc9709a3	1032	*/
AnnaBridge	189:f392fc9709a3	1033
AnnaBridge	189:f392fc9709a3	1034	/** @defgroup RCCEx_DFSDM1_Clock_Source RCCEx DFSDM1 Clock Source
AnnaBridge	189:f392fc9709a3	1035	* @{
AnnaBridge	189:f392fc9709a3	1036	*/
AnnaBridge	189:f392fc9709a3	1037	#define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	189:f392fc9709a3	1038	#define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL
AnnaBridge	189:f392fc9709a3	1039
AnnaBridge	189:f392fc9709a3	1040
AnnaBridge	189:f392fc9709a3	1041	/**
AnnaBridge	189:f392fc9709a3	1042	* @}
AnnaBridge	189:f392fc9709a3	1043	*/
AnnaBridge	189:f392fc9709a3	1044
AnnaBridge	189:f392fc9709a3	1045	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCCEx SPDIFRX Clock Source
AnnaBridge	189:f392fc9709a3	1046	* @{
AnnaBridge	189:f392fc9709a3	1047	*/
AnnaBridge	189:f392fc9709a3	1048	#define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)
AnnaBridge	189:f392fc9709a3	1049	#define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0
AnnaBridge	189:f392fc9709a3	1050	#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1
AnnaBridge	189:f392fc9709a3	1051	#define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL
AnnaBridge	189:f392fc9709a3	1052
AnnaBridge	189:f392fc9709a3	1053	/**
AnnaBridge	189:f392fc9709a3	1054	* @}
AnnaBridge	189:f392fc9709a3	1055	*/
AnnaBridge	189:f392fc9709a3	1056
AnnaBridge	189:f392fc9709a3	1057	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
AnnaBridge	189:f392fc9709a3	1058	* @{
AnnaBridge	189:f392fc9709a3	1059	*/
AnnaBridge	189:f392fc9709a3	1060	#define RCC_CECCLKSOURCE_LSE (0x00000000U)
AnnaBridge	189:f392fc9709a3	1061	#define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0
AnnaBridge	189:f392fc9709a3	1062	#define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1
AnnaBridge	189:f392fc9709a3	1063
AnnaBridge	189:f392fc9709a3	1064	/**
AnnaBridge	189:f392fc9709a3	1065	* @}
AnnaBridge	189:f392fc9709a3	1066	*/
AnnaBridge	189:f392fc9709a3	1067
AnnaBridge	189:f392fc9709a3	1068
AnnaBridge	189:f392fc9709a3	1069	/** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source
AnnaBridge	189:f392fc9709a3	1070	* @{
AnnaBridge	189:f392fc9709a3	1071	*/
AnnaBridge	189:f392fc9709a3	1072	#define RCC_CLKPSOURCE_HSI (0x00000000U)
AnnaBridge	189:f392fc9709a3	1073	#define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0
AnnaBridge	189:f392fc9709a3	1074	#define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1
AnnaBridge	189:f392fc9709a3	1075
AnnaBridge	189:f392fc9709a3	1076	/**
AnnaBridge	189:f392fc9709a3	1077	* @}
AnnaBridge	189:f392fc9709a3	1078	*/
AnnaBridge	189:f392fc9709a3	1079
AnnaBridge	189:f392fc9709a3	1080	/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
AnnaBridge	189:f392fc9709a3	1081	* @{
AnnaBridge	189:f392fc9709a3	1082	*/
AnnaBridge	189:f392fc9709a3	1083	#define RCC_TIMPRES_DESACTIVATED (0x00000000U)
AnnaBridge	189:f392fc9709a3	1084	#define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE
AnnaBridge	189:f392fc9709a3	1085
AnnaBridge	189:f392fc9709a3	1086	/**
AnnaBridge	189:f392fc9709a3	1087	* @}
AnnaBridge	189:f392fc9709a3	1088	*/
AnnaBridge	189:f392fc9709a3	1089
AnnaBridge	189:f392fc9709a3	1090
AnnaBridge	189:f392fc9709a3	1091	/** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx
AnnaBridge	189:f392fc9709a3	1092	* @{
AnnaBridge	189:f392fc9709a3	1093	*/
AnnaBridge	189:f392fc9709a3	1094	#define RCC_WWDG1 RCC_GCR_WW1RSC
AnnaBridge	189:f392fc9709a3	1095
AnnaBridge	189:f392fc9709a3	1096	/**
AnnaBridge	189:f392fc9709a3	1097	* @}
AnnaBridge	189:f392fc9709a3	1098	*/
AnnaBridge	189:f392fc9709a3	1099
AnnaBridge	189:f392fc9709a3	1100	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
AnnaBridge	189:f392fc9709a3	1101	* @{
AnnaBridge	189:f392fc9709a3	1102	*/
AnnaBridge	189:f392fc9709a3	1103	#define RCC_CRS_NONE (0x00000000U)
AnnaBridge	189:f392fc9709a3	1104	#define RCC_CRS_TIMEOUT (0x00000001U)
AnnaBridge	189:f392fc9709a3	1105	#define RCC_CRS_SYNCOK (0x00000002U)
AnnaBridge	189:f392fc9709a3	1106	#define RCC_CRS_SYNCWARN (0x00000004U)
AnnaBridge	189:f392fc9709a3	1107	#define RCC_CRS_SYNCERR (0x00000008U)
AnnaBridge	189:f392fc9709a3	1108	#define RCC_CRS_SYNCMISS (0x00000010U)
AnnaBridge	189:f392fc9709a3	1109	#define RCC_CRS_TRIMOVF (0x00000020U)
AnnaBridge	189:f392fc9709a3	1110	/**
AnnaBridge	189:f392fc9709a3	1111	* @}
AnnaBridge	189:f392fc9709a3	1112	*/
AnnaBridge	189:f392fc9709a3	1113
AnnaBridge	189:f392fc9709a3	1114	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
AnnaBridge	189:f392fc9709a3	1115	* @{
AnnaBridge	189:f392fc9709a3	1116	*/
AnnaBridge	189:f392fc9709a3	1117	#define RCC_CRS_SYNC_SOURCE_USB2 (0x00000000U) /!< Synchro Signal source USB2 SOF /
AnnaBridge	189:f392fc9709a3	1118	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
AnnaBridge	189:f392fc9709a3	1119	#define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB1 SOF (default) /
AnnaBridge	189:f392fc9709a3	1120
AnnaBridge	189:f392fc9709a3	1121
AnnaBridge	189:f392fc9709a3	1122
AnnaBridge	189:f392fc9709a3	1123	/**
AnnaBridge	189:f392fc9709a3	1124	* @}
AnnaBridge	189:f392fc9709a3	1125	*/
AnnaBridge	189:f392fc9709a3	1126
AnnaBridge	189:f392fc9709a3	1127	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
AnnaBridge	189:f392fc9709a3	1128	* @{
AnnaBridge	189:f392fc9709a3	1129	*/
AnnaBridge	189:f392fc9709a3	1130	#define RCC_CRS_SYNC_DIV1 (0x00000000U) /!< Synchro Signal not divided (default) /
AnnaBridge	189:f392fc9709a3	1131	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
AnnaBridge	189:f392fc9709a3	1132	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
AnnaBridge	189:f392fc9709a3	1133	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
AnnaBridge	189:f392fc9709a3	1134	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
AnnaBridge	189:f392fc9709a3	1135	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
AnnaBridge	189:f392fc9709a3	1136	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
AnnaBridge	189:f392fc9709a3	1137	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
AnnaBridge	189:f392fc9709a3	1138	/**
AnnaBridge	189:f392fc9709a3	1139	* @}
AnnaBridge	189:f392fc9709a3	1140	*/
AnnaBridge	189:f392fc9709a3	1141
AnnaBridge	189:f392fc9709a3	1142	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
AnnaBridge	189:f392fc9709a3	1143	* @{
AnnaBridge	189:f392fc9709a3	1144	*/
AnnaBridge	189:f392fc9709a3	1145	#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /!< Synchro Active on rising edge (default) /
AnnaBridge	189:f392fc9709a3	1146	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
AnnaBridge	189:f392fc9709a3	1147	/**
AnnaBridge	189:f392fc9709a3	1148	* @}
AnnaBridge	189:f392fc9709a3	1149	*/
AnnaBridge	189:f392fc9709a3	1150
AnnaBridge	189:f392fc9709a3	1151	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
AnnaBridge	189:f392fc9709a3	1152	* @{
AnnaBridge	189:f392fc9709a3	1153	*/
AnnaBridge	189:f392fc9709a3	1154	#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
AnnaBridge	189:f392fc9709a3	1155	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
AnnaBridge	189:f392fc9709a3	1156	/**
AnnaBridge	189:f392fc9709a3	1157	* @}
AnnaBridge	189:f392fc9709a3	1158	*/
AnnaBridge	189:f392fc9709a3	1159
AnnaBridge	189:f392fc9709a3	1160	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
AnnaBridge	189:f392fc9709a3	1161	* @{
AnnaBridge	189:f392fc9709a3	1162	*/
AnnaBridge	189:f392fc9709a3	1163	#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /!< Default Frequency error limit /
AnnaBridge	189:f392fc9709a3	1164	/**
AnnaBridge	189:f392fc9709a3	1165	* @}
AnnaBridge	189:f392fc9709a3	1166	*/
AnnaBridge	189:f392fc9709a3	1167
AnnaBridge	189:f392fc9709a3	1168	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
AnnaBridge	189:f392fc9709a3	1169	* @{
AnnaBridge	189:f392fc9709a3	1170	*/
AnnaBridge	189:f392fc9709a3	1171	#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
AnnaBridge	189:f392fc9709a3	1172	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
AnnaBridge	189:f392fc9709a3	1173	corresponds to a higher output frequency */
AnnaBridge	189:f392fc9709a3	1174	/**
AnnaBridge	189:f392fc9709a3	1175	* @}
AnnaBridge	189:f392fc9709a3	1176	*/
AnnaBridge	189:f392fc9709a3	1177
AnnaBridge	189:f392fc9709a3	1178	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
AnnaBridge	189:f392fc9709a3	1179	* @{
AnnaBridge	189:f392fc9709a3	1180	*/
AnnaBridge	189:f392fc9709a3	1181	#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /!< Upcounting direction, the actual frequency is above the target /
AnnaBridge	189:f392fc9709a3	1182	#define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
AnnaBridge	189:f392fc9709a3	1183	/**
AnnaBridge	189:f392fc9709a3	1184	* @}
AnnaBridge	189:f392fc9709a3	1185	*/
AnnaBridge	189:f392fc9709a3	1186
AnnaBridge	189:f392fc9709a3	1187	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
AnnaBridge	189:f392fc9709a3	1188	* @{
AnnaBridge	189:f392fc9709a3	1189	*/
AnnaBridge	189:f392fc9709a3	1190	#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /!< SYNC event OK /
AnnaBridge	189:f392fc9709a3	1191	#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /!< SYNC warning /
AnnaBridge	189:f392fc9709a3	1192	#define RCC_CRS_IT_ERR CRS_CR_ERRIE /!< Error /
AnnaBridge	189:f392fc9709a3	1193	#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /!< Expected SYNC /
AnnaBridge	189:f392fc9709a3	1194	#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /!< SYNC error /
AnnaBridge	189:f392fc9709a3	1195	#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /!< SYNC missed /
AnnaBridge	189:f392fc9709a3	1196	#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /!< Trimming overflow or underflow /
AnnaBridge	189:f392fc9709a3	1197
AnnaBridge	189:f392fc9709a3	1198	/**
AnnaBridge	189:f392fc9709a3	1199	* @}
AnnaBridge	189:f392fc9709a3	1200	*/
AnnaBridge	189:f392fc9709a3	1201
AnnaBridge	189:f392fc9709a3	1202	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
AnnaBridge	189:f392fc9709a3	1203	* @{
AnnaBridge	189:f392fc9709a3	1204	*/
AnnaBridge	189:f392fc9709a3	1205	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK flag /
AnnaBridge	189:f392fc9709a3	1206	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning flag /
AnnaBridge	189:f392fc9709a3	1207	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /!< Error flag /
AnnaBridge	189:f392fc9709a3	1208	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC flag /
AnnaBridge	189:f392fc9709a3	1209	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
AnnaBridge	189:f392fc9709a3	1210	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
AnnaBridge	189:f392fc9709a3	1211	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
AnnaBridge	189:f392fc9709a3	1212
AnnaBridge	189:f392fc9709a3	1213	/**
AnnaBridge	189:f392fc9709a3	1214	* @}
AnnaBridge	189:f392fc9709a3	1215	*/
AnnaBridge	189:f392fc9709a3	1216
AnnaBridge	189:f392fc9709a3	1217	/**
AnnaBridge	189:f392fc9709a3	1218	* @}
AnnaBridge	189:f392fc9709a3	1219	*/
AnnaBridge	189:f392fc9709a3	1220
AnnaBridge	189:f392fc9709a3	1221
AnnaBridge	189:f392fc9709a3	1222
AnnaBridge	189:f392fc9709a3	1223	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1224	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge	189:f392fc9709a3	1225	* @{
AnnaBridge	189:f392fc9709a3	1226	*/
AnnaBridge	189:f392fc9709a3	1227
AnnaBridge	189:f392fc9709a3	1228	/** @brief Macros to enable or disable PLL2.
AnnaBridge	189:f392fc9709a3	1229	* @note After enabling PLL2, the application software should wait on
AnnaBridge	189:f392fc9709a3	1230	* PLL2RDY flag to be set indicating that PLL2 clock is stable and can
AnnaBridge	189:f392fc9709a3	1231	* be used as kernel clock source.
AnnaBridge	189:f392fc9709a3	1232	* @note PLL2 is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	189:f392fc9709a3	1233	*/
AnnaBridge	189:f392fc9709a3	1234	#define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
AnnaBridge	189:f392fc9709a3	1235	#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
AnnaBridge	189:f392fc9709a3	1236
AnnaBridge	189:f392fc9709a3	1237	/**
AnnaBridge	189:f392fc9709a3	1238	* @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
AnnaBridge	189:f392fc9709a3	1239	* @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled,
AnnaBridge	189:f392fc9709a3	1240	* This is mainly used to save Power.
AnnaBridge	189:f392fc9709a3	1241	* @param __RCC_PLL2ClockOut__: Specifies the PLL2 clock to be outputted
AnnaBridge	189:f392fc9709a3	1242	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1243	* @arg RCC_PLL2_DIVP: This clock is used to generate system clock (up to 400MHZ)
AnnaBridge	189:f392fc9709a3	1244	* @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
AnnaBridge	189:f392fc9709a3	1245	* @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
AnnaBridge	189:f392fc9709a3	1246	* @retval None
AnnaBridge	189:f392fc9709a3	1247	*/
AnnaBridge	189:f392fc9709a3	1248	#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
AnnaBridge	189:f392fc9709a3	1249
AnnaBridge	189:f392fc9709a3	1250	#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
AnnaBridge	189:f392fc9709a3	1251
AnnaBridge	189:f392fc9709a3	1252	/**
AnnaBridge	189:f392fc9709a3	1253	* @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
AnnaBridge	189:f392fc9709a3	1254	* @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2
AnnaBridge	189:f392fc9709a3	1255	* @retval None
AnnaBridge	189:f392fc9709a3	1256	*/
AnnaBridge	189:f392fc9709a3	1257	#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
AnnaBridge	189:f392fc9709a3	1258
AnnaBridge	189:f392fc9709a3	1259	#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
AnnaBridge	189:f392fc9709a3	1260
AnnaBridge	189:f392fc9709a3	1261	/**
AnnaBridge	189:f392fc9709a3	1262	* @brief Macro to configures the PLL2 multiplication and division factors.
AnnaBridge	189:f392fc9709a3	1263	* @note This function must be used only when PLL2 is disabled.
AnnaBridge	189:f392fc9709a3	1264	*
AnnaBridge	189:f392fc9709a3	1265	* @param __PLL2M__: specifies the division factor for PLL2 VCO input clock
AnnaBridge	189:f392fc9709a3	1266	* This parameter must be a number between 1 and 63.
AnnaBridge	189:f392fc9709a3	1267	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	189:f392fc9709a3	1268	* frequency ranges from 1 to 16 MHz.
AnnaBridge	189:f392fc9709a3	1269	*
AnnaBridge	189:f392fc9709a3	1270	* @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock
AnnaBridge	189:f392fc9709a3	1271	* This parameter must be a number between 4 and 512.
AnnaBridge	189:f392fc9709a3	1272	* @note You have to set the PLL2N parameter correctly to ensure that the VCO
AnnaBridge	189:f392fc9709a3	1273	* output frequency is between 150 and 420 MHz (when in medium VCO range) or
AnnaBridge	189:f392fc9709a3	1274	* between 192 and 836 MHZ (when in wide VCO range)
AnnaBridge	189:f392fc9709a3	1275	*
AnnaBridge	189:f392fc9709a3	1276	* @param __PLL2P__: specifies the division factor for peripheral kernel clocks
AnnaBridge	189:f392fc9709a3	1277	* This parameter must be a number between 2 and 128 (where odd numbers not allowed)
AnnaBridge	189:f392fc9709a3	1278	*
AnnaBridge	189:f392fc9709a3	1279	* @param __PLL2Q__: specifies the division factor for peripheral kernel clocks
AnnaBridge	189:f392fc9709a3	1280	* This parameter must be a number between 1 and 128
AnnaBridge	189:f392fc9709a3	1281	*
AnnaBridge	189:f392fc9709a3	1282	* @param __PLL2R__: specifies the division factor for peripheral kernel clocks
AnnaBridge	189:f392fc9709a3	1283	* This parameter must be a number between 1 and 128
AnnaBridge	189:f392fc9709a3	1284	*
AnnaBridge	189:f392fc9709a3	1285	* @retval None
AnnaBridge	189:f392fc9709a3	1286	*/
AnnaBridge	189:f392fc9709a3	1287
AnnaBridge	189:f392fc9709a3	1288
AnnaBridge	189:f392fc9709a3	1289	#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
AnnaBridge	189:f392fc9709a3	1290	do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \
AnnaBridge	189:f392fc9709a3	1291	WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) \| ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) \| \
AnnaBridge	189:f392fc9709a3	1292	((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) \| ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
AnnaBridge	189:f392fc9709a3	1293	} while(0)
AnnaBridge	189:f392fc9709a3	1294	/**
AnnaBridge	189:f392fc9709a3	1295	* @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor
AnnaBridge	189:f392fc9709a3	1296	*
AnnaBridge	189:f392fc9709a3	1297	* @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
AnnaBridge	189:f392fc9709a3	1298	*
AnnaBridge	189:f392fc9709a3	1299	* @param __RCC_PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
AnnaBridge	189:f392fc9709a3	1300	* It should be a value between 0 and 8191
AnnaBridge	189:f392fc9709a3	1301	* @note Warning: the software has to set correctly these bits to insure that the VCO
AnnaBridge	189:f392fc9709a3	1302	* output frequency is between its valid frequency range, which is:
AnnaBridge	189:f392fc9709a3	1303	* 192 to 836 MHz if PLL2VCOSEL = 0
AnnaBridge	189:f392fc9709a3	1304	* 150 to 420 MHz if PLL2VCOSEL = 1.
AnnaBridge	189:f392fc9709a3	1305	*
AnnaBridge	189:f392fc9709a3	1306	*
AnnaBridge	189:f392fc9709a3	1307	* @retval None
AnnaBridge	189:f392fc9709a3	1308	*/
AnnaBridge	189:f392fc9709a3	1309	#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)
AnnaBridge	189:f392fc9709a3	1310
AnnaBridge	189:f392fc9709a3	1311	/** @brief Macro to select the PLL2 reference frequency range.
AnnaBridge	189:f392fc9709a3	1312	* @param __RCC_PLL2VCIRange__: specifies the PLL2 input frequency range
AnnaBridge	189:f392fc9709a3	1313	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1314	* @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
AnnaBridge	189:f392fc9709a3	1315	* @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
AnnaBridge	189:f392fc9709a3	1316	* @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
AnnaBridge	189:f392fc9709a3	1317	* @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
AnnaBridge	189:f392fc9709a3	1318	* @retval None
AnnaBridge	189:f392fc9709a3	1319	*/
AnnaBridge	189:f392fc9709a3	1320	#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
AnnaBridge	189:f392fc9709a3	1321	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
AnnaBridge	189:f392fc9709a3	1322
AnnaBridge	189:f392fc9709a3	1323
AnnaBridge	189:f392fc9709a3	1324	/** @brief Macro to select the PLL2 reference frequency range.
AnnaBridge	189:f392fc9709a3	1325	* @param __RCC_PLL2VCORange__: Specifies the PLL2 input frequency range
AnnaBridge	189:f392fc9709a3	1326	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1327	* @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz
AnnaBridge	189:f392fc9709a3	1328	* @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
AnnaBridge	189:f392fc9709a3	1329	* @retval None
AnnaBridge	189:f392fc9709a3	1330	*/
AnnaBridge	189:f392fc9709a3	1331	#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
AnnaBridge	189:f392fc9709a3	1332	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
AnnaBridge	189:f392fc9709a3	1333
AnnaBridge	189:f392fc9709a3	1334	/** @brief Macros to enable or disable the main PLL3.
AnnaBridge	189:f392fc9709a3	1335	* @note After enabling PLL3, the application software should wait on
AnnaBridge	189:f392fc9709a3	1336	* PLL3RDY flag to be set indicating that PLL3 clock is stable and can
AnnaBridge	189:f392fc9709a3	1337	* be used as kernel clock source.
AnnaBridge	189:f392fc9709a3	1338	* @note PLL3 is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	189:f392fc9709a3	1339	*/
AnnaBridge	189:f392fc9709a3	1340	#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
AnnaBridge	189:f392fc9709a3	1341	#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
AnnaBridge	189:f392fc9709a3	1342
AnnaBridge	189:f392fc9709a3	1343	/**
AnnaBridge	189:f392fc9709a3	1344	* @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
AnnaBridge	189:f392fc9709a3	1345	* @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3
AnnaBridge	189:f392fc9709a3	1346	* @retval None
AnnaBridge	189:f392fc9709a3	1347	*/
AnnaBridge	189:f392fc9709a3	1348	#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
AnnaBridge	189:f392fc9709a3	1349
AnnaBridge	189:f392fc9709a3	1350	#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
AnnaBridge	189:f392fc9709a3	1351
AnnaBridge	189:f392fc9709a3	1352	/**
AnnaBridge	189:f392fc9709a3	1353	* @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
AnnaBridge	189:f392fc9709a3	1354	* @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled,
AnnaBridge	189:f392fc9709a3	1355	* This is mainly used to save Power.
AnnaBridge	189:f392fc9709a3	1356	* @param __RCC_PLL3ClockOut__: specifies the PLL3 clock to be outputted
AnnaBridge	189:f392fc9709a3	1357	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1358	* @arg RCC_PLL3_DIVP: This clock is used to generate system clock (up to 400MHZ)
AnnaBridge	189:f392fc9709a3	1359	* @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
AnnaBridge	189:f392fc9709a3	1360	* @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
AnnaBridge	189:f392fc9709a3	1361	* @retval None
AnnaBridge	189:f392fc9709a3	1362	*/
AnnaBridge	189:f392fc9709a3	1363	#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
AnnaBridge	189:f392fc9709a3	1364
AnnaBridge	189:f392fc9709a3	1365	#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
AnnaBridge	189:f392fc9709a3	1366
AnnaBridge	189:f392fc9709a3	1367	/**
AnnaBridge	189:f392fc9709a3	1368	* @brief Macro to configures the PLL3 multiplication and division factors.
AnnaBridge	189:f392fc9709a3	1369	* @note This function must be used only when PLL3 is disabled.
AnnaBridge	189:f392fc9709a3	1370	*
AnnaBridge	189:f392fc9709a3	1371	* @param __PLL3M__: specifies the division factor for PLL3 VCO input clock
AnnaBridge	189:f392fc9709a3	1372	* This parameter must be a number between 1 and 63.
AnnaBridge	189:f392fc9709a3	1373	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	189:f392fc9709a3	1374	* frequency ranges from 1 to 16 MHz.
AnnaBridge	189:f392fc9709a3	1375	*
AnnaBridge	189:f392fc9709a3	1376	* @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock
AnnaBridge	189:f392fc9709a3	1377	* This parameter must be a number between 4 and 512.
AnnaBridge	189:f392fc9709a3	1378	* @note You have to set the PLL3N parameter correctly to ensure that the VCO
AnnaBridge	189:f392fc9709a3	1379	* output frequency is between 150 and 420 MHz (when in medium VCO range) or
AnnaBridge	189:f392fc9709a3	1380	* between 192 and 836 MHZ (when in wide VCO range)
AnnaBridge	189:f392fc9709a3	1381	*
AnnaBridge	189:f392fc9709a3	1382	* @param __PLL3P__: specifies the division factor for peripheral kernel clocks
AnnaBridge	189:f392fc9709a3	1383	* This parameter must be a number between 2 and 128 (where odd numbers not allowed)
AnnaBridge	189:f392fc9709a3	1384	*
AnnaBridge	189:f392fc9709a3	1385	* @param __PLL3Q__: specifies the division factor for peripheral kernel clocks
AnnaBridge	189:f392fc9709a3	1386	* This parameter must be a number between 1 and 128
AnnaBridge	189:f392fc9709a3	1387	*
AnnaBridge	189:f392fc9709a3	1388	* @param __PLL3R__: specifies the division factor for peripheral kernel clocks
AnnaBridge	189:f392fc9709a3	1389	* This parameter must be a number between 1 and 128
AnnaBridge	189:f392fc9709a3	1390	*
AnnaBridge	189:f392fc9709a3	1391	* @retval None
AnnaBridge	189:f392fc9709a3	1392	*/
AnnaBridge	189:f392fc9709a3	1393
AnnaBridge	189:f392fc9709a3	1394	#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
AnnaBridge	189:f392fc9709a3	1395	do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \
AnnaBridge	189:f392fc9709a3	1396	WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) \| ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) \| \
AnnaBridge	189:f392fc9709a3	1397	((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) \| ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
AnnaBridge	189:f392fc9709a3	1398	} while(0)
AnnaBridge	189:f392fc9709a3	1399
AnnaBridge	189:f392fc9709a3	1400
AnnaBridge	189:f392fc9709a3	1401
AnnaBridge	189:f392fc9709a3	1402	/**
AnnaBridge	189:f392fc9709a3	1403	* @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor
AnnaBridge	189:f392fc9709a3	1404	*
AnnaBridge	189:f392fc9709a3	1405	* @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
AnnaBridge	189:f392fc9709a3	1406	*
AnnaBridge	189:f392fc9709a3	1407	* @param __RCC_PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
AnnaBridge	189:f392fc9709a3	1408	* It should be a value between 0 and 8191
AnnaBridge	189:f392fc9709a3	1409	* @note Warning: the software has to set correctly these bits to insure that the VCO
AnnaBridge	189:f392fc9709a3	1410	* output frequency is between its valid frequency range, which is:
AnnaBridge	189:f392fc9709a3	1411	* 192 to 836 MHz if PLL3VCOSEL = 0
AnnaBridge	189:f392fc9709a3	1412	* 150 to 420 MHz if PLL3VCOSEL = 1.
AnnaBridge	189:f392fc9709a3	1413	*
AnnaBridge	189:f392fc9709a3	1414	*
AnnaBridge	189:f392fc9709a3	1415	* @retval None
AnnaBridge	189:f392fc9709a3	1416	*/
AnnaBridge	189:f392fc9709a3	1417	#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
AnnaBridge	189:f392fc9709a3	1418
AnnaBridge	189:f392fc9709a3	1419	/** @brief Macro to select the PLL3 reference frequency range.
AnnaBridge	189:f392fc9709a3	1420	* @param __RCC_PLL3VCIRange__: specifies the PLL1 input frequency range
AnnaBridge	189:f392fc9709a3	1421	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1422	* @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
AnnaBridge	189:f392fc9709a3	1423	* @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
AnnaBridge	189:f392fc9709a3	1424	* @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
AnnaBridge	189:f392fc9709a3	1425	* @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
AnnaBridge	189:f392fc9709a3	1426	* @retval None
AnnaBridge	189:f392fc9709a3	1427	*/
AnnaBridge	189:f392fc9709a3	1428	#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
AnnaBridge	189:f392fc9709a3	1429	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
AnnaBridge	189:f392fc9709a3	1430
AnnaBridge	189:f392fc9709a3	1431
AnnaBridge	189:f392fc9709a3	1432	/** @brief Macro to select the PLL3 reference frequency range.
AnnaBridge	189:f392fc9709a3	1433	* @param __RCC_PLL3VCORange__: specifies the PLL1 input frequency range
AnnaBridge	189:f392fc9709a3	1434	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1435	* @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz
AnnaBridge	189:f392fc9709a3	1436	* @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
AnnaBridge	189:f392fc9709a3	1437	* @retval None
AnnaBridge	189:f392fc9709a3	1438	*/
AnnaBridge	189:f392fc9709a3	1439	#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
AnnaBridge	189:f392fc9709a3	1440	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
AnnaBridge	189:f392fc9709a3	1441	/**
AnnaBridge	189:f392fc9709a3	1442	* @brief Macro to Configure the SAI1 clock source.
AnnaBridge	189:f392fc9709a3	1443	* @param __RCC_SAI1CLKSource__: defines the SAI1 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	1444	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	189:f392fc9709a3	1445	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1446	* @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
AnnaBridge	189:f392fc9709a3	1447	* @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
AnnaBridge	189:f392fc9709a3	1448	* @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
AnnaBridge	189:f392fc9709a3	1449	* @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC
AnnaBridge	189:f392fc9709a3	1450	* @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
AnnaBridge	189:f392fc9709a3	1451	* @retval None
AnnaBridge	189:f392fc9709a3	1452	*/
AnnaBridge	189:f392fc9709a3	1453	#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
AnnaBridge	189:f392fc9709a3	1454	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
AnnaBridge	189:f392fc9709a3	1455
AnnaBridge	189:f392fc9709a3	1456	/** @brief Macro to get the SAI1 clock source.
AnnaBridge	189:f392fc9709a3	1457	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1458	* @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
AnnaBridge	189:f392fc9709a3	1459	* @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
AnnaBridge	189:f392fc9709a3	1460	* @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
AnnaBridge	189:f392fc9709a3	1461	* @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP
AnnaBridge	189:f392fc9709a3	1462	* @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
AnnaBridge	189:f392fc9709a3	1463	*/
AnnaBridge	189:f392fc9709a3	1464	#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
AnnaBridge	189:f392fc9709a3	1465
AnnaBridge	189:f392fc9709a3	1466	/**
AnnaBridge	189:f392fc9709a3	1467	* @brief Macro to Configure the SPDIFRX clock source.
AnnaBridge	189:f392fc9709a3	1468	* @param __RCC_SPDIFCLKSource__: defines the SPDIFRX clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	1469	* from system PLL, PLL2, PLL3, or internal OSC clock
AnnaBridge	189:f392fc9709a3	1470	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1471	* @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL
AnnaBridge	189:f392fc9709a3	1472	* @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
AnnaBridge	189:f392fc9709a3	1473	* @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
AnnaBridge	189:f392fc9709a3	1474	* @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI
AnnaBridge	189:f392fc9709a3	1475	* @retval None
AnnaBridge	189:f392fc9709a3	1476	*/
AnnaBridge	189:f392fc9709a3	1477	#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
AnnaBridge	189:f392fc9709a3	1478	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
AnnaBridge	189:f392fc9709a3	1479	/**
AnnaBridge	189:f392fc9709a3	1480	* @brief Macro to get the SPDIFRX clock source.
AnnaBridge	189:f392fc9709a3	1481	* @retval None
AnnaBridge	189:f392fc9709a3	1482	*/
AnnaBridge	189:f392fc9709a3	1483	#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
AnnaBridge	189:f392fc9709a3	1484
AnnaBridge	189:f392fc9709a3	1485	/**
AnnaBridge	189:f392fc9709a3	1486	* @brief Macro to Configure the SAI2/3 clock source.
AnnaBridge	189:f392fc9709a3	1487	* @param __RCC_SAI23CLKSource__: defines the SAI2/3 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	1488	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	189:f392fc9709a3	1489	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1490	* @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
AnnaBridge	189:f392fc9709a3	1491	* @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
AnnaBridge	189:f392fc9709a3	1492	* @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
AnnaBridge	189:f392fc9709a3	1493	* @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP
AnnaBridge	189:f392fc9709a3	1494	* @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
AnnaBridge	189:f392fc9709a3	1495	* @retval None
AnnaBridge	189:f392fc9709a3	1496	*/
AnnaBridge	189:f392fc9709a3	1497	#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
AnnaBridge	189:f392fc9709a3	1498	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
AnnaBridge	189:f392fc9709a3	1499
AnnaBridge	189:f392fc9709a3	1500	/** @brief Macro to get the SAI2/3 clock source.
AnnaBridge	189:f392fc9709a3	1501	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1502	* @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
AnnaBridge	189:f392fc9709a3	1503	* @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
AnnaBridge	189:f392fc9709a3	1504	* @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
AnnaBridge	189:f392fc9709a3	1505	* @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP
AnnaBridge	189:f392fc9709a3	1506	* @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
AnnaBridge	189:f392fc9709a3	1507	*/
AnnaBridge	189:f392fc9709a3	1508	#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
AnnaBridge	189:f392fc9709a3	1509
AnnaBridge	189:f392fc9709a3	1510	/**
AnnaBridge	189:f392fc9709a3	1511	* @brief Macro to Configure the SAI2 clock source.
AnnaBridge	189:f392fc9709a3	1512	* @param __RCC_SAI2CLKSource__: defines the SAI2 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	1513	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	189:f392fc9709a3	1514	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1515	* @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
AnnaBridge	189:f392fc9709a3	1516	* @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
AnnaBridge	189:f392fc9709a3	1517	* @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
AnnaBridge	189:f392fc9709a3	1518	* @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP
AnnaBridge	189:f392fc9709a3	1519	* @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
AnnaBridge	189:f392fc9709a3	1520	* @retval None
AnnaBridge	189:f392fc9709a3	1521	*/
AnnaBridge	189:f392fc9709a3	1522	#define __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__ )\
AnnaBridge	189:f392fc9709a3	1523	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__))
AnnaBridge	189:f392fc9709a3	1524
AnnaBridge	189:f392fc9709a3	1525	/** @brief Macro to get the SAI2 clock source.
AnnaBridge	189:f392fc9709a3	1526	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1527	* @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
AnnaBridge	189:f392fc9709a3	1528	* @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
AnnaBridge	189:f392fc9709a3	1529	* @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
AnnaBridge	189:f392fc9709a3	1530	* @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP
AnnaBridge	189:f392fc9709a3	1531	* @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
AnnaBridge	189:f392fc9709a3	1532	*/
AnnaBridge	189:f392fc9709a3	1533	#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
AnnaBridge	189:f392fc9709a3	1534
AnnaBridge	189:f392fc9709a3	1535	/**
AnnaBridge	189:f392fc9709a3	1536	* @brief Macro to Configure the SAI3 clock source.
AnnaBridge	189:f392fc9709a3	1537	* @param __RCC_SAI3CLKSource__: defines the SAI3 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	1538	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	189:f392fc9709a3	1539	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1540	* @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
AnnaBridge	189:f392fc9709a3	1541	* @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
AnnaBridge	189:f392fc9709a3	1542	* @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
AnnaBridge	189:f392fc9709a3	1543	* @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP
AnnaBridge	189:f392fc9709a3	1544	* @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
AnnaBridge	189:f392fc9709a3	1545	* @retval None
AnnaBridge	189:f392fc9709a3	1546	*/
AnnaBridge	189:f392fc9709a3	1547	#define __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__ )\
AnnaBridge	189:f392fc9709a3	1548	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__))
AnnaBridge	189:f392fc9709a3	1549
AnnaBridge	189:f392fc9709a3	1550	/** @brief Macro to get the SAI3 clock source.
AnnaBridge	189:f392fc9709a3	1551	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1552	* @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
AnnaBridge	189:f392fc9709a3	1553	* @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
AnnaBridge	189:f392fc9709a3	1554	* @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
AnnaBridge	189:f392fc9709a3	1555	* @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP
AnnaBridge	189:f392fc9709a3	1556	* @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
AnnaBridge	189:f392fc9709a3	1557	*/
AnnaBridge	189:f392fc9709a3	1558	#define __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
AnnaBridge	189:f392fc9709a3	1559
AnnaBridge	189:f392fc9709a3	1560	/**
AnnaBridge	189:f392fc9709a3	1561	* @brief Macro to Configure the SAI4A clock source.
AnnaBridge	189:f392fc9709a3	1562	* @param __RCC_SAI4ACLKSource__: defines the SAI4A clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	1563	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	189:f392fc9709a3	1564	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1565	* @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL
AnnaBridge	189:f392fc9709a3	1566	* @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2
AnnaBridge	189:f392fc9709a3	1567	* @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3
AnnaBridge	189:f392fc9709a3	1568	* @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP
AnnaBridge	189:f392fc9709a3	1569	* @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock
AnnaBridge	189:f392fc9709a3	1570	* @retval None
AnnaBridge	189:f392fc9709a3	1571	*/
AnnaBridge	189:f392fc9709a3	1572	#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
AnnaBridge	189:f392fc9709a3	1573	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
AnnaBridge	189:f392fc9709a3	1574
AnnaBridge	189:f392fc9709a3	1575	/** @brief Macro to get the SAI4A clock source.
AnnaBridge	189:f392fc9709a3	1576	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1577	* @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL
AnnaBridge	189:f392fc9709a3	1578	* @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2
AnnaBridge	189:f392fc9709a3	1579	* @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3
AnnaBridge	189:f392fc9709a3	1580	* @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP
AnnaBridge	189:f392fc9709a3	1581	* @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock
AnnaBridge	189:f392fc9709a3	1582	*/
AnnaBridge	189:f392fc9709a3	1583	#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
AnnaBridge	189:f392fc9709a3	1584
AnnaBridge	189:f392fc9709a3	1585	/**
AnnaBridge	189:f392fc9709a3	1586	* @brief Macro to Configure the SAI4B clock source.
AnnaBridge	189:f392fc9709a3	1587	* @param __RCC_SAI4BCLKSource__: defines the SAI4B clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	1588	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	189:f392fc9709a3	1589	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1590	* @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
AnnaBridge	189:f392fc9709a3	1591	* @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
AnnaBridge	189:f392fc9709a3	1592	* @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
AnnaBridge	189:f392fc9709a3	1593	* @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP
AnnaBridge	189:f392fc9709a3	1594	* @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
AnnaBridge	189:f392fc9709a3	1595	* @retval None
AnnaBridge	189:f392fc9709a3	1596	*/
AnnaBridge	189:f392fc9709a3	1597	#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
AnnaBridge	189:f392fc9709a3	1598	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
AnnaBridge	189:f392fc9709a3	1599
AnnaBridge	189:f392fc9709a3	1600	/** @brief Macro to get the SAI4B clock source.
AnnaBridge	189:f392fc9709a3	1601	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1602	* @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
AnnaBridge	189:f392fc9709a3	1603	* @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
AnnaBridge	189:f392fc9709a3	1604	* @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
AnnaBridge	189:f392fc9709a3	1605	* @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP
AnnaBridge	189:f392fc9709a3	1606	* @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
AnnaBridge	189:f392fc9709a3	1607	*/
AnnaBridge	189:f392fc9709a3	1608	#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
AnnaBridge	189:f392fc9709a3	1609
AnnaBridge	189:f392fc9709a3	1610	/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).
AnnaBridge	189:f392fc9709a3	1611	*
AnnaBridge	189:f392fc9709a3	1612	* @param __I2C123CLKSource__: specifies the I2C1/2/3 clock source.
AnnaBridge	189:f392fc9709a3	1613	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1614	* @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
AnnaBridge	189:f392fc9709a3	1615	* @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
AnnaBridge	189:f392fc9709a3	1616	* @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
AnnaBridge	189:f392fc9709a3	1617	* @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
AnnaBridge	189:f392fc9709a3	1618	*/
AnnaBridge	189:f392fc9709a3	1619	#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
AnnaBridge	189:f392fc9709a3	1620	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
AnnaBridge	189:f392fc9709a3	1621
AnnaBridge	189:f392fc9709a3	1622	/** @brief macro to get the I2C1/2/3 clock source.
AnnaBridge	189:f392fc9709a3	1623	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1624	* @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
AnnaBridge	189:f392fc9709a3	1625	* @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
AnnaBridge	189:f392fc9709a3	1626	* @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
AnnaBridge	189:f392fc9709a3	1627	* @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
AnnaBridge	189:f392fc9709a3	1628	*/
AnnaBridge	189:f392fc9709a3	1629	#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
AnnaBridge	189:f392fc9709a3	1630
AnnaBridge	189:f392fc9709a3	1631	/** @brief macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge	189:f392fc9709a3	1632	*
AnnaBridge	189:f392fc9709a3	1633	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
AnnaBridge	189:f392fc9709a3	1634	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1635	* @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
AnnaBridge	189:f392fc9709a3	1636	* @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
AnnaBridge	189:f392fc9709a3	1637	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
AnnaBridge	189:f392fc9709a3	1638	* @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
AnnaBridge	189:f392fc9709a3	1639	*/
AnnaBridge	189:f392fc9709a3	1640	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
AnnaBridge	189:f392fc9709a3	1641	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1CLKSource__))
AnnaBridge	189:f392fc9709a3	1642
AnnaBridge	189:f392fc9709a3	1643	/** @brief macro to get the I2C1 clock source.
AnnaBridge	189:f392fc9709a3	1644	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1645	* @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
AnnaBridge	189:f392fc9709a3	1646	* @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
AnnaBridge	189:f392fc9709a3	1647	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
AnnaBridge	189:f392fc9709a3	1648	* @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
AnnaBridge	189:f392fc9709a3	1649	*/
AnnaBridge	189:f392fc9709a3	1650	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
AnnaBridge	189:f392fc9709a3	1651
AnnaBridge	189:f392fc9709a3	1652	/** @brief macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge	189:f392fc9709a3	1653	*
AnnaBridge	189:f392fc9709a3	1654	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
AnnaBridge	189:f392fc9709a3	1655	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1656	* @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
AnnaBridge	189:f392fc9709a3	1657	* @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
AnnaBridge	189:f392fc9709a3	1658	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
AnnaBridge	189:f392fc9709a3	1659	* @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
AnnaBridge	189:f392fc9709a3	1660	*/
AnnaBridge	189:f392fc9709a3	1661	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
AnnaBridge	189:f392fc9709a3	1662	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C2CLKSource__))
AnnaBridge	189:f392fc9709a3	1663
AnnaBridge	189:f392fc9709a3	1664	/** @brief macro to get the I2C2 clock source.
AnnaBridge	189:f392fc9709a3	1665	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1666	* @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
AnnaBridge	189:f392fc9709a3	1667	* @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
AnnaBridge	189:f392fc9709a3	1668	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
AnnaBridge	189:f392fc9709a3	1669	* @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
AnnaBridge	189:f392fc9709a3	1670	*/
AnnaBridge	189:f392fc9709a3	1671	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
AnnaBridge	189:f392fc9709a3	1672
AnnaBridge	189:f392fc9709a3	1673	/** @brief macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge	189:f392fc9709a3	1674	*
AnnaBridge	189:f392fc9709a3	1675	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
AnnaBridge	189:f392fc9709a3	1676	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1677	* @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
AnnaBridge	189:f392fc9709a3	1678	* @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
AnnaBridge	189:f392fc9709a3	1679	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
AnnaBridge	189:f392fc9709a3	1680	* @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
AnnaBridge	189:f392fc9709a3	1681	*/
AnnaBridge	189:f392fc9709a3	1682	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
AnnaBridge	189:f392fc9709a3	1683	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C3CLKSource__))
AnnaBridge	189:f392fc9709a3	1684
AnnaBridge	189:f392fc9709a3	1685	/** @brief macro to get the I2C3 clock source.
AnnaBridge	189:f392fc9709a3	1686	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1687	* @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
AnnaBridge	189:f392fc9709a3	1688	* @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
AnnaBridge	189:f392fc9709a3	1689	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
AnnaBridge	189:f392fc9709a3	1690	* @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
AnnaBridge	189:f392fc9709a3	1691	*/
AnnaBridge	189:f392fc9709a3	1692	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
AnnaBridge	189:f392fc9709a3	1693
AnnaBridge	189:f392fc9709a3	1694	/** @brief macro to configure the I2C4 clock (I2C4CLK).
AnnaBridge	189:f392fc9709a3	1695	*
AnnaBridge	189:f392fc9709a3	1696	* @param __I2C4CLKSource__: specifies the I2C4 clock source.
AnnaBridge	189:f392fc9709a3	1697	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1698	* @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
AnnaBridge	189:f392fc9709a3	1699	* @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
AnnaBridge	189:f392fc9709a3	1700	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
AnnaBridge	189:f392fc9709a3	1701	* @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
AnnaBridge	189:f392fc9709a3	1702	*/
AnnaBridge	189:f392fc9709a3	1703	#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
AnnaBridge	189:f392fc9709a3	1704	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
AnnaBridge	189:f392fc9709a3	1705
AnnaBridge	189:f392fc9709a3	1706	/** @brief macro to get the I2C4 clock source.
AnnaBridge	189:f392fc9709a3	1707	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1708	* @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
AnnaBridge	189:f392fc9709a3	1709	* @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
AnnaBridge	189:f392fc9709a3	1710	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
AnnaBridge	189:f392fc9709a3	1711	* @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
AnnaBridge	189:f392fc9709a3	1712	*/
AnnaBridge	189:f392fc9709a3	1713	#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
AnnaBridge	189:f392fc9709a3	1714
AnnaBridge	189:f392fc9709a3	1715	/** @brief macro to configure the USART1/6 clock (USART16CLK).
AnnaBridge	189:f392fc9709a3	1716	*
AnnaBridge	189:f392fc9709a3	1717	* @param __USART16CLKSource__: specifies the USART1/6 clock source.
AnnaBridge	189:f392fc9709a3	1718	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1719	* @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1720	* @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1721	* @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1722	* @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1723	* @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1724	* @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1725	*/
AnnaBridge	189:f392fc9709a3	1726	#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \
AnnaBridge	189:f392fc9709a3	1727	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))
AnnaBridge	189:f392fc9709a3	1728
AnnaBridge	189:f392fc9709a3	1729	/** @brief macro to get the USART1/6 clock source.
AnnaBridge	189:f392fc9709a3	1730	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1731	* @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1732	* @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1733	* @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1734	* @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1735	* @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1736	* @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock
AnnaBridge	189:f392fc9709a3	1737	*/
AnnaBridge	189:f392fc9709a3	1738	#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
AnnaBridge	189:f392fc9709a3	1739
AnnaBridge	189:f392fc9709a3	1740	/** @brief macro to configure the USART234578 clock (USART234578CLK).
AnnaBridge	189:f392fc9709a3	1741	*
AnnaBridge	189:f392fc9709a3	1742	* @param __USART234578CLKSource__: specifies the USART2/3/4/5/7/8 clock source.
AnnaBridge	189:f392fc9709a3	1743	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1744	* @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1745	* @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1746	* @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1747	* @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1748	* @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1749	* @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1750	*/
AnnaBridge	189:f392fc9709a3	1751	#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
AnnaBridge	189:f392fc9709a3	1752	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
AnnaBridge	189:f392fc9709a3	1753
AnnaBridge	189:f392fc9709a3	1754	/** @brief macro to get the USART2/3/4/5/7/8 clock source.
AnnaBridge	189:f392fc9709a3	1755	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1756	* @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1757	* @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1758	* @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1759	* @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1760	* @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1761	* @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
AnnaBridge	189:f392fc9709a3	1762	*/
AnnaBridge	189:f392fc9709a3	1763	#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	189:f392fc9709a3	1764
AnnaBridge	189:f392fc9709a3	1765	/** @brief macro to configure the USART1 clock (USART1CLK).
AnnaBridge	189:f392fc9709a3	1766	*
AnnaBridge	189:f392fc9709a3	1767	* @param __USART1CLKSource__: specifies the USART1 clock source.
AnnaBridge	189:f392fc9709a3	1768	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1769	* @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1770	* @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1771	* @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1772	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1773	* @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1774	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1775	*/
AnnaBridge	189:f392fc9709a3	1776	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
AnnaBridge	189:f392fc9709a3	1777	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART1CLKSource__))
AnnaBridge	189:f392fc9709a3	1778
AnnaBridge	189:f392fc9709a3	1779	/** @brief macro to get the USART1 clock source.
AnnaBridge	189:f392fc9709a3	1780	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1781	* @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1782	* @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1783	* @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1784	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1785	* @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1786	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
AnnaBridge	189:f392fc9709a3	1787	*/
AnnaBridge	189:f392fc9709a3	1788	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
AnnaBridge	189:f392fc9709a3	1789
AnnaBridge	189:f392fc9709a3	1790	/** @brief macro to configure the USART2 clock (USART2CLK).
AnnaBridge	189:f392fc9709a3	1791	*
AnnaBridge	189:f392fc9709a3	1792	* @param __USART2CLKSource__: specifies the USART2 clock source.
AnnaBridge	189:f392fc9709a3	1793	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1794	* @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1795	* @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1796	* @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1797	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1798	* @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1799	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1800	*/
AnnaBridge	189:f392fc9709a3	1801	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
AnnaBridge	189:f392fc9709a3	1802	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART2CLKSource__))
AnnaBridge	189:f392fc9709a3	1803
AnnaBridge	189:f392fc9709a3	1804	/** @brief macro to get the USART2 clock source.
AnnaBridge	189:f392fc9709a3	1805	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1806	* @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1807	* @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1808	* @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1809	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1810	* @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1811	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
AnnaBridge	189:f392fc9709a3	1812	*/
AnnaBridge	189:f392fc9709a3	1813	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	189:f392fc9709a3	1814
AnnaBridge	189:f392fc9709a3	1815	/** @brief macro to configure the USART3 clock (USART3CLK).
AnnaBridge	189:f392fc9709a3	1816	*
AnnaBridge	189:f392fc9709a3	1817	* @param __USART3CLKSource__: specifies the USART3 clock source.
AnnaBridge	189:f392fc9709a3	1818	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1819	* @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1820	* @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1821	* @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1822	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1823	* @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1824	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1825	*/
AnnaBridge	189:f392fc9709a3	1826	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
AnnaBridge	189:f392fc9709a3	1827	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART3CLKSource__))
AnnaBridge	189:f392fc9709a3	1828
AnnaBridge	189:f392fc9709a3	1829	/** @brief macro to get the USART3 clock source.
AnnaBridge	189:f392fc9709a3	1830	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1831	* @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1832	* @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1833	* @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1834	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1835	* @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1836	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
AnnaBridge	189:f392fc9709a3	1837	*/
AnnaBridge	189:f392fc9709a3	1838	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	189:f392fc9709a3	1839
AnnaBridge	189:f392fc9709a3	1840	/** @brief macro to configure the UART4 clock (UART4CLK).
AnnaBridge	189:f392fc9709a3	1841	*
AnnaBridge	189:f392fc9709a3	1842	* @param __UART4CLKSource__: specifies the UART4 clock source.
AnnaBridge	189:f392fc9709a3	1843	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1844	* @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1845	* @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1846	* @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1847	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1848	* @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1849	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1850	*/
AnnaBridge	189:f392fc9709a3	1851	#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
AnnaBridge	189:f392fc9709a3	1852	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART4CLKSource__))
AnnaBridge	189:f392fc9709a3	1853
AnnaBridge	189:f392fc9709a3	1854	/** @brief macro to get the UART4 clock source.
AnnaBridge	189:f392fc9709a3	1855	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1856	* @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1857	* @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1858	* @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1859	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1860	* @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1861	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
AnnaBridge	189:f392fc9709a3	1862	*/
AnnaBridge	189:f392fc9709a3	1863	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	189:f392fc9709a3	1864
AnnaBridge	189:f392fc9709a3	1865	/** @brief macro to configure the UART5 clock (UART5CLK).
AnnaBridge	189:f392fc9709a3	1866	*
AnnaBridge	189:f392fc9709a3	1867	* @param __UART5CLKSource__: specifies the UART5 clock source.
AnnaBridge	189:f392fc9709a3	1868	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1869	* @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1870	* @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1871	* @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1872	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1873	* @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1874	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1875	*/
AnnaBridge	189:f392fc9709a3	1876	#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
AnnaBridge	189:f392fc9709a3	1877	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART5CLKSource__))
AnnaBridge	189:f392fc9709a3	1878
AnnaBridge	189:f392fc9709a3	1879	/** @brief macro to get the UART5 clock source.
AnnaBridge	189:f392fc9709a3	1880	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1881	* @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1882	* @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1883	* @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1884	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1885	* @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1886	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
AnnaBridge	189:f392fc9709a3	1887	*/
AnnaBridge	189:f392fc9709a3	1888	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	189:f392fc9709a3	1889
AnnaBridge	189:f392fc9709a3	1890	/** @brief macro to configure the USART6 clock (USART6CLK).
AnnaBridge	189:f392fc9709a3	1891	*
AnnaBridge	189:f392fc9709a3	1892	* @param __USART6CLKSource__: specifies the USART6 clock source.
AnnaBridge	189:f392fc9709a3	1893	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1894	* @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1895	* @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1896	* @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1897	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1898	* @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1899	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1900	*/
AnnaBridge	189:f392fc9709a3	1901	#define __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) \
AnnaBridge	189:f392fc9709a3	1902	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART6CLKSource__))
AnnaBridge	189:f392fc9709a3	1903
AnnaBridge	189:f392fc9709a3	1904	/** @brief macro to get the USART6 clock source.
AnnaBridge	189:f392fc9709a3	1905	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1906	* @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1907	* @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1908	* @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1909	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1910	* @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1911	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
AnnaBridge	189:f392fc9709a3	1912	*/
AnnaBridge	189:f392fc9709a3	1913	#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
AnnaBridge	189:f392fc9709a3	1914
AnnaBridge	189:f392fc9709a3	1915	/** @brief macro to configure the UART5 clock (UART7CLK).
AnnaBridge	189:f392fc9709a3	1916	*
AnnaBridge	189:f392fc9709a3	1917	* @param __UART7CLKSource__: specifies the UART7 clock source.
AnnaBridge	189:f392fc9709a3	1918	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1919	* @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1920	* @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1921	* @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1922	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1923	* @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1924	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1925	*/
AnnaBridge	189:f392fc9709a3	1926	#define __HAL_RCC_UART7_CONFIG(__UART7CLKSource__) \
AnnaBridge	189:f392fc9709a3	1927	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART7CLKSource__))
AnnaBridge	189:f392fc9709a3	1928
AnnaBridge	189:f392fc9709a3	1929	/** @brief macro to get the UART7 clock source.
AnnaBridge	189:f392fc9709a3	1930	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1931	* @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1932	* @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1933	* @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1934	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1935	* @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1936	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
AnnaBridge	189:f392fc9709a3	1937	*/
AnnaBridge	189:f392fc9709a3	1938	#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	189:f392fc9709a3	1939
AnnaBridge	189:f392fc9709a3	1940	/** @brief macro to configure the UART8 clock (UART8CLK).
AnnaBridge	189:f392fc9709a3	1941	*
AnnaBridge	189:f392fc9709a3	1942	* @param __UART8CLKSource__: specifies the UART8 clock source.
AnnaBridge	189:f392fc9709a3	1943	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1944	* @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1945	* @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1946	* @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1947	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1948	* @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1949	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1950	*/
AnnaBridge	189:f392fc9709a3	1951	#define __HAL_RCC_UART8_CONFIG(__UART8CLKSource__) \
AnnaBridge	189:f392fc9709a3	1952	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART8CLKSource__))
AnnaBridge	189:f392fc9709a3	1953
AnnaBridge	189:f392fc9709a3	1954	/** @brief macro to get the UART8 clock source.
AnnaBridge	189:f392fc9709a3	1955	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1956	* @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1957	* @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1958	* @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1959	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1960	* @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1961	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
AnnaBridge	189:f392fc9709a3	1962	*/
AnnaBridge	189:f392fc9709a3	1963	#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	189:f392fc9709a3	1964
AnnaBridge	189:f392fc9709a3	1965	/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
AnnaBridge	189:f392fc9709a3	1966	*
AnnaBridge	189:f392fc9709a3	1967	* @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
AnnaBridge	189:f392fc9709a3	1968	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1969	* @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1970	* @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1971	* @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1972	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1973	* @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1974	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1975	*/
AnnaBridge	189:f392fc9709a3	1976	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
AnnaBridge	189:f392fc9709a3	1977	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
AnnaBridge	189:f392fc9709a3	1978
AnnaBridge	189:f392fc9709a3	1979	/** @brief macro to get the LPUART1 clock source.
AnnaBridge	189:f392fc9709a3	1980	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1981	* @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1982	* @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1983	* @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1984	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1985	* @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1986	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
AnnaBridge	189:f392fc9709a3	1987	*/
AnnaBridge	189:f392fc9709a3	1988	#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
AnnaBridge	189:f392fc9709a3	1989
AnnaBridge	189:f392fc9709a3	1990	/** @brief macro to get the LPTIM1 clock source.
AnnaBridge	189:f392fc9709a3	1991	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	1992	* @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	1993	* @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	1994	* @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	1995	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	1996	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	1997	* @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	1998	*/
AnnaBridge	189:f392fc9709a3	1999	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
AnnaBridge	189:f392fc9709a3	2000	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
AnnaBridge	189:f392fc9709a3	2001
AnnaBridge	189:f392fc9709a3	2002
AnnaBridge	189:f392fc9709a3	2003	/** @brief macro to get the LPTIM1 clock source.
AnnaBridge	189:f392fc9709a3	2004	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2005	* @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	2006	* @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	2007	* @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	2008	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	2009	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	2010	* @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
AnnaBridge	189:f392fc9709a3	2011	*/
AnnaBridge	189:f392fc9709a3	2012	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
AnnaBridge	189:f392fc9709a3	2013
AnnaBridge	189:f392fc9709a3	2014	/** @brief macro to get the LPTIM2 clock source.
AnnaBridge	189:f392fc9709a3	2015	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2016	* @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2017	* @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2018	* @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2019	* @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2020	* @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2021	* @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2022	*/
AnnaBridge	189:f392fc9709a3	2023	#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
AnnaBridge	189:f392fc9709a3	2024	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
AnnaBridge	189:f392fc9709a3	2025
AnnaBridge	189:f392fc9709a3	2026
AnnaBridge	189:f392fc9709a3	2027	/** @brief macro to get the LPTIM2 clock source.
AnnaBridge	189:f392fc9709a3	2028	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2029	* @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2030	* @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2031	* @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2032	* @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2033	* @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2034	* @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
AnnaBridge	189:f392fc9709a3	2035	*/
AnnaBridge	189:f392fc9709a3	2036	#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
AnnaBridge	189:f392fc9709a3	2037
AnnaBridge	189:f392fc9709a3	2038	/** @brief macro to get the LPTIM3/4/5 clock source.
AnnaBridge	189:f392fc9709a3	2039	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2040	* @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2041	* @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2042	* @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2043	* @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2044	* @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2045	* @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2046	*/
AnnaBridge	189:f392fc9709a3	2047	#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
AnnaBridge	189:f392fc9709a3	2048	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
AnnaBridge	189:f392fc9709a3	2049
AnnaBridge	189:f392fc9709a3	2050
AnnaBridge	189:f392fc9709a3	2051	/** @brief macro to get the LPTIM3/4/5 clock source.
AnnaBridge	189:f392fc9709a3	2052	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2053	* @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2054	* @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2055	* @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2056	* @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2057	* @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2058	* @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
AnnaBridge	189:f392fc9709a3	2059	*/
AnnaBridge	189:f392fc9709a3	2060	#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
AnnaBridge	189:f392fc9709a3	2061
AnnaBridge	189:f392fc9709a3	2062	/** @brief macro to get the LPTIM3 clock source.
AnnaBridge	189:f392fc9709a3	2063	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2064	* @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2065	* @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2066	* @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2067	* @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2068	* @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2069	* @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2070	*/
AnnaBridge	189:f392fc9709a3	2071	#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3CLKSource__) \
AnnaBridge	189:f392fc9709a3	2072	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM3CLKSource__))
AnnaBridge	189:f392fc9709a3	2073
AnnaBridge	189:f392fc9709a3	2074
AnnaBridge	189:f392fc9709a3	2075	/** @brief macro to get the LPTIM3 clock source.
AnnaBridge	189:f392fc9709a3	2076	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2077	* @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2078	* @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2079	* @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2080	* @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2081	* @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2082	* @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
AnnaBridge	189:f392fc9709a3	2083	*/
AnnaBridge	189:f392fc9709a3	2084	#define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
AnnaBridge	189:f392fc9709a3	2085
AnnaBridge	189:f392fc9709a3	2086	/** @brief macro to get the LPTIM4 clock source.
AnnaBridge	189:f392fc9709a3	2087	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2088	* @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2089	* @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2090	* @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2091	* @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2092	* @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2093	* @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2094	*/
AnnaBridge	189:f392fc9709a3	2095	#define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4CLKSource__) \
AnnaBridge	189:f392fc9709a3	2096	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM4CLKSource__))
AnnaBridge	189:f392fc9709a3	2097
AnnaBridge	189:f392fc9709a3	2098
AnnaBridge	189:f392fc9709a3	2099	/** @brief macro to get the LPTIM4 clock source.
AnnaBridge	189:f392fc9709a3	2100	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2101	* @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2102	* @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2103	* @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2104	* @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2105	* @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2106	* @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
AnnaBridge	189:f392fc9709a3	2107	*/
AnnaBridge	189:f392fc9709a3	2108	#define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
AnnaBridge	189:f392fc9709a3	2109
AnnaBridge	189:f392fc9709a3	2110	/** @brief macro to configure the LPTIM5 clock source.
AnnaBridge	189:f392fc9709a3	2111	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2112	* @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2113	* @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2114	* @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2115	* @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2116	* @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2117	* @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2118	*/
AnnaBridge	189:f392fc9709a3	2119	#define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5CLKSource__) \
AnnaBridge	189:f392fc9709a3	2120	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM5CLKSource__))
AnnaBridge	189:f392fc9709a3	2121
AnnaBridge	189:f392fc9709a3	2122
AnnaBridge	189:f392fc9709a3	2123	/** @brief macro to get the LPTIM5 clock source.
AnnaBridge	189:f392fc9709a3	2124	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2125	* @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2126	* @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2127	* @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2128	* @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2129	* @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2130	* @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
AnnaBridge	189:f392fc9709a3	2131	*/
AnnaBridge	189:f392fc9709a3	2132	#define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
AnnaBridge	189:f392fc9709a3	2133
AnnaBridge	189:f392fc9709a3	2134	/** @brief macro to configure the QSPI clock source.
AnnaBridge	189:f392fc9709a3	2135	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2136	* @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
AnnaBridge	189:f392fc9709a3	2137	* @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock
AnnaBridge	189:f392fc9709a3	2138	* @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock
AnnaBridge	189:f392fc9709a3	2139	* @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock
AnnaBridge	189:f392fc9709a3	2140	*/
AnnaBridge	189:f392fc9709a3	2141	#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
AnnaBridge	189:f392fc9709a3	2142	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
AnnaBridge	189:f392fc9709a3	2143
AnnaBridge	189:f392fc9709a3	2144
AnnaBridge	189:f392fc9709a3	2145	/** @brief macro to get the QSPI clock source.
AnnaBridge	189:f392fc9709a3	2146	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2147	* @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
AnnaBridge	189:f392fc9709a3	2148	* @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock
AnnaBridge	189:f392fc9709a3	2149	* @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock
AnnaBridge	189:f392fc9709a3	2150	* @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock
AnnaBridge	189:f392fc9709a3	2151	*/
AnnaBridge	189:f392fc9709a3	2152	#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
AnnaBridge	189:f392fc9709a3	2153
AnnaBridge	189:f392fc9709a3	2154	/** @brief macro to configure the FMC clock source.
AnnaBridge	189:f392fc9709a3	2155	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2156	* @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
AnnaBridge	189:f392fc9709a3	2157	* @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
AnnaBridge	189:f392fc9709a3	2158	* @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
AnnaBridge	189:f392fc9709a3	2159	* @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock
AnnaBridge	189:f392fc9709a3	2160	*/
AnnaBridge	189:f392fc9709a3	2161	#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
AnnaBridge	189:f392fc9709a3	2162	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
AnnaBridge	189:f392fc9709a3	2163
AnnaBridge	189:f392fc9709a3	2164
AnnaBridge	189:f392fc9709a3	2165	/** @brief macro to get the FMC clock source.
AnnaBridge	189:f392fc9709a3	2166	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2167	* @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
AnnaBridge	189:f392fc9709a3	2168	* @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
AnnaBridge	189:f392fc9709a3	2169	* @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
AnnaBridge	189:f392fc9709a3	2170	* @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock
AnnaBridge	189:f392fc9709a3	2171	*/
AnnaBridge	189:f392fc9709a3	2172	#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
AnnaBridge	189:f392fc9709a3	2173
AnnaBridge	189:f392fc9709a3	2174	/** @brief Macro to configure the USB clock (USBCLK).
AnnaBridge	189:f392fc9709a3	2175	* @param __USBCLKSource__: specifies the USB clock source.
AnnaBridge	189:f392fc9709a3	2176	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2177	* @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
AnnaBridge	189:f392fc9709a3	2178	* @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
AnnaBridge	189:f392fc9709a3	2179	* @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
AnnaBridge	189:f392fc9709a3	2180	*/
AnnaBridge	189:f392fc9709a3	2181	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
AnnaBridge	189:f392fc9709a3	2182	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
AnnaBridge	189:f392fc9709a3	2183
AnnaBridge	189:f392fc9709a3	2184	/** @brief Macro to get the USB clock source.
AnnaBridge	189:f392fc9709a3	2185	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2186	* @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
AnnaBridge	189:f392fc9709a3	2187	* @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
AnnaBridge	189:f392fc9709a3	2188	* @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
AnnaBridge	189:f392fc9709a3	2189	*/
AnnaBridge	189:f392fc9709a3	2190	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
AnnaBridge	189:f392fc9709a3	2191
AnnaBridge	189:f392fc9709a3	2192
AnnaBridge	189:f392fc9709a3	2193	/** @brief Macro to configure the ADC clock
AnnaBridge	189:f392fc9709a3	2194	* @param __ADCCLKSource__: specifies the ADC digital interface clock source.
AnnaBridge	189:f392fc9709a3	2195	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2196	* @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
AnnaBridge	189:f392fc9709a3	2197	* @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
AnnaBridge	189:f392fc9709a3	2198	* @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
AnnaBridge	189:f392fc9709a3	2199	*/
AnnaBridge	189:f392fc9709a3	2200	#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
AnnaBridge	189:f392fc9709a3	2201	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
AnnaBridge	189:f392fc9709a3	2202
AnnaBridge	189:f392fc9709a3	2203	/** @brief Macro to get the ADC clock source.
AnnaBridge	189:f392fc9709a3	2204	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2205	* @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
AnnaBridge	189:f392fc9709a3	2206	* @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
AnnaBridge	189:f392fc9709a3	2207	* @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
AnnaBridge	189:f392fc9709a3	2208	*/
AnnaBridge	189:f392fc9709a3	2209	#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
AnnaBridge	189:f392fc9709a3	2210
AnnaBridge	189:f392fc9709a3	2211	/** @brief Macro to configure the SWPMI1 clock
AnnaBridge	189:f392fc9709a3	2212	* @param __SWPMI1CLKSource__: specifies the SWPMI1 clock source.
AnnaBridge	189:f392fc9709a3	2213	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2214	* @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
AnnaBridge	189:f392fc9709a3	2215	* @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
AnnaBridge	189:f392fc9709a3	2216	*/
AnnaBridge	189:f392fc9709a3	2217	#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
AnnaBridge	189:f392fc9709a3	2218	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
AnnaBridge	189:f392fc9709a3	2219
AnnaBridge	189:f392fc9709a3	2220	/** @brief Macro to get the SWPMI1 clock source.
AnnaBridge	189:f392fc9709a3	2221	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2222	* @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
AnnaBridge	189:f392fc9709a3	2223	* @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
AnnaBridge	189:f392fc9709a3	2224	*/
AnnaBridge	189:f392fc9709a3	2225	#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
AnnaBridge	189:f392fc9709a3	2226
AnnaBridge	189:f392fc9709a3	2227	/** @brief Macro to configure the DFSDM1 clock
AnnaBridge	189:f392fc9709a3	2228	* @param __DFSDM1CLKSource__: specifies the DFSDM1 clock source.
AnnaBridge	189:f392fc9709a3	2229	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2230	* @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
AnnaBridge	189:f392fc9709a3	2231	* @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
AnnaBridge	189:f392fc9709a3	2232	*/
AnnaBridge	189:f392fc9709a3	2233	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
AnnaBridge	189:f392fc9709a3	2234	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
AnnaBridge	189:f392fc9709a3	2235
AnnaBridge	189:f392fc9709a3	2236	/** @brief Macro to get the DFSDM1 clock source.
AnnaBridge	189:f392fc9709a3	2237	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2238	* @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
AnnaBridge	189:f392fc9709a3	2239	* @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
AnnaBridge	189:f392fc9709a3	2240	*/
AnnaBridge	189:f392fc9709a3	2241	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
AnnaBridge	189:f392fc9709a3	2242
AnnaBridge	189:f392fc9709a3	2243	/** @brief macro to configure the CEC clock (CECCLK).
AnnaBridge	189:f392fc9709a3	2244	*
AnnaBridge	189:f392fc9709a3	2245	* @param __CECCLKSource__: specifies the CEC clock source.
AnnaBridge	189:f392fc9709a3	2246	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2247	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge	189:f392fc9709a3	2248	* @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
AnnaBridge	189:f392fc9709a3	2249	* @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
AnnaBridge	189:f392fc9709a3	2250	*/
AnnaBridge	189:f392fc9709a3	2251	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
AnnaBridge	189:f392fc9709a3	2252	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
AnnaBridge	189:f392fc9709a3	2253
AnnaBridge	189:f392fc9709a3	2254	/** @brief macro to get the CEC clock source.
AnnaBridge	189:f392fc9709a3	2255	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2256	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge	189:f392fc9709a3	2257	* @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
AnnaBridge	189:f392fc9709a3	2258	* @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
AnnaBridge	189:f392fc9709a3	2259	*/
AnnaBridge	189:f392fc9709a3	2260	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
AnnaBridge	189:f392fc9709a3	2261
AnnaBridge	189:f392fc9709a3	2262
AnnaBridge	189:f392fc9709a3	2263	/** @brief Macro to configure the CLKP : Oscillator clock for peripheral
AnnaBridge	189:f392fc9709a3	2264	* @param __CLKPSource__: specifies Oscillator clock for peripheral
AnnaBridge	189:f392fc9709a3	2265	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2266	* @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
AnnaBridge	189:f392fc9709a3	2267	* @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
AnnaBridge	189:f392fc9709a3	2268	* @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
AnnaBridge	189:f392fc9709a3	2269	*/
AnnaBridge	189:f392fc9709a3	2270	#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
AnnaBridge	189:f392fc9709a3	2271	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
AnnaBridge	189:f392fc9709a3	2272
AnnaBridge	189:f392fc9709a3	2273	/** @brief Macro to get the Oscillator clock for peripheral source.
AnnaBridge	189:f392fc9709a3	2274	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2275	* @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
AnnaBridge	189:f392fc9709a3	2276	* @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
AnnaBridge	189:f392fc9709a3	2277	* @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
AnnaBridge	189:f392fc9709a3	2278	*/
AnnaBridge	189:f392fc9709a3	2279	#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
AnnaBridge	189:f392fc9709a3	2280
AnnaBridge	189:f392fc9709a3	2281	#if defined(FDCAN1) \|\| defined(FDCAN2)
AnnaBridge	189:f392fc9709a3	2282	/** @brief Macro to configure the FDCAN clock
AnnaBridge	189:f392fc9709a3	2283	* @param __FDCANCLKSource__: specifies clock source for FDCAN
AnnaBridge	189:f392fc9709a3	2284	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2285	* @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
AnnaBridge	189:f392fc9709a3	2286	* @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
AnnaBridge	189:f392fc9709a3	2287	* @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
AnnaBridge	189:f392fc9709a3	2288	*/
AnnaBridge	189:f392fc9709a3	2289	#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
AnnaBridge	189:f392fc9709a3	2290	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
AnnaBridge	189:f392fc9709a3	2291
AnnaBridge	189:f392fc9709a3	2292	/** @brief Macro to get the FDCAN clock
AnnaBridge	189:f392fc9709a3	2293	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2294	* @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
AnnaBridge	189:f392fc9709a3	2295	* @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
AnnaBridge	189:f392fc9709a3	2296	* @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
AnnaBridge	189:f392fc9709a3	2297	*/
AnnaBridge	189:f392fc9709a3	2298	#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
AnnaBridge	189:f392fc9709a3	2299	#endif /FDCAN1 \|\| FDCAN2/
AnnaBridge	189:f392fc9709a3	2300	/**
AnnaBridge	189:f392fc9709a3	2301	* @brief Macro to Configure the SPI1/2/3 clock source.
AnnaBridge	189:f392fc9709a3	2302	* @param __RCC_SPI123CLKSource__: defines the SPI1/2/3 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	2303	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	189:f392fc9709a3	2304	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2305	* @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
AnnaBridge	189:f392fc9709a3	2306	* @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
AnnaBridge	189:f392fc9709a3	2307	* @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
AnnaBridge	189:f392fc9709a3	2308	* @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
AnnaBridge	189:f392fc9709a3	2309	* @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
AnnaBridge	189:f392fc9709a3	2310	* @retval None
AnnaBridge	189:f392fc9709a3	2311	*/
AnnaBridge	189:f392fc9709a3	2312	#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
AnnaBridge	189:f392fc9709a3	2313	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
AnnaBridge	189:f392fc9709a3	2314
AnnaBridge	189:f392fc9709a3	2315	/** @brief Macro to get the SPI1/2/3 clock source.
AnnaBridge	189:f392fc9709a3	2316	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2317	* @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
AnnaBridge	189:f392fc9709a3	2318	* @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
AnnaBridge	189:f392fc9709a3	2319	* @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
AnnaBridge	189:f392fc9709a3	2320	* @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
AnnaBridge	189:f392fc9709a3	2321	* @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
AnnaBridge	189:f392fc9709a3	2322	*/
AnnaBridge	189:f392fc9709a3	2323	#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
AnnaBridge	189:f392fc9709a3	2324
AnnaBridge	189:f392fc9709a3	2325	/**
AnnaBridge	189:f392fc9709a3	2326	* @brief Macro to Configure the SPI1 clock source.
AnnaBridge	189:f392fc9709a3	2327	* @param __RCC_SPI1CLKSource__: defines the SPI1 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	2328	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	189:f392fc9709a3	2329	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2330	* @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
AnnaBridge	189:f392fc9709a3	2331	* @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
AnnaBridge	189:f392fc9709a3	2332	* @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
AnnaBridge	189:f392fc9709a3	2333	* @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
AnnaBridge	189:f392fc9709a3	2334	* @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
AnnaBridge	189:f392fc9709a3	2335	* @retval None
AnnaBridge	189:f392fc9709a3	2336	*/
AnnaBridge	189:f392fc9709a3	2337	#define __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__ )\
AnnaBridge	189:f392fc9709a3	2338	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI1CLKSource__))
AnnaBridge	189:f392fc9709a3	2339
AnnaBridge	189:f392fc9709a3	2340	/** @brief Macro to get the SPI1 clock source.
AnnaBridge	189:f392fc9709a3	2341	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2342	* @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
AnnaBridge	189:f392fc9709a3	2343	* @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
AnnaBridge	189:f392fc9709a3	2344	* @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
AnnaBridge	189:f392fc9709a3	2345	* @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
AnnaBridge	189:f392fc9709a3	2346	* @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
AnnaBridge	189:f392fc9709a3	2347	*/
AnnaBridge	189:f392fc9709a3	2348	#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
AnnaBridge	189:f392fc9709a3	2349
AnnaBridge	189:f392fc9709a3	2350	/**
AnnaBridge	189:f392fc9709a3	2351	* @brief Macro to Configure the SPI2 clock source.
AnnaBridge	189:f392fc9709a3	2352	* @param __RCC_SPI2CLKSource__: defines the SPI2 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	2353	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	189:f392fc9709a3	2354	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2355	* @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
AnnaBridge	189:f392fc9709a3	2356	* @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
AnnaBridge	189:f392fc9709a3	2357	* @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
AnnaBridge	189:f392fc9709a3	2358	* @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
AnnaBridge	189:f392fc9709a3	2359	* @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
AnnaBridge	189:f392fc9709a3	2360	* @retval None
AnnaBridge	189:f392fc9709a3	2361	*/
AnnaBridge	189:f392fc9709a3	2362	#define __HAL_RCC_SPI2_CONFIG(__RCC_SPI2CLKSource__ )\
AnnaBridge	189:f392fc9709a3	2363	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI2CLKSource__))
AnnaBridge	189:f392fc9709a3	2364
AnnaBridge	189:f392fc9709a3	2365	/** @brief Macro to get the SPI2 clock source.
AnnaBridge	189:f392fc9709a3	2366	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2367	* @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
AnnaBridge	189:f392fc9709a3	2368	* @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
AnnaBridge	189:f392fc9709a3	2369	* @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
AnnaBridge	189:f392fc9709a3	2370	* @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
AnnaBridge	189:f392fc9709a3	2371	* @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
AnnaBridge	189:f392fc9709a3	2372	*/
AnnaBridge	189:f392fc9709a3	2373	#define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
AnnaBridge	189:f392fc9709a3	2374
AnnaBridge	189:f392fc9709a3	2375	/**
AnnaBridge	189:f392fc9709a3	2376	* @brief Macro to Configure the SPI3 clock source.
AnnaBridge	189:f392fc9709a3	2377	* @param __RCC_SPI3CLKSource__: defines the SPI3 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	2378	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	189:f392fc9709a3	2379	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2380	* @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
AnnaBridge	189:f392fc9709a3	2381	* @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
AnnaBridge	189:f392fc9709a3	2382	* @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
AnnaBridge	189:f392fc9709a3	2383	* @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
AnnaBridge	189:f392fc9709a3	2384	* @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
AnnaBridge	189:f392fc9709a3	2385	* @retval None
AnnaBridge	189:f392fc9709a3	2386	*/
AnnaBridge	189:f392fc9709a3	2387	#define __HAL_RCC_SPI3_CONFIG(__RCC_SPI3CLKSource__ )\
AnnaBridge	189:f392fc9709a3	2388	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI3CLKSource__))
AnnaBridge	189:f392fc9709a3	2389
AnnaBridge	189:f392fc9709a3	2390	/** @brief Macro to get the SPI3 clock source.
AnnaBridge	189:f392fc9709a3	2391	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2392	* @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
AnnaBridge	189:f392fc9709a3	2393	* @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
AnnaBridge	189:f392fc9709a3	2394	* @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
AnnaBridge	189:f392fc9709a3	2395	* @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
AnnaBridge	189:f392fc9709a3	2396	* @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
AnnaBridge	189:f392fc9709a3	2397	*/
AnnaBridge	189:f392fc9709a3	2398	#define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
AnnaBridge	189:f392fc9709a3	2399
AnnaBridge	189:f392fc9709a3	2400	/**
AnnaBridge	189:f392fc9709a3	2401	* @brief Macro to Configure the SPI4/5 clock source.
AnnaBridge	189:f392fc9709a3	2402	* @param __RCC_SPI45CLKSource__: defines the SPI4/5 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	2403	* from system PCLK, PLL2, PLL3, OSC
AnnaBridge	189:f392fc9709a3	2404	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2405	* @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
AnnaBridge	189:f392fc9709a3	2406	* @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
AnnaBridge	189:f392fc9709a3	2407	* @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
AnnaBridge	189:f392fc9709a3	2408	* @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
AnnaBridge	189:f392fc9709a3	2409	* @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
AnnaBridge	189:f392fc9709a3	2410	* @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
AnnaBridge	189:f392fc9709a3	2411	* @retval None
AnnaBridge	189:f392fc9709a3	2412	*/
AnnaBridge	189:f392fc9709a3	2413	#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
AnnaBridge	189:f392fc9709a3	2414	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
AnnaBridge	189:f392fc9709a3	2415
AnnaBridge	189:f392fc9709a3	2416	/** @brief Macro to get the SPI4/5 clock source.
AnnaBridge	189:f392fc9709a3	2417	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2418	* @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
AnnaBridge	189:f392fc9709a3	2419	* @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
AnnaBridge	189:f392fc9709a3	2420	* @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
AnnaBridge	189:f392fc9709a3	2421	* @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
AnnaBridge	189:f392fc9709a3	2422	* @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
AnnaBridge	189:f392fc9709a3	2423	* @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
AnnaBridge	189:f392fc9709a3	2424	*/
AnnaBridge	189:f392fc9709a3	2425	#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
AnnaBridge	189:f392fc9709a3	2426
AnnaBridge	189:f392fc9709a3	2427	/**
AnnaBridge	189:f392fc9709a3	2428	* @brief Macro to Configure the SPI4 clock source.
AnnaBridge	189:f392fc9709a3	2429	* @param __RCC_SPI4CLKSource__: defines the SPI4 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	2430	* from system PCLK, PLL2, PLL3, OSC
AnnaBridge	189:f392fc9709a3	2431	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2432	* @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
AnnaBridge	189:f392fc9709a3	2433	* @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
AnnaBridge	189:f392fc9709a3	2434	* @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
AnnaBridge	189:f392fc9709a3	2435	* @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
AnnaBridge	189:f392fc9709a3	2436	* @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
AnnaBridge	189:f392fc9709a3	2437	* @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
AnnaBridge	189:f392fc9709a3	2438	* @retval None
AnnaBridge	189:f392fc9709a3	2439	*/
AnnaBridge	189:f392fc9709a3	2440	#define __HAL_RCC_SPI4_CONFIG(__RCC_SPI4CLKSource__ )\
AnnaBridge	189:f392fc9709a3	2441	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI4CLKSource__))
AnnaBridge	189:f392fc9709a3	2442
AnnaBridge	189:f392fc9709a3	2443	/** @brief Macro to get the SPI4 clock source.
AnnaBridge	189:f392fc9709a3	2444	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2445	* @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
AnnaBridge	189:f392fc9709a3	2446	* @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
AnnaBridge	189:f392fc9709a3	2447	* @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
AnnaBridge	189:f392fc9709a3	2448	* @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
AnnaBridge	189:f392fc9709a3	2449	* @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
AnnaBridge	189:f392fc9709a3	2450	* @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
AnnaBridge	189:f392fc9709a3	2451	*/
AnnaBridge	189:f392fc9709a3	2452	#define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
AnnaBridge	189:f392fc9709a3	2453
AnnaBridge	189:f392fc9709a3	2454	/**
AnnaBridge	189:f392fc9709a3	2455	* @brief Macro to Configure the SPI5 clock source.
AnnaBridge	189:f392fc9709a3	2456	* @param __RCC_SPI5CLKSource__: defines the SPI5 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	2457	* from system PCLK, PLL2, PLL3, OSC
AnnaBridge	189:f392fc9709a3	2458	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2459	* @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
AnnaBridge	189:f392fc9709a3	2460	* @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
AnnaBridge	189:f392fc9709a3	2461	* @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
AnnaBridge	189:f392fc9709a3	2462	* @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
AnnaBridge	189:f392fc9709a3	2463	* @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
AnnaBridge	189:f392fc9709a3	2464	* @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
AnnaBridge	189:f392fc9709a3	2465	* @retval None
AnnaBridge	189:f392fc9709a3	2466	*/
AnnaBridge	189:f392fc9709a3	2467	#define __HAL_RCC_SPI5_CONFIG(__RCC_SPI5CLKSource__ )\
AnnaBridge	189:f392fc9709a3	2468	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI5CLKSource__))
AnnaBridge	189:f392fc9709a3	2469
AnnaBridge	189:f392fc9709a3	2470	/** @brief Macro to get the SPI5 clock source.
AnnaBridge	189:f392fc9709a3	2471	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2472	* @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
AnnaBridge	189:f392fc9709a3	2473	* @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
AnnaBridge	189:f392fc9709a3	2474	* @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
AnnaBridge	189:f392fc9709a3	2475	* @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
AnnaBridge	189:f392fc9709a3	2476	* @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
AnnaBridge	189:f392fc9709a3	2477	* @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
AnnaBridge	189:f392fc9709a3	2478	*/
AnnaBridge	189:f392fc9709a3	2479	#define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
AnnaBridge	189:f392fc9709a3	2480
AnnaBridge	189:f392fc9709a3	2481	/**
AnnaBridge	189:f392fc9709a3	2482	* @brief Macro to Configure the SPI6 clock source.
AnnaBridge	189:f392fc9709a3	2483	* @param __RCC_SPI6CLKSource__: defines the SPI6 clock source. This clock is derived
AnnaBridge	189:f392fc9709a3	2484	* from system PCLK, PLL2, PLL3, OSC
AnnaBridge	189:f392fc9709a3	2485	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2486	* @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
AnnaBridge	189:f392fc9709a3	2487	* @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
AnnaBridge	189:f392fc9709a3	2488	* @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
AnnaBridge	189:f392fc9709a3	2489	* @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
AnnaBridge	189:f392fc9709a3	2490	* @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
AnnaBridge	189:f392fc9709a3	2491	* @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
AnnaBridge	189:f392fc9709a3	2492	* @retval None
AnnaBridge	189:f392fc9709a3	2493	*/
AnnaBridge	189:f392fc9709a3	2494	#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
AnnaBridge	189:f392fc9709a3	2495	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
AnnaBridge	189:f392fc9709a3	2496
AnnaBridge	189:f392fc9709a3	2497	/** @brief Macro to get the SPI6 clock source.
AnnaBridge	189:f392fc9709a3	2498	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2499	* @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
AnnaBridge	189:f392fc9709a3	2500	* @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
AnnaBridge	189:f392fc9709a3	2501	* @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
AnnaBridge	189:f392fc9709a3	2502	* @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
AnnaBridge	189:f392fc9709a3	2503	* @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
AnnaBridge	189:f392fc9709a3	2504	* @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
AnnaBridge	189:f392fc9709a3	2505	*/
AnnaBridge	189:f392fc9709a3	2506	#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
AnnaBridge	189:f392fc9709a3	2507
AnnaBridge	189:f392fc9709a3	2508	/** @brief Macro to configure the SDMMC clock
AnnaBridge	189:f392fc9709a3	2509	* @param __SDMMCCLKSource__: specifies clock source for SDMMC
AnnaBridge	189:f392fc9709a3	2510	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2511	* @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock
AnnaBridge	189:f392fc9709a3	2512	* @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
AnnaBridge	189:f392fc9709a3	2513	*/
AnnaBridge	189:f392fc9709a3	2514	#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
AnnaBridge	189:f392fc9709a3	2515	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
AnnaBridge	189:f392fc9709a3	2516
AnnaBridge	189:f392fc9709a3	2517	/** @brief Macro to get the SDMMC clock
AnnaBridge	189:f392fc9709a3	2518	*/
AnnaBridge	189:f392fc9709a3	2519	#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
AnnaBridge	189:f392fc9709a3	2520
AnnaBridge	189:f392fc9709a3	2521	/** @brief macro to configure the RNG clock (RNGCLK).
AnnaBridge	189:f392fc9709a3	2522	*
AnnaBridge	189:f392fc9709a3	2523	* @param __RNGCLKSource__: specifies the RNG clock source.
AnnaBridge	189:f392fc9709a3	2524	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2525	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
AnnaBridge	189:f392fc9709a3	2526	* @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
AnnaBridge	189:f392fc9709a3	2527	* @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
AnnaBridge	189:f392fc9709a3	2528	* @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
AnnaBridge	189:f392fc9709a3	2529	*/
AnnaBridge	189:f392fc9709a3	2530	#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
AnnaBridge	189:f392fc9709a3	2531	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
AnnaBridge	189:f392fc9709a3	2532
AnnaBridge	189:f392fc9709a3	2533	/** @brief macro to get the RNG clock source.
AnnaBridge	189:f392fc9709a3	2534	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2535	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
AnnaBridge	189:f392fc9709a3	2536	* @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
AnnaBridge	189:f392fc9709a3	2537	* @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
AnnaBridge	189:f392fc9709a3	2538	* @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
AnnaBridge	189:f392fc9709a3	2539	*/
AnnaBridge	189:f392fc9709a3	2540	#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
AnnaBridge	189:f392fc9709a3	2541
AnnaBridge	189:f392fc9709a3	2542
AnnaBridge	189:f392fc9709a3	2543	/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
AnnaBridge	189:f392fc9709a3	2544	* @{
AnnaBridge	189:f392fc9709a3	2545	*/
AnnaBridge	189:f392fc9709a3	2546	/** @brief Macro to configure the HRTIM1 prescaler clock source.
AnnaBridge	189:f392fc9709a3	2547	* @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.
AnnaBridge	189:f392fc9709a3	2548	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2549	* @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock
AnnaBridge	189:f392fc9709a3	2550	* @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
AnnaBridge	189:f392fc9709a3	2551	*/
AnnaBridge	189:f392fc9709a3	2552	#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
AnnaBridge	189:f392fc9709a3	2553	MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
AnnaBridge	189:f392fc9709a3	2554
AnnaBridge	189:f392fc9709a3	2555	/** @brief Macro to get the HRTIM1 clock source.
AnnaBridge	189:f392fc9709a3	2556	* @retval The clock source can be one of the following values:
AnnaBridge	189:f392fc9709a3	2557	* @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock
AnnaBridge	189:f392fc9709a3	2558	* @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
AnnaBridge	189:f392fc9709a3	2559	*/
AnnaBridge	189:f392fc9709a3	2560	#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
AnnaBridge	189:f392fc9709a3	2561
AnnaBridge	189:f392fc9709a3	2562	/** @brief Macro to configure the Timers clocks prescalers
AnnaBridge	189:f392fc9709a3	2563	* @param __PRESC__ : specifies the Timers clocks prescalers selection
AnnaBridge	189:f392fc9709a3	2564	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2565	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge	189:f392fc9709a3	2566	* equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,
AnnaBridge	189:f392fc9709a3	2567	* else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
AnnaBridge	189:f392fc9709a3	2568	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge	189:f392fc9709a3	2569	* equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,
AnnaBridge	189:f392fc9709a3	2570	* else it is equal to 4 x Frcc_pclkx_d2
AnnaBridge	189:f392fc9709a3	2571	*/
AnnaBridge	189:f392fc9709a3	2572	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
AnnaBridge	189:f392fc9709a3	2573	RCC->CFGR \|= (__PRESC__); \
AnnaBridge	189:f392fc9709a3	2574	}while(0)
AnnaBridge	189:f392fc9709a3	2575
AnnaBridge	189:f392fc9709a3	2576	/**
AnnaBridge	189:f392fc9709a3	2577	* @}
AnnaBridge	189:f392fc9709a3	2578	*/
AnnaBridge	189:f392fc9709a3	2579	/**
AnnaBridge	189:f392fc9709a3	2580	* @brief Enable the specified CRS interrupts.
AnnaBridge	189:f392fc9709a3	2581	* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
AnnaBridge	189:f392fc9709a3	2582	* This parameter can be any combination of the following values:
AnnaBridge	189:f392fc9709a3	2583	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	189:f392fc9709a3	2584	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	189:f392fc9709a3	2585	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	189:f392fc9709a3	2586	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	189:f392fc9709a3	2587	* @retval None
AnnaBridge	189:f392fc9709a3	2588	*/
AnnaBridge	189:f392fc9709a3	2589	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	2590
AnnaBridge	189:f392fc9709a3	2591	/**
AnnaBridge	189:f392fc9709a3	2592	* @brief Disable the specified CRS interrupts.
AnnaBridge	189:f392fc9709a3	2593	* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
AnnaBridge	189:f392fc9709a3	2594	* This parameter can be any combination of the following values:
AnnaBridge	189:f392fc9709a3	2595	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	189:f392fc9709a3	2596	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	189:f392fc9709a3	2597	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	189:f392fc9709a3	2598	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	189:f392fc9709a3	2599	* @retval None
AnnaBridge	189:f392fc9709a3	2600	*/
AnnaBridge	189:f392fc9709a3	2601	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	2602
AnnaBridge	189:f392fc9709a3	2603	/** @brief Check whether the CRS interrupt has occurred or not.
AnnaBridge	189:f392fc9709a3	2604	* @param __INTERRUPT__ specifies the CRS interrupt source to check.
AnnaBridge	189:f392fc9709a3	2605	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2606	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	189:f392fc9709a3	2607	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	189:f392fc9709a3	2608	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	189:f392fc9709a3	2609	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	189:f392fc9709a3	2610	* @retval The new state of __INTERRUPT__ (SET or RESET).
AnnaBridge	189:f392fc9709a3	2611	*/
AnnaBridge	189:f392fc9709a3	2612	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
AnnaBridge	189:f392fc9709a3	2613
AnnaBridge	189:f392fc9709a3	2614	/** @brief Clear the CRS interrupt pending bits
AnnaBridge	189:f392fc9709a3	2615	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	189:f392fc9709a3	2616	* This parameter can be any combination of the following values:
AnnaBridge	189:f392fc9709a3	2617	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	189:f392fc9709a3	2618	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	189:f392fc9709a3	2619	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	189:f392fc9709a3	2620	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	189:f392fc9709a3	2621	* @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
AnnaBridge	189:f392fc9709a3	2622	* @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
AnnaBridge	189:f392fc9709a3	2623	* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
AnnaBridge	189:f392fc9709a3	2624	*/
AnnaBridge	189:f392fc9709a3	2625	/* CRS IT Error Mask */
AnnaBridge	189:f392fc9709a3	2626	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
AnnaBridge	189:f392fc9709a3	2627
AnnaBridge	189:f392fc9709a3	2628	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
AnnaBridge	189:f392fc9709a3	2629	if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
AnnaBridge	189:f392fc9709a3	2630	{ \
AnnaBridge	189:f392fc9709a3	2631	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
AnnaBridge	189:f392fc9709a3	2632	} \
AnnaBridge	189:f392fc9709a3	2633	else \
AnnaBridge	189:f392fc9709a3	2634	{ \
AnnaBridge	189:f392fc9709a3	2635	WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
AnnaBridge	189:f392fc9709a3	2636	} \
AnnaBridge	189:f392fc9709a3	2637	} while(0)
AnnaBridge	189:f392fc9709a3	2638
AnnaBridge	189:f392fc9709a3	2639	/**
AnnaBridge	189:f392fc9709a3	2640	* @brief Check whether the specified CRS flag is set or not.
AnnaBridge	189:f392fc9709a3	2641	* @param __FLAG__ specifies the flag to check.
AnnaBridge	189:f392fc9709a3	2642	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2643	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
AnnaBridge	189:f392fc9709a3	2644	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
AnnaBridge	189:f392fc9709a3	2645	* @arg @ref RCC_CRS_FLAG_ERR Error
AnnaBridge	189:f392fc9709a3	2646	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
AnnaBridge	189:f392fc9709a3	2647	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
AnnaBridge	189:f392fc9709a3	2648	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
AnnaBridge	189:f392fc9709a3	2649	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
AnnaBridge	189:f392fc9709a3	2650	* @retval The new state of _FLAG_ (TRUE or FALSE).
AnnaBridge	189:f392fc9709a3	2651	*/
AnnaBridge	189:f392fc9709a3	2652	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
AnnaBridge	189:f392fc9709a3	2653
AnnaBridge	189:f392fc9709a3	2654	/**
AnnaBridge	189:f392fc9709a3	2655	* @brief Clear the CRS specified FLAG.
AnnaBridge	189:f392fc9709a3	2656	* @param __FLAG__ specifies the flag to clear.
AnnaBridge	189:f392fc9709a3	2657	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2658	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
AnnaBridge	189:f392fc9709a3	2659	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
AnnaBridge	189:f392fc9709a3	2660	* @arg @ref RCC_CRS_FLAG_ERR Error
AnnaBridge	189:f392fc9709a3	2661	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
AnnaBridge	189:f392fc9709a3	2662	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
AnnaBridge	189:f392fc9709a3	2663	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
AnnaBridge	189:f392fc9709a3	2664	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
AnnaBridge	189:f392fc9709a3	2665	* @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
AnnaBridge	189:f392fc9709a3	2666	* @retval None
AnnaBridge	189:f392fc9709a3	2667	*/
AnnaBridge	189:f392fc9709a3	2668
AnnaBridge	189:f392fc9709a3	2669	/* CRS Flag Error Mask */
AnnaBridge	189:f392fc9709a3	2670	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
AnnaBridge	189:f392fc9709a3	2671
AnnaBridge	189:f392fc9709a3	2672	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
AnnaBridge	189:f392fc9709a3	2673	if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
AnnaBridge	189:f392fc9709a3	2674	{ \
AnnaBridge	189:f392fc9709a3	2675	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
AnnaBridge	189:f392fc9709a3	2676	} \
AnnaBridge	189:f392fc9709a3	2677	else \
AnnaBridge	189:f392fc9709a3	2678	{ \
AnnaBridge	189:f392fc9709a3	2679	WRITE_REG(CRS->ICR, (__FLAG__)); \
AnnaBridge	189:f392fc9709a3	2680	} \
AnnaBridge	189:f392fc9709a3	2681	} while(0)
AnnaBridge	189:f392fc9709a3	2682
AnnaBridge	189:f392fc9709a3	2683	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
AnnaBridge	189:f392fc9709a3	2684	* @{
AnnaBridge	189:f392fc9709a3	2685	*/
AnnaBridge	189:f392fc9709a3	2686	/**
AnnaBridge	189:f392fc9709a3	2687	* @brief Enable the oscillator clock for frequency error counter.
AnnaBridge	189:f392fc9709a3	2688	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge	189:f392fc9709a3	2689	* @retval None
AnnaBridge	189:f392fc9709a3	2690	*/
AnnaBridge	189:f392fc9709a3	2691	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge	189:f392fc9709a3	2692
AnnaBridge	189:f392fc9709a3	2693	/**
AnnaBridge	189:f392fc9709a3	2694	* @brief Disable the oscillator clock for frequency error counter.
AnnaBridge	189:f392fc9709a3	2695	* @retval None
AnnaBridge	189:f392fc9709a3	2696	*/
AnnaBridge	189:f392fc9709a3	2697	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge	189:f392fc9709a3	2698
AnnaBridge	189:f392fc9709a3	2699	/**
AnnaBridge	189:f392fc9709a3	2700	* @brief Enable the automatic hardware adjustment of TRIM bits.
AnnaBridge	189:f392fc9709a3	2701	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge	189:f392fc9709a3	2702	* @retval None
AnnaBridge	189:f392fc9709a3	2703	*/
AnnaBridge	189:f392fc9709a3	2704	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge	189:f392fc9709a3	2705
AnnaBridge	189:f392fc9709a3	2706	/**
AnnaBridge	189:f392fc9709a3	2707	* @brief Enable or disable the automatic hardware adjustment of TRIM bits.
AnnaBridge	189:f392fc9709a3	2708	* @retval None
AnnaBridge	189:f392fc9709a3	2709	*/
AnnaBridge	189:f392fc9709a3	2710	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge	189:f392fc9709a3	2711
AnnaBridge	189:f392fc9709a3	2712	/**
AnnaBridge	189:f392fc9709a3	2713	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
AnnaBridge	189:f392fc9709a3	2714	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
AnnaBridge	189:f392fc9709a3	2715	* of the synchronization source after pre-scaling. It is then decreased by one in order to
AnnaBridge	189:f392fc9709a3	2716	* reach the expected synchronization on the zero value. The formula is the following:
AnnaBridge	189:f392fc9709a3	2717	* RELOAD = (fTARGET / fSYNC) -1
AnnaBridge	189:f392fc9709a3	2718	* @param __FTARGET__ Target frequency (value in Hz)
AnnaBridge	189:f392fc9709a3	2719	* @param __FSYNC__ Synchronization signal frequency (value in Hz)
AnnaBridge	189:f392fc9709a3	2720	* @retval None
AnnaBridge	189:f392fc9709a3	2721	*/
AnnaBridge	189:f392fc9709a3	2722	#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
AnnaBridge	189:f392fc9709a3	2723
AnnaBridge	189:f392fc9709a3	2724
AnnaBridge	189:f392fc9709a3	2725	/**
AnnaBridge	189:f392fc9709a3	2726	* @}
AnnaBridge	189:f392fc9709a3	2727	*/
AnnaBridge	189:f392fc9709a3	2728
AnnaBridge	189:f392fc9709a3	2729
AnnaBridge	189:f392fc9709a3	2730	/**
AnnaBridge	189:f392fc9709a3	2731	* @}
AnnaBridge	189:f392fc9709a3	2732	*/
AnnaBridge	189:f392fc9709a3	2733
AnnaBridge	189:f392fc9709a3	2734
AnnaBridge	189:f392fc9709a3	2735	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	2736	/** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge	189:f392fc9709a3	2737	* @{
AnnaBridge	189:f392fc9709a3	2738	*/
AnnaBridge	189:f392fc9709a3	2739	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	189:f392fc9709a3	2740	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	189:f392fc9709a3	2741	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge	189:f392fc9709a3	2742	uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
AnnaBridge	189:f392fc9709a3	2743	uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
AnnaBridge	189:f392fc9709a3	2744	uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
AnnaBridge	189:f392fc9709a3	2745	void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
AnnaBridge	189:f392fc9709a3	2746	void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
AnnaBridge	189:f392fc9709a3	2747	void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
AnnaBridge	189:f392fc9709a3	2748	/**
AnnaBridge	189:f392fc9709a3	2749	* @}
AnnaBridge	189:f392fc9709a3	2750	*/
AnnaBridge	189:f392fc9709a3	2751
AnnaBridge	189:f392fc9709a3	2752	/** @addtogroup RCCEx_Exported_Functions_Group2
AnnaBridge	189:f392fc9709a3	2753	* @{
AnnaBridge	189:f392fc9709a3	2754	*/
AnnaBridge	189:f392fc9709a3	2755	void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
AnnaBridge	189:f392fc9709a3	2756	void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
AnnaBridge	189:f392fc9709a3	2757	void HAL_RCCEx_EnableLSECSS(void);
AnnaBridge	189:f392fc9709a3	2758	void HAL_RCCEx_DisableLSECSS(void);
AnnaBridge	189:f392fc9709a3	2759	void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
AnnaBridge	189:f392fc9709a3	2760	/**
AnnaBridge	189:f392fc9709a3	2761	* @}
AnnaBridge	189:f392fc9709a3	2762	*/
AnnaBridge	189:f392fc9709a3	2763
AnnaBridge	189:f392fc9709a3	2764
AnnaBridge	189:f392fc9709a3	2765	/** @addtogroup RCCEx_Exported_Functions_Group3
AnnaBridge	189:f392fc9709a3	2766	* @{
AnnaBridge	189:f392fc9709a3	2767	*/
AnnaBridge	189:f392fc9709a3	2768
AnnaBridge	189:f392fc9709a3	2769	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
AnnaBridge	189:f392fc9709a3	2770	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
AnnaBridge	189:f392fc9709a3	2771	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
AnnaBridge	189:f392fc9709a3	2772	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
AnnaBridge	189:f392fc9709a3	2773	void HAL_RCCEx_CRS_IRQHandler(void);
AnnaBridge	189:f392fc9709a3	2774	void HAL_RCCEx_CRS_SyncOkCallback(void);
AnnaBridge	189:f392fc9709a3	2775	void HAL_RCCEx_CRS_SyncWarnCallback(void);
AnnaBridge	189:f392fc9709a3	2776	void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
AnnaBridge	189:f392fc9709a3	2777	void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
AnnaBridge	189:f392fc9709a3	2778
AnnaBridge	189:f392fc9709a3	2779	/**
AnnaBridge	189:f392fc9709a3	2780	* @}
AnnaBridge	189:f392fc9709a3	2781	*/
AnnaBridge	189:f392fc9709a3	2782
AnnaBridge	189:f392fc9709a3	2783	/* Private macros ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	2784	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
AnnaBridge	189:f392fc9709a3	2785	* @{
AnnaBridge	189:f392fc9709a3	2786	*/
AnnaBridge	189:f392fc9709a3	2787	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
AnnaBridge	189:f392fc9709a3	2788	* @{
AnnaBridge	189:f392fc9709a3	2789	*/
AnnaBridge	189:f392fc9709a3	2790
AnnaBridge	189:f392fc9709a3	2791	#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) \|\| \
AnnaBridge	189:f392fc9709a3	2792	((VALUE) == RCC_PLL2_DIVQ) \|\| \
AnnaBridge	189:f392fc9709a3	2793	((VALUE) == RCC_PLL2_DIVR))
AnnaBridge	189:f392fc9709a3	2794
AnnaBridge	189:f392fc9709a3	2795	#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) \|\| \
AnnaBridge	189:f392fc9709a3	2796	((VALUE) == RCC_PLL3_DIVQ) \|\| \
AnnaBridge	189:f392fc9709a3	2797	((VALUE) == RCC_PLL3_DIVR))
AnnaBridge	189:f392fc9709a3	2798
AnnaBridge	189:f392fc9709a3	2799	#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)\|\| \
AnnaBridge	189:f392fc9709a3	2800	((SOURCE) == RCC_USART16CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2801	((SOURCE) == RCC_USART16CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2802	((SOURCE) == RCC_USART16CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2803	((SOURCE) == RCC_USART16CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2804	((SOURCE) == RCC_USART16CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2805
AnnaBridge	189:f392fc9709a3	2806	#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2807	((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2808	((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2809	((SOURCE) == RCC_USART234578CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2810	((SOURCE) == RCC_USART234578CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2811	((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2812
AnnaBridge	189:f392fc9709a3	2813	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)\|\| \
AnnaBridge	189:f392fc9709a3	2814	((SOURCE) == RCC_USART1CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2815	((SOURCE) == RCC_USART1CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2816	((SOURCE) == RCC_USART1CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2817	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2818	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2819
AnnaBridge	189:f392fc9709a3	2820	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2821	((SOURCE) == RCC_USART2CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2822	((SOURCE) == RCC_USART2CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2823	((SOURCE) == RCC_USART2CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2824	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2825	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2826
AnnaBridge	189:f392fc9709a3	2827	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2828	((SOURCE) == RCC_USART3CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2829	((SOURCE) == RCC_USART3CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2830	((SOURCE) == RCC_USART3CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2831	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2832	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2833
AnnaBridge	189:f392fc9709a3	2834	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	189:f392fc9709a3	2835	((SOURCE) == RCC_UART4CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2836	((SOURCE) == RCC_UART4CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2837	((SOURCE) == RCC_UART4CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2838	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2839	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2840
AnnaBridge	189:f392fc9709a3	2841	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	189:f392fc9709a3	2842	((SOURCE) == RCC_UART5CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2843	((SOURCE) == RCC_UART5CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2844	((SOURCE) == RCC_UART5CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2845	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2846	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2847
AnnaBridge	189:f392fc9709a3	2848	#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)\|\| \
AnnaBridge	189:f392fc9709a3	2849	((SOURCE) == RCC_USART6CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2850	((SOURCE) == RCC_USART6CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2851	((SOURCE) == RCC_USART6CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2852	((SOURCE) == RCC_USART6CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2853	((SOURCE) == RCC_USART6CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2854
AnnaBridge	189:f392fc9709a3	2855	#define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2856	((SOURCE) == RCC_UART7CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2857	((SOURCE) == RCC_UART7CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2858	((SOURCE) == RCC_UART7CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2859	((SOURCE) == RCC_UART7CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2860	((SOURCE) == RCC_UART7CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2861
AnnaBridge	189:f392fc9709a3	2862	#define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2863	((SOURCE) == RCC_UART8CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2864	((SOURCE) == RCC_UART8CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2865	((SOURCE) == RCC_UART8CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2866	((SOURCE) == RCC_UART8CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2867	((SOURCE) == RCC_UART8CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2868
AnnaBridge	189:f392fc9709a3	2869	#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) \|\| \
AnnaBridge	189:f392fc9709a3	2870	((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2871	((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2872	((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2873	((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2874	((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	2875
AnnaBridge	189:f392fc9709a3	2876	#define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2877	((SOURCE) == RCC_I2C123CLKSOURCE_HSI) \|\| \
AnnaBridge	189:f392fc9709a3	2878	((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2879	((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
AnnaBridge	189:f392fc9709a3	2880
AnnaBridge	189:f392fc9709a3	2881	#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2882	((SOURCE) == RCC_I2C1CLKSOURCE_HSI) \|\| \
AnnaBridge	189:f392fc9709a3	2883	((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2884	((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
AnnaBridge	189:f392fc9709a3	2885
AnnaBridge	189:f392fc9709a3	2886	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2887	((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
AnnaBridge	189:f392fc9709a3	2888	((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2889	((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
AnnaBridge	189:f392fc9709a3	2890
AnnaBridge	189:f392fc9709a3	2891	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2892	((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
AnnaBridge	189:f392fc9709a3	2893	((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2894	((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
AnnaBridge	189:f392fc9709a3	2895
AnnaBridge	189:f392fc9709a3	2896	#define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2897	((SOURCE) == RCC_I2C4CLKSOURCE_HSI) \|\| \
AnnaBridge	189:f392fc9709a3	2898	((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2899	((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
AnnaBridge	189:f392fc9709a3	2900
AnnaBridge	189:f392fc9709a3	2901	#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)\|\| \
AnnaBridge	189:f392fc9709a3	2902	((SOURCE) == RCC_RNGCLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	2903	((SOURCE) == RCC_RNGCLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	2904	((SOURCE) == RCC_RNGCLKSOURCE_LSI))
AnnaBridge	189:f392fc9709a3	2905
AnnaBridge	189:f392fc9709a3	2906	#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) \|\| \
AnnaBridge	189:f392fc9709a3	2907	((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
AnnaBridge	189:f392fc9709a3	2908
AnnaBridge	189:f392fc9709a3	2909	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	2910	((SOURCE) == RCC_USBCLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2911	((SOURCE) == RCC_USBCLKSOURCE_HSI48))
AnnaBridge	189:f392fc9709a3	2912
AnnaBridge	189:f392fc9709a3	2913	#define IS_RCC_SAI1CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2914	(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	2915	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2916	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2917	((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) \|\| \
AnnaBridge	189:f392fc9709a3	2918	((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
AnnaBridge	189:f392fc9709a3	2919
AnnaBridge	189:f392fc9709a3	2920	#define IS_RCC_SAI23CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2921	(((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	2922	((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2923	((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2924	((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) \|\| \
AnnaBridge	189:f392fc9709a3	2925	((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
AnnaBridge	189:f392fc9709a3	2926
AnnaBridge	189:f392fc9709a3	2927	#define IS_RCC_SAI2CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2928	(((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	2929	((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2930	((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2931	((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) \|\| \
AnnaBridge	189:f392fc9709a3	2932	((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
AnnaBridge	189:f392fc9709a3	2933
AnnaBridge	189:f392fc9709a3	2934	#define IS_RCC_SAI3CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2935	(((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	2936	((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2937	((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2938	((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) \|\| \
AnnaBridge	189:f392fc9709a3	2939	((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
AnnaBridge	189:f392fc9709a3	2940
AnnaBridge	189:f392fc9709a3	2941	#define IS_RCC_SPI123CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2942	(((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	2943	((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2944	((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2945	((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) \|\| \
AnnaBridge	189:f392fc9709a3	2946	((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
AnnaBridge	189:f392fc9709a3	2947
AnnaBridge	189:f392fc9709a3	2948	#define IS_RCC_SPI1CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2949	(((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	2950	((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2951	((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2952	((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) \|\| \
AnnaBridge	189:f392fc9709a3	2953	((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
AnnaBridge	189:f392fc9709a3	2954
AnnaBridge	189:f392fc9709a3	2955	#define IS_RCC_SPI2CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2956	(((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	2957	((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2958	((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2959	((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) \|\| \
AnnaBridge	189:f392fc9709a3	2960	((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
AnnaBridge	189:f392fc9709a3	2961
AnnaBridge	189:f392fc9709a3	2962	#define IS_RCC_SPI3CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2963	(((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	2964	((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2965	((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2966	((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) \|\| \
AnnaBridge	189:f392fc9709a3	2967	((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
AnnaBridge	189:f392fc9709a3	2968
AnnaBridge	189:f392fc9709a3	2969	#define IS_RCC_SPI45CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2970	(((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	189:f392fc9709a3	2971	((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2972	((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2973	((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) \|\| \
AnnaBridge	189:f392fc9709a3	2974	((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2975	((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
AnnaBridge	189:f392fc9709a3	2976
AnnaBridge	189:f392fc9709a3	2977	#define IS_RCC_SPI4CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2978	(((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	189:f392fc9709a3	2979	((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2980	((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2981	((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) \|\| \
AnnaBridge	189:f392fc9709a3	2982	((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2983	((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
AnnaBridge	189:f392fc9709a3	2984
AnnaBridge	189:f392fc9709a3	2985	#define IS_RCC_SPI5CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2986	(((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	2987	((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2988	((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2989	((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) \|\| \
AnnaBridge	189:f392fc9709a3	2990	((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2991	((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
AnnaBridge	189:f392fc9709a3	2992
AnnaBridge	189:f392fc9709a3	2993	#define IS_RCC_SPI6CLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	2994	(((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) \|\| \
AnnaBridge	189:f392fc9709a3	2995	((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	2996	((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	2997	((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) \|\| \
AnnaBridge	189:f392fc9709a3	2998	((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	2999	((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
AnnaBridge	189:f392fc9709a3	3000
AnnaBridge	189:f392fc9709a3	3001	#define IS_RCC_SAI4ACLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	3002	(((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	3003	((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3004	((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	3005	((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) \|\| \
AnnaBridge	189:f392fc9709a3	3006	((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
AnnaBridge	189:f392fc9709a3	3007
AnnaBridge	189:f392fc9709a3	3008	#define IS_RCC_SAI4BCLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	3009	(((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	3010	((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3011	((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	3012	((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) \|\| \
AnnaBridge	189:f392fc9709a3	3013	((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
AnnaBridge	189:f392fc9709a3	3014
AnnaBridge	189:f392fc9709a3	3015	#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
AnnaBridge	189:f392fc9709a3	3016	#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
AnnaBridge	189:f392fc9709a3	3017	#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	189:f392fc9709a3	3018	#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	189:f392fc9709a3	3019	#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	189:f392fc9709a3	3020
AnnaBridge	189:f392fc9709a3	3021	#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
AnnaBridge	189:f392fc9709a3	3022	#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
AnnaBridge	189:f392fc9709a3	3023	#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	189:f392fc9709a3	3024	#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	189:f392fc9709a3	3025	#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	189:f392fc9709a3	3026
AnnaBridge	189:f392fc9709a3	3027	#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) \|\| \
AnnaBridge	189:f392fc9709a3	3028	((VALUE) == RCC_PLL2VCIRANGE_1) \|\| \
AnnaBridge	189:f392fc9709a3	3029	((VALUE) == RCC_PLL2VCIRANGE_2) \|\| \
AnnaBridge	189:f392fc9709a3	3030	((VALUE) == RCC_PLL2VCIRANGE_3))
AnnaBridge	189:f392fc9709a3	3031
AnnaBridge	189:f392fc9709a3	3032	#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) \|\| \
AnnaBridge	189:f392fc9709a3	3033	((VALUE) == RCC_PLL3VCIRANGE_1) \|\| \
AnnaBridge	189:f392fc9709a3	3034	((VALUE) == RCC_PLL3VCIRANGE_2) \|\| \
AnnaBridge	189:f392fc9709a3	3035	((VALUE) == RCC_PLL3VCIRANGE_3))
AnnaBridge	189:f392fc9709a3	3036
AnnaBridge	189:f392fc9709a3	3037	#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) \|\| \
AnnaBridge	189:f392fc9709a3	3038	((VALUE) == RCC_PLL2VCOMEDIUM))
AnnaBridge	189:f392fc9709a3	3039
AnnaBridge	189:f392fc9709a3	3040	#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) \|\| \
AnnaBridge	189:f392fc9709a3	3041	((VALUE) == RCC_PLL3VCOMEDIUM))
AnnaBridge	189:f392fc9709a3	3042
AnnaBridge	189:f392fc9709a3	3043	#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
AnnaBridge	189:f392fc9709a3	3044
AnnaBridge	189:f392fc9709a3	3045	#define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	3046	((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3047	((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	3048	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	3049	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
AnnaBridge	189:f392fc9709a3	3050	((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
AnnaBridge	189:f392fc9709a3	3051
AnnaBridge	189:f392fc9709a3	3052	#define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	3053	((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3054	((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	3055	((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	3056	((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) \|\| \
AnnaBridge	189:f392fc9709a3	3057	((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
AnnaBridge	189:f392fc9709a3	3058
AnnaBridge	189:f392fc9709a3	3059	#define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	3060	((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3061	((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	3062	((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	3063	((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) \|\| \
AnnaBridge	189:f392fc9709a3	3064	((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
AnnaBridge	189:f392fc9709a3	3065
AnnaBridge	189:f392fc9709a3	3066	#define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	3067	((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3068	((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	3069	((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	3070	((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) \|\| \
AnnaBridge	189:f392fc9709a3	3071	((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
AnnaBridge	189:f392fc9709a3	3072
AnnaBridge	189:f392fc9709a3	3073	#define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	3074	((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3075	((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	3076	((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	3077	((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) \|\| \
AnnaBridge	189:f392fc9709a3	3078	((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
AnnaBridge	189:f392fc9709a3	3079
AnnaBridge	189:f392fc9709a3	3080	#define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	189:f392fc9709a3	3081	((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3082	((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	3083	((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	3084	((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) \|\| \
AnnaBridge	189:f392fc9709a3	3085	((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
AnnaBridge	189:f392fc9709a3	3086
AnnaBridge	189:f392fc9709a3	3087	#define IS_RCC_QSPICLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	3088	(((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) \|\| \
AnnaBridge	189:f392fc9709a3	3089	((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	3090	((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3091	((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
AnnaBridge	189:f392fc9709a3	3092
AnnaBridge	189:f392fc9709a3	3093	#define IS_RCC_FMCCLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	3094	(((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) \|\| \
AnnaBridge	189:f392fc9709a3	3095	((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	3096	((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3097	((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
AnnaBridge	189:f392fc9709a3	3098
AnnaBridge	189:f392fc9709a3	3099	#if defined(FDCAN1) \|\| defined(FDCAN2)
AnnaBridge	189:f392fc9709a3	3100	#define IS_RCC_FDCANCLK(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	3101	(((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) \|\| \
AnnaBridge	189:f392fc9709a3	3102	((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	3103	((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
AnnaBridge	189:f392fc9709a3	3104	#endif /FDCAN1 \|\| FDCAN2/
AnnaBridge	189:f392fc9709a3	3105
AnnaBridge	189:f392fc9709a3	3106	#define IS_RCC_SDMMC(__SOURCE__) \
AnnaBridge	189:f392fc9709a3	3107	(((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	3108	((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
AnnaBridge	189:f392fc9709a3	3109
AnnaBridge	189:f392fc9709a3	3110	#define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3111	((SOURCE) == RCC_ADCCLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	3112	((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
AnnaBridge	189:f392fc9709a3	3113
AnnaBridge	189:f392fc9709a3	3114	#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	189:f392fc9709a3	3115	((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	3116
AnnaBridge	189:f392fc9709a3	3117	#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	189:f392fc9709a3	3118	((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
AnnaBridge	189:f392fc9709a3	3119
AnnaBridge	189:f392fc9709a3	3120	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) \|\| \
AnnaBridge	189:f392fc9709a3	3121	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) \|\| \
AnnaBridge	189:f392fc9709a3	3122	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) \|\| \
AnnaBridge	189:f392fc9709a3	3123	((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
AnnaBridge	189:f392fc9709a3	3124
AnnaBridge	189:f392fc9709a3	3125	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	3126	((SOURCE) == RCC_CECCLKSOURCE_LSI) \|\| \
AnnaBridge	189:f392fc9709a3	3127	((SOURCE) == RCC_CECCLKSOURCE_CSI))
AnnaBridge	189:f392fc9709a3	3128
AnnaBridge	189:f392fc9709a3	3129	#define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) \|\| \
AnnaBridge	189:f392fc9709a3	3130	((SOURCE) == RCC_CLKPSOURCE_CSI) \|\| \
AnnaBridge	189:f392fc9709a3	3131	((SOURCE) == RCC_CLKPSOURCE_HSE))
AnnaBridge	189:f392fc9709a3	3132	#define IS_RCC_TIMPRES(VALUE) \
AnnaBridge	189:f392fc9709a3	3133	(((VALUE) == RCC_TIMPRES_DESACTIVATED) \|\| \
AnnaBridge	189:f392fc9709a3	3134	((VALUE) == RCC_TIMPRES_ACTIVATED))
AnnaBridge	189:f392fc9709a3	3135
AnnaBridge	189:f392fc9709a3	3136
AnnaBridge	189:f392fc9709a3	3137	#define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
AnnaBridge	189:f392fc9709a3	3138
AnnaBridge	189:f392fc9709a3	3139
AnnaBridge	189:f392fc9709a3	3140	#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) \|\| \
AnnaBridge	189:f392fc9709a3	3141	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
AnnaBridge	189:f392fc9709a3	3142	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1))
AnnaBridge	189:f392fc9709a3	3143
AnnaBridge	189:f392fc9709a3	3144	#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV2) \|\| \
AnnaBridge	189:f392fc9709a3	3145	((__DIV__) == RCC_CRS_SYNC_DIV4) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV8) \|\| \
AnnaBridge	189:f392fc9709a3	3146	((__DIV__) == RCC_CRS_SYNC_DIV16) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV32) \|\| \
AnnaBridge	189:f392fc9709a3	3147	((__DIV__) == RCC_CRS_SYNC_DIV64) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV128))
AnnaBridge	189:f392fc9709a3	3148
AnnaBridge	189:f392fc9709a3	3149	#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
AnnaBridge	189:f392fc9709a3	3150	((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
AnnaBridge	189:f392fc9709a3	3151
AnnaBridge	189:f392fc9709a3	3152	#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
AnnaBridge	189:f392fc9709a3	3153
AnnaBridge	189:f392fc9709a3	3154	#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
AnnaBridge	189:f392fc9709a3	3155
AnnaBridge	189:f392fc9709a3	3156	#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
AnnaBridge	189:f392fc9709a3	3157
AnnaBridge	189:f392fc9709a3	3158	#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) \|\| \
AnnaBridge	189:f392fc9709a3	3159	((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
AnnaBridge	189:f392fc9709a3	3160	/**
AnnaBridge	189:f392fc9709a3	3161	* @}
AnnaBridge	189:f392fc9709a3	3162	*/
AnnaBridge	189:f392fc9709a3	3163
AnnaBridge	189:f392fc9709a3	3164	/**
AnnaBridge	189:f392fc9709a3	3165	* @}
AnnaBridge	189:f392fc9709a3	3166	*/
AnnaBridge	189:f392fc9709a3	3167	/**
AnnaBridge	189:f392fc9709a3	3168	* @}
AnnaBridge	189:f392fc9709a3	3169	*/
AnnaBridge	189:f392fc9709a3	3170
AnnaBridge	189:f392fc9709a3	3171	/**
AnnaBridge	189:f392fc9709a3	3172	* @}
AnnaBridge	189:f392fc9709a3	3173	*/
AnnaBridge	189:f392fc9709a3	3174
AnnaBridge	189:f392fc9709a3	3175	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	3176	}
AnnaBridge	189:f392fc9709a3	3177	#endif
AnnaBridge	189:f392fc9709a3	3178
AnnaBridge	189:f392fc9709a3	3179	#endif /* STM32H7xx_HAL_RCC_EX_H */
AnnaBridge	189:f392fc9709a3	3180
AnnaBridge	189:f392fc9709a3	3181	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/