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targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32h7xx_hal_rcc.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of RCC HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. |
| AnnaBridge | 189:f392fc9709a3 | 10 | * All rights reserved.</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 11 | * |
| AnnaBridge | 189:f392fc9709a3 | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| AnnaBridge | 189:f392fc9709a3 | 13 | * the "License"; You may not use this file except in compliance with the |
| AnnaBridge | 189:f392fc9709a3 | 14 | * License. You may obtain a copy of the License at: |
| AnnaBridge | 189:f392fc9709a3 | 15 | * opensource.org/licenses/BSD-3-Clause |
| AnnaBridge | 189:f392fc9709a3 | 16 | * |
| AnnaBridge | 189:f392fc9709a3 | 17 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 18 | */ |
| AnnaBridge | 189:f392fc9709a3 | 19 | |
| AnnaBridge | 189:f392fc9709a3 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 21 | #ifndef STM32H7xx_HAL_RCC_H |
| AnnaBridge | 189:f392fc9709a3 | 22 | #define STM32H7xx_HAL_RCC_H |
| AnnaBridge | 189:f392fc9709a3 | 23 | |
| AnnaBridge | 189:f392fc9709a3 | 24 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 25 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 26 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 27 | |
| AnnaBridge | 189:f392fc9709a3 | 28 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 29 | #include "stm32h7xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 30 | |
| AnnaBridge | 189:f392fc9709a3 | 31 | /** @addtogroup STM32H7xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 32 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 33 | */ |
| AnnaBridge | 189:f392fc9709a3 | 34 | |
| AnnaBridge | 189:f392fc9709a3 | 35 | /** @addtogroup RCC |
| AnnaBridge | 189:f392fc9709a3 | 36 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 37 | */ |
| AnnaBridge | 189:f392fc9709a3 | 38 | |
| AnnaBridge | 189:f392fc9709a3 | 39 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 40 | |
| AnnaBridge | 189:f392fc9709a3 | 41 | /** @defgroup RCC_Exported_Types RCC Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 42 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 43 | */ |
| AnnaBridge | 189:f392fc9709a3 | 44 | |
| AnnaBridge | 189:f392fc9709a3 | 45 | /** |
| AnnaBridge | 189:f392fc9709a3 | 46 | * @brief RCC PLL configuration structure definition |
| AnnaBridge | 189:f392fc9709a3 | 47 | */ |
| AnnaBridge | 189:f392fc9709a3 | 48 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 49 | { |
| AnnaBridge | 189:f392fc9709a3 | 50 | uint32_t PLLState; /*!< The new state of the PLL. |
| AnnaBridge | 189:f392fc9709a3 | 51 | This parameter can be a value of @ref RCC_PLL_Config */ |
| AnnaBridge | 189:f392fc9709a3 | 52 | |
| AnnaBridge | 189:f392fc9709a3 | 53 | uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. |
| AnnaBridge | 189:f392fc9709a3 | 54 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 55 | |
| AnnaBridge | 189:f392fc9709a3 | 56 | uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. |
| AnnaBridge | 189:f392fc9709a3 | 57 | This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ |
| AnnaBridge | 189:f392fc9709a3 | 58 | |
| AnnaBridge | 189:f392fc9709a3 | 59 | uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. |
| AnnaBridge | 189:f392fc9709a3 | 60 | This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ |
| AnnaBridge | 189:f392fc9709a3 | 61 | |
| AnnaBridge | 189:f392fc9709a3 | 62 | uint32_t PLLP; /*!< PLLP: Division factor for system clock. |
| AnnaBridge | 189:f392fc9709a3 | 63 | This parameter must be a number between Min_Data = 2 and Max_Data = 128 |
| AnnaBridge | 189:f392fc9709a3 | 64 | odd division factors are not allowed */ |
| AnnaBridge | 189:f392fc9709a3 | 65 | |
| AnnaBridge | 189:f392fc9709a3 | 66 | uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. |
| AnnaBridge | 189:f392fc9709a3 | 67 | This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ |
| AnnaBridge | 189:f392fc9709a3 | 68 | |
| AnnaBridge | 189:f392fc9709a3 | 69 | uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. |
| AnnaBridge | 189:f392fc9709a3 | 70 | This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ |
| AnnaBridge | 189:f392fc9709a3 | 71 | uint32_t PLLRGE; /*!<PLLRGE: PLL1 clock Input range |
| AnnaBridge | 189:f392fc9709a3 | 72 | This parameter must be a value of @ref RCC_PLL1_VCI_Range */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | uint32_t PLLVCOSEL; /*!<PLLVCOSEL: PLL1 clock Output range |
| AnnaBridge | 189:f392fc9709a3 | 74 | This parameter must be a value of @ref RCC_PLL1_VCO_Range */ |
| AnnaBridge | 189:f392fc9709a3 | 75 | |
| AnnaBridge | 189:f392fc9709a3 | 76 | uint32_t PLLFRACN; /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for |
| AnnaBridge | 189:f392fc9709a3 | 77 | PLL1 VCO It should be a value between 0 and 8191 */ |
| AnnaBridge | 189:f392fc9709a3 | 78 | |
| AnnaBridge | 189:f392fc9709a3 | 79 | }RCC_PLLInitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 80 | |
| AnnaBridge | 189:f392fc9709a3 | 81 | |
| AnnaBridge | 189:f392fc9709a3 | 82 | /** |
| AnnaBridge | 189:f392fc9709a3 | 83 | * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition |
| AnnaBridge | 189:f392fc9709a3 | 84 | */ |
| AnnaBridge | 189:f392fc9709a3 | 85 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 86 | { |
| AnnaBridge | 189:f392fc9709a3 | 87 | uint32_t OscillatorType; /*!< The oscillators to be configured. |
| AnnaBridge | 189:f392fc9709a3 | 88 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | |
| AnnaBridge | 189:f392fc9709a3 | 90 | uint32_t HSEState; /*!< The new state of the HSE. |
| AnnaBridge | 189:f392fc9709a3 | 91 | This parameter can be a value of @ref RCC_HSE_Config */ |
| AnnaBridge | 189:f392fc9709a3 | 92 | |
| AnnaBridge | 189:f392fc9709a3 | 93 | uint32_t LSEState; /*!< The new state of the LSE. |
| AnnaBridge | 189:f392fc9709a3 | 94 | This parameter can be a value of @ref RCC_LSE_Config */ |
| AnnaBridge | 189:f392fc9709a3 | 95 | |
| AnnaBridge | 189:f392fc9709a3 | 96 | uint32_t HSIState; /*!< The new state of the HSI. |
| AnnaBridge | 189:f392fc9709a3 | 97 | This parameter can be a value of @ref RCC_HSI_Config */ |
| AnnaBridge | 189:f392fc9709a3 | 98 | |
| AnnaBridge | 189:f392fc9709a3 | 99 | uint32_t HSICalibrationValue; /*!< The calibration trimming value. |
| AnnaBridge | 189:f392fc9709a3 | 100 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F */ |
| AnnaBridge | 189:f392fc9709a3 | 101 | |
| AnnaBridge | 189:f392fc9709a3 | 102 | uint32_t LSIState; /*!< The new state of the LSI. |
| AnnaBridge | 189:f392fc9709a3 | 103 | This parameter can be a value of @ref RCC_LSI_Config */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | |
| AnnaBridge | 189:f392fc9709a3 | 105 | uint32_t HSI48State; /*!< The new state of the HSI48. |
| AnnaBridge | 189:f392fc9709a3 | 106 | This parameter can be a value of @ref RCC_HSI48_Config */ |
| AnnaBridge | 189:f392fc9709a3 | 107 | |
| AnnaBridge | 189:f392fc9709a3 | 108 | uint32_t CSIState; /*!< The new state of the CSI. |
| AnnaBridge | 189:f392fc9709a3 | 109 | This parameter can be a value of @ref RCC_CSI_Config */ |
| AnnaBridge | 189:f392fc9709a3 | 110 | |
| AnnaBridge | 189:f392fc9709a3 | 111 | uint32_t CSICalibrationValue; /*!< The calibration trimming value. |
| AnnaBridge | 189:f392fc9709a3 | 112 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
| AnnaBridge | 189:f392fc9709a3 | 113 | |
| AnnaBridge | 189:f392fc9709a3 | 114 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 115 | |
| AnnaBridge | 189:f392fc9709a3 | 116 | }RCC_OscInitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 117 | |
| AnnaBridge | 189:f392fc9709a3 | 118 | /** |
| AnnaBridge | 189:f392fc9709a3 | 119 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
| AnnaBridge | 189:f392fc9709a3 | 120 | */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 122 | { |
| AnnaBridge | 189:f392fc9709a3 | 123 | uint32_t ClockType; /*!< The clock to be configured. |
| AnnaBridge | 189:f392fc9709a3 | 124 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
| AnnaBridge | 189:f392fc9709a3 | 125 | |
| AnnaBridge | 189:f392fc9709a3 | 126 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
| AnnaBridge | 189:f392fc9709a3 | 127 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 128 | |
| AnnaBridge | 189:f392fc9709a3 | 129 | uint32_t SYSCLKDivider; /*!< The system clock divider. This parameter can be |
| AnnaBridge | 189:f392fc9709a3 | 130 | a value of @ref RCC_SYS_Clock_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 131 | |
| AnnaBridge | 189:f392fc9709a3 | 132 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
| AnnaBridge | 189:f392fc9709a3 | 133 | This parameter can be a value of @ref RCC_HCLK_Clock_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | |
| AnnaBridge | 189:f392fc9709a3 | 135 | uint32_t APB3CLKDivider; /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
| AnnaBridge | 189:f392fc9709a3 | 136 | This parameter can be a value of @ref RCC_APB3_Clock_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 137 | |
| AnnaBridge | 189:f392fc9709a3 | 138 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
| AnnaBridge | 189:f392fc9709a3 | 139 | This parameter can be a value of @ref RCC_APB1_Clock_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
| AnnaBridge | 189:f392fc9709a3 | 141 | This parameter can be a value of @ref RCC_APB2_Clock_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 142 | uint32_t APB4CLKDivider; /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
| AnnaBridge | 189:f392fc9709a3 | 143 | This parameter can be a value of @ref RCC_APB4_Clock_Source */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | }RCC_ClkInitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 145 | |
| AnnaBridge | 189:f392fc9709a3 | 146 | /** |
| AnnaBridge | 189:f392fc9709a3 | 147 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 148 | */ |
| AnnaBridge | 189:f392fc9709a3 | 149 | |
| AnnaBridge | 189:f392fc9709a3 | 150 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 151 | |
| AnnaBridge | 189:f392fc9709a3 | 152 | /** @defgroup RCC_Exported_Constants RCC Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 153 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 154 | */ |
| AnnaBridge | 189:f392fc9709a3 | 155 | |
| AnnaBridge | 189:f392fc9709a3 | 156 | /** @defgroup RCC_Oscillator_Type RCC Oscillator Type |
| AnnaBridge | 189:f392fc9709a3 | 157 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 158 | */ |
| AnnaBridge | 189:f392fc9709a3 | 159 | #define RCC_OSCILLATORTYPE_NONE (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define RCC_OSCILLATORTYPE_HSE (0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 161 | #define RCC_OSCILLATORTYPE_HSI (0x00000002U) |
| AnnaBridge | 189:f392fc9709a3 | 162 | #define RCC_OSCILLATORTYPE_LSE (0x00000004U) |
| AnnaBridge | 189:f392fc9709a3 | 163 | #define RCC_OSCILLATORTYPE_LSI (0x00000008U) |
| AnnaBridge | 189:f392fc9709a3 | 164 | #define RCC_OSCILLATORTYPE_CSI (0x00000010U) |
| AnnaBridge | 189:f392fc9709a3 | 165 | #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) |
| AnnaBridge | 189:f392fc9709a3 | 166 | |
| AnnaBridge | 189:f392fc9709a3 | 167 | /** |
| AnnaBridge | 189:f392fc9709a3 | 168 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 169 | */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | |
| AnnaBridge | 189:f392fc9709a3 | 171 | /** @defgroup RCC_HSE_Config RCC HSE Config |
| AnnaBridge | 189:f392fc9709a3 | 172 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 173 | */ |
| AnnaBridge | 189:f392fc9709a3 | 174 | #define RCC_HSE_OFF (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 175 | #define RCC_HSE_ON RCC_CR_HSEON |
| AnnaBridge | 189:f392fc9709a3 | 176 | #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) |
| AnnaBridge | 189:f392fc9709a3 | 177 | |
| AnnaBridge | 189:f392fc9709a3 | 178 | /** |
| AnnaBridge | 189:f392fc9709a3 | 179 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 180 | */ |
| AnnaBridge | 189:f392fc9709a3 | 181 | |
| AnnaBridge | 189:f392fc9709a3 | 182 | /** @defgroup RCC_LSE_Config RCC LSE Config |
| AnnaBridge | 189:f392fc9709a3 | 183 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 184 | */ |
| AnnaBridge | 189:f392fc9709a3 | 185 | #define RCC_LSE_OFF (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define RCC_LSE_ON RCC_BDCR_LSEON |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) |
| AnnaBridge | 189:f392fc9709a3 | 188 | |
| AnnaBridge | 189:f392fc9709a3 | 189 | /** |
| AnnaBridge | 189:f392fc9709a3 | 190 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 191 | */ |
| AnnaBridge | 189:f392fc9709a3 | 192 | |
| AnnaBridge | 189:f392fc9709a3 | 193 | /** @defgroup RCC_HSI_Config RCC HSI Config |
| AnnaBridge | 189:f392fc9709a3 | 194 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 195 | */ |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ |
| AnnaBridge | 189:f392fc9709a3 | 198 | |
| AnnaBridge | 189:f392fc9709a3 | 199 | #define RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | #define RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */ |
| AnnaBridge | 189:f392fc9709a3 | 201 | #define RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */ |
| AnnaBridge | 189:f392fc9709a3 | 202 | #define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION) /*!< HSI_DIV8 clock activation */ |
| AnnaBridge | 189:f392fc9709a3 | 203 | |
| AnnaBridge | 189:f392fc9709a3 | 204 | |
| AnnaBridge | 189:f392fc9709a3 | 205 | |
| AnnaBridge | 189:f392fc9709a3 | 206 | #define RCC_HSICALIBRATION_DEFAULT (0x20U) /* Default HSI calibration trimming value */ |
| AnnaBridge | 189:f392fc9709a3 | 207 | /** |
| AnnaBridge | 189:f392fc9709a3 | 208 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 209 | */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | |
| AnnaBridge | 189:f392fc9709a3 | 211 | /** @defgroup RCC_HSI48_Config RCC HSI48 Config |
| AnnaBridge | 189:f392fc9709a3 | 212 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 213 | */ |
| AnnaBridge | 189:f392fc9709a3 | 214 | #define RCC_HSI48_OFF ((uint8_t)0x00) |
| AnnaBridge | 189:f392fc9709a3 | 215 | #define RCC_HSI48_ON ((uint8_t)0x01) |
| AnnaBridge | 189:f392fc9709a3 | 216 | |
| AnnaBridge | 189:f392fc9709a3 | 217 | /** |
| AnnaBridge | 189:f392fc9709a3 | 218 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 219 | */ |
| AnnaBridge | 189:f392fc9709a3 | 220 | |
| AnnaBridge | 189:f392fc9709a3 | 221 | /** @defgroup RCC_LSI_Config RCC LSI Config |
| AnnaBridge | 189:f392fc9709a3 | 222 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 223 | */ |
| AnnaBridge | 189:f392fc9709a3 | 224 | #define RCC_LSI_OFF (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define RCC_LSI_ON RCC_CSR_LSION |
| AnnaBridge | 189:f392fc9709a3 | 226 | |
| AnnaBridge | 189:f392fc9709a3 | 227 | /** |
| AnnaBridge | 189:f392fc9709a3 | 228 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 229 | */ |
| AnnaBridge | 189:f392fc9709a3 | 230 | |
| AnnaBridge | 189:f392fc9709a3 | 231 | /** @defgroup RCC_CSI_Config RCC CSI Config |
| AnnaBridge | 189:f392fc9709a3 | 232 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 233 | */ |
| AnnaBridge | 189:f392fc9709a3 | 234 | #define RCC_CSI_OFF (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 235 | #define RCC_CSI_ON RCC_CR_CSION |
| AnnaBridge | 189:f392fc9709a3 | 236 | |
| AnnaBridge | 189:f392fc9709a3 | 237 | #define RCC_CSICALIBRATION_DEFAULT (0x10U) /* Default CSI calibration trimming value */ |
| AnnaBridge | 189:f392fc9709a3 | 238 | |
| AnnaBridge | 189:f392fc9709a3 | 239 | /** |
| AnnaBridge | 189:f392fc9709a3 | 240 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 241 | */ |
| AnnaBridge | 189:f392fc9709a3 | 242 | |
| AnnaBridge | 189:f392fc9709a3 | 243 | /** @defgroup RCC_PLL_Config RCC PLL Config |
| AnnaBridge | 189:f392fc9709a3 | 244 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 245 | */ |
| AnnaBridge | 189:f392fc9709a3 | 246 | #define RCC_PLL_NONE (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 247 | #define RCC_PLL_OFF (0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 248 | #define RCC_PLL_ON (0x00000002U) |
| AnnaBridge | 189:f392fc9709a3 | 249 | |
| AnnaBridge | 189:f392fc9709a3 | 250 | /** |
| AnnaBridge | 189:f392fc9709a3 | 251 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 252 | */ |
| AnnaBridge | 189:f392fc9709a3 | 253 | |
| AnnaBridge | 189:f392fc9709a3 | 254 | |
| AnnaBridge | 189:f392fc9709a3 | 255 | /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 256 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 257 | */ |
| AnnaBridge | 189:f392fc9709a3 | 258 | #define RCC_PLLSOURCE_HSI (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 259 | #define RCC_PLLSOURCE_CSI (0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 260 | #define RCC_PLLSOURCE_HSE (0x00000002U) |
| AnnaBridge | 189:f392fc9709a3 | 261 | #define RCC_PLLSOURCE_NONE (0x00000003U) |
| AnnaBridge | 189:f392fc9709a3 | 262 | /** |
| AnnaBridge | 189:f392fc9709a3 | 263 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 264 | */ |
| AnnaBridge | 189:f392fc9709a3 | 265 | |
| AnnaBridge | 189:f392fc9709a3 | 266 | /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output |
| AnnaBridge | 189:f392fc9709a3 | 267 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 268 | */ |
| AnnaBridge | 189:f392fc9709a3 | 269 | #define RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN |
| AnnaBridge | 189:f392fc9709a3 | 270 | #define RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN |
| AnnaBridge | 189:f392fc9709a3 | 271 | #define RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN |
| AnnaBridge | 189:f392fc9709a3 | 272 | |
| AnnaBridge | 189:f392fc9709a3 | 273 | /** |
| AnnaBridge | 189:f392fc9709a3 | 274 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 275 | */ |
| AnnaBridge | 189:f392fc9709a3 | 276 | |
| AnnaBridge | 189:f392fc9709a3 | 277 | |
| AnnaBridge | 189:f392fc9709a3 | 278 | |
| AnnaBridge | 189:f392fc9709a3 | 279 | /** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range |
| AnnaBridge | 189:f392fc9709a3 | 280 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 281 | */ |
| AnnaBridge | 189:f392fc9709a3 | 282 | #define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 |
| AnnaBridge | 189:f392fc9709a3 | 283 | #define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 |
| AnnaBridge | 189:f392fc9709a3 | 284 | #define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 |
| AnnaBridge | 189:f392fc9709a3 | 285 | #define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 |
| AnnaBridge | 189:f392fc9709a3 | 286 | |
| AnnaBridge | 189:f392fc9709a3 | 287 | |
| AnnaBridge | 189:f392fc9709a3 | 288 | /** |
| AnnaBridge | 189:f392fc9709a3 | 289 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 290 | */ |
| AnnaBridge | 189:f392fc9709a3 | 291 | |
| AnnaBridge | 189:f392fc9709a3 | 292 | |
| AnnaBridge | 189:f392fc9709a3 | 293 | /** @defgroup RCC_PLL1_VCO_Range RCC PLL1 VCO Range |
| AnnaBridge | 189:f392fc9709a3 | 294 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 295 | */ |
| AnnaBridge | 189:f392fc9709a3 | 296 | #define RCC_PLL1VCOWIDE (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 297 | #define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL |
| AnnaBridge | 189:f392fc9709a3 | 298 | |
| AnnaBridge | 189:f392fc9709a3 | 299 | /** |
| AnnaBridge | 189:f392fc9709a3 | 300 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 301 | */ |
| AnnaBridge | 189:f392fc9709a3 | 302 | |
| AnnaBridge | 189:f392fc9709a3 | 303 | |
| AnnaBridge | 189:f392fc9709a3 | 304 | /** @defgroup RCC_System_Clock_Type RCC System Clock Type |
| AnnaBridge | 189:f392fc9709a3 | 305 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 306 | */ |
| AnnaBridge | 189:f392fc9709a3 | 307 | #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 308 | #define RCC_CLOCKTYPE_HCLK (0x00000002U) |
| AnnaBridge | 189:f392fc9709a3 | 309 | #define RCC_CLOCKTYPE_D1PCLK1 (0x00000004U) |
| AnnaBridge | 189:f392fc9709a3 | 310 | #define RCC_CLOCKTYPE_PCLK1 (0x00000008U) |
| AnnaBridge | 189:f392fc9709a3 | 311 | #define RCC_CLOCKTYPE_PCLK2 (0x00000010U) |
| AnnaBridge | 189:f392fc9709a3 | 312 | #define RCC_CLOCKTYPE_D3PCLK1 (0x00000020U) |
| AnnaBridge | 189:f392fc9709a3 | 313 | |
| AnnaBridge | 189:f392fc9709a3 | 314 | /** |
| AnnaBridge | 189:f392fc9709a3 | 315 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 316 | */ |
| AnnaBridge | 189:f392fc9709a3 | 317 | |
| AnnaBridge | 189:f392fc9709a3 | 318 | /** @defgroup RCC_System_Clock_Source RCC System Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 319 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 320 | */ |
| AnnaBridge | 189:f392fc9709a3 | 321 | #define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI |
| AnnaBridge | 189:f392fc9709a3 | 322 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI |
| AnnaBridge | 189:f392fc9709a3 | 323 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE |
| AnnaBridge | 189:f392fc9709a3 | 324 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1 |
| AnnaBridge | 189:f392fc9709a3 | 325 | |
| AnnaBridge | 189:f392fc9709a3 | 326 | /** |
| AnnaBridge | 189:f392fc9709a3 | 327 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 328 | */ |
| AnnaBridge | 189:f392fc9709a3 | 329 | |
| AnnaBridge | 189:f392fc9709a3 | 330 | /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status |
| AnnaBridge | 189:f392fc9709a3 | 331 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 332 | */ |
| AnnaBridge | 189:f392fc9709a3 | 333 | #define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */ |
| AnnaBridge | 189:f392fc9709a3 | 334 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
| AnnaBridge | 189:f392fc9709a3 | 335 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
| AnnaBridge | 189:f392fc9709a3 | 336 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */ |
| AnnaBridge | 189:f392fc9709a3 | 337 | /** |
| AnnaBridge | 189:f392fc9709a3 | 338 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 339 | */ |
| AnnaBridge | 189:f392fc9709a3 | 340 | |
| AnnaBridge | 189:f392fc9709a3 | 341 | /** @defgroup RCC_SYS_Clock_Source RCC SYS Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 342 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 343 | */ |
| AnnaBridge | 189:f392fc9709a3 | 344 | #define RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 345 | #define RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 346 | #define RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 347 | #define RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 348 | #define RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16 |
| AnnaBridge | 189:f392fc9709a3 | 349 | #define RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64 |
| AnnaBridge | 189:f392fc9709a3 | 350 | #define RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128 |
| AnnaBridge | 189:f392fc9709a3 | 351 | #define RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256 |
| AnnaBridge | 189:f392fc9709a3 | 352 | #define RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512 |
| AnnaBridge | 189:f392fc9709a3 | 353 | |
| AnnaBridge | 189:f392fc9709a3 | 354 | /** |
| AnnaBridge | 189:f392fc9709a3 | 355 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 356 | */ |
| AnnaBridge | 189:f392fc9709a3 | 357 | |
| AnnaBridge | 189:f392fc9709a3 | 358 | |
| AnnaBridge | 189:f392fc9709a3 | 359 | /** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 360 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 361 | */ |
| AnnaBridge | 189:f392fc9709a3 | 362 | #define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 363 | #define RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 364 | #define RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 365 | #define RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 366 | #define RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16 |
| AnnaBridge | 189:f392fc9709a3 | 367 | #define RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64 |
| AnnaBridge | 189:f392fc9709a3 | 368 | #define RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128 |
| AnnaBridge | 189:f392fc9709a3 | 369 | #define RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256 |
| AnnaBridge | 189:f392fc9709a3 | 370 | #define RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512 |
| AnnaBridge | 189:f392fc9709a3 | 371 | |
| AnnaBridge | 189:f392fc9709a3 | 372 | /** |
| AnnaBridge | 189:f392fc9709a3 | 373 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 374 | */ |
| AnnaBridge | 189:f392fc9709a3 | 375 | |
| AnnaBridge | 189:f392fc9709a3 | 376 | /** @defgroup RCC_APB3_Clock_Source RCC APB3 Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 377 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 378 | */ |
| AnnaBridge | 189:f392fc9709a3 | 379 | #define RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 380 | #define RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 381 | #define RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 382 | #define RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 383 | #define RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16 |
| AnnaBridge | 189:f392fc9709a3 | 384 | |
| AnnaBridge | 189:f392fc9709a3 | 385 | /** |
| AnnaBridge | 189:f392fc9709a3 | 386 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 387 | */ |
| AnnaBridge | 189:f392fc9709a3 | 388 | |
| AnnaBridge | 189:f392fc9709a3 | 389 | /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 391 | */ |
| AnnaBridge | 189:f392fc9709a3 | 392 | #define RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 393 | #define RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 394 | #define RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 395 | #define RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 396 | #define RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16 |
| AnnaBridge | 189:f392fc9709a3 | 397 | |
| AnnaBridge | 189:f392fc9709a3 | 398 | /** |
| AnnaBridge | 189:f392fc9709a3 | 399 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 400 | */ |
| AnnaBridge | 189:f392fc9709a3 | 401 | |
| AnnaBridge | 189:f392fc9709a3 | 402 | /** @defgroup RCC_APB2_Clock_Source RCC APB2 Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 403 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 404 | */ |
| AnnaBridge | 189:f392fc9709a3 | 405 | #define RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 406 | #define RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 407 | #define RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 408 | #define RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 409 | #define RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16 |
| AnnaBridge | 189:f392fc9709a3 | 410 | |
| AnnaBridge | 189:f392fc9709a3 | 411 | /** |
| AnnaBridge | 189:f392fc9709a3 | 412 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 413 | */ |
| AnnaBridge | 189:f392fc9709a3 | 414 | |
| AnnaBridge | 189:f392fc9709a3 | 415 | /** @defgroup RCC_APB4_Clock_Source RCC APB4 Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 416 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 417 | */ |
| AnnaBridge | 189:f392fc9709a3 | 418 | #define RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1 |
| AnnaBridge | 189:f392fc9709a3 | 419 | #define RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2 |
| AnnaBridge | 189:f392fc9709a3 | 420 | #define RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4 |
| AnnaBridge | 189:f392fc9709a3 | 421 | #define RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8 |
| AnnaBridge | 189:f392fc9709a3 | 422 | #define RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16 |
| AnnaBridge | 189:f392fc9709a3 | 423 | |
| AnnaBridge | 189:f392fc9709a3 | 424 | /** |
| AnnaBridge | 189:f392fc9709a3 | 425 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 426 | */ |
| AnnaBridge | 189:f392fc9709a3 | 427 | |
| AnnaBridge | 189:f392fc9709a3 | 428 | /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 429 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 430 | */ |
| AnnaBridge | 189:f392fc9709a3 | 431 | #define RCC_RTCCLKSOURCE_LSE (0x00000100U) |
| AnnaBridge | 189:f392fc9709a3 | 432 | #define RCC_RTCCLKSOURCE_LSI (0x00000200U) |
| AnnaBridge | 189:f392fc9709a3 | 433 | #define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U) |
| AnnaBridge | 189:f392fc9709a3 | 434 | #define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U) |
| AnnaBridge | 189:f392fc9709a3 | 435 | #define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U) |
| AnnaBridge | 189:f392fc9709a3 | 436 | #define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U) |
| AnnaBridge | 189:f392fc9709a3 | 437 | #define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U) |
| AnnaBridge | 189:f392fc9709a3 | 438 | #define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U) |
| AnnaBridge | 189:f392fc9709a3 | 439 | #define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U) |
| AnnaBridge | 189:f392fc9709a3 | 440 | #define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U) |
| AnnaBridge | 189:f392fc9709a3 | 441 | #define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U) |
| AnnaBridge | 189:f392fc9709a3 | 442 | #define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U) |
| AnnaBridge | 189:f392fc9709a3 | 443 | #define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U) |
| AnnaBridge | 189:f392fc9709a3 | 444 | #define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U) |
| AnnaBridge | 189:f392fc9709a3 | 445 | #define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U) |
| AnnaBridge | 189:f392fc9709a3 | 446 | #define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U) |
| AnnaBridge | 189:f392fc9709a3 | 447 | #define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U) |
| AnnaBridge | 189:f392fc9709a3 | 448 | #define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U) |
| AnnaBridge | 189:f392fc9709a3 | 449 | #define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U) |
| AnnaBridge | 189:f392fc9709a3 | 450 | #define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U) |
| AnnaBridge | 189:f392fc9709a3 | 451 | #define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U) |
| AnnaBridge | 189:f392fc9709a3 | 452 | #define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U) |
| AnnaBridge | 189:f392fc9709a3 | 453 | #define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U) |
| AnnaBridge | 189:f392fc9709a3 | 454 | #define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U) |
| AnnaBridge | 189:f392fc9709a3 | 455 | #define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U) |
| AnnaBridge | 189:f392fc9709a3 | 456 | #define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U) |
| AnnaBridge | 189:f392fc9709a3 | 457 | #define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U) |
| AnnaBridge | 189:f392fc9709a3 | 458 | #define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U) |
| AnnaBridge | 189:f392fc9709a3 | 459 | #define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U) |
| AnnaBridge | 189:f392fc9709a3 | 460 | #define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U) |
| AnnaBridge | 189:f392fc9709a3 | 461 | #define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U) |
| AnnaBridge | 189:f392fc9709a3 | 462 | #define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U) |
| AnnaBridge | 189:f392fc9709a3 | 463 | #define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U) |
| AnnaBridge | 189:f392fc9709a3 | 464 | #define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U) |
| AnnaBridge | 189:f392fc9709a3 | 465 | #define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U) |
| AnnaBridge | 189:f392fc9709a3 | 466 | #define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U) |
| AnnaBridge | 189:f392fc9709a3 | 467 | #define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U) |
| AnnaBridge | 189:f392fc9709a3 | 468 | #define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U) |
| AnnaBridge | 189:f392fc9709a3 | 469 | #define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U) |
| AnnaBridge | 189:f392fc9709a3 | 470 | #define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U) |
| AnnaBridge | 189:f392fc9709a3 | 471 | #define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U) |
| AnnaBridge | 189:f392fc9709a3 | 472 | #define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U) |
| AnnaBridge | 189:f392fc9709a3 | 473 | #define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U) |
| AnnaBridge | 189:f392fc9709a3 | 474 | #define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U) |
| AnnaBridge | 189:f392fc9709a3 | 475 | #define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U) |
| AnnaBridge | 189:f392fc9709a3 | 476 | #define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U) |
| AnnaBridge | 189:f392fc9709a3 | 477 | #define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U) |
| AnnaBridge | 189:f392fc9709a3 | 478 | #define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U) |
| AnnaBridge | 189:f392fc9709a3 | 479 | #define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U) |
| AnnaBridge | 189:f392fc9709a3 | 480 | #define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U) |
| AnnaBridge | 189:f392fc9709a3 | 481 | #define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U) |
| AnnaBridge | 189:f392fc9709a3 | 482 | #define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U) |
| AnnaBridge | 189:f392fc9709a3 | 483 | #define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U) |
| AnnaBridge | 189:f392fc9709a3 | 484 | #define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U) |
| AnnaBridge | 189:f392fc9709a3 | 485 | #define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U) |
| AnnaBridge | 189:f392fc9709a3 | 486 | #define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U) |
| AnnaBridge | 189:f392fc9709a3 | 487 | #define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U) |
| AnnaBridge | 189:f392fc9709a3 | 488 | #define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U) |
| AnnaBridge | 189:f392fc9709a3 | 489 | #define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U) |
| AnnaBridge | 189:f392fc9709a3 | 490 | #define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U) |
| AnnaBridge | 189:f392fc9709a3 | 491 | #define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U) |
| AnnaBridge | 189:f392fc9709a3 | 492 | #define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U) |
| AnnaBridge | 189:f392fc9709a3 | 493 | #define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U) |
| AnnaBridge | 189:f392fc9709a3 | 494 | #define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U) |
| AnnaBridge | 189:f392fc9709a3 | 495 | |
| AnnaBridge | 189:f392fc9709a3 | 496 | |
| AnnaBridge | 189:f392fc9709a3 | 497 | /** |
| AnnaBridge | 189:f392fc9709a3 | 498 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 499 | */ |
| AnnaBridge | 189:f392fc9709a3 | 500 | |
| AnnaBridge | 189:f392fc9709a3 | 501 | |
| AnnaBridge | 189:f392fc9709a3 | 502 | /** @defgroup RCC_MCO_Index RCC MCO Index |
| AnnaBridge | 189:f392fc9709a3 | 503 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 504 | */ |
| AnnaBridge | 189:f392fc9709a3 | 505 | #define RCC_MCO1 (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 506 | #define RCC_MCO2 (0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 507 | |
| AnnaBridge | 189:f392fc9709a3 | 508 | /** |
| AnnaBridge | 189:f392fc9709a3 | 509 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 510 | */ |
| AnnaBridge | 189:f392fc9709a3 | 511 | |
| AnnaBridge | 189:f392fc9709a3 | 512 | /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 513 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 514 | */ |
| AnnaBridge | 189:f392fc9709a3 | 515 | #define RCC_MCO1SOURCE_HSI (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 516 | #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 |
| AnnaBridge | 189:f392fc9709a3 | 517 | #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 |
| AnnaBridge | 189:f392fc9709a3 | 518 | #define RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1) |
| AnnaBridge | 189:f392fc9709a3 | 519 | #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2 |
| AnnaBridge | 189:f392fc9709a3 | 520 | |
| AnnaBridge | 189:f392fc9709a3 | 521 | /** |
| AnnaBridge | 189:f392fc9709a3 | 522 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 523 | */ |
| AnnaBridge | 189:f392fc9709a3 | 524 | |
| AnnaBridge | 189:f392fc9709a3 | 525 | /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source |
| AnnaBridge | 189:f392fc9709a3 | 526 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 527 | */ |
| AnnaBridge | 189:f392fc9709a3 | 528 | #define RCC_MCO2SOURCE_SYSCLK (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 529 | #define RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0 |
| AnnaBridge | 189:f392fc9709a3 | 530 | #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 |
| AnnaBridge | 189:f392fc9709a3 | 531 | #define RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1) |
| AnnaBridge | 189:f392fc9709a3 | 532 | #define RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2 |
| AnnaBridge | 189:f392fc9709a3 | 533 | #define RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2) |
| AnnaBridge | 189:f392fc9709a3 | 534 | |
| AnnaBridge | 189:f392fc9709a3 | 535 | /** |
| AnnaBridge | 189:f392fc9709a3 | 536 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 537 | */ |
| AnnaBridge | 189:f392fc9709a3 | 538 | |
| AnnaBridge | 189:f392fc9709a3 | 539 | /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCOx Clock Prescaler |
| AnnaBridge | 189:f392fc9709a3 | 540 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 541 | */ |
| AnnaBridge | 189:f392fc9709a3 | 542 | #define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0 |
| AnnaBridge | 189:f392fc9709a3 | 543 | #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1 |
| AnnaBridge | 189:f392fc9709a3 | 544 | #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1) |
| AnnaBridge | 189:f392fc9709a3 | 545 | #define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2 |
| AnnaBridge | 189:f392fc9709a3 | 546 | #define RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) |
| AnnaBridge | 189:f392fc9709a3 | 547 | #define RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) |
| AnnaBridge | 189:f392fc9709a3 | 548 | #define RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) |
| AnnaBridge | 189:f392fc9709a3 | 549 | #define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3 |
| AnnaBridge | 189:f392fc9709a3 | 550 | #define RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3) |
| AnnaBridge | 189:f392fc9709a3 | 551 | #define RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) |
| AnnaBridge | 189:f392fc9709a3 | 552 | #define RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) |
| AnnaBridge | 189:f392fc9709a3 | 553 | #define RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) |
| AnnaBridge | 189:f392fc9709a3 | 554 | #define RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) |
| AnnaBridge | 189:f392fc9709a3 | 555 | #define RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) |
| AnnaBridge | 189:f392fc9709a3 | 556 | #define RCC_MCODIV_15 RCC_CFGR_MCO1PRE |
| AnnaBridge | 189:f392fc9709a3 | 557 | |
| AnnaBridge | 189:f392fc9709a3 | 558 | |
| AnnaBridge | 189:f392fc9709a3 | 559 | /** |
| AnnaBridge | 189:f392fc9709a3 | 560 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 561 | */ |
| AnnaBridge | 189:f392fc9709a3 | 562 | |
| AnnaBridge | 189:f392fc9709a3 | 563 | /** @defgroup RCC_Interrupt RCC Interrupt |
| AnnaBridge | 189:f392fc9709a3 | 564 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 565 | */ |
| AnnaBridge | 189:f392fc9709a3 | 566 | #define RCC_IT_LSIRDY (0x00000001U) |
| AnnaBridge | 189:f392fc9709a3 | 567 | #define RCC_IT_LSERDY (0x00000002U) |
| AnnaBridge | 189:f392fc9709a3 | 568 | #define RCC_IT_HSIRDY (0x00000004U) |
| AnnaBridge | 189:f392fc9709a3 | 569 | #define RCC_IT_HSERDY (0x00000008U) |
| AnnaBridge | 189:f392fc9709a3 | 570 | #define RCC_IT_CSIRDY (0x00000010U) |
| AnnaBridge | 189:f392fc9709a3 | 571 | #define RCC_IT_HSI48RDY (0x00000020U) |
| AnnaBridge | 189:f392fc9709a3 | 572 | #define RCC_IT_PLLRDY (0x00000040U) |
| AnnaBridge | 189:f392fc9709a3 | 573 | #define RCC_IT_PLL2RDY (0x00000080U) |
| AnnaBridge | 189:f392fc9709a3 | 574 | #define RCC_IT_PLL3RDY (0x00000100U) |
| AnnaBridge | 189:f392fc9709a3 | 575 | #define RCC_IT_LSECSS (0x00000200U) |
| AnnaBridge | 189:f392fc9709a3 | 576 | #define RCC_IT_CSS (0x00000400U) |
| AnnaBridge | 189:f392fc9709a3 | 577 | /** |
| AnnaBridge | 189:f392fc9709a3 | 578 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 579 | */ |
| AnnaBridge | 189:f392fc9709a3 | 580 | |
| AnnaBridge | 189:f392fc9709a3 | 581 | /** @defgroup RCC_Flag RCC Flag |
| AnnaBridge | 189:f392fc9709a3 | 582 | * Elements values convention: 0XXYYYYYb |
| AnnaBridge | 189:f392fc9709a3 | 583 | * - YYYYY : Flag position in the register |
| AnnaBridge | 189:f392fc9709a3 | 584 | * - 0XX : Register index |
| AnnaBridge | 189:f392fc9709a3 | 585 | * - 01: CR register |
| AnnaBridge | 189:f392fc9709a3 | 586 | * - 10: BDCR register |
| AnnaBridge | 189:f392fc9709a3 | 587 | * - 11: CSR register |
| AnnaBridge | 189:f392fc9709a3 | 588 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 589 | */ |
| AnnaBridge | 189:f392fc9709a3 | 590 | /* Flags in the CR register */ |
| AnnaBridge | 189:f392fc9709a3 | 591 | #define RCC_FLAG_HSIRDY ((uint8_t)0x22) |
| AnnaBridge | 189:f392fc9709a3 | 592 | #define RCC_FLAG_HSIDIV ((uint8_t)0x25) |
| AnnaBridge | 189:f392fc9709a3 | 593 | #define RCC_FLAG_CSIRDY ((uint8_t)0x28) |
| AnnaBridge | 189:f392fc9709a3 | 594 | #define RCC_FLAG_HSI48RDY ((uint8_t)0x2D) |
| AnnaBridge | 189:f392fc9709a3 | 595 | #define RCC_FLAG_D1CKRDY ((uint8_t)0x2E) |
| AnnaBridge | 189:f392fc9709a3 | 596 | #define RCC_FLAG_D2CKRDY ((uint8_t)0x2F) |
| AnnaBridge | 189:f392fc9709a3 | 597 | #define RCC_FLAG_HSERDY ((uint8_t)0x31) |
| AnnaBridge | 189:f392fc9709a3 | 598 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39) |
| AnnaBridge | 189:f392fc9709a3 | 599 | #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) |
| AnnaBridge | 189:f392fc9709a3 | 600 | #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) |
| AnnaBridge | 189:f392fc9709a3 | 601 | /* Flags in the BDCR register */ |
| AnnaBridge | 189:f392fc9709a3 | 602 | #define RCC_FLAG_LSERDY ((uint8_t)0x41) |
| AnnaBridge | 189:f392fc9709a3 | 603 | |
| AnnaBridge | 189:f392fc9709a3 | 604 | /* Flags in the CSR register */ |
| AnnaBridge | 189:f392fc9709a3 | 605 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61) |
| AnnaBridge | 189:f392fc9709a3 | 606 | |
| AnnaBridge | 189:f392fc9709a3 | 607 | /* Flags in the RSR register */ |
| AnnaBridge | 189:f392fc9709a3 | 608 | #define RCC_FLAG_CPURST ((uint8_t)0x91) |
| AnnaBridge | 189:f392fc9709a3 | 609 | |
| AnnaBridge | 189:f392fc9709a3 | 610 | #define RCC_FLAG_D1RST ((uint8_t)0x93) |
| AnnaBridge | 189:f392fc9709a3 | 611 | #define RCC_FLAG_D2RST ((uint8_t)0x94) |
| AnnaBridge | 189:f392fc9709a3 | 612 | #define RCC_FLAG_BORRST ((uint8_t)0x95) |
| AnnaBridge | 189:f392fc9709a3 | 613 | #define RCC_FLAG_PINRST ((uint8_t)0x96) |
| AnnaBridge | 189:f392fc9709a3 | 614 | #define RCC_FLAG_PORRST ((uint8_t)0x97) |
| AnnaBridge | 189:f392fc9709a3 | 615 | #define RCC_FLAG_SFTRST ((uint8_t)0x98) |
| AnnaBridge | 189:f392fc9709a3 | 616 | #define RCC_FLAG_IWDG1RST ((uint8_t)0x9A) |
| AnnaBridge | 189:f392fc9709a3 | 617 | #define RCC_FLAG_WWDG1RST ((uint8_t)0x9C) |
| AnnaBridge | 189:f392fc9709a3 | 618 | #define RCC_FLAG_LPWR1RST ((uint8_t)0x9E) |
| AnnaBridge | 189:f392fc9709a3 | 619 | #define RCC_FLAG_LPWR2RST ((uint8_t)0x9F) |
| AnnaBridge | 189:f392fc9709a3 | 620 | |
| AnnaBridge | 189:f392fc9709a3 | 621 | |
| AnnaBridge | 189:f392fc9709a3 | 622 | /** |
| AnnaBridge | 189:f392fc9709a3 | 623 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 624 | */ |
| AnnaBridge | 189:f392fc9709a3 | 625 | |
| AnnaBridge | 189:f392fc9709a3 | 626 | /** @defgroup RCC_LSEDrive_Config LSE Drive Config |
| AnnaBridge | 189:f392fc9709a3 | 627 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 628 | */ |
| AnnaBridge | 189:f392fc9709a3 | 629 | #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */ |
| AnnaBridge | 189:f392fc9709a3 | 630 | #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ |
| AnnaBridge | 189:f392fc9709a3 | 631 | #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ |
| AnnaBridge | 189:f392fc9709a3 | 632 | #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ |
| AnnaBridge | 189:f392fc9709a3 | 633 | /** |
| AnnaBridge | 189:f392fc9709a3 | 634 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 635 | */ |
| AnnaBridge | 189:f392fc9709a3 | 636 | |
| AnnaBridge | 189:f392fc9709a3 | 637 | /** @defgroup RCC_Stop_WakeUpClock RCC Stop WakeUpClock |
| AnnaBridge | 189:f392fc9709a3 | 638 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 639 | */ |
| AnnaBridge | 189:f392fc9709a3 | 640 | #define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 641 | #define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK |
| AnnaBridge | 189:f392fc9709a3 | 642 | |
| AnnaBridge | 189:f392fc9709a3 | 643 | /** |
| AnnaBridge | 189:f392fc9709a3 | 644 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 645 | */ |
| AnnaBridge | 189:f392fc9709a3 | 646 | |
| AnnaBridge | 189:f392fc9709a3 | 647 | /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock |
| AnnaBridge | 189:f392fc9709a3 | 648 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 649 | */ |
| AnnaBridge | 189:f392fc9709a3 | 650 | #define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U) |
| AnnaBridge | 189:f392fc9709a3 | 651 | #define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK |
| AnnaBridge | 189:f392fc9709a3 | 652 | |
| AnnaBridge | 189:f392fc9709a3 | 653 | |
| AnnaBridge | 189:f392fc9709a3 | 654 | /** |
| AnnaBridge | 189:f392fc9709a3 | 655 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 656 | */ |
| AnnaBridge | 189:f392fc9709a3 | 657 | /** |
| AnnaBridge | 189:f392fc9709a3 | 658 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 659 | */ |
| AnnaBridge | 189:f392fc9709a3 | 660 | |
| AnnaBridge | 189:f392fc9709a3 | 661 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 662 | |
| AnnaBridge | 189:f392fc9709a3 | 663 | /** @defgroup RCC_Exported_Macros RCC Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 664 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 665 | */ |
| AnnaBridge | 189:f392fc9709a3 | 666 | |
| AnnaBridge | 189:f392fc9709a3 | 667 | /** @brief Enable or disable the AHB3 peripheral clock. |
| AnnaBridge | 189:f392fc9709a3 | 668 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 669 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 670 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 671 | */ |
| AnnaBridge | 189:f392fc9709a3 | 672 | #define __HAL_RCC_MDMA_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 673 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 674 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 675 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 676 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 677 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 678 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 679 | |
| AnnaBridge | 189:f392fc9709a3 | 680 | #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 681 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 682 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 683 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 684 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 685 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 686 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 687 | |
| AnnaBridge | 189:f392fc9709a3 | 688 | #define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 689 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 690 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 691 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 692 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 693 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 694 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 695 | |
| AnnaBridge | 189:f392fc9709a3 | 696 | |
| AnnaBridge | 189:f392fc9709a3 | 697 | #define __HAL_RCC_FMC_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 698 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 699 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 700 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 701 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 702 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 703 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 704 | |
| AnnaBridge | 189:f392fc9709a3 | 705 | #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 706 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 707 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 708 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 709 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 710 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 711 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 712 | |
| AnnaBridge | 189:f392fc9709a3 | 713 | #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 714 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 715 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 716 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 717 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 718 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 719 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 720 | |
| AnnaBridge | 189:f392fc9709a3 | 721 | |
| AnnaBridge | 189:f392fc9709a3 | 722 | #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) |
| AnnaBridge | 189:f392fc9709a3 | 723 | #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) |
| AnnaBridge | 189:f392fc9709a3 | 724 | #define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) |
| AnnaBridge | 189:f392fc9709a3 | 725 | #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) |
| AnnaBridge | 189:f392fc9709a3 | 726 | #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) |
| AnnaBridge | 189:f392fc9709a3 | 727 | #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) |
| AnnaBridge | 189:f392fc9709a3 | 728 | |
| AnnaBridge | 189:f392fc9709a3 | 729 | |
| AnnaBridge | 189:f392fc9709a3 | 730 | /** @brief Get the enable or disable status of the AHB3 peripheral clock |
| AnnaBridge | 189:f392fc9709a3 | 731 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 732 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 733 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 734 | */ |
| AnnaBridge | 189:f392fc9709a3 | 735 | |
| AnnaBridge | 189:f392fc9709a3 | 736 | #define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 737 | #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 738 | #define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 739 | #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 740 | #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 741 | #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 742 | |
| AnnaBridge | 189:f392fc9709a3 | 743 | #define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 744 | #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 745 | #define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 746 | #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 747 | #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 748 | #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 749 | |
| AnnaBridge | 189:f392fc9709a3 | 750 | |
| AnnaBridge | 189:f392fc9709a3 | 751 | /** @brief Enable or disable the AHB1 peripheral clock. |
| AnnaBridge | 189:f392fc9709a3 | 752 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 753 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 754 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 755 | */ |
| AnnaBridge | 189:f392fc9709a3 | 756 | |
| AnnaBridge | 189:f392fc9709a3 | 757 | #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 758 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 759 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 760 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 761 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 762 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 763 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 764 | |
| AnnaBridge | 189:f392fc9709a3 | 765 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 766 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 767 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 768 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 769 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 770 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 771 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 772 | |
| AnnaBridge | 189:f392fc9709a3 | 773 | #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 774 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 775 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 776 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 777 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 778 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 779 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 780 | |
| AnnaBridge | 189:f392fc9709a3 | 781 | |
| AnnaBridge | 189:f392fc9709a3 | 782 | #define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 783 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 784 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 785 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 786 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 787 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 788 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 789 | |
| AnnaBridge | 189:f392fc9709a3 | 790 | #define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 791 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 792 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 793 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 794 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 795 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 796 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 797 | |
| AnnaBridge | 189:f392fc9709a3 | 798 | #define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 799 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 800 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 801 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 802 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 803 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 804 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 805 | |
| AnnaBridge | 189:f392fc9709a3 | 806 | #define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 807 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 808 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 809 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 810 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 811 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 812 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 813 | |
| AnnaBridge | 189:f392fc9709a3 | 814 | #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 815 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 816 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 817 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 818 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 819 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 820 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 821 | |
| AnnaBridge | 189:f392fc9709a3 | 822 | #define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 823 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 824 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 825 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 826 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 827 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 828 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 829 | |
| AnnaBridge | 189:f392fc9709a3 | 830 | #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) |
| AnnaBridge | 189:f392fc9709a3 | 831 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) |
| AnnaBridge | 189:f392fc9709a3 | 832 | #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) |
| AnnaBridge | 189:f392fc9709a3 | 833 | #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) |
| AnnaBridge | 189:f392fc9709a3 | 834 | #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) |
| AnnaBridge | 189:f392fc9709a3 | 835 | #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) |
| AnnaBridge | 189:f392fc9709a3 | 836 | #define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) |
| AnnaBridge | 189:f392fc9709a3 | 837 | #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) |
| AnnaBridge | 189:f392fc9709a3 | 838 | #define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) |
| AnnaBridge | 189:f392fc9709a3 | 839 | |
| AnnaBridge | 189:f392fc9709a3 | 840 | |
| AnnaBridge | 189:f392fc9709a3 | 841 | /** @brief Get the enable or disable status of the AHB1 peripheral clock |
| AnnaBridge | 189:f392fc9709a3 | 842 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 843 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 844 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 845 | */ |
| AnnaBridge | 189:f392fc9709a3 | 846 | |
| AnnaBridge | 189:f392fc9709a3 | 847 | #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 848 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 849 | #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 850 | #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 851 | #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 852 | #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 853 | #define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 854 | #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 855 | #define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 856 | |
| AnnaBridge | 189:f392fc9709a3 | 857 | #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 858 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 859 | #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 860 | #define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 861 | #define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 862 | #define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 863 | #define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 864 | #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 865 | #define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 866 | |
| AnnaBridge | 189:f392fc9709a3 | 867 | /** @brief Enable or disable the AHB2 peripheral clock. |
| AnnaBridge | 189:f392fc9709a3 | 868 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 869 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 870 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 871 | */ |
| AnnaBridge | 189:f392fc9709a3 | 872 | |
| AnnaBridge | 189:f392fc9709a3 | 873 | #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 874 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 875 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 876 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 877 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 878 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 879 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 880 | |
| AnnaBridge | 189:f392fc9709a3 | 881 | #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 882 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 883 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 884 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 885 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 886 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 887 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 888 | |
| AnnaBridge | 189:f392fc9709a3 | 889 | #define __HAL_RCC_HASH_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 890 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 891 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 892 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 893 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 894 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 895 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 896 | |
| AnnaBridge | 189:f392fc9709a3 | 897 | #define __HAL_RCC_RNG_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 898 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 899 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 900 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 901 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 902 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 903 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 904 | |
| AnnaBridge | 189:f392fc9709a3 | 905 | #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 906 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 907 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 908 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 909 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 910 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 911 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 912 | |
| AnnaBridge | 189:f392fc9709a3 | 913 | #define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 914 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 915 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 916 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 917 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 918 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 919 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 920 | |
| AnnaBridge | 189:f392fc9709a3 | 921 | #define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 922 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 923 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 924 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 925 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 926 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 927 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 928 | |
| AnnaBridge | 189:f392fc9709a3 | 929 | #define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 930 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 931 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 932 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 933 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 934 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 935 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 936 | |
| AnnaBridge | 189:f392fc9709a3 | 937 | #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) |
| AnnaBridge | 189:f392fc9709a3 | 938 | #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 939 | #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) |
| AnnaBridge | 189:f392fc9709a3 | 940 | #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) |
| AnnaBridge | 189:f392fc9709a3 | 941 | #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) |
| AnnaBridge | 189:f392fc9709a3 | 942 | #define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) |
| AnnaBridge | 189:f392fc9709a3 | 943 | #define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) |
| AnnaBridge | 189:f392fc9709a3 | 944 | #define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) |
| AnnaBridge | 189:f392fc9709a3 | 945 | |
| AnnaBridge | 189:f392fc9709a3 | 946 | |
| AnnaBridge | 189:f392fc9709a3 | 947 | /** @brief Get the enable or disable status of the AHB2 peripheral clock |
| AnnaBridge | 189:f392fc9709a3 | 948 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 949 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 950 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 951 | */ |
| AnnaBridge | 189:f392fc9709a3 | 952 | |
| AnnaBridge | 189:f392fc9709a3 | 953 | #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 954 | #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 955 | #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 956 | #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 957 | #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 958 | #define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 959 | #define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 960 | #define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 961 | |
| AnnaBridge | 189:f392fc9709a3 | 962 | #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 963 | #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 964 | #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 965 | #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 966 | #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 967 | #define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 968 | #define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 969 | #define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 970 | |
| AnnaBridge | 189:f392fc9709a3 | 971 | /** @brief Enable or disable the AHB4 peripheral clock. |
| AnnaBridge | 189:f392fc9709a3 | 972 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 973 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 974 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 975 | */ |
| AnnaBridge | 189:f392fc9709a3 | 976 | |
| AnnaBridge | 189:f392fc9709a3 | 977 | #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 978 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 979 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 980 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 981 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 982 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 983 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 984 | |
| AnnaBridge | 189:f392fc9709a3 | 985 | #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 986 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 987 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 988 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 989 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 990 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 991 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 992 | |
| AnnaBridge | 189:f392fc9709a3 | 993 | #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 994 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 995 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 996 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 997 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 998 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 999 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1000 | |
| AnnaBridge | 189:f392fc9709a3 | 1001 | #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1002 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1003 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1004 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1005 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1006 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1007 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1008 | |
| AnnaBridge | 189:f392fc9709a3 | 1009 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1010 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1011 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1012 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1013 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1014 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1015 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1016 | |
| AnnaBridge | 189:f392fc9709a3 | 1017 | #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1018 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1019 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1020 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1021 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1022 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1023 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1024 | |
| AnnaBridge | 189:f392fc9709a3 | 1025 | #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1026 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1027 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1028 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1029 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1030 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1031 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1032 | |
| AnnaBridge | 189:f392fc9709a3 | 1033 | #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1034 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1035 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1036 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1037 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1038 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1039 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1040 | |
| AnnaBridge | 189:f392fc9709a3 | 1041 | #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1042 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1043 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1044 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1045 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1046 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1047 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1048 | |
| AnnaBridge | 189:f392fc9709a3 | 1049 | #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1050 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1051 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1052 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1053 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1054 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1055 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1056 | |
| AnnaBridge | 189:f392fc9709a3 | 1057 | #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1058 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1059 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1060 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1061 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1062 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1063 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1064 | |
| AnnaBridge | 189:f392fc9709a3 | 1065 | #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1066 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1067 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1068 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1069 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1070 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1071 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1072 | |
| AnnaBridge | 189:f392fc9709a3 | 1073 | #define __HAL_RCC_BDMA_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1074 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1075 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1076 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1077 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1078 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1079 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1080 | |
| AnnaBridge | 189:f392fc9709a3 | 1081 | #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1082 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1083 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1084 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1085 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1086 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1087 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1088 | |
| AnnaBridge | 189:f392fc9709a3 | 1089 | #define __HAL_RCC_HSEM_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1090 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1091 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1092 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1093 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1094 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1095 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1096 | |
| AnnaBridge | 189:f392fc9709a3 | 1097 | #define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1098 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1099 | SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1100 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1101 | tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1102 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1103 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1104 | |
| AnnaBridge | 189:f392fc9709a3 | 1105 | |
| AnnaBridge | 189:f392fc9709a3 | 1106 | #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) |
| AnnaBridge | 189:f392fc9709a3 | 1107 | #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) |
| AnnaBridge | 189:f392fc9709a3 | 1108 | #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) |
| AnnaBridge | 189:f392fc9709a3 | 1109 | #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) |
| AnnaBridge | 189:f392fc9709a3 | 1110 | #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) |
| AnnaBridge | 189:f392fc9709a3 | 1111 | #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) |
| AnnaBridge | 189:f392fc9709a3 | 1112 | #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) |
| AnnaBridge | 189:f392fc9709a3 | 1113 | #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) |
| AnnaBridge | 189:f392fc9709a3 | 1114 | #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) |
| AnnaBridge | 189:f392fc9709a3 | 1115 | #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) |
| AnnaBridge | 189:f392fc9709a3 | 1116 | #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) |
| AnnaBridge | 189:f392fc9709a3 | 1117 | #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) |
| AnnaBridge | 189:f392fc9709a3 | 1118 | #define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) |
| AnnaBridge | 189:f392fc9709a3 | 1119 | #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) |
| AnnaBridge | 189:f392fc9709a3 | 1120 | #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) |
| AnnaBridge | 189:f392fc9709a3 | 1121 | #define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 1122 | |
| AnnaBridge | 189:f392fc9709a3 | 1123 | |
| AnnaBridge | 189:f392fc9709a3 | 1124 | /** @brief Get the enable or disable status of the AHB4 peripheral clock |
| AnnaBridge | 189:f392fc9709a3 | 1125 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 1126 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 1127 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 1128 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1129 | |
| AnnaBridge | 189:f392fc9709a3 | 1130 | #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1131 | #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1132 | #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1133 | #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1134 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1135 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1136 | #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1137 | #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1138 | #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1139 | #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1140 | #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1141 | #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1142 | #define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1143 | #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1144 | #define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1145 | #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1146 | |
| AnnaBridge | 189:f392fc9709a3 | 1147 | #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1148 | #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1149 | #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1150 | #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1151 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1152 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1153 | #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1154 | #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1155 | #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1156 | #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1157 | #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1158 | #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1159 | #define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1160 | #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1161 | #define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1162 | #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1163 | |
| AnnaBridge | 189:f392fc9709a3 | 1164 | |
| AnnaBridge | 189:f392fc9709a3 | 1165 | /** @brief Enable or disable the APB3 peripheral clock. |
| AnnaBridge | 189:f392fc9709a3 | 1166 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 1167 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 1168 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 1169 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1170 | |
| AnnaBridge | 189:f392fc9709a3 | 1171 | #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1172 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1173 | SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1174 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1175 | tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1176 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1177 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1178 | |
| AnnaBridge | 189:f392fc9709a3 | 1179 | #define __HAL_RCC_WWDG1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1180 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1181 | SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1182 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1183 | tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1184 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1185 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1186 | |
| AnnaBridge | 189:f392fc9709a3 | 1187 | #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) |
| AnnaBridge | 189:f392fc9709a3 | 1188 | #define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) |
| AnnaBridge | 189:f392fc9709a3 | 1189 | |
| AnnaBridge | 189:f392fc9709a3 | 1190 | |
| AnnaBridge | 189:f392fc9709a3 | 1191 | /** @brief Get the enable or disable status of the APB3 peripheral clock |
| AnnaBridge | 189:f392fc9709a3 | 1192 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 1193 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 1194 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 1195 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1196 | |
| AnnaBridge | 189:f392fc9709a3 | 1197 | #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1198 | #define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1199 | |
| AnnaBridge | 189:f392fc9709a3 | 1200 | #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1201 | #define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1202 | |
| AnnaBridge | 189:f392fc9709a3 | 1203 | |
| AnnaBridge | 189:f392fc9709a3 | 1204 | |
| AnnaBridge | 189:f392fc9709a3 | 1205 | /** @brief Enable or disable the APB1 peripheral clock. |
| AnnaBridge | 189:f392fc9709a3 | 1206 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 1207 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 1208 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 1209 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1210 | |
| AnnaBridge | 189:f392fc9709a3 | 1211 | #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1212 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1213 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1214 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1215 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1216 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1217 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1218 | |
| AnnaBridge | 189:f392fc9709a3 | 1219 | #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1220 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1221 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1222 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1223 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1224 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1225 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1226 | |
| AnnaBridge | 189:f392fc9709a3 | 1227 | #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1228 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1229 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1230 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1231 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1232 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1233 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1234 | |
| AnnaBridge | 189:f392fc9709a3 | 1235 | #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1236 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1237 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1238 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1239 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1240 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1241 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1242 | |
| AnnaBridge | 189:f392fc9709a3 | 1243 | #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1244 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1245 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1246 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1247 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1248 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1249 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1250 | |
| AnnaBridge | 189:f392fc9709a3 | 1251 | #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1252 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1253 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1254 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1255 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1256 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1257 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1258 | |
| AnnaBridge | 189:f392fc9709a3 | 1259 | #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1260 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1261 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1262 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1263 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1264 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1265 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1266 | |
| AnnaBridge | 189:f392fc9709a3 | 1267 | #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1268 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1269 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1270 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1271 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1272 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1273 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1274 | |
| AnnaBridge | 189:f392fc9709a3 | 1275 | #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1276 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1277 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1278 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1279 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1280 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1281 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1282 | |
| AnnaBridge | 189:f392fc9709a3 | 1283 | #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1284 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1285 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1286 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1287 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1288 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1289 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1290 | |
| AnnaBridge | 189:f392fc9709a3 | 1291 | |
| AnnaBridge | 189:f392fc9709a3 | 1292 | #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1293 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1294 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1295 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1296 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1297 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1298 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1299 | |
| AnnaBridge | 189:f392fc9709a3 | 1300 | #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1301 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1302 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1303 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1304 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1305 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1306 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1307 | |
| AnnaBridge | 189:f392fc9709a3 | 1308 | #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1309 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1310 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1311 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1312 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1313 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1314 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1315 | |
| AnnaBridge | 189:f392fc9709a3 | 1316 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1317 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1318 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1319 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1320 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1321 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1322 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1323 | |
| AnnaBridge | 189:f392fc9709a3 | 1324 | #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1325 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1326 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1327 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1328 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1329 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1330 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1331 | |
| AnnaBridge | 189:f392fc9709a3 | 1332 | #define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1333 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1334 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1335 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1336 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1337 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1338 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1339 | |
| AnnaBridge | 189:f392fc9709a3 | 1340 | #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1341 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1342 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1343 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1344 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1345 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1346 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1347 | |
| AnnaBridge | 189:f392fc9709a3 | 1348 | #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1349 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1350 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1351 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1352 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1353 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1354 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1355 | |
| AnnaBridge | 189:f392fc9709a3 | 1356 | #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1357 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1358 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1359 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1360 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1361 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1362 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1363 | |
| AnnaBridge | 189:f392fc9709a3 | 1364 | #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1365 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1366 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1367 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1368 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1369 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1370 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1371 | |
| AnnaBridge | 189:f392fc9709a3 | 1372 | #define __HAL_RCC_CEC_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1373 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1374 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1375 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1376 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1377 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1378 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1379 | |
| AnnaBridge | 189:f392fc9709a3 | 1380 | #define __HAL_RCC_DAC12_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1381 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1382 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1383 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1384 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1385 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1386 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1387 | |
| AnnaBridge | 189:f392fc9709a3 | 1388 | #define __HAL_RCC_UART7_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1389 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1390 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1391 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1392 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1393 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1394 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1395 | |
| AnnaBridge | 189:f392fc9709a3 | 1396 | #define __HAL_RCC_UART8_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1397 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1398 | SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1399 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1400 | tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1401 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1402 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1403 | |
| AnnaBridge | 189:f392fc9709a3 | 1404 | #define __HAL_RCC_CRS_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1405 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1406 | SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1407 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1408 | tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1409 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1410 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1411 | |
| AnnaBridge | 189:f392fc9709a3 | 1412 | #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1413 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1414 | SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1415 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1416 | tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1417 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1418 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1419 | |
| AnnaBridge | 189:f392fc9709a3 | 1420 | #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1421 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1422 | SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1423 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1424 | tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1425 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1426 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1427 | |
| AnnaBridge | 189:f392fc9709a3 | 1428 | #define __HAL_RCC_MDIOS_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1429 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1430 | SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1431 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1432 | tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1433 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1434 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1435 | |
| AnnaBridge | 189:f392fc9709a3 | 1436 | #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1437 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1438 | SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1439 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1440 | tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1441 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1442 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1443 | |
| AnnaBridge | 189:f392fc9709a3 | 1444 | |
| AnnaBridge | 189:f392fc9709a3 | 1445 | #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) |
| AnnaBridge | 189:f392fc9709a3 | 1446 | #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) |
| AnnaBridge | 189:f392fc9709a3 | 1447 | #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) |
| AnnaBridge | 189:f392fc9709a3 | 1448 | #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) |
| AnnaBridge | 189:f392fc9709a3 | 1449 | #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) |
| AnnaBridge | 189:f392fc9709a3 | 1450 | #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) |
| AnnaBridge | 189:f392fc9709a3 | 1451 | #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) |
| AnnaBridge | 189:f392fc9709a3 | 1452 | #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) |
| AnnaBridge | 189:f392fc9709a3 | 1453 | #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) |
| AnnaBridge | 189:f392fc9709a3 | 1454 | #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) |
| AnnaBridge | 189:f392fc9709a3 | 1455 | |
| AnnaBridge | 189:f392fc9709a3 | 1456 | #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) |
| AnnaBridge | 189:f392fc9709a3 | 1457 | #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) |
| AnnaBridge | 189:f392fc9709a3 | 1458 | #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) |
| AnnaBridge | 189:f392fc9709a3 | 1459 | #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) |
| AnnaBridge | 189:f392fc9709a3 | 1460 | #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) |
| AnnaBridge | 189:f392fc9709a3 | 1461 | #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) |
| AnnaBridge | 189:f392fc9709a3 | 1462 | #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) |
| AnnaBridge | 189:f392fc9709a3 | 1463 | #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) |
| AnnaBridge | 189:f392fc9709a3 | 1464 | #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) |
| AnnaBridge | 189:f392fc9709a3 | 1465 | #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) |
| AnnaBridge | 189:f392fc9709a3 | 1466 | #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) |
| AnnaBridge | 189:f392fc9709a3 | 1467 | #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) |
| AnnaBridge | 189:f392fc9709a3 | 1468 | #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) |
| AnnaBridge | 189:f392fc9709a3 | 1469 | #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) |
| AnnaBridge | 189:f392fc9709a3 | 1470 | #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) |
| AnnaBridge | 189:f392fc9709a3 | 1471 | #define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) |
| AnnaBridge | 189:f392fc9709a3 | 1472 | #define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) |
| AnnaBridge | 189:f392fc9709a3 | 1473 | #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) |
| AnnaBridge | 189:f392fc9709a3 | 1474 | #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) |
| AnnaBridge | 189:f392fc9709a3 | 1475 | |
| AnnaBridge | 189:f392fc9709a3 | 1476 | |
| AnnaBridge | 189:f392fc9709a3 | 1477 | /** @brief Get the enable or disable status of the APB1 peripheral clock |
| AnnaBridge | 189:f392fc9709a3 | 1478 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 1479 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 1480 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 1481 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1482 | |
| AnnaBridge | 189:f392fc9709a3 | 1483 | #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1484 | #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1485 | #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1486 | #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1487 | #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1488 | #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1489 | #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1490 | #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1491 | #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1492 | #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1493 | #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1494 | #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1495 | #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1496 | #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1497 | #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1498 | #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1499 | #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1500 | #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1501 | #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1502 | #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1503 | #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1504 | #define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1505 | #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1506 | #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1507 | #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1508 | #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1509 | #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1510 | #define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1511 | #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1512 | |
| AnnaBridge | 189:f392fc9709a3 | 1513 | #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1514 | #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1515 | #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1516 | #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1517 | #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1518 | #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1519 | #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1520 | #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1521 | #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1522 | #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1523 | #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1524 | #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1525 | #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1526 | #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1527 | #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1528 | #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1529 | #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1530 | #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1531 | #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1532 | #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1533 | #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1534 | #define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1535 | #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1536 | #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1537 | #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1538 | #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1539 | #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1540 | #define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1541 | #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1542 | |
| AnnaBridge | 189:f392fc9709a3 | 1543 | |
| AnnaBridge | 189:f392fc9709a3 | 1544 | /** @brief Enable or disable the APB2 peripheral clock. |
| AnnaBridge | 189:f392fc9709a3 | 1545 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 1546 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 1547 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 1548 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1549 | |
| AnnaBridge | 189:f392fc9709a3 | 1550 | #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1551 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1552 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1553 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1554 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1555 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1556 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1557 | |
| AnnaBridge | 189:f392fc9709a3 | 1558 | #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1559 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1560 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1561 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1562 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1563 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1564 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1565 | |
| AnnaBridge | 189:f392fc9709a3 | 1566 | #define __HAL_RCC_USART1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1567 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1568 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1569 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1570 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1571 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1572 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1573 | |
| AnnaBridge | 189:f392fc9709a3 | 1574 | #define __HAL_RCC_USART6_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1575 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1576 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1577 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1578 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1579 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1580 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1581 | |
| AnnaBridge | 189:f392fc9709a3 | 1582 | #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1583 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1584 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1585 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1586 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1587 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1588 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1589 | |
| AnnaBridge | 189:f392fc9709a3 | 1590 | #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1591 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1592 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1593 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1594 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1595 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1596 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1597 | |
| AnnaBridge | 189:f392fc9709a3 | 1598 | #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1599 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1600 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1601 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1602 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1603 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1604 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1605 | |
| AnnaBridge | 189:f392fc9709a3 | 1606 | #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1607 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1608 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1609 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1610 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1611 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1612 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1613 | |
| AnnaBridge | 189:f392fc9709a3 | 1614 | #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1615 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1616 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1617 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1618 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1619 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1620 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1621 | |
| AnnaBridge | 189:f392fc9709a3 | 1622 | #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1623 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1624 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1625 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1626 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1627 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1628 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1629 | |
| AnnaBridge | 189:f392fc9709a3 | 1630 | #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1631 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1632 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1633 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1634 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1635 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1636 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1637 | |
| AnnaBridge | 189:f392fc9709a3 | 1638 | #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1639 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1640 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1641 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1642 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1643 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1644 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1645 | |
| AnnaBridge | 189:f392fc9709a3 | 1646 | #define __HAL_RCC_SAI3_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1647 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1648 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1649 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1650 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1651 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1652 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1653 | |
| AnnaBridge | 189:f392fc9709a3 | 1654 | #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1655 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1656 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1657 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1658 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1659 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1660 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1661 | |
| AnnaBridge | 189:f392fc9709a3 | 1662 | #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1663 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1664 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1665 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1666 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1667 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1668 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1669 | |
| AnnaBridge | 189:f392fc9709a3 | 1670 | #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) |
| AnnaBridge | 189:f392fc9709a3 | 1671 | #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) |
| AnnaBridge | 189:f392fc9709a3 | 1672 | #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) |
| AnnaBridge | 189:f392fc9709a3 | 1673 | #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) |
| AnnaBridge | 189:f392fc9709a3 | 1674 | #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) |
| AnnaBridge | 189:f392fc9709a3 | 1675 | #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) |
| AnnaBridge | 189:f392fc9709a3 | 1676 | #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) |
| AnnaBridge | 189:f392fc9709a3 | 1677 | #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) |
| AnnaBridge | 189:f392fc9709a3 | 1678 | #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) |
| AnnaBridge | 189:f392fc9709a3 | 1679 | #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) |
| AnnaBridge | 189:f392fc9709a3 | 1680 | #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) |
| AnnaBridge | 189:f392fc9709a3 | 1681 | #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) |
| AnnaBridge | 189:f392fc9709a3 | 1682 | #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) |
| AnnaBridge | 189:f392fc9709a3 | 1683 | #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) |
| AnnaBridge | 189:f392fc9709a3 | 1684 | #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) |
| AnnaBridge | 189:f392fc9709a3 | 1685 | |
| AnnaBridge | 189:f392fc9709a3 | 1686 | |
| AnnaBridge | 189:f392fc9709a3 | 1687 | /** @brief Get the enable or disable status of the APB2 peripheral clock |
| AnnaBridge | 189:f392fc9709a3 | 1688 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 1689 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 1690 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 1691 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1692 | |
| AnnaBridge | 189:f392fc9709a3 | 1693 | #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1694 | #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1695 | #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1696 | #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1697 | #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1698 | #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1699 | #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1700 | #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1701 | #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1702 | #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1703 | #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1704 | #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1705 | #define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1706 | #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1707 | #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1708 | |
| AnnaBridge | 189:f392fc9709a3 | 1709 | #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1710 | #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1711 | #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1712 | #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1713 | #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1714 | #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1715 | #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1716 | #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1717 | #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1718 | #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1719 | #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1720 | #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1721 | #define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1722 | #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1723 | #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1724 | |
| AnnaBridge | 189:f392fc9709a3 | 1725 | |
| AnnaBridge | 189:f392fc9709a3 | 1726 | /** @brief Enable or disable the APB4 peripheral clock. |
| AnnaBridge | 189:f392fc9709a3 | 1727 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 1728 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 1729 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 1730 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1731 | |
| AnnaBridge | 189:f392fc9709a3 | 1732 | #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1733 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1734 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1735 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1736 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1737 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1738 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1739 | |
| AnnaBridge | 189:f392fc9709a3 | 1740 | #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1741 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1742 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1743 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1744 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1745 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1746 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1747 | |
| AnnaBridge | 189:f392fc9709a3 | 1748 | #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1749 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1750 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1751 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1752 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1753 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1754 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1755 | |
| AnnaBridge | 189:f392fc9709a3 | 1756 | #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1757 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1758 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1759 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1760 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1761 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1762 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1763 | |
| AnnaBridge | 189:f392fc9709a3 | 1764 | #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1765 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1766 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1767 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1768 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1769 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1770 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1771 | |
| AnnaBridge | 189:f392fc9709a3 | 1772 | #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1773 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1774 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1775 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1776 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1777 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1778 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1779 | |
| AnnaBridge | 189:f392fc9709a3 | 1780 | #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1781 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1782 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1783 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1784 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1785 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1786 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1787 | |
| AnnaBridge | 189:f392fc9709a3 | 1788 | #define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1789 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1790 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1791 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1792 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1793 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1794 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1795 | |
| AnnaBridge | 189:f392fc9709a3 | 1796 | #define __HAL_RCC_COMP12_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1797 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1798 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1799 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1800 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1801 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1802 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1803 | |
| AnnaBridge | 189:f392fc9709a3 | 1804 | #define __HAL_RCC_VREF_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1805 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1806 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1807 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1808 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1809 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1810 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1811 | |
| AnnaBridge | 189:f392fc9709a3 | 1812 | #define __HAL_RCC_SAI4_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1813 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1814 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1815 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1816 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1817 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1818 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1819 | |
| AnnaBridge | 189:f392fc9709a3 | 1820 | #define __HAL_RCC_RTC_CLK_ENABLE() do { \ |
| AnnaBridge | 189:f392fc9709a3 | 1821 | __IO uint32_t tmpreg; \ |
| AnnaBridge | 189:f392fc9709a3 | 1822 | SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1823 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 189:f392fc9709a3 | 1824 | tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ |
| AnnaBridge | 189:f392fc9709a3 | 1825 | UNUSED(tmpreg); \ |
| AnnaBridge | 189:f392fc9709a3 | 1826 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 1827 | |
| AnnaBridge | 189:f392fc9709a3 | 1828 | #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) |
| AnnaBridge | 189:f392fc9709a3 | 1829 | #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) |
| AnnaBridge | 189:f392fc9709a3 | 1830 | #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) |
| AnnaBridge | 189:f392fc9709a3 | 1831 | #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) |
| AnnaBridge | 189:f392fc9709a3 | 1832 | #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) |
| AnnaBridge | 189:f392fc9709a3 | 1833 | #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) |
| AnnaBridge | 189:f392fc9709a3 | 1834 | #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) |
| AnnaBridge | 189:f392fc9709a3 | 1835 | #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) |
| AnnaBridge | 189:f392fc9709a3 | 1836 | #define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) |
| AnnaBridge | 189:f392fc9709a3 | 1837 | #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) |
| AnnaBridge | 189:f392fc9709a3 | 1838 | #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) |
| AnnaBridge | 189:f392fc9709a3 | 1839 | #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) |
| AnnaBridge | 189:f392fc9709a3 | 1840 | |
| AnnaBridge | 189:f392fc9709a3 | 1841 | /** @brief Get the enable or disable status of the APB4 peripheral clock |
| AnnaBridge | 189:f392fc9709a3 | 1842 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 189:f392fc9709a3 | 1843 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 189:f392fc9709a3 | 1844 | * using it. |
| AnnaBridge | 189:f392fc9709a3 | 1845 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1846 | |
| AnnaBridge | 189:f392fc9709a3 | 1847 | #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1848 | #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1849 | #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1850 | #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1851 | #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1852 | #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1853 | #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1854 | #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1855 | #define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1856 | #define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1857 | #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1858 | #define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1859 | |
| AnnaBridge | 189:f392fc9709a3 | 1860 | #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1861 | #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1862 | #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1863 | #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1864 | #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1865 | #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1866 | #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1867 | #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1868 | #define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1869 | #define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1870 | #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1871 | #define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 1872 | |
| AnnaBridge | 189:f392fc9709a3 | 1873 | |
| AnnaBridge | 189:f392fc9709a3 | 1874 | /** @brief Enable or disable the AHB3 peripheral reset. |
| AnnaBridge | 189:f392fc9709a3 | 1875 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1876 | |
| AnnaBridge | 189:f392fc9709a3 | 1877 | #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 1878 | #define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST)) |
| AnnaBridge | 189:f392fc9709a3 | 1879 | #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1880 | #define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1881 | #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1882 | #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1883 | #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST)) |
| AnnaBridge | 189:f392fc9709a3 | 1884 | |
| AnnaBridge | 189:f392fc9709a3 | 1885 | |
| AnnaBridge | 189:f392fc9709a3 | 1886 | #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) |
| AnnaBridge | 189:f392fc9709a3 | 1887 | #define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST)) |
| AnnaBridge | 189:f392fc9709a3 | 1888 | #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1889 | #define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1890 | #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1891 | #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1892 | #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST)) |
| AnnaBridge | 189:f392fc9709a3 | 1893 | |
| AnnaBridge | 189:f392fc9709a3 | 1894 | |
| AnnaBridge | 189:f392fc9709a3 | 1895 | |
| AnnaBridge | 189:f392fc9709a3 | 1896 | /** @brief Force or release the AHB1 peripheral reset. |
| AnnaBridge | 189:f392fc9709a3 | 1897 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1898 | #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 1899 | #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) |
| AnnaBridge | 189:f392fc9709a3 | 1900 | #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) |
| AnnaBridge | 189:f392fc9709a3 | 1901 | #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST)) |
| AnnaBridge | 189:f392fc9709a3 | 1902 | #define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1903 | #define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1904 | #define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1905 | |
| AnnaBridge | 189:f392fc9709a3 | 1906 | #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) |
| AnnaBridge | 189:f392fc9709a3 | 1907 | #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST)) |
| AnnaBridge | 189:f392fc9709a3 | 1908 | #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST)) |
| AnnaBridge | 189:f392fc9709a3 | 1909 | #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST)) |
| AnnaBridge | 189:f392fc9709a3 | 1910 | #define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1911 | #define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1912 | #define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1913 | |
| AnnaBridge | 189:f392fc9709a3 | 1914 | |
| AnnaBridge | 189:f392fc9709a3 | 1915 | /** @brief Force or release the AHB2 peripheral reset. |
| AnnaBridge | 189:f392fc9709a3 | 1916 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1917 | #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 1918 | #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1919 | #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1920 | #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1921 | #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1922 | #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST)) |
| AnnaBridge | 189:f392fc9709a3 | 1923 | |
| AnnaBridge | 189:f392fc9709a3 | 1924 | #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) |
| AnnaBridge | 189:f392fc9709a3 | 1925 | #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1926 | #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1927 | #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1928 | #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST)) |
| AnnaBridge | 189:f392fc9709a3 | 1929 | #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST)) |
| AnnaBridge | 189:f392fc9709a3 | 1930 | |
| AnnaBridge | 189:f392fc9709a3 | 1931 | |
| AnnaBridge | 189:f392fc9709a3 | 1932 | /** @brief Force or release the AHB4 peripheral reset. |
| AnnaBridge | 189:f392fc9709a3 | 1933 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1934 | |
| AnnaBridge | 189:f392fc9709a3 | 1935 | #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0xFFFFFFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 1936 | #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST) |
| AnnaBridge | 189:f392fc9709a3 | 1937 | #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST) |
| AnnaBridge | 189:f392fc9709a3 | 1938 | #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST) |
| AnnaBridge | 189:f392fc9709a3 | 1939 | #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST) |
| AnnaBridge | 189:f392fc9709a3 | 1940 | #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST) |
| AnnaBridge | 189:f392fc9709a3 | 1941 | #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST) |
| AnnaBridge | 189:f392fc9709a3 | 1942 | #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST) |
| AnnaBridge | 189:f392fc9709a3 | 1943 | #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST) |
| AnnaBridge | 189:f392fc9709a3 | 1944 | #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST) |
| AnnaBridge | 189:f392fc9709a3 | 1945 | #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST) |
| AnnaBridge | 189:f392fc9709a3 | 1946 | #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST) |
| AnnaBridge | 189:f392fc9709a3 | 1947 | #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST) |
| AnnaBridge | 189:f392fc9709a3 | 1948 | #define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST) |
| AnnaBridge | 189:f392fc9709a3 | 1949 | #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST) |
| AnnaBridge | 189:f392fc9709a3 | 1950 | #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST) |
| AnnaBridge | 189:f392fc9709a3 | 1951 | |
| AnnaBridge | 189:f392fc9709a3 | 1952 | #define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U) |
| AnnaBridge | 189:f392fc9709a3 | 1953 | #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST) |
| AnnaBridge | 189:f392fc9709a3 | 1954 | #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST) |
| AnnaBridge | 189:f392fc9709a3 | 1955 | #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST) |
| AnnaBridge | 189:f392fc9709a3 | 1956 | #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST) |
| AnnaBridge | 189:f392fc9709a3 | 1957 | #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST) |
| AnnaBridge | 189:f392fc9709a3 | 1958 | #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST) |
| AnnaBridge | 189:f392fc9709a3 | 1959 | #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST) |
| AnnaBridge | 189:f392fc9709a3 | 1960 | #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST) |
| AnnaBridge | 189:f392fc9709a3 | 1961 | #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST) |
| AnnaBridge | 189:f392fc9709a3 | 1962 | #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST) |
| AnnaBridge | 189:f392fc9709a3 | 1963 | #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST) |
| AnnaBridge | 189:f392fc9709a3 | 1964 | #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST) |
| AnnaBridge | 189:f392fc9709a3 | 1965 | #define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST) |
| AnnaBridge | 189:f392fc9709a3 | 1966 | #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST) |
| AnnaBridge | 189:f392fc9709a3 | 1967 | #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST) |
| AnnaBridge | 189:f392fc9709a3 | 1968 | |
| AnnaBridge | 189:f392fc9709a3 | 1969 | |
| AnnaBridge | 189:f392fc9709a3 | 1970 | /** @brief Force or release the APB3 peripheral reset. |
| AnnaBridge | 189:f392fc9709a3 | 1971 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1972 | #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0xFFFFFFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 1973 | #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST) |
| AnnaBridge | 189:f392fc9709a3 | 1974 | |
| AnnaBridge | 189:f392fc9709a3 | 1975 | |
| AnnaBridge | 189:f392fc9709a3 | 1976 | #define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U) |
| AnnaBridge | 189:f392fc9709a3 | 1977 | #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST) |
| AnnaBridge | 189:f392fc9709a3 | 1978 | |
| AnnaBridge | 189:f392fc9709a3 | 1979 | |
| AnnaBridge | 189:f392fc9709a3 | 1980 | /** @brief Force or release the APB1 peripheral reset. |
| AnnaBridge | 189:f392fc9709a3 | 1981 | */ |
| AnnaBridge | 189:f392fc9709a3 | 1982 | #define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xFFFFFFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 1983 | #define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0xFFFFFFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 1984 | #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST) |
| AnnaBridge | 189:f392fc9709a3 | 1985 | #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST) |
| AnnaBridge | 189:f392fc9709a3 | 1986 | #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST) |
| AnnaBridge | 189:f392fc9709a3 | 1987 | #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST) |
| AnnaBridge | 189:f392fc9709a3 | 1988 | #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST) |
| AnnaBridge | 189:f392fc9709a3 | 1989 | #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST) |
| AnnaBridge | 189:f392fc9709a3 | 1990 | #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST) |
| AnnaBridge | 189:f392fc9709a3 | 1991 | #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST) |
| AnnaBridge | 189:f392fc9709a3 | 1992 | #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST) |
| AnnaBridge | 189:f392fc9709a3 | 1993 | #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST) |
| AnnaBridge | 189:f392fc9709a3 | 1994 | #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST) |
| AnnaBridge | 189:f392fc9709a3 | 1995 | #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST) |
| AnnaBridge | 189:f392fc9709a3 | 1996 | #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST) |
| AnnaBridge | 189:f392fc9709a3 | 1997 | #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST) |
| AnnaBridge | 189:f392fc9709a3 | 1998 | #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST) |
| AnnaBridge | 189:f392fc9709a3 | 1999 | #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2000 | #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST) |
| AnnaBridge | 189:f392fc9709a3 | 2001 | #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2002 | #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST) |
| AnnaBridge | 189:f392fc9709a3 | 2003 | #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST) |
| AnnaBridge | 189:f392fc9709a3 | 2004 | #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST) |
| AnnaBridge | 189:f392fc9709a3 | 2005 | #define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST) |
| AnnaBridge | 189:f392fc9709a3 | 2006 | #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST) |
| AnnaBridge | 189:f392fc9709a3 | 2007 | #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST) |
| AnnaBridge | 189:f392fc9709a3 | 2008 | #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST) |
| AnnaBridge | 189:f392fc9709a3 | 2009 | #define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST) |
| AnnaBridge | 189:f392fc9709a3 | 2010 | #define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST) |
| AnnaBridge | 189:f392fc9709a3 | 2011 | #define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST) |
| AnnaBridge | 189:f392fc9709a3 | 2012 | #define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST) |
| AnnaBridge | 189:f392fc9709a3 | 2013 | |
| AnnaBridge | 189:f392fc9709a3 | 2014 | #define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U) |
| AnnaBridge | 189:f392fc9709a3 | 2015 | #define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U) |
| AnnaBridge | 189:f392fc9709a3 | 2016 | #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST) |
| AnnaBridge | 189:f392fc9709a3 | 2017 | #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST) |
| AnnaBridge | 189:f392fc9709a3 | 2018 | #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2019 | #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST) |
| AnnaBridge | 189:f392fc9709a3 | 2020 | #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST) |
| AnnaBridge | 189:f392fc9709a3 | 2021 | #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST) |
| AnnaBridge | 189:f392fc9709a3 | 2022 | #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST) |
| AnnaBridge | 189:f392fc9709a3 | 2023 | #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST) |
| AnnaBridge | 189:f392fc9709a3 | 2024 | #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST) |
| AnnaBridge | 189:f392fc9709a3 | 2025 | #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2026 | #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST) |
| AnnaBridge | 189:f392fc9709a3 | 2027 | #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST) |
| AnnaBridge | 189:f392fc9709a3 | 2028 | #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST) |
| AnnaBridge | 189:f392fc9709a3 | 2029 | #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST) |
| AnnaBridge | 189:f392fc9709a3 | 2030 | #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST) |
| AnnaBridge | 189:f392fc9709a3 | 2031 | #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2032 | #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST) |
| AnnaBridge | 189:f392fc9709a3 | 2033 | #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2034 | #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST) |
| AnnaBridge | 189:f392fc9709a3 | 2035 | #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST) |
| AnnaBridge | 189:f392fc9709a3 | 2036 | #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST) |
| AnnaBridge | 189:f392fc9709a3 | 2037 | #define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST) |
| AnnaBridge | 189:f392fc9709a3 | 2038 | #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST) |
| AnnaBridge | 189:f392fc9709a3 | 2039 | #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST) |
| AnnaBridge | 189:f392fc9709a3 | 2040 | #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST) |
| AnnaBridge | 189:f392fc9709a3 | 2041 | #define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST) |
| AnnaBridge | 189:f392fc9709a3 | 2042 | #define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST) |
| AnnaBridge | 189:f392fc9709a3 | 2043 | #define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST) |
| AnnaBridge | 189:f392fc9709a3 | 2044 | #define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST) |
| AnnaBridge | 189:f392fc9709a3 | 2045 | |
| AnnaBridge | 189:f392fc9709a3 | 2046 | /** @brief Force or release the APB2 peripheral reset. |
| AnnaBridge | 189:f392fc9709a3 | 2047 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2048 | #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 2049 | #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2050 | #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST) |
| AnnaBridge | 189:f392fc9709a3 | 2051 | #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2052 | #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST) |
| AnnaBridge | 189:f392fc9709a3 | 2053 | #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2054 | #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2055 | #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST) |
| AnnaBridge | 189:f392fc9709a3 | 2056 | #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST) |
| AnnaBridge | 189:f392fc9709a3 | 2057 | #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST) |
| AnnaBridge | 189:f392fc9709a3 | 2058 | #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST) |
| AnnaBridge | 189:f392fc9709a3 | 2059 | #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2060 | #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST) |
| AnnaBridge | 189:f392fc9709a3 | 2061 | #define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST) |
| AnnaBridge | 189:f392fc9709a3 | 2062 | #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2063 | #define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST) |
| AnnaBridge | 189:f392fc9709a3 | 2064 | |
| AnnaBridge | 189:f392fc9709a3 | 2065 | #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) |
| AnnaBridge | 189:f392fc9709a3 | 2066 | #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2067 | #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST) |
| AnnaBridge | 189:f392fc9709a3 | 2068 | #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2069 | #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST) |
| AnnaBridge | 189:f392fc9709a3 | 2070 | #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2071 | #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2072 | #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST) |
| AnnaBridge | 189:f392fc9709a3 | 2073 | #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST) |
| AnnaBridge | 189:f392fc9709a3 | 2074 | #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST) |
| AnnaBridge | 189:f392fc9709a3 | 2075 | #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST) |
| AnnaBridge | 189:f392fc9709a3 | 2076 | #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2077 | #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST) |
| AnnaBridge | 189:f392fc9709a3 | 2078 | #define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST) |
| AnnaBridge | 189:f392fc9709a3 | 2079 | #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2080 | #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST) |
| AnnaBridge | 189:f392fc9709a3 | 2081 | |
| AnnaBridge | 189:f392fc9709a3 | 2082 | /** @brief Force or release the APB4 peripheral reset. |
| AnnaBridge | 189:f392fc9709a3 | 2083 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2084 | |
| AnnaBridge | 189:f392fc9709a3 | 2085 | #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0xFFFFFFFFU) |
| AnnaBridge | 189:f392fc9709a3 | 2086 | #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST) |
| AnnaBridge | 189:f392fc9709a3 | 2087 | #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2088 | #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST) |
| AnnaBridge | 189:f392fc9709a3 | 2089 | #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2090 | #define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST) |
| AnnaBridge | 189:f392fc9709a3 | 2091 | #define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST) |
| AnnaBridge | 189:f392fc9709a3 | 2092 | #define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2093 | #define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST) |
| AnnaBridge | 189:f392fc9709a3 | 2094 | #define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST) |
| AnnaBridge | 189:f392fc9709a3 | 2095 | #define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST) |
| AnnaBridge | 189:f392fc9709a3 | 2096 | #define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2097 | |
| AnnaBridge | 189:f392fc9709a3 | 2098 | #define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U) |
| AnnaBridge | 189:f392fc9709a3 | 2099 | #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST) |
| AnnaBridge | 189:f392fc9709a3 | 2100 | #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST) |
| AnnaBridge | 189:f392fc9709a3 | 2101 | #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST) |
| AnnaBridge | 189:f392fc9709a3 | 2102 | #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2103 | #define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST) |
| AnnaBridge | 189:f392fc9709a3 | 2104 | #define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST) |
| AnnaBridge | 189:f392fc9709a3 | 2105 | #define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2106 | #define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST) |
| AnnaBridge | 189:f392fc9709a3 | 2107 | #define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST) |
| AnnaBridge | 189:f392fc9709a3 | 2108 | #define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST) |
| AnnaBridge | 189:f392fc9709a3 | 2109 | #define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST) |
| AnnaBridge | 189:f392fc9709a3 | 2110 | |
| AnnaBridge | 189:f392fc9709a3 | 2111 | /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2112 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2113 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2114 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 189:f392fc9709a3 | 2115 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2116 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2117 | |
| AnnaBridge | 189:f392fc9709a3 | 2118 | |
| AnnaBridge | 189:f392fc9709a3 | 2119 | #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2120 | #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2121 | #define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2122 | #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2123 | #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2124 | #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2125 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2126 | #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2127 | #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2128 | #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2129 | #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2130 | |
| AnnaBridge | 189:f392fc9709a3 | 2131 | |
| AnnaBridge | 189:f392fc9709a3 | 2132 | #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2133 | #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2134 | #define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2135 | #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2136 | #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2137 | #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2138 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2139 | #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2140 | #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2141 | #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2142 | #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2143 | |
| AnnaBridge | 189:f392fc9709a3 | 2144 | |
| AnnaBridge | 189:f392fc9709a3 | 2145 | /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2146 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2147 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2148 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 189:f392fc9709a3 | 2149 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2150 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2151 | |
| AnnaBridge | 189:f392fc9709a3 | 2152 | #define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2153 | #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2154 | #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2155 | #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2156 | #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2157 | #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2158 | #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2159 | #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2160 | #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2161 | #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2162 | #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2163 | |
| AnnaBridge | 189:f392fc9709a3 | 2164 | #define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2165 | #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2166 | #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2167 | #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2168 | #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2169 | #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2170 | #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2171 | #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2172 | #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2173 | #define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2174 | #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2175 | |
| AnnaBridge | 189:f392fc9709a3 | 2176 | |
| AnnaBridge | 189:f392fc9709a3 | 2177 | /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2178 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2179 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2180 | * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. |
| AnnaBridge | 189:f392fc9709a3 | 2181 | * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2182 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2183 | |
| AnnaBridge | 189:f392fc9709a3 | 2184 | #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2185 | #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2186 | #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2187 | #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2188 | #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2189 | #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2190 | #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2191 | #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2192 | #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2193 | |
| AnnaBridge | 189:f392fc9709a3 | 2194 | #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2195 | #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2196 | #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2197 | #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2198 | #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2199 | #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2200 | #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2201 | #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2202 | #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2203 | |
| AnnaBridge | 189:f392fc9709a3 | 2204 | |
| AnnaBridge | 189:f392fc9709a3 | 2205 | /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2206 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2207 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2208 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 189:f392fc9709a3 | 2209 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2210 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2211 | |
| AnnaBridge | 189:f392fc9709a3 | 2212 | #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2213 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2214 | #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2215 | #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2216 | #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2217 | #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2218 | #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2219 | #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2220 | #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2221 | |
| AnnaBridge | 189:f392fc9709a3 | 2222 | #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2223 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2224 | #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2225 | #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2226 | #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2227 | #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2228 | #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2229 | #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2230 | #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2231 | |
| AnnaBridge | 189:f392fc9709a3 | 2232 | |
| AnnaBridge | 189:f392fc9709a3 | 2233 | /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2234 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2235 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2236 | * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. |
| AnnaBridge | 189:f392fc9709a3 | 2237 | * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2238 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2239 | |
| AnnaBridge | 189:f392fc9709a3 | 2240 | #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2241 | #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2242 | #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2243 | #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2244 | #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2245 | #define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2246 | #define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2247 | #define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2248 | |
| AnnaBridge | 189:f392fc9709a3 | 2249 | #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2250 | #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2251 | #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2252 | #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2253 | #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2254 | #define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2255 | #define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2256 | #define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2257 | |
| AnnaBridge | 189:f392fc9709a3 | 2258 | |
| AnnaBridge | 189:f392fc9709a3 | 2259 | /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2260 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2261 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2262 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 189:f392fc9709a3 | 2263 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2264 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2265 | |
| AnnaBridge | 189:f392fc9709a3 | 2266 | #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2267 | #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2268 | #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2269 | #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2270 | #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2271 | #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2272 | #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2273 | #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2274 | |
| AnnaBridge | 189:f392fc9709a3 | 2275 | #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2276 | #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2277 | #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2278 | #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2279 | #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2280 | #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2281 | #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2282 | #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2283 | |
| AnnaBridge | 189:f392fc9709a3 | 2284 | |
| AnnaBridge | 189:f392fc9709a3 | 2285 | /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2286 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2287 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2288 | * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. |
| AnnaBridge | 189:f392fc9709a3 | 2289 | * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2290 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2291 | |
| AnnaBridge | 189:f392fc9709a3 | 2292 | #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2293 | #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2294 | #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2295 | #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2296 | #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2297 | #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2298 | #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2299 | #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2300 | #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2301 | #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2302 | #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2303 | #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2304 | #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2305 | #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2306 | #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2307 | #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2308 | |
| AnnaBridge | 189:f392fc9709a3 | 2309 | #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2310 | #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2311 | #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2312 | #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2313 | #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2314 | #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2315 | #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2316 | #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2317 | #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2318 | #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2319 | #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2320 | #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2321 | #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2322 | #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2323 | #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2324 | #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) |
| AnnaBridge | 189:f392fc9709a3 | 2325 | |
| AnnaBridge | 189:f392fc9709a3 | 2326 | |
| AnnaBridge | 189:f392fc9709a3 | 2327 | /** @brief Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2328 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2329 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2330 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 189:f392fc9709a3 | 2331 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2332 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2333 | |
| AnnaBridge | 189:f392fc9709a3 | 2334 | #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2335 | #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2336 | #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2337 | #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2338 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2339 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2340 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2341 | #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2342 | #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2343 | #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2344 | #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2345 | #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2346 | #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2347 | #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2348 | #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2349 | #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2350 | |
| AnnaBridge | 189:f392fc9709a3 | 2351 | #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2352 | #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2353 | #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2354 | #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2355 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2356 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2357 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2358 | #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2359 | #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2360 | #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2361 | #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2362 | #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2363 | #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2364 | #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2365 | #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2366 | #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2367 | |
| AnnaBridge | 189:f392fc9709a3 | 2368 | |
| AnnaBridge | 189:f392fc9709a3 | 2369 | /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2370 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2371 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2372 | * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. |
| AnnaBridge | 189:f392fc9709a3 | 2373 | * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2374 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2375 | |
| AnnaBridge | 189:f392fc9709a3 | 2376 | #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2377 | #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2378 | |
| AnnaBridge | 189:f392fc9709a3 | 2379 | #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2380 | |
| AnnaBridge | 189:f392fc9709a3 | 2381 | #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2382 | |
| AnnaBridge | 189:f392fc9709a3 | 2383 | |
| AnnaBridge | 189:f392fc9709a3 | 2384 | /** @brief Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2385 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2386 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2387 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 189:f392fc9709a3 | 2388 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2389 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2390 | |
| AnnaBridge | 189:f392fc9709a3 | 2391 | #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2392 | #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2393 | |
| AnnaBridge | 189:f392fc9709a3 | 2394 | #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2395 | #define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2396 | |
| AnnaBridge | 189:f392fc9709a3 | 2397 | |
| AnnaBridge | 189:f392fc9709a3 | 2398 | /** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2399 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2400 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2401 | * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. |
| AnnaBridge | 189:f392fc9709a3 | 2402 | * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2403 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2404 | |
| AnnaBridge | 189:f392fc9709a3 | 2405 | #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2406 | #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2407 | #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2408 | #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2409 | #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2410 | #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2411 | #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2412 | #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2413 | #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2414 | #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2415 | |
| AnnaBridge | 189:f392fc9709a3 | 2416 | #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2417 | #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2418 | #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2419 | #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2420 | #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2421 | #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2422 | #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2423 | #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2424 | #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2425 | #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2426 | #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2427 | #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2428 | #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2429 | #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2430 | #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2431 | #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2432 | #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2433 | #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2434 | #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2435 | |
| AnnaBridge | 189:f392fc9709a3 | 2436 | |
| AnnaBridge | 189:f392fc9709a3 | 2437 | #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2438 | #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2439 | #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2440 | #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2441 | #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2442 | #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2443 | #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2444 | #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2445 | #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2446 | #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2447 | |
| AnnaBridge | 189:f392fc9709a3 | 2448 | #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2449 | #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2450 | #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2451 | #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2452 | #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2453 | #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2454 | #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2455 | #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2456 | #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2457 | #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2458 | #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2459 | #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2460 | #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2461 | #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2462 | #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2463 | #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2464 | #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2465 | #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2466 | #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2467 | |
| AnnaBridge | 189:f392fc9709a3 | 2468 | |
| AnnaBridge | 189:f392fc9709a3 | 2469 | /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2470 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2471 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2472 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 189:f392fc9709a3 | 2473 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2474 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2475 | |
| AnnaBridge | 189:f392fc9709a3 | 2476 | #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2477 | #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2478 | #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2479 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2480 | #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2481 | #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2482 | #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2483 | #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2484 | #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2485 | #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2486 | #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2487 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2488 | #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2489 | #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2490 | #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2491 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2492 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2493 | #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2494 | #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2495 | #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2496 | #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2497 | #define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2498 | #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2499 | #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2500 | #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2501 | #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2502 | #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2503 | #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2504 | #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2505 | |
| AnnaBridge | 189:f392fc9709a3 | 2506 | #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2507 | #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2508 | #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2509 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2510 | #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2511 | #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2512 | #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2513 | #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2514 | #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2515 | #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2516 | #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2517 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2518 | #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2519 | #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2520 | #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2521 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2522 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2523 | #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2524 | #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2525 | #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2526 | #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2527 | #define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2528 | #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2529 | #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2530 | #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2531 | #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2532 | #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2533 | #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2534 | #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2535 | |
| AnnaBridge | 189:f392fc9709a3 | 2536 | |
| AnnaBridge | 189:f392fc9709a3 | 2537 | /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2538 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2539 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2540 | * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. |
| AnnaBridge | 189:f392fc9709a3 | 2541 | * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2542 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2543 | |
| AnnaBridge | 189:f392fc9709a3 | 2544 | #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2545 | #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2546 | #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2547 | #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2548 | #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2549 | #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2550 | #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2551 | #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2552 | #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2553 | #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2554 | #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2555 | #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2556 | #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2557 | #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2558 | #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2559 | |
| AnnaBridge | 189:f392fc9709a3 | 2560 | #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2561 | #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2562 | #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2563 | #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2564 | #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2565 | #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2566 | #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2567 | #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2568 | #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2569 | #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2570 | #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2571 | #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2572 | #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2573 | #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2574 | #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2575 | |
| AnnaBridge | 189:f392fc9709a3 | 2576 | |
| AnnaBridge | 189:f392fc9709a3 | 2577 | /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2578 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2579 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2580 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 189:f392fc9709a3 | 2581 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2582 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2583 | |
| AnnaBridge | 189:f392fc9709a3 | 2584 | #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2585 | #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2586 | #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2587 | #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2588 | #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2589 | #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2590 | #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2591 | #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2592 | #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2593 | #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2594 | #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2595 | #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2596 | #define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2597 | #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2598 | #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2599 | |
| AnnaBridge | 189:f392fc9709a3 | 2600 | #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2601 | #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2602 | #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2603 | #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2604 | #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2605 | #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2606 | #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2607 | #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2608 | #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2609 | #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2610 | #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2611 | #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2612 | #define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2613 | #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2614 | #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2615 | |
| AnnaBridge | 189:f392fc9709a3 | 2616 | |
| AnnaBridge | 189:f392fc9709a3 | 2617 | /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2618 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2619 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2620 | * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. |
| AnnaBridge | 189:f392fc9709a3 | 2621 | * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2622 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2623 | |
| AnnaBridge | 189:f392fc9709a3 | 2624 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2625 | #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2626 | #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2627 | #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2628 | #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2629 | #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2630 | #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2631 | #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2632 | #define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2633 | #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2634 | #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2635 | #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2636 | |
| AnnaBridge | 189:f392fc9709a3 | 2637 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2638 | #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2639 | #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2640 | #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2641 | #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2642 | #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2643 | #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2644 | #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2645 | #define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2646 | #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2647 | #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2648 | #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) |
| AnnaBridge | 189:f392fc9709a3 | 2649 | |
| AnnaBridge | 189:f392fc9709a3 | 2650 | |
| AnnaBridge | 189:f392fc9709a3 | 2651 | |
| AnnaBridge | 189:f392fc9709a3 | 2652 | /** @brief Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode. |
| AnnaBridge | 189:f392fc9709a3 | 2653 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 189:f392fc9709a3 | 2654 | * power consumption. |
| AnnaBridge | 189:f392fc9709a3 | 2655 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 189:f392fc9709a3 | 2656 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 189:f392fc9709a3 | 2657 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2658 | |
| AnnaBridge | 189:f392fc9709a3 | 2659 | #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2660 | #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2661 | #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2662 | #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2663 | #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2664 | #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2665 | #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2666 | #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2667 | #define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2668 | #define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2669 | #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2670 | #define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2671 | |
| AnnaBridge | 189:f392fc9709a3 | 2672 | #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2673 | #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2674 | #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2675 | #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2676 | #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2677 | #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2678 | #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2679 | #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2680 | #define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2681 | #define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2682 | #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2683 | #define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U) |
| AnnaBridge | 189:f392fc9709a3 | 2684 | |
| AnnaBridge | 189:f392fc9709a3 | 2685 | /** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN |
| AnnaBridge | 189:f392fc9709a3 | 2686 | * @note After reset (default config), peripheral clock is disabled when CPU is in CSTOP |
| AnnaBridge | 189:f392fc9709a3 | 2687 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2688 | |
| AnnaBridge | 189:f392fc9709a3 | 2689 | #define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2690 | #define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2691 | #define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2692 | #define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2693 | #define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2694 | #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2695 | #define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2696 | #define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2697 | #define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2698 | #define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2699 | #define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2700 | #define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2701 | #define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2702 | #define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2703 | |
| AnnaBridge | 189:f392fc9709a3 | 2704 | #define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2705 | #define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2706 | |
| AnnaBridge | 189:f392fc9709a3 | 2707 | #define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2708 | #define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2709 | #define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2710 | #define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2711 | #define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2712 | #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2713 | #define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2714 | #define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2715 | #define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2716 | #define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2717 | #define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_RTCAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2718 | #define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_CRCAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2719 | #define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_SAI4AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2720 | #define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_ADC3AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2721 | |
| AnnaBridge | 189:f392fc9709a3 | 2722 | #define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2723 | #define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN) |
| AnnaBridge | 189:f392fc9709a3 | 2724 | |
| AnnaBridge | 189:f392fc9709a3 | 2725 | |
| AnnaBridge | 189:f392fc9709a3 | 2726 | /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). |
| AnnaBridge | 189:f392fc9709a3 | 2727 | * @note After enabling the HSI, the application software should wait on |
| AnnaBridge | 189:f392fc9709a3 | 2728 | * HSIRDY flag to be set indicating that HSI clock is stable and can |
| AnnaBridge | 189:f392fc9709a3 | 2729 | * be used to clock the PLL and/or system clock. |
| AnnaBridge | 189:f392fc9709a3 | 2730 | * @note HSI can not be stopped if it is used directly or through the PLL |
| AnnaBridge | 189:f392fc9709a3 | 2731 | * as system clock. In this case, you have to select another source |
| AnnaBridge | 189:f392fc9709a3 | 2732 | * of the system clock then stop the HSI. |
| AnnaBridge | 189:f392fc9709a3 | 2733 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
| AnnaBridge | 189:f392fc9709a3 | 2734 | * @param __STATE__ specifies the new state of the HSI. |
| AnnaBridge | 189:f392fc9709a3 | 2735 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2736 | * @arg RCC_HSI_OFF turn OFF the HSI oscillator |
| AnnaBridge | 189:f392fc9709a3 | 2737 | * @arg RCC_HSI_ON turn ON the HSI oscillator |
| AnnaBridge | 189:f392fc9709a3 | 2738 | * @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset) |
| AnnaBridge | 189:f392fc9709a3 | 2739 | * @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2 |
| AnnaBridge | 189:f392fc9709a3 | 2740 | * @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4 |
| AnnaBridge | 189:f392fc9709a3 | 2741 | * @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8 |
| AnnaBridge | 189:f392fc9709a3 | 2742 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
| AnnaBridge | 189:f392fc9709a3 | 2743 | * clock cycles. |
| AnnaBridge | 189:f392fc9709a3 | 2744 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2745 | #define __HAL_RCC_HSI_CONFIG(__STATE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 2746 | MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__)) |
| AnnaBridge | 189:f392fc9709a3 | 2747 | |
| AnnaBridge | 189:f392fc9709a3 | 2748 | |
| AnnaBridge | 189:f392fc9709a3 | 2749 | /** @brief Macro to get the HSI divider. |
| AnnaBridge | 189:f392fc9709a3 | 2750 | * @retval The HSI divider. The returned value can be one |
| AnnaBridge | 189:f392fc9709a3 | 2751 | * of the following: |
| AnnaBridge | 189:f392fc9709a3 | 2752 | * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset) |
| AnnaBridge | 189:f392fc9709a3 | 2753 | * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 |
| AnnaBridge | 189:f392fc9709a3 | 2754 | * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 |
| AnnaBridge | 189:f392fc9709a3 | 2755 | * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 |
| AnnaBridge | 189:f392fc9709a3 | 2756 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2757 | #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) |
| AnnaBridge | 189:f392fc9709a3 | 2758 | |
| AnnaBridge | 189:f392fc9709a3 | 2759 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
| AnnaBridge | 189:f392fc9709a3 | 2760 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
| AnnaBridge | 189:f392fc9709a3 | 2761 | * It is used (enabled by hardware) as system clock source after start-up |
| AnnaBridge | 189:f392fc9709a3 | 2762 | * from Reset, wakeup from STOP and STANDBY mode, or in case of failure |
| AnnaBridge | 189:f392fc9709a3 | 2763 | * of the HSE used directly or indirectly as system clock (if the Clock |
| AnnaBridge | 189:f392fc9709a3 | 2764 | * Security System CSS is enabled). |
| AnnaBridge | 189:f392fc9709a3 | 2765 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
| AnnaBridge | 189:f392fc9709a3 | 2766 | * you have to select another source of the system clock then stop the HSI. |
| AnnaBridge | 189:f392fc9709a3 | 2767 | * @note After enabling the HSI, the application software should wait on HSIRDY |
| AnnaBridge | 189:f392fc9709a3 | 2768 | * flag to be set indicating that HSI clock is stable and can be used as |
| AnnaBridge | 189:f392fc9709a3 | 2769 | * system clock source. |
| AnnaBridge | 189:f392fc9709a3 | 2770 | * This parameter can be: ENABLE or DISABLE. |
| AnnaBridge | 189:f392fc9709a3 | 2771 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
| AnnaBridge | 189:f392fc9709a3 | 2772 | * clock cycles. |
| AnnaBridge | 189:f392fc9709a3 | 2773 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2774 | #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) |
| AnnaBridge | 189:f392fc9709a3 | 2775 | #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) |
| AnnaBridge | 189:f392fc9709a3 | 2776 | |
| AnnaBridge | 189:f392fc9709a3 | 2777 | |
| AnnaBridge | 189:f392fc9709a3 | 2778 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
| AnnaBridge | 189:f392fc9709a3 | 2779 | * @note The calibration is used to compensate for the variations in voltage |
| AnnaBridge | 189:f392fc9709a3 | 2780 | * and temperature that influence the frequency of the internal HSI RC. |
| AnnaBridge | 189:f392fc9709a3 | 2781 | * @param __HSICalibrationValue__: specifies the calibration trimming value. |
| AnnaBridge | 189:f392fc9709a3 | 2782 | * This parameter must be a number between 0 and 0x3F. |
| AnnaBridge | 189:f392fc9709a3 | 2783 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2784 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ |
| AnnaBridge | 189:f392fc9709a3 | 2785 | MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_ICSCR_HSITRIM_Pos) |
| AnnaBridge | 189:f392fc9709a3 | 2786 | |
| AnnaBridge | 189:f392fc9709a3 | 2787 | |
| AnnaBridge | 189:f392fc9709a3 | 2788 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2789 | * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) |
| AnnaBridge | 189:f392fc9709a3 | 2790 | * in STOP mode to be quickly available as kernel clock for some peripherals. |
| AnnaBridge | 189:f392fc9709a3 | 2791 | * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication |
| AnnaBridge | 189:f392fc9709a3 | 2792 | * speed because of the HSI start-up time. |
| AnnaBridge | 189:f392fc9709a3 | 2793 | * @note The enable of this function has not effect on the HSION bit. |
| AnnaBridge | 189:f392fc9709a3 | 2794 | * This parameter can be: ENABLE or DISABLE. |
| AnnaBridge | 189:f392fc9709a3 | 2795 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2796 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2797 | #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) |
| AnnaBridge | 189:f392fc9709a3 | 2798 | #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) |
| AnnaBridge | 189:f392fc9709a3 | 2799 | |
| AnnaBridge | 189:f392fc9709a3 | 2800 | |
| AnnaBridge | 189:f392fc9709a3 | 2801 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2802 | * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). |
| AnnaBridge | 189:f392fc9709a3 | 2803 | * @note After enabling the HSI48, the application software should wait on |
| AnnaBridge | 189:f392fc9709a3 | 2804 | * HSI48RDY flag to be set indicating that HSI48 clock is stable and can |
| AnnaBridge | 189:f392fc9709a3 | 2805 | * be used to clock the USB. |
| AnnaBridge | 189:f392fc9709a3 | 2806 | * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. |
| AnnaBridge | 189:f392fc9709a3 | 2807 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2808 | #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON); |
| AnnaBridge | 189:f392fc9709a3 | 2809 | |
| AnnaBridge | 189:f392fc9709a3 | 2810 | #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); |
| AnnaBridge | 189:f392fc9709a3 | 2811 | |
| AnnaBridge | 189:f392fc9709a3 | 2812 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2813 | * @brief Macros to enable or disable the Internal oscillator (CSI). |
| AnnaBridge | 189:f392fc9709a3 | 2814 | * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. |
| AnnaBridge | 189:f392fc9709a3 | 2815 | * It is used (enabled by hardware) as system clock source after |
| AnnaBridge | 189:f392fc9709a3 | 2816 | * start-up from Reset, wakeup from STOP and STANDBY mode, or in case |
| AnnaBridge | 189:f392fc9709a3 | 2817 | * of failure of the HSE used directly or indirectly as system clock |
| AnnaBridge | 189:f392fc9709a3 | 2818 | * (if the Clock Security System CSS is enabled). |
| AnnaBridge | 189:f392fc9709a3 | 2819 | * @note CSI can not be stopped if it is used as system clock source. |
| AnnaBridge | 189:f392fc9709a3 | 2820 | * In this case, you have to select another source of the system |
| AnnaBridge | 189:f392fc9709a3 | 2821 | * clock then stop the CSI. |
| AnnaBridge | 189:f392fc9709a3 | 2822 | * @note After enabling the CSI, the application software should wait on |
| AnnaBridge | 189:f392fc9709a3 | 2823 | * CSIRDY flag to be set indicating that CSI clock is stable and can |
| AnnaBridge | 189:f392fc9709a3 | 2824 | * be used as system clock source. |
| AnnaBridge | 189:f392fc9709a3 | 2825 | * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator |
| AnnaBridge | 189:f392fc9709a3 | 2826 | * clock cycles. |
| AnnaBridge | 189:f392fc9709a3 | 2827 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2828 | #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) |
| AnnaBridge | 189:f392fc9709a3 | 2829 | #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) |
| AnnaBridge | 189:f392fc9709a3 | 2830 | |
| AnnaBridge | 189:f392fc9709a3 | 2831 | /** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. |
| AnnaBridge | 189:f392fc9709a3 | 2832 | * @note The calibration is used to compensate for the variations in voltage |
| AnnaBridge | 189:f392fc9709a3 | 2833 | * and temperature that influence the frequency of the internal CSI RC. |
| AnnaBridge | 189:f392fc9709a3 | 2834 | * @param __CSICalibrationValue__: specifies the calibration trimming value. |
| AnnaBridge | 189:f392fc9709a3 | 2835 | * This parameter must be a number between 0 and 0x1F. |
| AnnaBridge | 189:f392fc9709a3 | 2836 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2837 | #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ |
| AnnaBridge | 189:f392fc9709a3 | 2838 | MODIFY_REG(RCC->ICSCR, RCC_ICSCR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_ICSCR_CSITRIM_Pos) |
| AnnaBridge | 189:f392fc9709a3 | 2839 | |
| AnnaBridge | 189:f392fc9709a3 | 2840 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2841 | * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) |
| AnnaBridge | 189:f392fc9709a3 | 2842 | * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. |
| AnnaBridge | 189:f392fc9709a3 | 2843 | * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication |
| AnnaBridge | 189:f392fc9709a3 | 2844 | * speed because of the CSI start-up time. |
| AnnaBridge | 189:f392fc9709a3 | 2845 | * @note The enable of this function has not effect on the CSION bit. |
| AnnaBridge | 189:f392fc9709a3 | 2846 | * This parameter can be: ENABLE or DISABLE. |
| AnnaBridge | 189:f392fc9709a3 | 2847 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 2848 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2849 | #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) |
| AnnaBridge | 189:f392fc9709a3 | 2850 | #define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) |
| AnnaBridge | 189:f392fc9709a3 | 2851 | |
| AnnaBridge | 189:f392fc9709a3 | 2852 | |
| AnnaBridge | 189:f392fc9709a3 | 2853 | /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). |
| AnnaBridge | 189:f392fc9709a3 | 2854 | * @note After enabling the LSI, the application software should wait on |
| AnnaBridge | 189:f392fc9709a3 | 2855 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
| AnnaBridge | 189:f392fc9709a3 | 2856 | * be used to clock the IWDG and/or the RTC. |
| AnnaBridge | 189:f392fc9709a3 | 2857 | * @note LSI can not be disabled if the IWDG is running. |
| AnnaBridge | 189:f392fc9709a3 | 2858 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
| AnnaBridge | 189:f392fc9709a3 | 2859 | * clock cycles. |
| AnnaBridge | 189:f392fc9709a3 | 2860 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2861 | #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) |
| AnnaBridge | 189:f392fc9709a3 | 2862 | #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) |
| AnnaBridge | 189:f392fc9709a3 | 2863 | |
| AnnaBridge | 189:f392fc9709a3 | 2864 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2865 | * @brief Macro to configure the External High Speed oscillator (__HSE__). |
| AnnaBridge | 189:f392fc9709a3 | 2866 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
| AnnaBridge | 189:f392fc9709a3 | 2867 | * software should wait on HSERDY flag to be set indicating that HSE clock |
| AnnaBridge | 189:f392fc9709a3 | 2868 | * is stable and can be used to clock the PLL and/or system clock. |
| AnnaBridge | 189:f392fc9709a3 | 2869 | * @note HSE state can not be changed if it is used directly or through the |
| AnnaBridge | 189:f392fc9709a3 | 2870 | * PLL as system clock. In this case, you have to select another source |
| AnnaBridge | 189:f392fc9709a3 | 2871 | * of the system clock then change the HSE state (ex. disable it). |
| AnnaBridge | 189:f392fc9709a3 | 2872 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
| AnnaBridge | 189:f392fc9709a3 | 2873 | * @note This function reset the CSSON bit, so if the clock security system(CSS) |
| AnnaBridge | 189:f392fc9709a3 | 2874 | * was previously enabled you have to enable it again after calling this |
| AnnaBridge | 189:f392fc9709a3 | 2875 | * function. |
| AnnaBridge | 189:f392fc9709a3 | 2876 | * @param __STATE__: specifies the new state of the HSE. |
| AnnaBridge | 189:f392fc9709a3 | 2877 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2878 | * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after |
| AnnaBridge | 189:f392fc9709a3 | 2879 | * 6 HSE oscillator clock cycles. |
| AnnaBridge | 189:f392fc9709a3 | 2880 | * @arg RCC_HSE_ON: turn ON the HSE oscillator. |
| AnnaBridge | 189:f392fc9709a3 | 2881 | * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. |
| AnnaBridge | 189:f392fc9709a3 | 2882 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2883 | #define __HAL_RCC_HSE_CONFIG(__STATE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 2884 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 2885 | if ((__STATE__) == RCC_HSE_ON) \ |
| AnnaBridge | 189:f392fc9709a3 | 2886 | { \ |
| AnnaBridge | 189:f392fc9709a3 | 2887 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
| AnnaBridge | 189:f392fc9709a3 | 2888 | } \ |
| AnnaBridge | 189:f392fc9709a3 | 2889 | else if ((__STATE__) == RCC_HSE_OFF) \ |
| AnnaBridge | 189:f392fc9709a3 | 2890 | { \ |
| AnnaBridge | 189:f392fc9709a3 | 2891 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
| AnnaBridge | 189:f392fc9709a3 | 2892 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
| AnnaBridge | 189:f392fc9709a3 | 2893 | } \ |
| AnnaBridge | 189:f392fc9709a3 | 2894 | else if ((__STATE__) == RCC_HSE_BYPASS) \ |
| AnnaBridge | 189:f392fc9709a3 | 2895 | { \ |
| AnnaBridge | 189:f392fc9709a3 | 2896 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
| AnnaBridge | 189:f392fc9709a3 | 2897 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
| AnnaBridge | 189:f392fc9709a3 | 2898 | } \ |
| AnnaBridge | 189:f392fc9709a3 | 2899 | else \ |
| AnnaBridge | 189:f392fc9709a3 | 2900 | { \ |
| AnnaBridge | 189:f392fc9709a3 | 2901 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
| AnnaBridge | 189:f392fc9709a3 | 2902 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
| AnnaBridge | 189:f392fc9709a3 | 2903 | } \ |
| AnnaBridge | 189:f392fc9709a3 | 2904 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 2905 | |
| AnnaBridge | 189:f392fc9709a3 | 2906 | /** @defgroup RCC_LSE_Configuration LSE Configuration |
| AnnaBridge | 189:f392fc9709a3 | 2907 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 2908 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2909 | |
| AnnaBridge | 189:f392fc9709a3 | 2910 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2911 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
| AnnaBridge | 189:f392fc9709a3 | 2912 | * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. |
| AnnaBridge | 189:f392fc9709a3 | 2913 | * User should request a transition to LSE Off first and then LSE On or LSE Bypass. |
| AnnaBridge | 189:f392fc9709a3 | 2914 | * @note As the LSE is in the Backup domain and write access is denied to |
| AnnaBridge | 189:f392fc9709a3 | 2915 | * this domain after reset, you have to enable write access using |
| AnnaBridge | 189:f392fc9709a3 | 2916 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
| AnnaBridge | 189:f392fc9709a3 | 2917 | * (to be done once after reset). |
| AnnaBridge | 189:f392fc9709a3 | 2918 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
| AnnaBridge | 189:f392fc9709a3 | 2919 | * software should wait on LSERDY flag to be set indicating that LSE clock |
| AnnaBridge | 189:f392fc9709a3 | 2920 | * is stable and can be used to clock the RTC. |
| AnnaBridge | 189:f392fc9709a3 | 2921 | * @param __STATE__: specifies the new state of the LSE. |
| AnnaBridge | 189:f392fc9709a3 | 2922 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2923 | * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after |
| AnnaBridge | 189:f392fc9709a3 | 2924 | * 6 LSE oscillator clock cycles. |
| AnnaBridge | 189:f392fc9709a3 | 2925 | * @arg RCC_LSE_ON: turn ON the LSE oscillator. |
| AnnaBridge | 189:f392fc9709a3 | 2926 | * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. |
| AnnaBridge | 189:f392fc9709a3 | 2927 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2928 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 2929 | do { \ |
| AnnaBridge | 189:f392fc9709a3 | 2930 | if((__STATE__) == RCC_LSE_ON) \ |
| AnnaBridge | 189:f392fc9709a3 | 2931 | { \ |
| AnnaBridge | 189:f392fc9709a3 | 2932 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| AnnaBridge | 189:f392fc9709a3 | 2933 | } \ |
| AnnaBridge | 189:f392fc9709a3 | 2934 | else if((__STATE__) == RCC_LSE_OFF) \ |
| AnnaBridge | 189:f392fc9709a3 | 2935 | { \ |
| AnnaBridge | 189:f392fc9709a3 | 2936 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| AnnaBridge | 189:f392fc9709a3 | 2937 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
| AnnaBridge | 189:f392fc9709a3 | 2938 | } \ |
| AnnaBridge | 189:f392fc9709a3 | 2939 | else if((__STATE__) == RCC_LSE_BYPASS) \ |
| AnnaBridge | 189:f392fc9709a3 | 2940 | { \ |
| AnnaBridge | 189:f392fc9709a3 | 2941 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
| AnnaBridge | 189:f392fc9709a3 | 2942 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| AnnaBridge | 189:f392fc9709a3 | 2943 | } \ |
| AnnaBridge | 189:f392fc9709a3 | 2944 | else \ |
| AnnaBridge | 189:f392fc9709a3 | 2945 | { \ |
| AnnaBridge | 189:f392fc9709a3 | 2946 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| AnnaBridge | 189:f392fc9709a3 | 2947 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
| AnnaBridge | 189:f392fc9709a3 | 2948 | } \ |
| AnnaBridge | 189:f392fc9709a3 | 2949 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 2950 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2951 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 2952 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2953 | |
| AnnaBridge | 189:f392fc9709a3 | 2954 | /** @brief Macros to enable or disable the the RTC clock. |
| AnnaBridge | 189:f392fc9709a3 | 2955 | * @note These macros must be used only after the RTC clock source was selected. |
| AnnaBridge | 189:f392fc9709a3 | 2956 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2957 | #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) |
| AnnaBridge | 189:f392fc9709a3 | 2958 | #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) |
| AnnaBridge | 189:f392fc9709a3 | 2959 | |
| AnnaBridge | 189:f392fc9709a3 | 2960 | /** @brief Macros to configure the RTC clock (RTCCLK). |
| AnnaBridge | 189:f392fc9709a3 | 2961 | * @note As the RTC clock configuration bits are in the Backup domain and write |
| AnnaBridge | 189:f392fc9709a3 | 2962 | * access is denied to this domain after reset, you have to enable write |
| AnnaBridge | 189:f392fc9709a3 | 2963 | * access using the Power Backup Access macro before to configure |
| AnnaBridge | 189:f392fc9709a3 | 2964 | * the RTC clock source (to be done once after reset). |
| AnnaBridge | 189:f392fc9709a3 | 2965 | * @note Once the RTC clock is configured it can't be changed unless the |
| AnnaBridge | 189:f392fc9709a3 | 2966 | * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by |
| AnnaBridge | 189:f392fc9709a3 | 2967 | * a Power On Reset (POR). |
| AnnaBridge | 189:f392fc9709a3 | 2968 | * @param __RTCCLKSource__: specifies the RTC clock source. |
| AnnaBridge | 189:f392fc9709a3 | 2969 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 2970 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. |
| AnnaBridge | 189:f392fc9709a3 | 2971 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. |
| AnnaBridge | 189:f392fc9709a3 | 2972 | * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected |
| AnnaBridge | 189:f392fc9709a3 | 2973 | * as RTC clock, where x:[2,31] |
| AnnaBridge | 189:f392fc9709a3 | 2974 | * @note If the LSE or LSI is used as RTC clock source, the RTC continues to |
| AnnaBridge | 189:f392fc9709a3 | 2975 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
| AnnaBridge | 189:f392fc9709a3 | 2976 | * However, when the HSE clock is used as RTC clock source, the RTC |
| AnnaBridge | 189:f392fc9709a3 | 2977 | * cannot be used in STOP and STANDBY modes. |
| AnnaBridge | 189:f392fc9709a3 | 2978 | * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as |
| AnnaBridge | 189:f392fc9709a3 | 2979 | * RTC clock source). |
| AnnaBridge | 189:f392fc9709a3 | 2980 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2981 | #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ |
| AnnaBridge | 189:f392fc9709a3 | 2982 | MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) |
| AnnaBridge | 189:f392fc9709a3 | 2983 | |
| AnnaBridge | 189:f392fc9709a3 | 2984 | #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ |
| AnnaBridge | 189:f392fc9709a3 | 2985 | RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ |
| AnnaBridge | 189:f392fc9709a3 | 2986 | } while (0) |
| AnnaBridge | 189:f392fc9709a3 | 2987 | |
| AnnaBridge | 189:f392fc9709a3 | 2988 | #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) |
| AnnaBridge | 189:f392fc9709a3 | 2989 | |
| AnnaBridge | 189:f392fc9709a3 | 2990 | |
| AnnaBridge | 189:f392fc9709a3 | 2991 | /** @brief Macros to force or release the Backup domain reset. |
| AnnaBridge | 189:f392fc9709a3 | 2992 | * @note This function resets the RTC peripheral (including the backup registers) |
| AnnaBridge | 189:f392fc9709a3 | 2993 | * and the RTC clock source selection in RCC_CSR register. |
| AnnaBridge | 189:f392fc9709a3 | 2994 | * @note The BKPSRAM is not affected by this reset. |
| AnnaBridge | 189:f392fc9709a3 | 2995 | */ |
| AnnaBridge | 189:f392fc9709a3 | 2996 | #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) |
| AnnaBridge | 189:f392fc9709a3 | 2997 | #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) |
| AnnaBridge | 189:f392fc9709a3 | 2998 | |
| AnnaBridge | 189:f392fc9709a3 | 2999 | /** @brief Macros to enable or disable the main PLL. |
| AnnaBridge | 189:f392fc9709a3 | 3000 | * @note After enabling the main PLL, the application software should wait on |
| AnnaBridge | 189:f392fc9709a3 | 3001 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
| AnnaBridge | 189:f392fc9709a3 | 3002 | * be used as system clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3003 | * @note The main PLL can not be disabled if it is used as system clock source |
| AnnaBridge | 189:f392fc9709a3 | 3004 | * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. |
| AnnaBridge | 189:f392fc9709a3 | 3005 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3006 | #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) |
| AnnaBridge | 189:f392fc9709a3 | 3007 | #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) |
| AnnaBridge | 189:f392fc9709a3 | 3008 | |
| AnnaBridge | 189:f392fc9709a3 | 3009 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3010 | * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) |
| AnnaBridge | 189:f392fc9709a3 | 3011 | * @note Enabling/disabling those Clocks can be done only when the PLL is disabled. |
| AnnaBridge | 189:f392fc9709a3 | 3012 | * This is mainly used to save Power. |
| AnnaBridge | 189:f392fc9709a3 | 3013 | * (The ck_pll_p of the System PLL cannot be stopped if used as System Clock). |
| AnnaBridge | 189:f392fc9709a3 | 3014 | * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted |
| AnnaBridge | 189:f392fc9709a3 | 3015 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3016 | * @arg RCC_PLL1_DIVP: This clock is used to generate system clock (up to 400MHZ) |
| AnnaBridge | 189:f392fc9709a3 | 3017 | * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ) |
| AnnaBridge | 189:f392fc9709a3 | 3018 | * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock (up to 400MHZ) |
| AnnaBridge | 189:f392fc9709a3 | 3019 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3020 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3021 | #define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) |
| AnnaBridge | 189:f392fc9709a3 | 3022 | |
| AnnaBridge | 189:f392fc9709a3 | 3023 | #define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) |
| AnnaBridge | 189:f392fc9709a3 | 3024 | |
| AnnaBridge | 189:f392fc9709a3 | 3025 | |
| AnnaBridge | 189:f392fc9709a3 | 3026 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3027 | * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO |
| AnnaBridge | 189:f392fc9709a3 | 3028 | * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 |
| AnnaBridge | 189:f392fc9709a3 | 3029 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3030 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3031 | #define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) |
| AnnaBridge | 189:f392fc9709a3 | 3032 | |
| AnnaBridge | 189:f392fc9709a3 | 3033 | #define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) |
| AnnaBridge | 189:f392fc9709a3 | 3034 | |
| AnnaBridge | 189:f392fc9709a3 | 3035 | |
| AnnaBridge | 189:f392fc9709a3 | 3036 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3037 | * @brief Macro to configures the main PLL clock source, multiplication and division factors. |
| AnnaBridge | 189:f392fc9709a3 | 3038 | * @note This function must be used only when the main PLL is disabled. |
| AnnaBridge | 189:f392fc9709a3 | 3039 | * |
| AnnaBridge | 189:f392fc9709a3 | 3040 | * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3041 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3042 | * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry |
| AnnaBridge | 189:f392fc9709a3 | 3043 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
| AnnaBridge | 189:f392fc9709a3 | 3044 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
| AnnaBridge | 189:f392fc9709a3 | 3045 | * @note This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . |
| AnnaBridge | 189:f392fc9709a3 | 3046 | * |
| AnnaBridge | 189:f392fc9709a3 | 3047 | * @param __PLLM1__: specifies the division factor for PLL VCO input clock |
| AnnaBridge | 189:f392fc9709a3 | 3048 | * This parameter must be a number between 1 and 63. |
| AnnaBridge | 189:f392fc9709a3 | 3049 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
| AnnaBridge | 189:f392fc9709a3 | 3050 | * frequency ranges from 1 to 16 MHz. |
| AnnaBridge | 189:f392fc9709a3 | 3051 | * |
| AnnaBridge | 189:f392fc9709a3 | 3052 | * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock |
| AnnaBridge | 189:f392fc9709a3 | 3053 | * This parameter must be a number between 4 and 512. |
| AnnaBridge | 189:f392fc9709a3 | 3054 | * @note You have to set the PLLN parameter correctly to ensure that the VCO |
| AnnaBridge | 189:f392fc9709a3 | 3055 | * output frequency is between 150 and 420 MHz (when in medium VCO range) or |
| AnnaBridge | 189:f392fc9709a3 | 3056 | * between 192 and 836 MHZ (when in wide VCO range) |
| AnnaBridge | 189:f392fc9709a3 | 3057 | * |
| AnnaBridge | 189:f392fc9709a3 | 3058 | * @param __PLLP1__: specifies the division factor for system clock. |
| AnnaBridge | 189:f392fc9709a3 | 3059 | * This parameter must be a number between 2 and 128 (where odd numbers not allowed) |
| AnnaBridge | 189:f392fc9709a3 | 3060 | * |
| AnnaBridge | 189:f392fc9709a3 | 3061 | * @param __PLLQ1__: specifies the division factor for peripheral kernel clocks |
| AnnaBridge | 189:f392fc9709a3 | 3062 | * This parameter must be a number between 1 and 128 |
| AnnaBridge | 189:f392fc9709a3 | 3063 | * |
| AnnaBridge | 189:f392fc9709a3 | 3064 | * @param __PLLR1__: specifies the division factor for peripheral kernel clocks |
| AnnaBridge | 189:f392fc9709a3 | 3065 | * This parameter must be a number between 1 and 128 |
| AnnaBridge | 189:f392fc9709a3 | 3066 | * |
| AnnaBridge | 189:f392fc9709a3 | 3067 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3068 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3069 | |
| AnnaBridge | 189:f392fc9709a3 | 3070 | |
| AnnaBridge | 189:f392fc9709a3 | 3071 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \ |
| AnnaBridge | 189:f392fc9709a3 | 3072 | do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \ |
| AnnaBridge | 189:f392fc9709a3 | 3073 | WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \ |
| AnnaBridge | 189:f392fc9709a3 | 3074 | ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \ |
| AnnaBridge | 189:f392fc9709a3 | 3075 | } while(0) |
| AnnaBridge | 189:f392fc9709a3 | 3076 | |
| AnnaBridge | 189:f392fc9709a3 | 3077 | |
| AnnaBridge | 189:f392fc9709a3 | 3078 | /** @brief Macro to configure the PLLs clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3079 | * @note This function must be used only when all PLLs are disabled. |
| AnnaBridge | 189:f392fc9709a3 | 3080 | * @param __PLLSOURCE__: specifies the PLLs entry clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3081 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3082 | * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry |
| AnnaBridge | 189:f392fc9709a3 | 3083 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
| AnnaBridge | 189:f392fc9709a3 | 3084 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
| AnnaBridge | 189:f392fc9709a3 | 3085 | * |
| AnnaBridge | 189:f392fc9709a3 | 3086 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3087 | #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__)) |
| AnnaBridge | 189:f392fc9709a3 | 3088 | |
| AnnaBridge | 189:f392fc9709a3 | 3089 | |
| AnnaBridge | 189:f392fc9709a3 | 3090 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3091 | * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor |
| AnnaBridge | 189:f392fc9709a3 | 3092 | * |
| AnnaBridge | 189:f392fc9709a3 | 3093 | * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO |
| AnnaBridge | 189:f392fc9709a3 | 3094 | * |
| AnnaBridge | 189:f392fc9709a3 | 3095 | * @param __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO |
| AnnaBridge | 189:f392fc9709a3 | 3096 | * It should be a value between 0 and 8191 |
| AnnaBridge | 189:f392fc9709a3 | 3097 | * @note Warning: The software has to set correctly these bits to insure that the VCO |
| AnnaBridge | 189:f392fc9709a3 | 3098 | * output frequency is between its valid frequency range, which is: |
| AnnaBridge | 189:f392fc9709a3 | 3099 | * 192 to 836 MHz if PLL1VCOSEL = 0 |
| AnnaBridge | 189:f392fc9709a3 | 3100 | * 150 to 420 MHz if PLL1VCOSEL = 1. |
| AnnaBridge | 189:f392fc9709a3 | 3101 | * |
| AnnaBridge | 189:f392fc9709a3 | 3102 | * |
| AnnaBridge | 189:f392fc9709a3 | 3103 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3104 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3105 | #define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos) |
| AnnaBridge | 189:f392fc9709a3 | 3106 | |
| AnnaBridge | 189:f392fc9709a3 | 3107 | |
| AnnaBridge | 189:f392fc9709a3 | 3108 | /** @brief Macro to select the PLL1 reference frequency range. |
| AnnaBridge | 189:f392fc9709a3 | 3109 | * @param __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range |
| AnnaBridge | 189:f392fc9709a3 | 3110 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3111 | * @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz |
| AnnaBridge | 189:f392fc9709a3 | 3112 | * @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz |
| AnnaBridge | 189:f392fc9709a3 | 3113 | * @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz |
| AnnaBridge | 189:f392fc9709a3 | 3114 | * @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz |
| AnnaBridge | 189:f392fc9709a3 | 3115 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3116 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3117 | #define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \ |
| AnnaBridge | 189:f392fc9709a3 | 3118 | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__)) |
| AnnaBridge | 189:f392fc9709a3 | 3119 | |
| AnnaBridge | 189:f392fc9709a3 | 3120 | |
| AnnaBridge | 189:f392fc9709a3 | 3121 | /** @brief Macro to select the PLL1 reference frequency range. |
| AnnaBridge | 189:f392fc9709a3 | 3122 | * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range |
| AnnaBridge | 189:f392fc9709a3 | 3123 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3124 | * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz |
| AnnaBridge | 189:f392fc9709a3 | 3125 | * @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz |
| AnnaBridge | 189:f392fc9709a3 | 3126 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3127 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3128 | #define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \ |
| AnnaBridge | 189:f392fc9709a3 | 3129 | MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) |
| AnnaBridge | 189:f392fc9709a3 | 3130 | |
| AnnaBridge | 189:f392fc9709a3 | 3131 | |
| AnnaBridge | 189:f392fc9709a3 | 3132 | |
| AnnaBridge | 189:f392fc9709a3 | 3133 | /** @brief Macro to get the clock source used as system clock. |
| AnnaBridge | 189:f392fc9709a3 | 3134 | * @retval The clock source used as system clock. The returned value can be one |
| AnnaBridge | 189:f392fc9709a3 | 3135 | * of the following: |
| AnnaBridge | 189:f392fc9709a3 | 3136 | * - RCC_CFGR_SWS_CSI: CSI used as system clock. |
| AnnaBridge | 189:f392fc9709a3 | 3137 | * - RCC_CFGR_SWS_HSI: HSI used as system clock. |
| AnnaBridge | 189:f392fc9709a3 | 3138 | * - RCC_CFGR_SWS_HSE: HSE used as system clock. |
| AnnaBridge | 189:f392fc9709a3 | 3139 | * - RCC_CFGR_SWS_PLL: PLL used as system clock. |
| AnnaBridge | 189:f392fc9709a3 | 3140 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3141 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) |
| AnnaBridge | 189:f392fc9709a3 | 3142 | |
| AnnaBridge | 189:f392fc9709a3 | 3143 | |
| AnnaBridge | 189:f392fc9709a3 | 3144 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3145 | * @brief Macro to configure the system clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3146 | * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3147 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3148 | * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3149 | * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3150 | * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3151 | * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3152 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3153 | #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) |
| AnnaBridge | 189:f392fc9709a3 | 3154 | |
| AnnaBridge | 189:f392fc9709a3 | 3155 | /** @brief Macro to get the oscillator used as PLL clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3156 | * @retval The oscillator used as PLL clock source. The returned value can be one |
| AnnaBridge | 189:f392fc9709a3 | 3157 | * of the following: |
| AnnaBridge | 189:f392fc9709a3 | 3158 | * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3159 | * - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3160 | * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3161 | * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3162 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3163 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC)) |
| AnnaBridge | 189:f392fc9709a3 | 3164 | |
| AnnaBridge | 189:f392fc9709a3 | 3165 | /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config |
| AnnaBridge | 189:f392fc9709a3 | 3166 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3167 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3168 | |
| AnnaBridge | 189:f392fc9709a3 | 3169 | /** @brief Macro to configure the MCO1 clock. |
| AnnaBridge | 189:f392fc9709a3 | 3170 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3171 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3172 | * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source |
| AnnaBridge | 189:f392fc9709a3 | 3173 | * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source |
| AnnaBridge | 189:f392fc9709a3 | 3174 | * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source |
| AnnaBridge | 189:f392fc9709a3 | 3175 | * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source |
| AnnaBridge | 189:f392fc9709a3 | 3176 | * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source |
| AnnaBridge | 189:f392fc9709a3 | 3177 | * @param __MCODIV__ specifies the MCO clock prescaler. |
| AnnaBridge | 189:f392fc9709a3 | 3178 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3179 | * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock |
| AnnaBridge | 189:f392fc9709a3 | 3180 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3181 | #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
| AnnaBridge | 189:f392fc9709a3 | 3182 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) |
| AnnaBridge | 189:f392fc9709a3 | 3183 | |
| AnnaBridge | 189:f392fc9709a3 | 3184 | /** @brief Macro to configure the MCO2 clock. |
| AnnaBridge | 189:f392fc9709a3 | 3185 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
| AnnaBridge | 189:f392fc9709a3 | 3186 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3187 | * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source |
| AnnaBridge | 189:f392fc9709a3 | 3188 | * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source |
| AnnaBridge | 189:f392fc9709a3 | 3189 | * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source |
| AnnaBridge | 189:f392fc9709a3 | 3190 | * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source |
| AnnaBridge | 189:f392fc9709a3 | 3191 | * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source |
| AnnaBridge | 189:f392fc9709a3 | 3192 | * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source |
| AnnaBridge | 189:f392fc9709a3 | 3193 | * @param __MCODIV__ specifies the MCO clock prescaler. |
| AnnaBridge | 189:f392fc9709a3 | 3194 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3195 | * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock |
| AnnaBridge | 189:f392fc9709a3 | 3196 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3197 | #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
| AnnaBridge | 189:f392fc9709a3 | 3198 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); |
| AnnaBridge | 189:f392fc9709a3 | 3199 | |
| AnnaBridge | 189:f392fc9709a3 | 3200 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3201 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3202 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3203 | |
| AnnaBridge | 189:f392fc9709a3 | 3204 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3205 | * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. |
| AnnaBridge | 189:f392fc9709a3 | 3206 | * @note As the LSE is in the Backup domain and write access is denied to |
| AnnaBridge | 189:f392fc9709a3 | 3207 | * this domain after reset, you have to enable write access using |
| AnnaBridge | 189:f392fc9709a3 | 3208 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
| AnnaBridge | 189:f392fc9709a3 | 3209 | * (to be done once after reset). |
| AnnaBridge | 189:f392fc9709a3 | 3210 | * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. |
| AnnaBridge | 189:f392fc9709a3 | 3211 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3212 | * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. |
| AnnaBridge | 189:f392fc9709a3 | 3213 | * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. |
| AnnaBridge | 189:f392fc9709a3 | 3214 | * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. |
| AnnaBridge | 189:f392fc9709a3 | 3215 | * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. |
| AnnaBridge | 189:f392fc9709a3 | 3216 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3217 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3218 | #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ |
| AnnaBridge | 189:f392fc9709a3 | 3219 | MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) |
| AnnaBridge | 189:f392fc9709a3 | 3220 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3221 | * @brief Macro to configure the wake up from stop clock. |
| AnnaBridge | 189:f392fc9709a3 | 3222 | * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop |
| AnnaBridge | 189:f392fc9709a3 | 3223 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3224 | * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source |
| AnnaBridge | 189:f392fc9709a3 | 3225 | * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source |
| AnnaBridge | 189:f392fc9709a3 | 3226 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3227 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3228 | #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \ |
| AnnaBridge | 189:f392fc9709a3 | 3229 | MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__)) |
| AnnaBridge | 189:f392fc9709a3 | 3230 | |
| AnnaBridge | 189:f392fc9709a3 | 3231 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3232 | * @brief Macro to configure the Kernel wake up from stop clock. |
| AnnaBridge | 189:f392fc9709a3 | 3233 | * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop |
| AnnaBridge | 189:f392fc9709a3 | 3234 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3235 | * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source |
| AnnaBridge | 189:f392fc9709a3 | 3236 | * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source |
| AnnaBridge | 189:f392fc9709a3 | 3237 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 3238 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3239 | #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ |
| AnnaBridge | 189:f392fc9709a3 | 3240 | MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) |
| AnnaBridge | 189:f392fc9709a3 | 3241 | |
| AnnaBridge | 189:f392fc9709a3 | 3242 | /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management |
| AnnaBridge | 189:f392fc9709a3 | 3243 | * @brief macros to manage the specified RCC Flags and interrupts. |
| AnnaBridge | 189:f392fc9709a3 | 3244 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3245 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3246 | /** @brief Enable RCC interrupt. |
| AnnaBridge | 189:f392fc9709a3 | 3247 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. |
| AnnaBridge | 189:f392fc9709a3 | 3248 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3249 | * @arg RCC_IT_LSIRDY: LSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3250 | * @arg RCC_IT_LSERDY: LSE ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3251 | * @arg RCC_IT_CSIRDY: HSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3252 | * @arg RCC_IT_HSIRDY: HSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3253 | * @arg RCC_IT_HSERDY: HSE ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3254 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3255 | * @arg RCC_IT_PLLRDY: main PLL ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3256 | * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3257 | * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3258 | * @arg RCC_IT_LSECSS: Clock security system interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3259 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3260 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 3261 | |
| AnnaBridge | 189:f392fc9709a3 | 3262 | /** @brief Disable RCC interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3263 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. |
| AnnaBridge | 189:f392fc9709a3 | 3264 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3265 | * @arg RCC_IT_LSIRDY: LSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3266 | * @arg RCC_IT_LSERDY: LSE ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3267 | * @arg RCC_IT_CSIRDY: HSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3268 | * @arg RCC_IT_HSIRDY: HSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3269 | * @arg RCC_IT_HSERDY: HSE ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3270 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3271 | * @arg RCC_IT_PLLRDY: main PLL ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3272 | * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3273 | * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3274 | * @arg RCC_IT_LSECSS: Clock security system interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3275 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3276 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 3277 | |
| AnnaBridge | 189:f392fc9709a3 | 3278 | /** @brief Clear the RCC's interrupt pending bits |
| AnnaBridge | 189:f392fc9709a3 | 3279 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
| AnnaBridge | 189:f392fc9709a3 | 3280 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3281 | * @arg RCC_IT_LSIRDY: LSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3282 | * @arg RCC_IT_LSERDY: LSE ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3283 | * @arg RCC_IT_CSIRDY: CSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3284 | * @arg RCC_IT_HSIRDY: HSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3285 | * @arg RCC_IT_HSERDY: HSE ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3286 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3287 | * @arg RCC_IT_PLLRDY: main PLL ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3288 | * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3289 | * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3290 | * @arg RCC_IT_HSECSS: HSE Clock Security interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3291 | * @arg RCC_IT_LSECSS: Clock security system interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3292 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3293 | #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 3294 | |
| AnnaBridge | 189:f392fc9709a3 | 3295 | /** @brief Check the RCC's interrupt has occurred or not. |
| AnnaBridge | 189:f392fc9709a3 | 3296 | * @param __INTERRUPT__: specifies the RCC interrupt source to check. |
| AnnaBridge | 189:f392fc9709a3 | 3297 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3298 | * @arg RCC_IT_LSIRDY: LSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3299 | * @arg RCC_IT_LSERDY: LSE ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3300 | * @arg RCC_IT_CSIRDY: CSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3301 | * @arg RCC_IT_HSIRDY: HSI ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3302 | * @arg RCC_IT_HSERDY: HSE ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3303 | * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3304 | * @arg RCC_IT_PLLRDY: main PLL ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3305 | * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3306 | * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3307 | * @arg RCC_IT_HSECSS: HSE Clock Security interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3308 | * @arg RCC_IT_LSECSS: Clock security system interrupt |
| AnnaBridge | 189:f392fc9709a3 | 3309 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 3310 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3311 | #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) |
| AnnaBridge | 189:f392fc9709a3 | 3312 | |
| AnnaBridge | 189:f392fc9709a3 | 3313 | /** @brief Set RMVF bit to clear the reset flags. |
| AnnaBridge | 189:f392fc9709a3 | 3314 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3315 | #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) |
| AnnaBridge | 189:f392fc9709a3 | 3316 | |
| AnnaBridge | 189:f392fc9709a3 | 3317 | |
| AnnaBridge | 189:f392fc9709a3 | 3318 | /** @brief Check RCC flag is set or not. |
| AnnaBridge | 189:f392fc9709a3 | 3319 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 189:f392fc9709a3 | 3320 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 3321 | * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3322 | * @arg RCC_FLAG_HSIDIV: HSI divider flag |
| AnnaBridge | 189:f392fc9709a3 | 3323 | * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3324 | * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3325 | * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3326 | * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3327 | * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3328 | * @arg RCC_FLAG_PLLRDY: PLL1 clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3329 | * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3330 | * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3331 | * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3332 | * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready |
| AnnaBridge | 189:f392fc9709a3 | 3333 | * @arg RCC_FLAG_CPURST: CPU reset flag |
| AnnaBridge | 189:f392fc9709a3 | 3334 | * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag |
| AnnaBridge | 189:f392fc9709a3 | 3335 | * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag |
| AnnaBridge | 189:f392fc9709a3 | 3336 | * @arg RCC_FLAG_BORRST: BOR reset flag |
| AnnaBridge | 189:f392fc9709a3 | 3337 | * @arg RCC_FLAG_PINRST: Pin reset |
| AnnaBridge | 189:f392fc9709a3 | 3338 | * @arg RCC_FLAG_PORRST: POR/PDR reset |
| AnnaBridge | 189:f392fc9709a3 | 3339 | * @arg RCC_FLAG_SFTRST: System reset from CPU reset flag |
| AnnaBridge | 189:f392fc9709a3 | 3340 | * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag |
| AnnaBridge | 189:f392fc9709a3 | 3341 | * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset |
| AnnaBridge | 189:f392fc9709a3 | 3342 | * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset |
| AnnaBridge | 189:f392fc9709a3 | 3343 | * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag |
| AnnaBridge | 189:f392fc9709a3 | 3344 | * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag |
| AnnaBridge | 189:f392fc9709a3 | 3345 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 189:f392fc9709a3 | 3346 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3347 | #define RCC_FLAG_MASK ((uint8_t)0x1F) |
| AnnaBridge | 189:f392fc9709a3 | 3348 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ |
| AnnaBridge | 189:f392fc9709a3 | 3349 | ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) |
| AnnaBridge | 189:f392fc9709a3 | 3350 | |
| AnnaBridge | 189:f392fc9709a3 | 3351 | |
| AnnaBridge | 189:f392fc9709a3 | 3352 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3353 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3354 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3355 | |
| AnnaBridge | 189:f392fc9709a3 | 3356 | #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos) |
| AnnaBridge | 189:f392fc9709a3 | 3357 | |
| AnnaBridge | 189:f392fc9709a3 | 3358 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3359 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3360 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3361 | |
| AnnaBridge | 189:f392fc9709a3 | 3362 | /* Include RCC HAL Extension module */ |
| AnnaBridge | 189:f392fc9709a3 | 3363 | #include "stm32h7xx_hal_rcc_ex.h" |
| AnnaBridge | 189:f392fc9709a3 | 3364 | |
| AnnaBridge | 189:f392fc9709a3 | 3365 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 3366 | /** @addtogroup RCC_Exported_Functions |
| AnnaBridge | 189:f392fc9709a3 | 3367 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3368 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3369 | |
| AnnaBridge | 189:f392fc9709a3 | 3370 | /** @addtogroup RCC_Exported_Functions_Group1 |
| AnnaBridge | 189:f392fc9709a3 | 3371 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3372 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3373 | /* Initialization and de-initialization functions ******************************/ |
| AnnaBridge | 189:f392fc9709a3 | 3374 | HAL_StatusTypeDef HAL_RCC_DeInit(void); |
| AnnaBridge | 189:f392fc9709a3 | 3375 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 3376 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
| AnnaBridge | 189:f392fc9709a3 | 3377 | |
| AnnaBridge | 189:f392fc9709a3 | 3378 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3379 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3380 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3381 | |
| AnnaBridge | 189:f392fc9709a3 | 3382 | /** @addtogroup RCC_Exported_Functions_Group2 |
| AnnaBridge | 189:f392fc9709a3 | 3383 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3384 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3385 | /* Peripheral Control functions ************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 3386 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
| AnnaBridge | 189:f392fc9709a3 | 3387 | void HAL_RCC_EnableCSS(void); |
| AnnaBridge | 189:f392fc9709a3 | 3388 | void HAL_RCC_DisableCSS(void); |
| AnnaBridge | 189:f392fc9709a3 | 3389 | uint32_t HAL_RCC_GetSysClockFreq(void); |
| AnnaBridge | 189:f392fc9709a3 | 3390 | uint32_t HAL_RCC_GetHCLKFreq(void); |
| AnnaBridge | 189:f392fc9709a3 | 3391 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
| AnnaBridge | 189:f392fc9709a3 | 3392 | uint32_t HAL_RCC_GetPCLK2Freq(void); |
| AnnaBridge | 189:f392fc9709a3 | 3393 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
| AnnaBridge | 189:f392fc9709a3 | 3394 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
| AnnaBridge | 189:f392fc9709a3 | 3395 | /* CSS NMI IRQ handler */ |
| AnnaBridge | 189:f392fc9709a3 | 3396 | void HAL_RCC_NMI_IRQHandler(void); |
| AnnaBridge | 189:f392fc9709a3 | 3397 | /* User Callbacks in non blocking mode (IT mode) */ |
| AnnaBridge | 189:f392fc9709a3 | 3398 | void HAL_RCC_CCSCallback(void); |
| AnnaBridge | 189:f392fc9709a3 | 3399 | |
| AnnaBridge | 189:f392fc9709a3 | 3400 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3401 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3402 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3403 | |
| AnnaBridge | 189:f392fc9709a3 | 3404 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3405 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3406 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3407 | |
| AnnaBridge | 189:f392fc9709a3 | 3408 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 3409 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 3410 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 3411 | /** @defgroup RCC_Private_Constants RCC Private Constants |
| AnnaBridge | 189:f392fc9709a3 | 3412 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3413 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3414 | |
| AnnaBridge | 189:f392fc9709a3 | 3415 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
| AnnaBridge | 189:f392fc9709a3 | 3416 | #define HSI_TIMEOUT_VALUE (2U) /* 2 ms */ |
| AnnaBridge | 189:f392fc9709a3 | 3417 | #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */ |
| AnnaBridge | 189:f392fc9709a3 | 3418 | #define CSI_TIMEOUT_VALUE (2U) /* 2 ms */ |
| AnnaBridge | 189:f392fc9709a3 | 3419 | #define LSI_TIMEOUT_VALUE (2U) /* 2 ms */ |
| AnnaBridge | 189:f392fc9709a3 | 3420 | #define PLL_TIMEOUT_VALUE (2U) /* 2 ms */ |
| AnnaBridge | 189:f392fc9709a3 | 3421 | #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ |
| AnnaBridge | 189:f392fc9709a3 | 3422 | #define RCC_DBP_TIMEOUT_VALUE (100U) |
| AnnaBridge | 189:f392fc9709a3 | 3423 | #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
| AnnaBridge | 189:f392fc9709a3 | 3424 | |
| AnnaBridge | 189:f392fc9709a3 | 3425 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3426 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3427 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3428 | |
| AnnaBridge | 189:f392fc9709a3 | 3429 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 3430 | /** @addtogroup RCC_Private_Macros RCC Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 3431 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3432 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3433 | |
| AnnaBridge | 189:f392fc9709a3 | 3434 | /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters |
| AnnaBridge | 189:f392fc9709a3 | 3435 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 3436 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3437 | |
| AnnaBridge | 189:f392fc9709a3 | 3438 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3439 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3440 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3441 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3442 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3443 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3444 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) |
| AnnaBridge | 189:f392fc9709a3 | 3445 | |
| AnnaBridge | 189:f392fc9709a3 | 3446 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3447 | ((HSE) == RCC_HSE_BYPASS)) |
| AnnaBridge | 189:f392fc9709a3 | 3448 | |
| AnnaBridge | 189:f392fc9709a3 | 3449 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3450 | ((LSE) == RCC_LSE_BYPASS)) |
| AnnaBridge | 189:f392fc9709a3 | 3451 | |
| AnnaBridge | 189:f392fc9709a3 | 3452 | #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3453 | ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3454 | ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8)) |
| AnnaBridge | 189:f392fc9709a3 | 3455 | |
| AnnaBridge | 189:f392fc9709a3 | 3456 | #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) |
| AnnaBridge | 189:f392fc9709a3 | 3457 | |
| AnnaBridge | 189:f392fc9709a3 | 3458 | #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) |
| AnnaBridge | 189:f392fc9709a3 | 3459 | |
| AnnaBridge | 189:f392fc9709a3 | 3460 | #define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON)) |
| AnnaBridge | 189:f392fc9709a3 | 3461 | |
| AnnaBridge | 189:f392fc9709a3 | 3462 | #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3463 | ((PLL) == RCC_PLL_ON)) |
| AnnaBridge | 189:f392fc9709a3 | 3464 | |
| AnnaBridge | 189:f392fc9709a3 | 3465 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3466 | ((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3467 | ((SOURCE) == RCC_PLLSOURCE_NONE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3468 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
| AnnaBridge | 189:f392fc9709a3 | 3469 | #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) |
| AnnaBridge | 189:f392fc9709a3 | 3470 | #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) |
| AnnaBridge | 189:f392fc9709a3 | 3471 | #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) |
| AnnaBridge | 189:f392fc9709a3 | 3472 | #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) |
| AnnaBridge | 189:f392fc9709a3 | 3473 | #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) |
| AnnaBridge | 189:f392fc9709a3 | 3474 | |
| AnnaBridge | 189:f392fc9709a3 | 3475 | #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3476 | ((VALUE) == RCC_PLL1_DIVQ) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3477 | ((VALUE) == RCC_PLL1_DIVR)) |
| AnnaBridge | 189:f392fc9709a3 | 3478 | |
| AnnaBridge | 189:f392fc9709a3 | 3479 | #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU)) |
| AnnaBridge | 189:f392fc9709a3 | 3480 | |
| AnnaBridge | 189:f392fc9709a3 | 3481 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3482 | ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3483 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3484 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) |
| AnnaBridge | 189:f392fc9709a3 | 3485 | |
| AnnaBridge | 189:f392fc9709a3 | 3486 | #define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3487 | ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3488 | ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3489 | ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3490 | ((SYSCLK) == RCC_SYSCLK_DIV512)) |
| AnnaBridge | 189:f392fc9709a3 | 3491 | |
| AnnaBridge | 189:f392fc9709a3 | 3492 | |
| AnnaBridge | 189:f392fc9709a3 | 3493 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3494 | ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3495 | ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3496 | ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3497 | ((HCLK) == RCC_HCLK_DIV512)) |
| AnnaBridge | 189:f392fc9709a3 | 3498 | |
| AnnaBridge | 189:f392fc9709a3 | 3499 | #define IS_RCC_D1PCLK1(D1PCLK1) (((D1PCLK1) == RCC_APB3_DIV1) || ((D1PCLK1) == RCC_APB3_DIV2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3500 | ((D1PCLK1) == RCC_APB3_DIV4) || ((D1PCLK1) == RCC_APB3_DIV8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3501 | ((D1PCLK1) == RCC_APB3_DIV16)) |
| AnnaBridge | 189:f392fc9709a3 | 3502 | |
| AnnaBridge | 189:f392fc9709a3 | 3503 | #define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3504 | ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3505 | ((PCLK1) == RCC_APB1_DIV16)) |
| AnnaBridge | 189:f392fc9709a3 | 3506 | |
| AnnaBridge | 189:f392fc9709a3 | 3507 | #define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3508 | ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3509 | ((PCLK2) == RCC_APB2_DIV16)) |
| AnnaBridge | 189:f392fc9709a3 | 3510 | |
| AnnaBridge | 189:f392fc9709a3 | 3511 | #define IS_RCC_D3PCLK1(D3PCLK1) (((D3PCLK1) == RCC_APB4_DIV1) || ((D3PCLK1) == RCC_APB4_DIV2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3512 | ((D3PCLK1) == RCC_APB4_DIV4) || ((D3PCLK1) == RCC_APB4_DIV8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3513 | ((D3PCLK1) == RCC_APB4_DIV16)) |
| AnnaBridge | 189:f392fc9709a3 | 3514 | |
| AnnaBridge | 189:f392fc9709a3 | 3515 | #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3516 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3517 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3518 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3519 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3520 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3521 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3522 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3523 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3524 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3525 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3526 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3527 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3528 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3529 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3530 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3531 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3532 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3533 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3534 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3535 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3536 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3537 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3538 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3539 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3540 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3541 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3542 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3543 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3544 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3545 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3546 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63)) |
| AnnaBridge | 189:f392fc9709a3 | 3547 | |
| AnnaBridge | 189:f392fc9709a3 | 3548 | #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) |
| AnnaBridge | 189:f392fc9709a3 | 3549 | |
| AnnaBridge | 189:f392fc9709a3 | 3550 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3551 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3552 | ((SOURCE) == RCC_MCO1SOURCE_HSI48)) |
| AnnaBridge | 189:f392fc9709a3 | 3553 | |
| AnnaBridge | 189:f392fc9709a3 | 3554 | #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3555 | ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3556 | ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK)) |
| AnnaBridge | 189:f392fc9709a3 | 3557 | |
| AnnaBridge | 189:f392fc9709a3 | 3558 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3559 | ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3560 | ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3561 | ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3562 | ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3563 | ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3564 | ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3565 | ((DIV) == RCC_MCODIV_15)) |
| AnnaBridge | 189:f392fc9709a3 | 3566 | |
| AnnaBridge | 189:f392fc9709a3 | 3567 | |
| AnnaBridge | 189:f392fc9709a3 | 3568 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3569 | ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3570 | ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3571 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3572 | ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3573 | ((FLAG) == RCC_FLAG_LSIRDY) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3574 | ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3575 | ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3576 | ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3577 | ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ |
| AnnaBridge | 189:f392fc9709a3 | 3578 | ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ |
| AnnaBridge | 189:f392fc9709a3 | 3579 | ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) |
| AnnaBridge | 189:f392fc9709a3 | 3580 | |
| AnnaBridge | 189:f392fc9709a3 | 3581 | |
| AnnaBridge | 189:f392fc9709a3 | 3582 | #define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU) |
| AnnaBridge | 189:f392fc9709a3 | 3583 | #define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) |
| AnnaBridge | 189:f392fc9709a3 | 3584 | |
| AnnaBridge | 189:f392fc9709a3 | 3585 | #define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3586 | ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI)) |
| AnnaBridge | 189:f392fc9709a3 | 3587 | |
| AnnaBridge | 189:f392fc9709a3 | 3588 | #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ |
| AnnaBridge | 189:f392fc9709a3 | 3589 | ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) |
| AnnaBridge | 189:f392fc9709a3 | 3590 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3591 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3592 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3593 | |
| AnnaBridge | 189:f392fc9709a3 | 3594 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3595 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3596 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3597 | |
| AnnaBridge | 189:f392fc9709a3 | 3598 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3599 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3600 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3601 | |
| AnnaBridge | 189:f392fc9709a3 | 3602 | /** |
| AnnaBridge | 189:f392fc9709a3 | 3603 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 3604 | */ |
| AnnaBridge | 189:f392fc9709a3 | 3605 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 3606 | } |
| AnnaBridge | 189:f392fc9709a3 | 3607 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 3608 | |
| AnnaBridge | 189:f392fc9709a3 | 3609 | #endif /* STM32H7xx_HAL_RCC_H */ |
| AnnaBridge | 189:f392fc9709a3 | 3610 | |
| AnnaBridge | 189:f392fc9709a3 | 3611 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
