mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_qspi.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32h7xx_hal_qspi.c
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief QSPI HAL module driver.
AnnaBridge	189:f392fc9709a3	6	* This file provides firmware functions to manage the following
AnnaBridge	189:f392fc9709a3	7	* functionalities of the QuadSPI interface (QSPI).
AnnaBridge	189:f392fc9709a3	8	* + Initialization and de-initialization functions
AnnaBridge	189:f392fc9709a3	9	* + Indirect functional mode management
AnnaBridge	189:f392fc9709a3	10	* + Memory-mapped functional mode management
AnnaBridge	189:f392fc9709a3	11	* + Auto-polling functional mode management
AnnaBridge	189:f392fc9709a3	12	* + Interrupts and flags management
AnnaBridge	189:f392fc9709a3	13	* + MDMA channel configuration for indirect functional mode
AnnaBridge	189:f392fc9709a3	14	* + Errors management and abort functionality
AnnaBridge	189:f392fc9709a3	15	*
AnnaBridge	189:f392fc9709a3	16	*
AnnaBridge	189:f392fc9709a3	17	@verbatim
AnnaBridge	189:f392fc9709a3	18	===============================================================================
AnnaBridge	189:f392fc9709a3	19	##### How to use this driver #####
AnnaBridge	189:f392fc9709a3	20	===============================================================================
AnnaBridge	189:f392fc9709a3	21	[..]
AnnaBridge	189:f392fc9709a3	22	* Initialization *
AnnaBridge	189:f392fc9709a3	23	======================
AnnaBridge	189:f392fc9709a3	24	[..]
AnnaBridge	189:f392fc9709a3	25	(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
AnnaBridge	189:f392fc9709a3	26	(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
AnnaBridge	189:f392fc9709a3	27	(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
AnnaBridge	189:f392fc9709a3	28	(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
AnnaBridge	189:f392fc9709a3	29	(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
AnnaBridge	189:f392fc9709a3	30	(++) If interrupt mode is used, enable and configure QuadSPI global
AnnaBridge	189:f392fc9709a3	31	interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
AnnaBridge	189:f392fc9709a3	32	(++) If DMA mode is used, enable the clocks for the QuadSPI MDMA
AnnaBridge	189:f392fc9709a3	33	with __HAL_RCC_MDMA_CLK_ENABLE(), configure MDMA with HAL_MDMA_Init(),
AnnaBridge	189:f392fc9709a3	34	link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
AnnaBridge	189:f392fc9709a3	35	MDMA global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
AnnaBridge	189:f392fc9709a3	36	(#) Configure the flash size, the clock prescaler, the fifo threshold, the
AnnaBridge	189:f392fc9709a3	37	clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
AnnaBridge	189:f392fc9709a3	38
AnnaBridge	189:f392fc9709a3	39	* Indirect functional mode *
AnnaBridge	189:f392fc9709a3	40	================================
AnnaBridge	189:f392fc9709a3	41	[..]
AnnaBridge	189:f392fc9709a3	42	(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
AnnaBridge	189:f392fc9709a3	43	functions :
AnnaBridge	189:f392fc9709a3	44	(++) Instruction phase : the mode used and if present the instruction opcode.
AnnaBridge	189:f392fc9709a3	45	(++) Address phase : the mode used and if present the size and the address value.
AnnaBridge	189:f392fc9709a3	46	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
AnnaBridge	189:f392fc9709a3	47	bytes values.
AnnaBridge	189:f392fc9709a3	48	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
AnnaBridge	189:f392fc9709a3	49	(++) Data phase : the mode used and if present the number of bytes.
AnnaBridge	189:f392fc9709a3	50	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
AnnaBridge	189:f392fc9709a3	51	if activated.
AnnaBridge	189:f392fc9709a3	52	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
AnnaBridge	189:f392fc9709a3	53	(#) If no data is required for the command, it is sent directly to the memory :
AnnaBridge	189:f392fc9709a3	54	(++) In polling mode, the output of the function is done when the transfer is complete.
AnnaBridge	189:f392fc9709a3	55	(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
AnnaBridge	189:f392fc9709a3	56	(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
AnnaBridge	189:f392fc9709a3	57	HAL_QSPI_Transmit_IT() after the command configuration :
AnnaBridge	189:f392fc9709a3	58	(++) In polling mode, the output of the function is done when the transfer is complete.
AnnaBridge	189:f392fc9709a3	59	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
AnnaBridge	189:f392fc9709a3	60	is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
AnnaBridge	189:f392fc9709a3	61	(++) In DMA mode,HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
AnnaBridge	189:f392fc9709a3	62	(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
AnnaBridge	189:f392fc9709a3	63	HAL_QSPI_Receive_IT() after the command configuration :
AnnaBridge	189:f392fc9709a3	64	(++) In polling mode, the output of the function is done when the transfer is complete.
AnnaBridge	189:f392fc9709a3	65	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
AnnaBridge	189:f392fc9709a3	66	is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
AnnaBridge	189:f392fc9709a3	67	(++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
AnnaBridge	189:f392fc9709a3	68
AnnaBridge	189:f392fc9709a3	69	* Auto-polling functional mode *
AnnaBridge	189:f392fc9709a3	70	====================================
AnnaBridge	189:f392fc9709a3	71	[..]
AnnaBridge	189:f392fc9709a3	72	(#) Configure the command sequence and the auto-polling functional mode using the
AnnaBridge	189:f392fc9709a3	73	HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
AnnaBridge	189:f392fc9709a3	74	(++) Instruction phase : the mode used and if present the instruction opcode.
AnnaBridge	189:f392fc9709a3	75	(++) Address phase : the mode used and if present the size and the address value.
AnnaBridge	189:f392fc9709a3	76	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
AnnaBridge	189:f392fc9709a3	77	bytes values.
AnnaBridge	189:f392fc9709a3	78	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
AnnaBridge	189:f392fc9709a3	79	(++) Data phase : the mode used.
AnnaBridge	189:f392fc9709a3	80	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
AnnaBridge	189:f392fc9709a3	81	if activated.
AnnaBridge	189:f392fc9709a3	82	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
AnnaBridge	189:f392fc9709a3	83	(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
AnnaBridge	189:f392fc9709a3	84	the polling interval and the automatic stop activation.
AnnaBridge	189:f392fc9709a3	85	(#) After the configuration :
AnnaBridge	189:f392fc9709a3	86	(++) In polling mode, the output of the function is done when the status match is reached. The
AnnaBridge	189:f392fc9709a3	87	automatic stop is activated to avoid an infinite loop.
AnnaBridge	189:f392fc9709a3	88	(++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
AnnaBridge	189:f392fc9709a3	89
AnnaBridge	189:f392fc9709a3	90	* MDMA functional mode *
AnnaBridge	189:f392fc9709a3	91	====================================
AnnaBridge	189:f392fc9709a3	92	[..]
AnnaBridge	189:f392fc9709a3	93	(#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_QSPI_MspInit() function :
AnnaBridge	189:f392fc9709a3	94	(++) MDMA settings for write operation :
AnnaBridge	189:f392fc9709a3	95	(+) The DestinationInc should be MDMA_DEST_INC_DISABLE
AnnaBridge	189:f392fc9709a3	96	(+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
AnnaBridge	189:f392fc9709a3	97	(+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
AnnaBridge	189:f392fc9709a3	98	aligned with @ref MDMA_Source_increment_mode .
AnnaBridge	189:f392fc9709a3	99	(+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
AnnaBridge	189:f392fc9709a3	100	(++) MDMA settings for read operation :
AnnaBridge	189:f392fc9709a3	101	(+) The SourceInc should be MDMA_SRC_INC_DISABLE
AnnaBridge	189:f392fc9709a3	102	(+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
AnnaBridge	189:f392fc9709a3	103	(+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
AnnaBridge	189:f392fc9709a3	104	(+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
AnnaBridge	189:f392fc9709a3	105	aligned with @ref MDMA_Destination_increment_mode.
AnnaBridge	189:f392fc9709a3	106	(++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi.
AnnaBridge	189:f392fc9709a3	107	(#)In case of wrong MDMA setting
AnnaBridge	189:f392fc9709a3	108	(++) For write operation :
AnnaBridge	189:f392fc9709a3	109	(+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_QSPI_Transmit_DMA().
AnnaBridge	189:f392fc9709a3	110	(++) For read operation :
AnnaBridge	189:f392fc9709a3	111	(+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_QSPI_Receive_DMA().
AnnaBridge	189:f392fc9709a3	112
AnnaBridge	189:f392fc9709a3	113	* Memory-mapped functional mode *
AnnaBridge	189:f392fc9709a3	114	=====================================
AnnaBridge	189:f392fc9709a3	115	[..]
AnnaBridge	189:f392fc9709a3	116	(#) Configure the command sequence and the memory-mapped functional mode using the
AnnaBridge	189:f392fc9709a3	117	HAL_QSPI_MemoryMapped() functions :
AnnaBridge	189:f392fc9709a3	118	(++) Instruction phase : the mode used and if present the instruction opcode.
AnnaBridge	189:f392fc9709a3	119	(++) Address phase : the mode used and the size.
AnnaBridge	189:f392fc9709a3	120	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
AnnaBridge	189:f392fc9709a3	121	bytes values.
AnnaBridge	189:f392fc9709a3	122	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
AnnaBridge	189:f392fc9709a3	123	(++) Data phase : the mode used.
AnnaBridge	189:f392fc9709a3	124	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
AnnaBridge	189:f392fc9709a3	125	if activated.
AnnaBridge	189:f392fc9709a3	126	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
AnnaBridge	189:f392fc9709a3	127	(++) The timeout activation and the timeout period.
AnnaBridge	189:f392fc9709a3	128	(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
AnnaBridge	189:f392fc9709a3	129	the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
AnnaBridge	189:f392fc9709a3	130
AnnaBridge	189:f392fc9709a3	131	* Errors management and abort functionality *
AnnaBridge	189:f392fc9709a3	132	=================================================
AnnaBridge	189:f392fc9709a3	133	[..]
AnnaBridge	189:f392fc9709a3	134	(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
AnnaBridge	189:f392fc9709a3	135	(#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
AnnaBridge	189:f392fc9709a3	136	flushes the fifo :
AnnaBridge	189:f392fc9709a3	137	(++) In polling mode, the output of the function is done when the transfer
AnnaBridge	189:f392fc9709a3	138	complete bit is set and the busy bit cleared.
AnnaBridge	189:f392fc9709a3	139	(++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
AnnaBridge	189:f392fc9709a3	140	the transfer complete bi is set.
AnnaBridge	189:f392fc9709a3	141
AnnaBridge	189:f392fc9709a3	142	* Control functions *
AnnaBridge	189:f392fc9709a3	143	=========================
AnnaBridge	189:f392fc9709a3	144	[..]
AnnaBridge	189:f392fc9709a3	145	(#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
AnnaBridge	189:f392fc9709a3	146	(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
AnnaBridge	189:f392fc9709a3	147	(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
AnnaBridge	189:f392fc9709a3	148	(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
AnnaBridge	189:f392fc9709a3	149
AnnaBridge	189:f392fc9709a3	150	* Callback registration *
AnnaBridge	189:f392fc9709a3	151	=============================================
AnnaBridge	189:f392fc9709a3	152	[..]
AnnaBridge	189:f392fc9709a3	153	The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
AnnaBridge	189:f392fc9709a3	154	allows the user to configure dynamically the driver callbacks.
AnnaBridge	189:f392fc9709a3	155
AnnaBridge	189:f392fc9709a3	156	Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
AnnaBridge	189:f392fc9709a3	157	it allows to register following callbacks:
AnnaBridge	189:f392fc9709a3	158	(+) ErrorCallback : callback when error occurs.
AnnaBridge	189:f392fc9709a3	159	(+) AbortCpltCallback : callback when abort is completed.
AnnaBridge	189:f392fc9709a3	160	(+) FifoThresholdCallback : callback when the fifo threshold is reached.
AnnaBridge	189:f392fc9709a3	161	(+) CmdCpltCallback : callback when a command without data is completed.
AnnaBridge	189:f392fc9709a3	162	(+) RxCpltCallback : callback when a reception transfer is completed.
AnnaBridge	189:f392fc9709a3	163	(+) TxCpltCallback : callback when a transmission transfer is completed.
AnnaBridge	189:f392fc9709a3	164	(+) StatusMatchCallback : callback when a status match occurs.
AnnaBridge	189:f392fc9709a3	165	(+) TimeOutCallback : callback when the timeout perioed expires.
AnnaBridge	189:f392fc9709a3	166	(+) MspInitCallback : QSPI MspInit.
AnnaBridge	189:f392fc9709a3	167	(+) MspDeInitCallback : QSPI MspDeInit.
AnnaBridge	189:f392fc9709a3	168	This function takes as parameters the HAL peripheral handle, the Callback ID
AnnaBridge	189:f392fc9709a3	169	and a pointer to the user callback function.
AnnaBridge	189:f392fc9709a3	170
AnnaBridge	189:f392fc9709a3	171	Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
AnnaBridge	189:f392fc9709a3	172	weak (surcharged) function. It allows to reset following callbacks:
AnnaBridge	189:f392fc9709a3	173	(+) ErrorCallback : callback when error occurs.
AnnaBridge	189:f392fc9709a3	174	(+) AbortCpltCallback : callback when abort is completed.
AnnaBridge	189:f392fc9709a3	175	(+) FifoThresholdCallback : callback when the fifo threshold is reached.
AnnaBridge	189:f392fc9709a3	176	(+) CmdCpltCallback : callback when a command without data is completed.
AnnaBridge	189:f392fc9709a3	177	(+) RxCpltCallback : callback when a reception transfer is completed.
AnnaBridge	189:f392fc9709a3	178	(+) TxCpltCallback : callback when a transmission transfer is completed.
AnnaBridge	189:f392fc9709a3	179	(+) StatusMatchCallback : callback when a status match occurs.
AnnaBridge	189:f392fc9709a3	180	(+) TimeOutCallback : callback when the timeout perioed expires.
AnnaBridge	189:f392fc9709a3	181	(+) MspInitCallback : QSPI MspInit.
AnnaBridge	189:f392fc9709a3	182	(+) MspDeInitCallback : QSPI MspDeInit.
AnnaBridge	189:f392fc9709a3	183	This function) takes as parameters the HAL peripheral handle and the Callback ID.
AnnaBridge	189:f392fc9709a3	184
AnnaBridge	189:f392fc9709a3	185	By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
AnnaBridge	189:f392fc9709a3	186	all callbacks are reset to the corresponding legacy weak (surcharged) functions.
AnnaBridge	189:f392fc9709a3	187	Exception done for MspInit and MspDeInit callbacks that are respectively
AnnaBridge	189:f392fc9709a3	188	reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
AnnaBridge	189:f392fc9709a3	189	and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
AnnaBridge	189:f392fc9709a3	190	If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
AnnaBridge	189:f392fc9709a3	191	keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
AnnaBridge	189:f392fc9709a3	192
AnnaBridge	189:f392fc9709a3	193	Callbacks can be registered/unregistered in READY state only.
AnnaBridge	189:f392fc9709a3	194	Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
AnnaBridge	189:f392fc9709a3	195	in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
AnnaBridge	189:f392fc9709a3	196	during the Init/DeInit.
AnnaBridge	189:f392fc9709a3	197	In that case first register the MspInit/MspDeInit user callbacks
AnnaBridge	189:f392fc9709a3	198	using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
AnnaBridge	189:f392fc9709a3	199	or @ref HAL_QSPI_Init function.
AnnaBridge	189:f392fc9709a3	200
AnnaBridge	189:f392fc9709a3	201	When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
AnnaBridge	189:f392fc9709a3	202	not defined, the callback registering feature is not available
AnnaBridge	189:f392fc9709a3	203	and weak (surcharged) callbacks are used.
AnnaBridge	189:f392fc9709a3	204
AnnaBridge	189:f392fc9709a3	205	* Workarounds linked to Silicon Limitation *
AnnaBridge	189:f392fc9709a3	206	====================================================
AnnaBridge	189:f392fc9709a3	207	[..]
AnnaBridge	189:f392fc9709a3	208	(#) Workarounds Implemented inside HAL Driver
AnnaBridge	189:f392fc9709a3	209	(++) Extra data written in the FIFO at the end of a read transfer
AnnaBridge	189:f392fc9709a3	210
AnnaBridge	189:f392fc9709a3	211	@endverbatim
AnnaBridge	189:f392fc9709a3	212	******************************************************************************
AnnaBridge	189:f392fc9709a3	213	* @attention
AnnaBridge	189:f392fc9709a3	214	*
AnnaBridge	189:f392fc9709a3	215	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
AnnaBridge	189:f392fc9709a3	216	* All rights reserved.</center></h2>
AnnaBridge	189:f392fc9709a3	217	*
AnnaBridge	189:f392fc9709a3	218	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	189:f392fc9709a3	219	* the "License"; You may not use this file except in compliance with the
AnnaBridge	189:f392fc9709a3	220	* License. You may obtain a copy of the License at:
AnnaBridge	189:f392fc9709a3	221	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	189:f392fc9709a3	222	*
AnnaBridge	189:f392fc9709a3	223	******************************************************************************
AnnaBridge	189:f392fc9709a3	224	*/
AnnaBridge	189:f392fc9709a3	225
AnnaBridge	189:f392fc9709a3	226	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	227	#include "stm32h7xx_hal.h"
AnnaBridge	189:f392fc9709a3	228
AnnaBridge	189:f392fc9709a3	229	/** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge	189:f392fc9709a3	230	* @{
AnnaBridge	189:f392fc9709a3	231	*/
AnnaBridge	189:f392fc9709a3	232
AnnaBridge	189:f392fc9709a3	233	/** @defgroup QSPI QSPI
AnnaBridge	189:f392fc9709a3	234	* @brief QSPI HAL module driver
AnnaBridge	189:f392fc9709a3	235	* @{
AnnaBridge	189:f392fc9709a3	236	*/
AnnaBridge	189:f392fc9709a3	237	#ifdef HAL_QSPI_MODULE_ENABLED
AnnaBridge	189:f392fc9709a3	238
AnnaBridge	189:f392fc9709a3	239	/* Private typedef -----------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	240
AnnaBridge	189:f392fc9709a3	241	/* Private define ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	242	/** @defgroup QSPI_Private_Constants QSPI Private Constants
AnnaBridge	189:f392fc9709a3	243	* @{
AnnaBridge	189:f392fc9709a3	244	*/
AnnaBridge	189:f392fc9709a3	245	#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /!<Indirect write mode/
AnnaBridge	189:f392fc9709a3	246	#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /!<Indirect read mode/
AnnaBridge	189:f392fc9709a3	247	#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /!<Automatic polling mode/
AnnaBridge	189:f392fc9709a3	248	#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /!<Memory-mapped mode/
AnnaBridge	189:f392fc9709a3	249	/**
AnnaBridge	189:f392fc9709a3	250	* @}
AnnaBridge	189:f392fc9709a3	251	*/
AnnaBridge	189:f392fc9709a3	252
AnnaBridge	189:f392fc9709a3	253	/* Private macro -------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	254	/** @defgroup QSPI_Private_Macros QSPI Private Macros
AnnaBridge	189:f392fc9709a3	255	* @{
AnnaBridge	189:f392fc9709a3	256	*/
AnnaBridge	189:f392fc9709a3	257	#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) \|\| \
AnnaBridge	189:f392fc9709a3	258	((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) \|\| \
AnnaBridge	189:f392fc9709a3	259	((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) \|\| \
AnnaBridge	189:f392fc9709a3	260	((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
AnnaBridge	189:f392fc9709a3	261	/**
AnnaBridge	189:f392fc9709a3	262	* @}
AnnaBridge	189:f392fc9709a3	263	*/
AnnaBridge	189:f392fc9709a3	264
AnnaBridge	189:f392fc9709a3	265	/* Private variables ---------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	266
AnnaBridge	189:f392fc9709a3	267	/* Private function prototypes -----------------------------------------------*/
AnnaBridge	189:f392fc9709a3	268	static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma);
AnnaBridge	189:f392fc9709a3	269	static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma);
AnnaBridge	189:f392fc9709a3	270	static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma);
AnnaBridge	189:f392fc9709a3	271	static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma);
AnnaBridge	189:f392fc9709a3	272	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
AnnaBridge	189:f392fc9709a3	273	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode);
AnnaBridge	189:f392fc9709a3	274
AnnaBridge	189:f392fc9709a3	275	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	276
AnnaBridge	189:f392fc9709a3	277	/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
AnnaBridge	189:f392fc9709a3	278	* @{
AnnaBridge	189:f392fc9709a3	279	*/
AnnaBridge	189:f392fc9709a3	280
AnnaBridge	189:f392fc9709a3	281	/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
AnnaBridge	189:f392fc9709a3	282	* @brief Initialization and Configuration functions
AnnaBridge	189:f392fc9709a3	283	*
AnnaBridge	189:f392fc9709a3	284	@verbatim
AnnaBridge	189:f392fc9709a3	285	===============================================================================
AnnaBridge	189:f392fc9709a3	286	##### Initialization and Configuration functions #####
AnnaBridge	189:f392fc9709a3	287	===============================================================================
AnnaBridge	189:f392fc9709a3	288	[..]
AnnaBridge	189:f392fc9709a3	289	This subsection provides a set of functions allowing to :
AnnaBridge	189:f392fc9709a3	290	(+) Initialize the QuadSPI.
AnnaBridge	189:f392fc9709a3	291	(+) De-initialize the QuadSPI.
AnnaBridge	189:f392fc9709a3	292
AnnaBridge	189:f392fc9709a3	293	@endverbatim
AnnaBridge	189:f392fc9709a3	294	* @{
AnnaBridge	189:f392fc9709a3	295	*/
AnnaBridge	189:f392fc9709a3	296
AnnaBridge	189:f392fc9709a3	297	/**
AnnaBridge	189:f392fc9709a3	298	* @brief Initialize the QSPI mode according to the specified parameters
AnnaBridge	189:f392fc9709a3	299	* in the QSPI_InitTypeDef and initialize the associated handle.
AnnaBridge	189:f392fc9709a3	300	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	301	* @retval HAL status
AnnaBridge	189:f392fc9709a3	302	*/
AnnaBridge	189:f392fc9709a3	303	HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	304	{
AnnaBridge	189:f392fc9709a3	305	HAL_StatusTypeDef status;
AnnaBridge	189:f392fc9709a3	306	uint32_t tickstart = HAL_GetTick();
AnnaBridge	189:f392fc9709a3	307
AnnaBridge	189:f392fc9709a3	308	/* Check the QSPI handle allocation */
AnnaBridge	189:f392fc9709a3	309	if(hqspi == NULL)
AnnaBridge	189:f392fc9709a3	310	{
AnnaBridge	189:f392fc9709a3	311	return HAL_ERROR;
AnnaBridge	189:f392fc9709a3	312	}
AnnaBridge	189:f392fc9709a3	313
AnnaBridge	189:f392fc9709a3	314	/* Check the parameters */
AnnaBridge	189:f392fc9709a3	315	assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
AnnaBridge	189:f392fc9709a3	316	assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
AnnaBridge	189:f392fc9709a3	317	assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
AnnaBridge	189:f392fc9709a3	318	assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
AnnaBridge	189:f392fc9709a3	319	assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
AnnaBridge	189:f392fc9709a3	320	assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
AnnaBridge	189:f392fc9709a3	321	assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
AnnaBridge	189:f392fc9709a3	322	assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
AnnaBridge	189:f392fc9709a3	323
AnnaBridge	189:f392fc9709a3	324	if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
AnnaBridge	189:f392fc9709a3	325	{
AnnaBridge	189:f392fc9709a3	326	assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
AnnaBridge	189:f392fc9709a3	327	}
AnnaBridge	189:f392fc9709a3	328
AnnaBridge	189:f392fc9709a3	329	/* Process locked */
AnnaBridge	189:f392fc9709a3	330	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	331
AnnaBridge	189:f392fc9709a3	332	if(hqspi->State == HAL_QSPI_STATE_RESET)
AnnaBridge	189:f392fc9709a3	333	{
AnnaBridge	189:f392fc9709a3	334	/* Allocate lock resource and initialize it */
AnnaBridge	189:f392fc9709a3	335	hqspi->Lock = HAL_UNLOCKED;
AnnaBridge	189:f392fc9709a3	336
AnnaBridge	189:f392fc9709a3	337	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	338	/* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
AnnaBridge	189:f392fc9709a3	339	hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
AnnaBridge	189:f392fc9709a3	340	hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
AnnaBridge	189:f392fc9709a3	341	hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
AnnaBridge	189:f392fc9709a3	342	hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
AnnaBridge	189:f392fc9709a3	343	hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
AnnaBridge	189:f392fc9709a3	344	hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
AnnaBridge	189:f392fc9709a3	345	hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
AnnaBridge	189:f392fc9709a3	346	hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
AnnaBridge	189:f392fc9709a3	347
AnnaBridge	189:f392fc9709a3	348	if(hqspi->MspInitCallback == NULL)
AnnaBridge	189:f392fc9709a3	349	{
AnnaBridge	189:f392fc9709a3	350	hqspi->MspInitCallback = HAL_QSPI_MspInit;
AnnaBridge	189:f392fc9709a3	351	}
AnnaBridge	189:f392fc9709a3	352
AnnaBridge	189:f392fc9709a3	353	/* Init the low level hardware */
AnnaBridge	189:f392fc9709a3	354	hqspi->MspInitCallback(hqspi);
AnnaBridge	189:f392fc9709a3	355	#else
AnnaBridge	189:f392fc9709a3	356	/* Init the low level hardware : GPIO, CLOCK */
AnnaBridge	189:f392fc9709a3	357	HAL_QSPI_MspInit(hqspi);
AnnaBridge	189:f392fc9709a3	358	#endif
AnnaBridge	189:f392fc9709a3	359	/* Configure the default timeout for the QSPI memory access */
AnnaBridge	189:f392fc9709a3	360	HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
AnnaBridge	189:f392fc9709a3	361	}
AnnaBridge	189:f392fc9709a3	362
AnnaBridge	189:f392fc9709a3	363	/* Configure QSPI FIFO Threshold */
AnnaBridge	189:f392fc9709a3	364	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
AnnaBridge	189:f392fc9709a3	365	((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
AnnaBridge	189:f392fc9709a3	366
AnnaBridge	189:f392fc9709a3	367	/* Wait till BUSY flag reset */
AnnaBridge	189:f392fc9709a3	368	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
AnnaBridge	189:f392fc9709a3	369
AnnaBridge	189:f392fc9709a3	370	if(status == HAL_OK)
AnnaBridge	189:f392fc9709a3	371	{
AnnaBridge	189:f392fc9709a3	372	/* Configure QSPI Clock Prescaler and Sample Shift */
AnnaBridge	189:f392fc9709a3	373	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT \| QUADSPI_CR_FSEL \| QUADSPI_CR_DFM),
AnnaBridge	189:f392fc9709a3	374	((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) \|
AnnaBridge	189:f392fc9709a3	375	hqspi->Init.SampleShifting \| hqspi->Init.FlashID \| hqspi->Init.DualFlash));
AnnaBridge	189:f392fc9709a3	376
AnnaBridge	189:f392fc9709a3	377	/* Configure QSPI Flash Size, CS High Time and Clock Mode */
AnnaBridge	189:f392fc9709a3	378	MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE \| QUADSPI_DCR_CSHT \| QUADSPI_DCR_CKMODE),
AnnaBridge	189:f392fc9709a3	379	((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) \|
AnnaBridge	189:f392fc9709a3	380	hqspi->Init.ChipSelectHighTime \| hqspi->Init.ClockMode));
AnnaBridge	189:f392fc9709a3	381
AnnaBridge	189:f392fc9709a3	382	/* Enable the QSPI peripheral */
AnnaBridge	189:f392fc9709a3	383	__HAL_QSPI_ENABLE(hqspi);
AnnaBridge	189:f392fc9709a3	384
AnnaBridge	189:f392fc9709a3	385	/* Set QSPI error code to none */
AnnaBridge	189:f392fc9709a3	386	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	387
AnnaBridge	189:f392fc9709a3	388	/* Initialize the QSPI state */
AnnaBridge	189:f392fc9709a3	389	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	390	}
AnnaBridge	189:f392fc9709a3	391
AnnaBridge	189:f392fc9709a3	392	/* Release Lock */
AnnaBridge	189:f392fc9709a3	393	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	394
AnnaBridge	189:f392fc9709a3	395	/* Return function status */
AnnaBridge	189:f392fc9709a3	396	return status;
AnnaBridge	189:f392fc9709a3	397	}
AnnaBridge	189:f392fc9709a3	398
AnnaBridge	189:f392fc9709a3	399	/**
AnnaBridge	189:f392fc9709a3	400	* @brief De-Initialize the QSPI peripheral.
AnnaBridge	189:f392fc9709a3	401	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	402	* @retval HAL status
AnnaBridge	189:f392fc9709a3	403	*/
AnnaBridge	189:f392fc9709a3	404	HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	405	{
AnnaBridge	189:f392fc9709a3	406	/* Check the QSPI handle allocation */
AnnaBridge	189:f392fc9709a3	407	if(hqspi == NULL)
AnnaBridge	189:f392fc9709a3	408	{
AnnaBridge	189:f392fc9709a3	409	return HAL_ERROR;
AnnaBridge	189:f392fc9709a3	410	}
AnnaBridge	189:f392fc9709a3	411
AnnaBridge	189:f392fc9709a3	412	/* Process locked */
AnnaBridge	189:f392fc9709a3	413	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	414
AnnaBridge	189:f392fc9709a3	415	/* Disable the QSPI Peripheral Clock */
AnnaBridge	189:f392fc9709a3	416	__HAL_QSPI_DISABLE(hqspi);
AnnaBridge	189:f392fc9709a3	417
AnnaBridge	189:f392fc9709a3	418	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	419	if(hqspi->MspDeInitCallback == NULL)
AnnaBridge	189:f392fc9709a3	420	{
AnnaBridge	189:f392fc9709a3	421	hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
AnnaBridge	189:f392fc9709a3	422	}
AnnaBridge	189:f392fc9709a3	423
AnnaBridge	189:f392fc9709a3	424	/* DeInit the low level hardware */
AnnaBridge	189:f392fc9709a3	425	hqspi->MspDeInitCallback(hqspi);
AnnaBridge	189:f392fc9709a3	426	#else
AnnaBridge	189:f392fc9709a3	427	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
AnnaBridge	189:f392fc9709a3	428	HAL_QSPI_MspDeInit(hqspi);
AnnaBridge	189:f392fc9709a3	429	#endif
AnnaBridge	189:f392fc9709a3	430
AnnaBridge	189:f392fc9709a3	431	/* Set QSPI error code to none */
AnnaBridge	189:f392fc9709a3	432	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	433
AnnaBridge	189:f392fc9709a3	434	/* Initialize the QSPI state */
AnnaBridge	189:f392fc9709a3	435	hqspi->State = HAL_QSPI_STATE_RESET;
AnnaBridge	189:f392fc9709a3	436
AnnaBridge	189:f392fc9709a3	437	/* Release Lock */
AnnaBridge	189:f392fc9709a3	438	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	439
AnnaBridge	189:f392fc9709a3	440	return HAL_OK;
AnnaBridge	189:f392fc9709a3	441	}
AnnaBridge	189:f392fc9709a3	442
AnnaBridge	189:f392fc9709a3	443	/**
AnnaBridge	189:f392fc9709a3	444	* @brief Initialize the QSPI MSP.
AnnaBridge	189:f392fc9709a3	445	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	446	* @retval None
AnnaBridge	189:f392fc9709a3	447	*/
AnnaBridge	189:f392fc9709a3	448	__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	449	{
AnnaBridge	189:f392fc9709a3	450	/* Prevent unused argument(s) compilation warning */
AnnaBridge	189:f392fc9709a3	451	UNUSED(hqspi);
AnnaBridge	189:f392fc9709a3	452
AnnaBridge	189:f392fc9709a3	453	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	189:f392fc9709a3	454	the HAL_QSPI_MspInit can be implemented in the user file
AnnaBridge	189:f392fc9709a3	455	*/
AnnaBridge	189:f392fc9709a3	456	}
AnnaBridge	189:f392fc9709a3	457
AnnaBridge	189:f392fc9709a3	458	/**
AnnaBridge	189:f392fc9709a3	459	* @brief DeInitialize the QSPI MSP.
AnnaBridge	189:f392fc9709a3	460	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	461	* @retval None
AnnaBridge	189:f392fc9709a3	462	*/
AnnaBridge	189:f392fc9709a3	463	__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	464	{
AnnaBridge	189:f392fc9709a3	465	/* Prevent unused argument(s) compilation warning */
AnnaBridge	189:f392fc9709a3	466	UNUSED(hqspi);
AnnaBridge	189:f392fc9709a3	467
AnnaBridge	189:f392fc9709a3	468	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	189:f392fc9709a3	469	the HAL_QSPI_MspDeInit can be implemented in the user file
AnnaBridge	189:f392fc9709a3	470	*/
AnnaBridge	189:f392fc9709a3	471	}
AnnaBridge	189:f392fc9709a3	472
AnnaBridge	189:f392fc9709a3	473	/**
AnnaBridge	189:f392fc9709a3	474	* @}
AnnaBridge	189:f392fc9709a3	475	*/
AnnaBridge	189:f392fc9709a3	476
AnnaBridge	189:f392fc9709a3	477	/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
AnnaBridge	189:f392fc9709a3	478	* @brief QSPI Transmit/Receive functions
AnnaBridge	189:f392fc9709a3	479	*
AnnaBridge	189:f392fc9709a3	480	@verbatim
AnnaBridge	189:f392fc9709a3	481	===============================================================================
AnnaBridge	189:f392fc9709a3	482	##### IO operation functions #####
AnnaBridge	189:f392fc9709a3	483	===============================================================================
AnnaBridge	189:f392fc9709a3	484	[..]
AnnaBridge	189:f392fc9709a3	485	This subsection provides a set of functions allowing to :
AnnaBridge	189:f392fc9709a3	486	(+) Handle the interrupts.
AnnaBridge	189:f392fc9709a3	487	(+) Handle the command sequence.
AnnaBridge	189:f392fc9709a3	488	(+) Transmit data in blocking, interrupt or DMA mode.
AnnaBridge	189:f392fc9709a3	489	(+) Receive data in blocking, interrupt or DMA mode.
AnnaBridge	189:f392fc9709a3	490	(+) Manage the auto-polling functional mode.
AnnaBridge	189:f392fc9709a3	491	(+) Manage the memory-mapped functional mode.
AnnaBridge	189:f392fc9709a3	492
AnnaBridge	189:f392fc9709a3	493	@endverbatim
AnnaBridge	189:f392fc9709a3	494	* @{
AnnaBridge	189:f392fc9709a3	495	*/
AnnaBridge	189:f392fc9709a3	496
AnnaBridge	189:f392fc9709a3	497	/**
AnnaBridge	189:f392fc9709a3	498	* @brief Handle QSPI interrupt request.
AnnaBridge	189:f392fc9709a3	499	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	500	* @retval None
AnnaBridge	189:f392fc9709a3	501	*/
AnnaBridge	189:f392fc9709a3	502	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	503	{
AnnaBridge	189:f392fc9709a3	504	__IO uint32_t *data_reg;
AnnaBridge	189:f392fc9709a3	505	uint32_t flag = READ_REG(hqspi->Instance->SR);
AnnaBridge	189:f392fc9709a3	506	uint32_t itsource = READ_REG(hqspi->Instance->CR);
AnnaBridge	189:f392fc9709a3	507
AnnaBridge	189:f392fc9709a3	508	/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
AnnaBridge	189:f392fc9709a3	509	if(((flag & QSPI_FLAG_FT) == QSPI_FLAG_FT) && ((itsource & QSPI_IT_FT) == QSPI_IT_FT))
AnnaBridge	189:f392fc9709a3	510	{
AnnaBridge	189:f392fc9709a3	511	data_reg = &hqspi->Instance->DR;
AnnaBridge	189:f392fc9709a3	512
AnnaBridge	189:f392fc9709a3	513	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
AnnaBridge	189:f392fc9709a3	514	{
AnnaBridge	189:f392fc9709a3	515	/* Transmission process */
AnnaBridge	189:f392fc9709a3	516	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
AnnaBridge	189:f392fc9709a3	517	{
AnnaBridge	189:f392fc9709a3	518	if (hqspi->TxXferCount > 0U)
AnnaBridge	189:f392fc9709a3	519	{
AnnaBridge	189:f392fc9709a3	520	/* Fill the FIFO until the threshold is reached */
AnnaBridge	189:f392fc9709a3	521	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr;
AnnaBridge	189:f392fc9709a3	522	hqspi->pTxBuffPtr++;
AnnaBridge	189:f392fc9709a3	523	hqspi->TxXferCount--;
AnnaBridge	189:f392fc9709a3	524	}
AnnaBridge	189:f392fc9709a3	525	else
AnnaBridge	189:f392fc9709a3	526	{
AnnaBridge	189:f392fc9709a3	527	/* No more data available for the transfer */
AnnaBridge	189:f392fc9709a3	528	/* Disable the QSPI FIFO Threshold Interrupt */
AnnaBridge	189:f392fc9709a3	529	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
AnnaBridge	189:f392fc9709a3	530	break;
AnnaBridge	189:f392fc9709a3	531	}
AnnaBridge	189:f392fc9709a3	532	}
AnnaBridge	189:f392fc9709a3	533	}
AnnaBridge	189:f392fc9709a3	534	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
AnnaBridge	189:f392fc9709a3	535	{
AnnaBridge	189:f392fc9709a3	536	/* Receiving Process */
AnnaBridge	189:f392fc9709a3	537	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
AnnaBridge	189:f392fc9709a3	538	{
AnnaBridge	189:f392fc9709a3	539	if (hqspi->RxXferCount > 0U)
AnnaBridge	189:f392fc9709a3	540	{
AnnaBridge	189:f392fc9709a3	541	/* Read the FIFO until the threshold is reached */
AnnaBridge	189:f392fc9709a3	542	hqspi->pRxBuffPtr = (__IO uint8_t *)data_reg;
AnnaBridge	189:f392fc9709a3	543	hqspi->pRxBuffPtr++;
AnnaBridge	189:f392fc9709a3	544	hqspi->RxXferCount--;
AnnaBridge	189:f392fc9709a3	545	}
AnnaBridge	189:f392fc9709a3	546	else
AnnaBridge	189:f392fc9709a3	547	{
AnnaBridge	189:f392fc9709a3	548	/* All data have been received for the transfer */
AnnaBridge	189:f392fc9709a3	549	/* Disable the QSPI FIFO Threshold Interrupt */
AnnaBridge	189:f392fc9709a3	550	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
AnnaBridge	189:f392fc9709a3	551	break;
AnnaBridge	189:f392fc9709a3	552	}
AnnaBridge	189:f392fc9709a3	553	}
AnnaBridge	189:f392fc9709a3	554	}
AnnaBridge	189:f392fc9709a3	555	else
AnnaBridge	189:f392fc9709a3	556	{
AnnaBridge	189:f392fc9709a3	557	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	558	}
AnnaBridge	189:f392fc9709a3	559	/* FIFO Threshold callback */
AnnaBridge	189:f392fc9709a3	560	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	561	hqspi->FifoThresholdCallback(hqspi);
AnnaBridge	189:f392fc9709a3	562	#else
AnnaBridge	189:f392fc9709a3	563	HAL_QSPI_FifoThresholdCallback(hqspi);
AnnaBridge	189:f392fc9709a3	564	#endif
AnnaBridge	189:f392fc9709a3	565	}
AnnaBridge	189:f392fc9709a3	566
AnnaBridge	189:f392fc9709a3	567	/* QSPI Transfer Complete interrupt occurred -------------------------------*/
AnnaBridge	189:f392fc9709a3	568	else if(((flag & QSPI_FLAG_TC) == QSPI_FLAG_TC) && ((itsource & QSPI_IT_TC) == QSPI_IT_TC))
AnnaBridge	189:f392fc9709a3	569	{
AnnaBridge	189:f392fc9709a3	570	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	571	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
AnnaBridge	189:f392fc9709a3	572
AnnaBridge	189:f392fc9709a3	573	/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
AnnaBridge	189:f392fc9709a3	574	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
AnnaBridge	189:f392fc9709a3	575
AnnaBridge	189:f392fc9709a3	576	/* Transfer complete callback */
AnnaBridge	189:f392fc9709a3	577	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
AnnaBridge	189:f392fc9709a3	578	{
AnnaBridge	189:f392fc9709a3	579	if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
AnnaBridge	189:f392fc9709a3	580	{
AnnaBridge	189:f392fc9709a3	581	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
AnnaBridge	189:f392fc9709a3	582	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
AnnaBridge	189:f392fc9709a3	583
AnnaBridge	189:f392fc9709a3	584	/* Disable the MDMA channel */
AnnaBridge	189:f392fc9709a3	585	__HAL_MDMA_DISABLE(hqspi->hmdma);
AnnaBridge	189:f392fc9709a3	586	}
AnnaBridge	189:f392fc9709a3	587
AnnaBridge	189:f392fc9709a3	588	/* Change state of QSPI */
AnnaBridge	189:f392fc9709a3	589	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	590
AnnaBridge	189:f392fc9709a3	591	/* TX Complete callback */
AnnaBridge	189:f392fc9709a3	592	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	593	hqspi->TxCpltCallback(hqspi);
AnnaBridge	189:f392fc9709a3	594	#else
AnnaBridge	189:f392fc9709a3	595	HAL_QSPI_TxCpltCallback(hqspi);
AnnaBridge	189:f392fc9709a3	596	#endif
AnnaBridge	189:f392fc9709a3	597	}
AnnaBridge	189:f392fc9709a3	598	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
AnnaBridge	189:f392fc9709a3	599	{
AnnaBridge	189:f392fc9709a3	600	if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
AnnaBridge	189:f392fc9709a3	601	{
AnnaBridge	189:f392fc9709a3	602	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
AnnaBridge	189:f392fc9709a3	603	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
AnnaBridge	189:f392fc9709a3	604
AnnaBridge	189:f392fc9709a3	605	/* Disable the MDMA channel */
AnnaBridge	189:f392fc9709a3	606	__HAL_MDMA_DISABLE(hqspi->hmdma);
AnnaBridge	189:f392fc9709a3	607	}
AnnaBridge	189:f392fc9709a3	608	else
AnnaBridge	189:f392fc9709a3	609	{
AnnaBridge	189:f392fc9709a3	610	data_reg = &hqspi->Instance->DR;
AnnaBridge	189:f392fc9709a3	611	while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
AnnaBridge	189:f392fc9709a3	612	{
AnnaBridge	189:f392fc9709a3	613	if (hqspi->RxXferCount > 0U)
AnnaBridge	189:f392fc9709a3	614	{
AnnaBridge	189:f392fc9709a3	615	/* Read the last data received in the FIFO until it is empty */
AnnaBridge	189:f392fc9709a3	616	hqspi->pRxBuffPtr = (__IO uint8_t *)data_reg;
AnnaBridge	189:f392fc9709a3	617	hqspi->pRxBuffPtr++;
AnnaBridge	189:f392fc9709a3	618	hqspi->RxXferCount--;
AnnaBridge	189:f392fc9709a3	619	}
AnnaBridge	189:f392fc9709a3	620	else
AnnaBridge	189:f392fc9709a3	621	{
AnnaBridge	189:f392fc9709a3	622	/* All data have been received for the transfer */
AnnaBridge	189:f392fc9709a3	623	break;
AnnaBridge	189:f392fc9709a3	624	}
AnnaBridge	189:f392fc9709a3	625	}
AnnaBridge	189:f392fc9709a3	626	}
AnnaBridge	189:f392fc9709a3	627
AnnaBridge	189:f392fc9709a3	628	/* Change state of QSPI */
AnnaBridge	189:f392fc9709a3	629	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	630
AnnaBridge	189:f392fc9709a3	631	/* RX Complete callback */
AnnaBridge	189:f392fc9709a3	632	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	633	hqspi->RxCpltCallback(hqspi);
AnnaBridge	189:f392fc9709a3	634	#else
AnnaBridge	189:f392fc9709a3	635	HAL_QSPI_RxCpltCallback(hqspi);
AnnaBridge	189:f392fc9709a3	636	#endif
AnnaBridge	189:f392fc9709a3	637	}
AnnaBridge	189:f392fc9709a3	638	else if(hqspi->State == HAL_QSPI_STATE_BUSY)
AnnaBridge	189:f392fc9709a3	639	{
AnnaBridge	189:f392fc9709a3	640	/* Change state of QSPI */
AnnaBridge	189:f392fc9709a3	641	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	642
AnnaBridge	189:f392fc9709a3	643	/* Command Complete callback */
AnnaBridge	189:f392fc9709a3	644	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	645	hqspi->CmdCpltCallback(hqspi);
AnnaBridge	189:f392fc9709a3	646	#else
AnnaBridge	189:f392fc9709a3	647	HAL_QSPI_CmdCpltCallback(hqspi);
AnnaBridge	189:f392fc9709a3	648	#endif
AnnaBridge	189:f392fc9709a3	649	}
AnnaBridge	189:f392fc9709a3	650	else if(hqspi->State == HAL_QSPI_STATE_ABORT)
AnnaBridge	189:f392fc9709a3	651	{
AnnaBridge	189:f392fc9709a3	652	/* Reset functional mode configuration to indirect write mode by default */
AnnaBridge	189:f392fc9709a3	653	CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
AnnaBridge	189:f392fc9709a3	654
AnnaBridge	189:f392fc9709a3	655	/* Change state of QSPI */
AnnaBridge	189:f392fc9709a3	656	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	657
AnnaBridge	189:f392fc9709a3	658	if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
AnnaBridge	189:f392fc9709a3	659	{
AnnaBridge	189:f392fc9709a3	660	/* Abort called by the user */
AnnaBridge	189:f392fc9709a3	661
AnnaBridge	189:f392fc9709a3	662	/* Abort Complete callback */
AnnaBridge	189:f392fc9709a3	663	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	664	hqspi->AbortCpltCallback(hqspi);
AnnaBridge	189:f392fc9709a3	665	#else
AnnaBridge	189:f392fc9709a3	666	HAL_QSPI_AbortCpltCallback(hqspi);
AnnaBridge	189:f392fc9709a3	667	#endif
AnnaBridge	189:f392fc9709a3	668	}
AnnaBridge	189:f392fc9709a3	669	else
AnnaBridge	189:f392fc9709a3	670	{
AnnaBridge	189:f392fc9709a3	671	/* Abort due to an error (eg : MDMA error) */
AnnaBridge	189:f392fc9709a3	672
AnnaBridge	189:f392fc9709a3	673	/* Error callback */
AnnaBridge	189:f392fc9709a3	674	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	675	hqspi->ErrorCallback(hqspi);
AnnaBridge	189:f392fc9709a3	676	#else
AnnaBridge	189:f392fc9709a3	677	HAL_QSPI_ErrorCallback(hqspi);
AnnaBridge	189:f392fc9709a3	678	#endif
AnnaBridge	189:f392fc9709a3	679	}
AnnaBridge	189:f392fc9709a3	680	}
AnnaBridge	189:f392fc9709a3	681	else
AnnaBridge	189:f392fc9709a3	682	{
AnnaBridge	189:f392fc9709a3	683	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	684	}
AnnaBridge	189:f392fc9709a3	685	}
AnnaBridge	189:f392fc9709a3	686
AnnaBridge	189:f392fc9709a3	687	/* QSPI Status Match interrupt occurred ------------------------------------*/
AnnaBridge	189:f392fc9709a3	688	else if(((flag & QSPI_FLAG_SM)== QSPI_FLAG_SM) && ((itsource & QSPI_IT_SM) == QSPI_IT_SM))
AnnaBridge	189:f392fc9709a3	689	{
AnnaBridge	189:f392fc9709a3	690	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	691	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
AnnaBridge	189:f392fc9709a3	692
AnnaBridge	189:f392fc9709a3	693	/* Check if the automatic poll mode stop is activated */
AnnaBridge	189:f392fc9709a3	694	if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
AnnaBridge	189:f392fc9709a3	695	{
AnnaBridge	189:f392fc9709a3	696	/* Disable the QSPI Transfer Error and Status Match Interrupts */
AnnaBridge	189:f392fc9709a3	697	__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
AnnaBridge	189:f392fc9709a3	698
AnnaBridge	189:f392fc9709a3	699	/* Change state of QSPI */
AnnaBridge	189:f392fc9709a3	700	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	701	}
AnnaBridge	189:f392fc9709a3	702
AnnaBridge	189:f392fc9709a3	703	/* Status match callback */
AnnaBridge	189:f392fc9709a3	704	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	705	hqspi->StatusMatchCallback(hqspi);
AnnaBridge	189:f392fc9709a3	706	#else
AnnaBridge	189:f392fc9709a3	707	HAL_QSPI_StatusMatchCallback(hqspi);
AnnaBridge	189:f392fc9709a3	708	#endif
AnnaBridge	189:f392fc9709a3	709	}
AnnaBridge	189:f392fc9709a3	710
AnnaBridge	189:f392fc9709a3	711	/* QSPI Transfer Error interrupt occurred ----------------------------------*/
AnnaBridge	189:f392fc9709a3	712	else if(((flag & QSPI_FLAG_TE) == QSPI_FLAG_TE) && ((itsource & QSPI_IT_TE) == QSPI_IT_TE))
AnnaBridge	189:f392fc9709a3	713	{
AnnaBridge	189:f392fc9709a3	714	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	715	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
AnnaBridge	189:f392fc9709a3	716
AnnaBridge	189:f392fc9709a3	717	/* Disable all the QSPI Interrupts */
AnnaBridge	189:f392fc9709a3	718	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
AnnaBridge	189:f392fc9709a3	719
AnnaBridge	189:f392fc9709a3	720	/* Set error code */
AnnaBridge	189:f392fc9709a3	721	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TRANSFER;
AnnaBridge	189:f392fc9709a3	722
AnnaBridge	189:f392fc9709a3	723	if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
AnnaBridge	189:f392fc9709a3	724	{
AnnaBridge	189:f392fc9709a3	725	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
AnnaBridge	189:f392fc9709a3	726	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
AnnaBridge	189:f392fc9709a3	727
AnnaBridge	189:f392fc9709a3	728	/* Disable the MDMA channel */
AnnaBridge	189:f392fc9709a3	729	hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
AnnaBridge	189:f392fc9709a3	730	if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
AnnaBridge	189:f392fc9709a3	731	{
AnnaBridge	189:f392fc9709a3	732	/* Set error code to DMA */
AnnaBridge	189:f392fc9709a3	733	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
AnnaBridge	189:f392fc9709a3	734
AnnaBridge	189:f392fc9709a3	735	/* Change state of QSPI */
AnnaBridge	189:f392fc9709a3	736	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	737
AnnaBridge	189:f392fc9709a3	738	/* Error callback */
AnnaBridge	189:f392fc9709a3	739	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	740	hqspi->ErrorCallback(hqspi);
AnnaBridge	189:f392fc9709a3	741	#else
AnnaBridge	189:f392fc9709a3	742	HAL_QSPI_ErrorCallback(hqspi);
AnnaBridge	189:f392fc9709a3	743	#endif
AnnaBridge	189:f392fc9709a3	744	}
AnnaBridge	189:f392fc9709a3	745	}
AnnaBridge	189:f392fc9709a3	746	else
AnnaBridge	189:f392fc9709a3	747	{
AnnaBridge	189:f392fc9709a3	748	/* Change state of QSPI */
AnnaBridge	189:f392fc9709a3	749	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	750
AnnaBridge	189:f392fc9709a3	751	/* Error callback */
AnnaBridge	189:f392fc9709a3	752	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	753	hqspi->ErrorCallback(hqspi);
AnnaBridge	189:f392fc9709a3	754	#else
AnnaBridge	189:f392fc9709a3	755	HAL_QSPI_ErrorCallback(hqspi);
AnnaBridge	189:f392fc9709a3	756	#endif
AnnaBridge	189:f392fc9709a3	757	}
AnnaBridge	189:f392fc9709a3	758	}
AnnaBridge	189:f392fc9709a3	759
AnnaBridge	189:f392fc9709a3	760	/* QSPI Timeout interrupt occurred -----------------------------------------*/
AnnaBridge	189:f392fc9709a3	761	else if(((flag & QSPI_FLAG_TO) == QSPI_FLAG_TO) && ((itsource & QSPI_IT_TO) == QSPI_IT_TO))
AnnaBridge	189:f392fc9709a3	762	{
AnnaBridge	189:f392fc9709a3	763	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	764	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
AnnaBridge	189:f392fc9709a3	765
AnnaBridge	189:f392fc9709a3	766	/* Timeout callback */
AnnaBridge	189:f392fc9709a3	767	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	768	hqspi->TimeOutCallback(hqspi);
AnnaBridge	189:f392fc9709a3	769	#else
AnnaBridge	189:f392fc9709a3	770	HAL_QSPI_TimeOutCallback(hqspi);
AnnaBridge	189:f392fc9709a3	771	#endif
AnnaBridge	189:f392fc9709a3	772	}
AnnaBridge	189:f392fc9709a3	773	else
AnnaBridge	189:f392fc9709a3	774	{
AnnaBridge	189:f392fc9709a3	775	/* Nothing to do */
AnnaBridge	189:f392fc9709a3	776	}
AnnaBridge	189:f392fc9709a3	777	}
AnnaBridge	189:f392fc9709a3	778
AnnaBridge	189:f392fc9709a3	779	/**
AnnaBridge	189:f392fc9709a3	780	* @brief Set the command configuration.
AnnaBridge	189:f392fc9709a3	781	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	782	* @param cmd : structure that contains the command configuration information
AnnaBridge	189:f392fc9709a3	783	* @param Timeout : Timeout duration
AnnaBridge	189:f392fc9709a3	784	* @note This function is used only in Indirect Read or Write Modes
AnnaBridge	189:f392fc9709a3	785	* @retval HAL status
AnnaBridge	189:f392fc9709a3	786	*/
AnnaBridge	189:f392fc9709a3	787	HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout)
AnnaBridge	189:f392fc9709a3	788	{
AnnaBridge	189:f392fc9709a3	789	HAL_StatusTypeDef status;
AnnaBridge	189:f392fc9709a3	790	uint32_t tickstart = HAL_GetTick();
AnnaBridge	189:f392fc9709a3	791
AnnaBridge	189:f392fc9709a3	792	/* Check the parameters */
AnnaBridge	189:f392fc9709a3	793	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
AnnaBridge	189:f392fc9709a3	794	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
AnnaBridge	189:f392fc9709a3	795	{
AnnaBridge	189:f392fc9709a3	796	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
AnnaBridge	189:f392fc9709a3	797	}
AnnaBridge	189:f392fc9709a3	798
AnnaBridge	189:f392fc9709a3	799	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
AnnaBridge	189:f392fc9709a3	800	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
AnnaBridge	189:f392fc9709a3	801	{
AnnaBridge	189:f392fc9709a3	802	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
AnnaBridge	189:f392fc9709a3	803	}
AnnaBridge	189:f392fc9709a3	804
AnnaBridge	189:f392fc9709a3	805	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
AnnaBridge	189:f392fc9709a3	806	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
AnnaBridge	189:f392fc9709a3	807	{
AnnaBridge	189:f392fc9709a3	808	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
AnnaBridge	189:f392fc9709a3	809	}
AnnaBridge	189:f392fc9709a3	810
AnnaBridge	189:f392fc9709a3	811	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
AnnaBridge	189:f392fc9709a3	812	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
AnnaBridge	189:f392fc9709a3	813
AnnaBridge	189:f392fc9709a3	814	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
AnnaBridge	189:f392fc9709a3	815	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
AnnaBridge	189:f392fc9709a3	816	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
AnnaBridge	189:f392fc9709a3	817
AnnaBridge	189:f392fc9709a3	818	/* Process locked */
AnnaBridge	189:f392fc9709a3	819	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	820
AnnaBridge	189:f392fc9709a3	821	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	822	{
AnnaBridge	189:f392fc9709a3	823	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	824
AnnaBridge	189:f392fc9709a3	825	/* Update QSPI state */
AnnaBridge	189:f392fc9709a3	826	hqspi->State = HAL_QSPI_STATE_BUSY;
AnnaBridge	189:f392fc9709a3	827
AnnaBridge	189:f392fc9709a3	828	/* Wait till BUSY flag reset */
AnnaBridge	189:f392fc9709a3	829	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
AnnaBridge	189:f392fc9709a3	830
AnnaBridge	189:f392fc9709a3	831	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	832	{
AnnaBridge	189:f392fc9709a3	833	/* Call the configuration function */
AnnaBridge	189:f392fc9709a3	834	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
AnnaBridge	189:f392fc9709a3	835
AnnaBridge	189:f392fc9709a3	836	if (cmd->DataMode == QSPI_DATA_NONE)
AnnaBridge	189:f392fc9709a3	837	{
AnnaBridge	189:f392fc9709a3	838	/* When there is no data phase, the transfer start as soon as the configuration is done
AnnaBridge	189:f392fc9709a3	839	so wait until TC flag is set to go back in idle state */
AnnaBridge	189:f392fc9709a3	840	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
AnnaBridge	189:f392fc9709a3	841
AnnaBridge	189:f392fc9709a3	842	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	843	{
AnnaBridge	189:f392fc9709a3	844	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
AnnaBridge	189:f392fc9709a3	845
AnnaBridge	189:f392fc9709a3	846	/* Update QSPI state */
AnnaBridge	189:f392fc9709a3	847	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	848	}
AnnaBridge	189:f392fc9709a3	849
AnnaBridge	189:f392fc9709a3	850	}
AnnaBridge	189:f392fc9709a3	851	else
AnnaBridge	189:f392fc9709a3	852	{
AnnaBridge	189:f392fc9709a3	853	/* Update QSPI state */
AnnaBridge	189:f392fc9709a3	854	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	855	}
AnnaBridge	189:f392fc9709a3	856	}
AnnaBridge	189:f392fc9709a3	857	}
AnnaBridge	189:f392fc9709a3	858	else
AnnaBridge	189:f392fc9709a3	859	{
AnnaBridge	189:f392fc9709a3	860	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	861	}
AnnaBridge	189:f392fc9709a3	862
AnnaBridge	189:f392fc9709a3	863	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	864	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	865
AnnaBridge	189:f392fc9709a3	866	/* Return function status */
AnnaBridge	189:f392fc9709a3	867	return status;
AnnaBridge	189:f392fc9709a3	868	}
AnnaBridge	189:f392fc9709a3	869
AnnaBridge	189:f392fc9709a3	870	/**
AnnaBridge	189:f392fc9709a3	871	* @brief Set the command configuration in interrupt mode.
AnnaBridge	189:f392fc9709a3	872	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	873	* @param cmd : structure that contains the command configuration information
AnnaBridge	189:f392fc9709a3	874	* @note This function is used only in Indirect Read or Write Modes
AnnaBridge	189:f392fc9709a3	875	* @retval HAL status
AnnaBridge	189:f392fc9709a3	876	*/
AnnaBridge	189:f392fc9709a3	877	HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd)
AnnaBridge	189:f392fc9709a3	878	{
AnnaBridge	189:f392fc9709a3	879	HAL_StatusTypeDef status;
AnnaBridge	189:f392fc9709a3	880	uint32_t tickstart = HAL_GetTick();
AnnaBridge	189:f392fc9709a3	881
AnnaBridge	189:f392fc9709a3	882	/* Check the parameters */
AnnaBridge	189:f392fc9709a3	883	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
AnnaBridge	189:f392fc9709a3	884	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
AnnaBridge	189:f392fc9709a3	885	{
AnnaBridge	189:f392fc9709a3	886	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
AnnaBridge	189:f392fc9709a3	887	}
AnnaBridge	189:f392fc9709a3	888
AnnaBridge	189:f392fc9709a3	889	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
AnnaBridge	189:f392fc9709a3	890	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
AnnaBridge	189:f392fc9709a3	891	{
AnnaBridge	189:f392fc9709a3	892	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
AnnaBridge	189:f392fc9709a3	893	}
AnnaBridge	189:f392fc9709a3	894
AnnaBridge	189:f392fc9709a3	895	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
AnnaBridge	189:f392fc9709a3	896	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
AnnaBridge	189:f392fc9709a3	897	{
AnnaBridge	189:f392fc9709a3	898	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
AnnaBridge	189:f392fc9709a3	899	}
AnnaBridge	189:f392fc9709a3	900
AnnaBridge	189:f392fc9709a3	901	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
AnnaBridge	189:f392fc9709a3	902	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
AnnaBridge	189:f392fc9709a3	903
AnnaBridge	189:f392fc9709a3	904	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
AnnaBridge	189:f392fc9709a3	905	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
AnnaBridge	189:f392fc9709a3	906	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
AnnaBridge	189:f392fc9709a3	907
AnnaBridge	189:f392fc9709a3	908	/* Process locked */
AnnaBridge	189:f392fc9709a3	909	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	910
AnnaBridge	189:f392fc9709a3	911	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	912	{
AnnaBridge	189:f392fc9709a3	913	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	914
AnnaBridge	189:f392fc9709a3	915	/* Update QSPI state */
AnnaBridge	189:f392fc9709a3	916	hqspi->State = HAL_QSPI_STATE_BUSY;
AnnaBridge	189:f392fc9709a3	917
AnnaBridge	189:f392fc9709a3	918	/* Wait till BUSY flag reset */
AnnaBridge	189:f392fc9709a3	919	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
AnnaBridge	189:f392fc9709a3	920
AnnaBridge	189:f392fc9709a3	921	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	922	{
AnnaBridge	189:f392fc9709a3	923	if (cmd->DataMode == QSPI_DATA_NONE)
AnnaBridge	189:f392fc9709a3	924	{
AnnaBridge	189:f392fc9709a3	925	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	926	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
AnnaBridge	189:f392fc9709a3	927	}
AnnaBridge	189:f392fc9709a3	928
AnnaBridge	189:f392fc9709a3	929	/* Call the configuration function */
AnnaBridge	189:f392fc9709a3	930	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
AnnaBridge	189:f392fc9709a3	931
AnnaBridge	189:f392fc9709a3	932	if (cmd->DataMode == QSPI_DATA_NONE)
AnnaBridge	189:f392fc9709a3	933	{
AnnaBridge	189:f392fc9709a3	934	/* When there is no data phase, the transfer start as soon as the configuration is done
AnnaBridge	189:f392fc9709a3	935	so activate TC and TE interrupts */
AnnaBridge	189:f392fc9709a3	936	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	937	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	938
AnnaBridge	189:f392fc9709a3	939	/* Enable the QSPI Transfer Error Interrupt */
AnnaBridge	189:f392fc9709a3	940	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_TC);
AnnaBridge	189:f392fc9709a3	941	}
AnnaBridge	189:f392fc9709a3	942	else
AnnaBridge	189:f392fc9709a3	943	{
AnnaBridge	189:f392fc9709a3	944	/* Update QSPI state */
AnnaBridge	189:f392fc9709a3	945	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	946
AnnaBridge	189:f392fc9709a3	947	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	948	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	949	}
AnnaBridge	189:f392fc9709a3	950	}
AnnaBridge	189:f392fc9709a3	951	else
AnnaBridge	189:f392fc9709a3	952	{
AnnaBridge	189:f392fc9709a3	953	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	954	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	955	}
AnnaBridge	189:f392fc9709a3	956	}
AnnaBridge	189:f392fc9709a3	957	else
AnnaBridge	189:f392fc9709a3	958	{
AnnaBridge	189:f392fc9709a3	959	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	960
AnnaBridge	189:f392fc9709a3	961	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	962	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	963	}
AnnaBridge	189:f392fc9709a3	964
AnnaBridge	189:f392fc9709a3	965	/* Return function status */
AnnaBridge	189:f392fc9709a3	966	return status;
AnnaBridge	189:f392fc9709a3	967	}
AnnaBridge	189:f392fc9709a3	968
AnnaBridge	189:f392fc9709a3	969	/**
AnnaBridge	189:f392fc9709a3	970	* @brief Transmit an amount of data in blocking mode.
AnnaBridge	189:f392fc9709a3	971	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	972	* @param pData: pointer to data buffer
AnnaBridge	189:f392fc9709a3	973	* @param Timeout : Timeout duration
AnnaBridge	189:f392fc9709a3	974	* @note This function is used only in Indirect Write Mode
AnnaBridge	189:f392fc9709a3	975	* @retval HAL status
AnnaBridge	189:f392fc9709a3	976	*/
AnnaBridge	189:f392fc9709a3	977	HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
AnnaBridge	189:f392fc9709a3	978	{
AnnaBridge	189:f392fc9709a3	979	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	980	uint32_t tickstart = HAL_GetTick();
AnnaBridge	189:f392fc9709a3	981	__IO uint32_t *data_reg = &hqspi->Instance->DR;
AnnaBridge	189:f392fc9709a3	982
AnnaBridge	189:f392fc9709a3	983	/* Process locked */
AnnaBridge	189:f392fc9709a3	984	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	985
AnnaBridge	189:f392fc9709a3	986	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	987	{
AnnaBridge	189:f392fc9709a3	988	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	989
AnnaBridge	189:f392fc9709a3	990	if(pData != NULL )
AnnaBridge	189:f392fc9709a3	991	{
AnnaBridge	189:f392fc9709a3	992	/* Update state */
AnnaBridge	189:f392fc9709a3	993	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
AnnaBridge	189:f392fc9709a3	994
AnnaBridge	189:f392fc9709a3	995	/* Configure counters and size of the handle */
AnnaBridge	189:f392fc9709a3	996	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	997	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	998	hqspi->pTxBuffPtr = pData;
AnnaBridge	189:f392fc9709a3	999
AnnaBridge	189:f392fc9709a3	1000	/* Configure QSPI: CCR register with functional as indirect write */
AnnaBridge	189:f392fc9709a3	1001	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
AnnaBridge	189:f392fc9709a3	1002
AnnaBridge	189:f392fc9709a3	1003	while(hqspi->TxXferCount > 0U)
AnnaBridge	189:f392fc9709a3	1004	{
AnnaBridge	189:f392fc9709a3	1005	/* Wait until FT flag is set to send data */
AnnaBridge	189:f392fc9709a3	1006	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
AnnaBridge	189:f392fc9709a3	1007
AnnaBridge	189:f392fc9709a3	1008	if (status != HAL_OK)
AnnaBridge	189:f392fc9709a3	1009	{
AnnaBridge	189:f392fc9709a3	1010	break;
AnnaBridge	189:f392fc9709a3	1011	}
AnnaBridge	189:f392fc9709a3	1012
AnnaBridge	189:f392fc9709a3	1013	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr;
AnnaBridge	189:f392fc9709a3	1014	hqspi->pTxBuffPtr++;
AnnaBridge	189:f392fc9709a3	1015	hqspi->TxXferCount--;
AnnaBridge	189:f392fc9709a3	1016	}
AnnaBridge	189:f392fc9709a3	1017
AnnaBridge	189:f392fc9709a3	1018	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	1019	{
AnnaBridge	189:f392fc9709a3	1020	/* Wait until TC flag is set to go back in idle state */
AnnaBridge	189:f392fc9709a3	1021	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
AnnaBridge	189:f392fc9709a3	1022
AnnaBridge	189:f392fc9709a3	1023	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	1024	{
AnnaBridge	189:f392fc9709a3	1025	/* Clear Transfer Complete bit */
AnnaBridge	189:f392fc9709a3	1026	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
AnnaBridge	189:f392fc9709a3	1027
AnnaBridge	189:f392fc9709a3	1028	}
AnnaBridge	189:f392fc9709a3	1029	}
AnnaBridge	189:f392fc9709a3	1030
AnnaBridge	189:f392fc9709a3	1031	/* Update QSPI state */
AnnaBridge	189:f392fc9709a3	1032	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	1033	}
AnnaBridge	189:f392fc9709a3	1034	else
AnnaBridge	189:f392fc9709a3	1035	{
AnnaBridge	189:f392fc9709a3	1036	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
AnnaBridge	189:f392fc9709a3	1037	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1038	}
AnnaBridge	189:f392fc9709a3	1039	}
AnnaBridge	189:f392fc9709a3	1040	else
AnnaBridge	189:f392fc9709a3	1041	{
AnnaBridge	189:f392fc9709a3	1042	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	1043	}
AnnaBridge	189:f392fc9709a3	1044
AnnaBridge	189:f392fc9709a3	1045	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1046	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1047
AnnaBridge	189:f392fc9709a3	1048	return status;
AnnaBridge	189:f392fc9709a3	1049	}
AnnaBridge	189:f392fc9709a3	1050
AnnaBridge	189:f392fc9709a3	1051
AnnaBridge	189:f392fc9709a3	1052	/**
AnnaBridge	189:f392fc9709a3	1053	* @brief Receive an amount of data in blocking mode.
AnnaBridge	189:f392fc9709a3	1054	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1055	* @param pData: pointer to data buffer
AnnaBridge	189:f392fc9709a3	1056	* @param Timeout : Timeout duration
AnnaBridge	189:f392fc9709a3	1057	* @note This function is used only in Indirect Read Mode
AnnaBridge	189:f392fc9709a3	1058	* @retval HAL status
AnnaBridge	189:f392fc9709a3	1059	*/
AnnaBridge	189:f392fc9709a3	1060	HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
AnnaBridge	189:f392fc9709a3	1061	{
AnnaBridge	189:f392fc9709a3	1062	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	1063	uint32_t tickstart = HAL_GetTick();
AnnaBridge	189:f392fc9709a3	1064	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
AnnaBridge	189:f392fc9709a3	1065	__IO uint32_t *data_reg = &hqspi->Instance->DR;
AnnaBridge	189:f392fc9709a3	1066
AnnaBridge	189:f392fc9709a3	1067	/* Process locked */
AnnaBridge	189:f392fc9709a3	1068	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1069
AnnaBridge	189:f392fc9709a3	1070	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	1071	{
AnnaBridge	189:f392fc9709a3	1072	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	1073
AnnaBridge	189:f392fc9709a3	1074	if(pData != NULL )
AnnaBridge	189:f392fc9709a3	1075	{
AnnaBridge	189:f392fc9709a3	1076	/* Update state */
AnnaBridge	189:f392fc9709a3	1077	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
AnnaBridge	189:f392fc9709a3	1078
AnnaBridge	189:f392fc9709a3	1079	/* Configure counters and size of the handle */
AnnaBridge	189:f392fc9709a3	1080	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	1081	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	1082	hqspi->pRxBuffPtr = pData;
AnnaBridge	189:f392fc9709a3	1083
AnnaBridge	189:f392fc9709a3	1084	/* Configure QSPI: CCR register with functional as indirect read */
AnnaBridge	189:f392fc9709a3	1085	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
AnnaBridge	189:f392fc9709a3	1086
AnnaBridge	189:f392fc9709a3	1087	/* Start the transfer by re-writing the address in AR register */
AnnaBridge	189:f392fc9709a3	1088	WRITE_REG(hqspi->Instance->AR, addr_reg);
AnnaBridge	189:f392fc9709a3	1089
AnnaBridge	189:f392fc9709a3	1090	while(hqspi->RxXferCount > 0U)
AnnaBridge	189:f392fc9709a3	1091	{
AnnaBridge	189:f392fc9709a3	1092	/* Wait until FT or TC flag is set to read received data */
AnnaBridge	189:f392fc9709a3	1093	status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT \| QSPI_FLAG_TC), SET, tickstart, Timeout);
AnnaBridge	189:f392fc9709a3	1094
AnnaBridge	189:f392fc9709a3	1095	if (status != HAL_OK)
AnnaBridge	189:f392fc9709a3	1096	{
AnnaBridge	189:f392fc9709a3	1097	break;
AnnaBridge	189:f392fc9709a3	1098	}
AnnaBridge	189:f392fc9709a3	1099
AnnaBridge	189:f392fc9709a3	1100	hqspi->pRxBuffPtr = (__IO uint8_t *)data_reg;
AnnaBridge	189:f392fc9709a3	1101	hqspi->pRxBuffPtr++;
AnnaBridge	189:f392fc9709a3	1102	hqspi->RxXferCount--;
AnnaBridge	189:f392fc9709a3	1103	}
AnnaBridge	189:f392fc9709a3	1104
AnnaBridge	189:f392fc9709a3	1105	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	1106	{
AnnaBridge	189:f392fc9709a3	1107	/* Wait until TC flag is set to go back in idle state */
AnnaBridge	189:f392fc9709a3	1108	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
AnnaBridge	189:f392fc9709a3	1109
AnnaBridge	189:f392fc9709a3	1110	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	1111	{
AnnaBridge	189:f392fc9709a3	1112	/* Clear Transfer Complete bit */
AnnaBridge	189:f392fc9709a3	1113	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
AnnaBridge	189:f392fc9709a3	1114	}
AnnaBridge	189:f392fc9709a3	1115	}
AnnaBridge	189:f392fc9709a3	1116
AnnaBridge	189:f392fc9709a3	1117	/* Update QSPI state */
AnnaBridge	189:f392fc9709a3	1118	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	1119	}
AnnaBridge	189:f392fc9709a3	1120	else
AnnaBridge	189:f392fc9709a3	1121	{
AnnaBridge	189:f392fc9709a3	1122	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
AnnaBridge	189:f392fc9709a3	1123	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1124	}
AnnaBridge	189:f392fc9709a3	1125	}
AnnaBridge	189:f392fc9709a3	1126	else
AnnaBridge	189:f392fc9709a3	1127	{
AnnaBridge	189:f392fc9709a3	1128	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	1129	}
AnnaBridge	189:f392fc9709a3	1130
AnnaBridge	189:f392fc9709a3	1131	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1132	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1133
AnnaBridge	189:f392fc9709a3	1134	return status;
AnnaBridge	189:f392fc9709a3	1135	}
AnnaBridge	189:f392fc9709a3	1136
AnnaBridge	189:f392fc9709a3	1137	/**
AnnaBridge	189:f392fc9709a3	1138	* @brief Send an amount of data in non-blocking mode with interrupt.
AnnaBridge	189:f392fc9709a3	1139	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1140	* @param pData: pointer to data buffer
AnnaBridge	189:f392fc9709a3	1141	* @note This function is used only in Indirect Write Mode
AnnaBridge	189:f392fc9709a3	1142	* @retval HAL status
AnnaBridge	189:f392fc9709a3	1143	*/
AnnaBridge	189:f392fc9709a3	1144	HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
AnnaBridge	189:f392fc9709a3	1145	{
AnnaBridge	189:f392fc9709a3	1146	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	1147
AnnaBridge	189:f392fc9709a3	1148	/* Process locked */
AnnaBridge	189:f392fc9709a3	1149	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1150
AnnaBridge	189:f392fc9709a3	1151	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	1152	{
AnnaBridge	189:f392fc9709a3	1153	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	1154
AnnaBridge	189:f392fc9709a3	1155	if(pData != NULL )
AnnaBridge	189:f392fc9709a3	1156	{
AnnaBridge	189:f392fc9709a3	1157	/* Update state */
AnnaBridge	189:f392fc9709a3	1158	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
AnnaBridge	189:f392fc9709a3	1159
AnnaBridge	189:f392fc9709a3	1160	/* Configure counters and size of the handle */
AnnaBridge	189:f392fc9709a3	1161	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	1162	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	1163	hqspi->pTxBuffPtr = pData;
AnnaBridge	189:f392fc9709a3	1164
AnnaBridge	189:f392fc9709a3	1165	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	1166	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
AnnaBridge	189:f392fc9709a3	1167
AnnaBridge	189:f392fc9709a3	1168	/* Configure QSPI: CCR register with functional as indirect write */
AnnaBridge	189:f392fc9709a3	1169	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
AnnaBridge	189:f392fc9709a3	1170
AnnaBridge	189:f392fc9709a3	1171	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1172	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1173
AnnaBridge	189:f392fc9709a3	1174	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
AnnaBridge	189:f392fc9709a3	1175	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
AnnaBridge	189:f392fc9709a3	1176	}
AnnaBridge	189:f392fc9709a3	1177	else
AnnaBridge	189:f392fc9709a3	1178	{
AnnaBridge	189:f392fc9709a3	1179	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
AnnaBridge	189:f392fc9709a3	1180	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1181
AnnaBridge	189:f392fc9709a3	1182	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1183	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1184	}
AnnaBridge	189:f392fc9709a3	1185	}
AnnaBridge	189:f392fc9709a3	1186	else
AnnaBridge	189:f392fc9709a3	1187	{
AnnaBridge	189:f392fc9709a3	1188	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	1189
AnnaBridge	189:f392fc9709a3	1190	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1191	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1192	}
AnnaBridge	189:f392fc9709a3	1193
AnnaBridge	189:f392fc9709a3	1194	return status;
AnnaBridge	189:f392fc9709a3	1195	}
AnnaBridge	189:f392fc9709a3	1196
AnnaBridge	189:f392fc9709a3	1197	/**
AnnaBridge	189:f392fc9709a3	1198	* @brief Receive an amount of data in non-blocking mode with interrupt.
AnnaBridge	189:f392fc9709a3	1199	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1200	* @param pData: pointer to data buffer
AnnaBridge	189:f392fc9709a3	1201	* @note This function is used only in Indirect Read Mode
AnnaBridge	189:f392fc9709a3	1202	* @retval HAL status
AnnaBridge	189:f392fc9709a3	1203	*/
AnnaBridge	189:f392fc9709a3	1204	HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
AnnaBridge	189:f392fc9709a3	1205	{
AnnaBridge	189:f392fc9709a3	1206	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	1207	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
AnnaBridge	189:f392fc9709a3	1208
AnnaBridge	189:f392fc9709a3	1209	/* Process locked */
AnnaBridge	189:f392fc9709a3	1210	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1211
AnnaBridge	189:f392fc9709a3	1212	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	1213	{
AnnaBridge	189:f392fc9709a3	1214	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	1215
AnnaBridge	189:f392fc9709a3	1216	if(pData != NULL )
AnnaBridge	189:f392fc9709a3	1217	{
AnnaBridge	189:f392fc9709a3	1218	/* Update state */
AnnaBridge	189:f392fc9709a3	1219	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
AnnaBridge	189:f392fc9709a3	1220
AnnaBridge	189:f392fc9709a3	1221	/* Configure counters and size of the handle */
AnnaBridge	189:f392fc9709a3	1222	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	1223	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	1224	hqspi->pRxBuffPtr = pData;
AnnaBridge	189:f392fc9709a3	1225
AnnaBridge	189:f392fc9709a3	1226	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	1227	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
AnnaBridge	189:f392fc9709a3	1228
AnnaBridge	189:f392fc9709a3	1229	/* Configure QSPI: CCR register with functional as indirect read */
AnnaBridge	189:f392fc9709a3	1230	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
AnnaBridge	189:f392fc9709a3	1231
AnnaBridge	189:f392fc9709a3	1232	/* Start the transfer by re-writing the address in AR register */
AnnaBridge	189:f392fc9709a3	1233	WRITE_REG(hqspi->Instance->AR, addr_reg);
AnnaBridge	189:f392fc9709a3	1234
AnnaBridge	189:f392fc9709a3	1235	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1236	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1237
AnnaBridge	189:f392fc9709a3	1238	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
AnnaBridge	189:f392fc9709a3	1239	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
AnnaBridge	189:f392fc9709a3	1240	}
AnnaBridge	189:f392fc9709a3	1241	else
AnnaBridge	189:f392fc9709a3	1242	{
AnnaBridge	189:f392fc9709a3	1243	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
AnnaBridge	189:f392fc9709a3	1244	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1245
AnnaBridge	189:f392fc9709a3	1246	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1247	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1248	}
AnnaBridge	189:f392fc9709a3	1249	}
AnnaBridge	189:f392fc9709a3	1250	else
AnnaBridge	189:f392fc9709a3	1251	{
AnnaBridge	189:f392fc9709a3	1252	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	1253
AnnaBridge	189:f392fc9709a3	1254	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1255	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1256	}
AnnaBridge	189:f392fc9709a3	1257
AnnaBridge	189:f392fc9709a3	1258	return status;
AnnaBridge	189:f392fc9709a3	1259	}
AnnaBridge	189:f392fc9709a3	1260
AnnaBridge	189:f392fc9709a3	1261	/**
AnnaBridge	189:f392fc9709a3	1262	* @brief Send an amount of data in non-blocking mode with DMA.
AnnaBridge	189:f392fc9709a3	1263	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1264	* @param pData: pointer to data buffer
AnnaBridge	189:f392fc9709a3	1265	* @note This function is used only in Indirect Write Mode
AnnaBridge	189:f392fc9709a3	1266	* @note If MDMA peripheral access is configured as halfword, the number
AnnaBridge	189:f392fc9709a3	1267	* of data and the fifo threshold should be aligned on halfword
AnnaBridge	189:f392fc9709a3	1268	* @note If MDMA peripheral access is configured as word, the number
AnnaBridge	189:f392fc9709a3	1269	* of data and the fifo threshold should be aligned on word
AnnaBridge	189:f392fc9709a3	1270	* @retval HAL status
AnnaBridge	189:f392fc9709a3	1271	*/
AnnaBridge	189:f392fc9709a3	1272	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
AnnaBridge	189:f392fc9709a3	1273	{
AnnaBridge	189:f392fc9709a3	1274	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	1275
AnnaBridge	189:f392fc9709a3	1276	/* Process locked */
AnnaBridge	189:f392fc9709a3	1277	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1278
AnnaBridge	189:f392fc9709a3	1279	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	1280	{
AnnaBridge	189:f392fc9709a3	1281	/* Clear the error code */
AnnaBridge	189:f392fc9709a3	1282	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	1283
AnnaBridge	189:f392fc9709a3	1284	if(pData != NULL )
AnnaBridge	189:f392fc9709a3	1285	{
AnnaBridge	189:f392fc9709a3	1286
AnnaBridge	189:f392fc9709a3	1287	/* Update state */
AnnaBridge	189:f392fc9709a3	1288	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
AnnaBridge	189:f392fc9709a3	1289
AnnaBridge	189:f392fc9709a3	1290	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	1291	__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE \| QSPI_FLAG_TC));
AnnaBridge	189:f392fc9709a3	1292
AnnaBridge	189:f392fc9709a3	1293	/* Configure counters and size of the handle */
AnnaBridge	189:f392fc9709a3	1294	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	1295	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	1296	hqspi->pTxBuffPtr = pData;
AnnaBridge	189:f392fc9709a3	1297
AnnaBridge	189:f392fc9709a3	1298	/* Configure QSPI: CCR register with functional mode as indirect write */
AnnaBridge	189:f392fc9709a3	1299	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
AnnaBridge	189:f392fc9709a3	1300
AnnaBridge	189:f392fc9709a3	1301	/* Set the QSPI MDMA transfer complete callback */
AnnaBridge	189:f392fc9709a3	1302	hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
AnnaBridge	189:f392fc9709a3	1303
AnnaBridge	189:f392fc9709a3	1304	/* Set the MDMA error callback */
AnnaBridge	189:f392fc9709a3	1305	hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
AnnaBridge	189:f392fc9709a3	1306
AnnaBridge	189:f392fc9709a3	1307	/* Clear the MDMA abort callback */
AnnaBridge	189:f392fc9709a3	1308	hqspi->hmdma->XferAbortCallback = NULL;
AnnaBridge	189:f392fc9709a3	1309
AnnaBridge	189:f392fc9709a3	1310	/* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
AnnaBridge	189:f392fc9709a3	1311	MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC \| MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
AnnaBridge	189:f392fc9709a3	1312
AnnaBridge	189:f392fc9709a3	1313	/* Update MDMA configuration with the correct SourceInc field for Write operation */
AnnaBridge	189:f392fc9709a3	1314	if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
AnnaBridge	189:f392fc9709a3	1315	{
AnnaBridge	189:f392fc9709a3	1316	MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC \| MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
AnnaBridge	189:f392fc9709a3	1317	}
AnnaBridge	189:f392fc9709a3	1318	else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
AnnaBridge	189:f392fc9709a3	1319	{
AnnaBridge	189:f392fc9709a3	1320	MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC \| MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
AnnaBridge	189:f392fc9709a3	1321	}
AnnaBridge	189:f392fc9709a3	1322	else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
AnnaBridge	189:f392fc9709a3	1323	{
AnnaBridge	189:f392fc9709a3	1324	MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC \| MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
AnnaBridge	189:f392fc9709a3	1325	}
AnnaBridge	189:f392fc9709a3	1326	else
AnnaBridge	189:f392fc9709a3	1327	{
AnnaBridge	189:f392fc9709a3	1328	/* in case of incorrect source data size */
AnnaBridge	189:f392fc9709a3	1329	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
AnnaBridge	189:f392fc9709a3	1330	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1331	}
AnnaBridge	189:f392fc9709a3	1332
AnnaBridge	189:f392fc9709a3	1333	/* Enable the QSPI transfer error and complete Interrupts : Workaround for QSPI low kernel clock frequency */
AnnaBridge	189:f392fc9709a3	1334	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \|QSPI_IT_TC);
AnnaBridge	189:f392fc9709a3	1335
AnnaBridge	189:f392fc9709a3	1336	/* Enable the QSPI transmit MDMA */
AnnaBridge	189:f392fc9709a3	1337	if(HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
AnnaBridge	189:f392fc9709a3	1338	{
AnnaBridge	189:f392fc9709a3	1339	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1340	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1341
AnnaBridge	189:f392fc9709a3	1342	/* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
AnnaBridge	189:f392fc9709a3	1343	}
AnnaBridge	189:f392fc9709a3	1344	}
AnnaBridge	189:f392fc9709a3	1345	else
AnnaBridge	189:f392fc9709a3	1346	{
AnnaBridge	189:f392fc9709a3	1347	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
AnnaBridge	189:f392fc9709a3	1348	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1349
AnnaBridge	189:f392fc9709a3	1350	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1351	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1352	}
AnnaBridge	189:f392fc9709a3	1353	}
AnnaBridge	189:f392fc9709a3	1354	else
AnnaBridge	189:f392fc9709a3	1355	{
AnnaBridge	189:f392fc9709a3	1356	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	1357
AnnaBridge	189:f392fc9709a3	1358	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1359	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1360	}
AnnaBridge	189:f392fc9709a3	1361
AnnaBridge	189:f392fc9709a3	1362	return status;
AnnaBridge	189:f392fc9709a3	1363	}
AnnaBridge	189:f392fc9709a3	1364
AnnaBridge	189:f392fc9709a3	1365	/**
AnnaBridge	189:f392fc9709a3	1366	* @brief Receive an amount of data in non-blocking mode with DMA.
AnnaBridge	189:f392fc9709a3	1367	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1368	* @param pData: pointer to data buffer.
AnnaBridge	189:f392fc9709a3	1369	* @note This function is used only in Indirect Read Mode
AnnaBridge	189:f392fc9709a3	1370	* @retval HAL status
AnnaBridge	189:f392fc9709a3	1371	*/
AnnaBridge	189:f392fc9709a3	1372	HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
AnnaBridge	189:f392fc9709a3	1373	{
AnnaBridge	189:f392fc9709a3	1374	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	1375	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
AnnaBridge	189:f392fc9709a3	1376
AnnaBridge	189:f392fc9709a3	1377	/* Process locked */
AnnaBridge	189:f392fc9709a3	1378	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1379
AnnaBridge	189:f392fc9709a3	1380	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	1381	{
AnnaBridge	189:f392fc9709a3	1382	/* Clear the error code */
AnnaBridge	189:f392fc9709a3	1383	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	1384
AnnaBridge	189:f392fc9709a3	1385	if(pData != NULL )
AnnaBridge	189:f392fc9709a3	1386	{
AnnaBridge	189:f392fc9709a3	1387
AnnaBridge	189:f392fc9709a3	1388	/* Update state */
AnnaBridge	189:f392fc9709a3	1389	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
AnnaBridge	189:f392fc9709a3	1390
AnnaBridge	189:f392fc9709a3	1391	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	1392	__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE \| QSPI_FLAG_TC));
AnnaBridge	189:f392fc9709a3	1393
AnnaBridge	189:f392fc9709a3	1394	/* Configure counters and size of the handle */
AnnaBridge	189:f392fc9709a3	1395	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	1396	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
AnnaBridge	189:f392fc9709a3	1397	hqspi->pRxBuffPtr = pData;
AnnaBridge	189:f392fc9709a3	1398
AnnaBridge	189:f392fc9709a3	1399	/* Set the QSPI DMA transfer complete callback */
AnnaBridge	189:f392fc9709a3	1400	hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
AnnaBridge	189:f392fc9709a3	1401
AnnaBridge	189:f392fc9709a3	1402	/* Set the MDMA error callback */
AnnaBridge	189:f392fc9709a3	1403	hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
AnnaBridge	189:f392fc9709a3	1404
AnnaBridge	189:f392fc9709a3	1405	/* Clear the MDMA abort callback */
AnnaBridge	189:f392fc9709a3	1406	hqspi->hmdma->XferAbortCallback = NULL;
AnnaBridge	189:f392fc9709a3	1407
AnnaBridge	189:f392fc9709a3	1408
AnnaBridge	189:f392fc9709a3	1409	/* QSPI need to be configured to indirect mode before starting
AnnaBridge	189:f392fc9709a3	1410	the MDMA to avoid primatury triggering for the MDMA transfert */
AnnaBridge	189:f392fc9709a3	1411	/* Configure QSPI: CCR register with functional as indirect read */
AnnaBridge	189:f392fc9709a3	1412	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
AnnaBridge	189:f392fc9709a3	1413
AnnaBridge	189:f392fc9709a3	1414	/* Start the transfer by re-writing the address in AR register */
AnnaBridge	189:f392fc9709a3	1415	WRITE_REG(hqspi->Instance->AR, addr_reg);
AnnaBridge	189:f392fc9709a3	1416
AnnaBridge	189:f392fc9709a3	1417	/* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Increment to disable */
AnnaBridge	189:f392fc9709a3	1418	MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC \| MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
AnnaBridge	189:f392fc9709a3	1419
AnnaBridge	189:f392fc9709a3	1420	/* Update MDMA configuration with the correct DestinationInc field for read operation */
AnnaBridge	189:f392fc9709a3	1421	if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
AnnaBridge	189:f392fc9709a3	1422	{
AnnaBridge	189:f392fc9709a3	1423	MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC \| MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE);
AnnaBridge	189:f392fc9709a3	1424	}
AnnaBridge	189:f392fc9709a3	1425	else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD)
AnnaBridge	189:f392fc9709a3	1426	{
AnnaBridge	189:f392fc9709a3	1427	MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC \| MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD);
AnnaBridge	189:f392fc9709a3	1428	}
AnnaBridge	189:f392fc9709a3	1429	else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD)
AnnaBridge	189:f392fc9709a3	1430	{
AnnaBridge	189:f392fc9709a3	1431	MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC \| MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
AnnaBridge	189:f392fc9709a3	1432	}
AnnaBridge	189:f392fc9709a3	1433	else
AnnaBridge	189:f392fc9709a3	1434	{
AnnaBridge	189:f392fc9709a3	1435	/* in case of incorrect destination data size */
AnnaBridge	189:f392fc9709a3	1436	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
AnnaBridge	189:f392fc9709a3	1437	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1438	}
AnnaBridge	189:f392fc9709a3	1439
AnnaBridge	189:f392fc9709a3	1440	/* Enable the MDMA */
AnnaBridge	189:f392fc9709a3	1441	if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
AnnaBridge	189:f392fc9709a3	1442	{
AnnaBridge	189:f392fc9709a3	1443	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1444	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1445
AnnaBridge	189:f392fc9709a3	1446	/* Enable the QSPI transfer error Interrupt */
AnnaBridge	189:f392fc9709a3	1447	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
AnnaBridge	189:f392fc9709a3	1448
AnnaBridge	189:f392fc9709a3	1449	/* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
AnnaBridge	189:f392fc9709a3	1450	}
AnnaBridge	189:f392fc9709a3	1451	}
AnnaBridge	189:f392fc9709a3	1452	else
AnnaBridge	189:f392fc9709a3	1453	{
AnnaBridge	189:f392fc9709a3	1454	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1455
AnnaBridge	189:f392fc9709a3	1456	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1457	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1458	}
AnnaBridge	189:f392fc9709a3	1459	}
AnnaBridge	189:f392fc9709a3	1460	else
AnnaBridge	189:f392fc9709a3	1461	{
AnnaBridge	189:f392fc9709a3	1462	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	1463
AnnaBridge	189:f392fc9709a3	1464	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1465	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1466	}
AnnaBridge	189:f392fc9709a3	1467
AnnaBridge	189:f392fc9709a3	1468	return status;
AnnaBridge	189:f392fc9709a3	1469	}
AnnaBridge	189:f392fc9709a3	1470
AnnaBridge	189:f392fc9709a3	1471	/**
AnnaBridge	189:f392fc9709a3	1472	* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
AnnaBridge	189:f392fc9709a3	1473	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1474	* @param cmd: structure that contains the command configuration information.
AnnaBridge	189:f392fc9709a3	1475	* @param cfg: structure that contains the polling configuration information.
AnnaBridge	189:f392fc9709a3	1476	* @param Timeout : Timeout duration
AnnaBridge	189:f392fc9709a3	1477	* @note This function is used only in Automatic Polling Mode
AnnaBridge	189:f392fc9709a3	1478	* @retval HAL status
AnnaBridge	189:f392fc9709a3	1479	*/
AnnaBridge	189:f392fc9709a3	1480	HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
AnnaBridge	189:f392fc9709a3	1481	{
AnnaBridge	189:f392fc9709a3	1482	HAL_StatusTypeDef status;
AnnaBridge	189:f392fc9709a3	1483	uint32_t tickstart = HAL_GetTick();
AnnaBridge	189:f392fc9709a3	1484
AnnaBridge	189:f392fc9709a3	1485	/* Check the parameters */
AnnaBridge	189:f392fc9709a3	1486	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
AnnaBridge	189:f392fc9709a3	1487	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
AnnaBridge	189:f392fc9709a3	1488	{
AnnaBridge	189:f392fc9709a3	1489	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
AnnaBridge	189:f392fc9709a3	1490	}
AnnaBridge	189:f392fc9709a3	1491
AnnaBridge	189:f392fc9709a3	1492	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
AnnaBridge	189:f392fc9709a3	1493	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
AnnaBridge	189:f392fc9709a3	1494	{
AnnaBridge	189:f392fc9709a3	1495	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
AnnaBridge	189:f392fc9709a3	1496	}
AnnaBridge	189:f392fc9709a3	1497
AnnaBridge	189:f392fc9709a3	1498	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
AnnaBridge	189:f392fc9709a3	1499	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
AnnaBridge	189:f392fc9709a3	1500	{
AnnaBridge	189:f392fc9709a3	1501	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
AnnaBridge	189:f392fc9709a3	1502	}
AnnaBridge	189:f392fc9709a3	1503
AnnaBridge	189:f392fc9709a3	1504	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
AnnaBridge	189:f392fc9709a3	1505	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
AnnaBridge	189:f392fc9709a3	1506
AnnaBridge	189:f392fc9709a3	1507	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
AnnaBridge	189:f392fc9709a3	1508	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
AnnaBridge	189:f392fc9709a3	1509	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
AnnaBridge	189:f392fc9709a3	1510
AnnaBridge	189:f392fc9709a3	1511	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
AnnaBridge	189:f392fc9709a3	1512	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
AnnaBridge	189:f392fc9709a3	1513	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
AnnaBridge	189:f392fc9709a3	1514
AnnaBridge	189:f392fc9709a3	1515	/* Process locked */
AnnaBridge	189:f392fc9709a3	1516	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1517
AnnaBridge	189:f392fc9709a3	1518	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	1519	{
AnnaBridge	189:f392fc9709a3	1520	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	1521
AnnaBridge	189:f392fc9709a3	1522	/* Update state */
AnnaBridge	189:f392fc9709a3	1523	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
AnnaBridge	189:f392fc9709a3	1524
AnnaBridge	189:f392fc9709a3	1525	/* Wait till BUSY flag reset */
AnnaBridge	189:f392fc9709a3	1526	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
AnnaBridge	189:f392fc9709a3	1527
AnnaBridge	189:f392fc9709a3	1528	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	1529	{
AnnaBridge	189:f392fc9709a3	1530	/* Configure QSPI: PSMAR register with the status match value */
AnnaBridge	189:f392fc9709a3	1531	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
AnnaBridge	189:f392fc9709a3	1532
AnnaBridge	189:f392fc9709a3	1533	/* Configure QSPI: PSMKR register with the status mask value */
AnnaBridge	189:f392fc9709a3	1534	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
AnnaBridge	189:f392fc9709a3	1535
AnnaBridge	189:f392fc9709a3	1536	/* Configure QSPI: PIR register with the interval value */
AnnaBridge	189:f392fc9709a3	1537	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
AnnaBridge	189:f392fc9709a3	1538
AnnaBridge	189:f392fc9709a3	1539	/* Configure QSPI: CR register with Match mode and Automatic stop enabled
AnnaBridge	189:f392fc9709a3	1540	(otherwise there will be an infinite loop in blocking mode) */
AnnaBridge	189:f392fc9709a3	1541	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
AnnaBridge	189:f392fc9709a3	1542	(cfg->MatchMode \| QSPI_AUTOMATIC_STOP_ENABLE));
AnnaBridge	189:f392fc9709a3	1543
AnnaBridge	189:f392fc9709a3	1544	/* Call the configuration function */
AnnaBridge	189:f392fc9709a3	1545	cmd->NbData = cfg->StatusBytesSize;
AnnaBridge	189:f392fc9709a3	1546	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
AnnaBridge	189:f392fc9709a3	1547
AnnaBridge	189:f392fc9709a3	1548	/* Wait until SM flag is set to go back in idle state */
AnnaBridge	189:f392fc9709a3	1549	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
AnnaBridge	189:f392fc9709a3	1550
AnnaBridge	189:f392fc9709a3	1551	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	1552	{
AnnaBridge	189:f392fc9709a3	1553	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
AnnaBridge	189:f392fc9709a3	1554
AnnaBridge	189:f392fc9709a3	1555	/* Update state */
AnnaBridge	189:f392fc9709a3	1556	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	1557	}
AnnaBridge	189:f392fc9709a3	1558	}
AnnaBridge	189:f392fc9709a3	1559	}
AnnaBridge	189:f392fc9709a3	1560	else
AnnaBridge	189:f392fc9709a3	1561	{
AnnaBridge	189:f392fc9709a3	1562	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	1563	}
AnnaBridge	189:f392fc9709a3	1564
AnnaBridge	189:f392fc9709a3	1565	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1566	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1567
AnnaBridge	189:f392fc9709a3	1568	/* Return function status */
AnnaBridge	189:f392fc9709a3	1569	return status;
AnnaBridge	189:f392fc9709a3	1570	}
AnnaBridge	189:f392fc9709a3	1571
AnnaBridge	189:f392fc9709a3	1572	/**
AnnaBridge	189:f392fc9709a3	1573	* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
AnnaBridge	189:f392fc9709a3	1574	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1575	* @param cmd: structure that contains the command configuration information.
AnnaBridge	189:f392fc9709a3	1576	* @param cfg: structure that contains the polling configuration information.
AnnaBridge	189:f392fc9709a3	1577	* @note This function is used only in Automatic Polling Mode
AnnaBridge	189:f392fc9709a3	1578	* @retval HAL status
AnnaBridge	189:f392fc9709a3	1579	*/
AnnaBridge	189:f392fc9709a3	1580	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg)
AnnaBridge	189:f392fc9709a3	1581	{
AnnaBridge	189:f392fc9709a3	1582	HAL_StatusTypeDef status;
AnnaBridge	189:f392fc9709a3	1583	uint32_t tickstart = HAL_GetTick();
AnnaBridge	189:f392fc9709a3	1584
AnnaBridge	189:f392fc9709a3	1585	/* Check the parameters */
AnnaBridge	189:f392fc9709a3	1586	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
AnnaBridge	189:f392fc9709a3	1587	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
AnnaBridge	189:f392fc9709a3	1588	{
AnnaBridge	189:f392fc9709a3	1589	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
AnnaBridge	189:f392fc9709a3	1590	}
AnnaBridge	189:f392fc9709a3	1591
AnnaBridge	189:f392fc9709a3	1592	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
AnnaBridge	189:f392fc9709a3	1593	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
AnnaBridge	189:f392fc9709a3	1594	{
AnnaBridge	189:f392fc9709a3	1595	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
AnnaBridge	189:f392fc9709a3	1596	}
AnnaBridge	189:f392fc9709a3	1597
AnnaBridge	189:f392fc9709a3	1598	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
AnnaBridge	189:f392fc9709a3	1599	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
AnnaBridge	189:f392fc9709a3	1600	{
AnnaBridge	189:f392fc9709a3	1601	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
AnnaBridge	189:f392fc9709a3	1602	}
AnnaBridge	189:f392fc9709a3	1603
AnnaBridge	189:f392fc9709a3	1604	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
AnnaBridge	189:f392fc9709a3	1605	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
AnnaBridge	189:f392fc9709a3	1606
AnnaBridge	189:f392fc9709a3	1607	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
AnnaBridge	189:f392fc9709a3	1608	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
AnnaBridge	189:f392fc9709a3	1609	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
AnnaBridge	189:f392fc9709a3	1610
AnnaBridge	189:f392fc9709a3	1611	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
AnnaBridge	189:f392fc9709a3	1612	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
AnnaBridge	189:f392fc9709a3	1613	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
AnnaBridge	189:f392fc9709a3	1614	assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
AnnaBridge	189:f392fc9709a3	1615
AnnaBridge	189:f392fc9709a3	1616	/* Process locked */
AnnaBridge	189:f392fc9709a3	1617	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1618
AnnaBridge	189:f392fc9709a3	1619	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	1620	{
AnnaBridge	189:f392fc9709a3	1621	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	1622
AnnaBridge	189:f392fc9709a3	1623	/* Update state */
AnnaBridge	189:f392fc9709a3	1624	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
AnnaBridge	189:f392fc9709a3	1625
AnnaBridge	189:f392fc9709a3	1626	/* Wait till BUSY flag reset */
AnnaBridge	189:f392fc9709a3	1627	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
AnnaBridge	189:f392fc9709a3	1628
AnnaBridge	189:f392fc9709a3	1629	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	1630	{
AnnaBridge	189:f392fc9709a3	1631	/* Configure QSPI: PSMAR register with the status match value */
AnnaBridge	189:f392fc9709a3	1632	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
AnnaBridge	189:f392fc9709a3	1633
AnnaBridge	189:f392fc9709a3	1634	/* Configure QSPI: PSMKR register with the status mask value */
AnnaBridge	189:f392fc9709a3	1635	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
AnnaBridge	189:f392fc9709a3	1636
AnnaBridge	189:f392fc9709a3	1637	/* Configure QSPI: PIR register with the interval value */
AnnaBridge	189:f392fc9709a3	1638	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
AnnaBridge	189:f392fc9709a3	1639
AnnaBridge	189:f392fc9709a3	1640	/* Configure QSPI: CR register with Match mode and Automatic stop mode */
AnnaBridge	189:f392fc9709a3	1641	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
AnnaBridge	189:f392fc9709a3	1642	(cfg->MatchMode \| cfg->AutomaticStop));
AnnaBridge	189:f392fc9709a3	1643
AnnaBridge	189:f392fc9709a3	1644	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	1645	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_SM);
AnnaBridge	189:f392fc9709a3	1646
AnnaBridge	189:f392fc9709a3	1647	/* Call the configuration function */
AnnaBridge	189:f392fc9709a3	1648	cmd->NbData = cfg->StatusBytesSize;
AnnaBridge	189:f392fc9709a3	1649	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
AnnaBridge	189:f392fc9709a3	1650
AnnaBridge	189:f392fc9709a3	1651	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1652	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1653
AnnaBridge	189:f392fc9709a3	1654	/* Enable the QSPI Transfer Error and status match Interrupt */
AnnaBridge	189:f392fc9709a3	1655	__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
AnnaBridge	189:f392fc9709a3	1656
AnnaBridge	189:f392fc9709a3	1657	}
AnnaBridge	189:f392fc9709a3	1658	else
AnnaBridge	189:f392fc9709a3	1659	{
AnnaBridge	189:f392fc9709a3	1660	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1661	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1662	}
AnnaBridge	189:f392fc9709a3	1663	}
AnnaBridge	189:f392fc9709a3	1664	else
AnnaBridge	189:f392fc9709a3	1665	{
AnnaBridge	189:f392fc9709a3	1666	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	1667
AnnaBridge	189:f392fc9709a3	1668	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1669	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1670	}
AnnaBridge	189:f392fc9709a3	1671
AnnaBridge	189:f392fc9709a3	1672	/* Return function status */
AnnaBridge	189:f392fc9709a3	1673	return status;
AnnaBridge	189:f392fc9709a3	1674	}
AnnaBridge	189:f392fc9709a3	1675
AnnaBridge	189:f392fc9709a3	1676	/**
AnnaBridge	189:f392fc9709a3	1677	* @brief Configure the Memory Mapped mode.
AnnaBridge	189:f392fc9709a3	1678	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1679	* @param cmd: structure that contains the command configuration information.
AnnaBridge	189:f392fc9709a3	1680	* @param cfg: structure that contains the memory mapped configuration information.
AnnaBridge	189:f392fc9709a3	1681	* @note This function is used only in Memory mapped Mode
AnnaBridge	189:f392fc9709a3	1682	* @retval HAL status
AnnaBridge	189:f392fc9709a3	1683	*/
AnnaBridge	189:f392fc9709a3	1684	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg)
AnnaBridge	189:f392fc9709a3	1685	{
AnnaBridge	189:f392fc9709a3	1686	HAL_StatusTypeDef status;
AnnaBridge	189:f392fc9709a3	1687	uint32_t tickstart = HAL_GetTick();
AnnaBridge	189:f392fc9709a3	1688
AnnaBridge	189:f392fc9709a3	1689	/* Check the parameters */
AnnaBridge	189:f392fc9709a3	1690	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
AnnaBridge	189:f392fc9709a3	1691	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
AnnaBridge	189:f392fc9709a3	1692	{
AnnaBridge	189:f392fc9709a3	1693	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
AnnaBridge	189:f392fc9709a3	1694	}
AnnaBridge	189:f392fc9709a3	1695
AnnaBridge	189:f392fc9709a3	1696	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
AnnaBridge	189:f392fc9709a3	1697	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
AnnaBridge	189:f392fc9709a3	1698	{
AnnaBridge	189:f392fc9709a3	1699	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
AnnaBridge	189:f392fc9709a3	1700	}
AnnaBridge	189:f392fc9709a3	1701
AnnaBridge	189:f392fc9709a3	1702	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
AnnaBridge	189:f392fc9709a3	1703	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
AnnaBridge	189:f392fc9709a3	1704	{
AnnaBridge	189:f392fc9709a3	1705	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
AnnaBridge	189:f392fc9709a3	1706	}
AnnaBridge	189:f392fc9709a3	1707
AnnaBridge	189:f392fc9709a3	1708	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
AnnaBridge	189:f392fc9709a3	1709	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
AnnaBridge	189:f392fc9709a3	1710
AnnaBridge	189:f392fc9709a3	1711	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
AnnaBridge	189:f392fc9709a3	1712	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
AnnaBridge	189:f392fc9709a3	1713	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
AnnaBridge	189:f392fc9709a3	1714
AnnaBridge	189:f392fc9709a3	1715	assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
AnnaBridge	189:f392fc9709a3	1716
AnnaBridge	189:f392fc9709a3	1717	/* Process locked */
AnnaBridge	189:f392fc9709a3	1718	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1719
AnnaBridge	189:f392fc9709a3	1720	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	1721	{
AnnaBridge	189:f392fc9709a3	1722	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
AnnaBridge	189:f392fc9709a3	1723
AnnaBridge	189:f392fc9709a3	1724	/* Update state */
AnnaBridge	189:f392fc9709a3	1725	hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
AnnaBridge	189:f392fc9709a3	1726
AnnaBridge	189:f392fc9709a3	1727	/* Wait till BUSY flag reset */
AnnaBridge	189:f392fc9709a3	1728	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
AnnaBridge	189:f392fc9709a3	1729
AnnaBridge	189:f392fc9709a3	1730	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	1731	{
AnnaBridge	189:f392fc9709a3	1732	/* Configure QSPI: CR register with timeout counter enable */
AnnaBridge	189:f392fc9709a3	1733	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
AnnaBridge	189:f392fc9709a3	1734
AnnaBridge	189:f392fc9709a3	1735	if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
AnnaBridge	189:f392fc9709a3	1736	{
AnnaBridge	189:f392fc9709a3	1737	assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
AnnaBridge	189:f392fc9709a3	1738
AnnaBridge	189:f392fc9709a3	1739	/* Configure QSPI: LPTR register with the low-power timeout value */
AnnaBridge	189:f392fc9709a3	1740	WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
AnnaBridge	189:f392fc9709a3	1741
AnnaBridge	189:f392fc9709a3	1742	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	1743	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
AnnaBridge	189:f392fc9709a3	1744
AnnaBridge	189:f392fc9709a3	1745	/* Enable the QSPI TimeOut Interrupt */
AnnaBridge	189:f392fc9709a3	1746	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
AnnaBridge	189:f392fc9709a3	1747	}
AnnaBridge	189:f392fc9709a3	1748
AnnaBridge	189:f392fc9709a3	1749	/* Call the configuration function */
AnnaBridge	189:f392fc9709a3	1750	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
AnnaBridge	189:f392fc9709a3	1751	}
AnnaBridge	189:f392fc9709a3	1752	}
AnnaBridge	189:f392fc9709a3	1753	else
AnnaBridge	189:f392fc9709a3	1754	{
AnnaBridge	189:f392fc9709a3	1755	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	1756	}
AnnaBridge	189:f392fc9709a3	1757
AnnaBridge	189:f392fc9709a3	1758	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	1759	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1760
AnnaBridge	189:f392fc9709a3	1761	/* Return function status */
AnnaBridge	189:f392fc9709a3	1762	return status;
AnnaBridge	189:f392fc9709a3	1763	}
AnnaBridge	189:f392fc9709a3	1764
AnnaBridge	189:f392fc9709a3	1765	/**
AnnaBridge	189:f392fc9709a3	1766	* @brief Transfer Error callback.
AnnaBridge	189:f392fc9709a3	1767	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1768	* @retval None
AnnaBridge	189:f392fc9709a3	1769	*/
AnnaBridge	189:f392fc9709a3	1770	__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	1771	{
AnnaBridge	189:f392fc9709a3	1772	/* Prevent unused argument(s) compilation warning */
AnnaBridge	189:f392fc9709a3	1773	UNUSED(hqspi);
AnnaBridge	189:f392fc9709a3	1774
AnnaBridge	189:f392fc9709a3	1775	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	189:f392fc9709a3	1776	the HAL_QSPI_ErrorCallback could be implemented in the user file
AnnaBridge	189:f392fc9709a3	1777	*/
AnnaBridge	189:f392fc9709a3	1778	}
AnnaBridge	189:f392fc9709a3	1779
AnnaBridge	189:f392fc9709a3	1780	/**
AnnaBridge	189:f392fc9709a3	1781	* @brief Abort completed callback.
AnnaBridge	189:f392fc9709a3	1782	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1783	* @retval None
AnnaBridge	189:f392fc9709a3	1784	*/
AnnaBridge	189:f392fc9709a3	1785	__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	1786	{
AnnaBridge	189:f392fc9709a3	1787	/* Prevent unused argument(s) compilation warning */
AnnaBridge	189:f392fc9709a3	1788	UNUSED(hqspi);
AnnaBridge	189:f392fc9709a3	1789
AnnaBridge	189:f392fc9709a3	1790	/* NOTE: This function should not be modified, when the callback is needed,
AnnaBridge	189:f392fc9709a3	1791	the HAL_QSPI_AbortCpltCallback could be implemented in the user file
AnnaBridge	189:f392fc9709a3	1792	*/
AnnaBridge	189:f392fc9709a3	1793	}
AnnaBridge	189:f392fc9709a3	1794
AnnaBridge	189:f392fc9709a3	1795	/**
AnnaBridge	189:f392fc9709a3	1796	* @brief Command completed callback.
AnnaBridge	189:f392fc9709a3	1797	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1798	* @retval None
AnnaBridge	189:f392fc9709a3	1799	*/
AnnaBridge	189:f392fc9709a3	1800	__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	1801	{
AnnaBridge	189:f392fc9709a3	1802	/* Prevent unused argument(s) compilation warning */
AnnaBridge	189:f392fc9709a3	1803	UNUSED(hqspi);
AnnaBridge	189:f392fc9709a3	1804
AnnaBridge	189:f392fc9709a3	1805	/* NOTE: This function should not be modified, when the callback is needed,
AnnaBridge	189:f392fc9709a3	1806	the HAL_QSPI_CmdCpltCallback could be implemented in the user file
AnnaBridge	189:f392fc9709a3	1807	*/
AnnaBridge	189:f392fc9709a3	1808	}
AnnaBridge	189:f392fc9709a3	1809
AnnaBridge	189:f392fc9709a3	1810	/**
AnnaBridge	189:f392fc9709a3	1811	* @brief Rx Transfer completed callback.
AnnaBridge	189:f392fc9709a3	1812	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1813	* @retval None
AnnaBridge	189:f392fc9709a3	1814	*/
AnnaBridge	189:f392fc9709a3	1815	__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	1816	{
AnnaBridge	189:f392fc9709a3	1817	/* Prevent unused argument(s) compilation warning */
AnnaBridge	189:f392fc9709a3	1818	UNUSED(hqspi);
AnnaBridge	189:f392fc9709a3	1819
AnnaBridge	189:f392fc9709a3	1820	/* NOTE: This function should not be modified, when the callback is needed,
AnnaBridge	189:f392fc9709a3	1821	the HAL_QSPI_RxCpltCallback could be implemented in the user file
AnnaBridge	189:f392fc9709a3	1822	*/
AnnaBridge	189:f392fc9709a3	1823	}
AnnaBridge	189:f392fc9709a3	1824
AnnaBridge	189:f392fc9709a3	1825	/**
AnnaBridge	189:f392fc9709a3	1826	* @brief Tx Transfer completed callback.
AnnaBridge	189:f392fc9709a3	1827	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1828	* @retval None
AnnaBridge	189:f392fc9709a3	1829	*/
AnnaBridge	189:f392fc9709a3	1830	__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	1831	{
AnnaBridge	189:f392fc9709a3	1832	/* Prevent unused argument(s) compilation warning */
AnnaBridge	189:f392fc9709a3	1833	UNUSED(hqspi);
AnnaBridge	189:f392fc9709a3	1834
AnnaBridge	189:f392fc9709a3	1835	/* NOTE: This function should not be modified, when the callback is needed,
AnnaBridge	189:f392fc9709a3	1836	the HAL_QSPI_TxCpltCallback could be implemented in the user file
AnnaBridge	189:f392fc9709a3	1837	*/
AnnaBridge	189:f392fc9709a3	1838	}
AnnaBridge	189:f392fc9709a3	1839
AnnaBridge	189:f392fc9709a3	1840
AnnaBridge	189:f392fc9709a3	1841	/**
AnnaBridge	189:f392fc9709a3	1842	* @brief FIFO Threshold callback.
AnnaBridge	189:f392fc9709a3	1843	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1844	* @retval None
AnnaBridge	189:f392fc9709a3	1845	*/
AnnaBridge	189:f392fc9709a3	1846	__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	1847	{
AnnaBridge	189:f392fc9709a3	1848	/* Prevent unused argument(s) compilation warning */
AnnaBridge	189:f392fc9709a3	1849	UNUSED(hqspi);
AnnaBridge	189:f392fc9709a3	1850
AnnaBridge	189:f392fc9709a3	1851	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	189:f392fc9709a3	1852	the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
AnnaBridge	189:f392fc9709a3	1853	*/
AnnaBridge	189:f392fc9709a3	1854	}
AnnaBridge	189:f392fc9709a3	1855
AnnaBridge	189:f392fc9709a3	1856	/**
AnnaBridge	189:f392fc9709a3	1857	* @brief Status Match callback.
AnnaBridge	189:f392fc9709a3	1858	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1859	* @retval None
AnnaBridge	189:f392fc9709a3	1860	*/
AnnaBridge	189:f392fc9709a3	1861	__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	1862	{
AnnaBridge	189:f392fc9709a3	1863	/* Prevent unused argument(s) compilation warning */
AnnaBridge	189:f392fc9709a3	1864	UNUSED(hqspi);
AnnaBridge	189:f392fc9709a3	1865
AnnaBridge	189:f392fc9709a3	1866	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	189:f392fc9709a3	1867	the HAL_QSPI_StatusMatchCallback could be implemented in the user file
AnnaBridge	189:f392fc9709a3	1868	*/
AnnaBridge	189:f392fc9709a3	1869	}
AnnaBridge	189:f392fc9709a3	1870
AnnaBridge	189:f392fc9709a3	1871	/**
AnnaBridge	189:f392fc9709a3	1872	* @brief Timeout callback.
AnnaBridge	189:f392fc9709a3	1873	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	1874	* @retval None
AnnaBridge	189:f392fc9709a3	1875	*/
AnnaBridge	189:f392fc9709a3	1876	__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	1877	{
AnnaBridge	189:f392fc9709a3	1878	/* Prevent unused argument(s) compilation warning */
AnnaBridge	189:f392fc9709a3	1879	UNUSED(hqspi);
AnnaBridge	189:f392fc9709a3	1880
AnnaBridge	189:f392fc9709a3	1881	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	189:f392fc9709a3	1882	the HAL_QSPI_TimeOutCallback could be implemented in the user file
AnnaBridge	189:f392fc9709a3	1883	*/
AnnaBridge	189:f392fc9709a3	1884	}
AnnaBridge	189:f392fc9709a3	1885	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	1886	/**
AnnaBridge	189:f392fc9709a3	1887	* @brief Register a User QSPI Callback
AnnaBridge	189:f392fc9709a3	1888	* To be used instead of the weak (surcharged) predefined callback
AnnaBridge	189:f392fc9709a3	1889	* @param hqspi : QSPI handle
AnnaBridge	189:f392fc9709a3	1890	* @param CallbackId : ID of the callback to be registered
AnnaBridge	189:f392fc9709a3	1891	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1892	* @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
AnnaBridge	189:f392fc9709a3	1893	* @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
AnnaBridge	189:f392fc9709a3	1894	* @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
AnnaBridge	189:f392fc9709a3	1895	* @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
AnnaBridge	189:f392fc9709a3	1896	* @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
AnnaBridge	189:f392fc9709a3	1897	* @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
AnnaBridge	189:f392fc9709a3	1898	* @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
AnnaBridge	189:f392fc9709a3	1899	* @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
AnnaBridge	189:f392fc9709a3	1900	* @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
AnnaBridge	189:f392fc9709a3	1901	* @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
AnnaBridge	189:f392fc9709a3	1902	* @param pCallback : pointer to the Callback function
AnnaBridge	189:f392fc9709a3	1903	* @retval status
AnnaBridge	189:f392fc9709a3	1904	*/
AnnaBridge	189:f392fc9709a3	1905	HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
AnnaBridge	189:f392fc9709a3	1906	{
AnnaBridge	189:f392fc9709a3	1907	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	1908
AnnaBridge	189:f392fc9709a3	1909	if(pCallback == NULL)
AnnaBridge	189:f392fc9709a3	1910	{
AnnaBridge	189:f392fc9709a3	1911	/* Update the error code */
AnnaBridge	189:f392fc9709a3	1912	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_CALLBACK;
AnnaBridge	189:f392fc9709a3	1913	return HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1914	}
AnnaBridge	189:f392fc9709a3	1915
AnnaBridge	189:f392fc9709a3	1916	/* Process locked */
AnnaBridge	189:f392fc9709a3	1917	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1918
AnnaBridge	189:f392fc9709a3	1919	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	1920	{
AnnaBridge	189:f392fc9709a3	1921	switch (CallbackId)
AnnaBridge	189:f392fc9709a3	1922	{
AnnaBridge	189:f392fc9709a3	1923	case HAL_QSPI_ERROR_CB_ID :
AnnaBridge	189:f392fc9709a3	1924	hqspi->ErrorCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1925	break;
AnnaBridge	189:f392fc9709a3	1926	case HAL_QSPI_ABORT_CB_ID :
AnnaBridge	189:f392fc9709a3	1927	hqspi->AbortCpltCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1928	break;
AnnaBridge	189:f392fc9709a3	1929	case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
AnnaBridge	189:f392fc9709a3	1930	hqspi->FifoThresholdCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1931	break;
AnnaBridge	189:f392fc9709a3	1932	case HAL_QSPI_CMD_CPLT_CB_ID :
AnnaBridge	189:f392fc9709a3	1933	hqspi->CmdCpltCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1934	break;
AnnaBridge	189:f392fc9709a3	1935	case HAL_QSPI_RX_CPLT_CB_ID :
AnnaBridge	189:f392fc9709a3	1936	hqspi->RxCpltCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1937	break;
AnnaBridge	189:f392fc9709a3	1938	case HAL_QSPI_TX_CPLT_CB_ID :
AnnaBridge	189:f392fc9709a3	1939	hqspi->TxCpltCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1940	break;
AnnaBridge	189:f392fc9709a3	1941	case HAL_QSPI_STATUS_MATCH_CB_ID :
AnnaBridge	189:f392fc9709a3	1942	hqspi->StatusMatchCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1943	break;
AnnaBridge	189:f392fc9709a3	1944	case HAL_QSPI_TIMEOUT_CB_ID :
AnnaBridge	189:f392fc9709a3	1945	hqspi->TimeOutCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1946	break;
AnnaBridge	189:f392fc9709a3	1947	case HAL_QSPI_MSP_INIT_CB_ID :
AnnaBridge	189:f392fc9709a3	1948	hqspi->MspInitCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1949	break;
AnnaBridge	189:f392fc9709a3	1950	case HAL_QSPI_MSP_DEINIT_CB_ID :
AnnaBridge	189:f392fc9709a3	1951	hqspi->MspDeInitCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1952	break;
AnnaBridge	189:f392fc9709a3	1953	default :
AnnaBridge	189:f392fc9709a3	1954	/* Update the error code */
AnnaBridge	189:f392fc9709a3	1955	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_CALLBACK;
AnnaBridge	189:f392fc9709a3	1956	/* update return status */
AnnaBridge	189:f392fc9709a3	1957	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1958	break;
AnnaBridge	189:f392fc9709a3	1959	}
AnnaBridge	189:f392fc9709a3	1960	}
AnnaBridge	189:f392fc9709a3	1961	else if (hqspi->State == HAL_QSPI_STATE_RESET)
AnnaBridge	189:f392fc9709a3	1962	{
AnnaBridge	189:f392fc9709a3	1963	switch (CallbackId)
AnnaBridge	189:f392fc9709a3	1964	{
AnnaBridge	189:f392fc9709a3	1965	case HAL_QSPI_MSP_INIT_CB_ID :
AnnaBridge	189:f392fc9709a3	1966	hqspi->MspInitCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1967	break;
AnnaBridge	189:f392fc9709a3	1968	case HAL_QSPI_MSP_DEINIT_CB_ID :
AnnaBridge	189:f392fc9709a3	1969	hqspi->MspDeInitCallback = pCallback;
AnnaBridge	189:f392fc9709a3	1970	break;
AnnaBridge	189:f392fc9709a3	1971	default :
AnnaBridge	189:f392fc9709a3	1972	/* Update the error code */
AnnaBridge	189:f392fc9709a3	1973	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_CALLBACK;
AnnaBridge	189:f392fc9709a3	1974	/* update return status */
AnnaBridge	189:f392fc9709a3	1975	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1976	break;
AnnaBridge	189:f392fc9709a3	1977	}
AnnaBridge	189:f392fc9709a3	1978	}
AnnaBridge	189:f392fc9709a3	1979	else
AnnaBridge	189:f392fc9709a3	1980	{
AnnaBridge	189:f392fc9709a3	1981	/* Update the error code */
AnnaBridge	189:f392fc9709a3	1982	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_CALLBACK;
AnnaBridge	189:f392fc9709a3	1983	/* update return status */
AnnaBridge	189:f392fc9709a3	1984	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	1985	}
AnnaBridge	189:f392fc9709a3	1986
AnnaBridge	189:f392fc9709a3	1987	/* Release Lock */
AnnaBridge	189:f392fc9709a3	1988	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	1989	return status;
AnnaBridge	189:f392fc9709a3	1990	}
AnnaBridge	189:f392fc9709a3	1991
AnnaBridge	189:f392fc9709a3	1992	/**
AnnaBridge	189:f392fc9709a3	1993	* @brief Unregister a User QSPI Callback
AnnaBridge	189:f392fc9709a3	1994	* QSPI Callback is redirected to the weak (surcharged) predefined callback
AnnaBridge	189:f392fc9709a3	1995	* @param hqspi : QSPI handle
AnnaBridge	189:f392fc9709a3	1996	* @param CallbackId : ID of the callback to be unregistered
AnnaBridge	189:f392fc9709a3	1997	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	1998	* @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
AnnaBridge	189:f392fc9709a3	1999	* @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
AnnaBridge	189:f392fc9709a3	2000	* @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
AnnaBridge	189:f392fc9709a3	2001	* @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
AnnaBridge	189:f392fc9709a3	2002	* @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
AnnaBridge	189:f392fc9709a3	2003	* @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
AnnaBridge	189:f392fc9709a3	2004	* @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
AnnaBridge	189:f392fc9709a3	2005	* @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
AnnaBridge	189:f392fc9709a3	2006	* @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
AnnaBridge	189:f392fc9709a3	2007	* @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
AnnaBridge	189:f392fc9709a3	2008	* @retval status
AnnaBridge	189:f392fc9709a3	2009	*/
AnnaBridge	189:f392fc9709a3	2010	HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
AnnaBridge	189:f392fc9709a3	2011	{
AnnaBridge	189:f392fc9709a3	2012	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	2013
AnnaBridge	189:f392fc9709a3	2014	/* Process locked */
AnnaBridge	189:f392fc9709a3	2015	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	2016
AnnaBridge	189:f392fc9709a3	2017	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	2018	{
AnnaBridge	189:f392fc9709a3	2019	switch (CallbackId)
AnnaBridge	189:f392fc9709a3	2020	{
AnnaBridge	189:f392fc9709a3	2021	case HAL_QSPI_ERROR_CB_ID :
AnnaBridge	189:f392fc9709a3	2022	hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
AnnaBridge	189:f392fc9709a3	2023	break;
AnnaBridge	189:f392fc9709a3	2024	case HAL_QSPI_ABORT_CB_ID :
AnnaBridge	189:f392fc9709a3	2025	hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
AnnaBridge	189:f392fc9709a3	2026	break;
AnnaBridge	189:f392fc9709a3	2027	case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
AnnaBridge	189:f392fc9709a3	2028	hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
AnnaBridge	189:f392fc9709a3	2029	break;
AnnaBridge	189:f392fc9709a3	2030	case HAL_QSPI_CMD_CPLT_CB_ID :
AnnaBridge	189:f392fc9709a3	2031	hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
AnnaBridge	189:f392fc9709a3	2032	break;
AnnaBridge	189:f392fc9709a3	2033	case HAL_QSPI_RX_CPLT_CB_ID :
AnnaBridge	189:f392fc9709a3	2034	hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
AnnaBridge	189:f392fc9709a3	2035	break;
AnnaBridge	189:f392fc9709a3	2036	case HAL_QSPI_TX_CPLT_CB_ID :
AnnaBridge	189:f392fc9709a3	2037	hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
AnnaBridge	189:f392fc9709a3	2038	break;
AnnaBridge	189:f392fc9709a3	2039	case HAL_QSPI_STATUS_MATCH_CB_ID :
AnnaBridge	189:f392fc9709a3	2040	hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
AnnaBridge	189:f392fc9709a3	2041	break;
AnnaBridge	189:f392fc9709a3	2042	case HAL_QSPI_TIMEOUT_CB_ID :
AnnaBridge	189:f392fc9709a3	2043	hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
AnnaBridge	189:f392fc9709a3	2044	break;
AnnaBridge	189:f392fc9709a3	2045	case HAL_QSPI_MSP_INIT_CB_ID :
AnnaBridge	189:f392fc9709a3	2046	hqspi->MspInitCallback = HAL_QSPI_MspInit;
AnnaBridge	189:f392fc9709a3	2047	break;
AnnaBridge	189:f392fc9709a3	2048	case HAL_QSPI_MSP_DEINIT_CB_ID :
AnnaBridge	189:f392fc9709a3	2049	hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
AnnaBridge	189:f392fc9709a3	2050	break;
AnnaBridge	189:f392fc9709a3	2051	default :
AnnaBridge	189:f392fc9709a3	2052	/* Update the error code */
AnnaBridge	189:f392fc9709a3	2053	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_CALLBACK;
AnnaBridge	189:f392fc9709a3	2054	/* update return status */
AnnaBridge	189:f392fc9709a3	2055	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	2056	break;
AnnaBridge	189:f392fc9709a3	2057	}
AnnaBridge	189:f392fc9709a3	2058	}
AnnaBridge	189:f392fc9709a3	2059	else if (hqspi->State == HAL_QSPI_STATE_RESET)
AnnaBridge	189:f392fc9709a3	2060	{
AnnaBridge	189:f392fc9709a3	2061	switch (CallbackId)
AnnaBridge	189:f392fc9709a3	2062	{
AnnaBridge	189:f392fc9709a3	2063	case HAL_QSPI_MSP_INIT_CB_ID :
AnnaBridge	189:f392fc9709a3	2064	hqspi->MspInitCallback = HAL_QSPI_MspInit;
AnnaBridge	189:f392fc9709a3	2065	break;
AnnaBridge	189:f392fc9709a3	2066	case HAL_QSPI_MSP_DEINIT_CB_ID :
AnnaBridge	189:f392fc9709a3	2067	hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
AnnaBridge	189:f392fc9709a3	2068	break;
AnnaBridge	189:f392fc9709a3	2069	default :
AnnaBridge	189:f392fc9709a3	2070	/* Update the error code */
AnnaBridge	189:f392fc9709a3	2071	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_CALLBACK;
AnnaBridge	189:f392fc9709a3	2072	/* update return status */
AnnaBridge	189:f392fc9709a3	2073	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	2074	break;
AnnaBridge	189:f392fc9709a3	2075	}
AnnaBridge	189:f392fc9709a3	2076	}
AnnaBridge	189:f392fc9709a3	2077	else
AnnaBridge	189:f392fc9709a3	2078	{
AnnaBridge	189:f392fc9709a3	2079	/* Update the error code */
AnnaBridge	189:f392fc9709a3	2080	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_CALLBACK;
AnnaBridge	189:f392fc9709a3	2081	/* update return status */
AnnaBridge	189:f392fc9709a3	2082	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	2083	}
AnnaBridge	189:f392fc9709a3	2084
AnnaBridge	189:f392fc9709a3	2085	/* Release Lock */
AnnaBridge	189:f392fc9709a3	2086	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	2087	return status;
AnnaBridge	189:f392fc9709a3	2088	}
AnnaBridge	189:f392fc9709a3	2089	#endif
AnnaBridge	189:f392fc9709a3	2090
AnnaBridge	189:f392fc9709a3	2091	/**
AnnaBridge	189:f392fc9709a3	2092	* @}
AnnaBridge	189:f392fc9709a3	2093	*/
AnnaBridge	189:f392fc9709a3	2094
AnnaBridge	189:f392fc9709a3	2095	/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
AnnaBridge	189:f392fc9709a3	2096	* @brief QSPI control and State functions
AnnaBridge	189:f392fc9709a3	2097	*
AnnaBridge	189:f392fc9709a3	2098	@verbatim
AnnaBridge	189:f392fc9709a3	2099	===============================================================================
AnnaBridge	189:f392fc9709a3	2100	##### Peripheral Control and State functions #####
AnnaBridge	189:f392fc9709a3	2101	===============================================================================
AnnaBridge	189:f392fc9709a3	2102	[..]
AnnaBridge	189:f392fc9709a3	2103	This subsection provides a set of functions allowing to :
AnnaBridge	189:f392fc9709a3	2104	(+) Check in run-time the state of the driver.
AnnaBridge	189:f392fc9709a3	2105	(+) Check the error code set during last operation.
AnnaBridge	189:f392fc9709a3	2106	(+) Abort any operation.
AnnaBridge	189:f392fc9709a3	2107
AnnaBridge	189:f392fc9709a3	2108
AnnaBridge	189:f392fc9709a3	2109	@endverbatim
AnnaBridge	189:f392fc9709a3	2110	* @{
AnnaBridge	189:f392fc9709a3	2111	*/
AnnaBridge	189:f392fc9709a3	2112
AnnaBridge	189:f392fc9709a3	2113	/**
AnnaBridge	189:f392fc9709a3	2114	* @brief Return the QSPI handle state.
AnnaBridge	189:f392fc9709a3	2115	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	2116	* @retval HAL state
AnnaBridge	189:f392fc9709a3	2117	*/
AnnaBridge	189:f392fc9709a3	2118	HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	2119	{
AnnaBridge	189:f392fc9709a3	2120	/* Return QSPI handle state */
AnnaBridge	189:f392fc9709a3	2121	return hqspi->State;
AnnaBridge	189:f392fc9709a3	2122	}
AnnaBridge	189:f392fc9709a3	2123
AnnaBridge	189:f392fc9709a3	2124	/**
AnnaBridge	189:f392fc9709a3	2125	* @brief Return the QSPI error code.
AnnaBridge	189:f392fc9709a3	2126	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	2127	* @retval QSPI Error Code
AnnaBridge	189:f392fc9709a3	2128	*/
AnnaBridge	189:f392fc9709a3	2129	uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	2130	{
AnnaBridge	189:f392fc9709a3	2131	return hqspi->ErrorCode;
AnnaBridge	189:f392fc9709a3	2132	}
AnnaBridge	189:f392fc9709a3	2133
AnnaBridge	189:f392fc9709a3	2134	/**
AnnaBridge	189:f392fc9709a3	2135	* @brief Abort the current transmission.
AnnaBridge	189:f392fc9709a3	2136	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	2137	* @retval HAL status
AnnaBridge	189:f392fc9709a3	2138	*/
AnnaBridge	189:f392fc9709a3	2139	HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	2140	{
AnnaBridge	189:f392fc9709a3	2141	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	2142	uint32_t tickstart = HAL_GetTick();
AnnaBridge	189:f392fc9709a3	2143
AnnaBridge	189:f392fc9709a3	2144	/* Check if the state is in one of the busy states */
AnnaBridge	189:f392fc9709a3	2145	if (((uint32_t)hqspi->State & 0x2U) != 0U)
AnnaBridge	189:f392fc9709a3	2146	{
AnnaBridge	189:f392fc9709a3	2147	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	2148	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	2149
AnnaBridge	189:f392fc9709a3	2150	if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
AnnaBridge	189:f392fc9709a3	2151	{
AnnaBridge	189:f392fc9709a3	2152	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
AnnaBridge	189:f392fc9709a3	2153	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
AnnaBridge	189:f392fc9709a3	2154
AnnaBridge	189:f392fc9709a3	2155	/* Abort MDMA */
AnnaBridge	189:f392fc9709a3	2156	status = HAL_MDMA_Abort(hqspi->hmdma);
AnnaBridge	189:f392fc9709a3	2157	if(status != HAL_OK)
AnnaBridge	189:f392fc9709a3	2158	{
AnnaBridge	189:f392fc9709a3	2159	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
AnnaBridge	189:f392fc9709a3	2160	}
AnnaBridge	189:f392fc9709a3	2161	}
AnnaBridge	189:f392fc9709a3	2162
AnnaBridge	189:f392fc9709a3	2163	/* Configure QSPI: CR register with Abort request */
AnnaBridge	189:f392fc9709a3	2164	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
AnnaBridge	189:f392fc9709a3	2165
AnnaBridge	189:f392fc9709a3	2166	/* Wait until TC flag is set to go back in idle state */
AnnaBridge	189:f392fc9709a3	2167	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
AnnaBridge	189:f392fc9709a3	2168
AnnaBridge	189:f392fc9709a3	2169	if(status == HAL_OK)
AnnaBridge	189:f392fc9709a3	2170	{
AnnaBridge	189:f392fc9709a3	2171	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
AnnaBridge	189:f392fc9709a3	2172
AnnaBridge	189:f392fc9709a3	2173	/* Wait until BUSY flag is reset */
AnnaBridge	189:f392fc9709a3	2174	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
AnnaBridge	189:f392fc9709a3	2175	}
AnnaBridge	189:f392fc9709a3	2176
AnnaBridge	189:f392fc9709a3	2177	if (status == HAL_OK)
AnnaBridge	189:f392fc9709a3	2178	{
AnnaBridge	189:f392fc9709a3	2179	/* Update state */
AnnaBridge	189:f392fc9709a3	2180	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	2181	}
AnnaBridge	189:f392fc9709a3	2182	}
AnnaBridge	189:f392fc9709a3	2183
AnnaBridge	189:f392fc9709a3	2184	return status;
AnnaBridge	189:f392fc9709a3	2185	}
AnnaBridge	189:f392fc9709a3	2186
AnnaBridge	189:f392fc9709a3	2187	/**
AnnaBridge	189:f392fc9709a3	2188	* @brief Abort the current transmission (non-blocking function)
AnnaBridge	189:f392fc9709a3	2189	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	2190	* @retval HAL status
AnnaBridge	189:f392fc9709a3	2191	*/
AnnaBridge	189:f392fc9709a3	2192	HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	2193	{
AnnaBridge	189:f392fc9709a3	2194	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	2195
AnnaBridge	189:f392fc9709a3	2196	/* Check if the state is in one of the busy states */
AnnaBridge	189:f392fc9709a3	2197	if (((uint32_t)hqspi->State & 0x2U) != 0U)
AnnaBridge	189:f392fc9709a3	2198	{
AnnaBridge	189:f392fc9709a3	2199	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	2200	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	2201
AnnaBridge	189:f392fc9709a3	2202	/* Update QSPI state */
AnnaBridge	189:f392fc9709a3	2203	hqspi->State = HAL_QSPI_STATE_ABORT;
AnnaBridge	189:f392fc9709a3	2204
AnnaBridge	189:f392fc9709a3	2205	/* Disable all interrupts */
AnnaBridge	189:f392fc9709a3	2206	__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO \| QSPI_IT_SM \| QSPI_IT_FT \| QSPI_IT_TC \| QSPI_IT_TE));
AnnaBridge	189:f392fc9709a3	2207
AnnaBridge	189:f392fc9709a3	2208	if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
AnnaBridge	189:f392fc9709a3	2209	{
AnnaBridge	189:f392fc9709a3	2210	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
AnnaBridge	189:f392fc9709a3	2211	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
AnnaBridge	189:f392fc9709a3	2212
AnnaBridge	189:f392fc9709a3	2213	/* Abort MDMA channel */
AnnaBridge	189:f392fc9709a3	2214	hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
AnnaBridge	189:f392fc9709a3	2215	if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
AnnaBridge	189:f392fc9709a3	2216	{
AnnaBridge	189:f392fc9709a3	2217	/* Set error code to DMA */
AnnaBridge	189:f392fc9709a3	2218	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
AnnaBridge	189:f392fc9709a3	2219
AnnaBridge	189:f392fc9709a3	2220	status = HAL_ERROR;
AnnaBridge	189:f392fc9709a3	2221	}
AnnaBridge	189:f392fc9709a3	2222	}
AnnaBridge	189:f392fc9709a3	2223	else
AnnaBridge	189:f392fc9709a3	2224	{
AnnaBridge	189:f392fc9709a3	2225	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	2226	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
AnnaBridge	189:f392fc9709a3	2227
AnnaBridge	189:f392fc9709a3	2228	/* Enable the QSPI Transfer Complete Interrupt */
AnnaBridge	189:f392fc9709a3	2229	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
AnnaBridge	189:f392fc9709a3	2230
AnnaBridge	189:f392fc9709a3	2231	/* Configure QSPI: CR register with Abort request */
AnnaBridge	189:f392fc9709a3	2232	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
AnnaBridge	189:f392fc9709a3	2233	}
AnnaBridge	189:f392fc9709a3	2234	}
AnnaBridge	189:f392fc9709a3	2235	return status;
AnnaBridge	189:f392fc9709a3	2236	}
AnnaBridge	189:f392fc9709a3	2237
AnnaBridge	189:f392fc9709a3	2238	/** @brief Set QSPI timeout.
AnnaBridge	189:f392fc9709a3	2239	* @param hqspi: QSPI handle.
AnnaBridge	189:f392fc9709a3	2240	* @param Timeout: Timeout for the QSPI memory access.
AnnaBridge	189:f392fc9709a3	2241	* @retval None
AnnaBridge	189:f392fc9709a3	2242	*/
AnnaBridge	189:f392fc9709a3	2243	void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
AnnaBridge	189:f392fc9709a3	2244	{
AnnaBridge	189:f392fc9709a3	2245	hqspi->Timeout = Timeout;
AnnaBridge	189:f392fc9709a3	2246	}
AnnaBridge	189:f392fc9709a3	2247
AnnaBridge	189:f392fc9709a3	2248	/** @brief Set QSPI Fifo threshold.
AnnaBridge	189:f392fc9709a3	2249	* @param hqspi: QSPI handle.
AnnaBridge	189:f392fc9709a3	2250	* @param Threshold: Threshold of the Fifo (value between 1 and 16).
AnnaBridge	189:f392fc9709a3	2251	* @retval HAL status
AnnaBridge	189:f392fc9709a3	2252	*/
AnnaBridge	189:f392fc9709a3	2253	HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
AnnaBridge	189:f392fc9709a3	2254	{
AnnaBridge	189:f392fc9709a3	2255	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	2256
AnnaBridge	189:f392fc9709a3	2257	/* Process locked */
AnnaBridge	189:f392fc9709a3	2258	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	2259
AnnaBridge	189:f392fc9709a3	2260	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	2261	{
AnnaBridge	189:f392fc9709a3	2262	/* Synchronize init structure with new FIFO threshold value */
AnnaBridge	189:f392fc9709a3	2263	hqspi->Init.FifoThreshold = Threshold;
AnnaBridge	189:f392fc9709a3	2264
AnnaBridge	189:f392fc9709a3	2265	/* Configure QSPI FIFO Threshold */
AnnaBridge	189:f392fc9709a3	2266	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
AnnaBridge	189:f392fc9709a3	2267	((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
AnnaBridge	189:f392fc9709a3	2268	}
AnnaBridge	189:f392fc9709a3	2269	else
AnnaBridge	189:f392fc9709a3	2270	{
AnnaBridge	189:f392fc9709a3	2271	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	2272	}
AnnaBridge	189:f392fc9709a3	2273
AnnaBridge	189:f392fc9709a3	2274	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	2275	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	2276
AnnaBridge	189:f392fc9709a3	2277	/* Return function status */
AnnaBridge	189:f392fc9709a3	2278	return status;
AnnaBridge	189:f392fc9709a3	2279	}
AnnaBridge	189:f392fc9709a3	2280
AnnaBridge	189:f392fc9709a3	2281	/** @brief Get QSPI Fifo threshold.
AnnaBridge	189:f392fc9709a3	2282	* @param hqspi: QSPI handle.
AnnaBridge	189:f392fc9709a3	2283	* @retval Fifo threshold (value between 1 and 16)
AnnaBridge	189:f392fc9709a3	2284	*/
AnnaBridge	189:f392fc9709a3	2285	uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
AnnaBridge	189:f392fc9709a3	2286	{
AnnaBridge	189:f392fc9709a3	2287	return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
AnnaBridge	189:f392fc9709a3	2288	}
AnnaBridge	189:f392fc9709a3	2289
AnnaBridge	189:f392fc9709a3	2290	/** @brief Set FlashID.
AnnaBridge	189:f392fc9709a3	2291	* @param hqspi : QSPI handle.
AnnaBridge	189:f392fc9709a3	2292	* @param FlashID : Index of the flash memory to be accessed.
AnnaBridge	189:f392fc9709a3	2293	* This parameter can be a value of @ref QSPI_Flash_Select.
AnnaBridge	189:f392fc9709a3	2294	* @note The FlashID is ignored when dual flash mode is enabled.
AnnaBridge	189:f392fc9709a3	2295	* @retval HAL status
AnnaBridge	189:f392fc9709a3	2296	*/
AnnaBridge	189:f392fc9709a3	2297	HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
AnnaBridge	189:f392fc9709a3	2298	{
AnnaBridge	189:f392fc9709a3	2299	HAL_StatusTypeDef status = HAL_OK;
AnnaBridge	189:f392fc9709a3	2300
AnnaBridge	189:f392fc9709a3	2301	/* Check the parameter */
AnnaBridge	189:f392fc9709a3	2302	assert_param(IS_QSPI_FLASH_ID(FlashID));
AnnaBridge	189:f392fc9709a3	2303
AnnaBridge	189:f392fc9709a3	2304	/* Process locked */
AnnaBridge	189:f392fc9709a3	2305	__HAL_LOCK(hqspi);
AnnaBridge	189:f392fc9709a3	2306
AnnaBridge	189:f392fc9709a3	2307	if(hqspi->State == HAL_QSPI_STATE_READY)
AnnaBridge	189:f392fc9709a3	2308	{
AnnaBridge	189:f392fc9709a3	2309	/* Synchronize init structure with new FlashID value */
AnnaBridge	189:f392fc9709a3	2310	hqspi->Init.FlashID = FlashID;
AnnaBridge	189:f392fc9709a3	2311
AnnaBridge	189:f392fc9709a3	2312	/* Configure QSPI FlashID */
AnnaBridge	189:f392fc9709a3	2313	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
AnnaBridge	189:f392fc9709a3	2314	}
AnnaBridge	189:f392fc9709a3	2315	else
AnnaBridge	189:f392fc9709a3	2316	{
AnnaBridge	189:f392fc9709a3	2317	status = HAL_BUSY;
AnnaBridge	189:f392fc9709a3	2318	}
AnnaBridge	189:f392fc9709a3	2319
AnnaBridge	189:f392fc9709a3	2320	/* Process unlocked */
AnnaBridge	189:f392fc9709a3	2321	__HAL_UNLOCK(hqspi);
AnnaBridge	189:f392fc9709a3	2322
AnnaBridge	189:f392fc9709a3	2323	/* Return function status */
AnnaBridge	189:f392fc9709a3	2324	return status;
AnnaBridge	189:f392fc9709a3	2325	}
AnnaBridge	189:f392fc9709a3	2326
AnnaBridge	189:f392fc9709a3	2327	/**
AnnaBridge	189:f392fc9709a3	2328	* @}
AnnaBridge	189:f392fc9709a3	2329	*/
AnnaBridge	189:f392fc9709a3	2330
AnnaBridge	189:f392fc9709a3	2331	/**
AnnaBridge	189:f392fc9709a3	2332	* @brief DMA QSPI receive process complete callback.
AnnaBridge	189:f392fc9709a3	2333	* @param hmdma: MDMA handle
AnnaBridge	189:f392fc9709a3	2334	* @retval None
AnnaBridge	189:f392fc9709a3	2335	*/
AnnaBridge	189:f392fc9709a3	2336	static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
AnnaBridge	189:f392fc9709a3	2337	{
AnnaBridge	189:f392fc9709a3	2338	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
AnnaBridge	189:f392fc9709a3	2339	hqspi->RxXferCount = 0U;
AnnaBridge	189:f392fc9709a3	2340
AnnaBridge	189:f392fc9709a3	2341	/* Enable the QSPI transfer complete Interrupt */
AnnaBridge	189:f392fc9709a3	2342	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
AnnaBridge	189:f392fc9709a3	2343	}
AnnaBridge	189:f392fc9709a3	2344
AnnaBridge	189:f392fc9709a3	2345	/**
AnnaBridge	189:f392fc9709a3	2346	* @brief DMA QSPI transmit process complete callback.
AnnaBridge	189:f392fc9709a3	2347	* @param hmdma: MDMA handle
AnnaBridge	189:f392fc9709a3	2348	* @retval None
AnnaBridge	189:f392fc9709a3	2349	*/
AnnaBridge	189:f392fc9709a3	2350	static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
AnnaBridge	189:f392fc9709a3	2351	{
AnnaBridge	189:f392fc9709a3	2352	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
AnnaBridge	189:f392fc9709a3	2353	hqspi->TxXferCount = 0U;
AnnaBridge	189:f392fc9709a3	2354
AnnaBridge	189:f392fc9709a3	2355	/* Enable the QSPI transfer complete Interrupt */
AnnaBridge	189:f392fc9709a3	2356	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
AnnaBridge	189:f392fc9709a3	2357	}
AnnaBridge	189:f392fc9709a3	2358
AnnaBridge	189:f392fc9709a3	2359	/**
AnnaBridge	189:f392fc9709a3	2360	* @brief DMA QSPI communication error callback.
AnnaBridge	189:f392fc9709a3	2361	* @param hmdma: MDMA handle
AnnaBridge	189:f392fc9709a3	2362	* @retval None
AnnaBridge	189:f392fc9709a3	2363	*/
AnnaBridge	189:f392fc9709a3	2364	static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
AnnaBridge	189:f392fc9709a3	2365	{
AnnaBridge	189:f392fc9709a3	2366	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
AnnaBridge	189:f392fc9709a3	2367
AnnaBridge	189:f392fc9709a3	2368	hqspi->RxXferCount = 0U;
AnnaBridge	189:f392fc9709a3	2369	hqspi->TxXferCount = 0U;
AnnaBridge	189:f392fc9709a3	2370	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
AnnaBridge	189:f392fc9709a3	2371
AnnaBridge	189:f392fc9709a3	2372	/* Disable the MDMA transfer by clearing the DMAEN bit in the QSPI CR register */
AnnaBridge	189:f392fc9709a3	2373	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
AnnaBridge	189:f392fc9709a3	2374
AnnaBridge	189:f392fc9709a3	2375	/* Abort the QSPI */
AnnaBridge	189:f392fc9709a3	2376	(void)HAL_QSPI_Abort_IT(hqspi);
AnnaBridge	189:f392fc9709a3	2377
AnnaBridge	189:f392fc9709a3	2378	}
AnnaBridge	189:f392fc9709a3	2379
AnnaBridge	189:f392fc9709a3	2380	/**
AnnaBridge	189:f392fc9709a3	2381	* @brief MDMA QSPI abort complete callback.
AnnaBridge	189:f392fc9709a3	2382	* @param hmdma: MDMA handle
AnnaBridge	189:f392fc9709a3	2383	* @retval None
AnnaBridge	189:f392fc9709a3	2384	*/
AnnaBridge	189:f392fc9709a3	2385	static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
AnnaBridge	189:f392fc9709a3	2386	{
AnnaBridge	189:f392fc9709a3	2387	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
AnnaBridge	189:f392fc9709a3	2388
AnnaBridge	189:f392fc9709a3	2389	hqspi->RxXferCount = 0U;
AnnaBridge	189:f392fc9709a3	2390	hqspi->TxXferCount = 0U;
AnnaBridge	189:f392fc9709a3	2391
AnnaBridge	189:f392fc9709a3	2392	if(hqspi->State == HAL_QSPI_STATE_ABORT)
AnnaBridge	189:f392fc9709a3	2393	{
AnnaBridge	189:f392fc9709a3	2394	/* MDMA Abort called by QSPI abort */
AnnaBridge	189:f392fc9709a3	2395	/* Clear interrupt */
AnnaBridge	189:f392fc9709a3	2396	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
AnnaBridge	189:f392fc9709a3	2397
AnnaBridge	189:f392fc9709a3	2398	/* Enable the QSPI Transfer Complete Interrupt */
AnnaBridge	189:f392fc9709a3	2399	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
AnnaBridge	189:f392fc9709a3	2400
AnnaBridge	189:f392fc9709a3	2401	/* Configure QSPI: CR register with Abort request */
AnnaBridge	189:f392fc9709a3	2402	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
AnnaBridge	189:f392fc9709a3	2403	}
AnnaBridge	189:f392fc9709a3	2404	else
AnnaBridge	189:f392fc9709a3	2405	{
AnnaBridge	189:f392fc9709a3	2406	/* MDMA Abort called due to a transfer error interrupt */
AnnaBridge	189:f392fc9709a3	2407	/* Change state of QSPI */
AnnaBridge	189:f392fc9709a3	2408	hqspi->State = HAL_QSPI_STATE_READY;
AnnaBridge	189:f392fc9709a3	2409
AnnaBridge	189:f392fc9709a3	2410	/* Error callback */
AnnaBridge	189:f392fc9709a3	2411	#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge	189:f392fc9709a3	2412	hqspi->ErrorCallback(hqspi);
AnnaBridge	189:f392fc9709a3	2413	#else
AnnaBridge	189:f392fc9709a3	2414	HAL_QSPI_ErrorCallback(hqspi);
AnnaBridge	189:f392fc9709a3	2415	#endif
AnnaBridge	189:f392fc9709a3	2416	}
AnnaBridge	189:f392fc9709a3	2417	}
AnnaBridge	189:f392fc9709a3	2418	/**
AnnaBridge	189:f392fc9709a3	2419	* @brief Wait for a flag state until timeout.
AnnaBridge	189:f392fc9709a3	2420	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	2421	* @param Flag: Flag checked
AnnaBridge	189:f392fc9709a3	2422	* @param State: Value of the flag expected
AnnaBridge	189:f392fc9709a3	2423	* @param Tickstart: Tick start value
AnnaBridge	189:f392fc9709a3	2424	* @param Timeout: Duration of the timeout
AnnaBridge	189:f392fc9709a3	2425	* @retval HAL status
AnnaBridge	189:f392fc9709a3	2426	*/
AnnaBridge	189:f392fc9709a3	2427	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
AnnaBridge	189:f392fc9709a3	2428	FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
AnnaBridge	189:f392fc9709a3	2429	{
AnnaBridge	189:f392fc9709a3	2430	/* Wait until flag is in expected state */
AnnaBridge	189:f392fc9709a3	2431	while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
AnnaBridge	189:f392fc9709a3	2432	{
AnnaBridge	189:f392fc9709a3	2433	/* Check for the Timeout */
AnnaBridge	189:f392fc9709a3	2434	if (Timeout != HAL_MAX_DELAY)
AnnaBridge	189:f392fc9709a3	2435	{
AnnaBridge	189:f392fc9709a3	2436	if(((HAL_GetTick() - Tickstart) > Timeout) \|\| (Timeout == 0U))
AnnaBridge	189:f392fc9709a3	2437	{
AnnaBridge	189:f392fc9709a3	2438	hqspi->State = HAL_QSPI_STATE_ERROR;
AnnaBridge	189:f392fc9709a3	2439	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
AnnaBridge	189:f392fc9709a3	2440
AnnaBridge	189:f392fc9709a3	2441	return HAL_ERROR;
AnnaBridge	189:f392fc9709a3	2442	}
AnnaBridge	189:f392fc9709a3	2443	}
AnnaBridge	189:f392fc9709a3	2444	}
AnnaBridge	189:f392fc9709a3	2445	return HAL_OK;
AnnaBridge	189:f392fc9709a3	2446	}
AnnaBridge	189:f392fc9709a3	2447
AnnaBridge	189:f392fc9709a3	2448	/**
AnnaBridge	189:f392fc9709a3	2449	* @brief Configure the communication registers.
AnnaBridge	189:f392fc9709a3	2450	* @param hqspi: QSPI handle
AnnaBridge	189:f392fc9709a3	2451	* @param cmd: structure that contains the command configuration information
AnnaBridge	189:f392fc9709a3	2452	* @param FunctionalMode: functional mode to configured
AnnaBridge	189:f392fc9709a3	2453	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	2454	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
AnnaBridge	189:f392fc9709a3	2455	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
AnnaBridge	189:f392fc9709a3	2456	* @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
AnnaBridge	189:f392fc9709a3	2457	* @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
AnnaBridge	189:f392fc9709a3	2458	* @retval None
AnnaBridge	189:f392fc9709a3	2459	*/
AnnaBridge	189:f392fc9709a3	2460	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode)
AnnaBridge	189:f392fc9709a3	2461	{
AnnaBridge	189:f392fc9709a3	2462	assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
AnnaBridge	189:f392fc9709a3	2463
AnnaBridge	189:f392fc9709a3	2464	if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
AnnaBridge	189:f392fc9709a3	2465	{
AnnaBridge	189:f392fc9709a3	2466	/* Configure QSPI: DLR register with the number of data to read or write */
AnnaBridge	189:f392fc9709a3	2467	WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
AnnaBridge	189:f392fc9709a3	2468	}
AnnaBridge	189:f392fc9709a3	2469
AnnaBridge	189:f392fc9709a3	2470	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
AnnaBridge	189:f392fc9709a3	2471	{
AnnaBridge	189:f392fc9709a3	2472	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
AnnaBridge	189:f392fc9709a3	2473	{
AnnaBridge	189:f392fc9709a3	2474	/* Configure QSPI: ABR register with alternate bytes value */
AnnaBridge	189:f392fc9709a3	2475	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
AnnaBridge	189:f392fc9709a3	2476
AnnaBridge	189:f392fc9709a3	2477	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
AnnaBridge	189:f392fc9709a3	2478	{
AnnaBridge	189:f392fc9709a3	2479	/---- Command with instruction, address and alternate bytes ----/
AnnaBridge	189:f392fc9709a3	2480	/* Configure QSPI: CCR register with all communications parameters */
AnnaBridge	189:f392fc9709a3	2481	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
AnnaBridge	189:f392fc9709a3	2482	cmd->DataMode \| (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) \|
AnnaBridge	189:f392fc9709a3	2483	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
AnnaBridge	189:f392fc9709a3	2484	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
AnnaBridge	189:f392fc9709a3	2485	cmd->Instruction \| FunctionalMode));
AnnaBridge	189:f392fc9709a3	2486
AnnaBridge	189:f392fc9709a3	2487	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
AnnaBridge	189:f392fc9709a3	2488	{
AnnaBridge	189:f392fc9709a3	2489	/* Configure QSPI: AR register with address value */
AnnaBridge	189:f392fc9709a3	2490	WRITE_REG(hqspi->Instance->AR, cmd->Address);
AnnaBridge	189:f392fc9709a3	2491	}
AnnaBridge	189:f392fc9709a3	2492	}
AnnaBridge	189:f392fc9709a3	2493	else
AnnaBridge	189:f392fc9709a3	2494	{
AnnaBridge	189:f392fc9709a3	2495	/---- Command with instruction and alternate bytes ----/
AnnaBridge	189:f392fc9709a3	2496	/* Configure QSPI: CCR register with all communications parameters */
AnnaBridge	189:f392fc9709a3	2497	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
AnnaBridge	189:f392fc9709a3	2498	cmd->DataMode \| (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) \|
AnnaBridge	189:f392fc9709a3	2499	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
AnnaBridge	189:f392fc9709a3	2500	cmd->AddressMode \| cmd->InstructionMode \|
AnnaBridge	189:f392fc9709a3	2501	cmd->Instruction \| FunctionalMode));
AnnaBridge	189:f392fc9709a3	2502	}
AnnaBridge	189:f392fc9709a3	2503	}
AnnaBridge	189:f392fc9709a3	2504	else
AnnaBridge	189:f392fc9709a3	2505	{
AnnaBridge	189:f392fc9709a3	2506	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
AnnaBridge	189:f392fc9709a3	2507	{
AnnaBridge	189:f392fc9709a3	2508	/---- Command with instruction and address ----/
AnnaBridge	189:f392fc9709a3	2509	/* Configure QSPI: CCR register with all communications parameters */
AnnaBridge	189:f392fc9709a3	2510	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
AnnaBridge	189:f392fc9709a3	2511	cmd->DataMode \| (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) \|
AnnaBridge	189:f392fc9709a3	2512	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
AnnaBridge	189:f392fc9709a3	2513	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
AnnaBridge	189:f392fc9709a3	2514
AnnaBridge	189:f392fc9709a3	2515	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
AnnaBridge	189:f392fc9709a3	2516	{
AnnaBridge	189:f392fc9709a3	2517	/* Configure QSPI: AR register with address value */
AnnaBridge	189:f392fc9709a3	2518	WRITE_REG(hqspi->Instance->AR, cmd->Address);
AnnaBridge	189:f392fc9709a3	2519	}
AnnaBridge	189:f392fc9709a3	2520	}
AnnaBridge	189:f392fc9709a3	2521	else
AnnaBridge	189:f392fc9709a3	2522	{
AnnaBridge	189:f392fc9709a3	2523	/---- Command with only instruction ----/
AnnaBridge	189:f392fc9709a3	2524	/* Configure QSPI: CCR register with all communications parameters */
AnnaBridge	189:f392fc9709a3	2525	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
AnnaBridge	189:f392fc9709a3	2526	cmd->DataMode \| (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) \|
AnnaBridge	189:f392fc9709a3	2527	cmd->AlternateByteMode \| cmd->AddressMode \|
AnnaBridge	189:f392fc9709a3	2528	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
AnnaBridge	189:f392fc9709a3	2529	}
AnnaBridge	189:f392fc9709a3	2530	}
AnnaBridge	189:f392fc9709a3	2531	}
AnnaBridge	189:f392fc9709a3	2532	else
AnnaBridge	189:f392fc9709a3	2533	{
AnnaBridge	189:f392fc9709a3	2534	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
AnnaBridge	189:f392fc9709a3	2535	{
AnnaBridge	189:f392fc9709a3	2536	/* Configure QSPI: ABR register with alternate bytes value */
AnnaBridge	189:f392fc9709a3	2537	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
AnnaBridge	189:f392fc9709a3	2538
AnnaBridge	189:f392fc9709a3	2539	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
AnnaBridge	189:f392fc9709a3	2540	{
AnnaBridge	189:f392fc9709a3	2541	/---- Command with address and alternate bytes ----/
AnnaBridge	189:f392fc9709a3	2542	/* Configure QSPI: CCR register with all communications parameters */
AnnaBridge	189:f392fc9709a3	2543	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
AnnaBridge	189:f392fc9709a3	2544	cmd->DataMode \| (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) \|
AnnaBridge	189:f392fc9709a3	2545	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
AnnaBridge	189:f392fc9709a3	2546	cmd->AddressSize \| cmd->AddressMode \|
AnnaBridge	189:f392fc9709a3	2547	cmd->InstructionMode \| FunctionalMode));
AnnaBridge	189:f392fc9709a3	2548
AnnaBridge	189:f392fc9709a3	2549	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
AnnaBridge	189:f392fc9709a3	2550	{
AnnaBridge	189:f392fc9709a3	2551	/* Configure QSPI: AR register with address value */
AnnaBridge	189:f392fc9709a3	2552	WRITE_REG(hqspi->Instance->AR, cmd->Address);
AnnaBridge	189:f392fc9709a3	2553	}
AnnaBridge	189:f392fc9709a3	2554	}
AnnaBridge	189:f392fc9709a3	2555	else
AnnaBridge	189:f392fc9709a3	2556	{
AnnaBridge	189:f392fc9709a3	2557	/---- Command with only alternate bytes ----/
AnnaBridge	189:f392fc9709a3	2558	/* Configure QSPI: CCR register with all communications parameters */
AnnaBridge	189:f392fc9709a3	2559	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
AnnaBridge	189:f392fc9709a3	2560	cmd->DataMode \| (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) \|
AnnaBridge	189:f392fc9709a3	2561	cmd->AlternateBytesSize \| cmd->AlternateByteMode \|
AnnaBridge	189:f392fc9709a3	2562	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
AnnaBridge	189:f392fc9709a3	2563	}
AnnaBridge	189:f392fc9709a3	2564	}
AnnaBridge	189:f392fc9709a3	2565	else
AnnaBridge	189:f392fc9709a3	2566	{
AnnaBridge	189:f392fc9709a3	2567	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
AnnaBridge	189:f392fc9709a3	2568	{
AnnaBridge	189:f392fc9709a3	2569	/---- Command with only address ----/
AnnaBridge	189:f392fc9709a3	2570	/* Configure QSPI: CCR register with all communications parameters */
AnnaBridge	189:f392fc9709a3	2571	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
AnnaBridge	189:f392fc9709a3	2572	cmd->DataMode \| (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) \|
AnnaBridge	189:f392fc9709a3	2573	cmd->AlternateByteMode \| cmd->AddressSize \|
AnnaBridge	189:f392fc9709a3	2574	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
AnnaBridge	189:f392fc9709a3	2575
AnnaBridge	189:f392fc9709a3	2576	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
AnnaBridge	189:f392fc9709a3	2577	{
AnnaBridge	189:f392fc9709a3	2578	/* Configure QSPI: AR register with address value */
AnnaBridge	189:f392fc9709a3	2579	WRITE_REG(hqspi->Instance->AR, cmd->Address);
AnnaBridge	189:f392fc9709a3	2580	}
AnnaBridge	189:f392fc9709a3	2581	}
AnnaBridge	189:f392fc9709a3	2582	else
AnnaBridge	189:f392fc9709a3	2583	{
AnnaBridge	189:f392fc9709a3	2584	/---- Command with only data phase ----/
AnnaBridge	189:f392fc9709a3	2585	if (cmd->DataMode != QSPI_DATA_NONE)
AnnaBridge	189:f392fc9709a3	2586	{
AnnaBridge	189:f392fc9709a3	2587	/* Configure QSPI: CCR register with all communications parameters */
AnnaBridge	189:f392fc9709a3	2588	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
AnnaBridge	189:f392fc9709a3	2589	cmd->DataMode \| (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) \|
AnnaBridge	189:f392fc9709a3	2590	cmd->AlternateByteMode \| cmd->AddressMode \|
AnnaBridge	189:f392fc9709a3	2591	cmd->InstructionMode \| FunctionalMode));
AnnaBridge	189:f392fc9709a3	2592	}
AnnaBridge	189:f392fc9709a3	2593	}
AnnaBridge	189:f392fc9709a3	2594	}
AnnaBridge	189:f392fc9709a3	2595	}
AnnaBridge	189:f392fc9709a3	2596	}
AnnaBridge	189:f392fc9709a3	2597
AnnaBridge	189:f392fc9709a3	2598	/**
AnnaBridge	189:f392fc9709a3	2599	* @}
AnnaBridge	189:f392fc9709a3	2600	*/
AnnaBridge	189:f392fc9709a3	2601
AnnaBridge	189:f392fc9709a3	2602	/**
AnnaBridge	189:f392fc9709a3	2603	* @}
AnnaBridge	189:f392fc9709a3	2604	*/
AnnaBridge	189:f392fc9709a3	2605
AnnaBridge	189:f392fc9709a3	2606	#endif /* HAL_QSPI_MODULE_ENABLED */
AnnaBridge	189:f392fc9709a3	2607	/**
AnnaBridge	189:f392fc9709a3	2608	* @}
AnnaBridge	189:f392fc9709a3	2609	*/
AnnaBridge	189:f392fc9709a3	2610
AnnaBridge	189:f392fc9709a3	2611	/**
AnnaBridge	189:f392fc9709a3	2612	* @}
AnnaBridge	189:f392fc9709a3	2613	*/
AnnaBridge	189:f392fc9709a3	2614
AnnaBridge	189:f392fc9709a3	2615	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/