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targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pwr.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 ******************************************************************************
AnnaBridge 189:f392fc9709a3 3 * @file stm32h7xx_hal_pwr.c
AnnaBridge 189:f392fc9709a3 4 * @author MCD Application Team
AnnaBridge 189:f392fc9709a3 5 * @brief PWR HAL module driver.
AnnaBridge 189:f392fc9709a3 6 * This file provides firmware functions to manage the following
AnnaBridge 189:f392fc9709a3 7 * functionalities of the Power Controller (PWR) peripheral:
AnnaBridge 189:f392fc9709a3 8 * + Initialization and de-initialization functions
AnnaBridge 189:f392fc9709a3 9 * + Peripheral Control functions
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 ******************************************************************************
AnnaBridge 189:f392fc9709a3 12 * @attention
AnnaBridge 189:f392fc9709a3 13 *
AnnaBridge 189:f392fc9709a3 14 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge 189:f392fc9709a3 15 * All rights reserved.</center></h2>
AnnaBridge 189:f392fc9709a3 16 *
AnnaBridge 189:f392fc9709a3 17 * This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge 189:f392fc9709a3 18 * the "License"; You may not use this file except in compliance with the
AnnaBridge 189:f392fc9709a3 19 * License. You may obtain a copy of the License at:
AnnaBridge 189:f392fc9709a3 20 * opensource.org/licenses/BSD-3-Clause
AnnaBridge 189:f392fc9709a3 21 *
AnnaBridge 189:f392fc9709a3 22 ******************************************************************************
AnnaBridge 189:f392fc9709a3 23 */
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25 /* Includes ------------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 26 #include "stm32h7xx_hal.h"
AnnaBridge 189:f392fc9709a3 27
AnnaBridge 189:f392fc9709a3 28 /** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge 189:f392fc9709a3 29 * @{
AnnaBridge 189:f392fc9709a3 30 */
AnnaBridge 189:f392fc9709a3 31
AnnaBridge 189:f392fc9709a3 32 /** @defgroup PWR PWR
AnnaBridge 189:f392fc9709a3 33 * @brief PWR HAL module driver
AnnaBridge 189:f392fc9709a3 34 * @{
AnnaBridge 189:f392fc9709a3 35 */
AnnaBridge 189:f392fc9709a3 36
AnnaBridge 189:f392fc9709a3 37 #ifdef HAL_PWR_MODULE_ENABLED
AnnaBridge 189:f392fc9709a3 38
AnnaBridge 189:f392fc9709a3 39 /* Private typedef -----------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 40 /* Private define ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 41 /** @addtogroup PWR_Private_Constants PWR Private Constants
AnnaBridge 189:f392fc9709a3 42 * @{
AnnaBridge 189:f392fc9709a3 43 */
AnnaBridge 189:f392fc9709a3 44
AnnaBridge 189:f392fc9709a3 45 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
AnnaBridge 189:f392fc9709a3 46 * @{
AnnaBridge 189:f392fc9709a3 47 */
AnnaBridge 189:f392fc9709a3 48 #define PVD_MODE_IT ((uint32_t)0x00010000U)
AnnaBridge 189:f392fc9709a3 49 #define PVD_MODE_EVT ((uint32_t)0x00020000U)
AnnaBridge 189:f392fc9709a3 50 #define PVD_RISING_EDGE ((uint32_t)0x00000001U)
AnnaBridge 189:f392fc9709a3 51 #define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
AnnaBridge 189:f392fc9709a3 52 #define PVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)
AnnaBridge 189:f392fc9709a3 53 /**
AnnaBridge 189:f392fc9709a3 54 * @}
AnnaBridge 189:f392fc9709a3 55 */
AnnaBridge 189:f392fc9709a3 56
AnnaBridge 189:f392fc9709a3 57 /**
AnnaBridge 189:f392fc9709a3 58 * @}
AnnaBridge 189:f392fc9709a3 59 */
AnnaBridge 189:f392fc9709a3 60 /* Private macro -------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 61 /* Private variables ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 62 /* Private function prototypes -----------------------------------------------*/
AnnaBridge 189:f392fc9709a3 63 /* Private functions ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 64
AnnaBridge 189:f392fc9709a3 65 /** @defgroup PWR_Exported_Functions PWR Exported Functions
AnnaBridge 189:f392fc9709a3 66 * @{
AnnaBridge 189:f392fc9709a3 67 */
AnnaBridge 189:f392fc9709a3 68
AnnaBridge 189:f392fc9709a3 69 /** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
AnnaBridge 189:f392fc9709a3 70 * @brief Initialization and De-Initialization functions
AnnaBridge 189:f392fc9709a3 71 *
AnnaBridge 189:f392fc9709a3 72 @verbatim
AnnaBridge 189:f392fc9709a3 73 ===============================================================================
AnnaBridge 189:f392fc9709a3 74 ##### Initialization and De-Initialization functions #####
AnnaBridge 189:f392fc9709a3 75 ===============================================================================
AnnaBridge 189:f392fc9709a3 76 [..]
AnnaBridge 189:f392fc9709a3 77 After reset, the backup domain (RTC registers, RTC backup data
AnnaBridge 189:f392fc9709a3 78 registers and backup SRAM) is protected against possible unwanted
AnnaBridge 189:f392fc9709a3 79 write accesses.
AnnaBridge 189:f392fc9709a3 80 To enable access to the RTC Domain and RTC registers, proceed as follows:
AnnaBridge 189:f392fc9709a3 81 (+) Enable the Power Controller (PWR) APB1 interface clock using the
AnnaBridge 189:f392fc9709a3 82 __HAL_RCC_PWR_CLK_ENABLE() macro.
AnnaBridge 189:f392fc9709a3 83 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
AnnaBridge 189:f392fc9709a3 84
AnnaBridge 189:f392fc9709a3 85 @endverbatim
AnnaBridge 189:f392fc9709a3 86 * @{
AnnaBridge 189:f392fc9709a3 87 */
AnnaBridge 189:f392fc9709a3 88
AnnaBridge 189:f392fc9709a3 89 /**
AnnaBridge 189:f392fc9709a3 90 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
AnnaBridge 189:f392fc9709a3 91 * @note This functionality is not available in this product.
AnnaBridge 189:f392fc9709a3 92 * The prototype is kept just to maintain compatibility with other products.
AnnaBridge 189:f392fc9709a3 93 * @retval None
AnnaBridge 189:f392fc9709a3 94 */
AnnaBridge 189:f392fc9709a3 95 void HAL_PWR_DeInit(void)
AnnaBridge 189:f392fc9709a3 96 {
AnnaBridge 189:f392fc9709a3 97 }
AnnaBridge 189:f392fc9709a3 98
AnnaBridge 189:f392fc9709a3 99 /**
AnnaBridge 189:f392fc9709a3 100 * @brief Enable access to the backup domain (RTC registers, RTC
AnnaBridge 189:f392fc9709a3 101 * backup data registers and backup SRAM).
AnnaBridge 189:f392fc9709a3 102 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
AnnaBridge 189:f392fc9709a3 103 * Backup Domain Access should be kept enabled.
AnnaBridge 189:f392fc9709a3 104 * @retval None
AnnaBridge 189:f392fc9709a3 105 */
AnnaBridge 189:f392fc9709a3 106 void HAL_PWR_EnableBkUpAccess(void)
AnnaBridge 189:f392fc9709a3 107 {
AnnaBridge 189:f392fc9709a3 108 /* Enable access to RTC and backup registers */
AnnaBridge 189:f392fc9709a3 109 SET_BIT(PWR->CR1, PWR_CR1_DBP);
AnnaBridge 189:f392fc9709a3 110 }
AnnaBridge 189:f392fc9709a3 111
AnnaBridge 189:f392fc9709a3 112 /**
AnnaBridge 189:f392fc9709a3 113 * @brief Disable access to the backup domain (RTC registers, RTC
AnnaBridge 189:f392fc9709a3 114 * backup data registers and backup SRAM).
AnnaBridge 189:f392fc9709a3 115 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
AnnaBridge 189:f392fc9709a3 116 * Backup Domain Access should be kept enabled.
AnnaBridge 189:f392fc9709a3 117 * @retval None
AnnaBridge 189:f392fc9709a3 118 */
AnnaBridge 189:f392fc9709a3 119 void HAL_PWR_DisableBkUpAccess(void)
AnnaBridge 189:f392fc9709a3 120 {
AnnaBridge 189:f392fc9709a3 121 /* Disable access to RTC and backup registers */
AnnaBridge 189:f392fc9709a3 122 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
AnnaBridge 189:f392fc9709a3 123 }
AnnaBridge 189:f392fc9709a3 124
AnnaBridge 189:f392fc9709a3 125 /**
AnnaBridge 189:f392fc9709a3 126 * @}
AnnaBridge 189:f392fc9709a3 127 */
AnnaBridge 189:f392fc9709a3 128
AnnaBridge 189:f392fc9709a3 129 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
AnnaBridge 189:f392fc9709a3 130 * @brief Low Power modes configuration functions
AnnaBridge 189:f392fc9709a3 131 *
AnnaBridge 189:f392fc9709a3 132 @verbatim
AnnaBridge 189:f392fc9709a3 133
AnnaBridge 189:f392fc9709a3 134 ===============================================================================
AnnaBridge 189:f392fc9709a3 135 ##### Peripheral Control functions #####
AnnaBridge 189:f392fc9709a3 136 ===============================================================================
AnnaBridge 189:f392fc9709a3 137
AnnaBridge 189:f392fc9709a3 138 *** PVD configuration ***
AnnaBridge 189:f392fc9709a3 139 =========================
AnnaBridge 189:f392fc9709a3 140 [..]
AnnaBridge 189:f392fc9709a3 141 (+) The PVD is used to monitor the VDD power supply by comparing it to a
AnnaBridge 189:f392fc9709a3 142 threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 register).
AnnaBridge 189:f392fc9709a3 143 (+) A PVDO flag is available to indicate if VDD is higher or lower
AnnaBridge 189:f392fc9709a3 144 than the PVD threshold. This event is internally connected to the EXTI
AnnaBridge 189:f392fc9709a3 145 line 16 to generate an interrupt if enabled.
AnnaBridge 189:f392fc9709a3 146 It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
AnnaBridge 189:f392fc9709a3 147 (+) The PVD is stopped in Standby mode.
AnnaBridge 189:f392fc9709a3 148
AnnaBridge 189:f392fc9709a3 149 *** Wake-up pin configuration ***
AnnaBridge 189:f392fc9709a3 150 ================================
AnnaBridge 189:f392fc9709a3 151 [..]
AnnaBridge 189:f392fc9709a3 152 (+) Wake-up pin is used to wake up the system from Standby mode.
AnnaBridge 189:f392fc9709a3 153 The pin pull is configurable through the WKUPEPR register to be in No pull-up, Pull-up and Pull-down.
AnnaBridge 189:f392fc9709a3 154 The pin polarity is configurable through the WKUPEPR register to be active on rising or falling edges.
AnnaBridge 189:f392fc9709a3 155 (+) There are up to six Wake-up pin in the STM32H7 devices family.
AnnaBridge 189:f392fc9709a3 156
AnnaBridge 189:f392fc9709a3 157 *** Low Power modes configuration ***
AnnaBridge 189:f392fc9709a3 158 =====================================
AnnaBridge 189:f392fc9709a3 159 [..]
AnnaBridge 189:f392fc9709a3 160 The device present 3 principles low-power modes features:
AnnaBridge 189:f392fc9709a3 161 (+) SLEEP mode: Cortex-M7 core stopped and D1, D2 and D3 peripherals kept running.
AnnaBridge 189:f392fc9709a3 162 (+) STOP mode: all clocks are stopped and the regulator is running in main or low power mode.
AnnaBridge 189:f392fc9709a3 163 (+) STANDBY mode: D1, D2 and D3 domains enter DSTANDBY mode and the VCORE supply
AnnaBridge 189:f392fc9709a3 164 regulator is powered off.
AnnaBridge 189:f392fc9709a3 165
AnnaBridge 189:f392fc9709a3 166 *** SLEEP mode ***
AnnaBridge 189:f392fc9709a3 167 ==================
AnnaBridge 189:f392fc9709a3 168 [..]
AnnaBridge 189:f392fc9709a3 169 (+) Entry:
AnnaBridge 189:f392fc9709a3 170 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry)
AnnaBridge 189:f392fc9709a3 171 function.
AnnaBridge 189:f392fc9709a3 172
AnnaBridge 189:f392fc9709a3 173 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
AnnaBridge 189:f392fc9709a3 174 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
AnnaBridge 189:f392fc9709a3 175
AnnaBridge 189:f392fc9709a3 176 -@@- The Regulator parameter is not used for the STM32H7 family
AnnaBridge 189:f392fc9709a3 177 and is kept as parameter just to maintain compatibility with the
AnnaBridge 189:f392fc9709a3 178 lower power families (STM32L).
AnnaBridge 189:f392fc9709a3 179 (+) Exit:
AnnaBridge 189:f392fc9709a3 180 Any peripheral interrupt acknowledged by the nested vectored interrupt
AnnaBridge 189:f392fc9709a3 181 controller (NVIC) can wake up the device from Sleep mode.
AnnaBridge 189:f392fc9709a3 182
AnnaBridge 189:f392fc9709a3 183 *** STOP mode ***
AnnaBridge 189:f392fc9709a3 184 =================
AnnaBridge 189:f392fc9709a3 185 [..]
AnnaBridge 189:f392fc9709a3 186 In system Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
AnnaBridge 189:f392fc9709a3 187 and the HSE RC oscillators are disabled. Internal SRAM and register contents
AnnaBridge 189:f392fc9709a3 188 are preserved.
AnnaBridge 189:f392fc9709a3 189 The voltage regulator can be configured either in normal or low-power mode.
AnnaBridge 189:f392fc9709a3 190 To minimize the consumption In Stop mode, FLASH can be powered off before
AnnaBridge 189:f392fc9709a3 191 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
AnnaBridge 189:f392fc9709a3 192 It can be switched on again by software after exiting the Stop mode using
AnnaBridge 189:f392fc9709a3 193 the HAL_PWREx_DisableFlashPowerDown() function.
AnnaBridge 189:f392fc9709a3 194
AnnaBridge 189:f392fc9709a3 195 (+) Entry:
AnnaBridge 189:f392fc9709a3 196 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry)
AnnaBridge 189:f392fc9709a3 197 function with:
AnnaBridge 189:f392fc9709a3 198 (++) Regulator:
AnnaBridge 189:f392fc9709a3 199 (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
AnnaBridge 189:f392fc9709a3 200 (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
AnnaBridge 189:f392fc9709a3 201 (++) STOPEntry:
AnnaBridge 189:f392fc9709a3 202 (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
AnnaBridge 189:f392fc9709a3 203 (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
AnnaBridge 189:f392fc9709a3 204 (+) Exit:
AnnaBridge 189:f392fc9709a3 205 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
AnnaBridge 189:f392fc9709a3 206
AnnaBridge 189:f392fc9709a3 207 *** STANDBY mode ***
AnnaBridge 189:f392fc9709a3 208 ====================
AnnaBridge 189:f392fc9709a3 209 [..]
AnnaBridge 189:f392fc9709a3 210 (+)
AnnaBridge 189:f392fc9709a3 211 The system Standby mode allows to achieve the lowest power consumption. It is based
AnnaBridge 189:f392fc9709a3 212 on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
AnnaBridge 189:f392fc9709a3 213 The system is consequently powered off. The PLL, the HSI oscillator and
AnnaBridge 189:f392fc9709a3 214 the HSE oscillator are also switched off. SRAM and register contents are lost
AnnaBridge 189:f392fc9709a3 215 except for the RTC registers, RTC backup registers, backup SRAM and Standby
AnnaBridge 189:f392fc9709a3 216 circuitry.
AnnaBridge 189:f392fc9709a3 217 [..]
AnnaBridge 189:f392fc9709a3 218 The voltage regulator is OFF.
AnnaBridge 189:f392fc9709a3 219 (++) Entry:
AnnaBridge 189:f392fc9709a3 220 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
AnnaBridge 189:f392fc9709a3 221 (++) Exit:
AnnaBridge 189:f392fc9709a3 222 (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
AnnaBridge 189:f392fc9709a3 223 wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
AnnaBridge 189:f392fc9709a3 224
AnnaBridge 189:f392fc9709a3 225 *** Auto-wakeup (AWU) from low-power mode ***
AnnaBridge 189:f392fc9709a3 226 =============================================
AnnaBridge 189:f392fc9709a3 227 [..]
AnnaBridge 189:f392fc9709a3 228 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
AnnaBridge 189:f392fc9709a3 229 Wakeup event, a tamper event or a time-stamp event, without depending on
AnnaBridge 189:f392fc9709a3 230 an external interrupt (Auto-wakeup mode).
AnnaBridge 189:f392fc9709a3 231 (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
AnnaBridge 189:f392fc9709a3 232 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
AnnaBridge 189:f392fc9709a3 233 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
AnnaBridge 189:f392fc9709a3 234 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
AnnaBridge 189:f392fc9709a3 235 is necessary to configure the RTC to detect the tamper or time stamp event using the
AnnaBridge 189:f392fc9709a3 236 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
AnnaBridge 189:f392fc9709a3 237 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
AnnaBridge 189:f392fc9709a3 238 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
AnnaBridge 189:f392fc9709a3 239
AnnaBridge 189:f392fc9709a3 240 @endverbatim
AnnaBridge 189:f392fc9709a3 241 * @{
AnnaBridge 189:f392fc9709a3 242 */
AnnaBridge 189:f392fc9709a3 243
AnnaBridge 189:f392fc9709a3 244 /**
AnnaBridge 189:f392fc9709a3 245 * @brief Configure the voltage threshold detected by the Power Voltage Detector(PVD).
AnnaBridge 189:f392fc9709a3 246 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
AnnaBridge 189:f392fc9709a3 247 * information for the PVD.
AnnaBridge 189:f392fc9709a3 248 * @note Refer to the electrical characteristics of your device datasheet for
AnnaBridge 189:f392fc9709a3 249 * more details about the voltage threshold corresponding to each
AnnaBridge 189:f392fc9709a3 250 * detection level.
AnnaBridge 189:f392fc9709a3 251 * @retval None
AnnaBridge 189:f392fc9709a3 252 */
AnnaBridge 189:f392fc9709a3 253 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
AnnaBridge 189:f392fc9709a3 254 {
AnnaBridge 189:f392fc9709a3 255 /* Check the parameters */
AnnaBridge 189:f392fc9709a3 256 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
AnnaBridge 189:f392fc9709a3 257 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
AnnaBridge 189:f392fc9709a3 258
AnnaBridge 189:f392fc9709a3 259 /* Set PLS[7:5] bits according to PVDLevel value */
AnnaBridge 189:f392fc9709a3 260 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
AnnaBridge 189:f392fc9709a3 261
AnnaBridge 189:f392fc9709a3 262 /* Clear any previous config */
AnnaBridge 189:f392fc9709a3 263 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
AnnaBridge 189:f392fc9709a3 264 __HAL_PWR_PVD_EXTI_DISABLE_IT();
AnnaBridge 189:f392fc9709a3 265 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
AnnaBridge 189:f392fc9709a3 266 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
AnnaBridge 189:f392fc9709a3 267
AnnaBridge 189:f392fc9709a3 268 /* Configure interrupt mode */
AnnaBridge 189:f392fc9709a3 269 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
AnnaBridge 189:f392fc9709a3 270 {
AnnaBridge 189:f392fc9709a3 271 __HAL_PWR_PVD_EXTI_ENABLE_IT();
AnnaBridge 189:f392fc9709a3 272 }
AnnaBridge 189:f392fc9709a3 273
AnnaBridge 189:f392fc9709a3 274 /* Configure event mode */
AnnaBridge 189:f392fc9709a3 275 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
AnnaBridge 189:f392fc9709a3 276 {
AnnaBridge 189:f392fc9709a3 277 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
AnnaBridge 189:f392fc9709a3 278 }
AnnaBridge 189:f392fc9709a3 279
AnnaBridge 189:f392fc9709a3 280 /* Configure the edge */
AnnaBridge 189:f392fc9709a3 281 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
AnnaBridge 189:f392fc9709a3 282 {
AnnaBridge 189:f392fc9709a3 283 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
AnnaBridge 189:f392fc9709a3 284 }
AnnaBridge 189:f392fc9709a3 285
AnnaBridge 189:f392fc9709a3 286 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
AnnaBridge 189:f392fc9709a3 287 {
AnnaBridge 189:f392fc9709a3 288 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
AnnaBridge 189:f392fc9709a3 289 }
AnnaBridge 189:f392fc9709a3 290 }
AnnaBridge 189:f392fc9709a3 291
AnnaBridge 189:f392fc9709a3 292 /**
AnnaBridge 189:f392fc9709a3 293 * @brief Enable the Power Voltage Detector(PVD).
AnnaBridge 189:f392fc9709a3 294 * @retval None
AnnaBridge 189:f392fc9709a3 295 */
AnnaBridge 189:f392fc9709a3 296 void HAL_PWR_EnablePVD(void)
AnnaBridge 189:f392fc9709a3 297 {
AnnaBridge 189:f392fc9709a3 298 /* Enable the power voltage detector */
AnnaBridge 189:f392fc9709a3 299 SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
AnnaBridge 189:f392fc9709a3 300 }
AnnaBridge 189:f392fc9709a3 301
AnnaBridge 189:f392fc9709a3 302 /**
AnnaBridge 189:f392fc9709a3 303 * @brief Disable the Power Voltage Detector(PVD).
AnnaBridge 189:f392fc9709a3 304 * @retval None
AnnaBridge 189:f392fc9709a3 305 */
AnnaBridge 189:f392fc9709a3 306 void HAL_PWR_DisablePVD(void)
AnnaBridge 189:f392fc9709a3 307 {
AnnaBridge 189:f392fc9709a3 308 /* Disable the power voltage detector */
AnnaBridge 189:f392fc9709a3 309 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
AnnaBridge 189:f392fc9709a3 310 }
AnnaBridge 189:f392fc9709a3 311
AnnaBridge 189:f392fc9709a3 312 /**
AnnaBridge 189:f392fc9709a3 313 * @brief Enable the WakeUp PINx functionality.
AnnaBridge 189:f392fc9709a3 314 * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
AnnaBridge 189:f392fc9709a3 315 * This parameter can be one of the following legacy values, which sets the default:
AnnaBridge 189:f392fc9709a3 316 * polarity detection on high level (rising edge):
AnnaBridge 189:f392fc9709a3 317 * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4,
AnnaBridge 189:f392fc9709a3 318 * PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 or one of the following values where
AnnaBridge 189:f392fc9709a3 319 * the user can explicitly states the enabled pin and the chosen polarity.
AnnaBridge 189:f392fc9709a3 320 * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
AnnaBridge 189:f392fc9709a3 321 * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
AnnaBridge 189:f392fc9709a3 322 * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
AnnaBridge 189:f392fc9709a3 323 * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
AnnaBridge 189:f392fc9709a3 324 * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
AnnaBridge 189:f392fc9709a3 325 * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
AnnaBridge 189:f392fc9709a3 326 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
AnnaBridge 189:f392fc9709a3 327 * @retval None
AnnaBridge 189:f392fc9709a3 328 */
AnnaBridge 189:f392fc9709a3 329 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
AnnaBridge 189:f392fc9709a3 330 {
AnnaBridge 189:f392fc9709a3 331 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
AnnaBridge 189:f392fc9709a3 332
AnnaBridge 189:f392fc9709a3 333 /* Enable and Specify the Wake-Up pin polarity and the pull configuration
AnnaBridge 189:f392fc9709a3 334 for the event detection (rising or falling edge) */
AnnaBridge 189:f392fc9709a3 335 MODIFY_REG(PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
AnnaBridge 189:f392fc9709a3 336 }
AnnaBridge 189:f392fc9709a3 337
AnnaBridge 189:f392fc9709a3 338 /**
AnnaBridge 189:f392fc9709a3 339 * @brief Disable the WakeUp PINx functionality.
AnnaBridge 189:f392fc9709a3 340 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
AnnaBridge 189:f392fc9709a3 341 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 342 * @arg PWR_WAKEUP_PIN1
AnnaBridge 189:f392fc9709a3 343 * @arg PWR_WAKEUP_PIN2
AnnaBridge 189:f392fc9709a3 344 * @arg PWR_WAKEUP_PIN3
AnnaBridge 189:f392fc9709a3 345 * @arg PWR_WAKEUP_PIN4
AnnaBridge 189:f392fc9709a3 346 * @arg PWR_WAKEUP_PIN5
AnnaBridge 189:f392fc9709a3 347 * @arg PWR_WAKEUP_PIN6
AnnaBridge 189:f392fc9709a3 348 * @retval None
AnnaBridge 189:f392fc9709a3 349 */
AnnaBridge 189:f392fc9709a3 350 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
AnnaBridge 189:f392fc9709a3 351 {
AnnaBridge 189:f392fc9709a3 352 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
AnnaBridge 189:f392fc9709a3 353
AnnaBridge 189:f392fc9709a3 354 CLEAR_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
AnnaBridge 189:f392fc9709a3 355 }
AnnaBridge 189:f392fc9709a3 356
AnnaBridge 189:f392fc9709a3 357 /**
AnnaBridge 189:f392fc9709a3 358 * @brief Enter the current core to Sleep mode.
AnnaBridge 189:f392fc9709a3 359 * @param Regulator: Specifies the regulator state in SLEEP mode.
AnnaBridge 189:f392fc9709a3 360 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 361 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
AnnaBridge 189:f392fc9709a3 362 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
AnnaBridge 189:f392fc9709a3 363 * @note This parameter is not used for the STM32H7 family and is kept as parameter
AnnaBridge 189:f392fc9709a3 364 * just to maintain compatibility with the lower power families.
AnnaBridge 189:f392fc9709a3 365 * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
AnnaBridge 189:f392fc9709a3 366 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 367 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
AnnaBridge 189:f392fc9709a3 368 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
AnnaBridge 189:f392fc9709a3 369 * @retval None
AnnaBridge 189:f392fc9709a3 370 */
AnnaBridge 189:f392fc9709a3 371 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
AnnaBridge 189:f392fc9709a3 372 {
AnnaBridge 189:f392fc9709a3 373 /* Check the parameters */
AnnaBridge 189:f392fc9709a3 374 assert_param(IS_PWR_REGULATOR(Regulator));
AnnaBridge 189:f392fc9709a3 375 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
AnnaBridge 189:f392fc9709a3 376
AnnaBridge 189:f392fc9709a3 377 /* Clear SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 378 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 189:f392fc9709a3 379
AnnaBridge 189:f392fc9709a3 380 /* Select SLEEP mode entry */
AnnaBridge 189:f392fc9709a3 381 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
AnnaBridge 189:f392fc9709a3 382 {
AnnaBridge 189:f392fc9709a3 383 /* Request Wait For Interrupt */
AnnaBridge 189:f392fc9709a3 384 __WFI();
AnnaBridge 189:f392fc9709a3 385 }
AnnaBridge 189:f392fc9709a3 386 else
AnnaBridge 189:f392fc9709a3 387 {
AnnaBridge 189:f392fc9709a3 388 /* Request Wait For Event */
AnnaBridge 189:f392fc9709a3 389 __WFE();
AnnaBridge 189:f392fc9709a3 390 }
AnnaBridge 189:f392fc9709a3 391 }
AnnaBridge 189:f392fc9709a3 392
AnnaBridge 189:f392fc9709a3 393 /**
AnnaBridge 189:f392fc9709a3 394 * @brief Enter the system to STOP mode.
AnnaBridge 189:f392fc9709a3 395 * @note This API must be used only for single core devices.
AnnaBridge 189:f392fc9709a3 396 * @note In System Stop mode, all I/O pins keep the same state as in Run mode.
AnnaBridge 189:f392fc9709a3 397 * @note When exiting System Stop mode by issuing an interrupt or a wakeup event,
AnnaBridge 189:f392fc9709a3 398 * the HSI RC oscillator is selected as default system wakeup clock.
AnnaBridge 189:f392fc9709a3 399 * @note In System STOP mode, when the voltage regulator operates in low power mode,
AnnaBridge 189:f392fc9709a3 400 * an additional startup delay is incurred when the system is waking up.
AnnaBridge 189:f392fc9709a3 401 * By keeping the internal regulator ON during Stop mode, the consumption
AnnaBridge 189:f392fc9709a3 402 * is higher although the startup time is reduced.
AnnaBridge 189:f392fc9709a3 403 * @param Regulator: Specifies the regulator state in Stop mode.
AnnaBridge 189:f392fc9709a3 404 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 405 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
AnnaBridge 189:f392fc9709a3 406 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
AnnaBridge 189:f392fc9709a3 407 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
AnnaBridge 189:f392fc9709a3 408 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 409 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
AnnaBridge 189:f392fc9709a3 410 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
AnnaBridge 189:f392fc9709a3 411 * @retval None
AnnaBridge 189:f392fc9709a3 412 */
AnnaBridge 189:f392fc9709a3 413 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
AnnaBridge 189:f392fc9709a3 414 {
AnnaBridge 189:f392fc9709a3 415 uint32_t tmpreg;
AnnaBridge 189:f392fc9709a3 416
AnnaBridge 189:f392fc9709a3 417 /* Check the parameters */
AnnaBridge 189:f392fc9709a3 418 assert_param(IS_PWR_REGULATOR(Regulator));
AnnaBridge 189:f392fc9709a3 419 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
AnnaBridge 189:f392fc9709a3 420
AnnaBridge 189:f392fc9709a3 421 /* Select the regulator state in Stop mode */
AnnaBridge 189:f392fc9709a3 422 tmpreg = PWR->CR1;
AnnaBridge 189:f392fc9709a3 423 /* Clear PDDS and LPDS bits */
AnnaBridge 189:f392fc9709a3 424 tmpreg &= (uint32_t)~(PWR_CR1_LPDS);
AnnaBridge 189:f392fc9709a3 425
AnnaBridge 189:f392fc9709a3 426 /* Set LPDS bit according to Regulator value */
AnnaBridge 189:f392fc9709a3 427 tmpreg |= Regulator;
AnnaBridge 189:f392fc9709a3 428
AnnaBridge 189:f392fc9709a3 429 /* Store the new value */
AnnaBridge 189:f392fc9709a3 430 PWR->CR1 = tmpreg;
AnnaBridge 189:f392fc9709a3 431
AnnaBridge 189:f392fc9709a3 432 /* Keep DSTOP mode when D1 domain enters Deepsleep */
AnnaBridge 189:f392fc9709a3 433 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
AnnaBridge 189:f392fc9709a3 434
AnnaBridge 189:f392fc9709a3 435 /* Keep DSTOP mode when D2 domain enters Deepsleep */
AnnaBridge 189:f392fc9709a3 436 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
AnnaBridge 189:f392fc9709a3 437
AnnaBridge 189:f392fc9709a3 438 /* Keep DSTOP mode when D3 domain enters Deepsleep */
AnnaBridge 189:f392fc9709a3 439 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
AnnaBridge 189:f392fc9709a3 440
AnnaBridge 189:f392fc9709a3 441 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 442 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
AnnaBridge 189:f392fc9709a3 443
AnnaBridge 189:f392fc9709a3 444 /* Ensure that all instructions done before entering STOP mode */
AnnaBridge 189:f392fc9709a3 445 __DSB();
AnnaBridge 189:f392fc9709a3 446 __ISB();
AnnaBridge 189:f392fc9709a3 447
AnnaBridge 189:f392fc9709a3 448 /* Select Stop mode entry */
AnnaBridge 189:f392fc9709a3 449 if(STOPEntry == PWR_STOPENTRY_WFI)
AnnaBridge 189:f392fc9709a3 450 {
AnnaBridge 189:f392fc9709a3 451 /* Request Wait For Interrupt */
AnnaBridge 189:f392fc9709a3 452 __WFI();
AnnaBridge 189:f392fc9709a3 453 }
AnnaBridge 189:f392fc9709a3 454 else
AnnaBridge 189:f392fc9709a3 455 {
AnnaBridge 189:f392fc9709a3 456 /* Request Wait For Event */
AnnaBridge 189:f392fc9709a3 457 __WFE();
AnnaBridge 189:f392fc9709a3 458 }
AnnaBridge 189:f392fc9709a3 459 /* Reset SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 460 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
AnnaBridge 189:f392fc9709a3 461 }
AnnaBridge 189:f392fc9709a3 462
AnnaBridge 189:f392fc9709a3 463 /**
AnnaBridge 189:f392fc9709a3 464 * @brief Enter the system to STANDBY mode.
AnnaBridge 189:f392fc9709a3 465 * @note The system enters Standby mode only when the D1, D2 and D3 domains are in DStandby.
AnnaBridge 189:f392fc9709a3 466 * @note When the System exit STANDBY mode by issuing an interrupt or a wakeup event,
AnnaBridge 189:f392fc9709a3 467 * the HSI RC oscillator is selected as system clock.
AnnaBridge 189:f392fc9709a3 468 * @retval None.
AnnaBridge 189:f392fc9709a3 469 */
AnnaBridge 189:f392fc9709a3 470 void HAL_PWR_EnterSTANDBYMode(void)
AnnaBridge 189:f392fc9709a3 471 {
AnnaBridge 189:f392fc9709a3 472 /* Keep DSTANDBY mode when D1 domain enters Deepsleep */
AnnaBridge 189:f392fc9709a3 473 SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
AnnaBridge 189:f392fc9709a3 474
AnnaBridge 189:f392fc9709a3 475 /* Keep DSTANDBY mode when D2 domain enters Deepsleep */
AnnaBridge 189:f392fc9709a3 476 SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
AnnaBridge 189:f392fc9709a3 477
AnnaBridge 189:f392fc9709a3 478 /* Keep DSTANDBY mode when D3 domain enters Deepsleep */
AnnaBridge 189:f392fc9709a3 479 SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
AnnaBridge 189:f392fc9709a3 480
AnnaBridge 189:f392fc9709a3 481 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 482 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
AnnaBridge 189:f392fc9709a3 483
AnnaBridge 189:f392fc9709a3 484 /* This option is used to ensure that store operations are completed */
AnnaBridge 189:f392fc9709a3 485 #if defined ( __CC_ARM)
AnnaBridge 189:f392fc9709a3 486 __force_stores();
AnnaBridge 189:f392fc9709a3 487 #endif
AnnaBridge 189:f392fc9709a3 488 /* Request Wait For Interrupt */
AnnaBridge 189:f392fc9709a3 489 __WFI();
AnnaBridge 189:f392fc9709a3 490 }
AnnaBridge 189:f392fc9709a3 491
AnnaBridge 189:f392fc9709a3 492 /**
AnnaBridge 189:f392fc9709a3 493 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
AnnaBridge 189:f392fc9709a3 494 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
AnnaBridge 189:f392fc9709a3 495 * re-enters SLEEP mode when an interruption handling is over.
AnnaBridge 189:f392fc9709a3 496 * Setting this bit is useful when the processor is expected to run only on
AnnaBridge 189:f392fc9709a3 497 * interruptions handling.
AnnaBridge 189:f392fc9709a3 498 * @retval None
AnnaBridge 189:f392fc9709a3 499 */
AnnaBridge 189:f392fc9709a3 500 void HAL_PWR_EnableSleepOnExit(void)
AnnaBridge 189:f392fc9709a3 501 {
AnnaBridge 189:f392fc9709a3 502 /* Set SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 503 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 189:f392fc9709a3 504 }
AnnaBridge 189:f392fc9709a3 505
AnnaBridge 189:f392fc9709a3 506
AnnaBridge 189:f392fc9709a3 507 /**
AnnaBridge 189:f392fc9709a3 508 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
AnnaBridge 189:f392fc9709a3 509 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
AnnaBridge 189:f392fc9709a3 510 * re-enters SLEEP mode when an interruption handling is over.
AnnaBridge 189:f392fc9709a3 511 * @retval None
AnnaBridge 189:f392fc9709a3 512 */
AnnaBridge 189:f392fc9709a3 513 void HAL_PWR_DisableSleepOnExit(void)
AnnaBridge 189:f392fc9709a3 514 {
AnnaBridge 189:f392fc9709a3 515 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 516 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 189:f392fc9709a3 517 }
AnnaBridge 189:f392fc9709a3 518
AnnaBridge 189:f392fc9709a3 519 /**
AnnaBridge 189:f392fc9709a3 520 * @brief Enable CORTEX SEVONPEND bit.
AnnaBridge 189:f392fc9709a3 521 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
AnnaBridge 189:f392fc9709a3 522 * WFE to wake up when an interrupt moves from inactive to pended.
AnnaBridge 189:f392fc9709a3 523 * @retval None
AnnaBridge 189:f392fc9709a3 524 */
AnnaBridge 189:f392fc9709a3 525 void HAL_PWR_EnableSEVOnPend(void)
AnnaBridge 189:f392fc9709a3 526 {
AnnaBridge 189:f392fc9709a3 527 /* Set SEVONPEND bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 528 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 189:f392fc9709a3 529 }
AnnaBridge 189:f392fc9709a3 530
AnnaBridge 189:f392fc9709a3 531 /**
AnnaBridge 189:f392fc9709a3 532 * @brief Disable CORTEX SEVONPEND bit.
AnnaBridge 189:f392fc9709a3 533 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
AnnaBridge 189:f392fc9709a3 534 * WFE to wake up when an interrupt moves from inactive to pended.
AnnaBridge 189:f392fc9709a3 535 * @retval None
AnnaBridge 189:f392fc9709a3 536 */
AnnaBridge 189:f392fc9709a3 537 void HAL_PWR_DisableSEVOnPend(void)
AnnaBridge 189:f392fc9709a3 538 {
AnnaBridge 189:f392fc9709a3 539 /* Clear SEVONPEND bit of Cortex System Control Register */
AnnaBridge 189:f392fc9709a3 540 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 189:f392fc9709a3 541 }
AnnaBridge 189:f392fc9709a3 542
AnnaBridge 189:f392fc9709a3 543 /**
AnnaBridge 189:f392fc9709a3 544 * @brief This function handles the PWR PVD interrupt request.
AnnaBridge 189:f392fc9709a3 545 * @note This API should be called under the PVD_IRQHandler().
AnnaBridge 189:f392fc9709a3 546 * @retval None
AnnaBridge 189:f392fc9709a3 547 */
AnnaBridge 189:f392fc9709a3 548 void HAL_PWR_PVD_IRQHandler(void)
AnnaBridge 189:f392fc9709a3 549 {
AnnaBridge 189:f392fc9709a3 550 /* PVD EXTI line interrupt detected */
AnnaBridge 189:f392fc9709a3 551 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
AnnaBridge 189:f392fc9709a3 552 {
AnnaBridge 189:f392fc9709a3 553 /* PWR PVD interrupt user callback */
AnnaBridge 189:f392fc9709a3 554 HAL_PWR_PVDCallback();
AnnaBridge 189:f392fc9709a3 555
AnnaBridge 189:f392fc9709a3 556 /* Clear PWR EXTI pending bit */
AnnaBridge 189:f392fc9709a3 557 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
AnnaBridge 189:f392fc9709a3 558 }
AnnaBridge 189:f392fc9709a3 559 }
AnnaBridge 189:f392fc9709a3 560
AnnaBridge 189:f392fc9709a3 561 /**
AnnaBridge 189:f392fc9709a3 562 * @brief PWR PVD interrupt callback
AnnaBridge 189:f392fc9709a3 563 * @retval None
AnnaBridge 189:f392fc9709a3 564 */
AnnaBridge 189:f392fc9709a3 565 __weak void HAL_PWR_PVDCallback(void)
AnnaBridge 189:f392fc9709a3 566 {
AnnaBridge 189:f392fc9709a3 567 /* NOTE : This function Should not be modified, when the callback is needed,
AnnaBridge 189:f392fc9709a3 568 the HAL_PWR_PVDCallback could be implemented in the user file
AnnaBridge 189:f392fc9709a3 569 */
AnnaBridge 189:f392fc9709a3 570 }
AnnaBridge 189:f392fc9709a3 571
AnnaBridge 189:f392fc9709a3 572 /**
AnnaBridge 189:f392fc9709a3 573 * @}
AnnaBridge 189:f392fc9709a3 574 */
AnnaBridge 189:f392fc9709a3 575
AnnaBridge 189:f392fc9709a3 576 /**
AnnaBridge 189:f392fc9709a3 577 * @}
AnnaBridge 189:f392fc9709a3 578 */
AnnaBridge 189:f392fc9709a3 579
AnnaBridge 189:f392fc9709a3 580 #endif /* HAL_PWR_MODULE_ENABLED */
AnnaBridge 189:f392fc9709a3 581 /**
AnnaBridge 189:f392fc9709a3 582 * @}
AnnaBridge 189:f392fc9709a3 583 */
AnnaBridge 189:f392fc9709a3 584
AnnaBridge 189:f392fc9709a3 585 /**
AnnaBridge 189:f392fc9709a3 586 * @}
AnnaBridge 189:f392fc9709a3 587 */
AnnaBridge 189:f392fc9709a3 588
AnnaBridge 189:f392fc9709a3 589 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/