mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
182:a56a73fd2a6f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f767xx.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * This file contains:
<> 144:ef7eb2e8f9f7 8 * - Data structures and the address mapping for all peripherals
<> 144:ef7eb2e8f9f7 9 * - Peripheral's registers declarations and bits definition
<> 144:ef7eb2e8f9f7 10 * - Macros to access peripheral’s registers hardware
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 ******************************************************************************
<> 144:ef7eb2e8f9f7 13 * @attention
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 18 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 19 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 20 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 22 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 23 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 25 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 26 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 38 *
<> 144:ef7eb2e8f9f7 39 ******************************************************************************
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /** @addtogroup CMSIS_Device
<> 144:ef7eb2e8f9f7 43 * @{
<> 144:ef7eb2e8f9f7 44 */
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /** @addtogroup stm32f767xx
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 */
<> 161:2cc1468da177 49
<> 144:ef7eb2e8f9f7 50 #ifndef __STM32F767xx_H
<> 144:ef7eb2e8f9f7 51 #define __STM32F767xx_H
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 54 extern "C" {
<> 144:ef7eb2e8f9f7 55 #endif /* __cplusplus */
<> 161:2cc1468da177 56
<> 144:ef7eb2e8f9f7 57 /** @addtogroup Configuration_section_for_CMSIS
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /**
<> 161:2cc1468da177 62 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
<> 161:2cc1468da177 63 * in @ref Library_configuration_section
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef enum
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
<> 144:ef7eb2e8f9f7 68 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 69 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
<> 144:ef7eb2e8f9f7 70 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
<> 144:ef7eb2e8f9f7 71 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
<> 144:ef7eb2e8f9f7 72 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 73 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
<> 144:ef7eb2e8f9f7 74 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 75 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 76 /****** STM32 specific Interrupt Numbers **********************************************************************/
<> 144:ef7eb2e8f9f7 77 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 144:ef7eb2e8f9f7 78 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
<> 144:ef7eb2e8f9f7 79 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
<> 144:ef7eb2e8f9f7 80 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
<> 144:ef7eb2e8f9f7 81 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 144:ef7eb2e8f9f7 82 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 144:ef7eb2e8f9f7 83 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 144:ef7eb2e8f9f7 84 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 144:ef7eb2e8f9f7 85 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
<> 144:ef7eb2e8f9f7 86 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 144:ef7eb2e8f9f7 87 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 144:ef7eb2e8f9f7 88 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
<> 144:ef7eb2e8f9f7 89 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
<> 144:ef7eb2e8f9f7 90 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
<> 144:ef7eb2e8f9f7 91 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
<> 144:ef7eb2e8f9f7 92 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
<> 144:ef7eb2e8f9f7 93 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
<> 144:ef7eb2e8f9f7 94 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
<> 144:ef7eb2e8f9f7 95 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
<> 144:ef7eb2e8f9f7 96 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
<> 144:ef7eb2e8f9f7 97 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
<> 144:ef7eb2e8f9f7 98 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
<> 144:ef7eb2e8f9f7 99 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
<> 144:ef7eb2e8f9f7 100 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 144:ef7eb2e8f9f7 101 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
<> 144:ef7eb2e8f9f7 102 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
<> 144:ef7eb2e8f9f7 103 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
<> 144:ef7eb2e8f9f7 104 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
<> 144:ef7eb2e8f9f7 105 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 144:ef7eb2e8f9f7 106 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 144:ef7eb2e8f9f7 107 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 144:ef7eb2e8f9f7 108 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
<> 144:ef7eb2e8f9f7 109 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 144:ef7eb2e8f9f7 110 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
<> 161:2cc1468da177 111 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 144:ef7eb2e8f9f7 112 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 144:ef7eb2e8f9f7 113 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 144:ef7eb2e8f9f7 114 USART1_IRQn = 37, /*!< USART1 global Interrupt */
<> 144:ef7eb2e8f9f7 115 USART2_IRQn = 38, /*!< USART2 global Interrupt */
<> 144:ef7eb2e8f9f7 116 USART3_IRQn = 39, /*!< USART3 global Interrupt */
<> 144:ef7eb2e8f9f7 117 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 144:ef7eb2e8f9f7 118 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
<> 161:2cc1468da177 119 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
<> 144:ef7eb2e8f9f7 120 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
<> 144:ef7eb2e8f9f7 121 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
<> 144:ef7eb2e8f9f7 122 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
<> 144:ef7eb2e8f9f7 123 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
<> 144:ef7eb2e8f9f7 124 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
<> 144:ef7eb2e8f9f7 125 FMC_IRQn = 48, /*!< FMC global Interrupt */
<> 144:ef7eb2e8f9f7 126 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
<> 144:ef7eb2e8f9f7 127 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
<> 144:ef7eb2e8f9f7 128 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
<> 144:ef7eb2e8f9f7 129 UART4_IRQn = 52, /*!< UART4 global Interrupt */
<> 144:ef7eb2e8f9f7 130 UART5_IRQn = 53, /*!< UART5 global Interrupt */
<> 144:ef7eb2e8f9f7 131 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
<> 144:ef7eb2e8f9f7 132 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
<> 144:ef7eb2e8f9f7 133 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
<> 144:ef7eb2e8f9f7 134 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
<> 144:ef7eb2e8f9f7 135 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
<> 144:ef7eb2e8f9f7 136 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
<> 144:ef7eb2e8f9f7 137 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
<> 144:ef7eb2e8f9f7 138 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
<> 144:ef7eb2e8f9f7 139 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
<> 144:ef7eb2e8f9f7 140 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
<> 144:ef7eb2e8f9f7 141 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
<> 144:ef7eb2e8f9f7 142 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
<> 144:ef7eb2e8f9f7 143 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
<> 144:ef7eb2e8f9f7 144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
<> 144:ef7eb2e8f9f7 145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
<> 144:ef7eb2e8f9f7 146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
<> 144:ef7eb2e8f9f7 147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
<> 144:ef7eb2e8f9f7 148 USART6_IRQn = 71, /*!< USART6 global interrupt */
<> 144:ef7eb2e8f9f7 149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
<> 144:ef7eb2e8f9f7 150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
<> 144:ef7eb2e8f9f7 151 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
<> 144:ef7eb2e8f9f7 152 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
<> 144:ef7eb2e8f9f7 153 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
<> 144:ef7eb2e8f9f7 154 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
<> 144:ef7eb2e8f9f7 155 DCMI_IRQn = 78, /*!< DCMI global interrupt */
<> 144:ef7eb2e8f9f7 156 RNG_IRQn = 80, /*!< RNG global interrupt */
<> 144:ef7eb2e8f9f7 157 FPU_IRQn = 81, /*!< FPU global interrupt */
<> 144:ef7eb2e8f9f7 158 UART7_IRQn = 82, /*!< UART7 global interrupt */
<> 144:ef7eb2e8f9f7 159 UART8_IRQn = 83, /*!< UART8 global interrupt */
<> 144:ef7eb2e8f9f7 160 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
<> 144:ef7eb2e8f9f7 161 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
<> 144:ef7eb2e8f9f7 162 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
<> 144:ef7eb2e8f9f7 163 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
<> 144:ef7eb2e8f9f7 164 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
<> 144:ef7eb2e8f9f7 165 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
<> 144:ef7eb2e8f9f7 166 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
<> 144:ef7eb2e8f9f7 167 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
<> 144:ef7eb2e8f9f7 168 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
<> 144:ef7eb2e8f9f7 169 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
<> 144:ef7eb2e8f9f7 170 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
<> 144:ef7eb2e8f9f7 171 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
<> 144:ef7eb2e8f9f7 172 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
<> 144:ef7eb2e8f9f7 173 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
<> 144:ef7eb2e8f9f7 174 DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
<> 144:ef7eb2e8f9f7 175 DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
<> 144:ef7eb2e8f9f7 176 DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
<> 144:ef7eb2e8f9f7 177 DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
<> 144:ef7eb2e8f9f7 178 SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
<> 144:ef7eb2e8f9f7 179 CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
<> 144:ef7eb2e8f9f7 180 CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
<> 144:ef7eb2e8f9f7 181 CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
<> 144:ef7eb2e8f9f7 182 CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
<> 144:ef7eb2e8f9f7 183 JPEG_IRQn = 108, /*!< JPEG global Interrupt */
<> 144:ef7eb2e8f9f7 184 MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
<> 144:ef7eb2e8f9f7 185 } IRQn_Type;
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /**
<> 144:ef7eb2e8f9f7 188 * @}
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /**
<> 161:2cc1468da177 192 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
<> 144:ef7eb2e8f9f7 195 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
<> 144:ef7eb2e8f9f7 196 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
<> 144:ef7eb2e8f9f7 197 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 198 #define __FPU_PRESENT 1 /*!< FPU present */
<> 144:ef7eb2e8f9f7 199 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
<> 144:ef7eb2e8f9f7 200 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
<> 144:ef7eb2e8f9f7 201 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
<> 161:2cc1468da177 202
<> 161:2cc1468da177 203
<> 144:ef7eb2e8f9f7 204 #include "system_stm32f7xx.h"
<> 144:ef7eb2e8f9f7 205 #include <stdint.h>
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /** @addtogroup Peripheral_registers_structures
<> 144:ef7eb2e8f9f7 208 * @{
<> 161:2cc1468da177 209 */
<> 161:2cc1468da177 210
<> 161:2cc1468da177 211 /**
<> 161:2cc1468da177 212 * @brief Analog to Digital Converter
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 typedef struct
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
<> 161:2cc1468da177 218 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 219 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 220 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 221 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 222 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 223 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 224 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 225 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 226 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 227 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 228 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 229 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 230 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 231 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
<> 144:ef7eb2e8f9f7 232 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 233 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 234 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 235 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 236 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 237 } ADC_TypeDef;
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 typedef struct
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
<> 144:ef7eb2e8f9f7 242 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
<> 144:ef7eb2e8f9f7 243 __IO uint32_t CDR; /*!< ADC common regular data register for dual
<> 144:ef7eb2e8f9f7 244 AND triple modes, Address offset: ADC1 base address + 0x308 */
<> 144:ef7eb2e8f9f7 245 } ADC_Common_TypeDef;
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247
<> 161:2cc1468da177 248 /**
<> 161:2cc1468da177 249 * @brief Controller Area Network TxMailBox
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 typedef struct
<> 144:ef7eb2e8f9f7 253 {
<> 144:ef7eb2e8f9f7 254 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
<> 144:ef7eb2e8f9f7 255 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
<> 144:ef7eb2e8f9f7 256 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
<> 144:ef7eb2e8f9f7 257 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
<> 144:ef7eb2e8f9f7 258 } CAN_TxMailBox_TypeDef;
<> 144:ef7eb2e8f9f7 259
<> 161:2cc1468da177 260 /**
<> 161:2cc1468da177 261 * @brief Controller Area Network FIFOMailBox
<> 161:2cc1468da177 262 */
<> 161:2cc1468da177 263
<> 144:ef7eb2e8f9f7 264 typedef struct
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
<> 144:ef7eb2e8f9f7 267 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
<> 144:ef7eb2e8f9f7 268 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
<> 144:ef7eb2e8f9f7 269 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
<> 144:ef7eb2e8f9f7 270 } CAN_FIFOMailBox_TypeDef;
<> 144:ef7eb2e8f9f7 271
<> 161:2cc1468da177 272 /**
<> 161:2cc1468da177 273 * @brief Controller Area Network FilterRegister
<> 161:2cc1468da177 274 */
<> 161:2cc1468da177 275
<> 144:ef7eb2e8f9f7 276 typedef struct
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
<> 144:ef7eb2e8f9f7 279 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
<> 144:ef7eb2e8f9f7 280 } CAN_FilterRegister_TypeDef;
<> 144:ef7eb2e8f9f7 281
<> 161:2cc1468da177 282 /**
<> 161:2cc1468da177 283 * @brief Controller Area Network
<> 161:2cc1468da177 284 */
<> 161:2cc1468da177 285
<> 144:ef7eb2e8f9f7 286 typedef struct
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 289 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 290 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 291 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 292 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 293 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 294 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 295 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 296 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
<> 144:ef7eb2e8f9f7 297 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
<> 144:ef7eb2e8f9f7 298 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
<> 144:ef7eb2e8f9f7 299 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
<> 144:ef7eb2e8f9f7 300 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
<> 144:ef7eb2e8f9f7 301 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
<> 144:ef7eb2e8f9f7 302 uint32_t RESERVED2; /*!< Reserved, 0x208 */
<> 144:ef7eb2e8f9f7 303 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
<> 144:ef7eb2e8f9f7 304 uint32_t RESERVED3; /*!< Reserved, 0x210 */
<> 144:ef7eb2e8f9f7 305 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
<> 144:ef7eb2e8f9f7 306 uint32_t RESERVED4; /*!< Reserved, 0x218 */
<> 144:ef7eb2e8f9f7 307 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
<> 161:2cc1468da177 308 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
<> 144:ef7eb2e8f9f7 309 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
<> 144:ef7eb2e8f9f7 310 } CAN_TypeDef;
<> 144:ef7eb2e8f9f7 311
<> 161:2cc1468da177 312 /**
<> 161:2cc1468da177 313 * @brief HDMI-CEC
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 typedef struct
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
<> 144:ef7eb2e8f9f7 319 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
<> 144:ef7eb2e8f9f7 320 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
<> 144:ef7eb2e8f9f7 321 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
<> 144:ef7eb2e8f9f7 322 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
<> 144:ef7eb2e8f9f7 323 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
<> 144:ef7eb2e8f9f7 324 }CEC_TypeDef;
<> 144:ef7eb2e8f9f7 325
<> 161:2cc1468da177 326 /**
<> 161:2cc1468da177 327 * @brief CRC calculation unit
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 typedef struct
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 333 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 334 uint8_t RESERVED0; /*!< Reserved, 0x05 */
<> 144:ef7eb2e8f9f7 335 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 144:ef7eb2e8f9f7 336 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 337 uint32_t RESERVED2; /*!< Reserved, 0x0C */
<> 144:ef7eb2e8f9f7 338 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 339 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 340 } CRC_TypeDef;
<> 144:ef7eb2e8f9f7 341
<> 161:2cc1468da177 342 /**
<> 144:ef7eb2e8f9f7 343 * @brief Digital to Analog Converter
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 typedef struct
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 349 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 350 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 351 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 352 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 353 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 354 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 355 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 356 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 357 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 358 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 359 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 360 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 361 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 362 } DAC_TypeDef;
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @brief DFSDM module registers
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 typedef struct
<> 144:ef7eb2e8f9f7 368 {
<> 144:ef7eb2e8f9f7 369 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
<> 144:ef7eb2e8f9f7 370 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
<> 144:ef7eb2e8f9f7 371 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
<> 144:ef7eb2e8f9f7 372 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
<> 144:ef7eb2e8f9f7 373 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
<> 144:ef7eb2e8f9f7 374 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
<> 144:ef7eb2e8f9f7 375 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
<> 144:ef7eb2e8f9f7 376 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
<> 144:ef7eb2e8f9f7 377 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
<> 144:ef7eb2e8f9f7 378 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
<> 144:ef7eb2e8f9f7 379 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
<> 144:ef7eb2e8f9f7 380 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
<> 144:ef7eb2e8f9f7 381 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
<> 144:ef7eb2e8f9f7 382 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
<> 144:ef7eb2e8f9f7 383 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
<> 144:ef7eb2e8f9f7 384 } DFSDM_Filter_TypeDef;
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /**
<> 144:ef7eb2e8f9f7 387 * @brief DFSDM channel configuration registers
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389 typedef struct
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 392 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 393 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
<> 144:ef7eb2e8f9f7 394 short circuit detector register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 395 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 396 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 397 } DFSDM_Channel_TypeDef;
<> 144:ef7eb2e8f9f7 398
<> 161:2cc1468da177 399 /**
<> 144:ef7eb2e8f9f7 400 * @brief Debug MCU
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 typedef struct
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 406 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 407 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 408 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 409 }DBGMCU_TypeDef;
<> 144:ef7eb2e8f9f7 410
<> 161:2cc1468da177 411 /**
<> 144:ef7eb2e8f9f7 412 * @brief DCMI
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 typedef struct
<> 144:ef7eb2e8f9f7 416 {
<> 144:ef7eb2e8f9f7 417 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 418 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 419 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 420 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 421 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 422 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 423 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 424 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 425 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 426 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 427 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 428 } DCMI_TypeDef;
<> 144:ef7eb2e8f9f7 429
<> 161:2cc1468da177 430 /**
<> 144:ef7eb2e8f9f7 431 * @brief DMA Controller
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 typedef struct
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 __IO uint32_t CR; /*!< DMA stream x configuration register */
<> 144:ef7eb2e8f9f7 437 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
<> 144:ef7eb2e8f9f7 438 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
<> 144:ef7eb2e8f9f7 439 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
<> 144:ef7eb2e8f9f7 440 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
<> 144:ef7eb2e8f9f7 441 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
<> 144:ef7eb2e8f9f7 442 } DMA_Stream_TypeDef;
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 typedef struct
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 447 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 448 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 449 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 450 } DMA_TypeDef;
<> 144:ef7eb2e8f9f7 451
<> 161:2cc1468da177 452 /**
<> 144:ef7eb2e8f9f7 453 * @brief DMA2D Controller
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 typedef struct
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 459 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 460 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 461 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 462 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 463 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 464 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 465 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 466 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 467 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 468 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 469 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 470 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 471 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 472 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 473 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 474 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 475 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 476 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 477 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 478 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
<> 144:ef7eb2e8f9f7 479 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
<> 144:ef7eb2e8f9f7 480 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
<> 144:ef7eb2e8f9f7 481 } DMA2D_TypeDef;
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483
<> 161:2cc1468da177 484 /**
<> 144:ef7eb2e8f9f7 485 * @brief Ethernet MAC
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 typedef struct
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 __IO uint32_t MACCR;
<> 144:ef7eb2e8f9f7 491 __IO uint32_t MACFFR;
<> 144:ef7eb2e8f9f7 492 __IO uint32_t MACHTHR;
<> 144:ef7eb2e8f9f7 493 __IO uint32_t MACHTLR;
<> 144:ef7eb2e8f9f7 494 __IO uint32_t MACMIIAR;
<> 144:ef7eb2e8f9f7 495 __IO uint32_t MACMIIDR;
<> 144:ef7eb2e8f9f7 496 __IO uint32_t MACFCR;
<> 144:ef7eb2e8f9f7 497 __IO uint32_t MACVLANTR; /* 8 */
<> 144:ef7eb2e8f9f7 498 uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 499 __IO uint32_t MACRWUFFR; /* 11 */
<> 144:ef7eb2e8f9f7 500 __IO uint32_t MACPMTCSR;
<> 161:2cc1468da177 501 uint32_t RESERVED1;
<> 161:2cc1468da177 502 __IO uint32_t MACDBGR;
<> 144:ef7eb2e8f9f7 503 __IO uint32_t MACSR; /* 15 */
<> 144:ef7eb2e8f9f7 504 __IO uint32_t MACIMR;
<> 144:ef7eb2e8f9f7 505 __IO uint32_t MACA0HR;
<> 144:ef7eb2e8f9f7 506 __IO uint32_t MACA0LR;
<> 144:ef7eb2e8f9f7 507 __IO uint32_t MACA1HR;
<> 144:ef7eb2e8f9f7 508 __IO uint32_t MACA1LR;
<> 144:ef7eb2e8f9f7 509 __IO uint32_t MACA2HR;
<> 144:ef7eb2e8f9f7 510 __IO uint32_t MACA2LR;
<> 144:ef7eb2e8f9f7 511 __IO uint32_t MACA3HR;
<> 144:ef7eb2e8f9f7 512 __IO uint32_t MACA3LR; /* 24 */
<> 144:ef7eb2e8f9f7 513 uint32_t RESERVED2[40];
<> 144:ef7eb2e8f9f7 514 __IO uint32_t MMCCR; /* 65 */
<> 144:ef7eb2e8f9f7 515 __IO uint32_t MMCRIR;
<> 144:ef7eb2e8f9f7 516 __IO uint32_t MMCTIR;
<> 144:ef7eb2e8f9f7 517 __IO uint32_t MMCRIMR;
<> 144:ef7eb2e8f9f7 518 __IO uint32_t MMCTIMR; /* 69 */
<> 144:ef7eb2e8f9f7 519 uint32_t RESERVED3[14];
<> 144:ef7eb2e8f9f7 520 __IO uint32_t MMCTGFSCCR; /* 84 */
<> 144:ef7eb2e8f9f7 521 __IO uint32_t MMCTGFMSCCR;
<> 144:ef7eb2e8f9f7 522 uint32_t RESERVED4[5];
<> 144:ef7eb2e8f9f7 523 __IO uint32_t MMCTGFCR;
<> 144:ef7eb2e8f9f7 524 uint32_t RESERVED5[10];
<> 144:ef7eb2e8f9f7 525 __IO uint32_t MMCRFCECR;
<> 144:ef7eb2e8f9f7 526 __IO uint32_t MMCRFAECR;
<> 144:ef7eb2e8f9f7 527 uint32_t RESERVED6[10];
<> 144:ef7eb2e8f9f7 528 __IO uint32_t MMCRGUFCR;
<> 144:ef7eb2e8f9f7 529 uint32_t RESERVED7[334];
<> 144:ef7eb2e8f9f7 530 __IO uint32_t PTPTSCR;
<> 144:ef7eb2e8f9f7 531 __IO uint32_t PTPSSIR;
<> 144:ef7eb2e8f9f7 532 __IO uint32_t PTPTSHR;
<> 144:ef7eb2e8f9f7 533 __IO uint32_t PTPTSLR;
<> 144:ef7eb2e8f9f7 534 __IO uint32_t PTPTSHUR;
<> 144:ef7eb2e8f9f7 535 __IO uint32_t PTPTSLUR;
<> 144:ef7eb2e8f9f7 536 __IO uint32_t PTPTSAR;
<> 144:ef7eb2e8f9f7 537 __IO uint32_t PTPTTHR;
<> 144:ef7eb2e8f9f7 538 __IO uint32_t PTPTTLR;
<> 144:ef7eb2e8f9f7 539 __IO uint32_t RESERVED8;
<> 144:ef7eb2e8f9f7 540 __IO uint32_t PTPTSSR;
<> 144:ef7eb2e8f9f7 541 uint32_t RESERVED9[565];
<> 144:ef7eb2e8f9f7 542 __IO uint32_t DMABMR;
<> 144:ef7eb2e8f9f7 543 __IO uint32_t DMATPDR;
<> 144:ef7eb2e8f9f7 544 __IO uint32_t DMARPDR;
<> 144:ef7eb2e8f9f7 545 __IO uint32_t DMARDLAR;
<> 144:ef7eb2e8f9f7 546 __IO uint32_t DMATDLAR;
<> 144:ef7eb2e8f9f7 547 __IO uint32_t DMASR;
<> 144:ef7eb2e8f9f7 548 __IO uint32_t DMAOMR;
<> 144:ef7eb2e8f9f7 549 __IO uint32_t DMAIER;
<> 144:ef7eb2e8f9f7 550 __IO uint32_t DMAMFBOCR;
<> 144:ef7eb2e8f9f7 551 __IO uint32_t DMARSWTR;
<> 144:ef7eb2e8f9f7 552 uint32_t RESERVED10[8];
<> 144:ef7eb2e8f9f7 553 __IO uint32_t DMACHTDR;
<> 144:ef7eb2e8f9f7 554 __IO uint32_t DMACHRDR;
<> 144:ef7eb2e8f9f7 555 __IO uint32_t DMACHTBAR;
<> 144:ef7eb2e8f9f7 556 __IO uint32_t DMACHRBAR;
<> 144:ef7eb2e8f9f7 557 } ETH_TypeDef;
<> 144:ef7eb2e8f9f7 558
<> 161:2cc1468da177 559 /**
<> 144:ef7eb2e8f9f7 560 * @brief External Interrupt/Event Controller
<> 144:ef7eb2e8f9f7 561 */
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 typedef struct
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 566 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 567 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 568 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 569 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 570 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 571 } EXTI_TypeDef;
<> 144:ef7eb2e8f9f7 572
<> 161:2cc1468da177 573 /**
<> 144:ef7eb2e8f9f7 574 * @brief FLASH Registers
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 typedef struct
<> 144:ef7eb2e8f9f7 578 {
<> 144:ef7eb2e8f9f7 579 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 580 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 581 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 582 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 583 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 584 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 585 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 586 } FLASH_TypeDef;
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589
<> 161:2cc1468da177 590 /**
<> 144:ef7eb2e8f9f7 591 * @brief Flexible Memory Controller
<> 144:ef7eb2e8f9f7 592 */
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 typedef struct
<> 144:ef7eb2e8f9f7 595 {
<> 161:2cc1468da177 596 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
<> 161:2cc1468da177 597 } FMC_Bank1_TypeDef;
<> 161:2cc1468da177 598
<> 161:2cc1468da177 599 /**
<> 144:ef7eb2e8f9f7 600 * @brief Flexible Memory Controller Bank1E
<> 144:ef7eb2e8f9f7 601 */
<> 161:2cc1468da177 602
<> 144:ef7eb2e8f9f7 603 typedef struct
<> 144:ef7eb2e8f9f7 604 {
<> 144:ef7eb2e8f9f7 605 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
<> 144:ef7eb2e8f9f7 606 } FMC_Bank1E_TypeDef;
<> 144:ef7eb2e8f9f7 607
<> 161:2cc1468da177 608 /**
<> 144:ef7eb2e8f9f7 609 * @brief Flexible Memory Controller Bank3
<> 144:ef7eb2e8f9f7 610 */
<> 161:2cc1468da177 611
<> 144:ef7eb2e8f9f7 612 typedef struct
<> 144:ef7eb2e8f9f7 613 {
<> 144:ef7eb2e8f9f7 614 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 615 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 616 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 617 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 618 uint32_t RESERVED0; /*!< Reserved, 0x90 */
<> 144:ef7eb2e8f9f7 619 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
<> 144:ef7eb2e8f9f7 620 } FMC_Bank3_TypeDef;
<> 161:2cc1468da177 621
<> 161:2cc1468da177 622 /**
<> 144:ef7eb2e8f9f7 623 * @brief Flexible Memory Controller Bank5_6
<> 144:ef7eb2e8f9f7 624 */
<> 161:2cc1468da177 625
<> 144:ef7eb2e8f9f7 626 typedef struct
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
<> 144:ef7eb2e8f9f7 629 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
<> 144:ef7eb2e8f9f7 630 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
<> 144:ef7eb2e8f9f7 631 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
<> 144:ef7eb2e8f9f7 632 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
<> 161:2cc1468da177 633 } FMC_Bank5_6_TypeDef;
<> 161:2cc1468da177 634
<> 161:2cc1468da177 635
<> 161:2cc1468da177 636 /**
<> 144:ef7eb2e8f9f7 637 * @brief General Purpose I/O
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 typedef struct
<> 144:ef7eb2e8f9f7 641 {
<> 144:ef7eb2e8f9f7 642 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 643 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 644 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 645 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 646 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 647 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 648 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 649 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 650 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
<> 144:ef7eb2e8f9f7 651 } GPIO_TypeDef;
<> 144:ef7eb2e8f9f7 652
<> 161:2cc1468da177 653 /**
<> 144:ef7eb2e8f9f7 654 * @brief System configuration controller
<> 144:ef7eb2e8f9f7 655 */
<> 161:2cc1468da177 656
<> 144:ef7eb2e8f9f7 657 typedef struct
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 660 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 661 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
<> 144:ef7eb2e8f9f7 662 uint32_t RESERVED; /*!< Reserved, 0x18 */
<> 144:ef7eb2e8f9f7 663 __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 664 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 665 } SYSCFG_TypeDef;
<> 144:ef7eb2e8f9f7 666
<> 161:2cc1468da177 667 /**
<> 144:ef7eb2e8f9f7 668 * @brief Inter-integrated Circuit Interface
<> 144:ef7eb2e8f9f7 669 */
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 typedef struct
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 161:2cc1468da177 674 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 675 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 676 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 677 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 678 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 679 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 680 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 681 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 682 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
<> 161:2cc1468da177 683 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 684 } I2C_TypeDef;
<> 144:ef7eb2e8f9f7 685
<> 161:2cc1468da177 686 /**
<> 144:ef7eb2e8f9f7 687 * @brief Independent WATCHDOG
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 typedef struct
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 693 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 694 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 695 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 696 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 697 } IWDG_TypeDef;
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699
<> 161:2cc1468da177 700 /**
<> 144:ef7eb2e8f9f7 701 * @brief LCD-TFT Display Controller
<> 144:ef7eb2e8f9f7 702 */
<> 161:2cc1468da177 703
<> 144:ef7eb2e8f9f7 704 typedef struct
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
<> 144:ef7eb2e8f9f7 707 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 708 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 709 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 710 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 711 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 712 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
<> 144:ef7eb2e8f9f7 713 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 714 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
<> 144:ef7eb2e8f9f7 715 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 716 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
<> 144:ef7eb2e8f9f7 717 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 718 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 719 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 720 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 721 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 722 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
<> 161:2cc1468da177 723 } LTDC_TypeDef;
<> 161:2cc1468da177 724
<> 161:2cc1468da177 725 /**
<> 144:ef7eb2e8f9f7 726 * @brief LCD-TFT Display layer x Controller
<> 144:ef7eb2e8f9f7 727 */
<> 161:2cc1468da177 728
<> 144:ef7eb2e8f9f7 729 typedef struct
<> 161:2cc1468da177 730 {
<> 144:ef7eb2e8f9f7 731 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 732 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 733 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 734 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
<> 144:ef7eb2e8f9f7 735 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
<> 144:ef7eb2e8f9f7 736 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
<> 144:ef7eb2e8f9f7 737 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
<> 144:ef7eb2e8f9f7 738 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
<> 144:ef7eb2e8f9f7 739 uint32_t RESERVED0[2]; /*!< Reserved */
<> 144:ef7eb2e8f9f7 740 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
<> 144:ef7eb2e8f9f7 741 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
<> 144:ef7eb2e8f9f7 742 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
<> 144:ef7eb2e8f9f7 743 uint32_t RESERVED1[3]; /*!< Reserved */
<> 144:ef7eb2e8f9f7 744 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 } LTDC_Layer_TypeDef;
<> 144:ef7eb2e8f9f7 747
<> 161:2cc1468da177 748 /**
<> 144:ef7eb2e8f9f7 749 * @brief Power Control
<> 144:ef7eb2e8f9f7 750 */
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 typedef struct
<> 144:ef7eb2e8f9f7 753 {
<> 144:ef7eb2e8f9f7 754 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 755 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 756 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 757 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 758 } PWR_TypeDef;
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760
<> 161:2cc1468da177 761 /**
<> 144:ef7eb2e8f9f7 762 * @brief Reset and Clock Control
<> 144:ef7eb2e8f9f7 763 */
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 typedef struct
<> 144:ef7eb2e8f9f7 766 {
<> 144:ef7eb2e8f9f7 767 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 768 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 769 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 770 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 771 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 772 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 773 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 774 uint32_t RESERVED0; /*!< Reserved, 0x1C */
<> 144:ef7eb2e8f9f7 775 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 776 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 777 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
<> 144:ef7eb2e8f9f7 778 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 779 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 780 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 781 uint32_t RESERVED2; /*!< Reserved, 0x3C */
<> 144:ef7eb2e8f9f7 782 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 783 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 784 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
<> 144:ef7eb2e8f9f7 785 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 786 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 787 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 788 uint32_t RESERVED4; /*!< Reserved, 0x5C */
<> 144:ef7eb2e8f9f7 789 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 790 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 791 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
<> 144:ef7eb2e8f9f7 792 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
<> 144:ef7eb2e8f9f7 793 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
<> 144:ef7eb2e8f9f7 794 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
<> 144:ef7eb2e8f9f7 795 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 796 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 797 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 798 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 799 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 } RCC_TypeDef;
<> 144:ef7eb2e8f9f7 802
<> 161:2cc1468da177 803 /**
<> 144:ef7eb2e8f9f7 804 * @brief Real-Time Clock
<> 144:ef7eb2e8f9f7 805 */
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 typedef struct
<> 144:ef7eb2e8f9f7 808 {
<> 144:ef7eb2e8f9f7 809 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 810 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 161:2cc1468da177 811 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 812 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 813 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 814 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 815 uint32_t reserved; /*!< Reserved */
<> 144:ef7eb2e8f9f7 816 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 817 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 818 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 819 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 820 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 821 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 822 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 823 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 824 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 825 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 826 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 827 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 828 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 829 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 830 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 831 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 832 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 144:ef7eb2e8f9f7 833 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 834 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 835 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 144:ef7eb2e8f9f7 836 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 144:ef7eb2e8f9f7 837 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 144:ef7eb2e8f9f7 838 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 144:ef7eb2e8f9f7 839 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 144:ef7eb2e8f9f7 840 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 144:ef7eb2e8f9f7 841 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 842 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 843 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 844 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 845 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
<> 144:ef7eb2e8f9f7 846 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
<> 144:ef7eb2e8f9f7 847 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
<> 144:ef7eb2e8f9f7 848 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
<> 144:ef7eb2e8f9f7 849 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
<> 144:ef7eb2e8f9f7 850 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
<> 144:ef7eb2e8f9f7 851 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
<> 144:ef7eb2e8f9f7 852 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
<> 144:ef7eb2e8f9f7 853 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
<> 144:ef7eb2e8f9f7 854 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
<> 144:ef7eb2e8f9f7 855 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
<> 144:ef7eb2e8f9f7 856 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
<> 144:ef7eb2e8f9f7 857 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
<> 144:ef7eb2e8f9f7 858 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
<> 144:ef7eb2e8f9f7 859 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
<> 144:ef7eb2e8f9f7 860 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
<> 144:ef7eb2e8f9f7 861 } RTC_TypeDef;
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863
<> 161:2cc1468da177 864 /**
<> 144:ef7eb2e8f9f7 865 * @brief Serial Audio Interface
<> 144:ef7eb2e8f9f7 866 */
<> 161:2cc1468da177 867
<> 144:ef7eb2e8f9f7 868 typedef struct
<> 144:ef7eb2e8f9f7 869 {
<> 144:ef7eb2e8f9f7 870 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 871 } SAI_TypeDef;
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 typedef struct
<> 144:ef7eb2e8f9f7 874 {
<> 144:ef7eb2e8f9f7 875 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 876 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 877 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 878 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 879 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 880 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 881 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 882 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 883 } SAI_Block_TypeDef;
<> 144:ef7eb2e8f9f7 884
<> 161:2cc1468da177 885 /**
<> 144:ef7eb2e8f9f7 886 * @brief SPDIF-RX Interface
<> 144:ef7eb2e8f9f7 887 */
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 typedef struct
<> 144:ef7eb2e8f9f7 890 {
<> 144:ef7eb2e8f9f7 891 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
<> 161:2cc1468da177 892 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 893 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
<> 161:2cc1468da177 894 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 895 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 896 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 897 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 898 } SPDIFRX_TypeDef;
<> 144:ef7eb2e8f9f7 899
<> 161:2cc1468da177 900 /**
<> 144:ef7eb2e8f9f7 901 * @brief SD host Interface
<> 144:ef7eb2e8f9f7 902 */
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 typedef struct
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 907 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 908 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 909 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 910 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 911 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 912 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 913 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 914 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 915 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 916 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 917 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 918 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 919 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 920 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 921 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 922 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
<> 144:ef7eb2e8f9f7 923 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 924 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
<> 144:ef7eb2e8f9f7 925 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 926 } SDMMC_TypeDef;
<> 144:ef7eb2e8f9f7 927
<> 161:2cc1468da177 928 /**
<> 144:ef7eb2e8f9f7 929 * @brief Serial Peripheral Interface
<> 144:ef7eb2e8f9f7 930 */
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 typedef struct
<> 144:ef7eb2e8f9f7 933 {
<> 144:ef7eb2e8f9f7 934 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 935 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 936 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 937 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 938 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 939 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 940 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 941 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 942 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 943 } SPI_TypeDef;
<> 144:ef7eb2e8f9f7 944
<> 161:2cc1468da177 945 /**
<> 144:ef7eb2e8f9f7 946 * @brief QUAD Serial Peripheral Interface
<> 144:ef7eb2e8f9f7 947 */
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 typedef struct
<> 144:ef7eb2e8f9f7 950 {
<> 144:ef7eb2e8f9f7 951 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 952 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 953 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 954 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 955 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 956 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 957 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 958 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 959 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 960 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
<> 161:2cc1468da177 961 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 962 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
<> 161:2cc1468da177 963 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 964 } QUADSPI_TypeDef;
<> 144:ef7eb2e8f9f7 965
<> 161:2cc1468da177 966 /**
<> 144:ef7eb2e8f9f7 967 * @brief TIM
<> 144:ef7eb2e8f9f7 968 */
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 typedef struct
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 973 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 974 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 975 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 976 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 977 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 978 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 979 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 980 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 981 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 982 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 983 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 984 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 985 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 986 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 987 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 988 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 989 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 990 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 991 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 992 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 993 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 994 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 995 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
<> 144:ef7eb2e8f9f7 996 __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 997 __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 } TIM_TypeDef;
<> 144:ef7eb2e8f9f7 1000
<> 161:2cc1468da177 1001 /**
<> 144:ef7eb2e8f9f7 1002 * @brief LPTIMIMER
<> 144:ef7eb2e8f9f7 1003 */
<> 144:ef7eb2e8f9f7 1004 typedef struct
<> 144:ef7eb2e8f9f7 1005 {
<> 144:ef7eb2e8f9f7 1006 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 1007 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 1008 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 1009 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 1010 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 1011 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 1012 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 1013 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 1014 } LPTIM_TypeDef;
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016
<> 161:2cc1468da177 1017 /**
<> 144:ef7eb2e8f9f7 1018 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 144:ef7eb2e8f9f7 1019 */
<> 161:2cc1468da177 1020
<> 144:ef7eb2e8f9f7 1021 typedef struct
<> 144:ef7eb2e8f9f7 1022 {
<> 161:2cc1468da177 1023 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
<> 161:2cc1468da177 1024 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 1025 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
<> 161:2cc1468da177 1026 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 1027 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
<> 161:2cc1468da177 1028 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 1029 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 1030 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 1031 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 1032 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 1033 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 1034 } USART_TypeDef;
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036
<> 161:2cc1468da177 1037 /**
<> 144:ef7eb2e8f9f7 1038 * @brief Window WATCHDOG
<> 144:ef7eb2e8f9f7 1039 */
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 typedef struct
<> 144:ef7eb2e8f9f7 1042 {
<> 144:ef7eb2e8f9f7 1043 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 1044 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 1045 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 1046 } WWDG_TypeDef;
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048
<> 161:2cc1468da177 1049 /**
<> 144:ef7eb2e8f9f7 1050 * @brief RNG
<> 144:ef7eb2e8f9f7 1051 */
<> 161:2cc1468da177 1052
<> 161:2cc1468da177 1053 typedef struct
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 1056 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 1057 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 1058 } RNG_TypeDef;
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /**
<> 144:ef7eb2e8f9f7 1061 * @}
<> 144:ef7eb2e8f9f7 1062 */
<> 144:ef7eb2e8f9f7 1063
<> 161:2cc1468da177 1064 /**
<> 144:ef7eb2e8f9f7 1065 * @brief USB_OTG_Core_Registers
<> 144:ef7eb2e8f9f7 1066 */
<> 144:ef7eb2e8f9f7 1067 typedef struct
<> 144:ef7eb2e8f9f7 1068 {
<> 144:ef7eb2e8f9f7 1069 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
<> 144:ef7eb2e8f9f7 1070 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
<> 144:ef7eb2e8f9f7 1071 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
<> 144:ef7eb2e8f9f7 1072 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
<> 144:ef7eb2e8f9f7 1073 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
<> 144:ef7eb2e8f9f7 1074 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
<> 144:ef7eb2e8f9f7 1075 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
<> 144:ef7eb2e8f9f7 1076 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
<> 144:ef7eb2e8f9f7 1077 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
<> 144:ef7eb2e8f9f7 1078 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
<> 144:ef7eb2e8f9f7 1079 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
<> 144:ef7eb2e8f9f7 1080 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
<> 144:ef7eb2e8f9f7 1081 uint32_t Reserved30[2]; /*!< Reserved 030h */
<> 144:ef7eb2e8f9f7 1082 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
<> 144:ef7eb2e8f9f7 1083 __IO uint32_t CID; /*!< User ID Register 03Ch */
<> 144:ef7eb2e8f9f7 1084 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
<> 144:ef7eb2e8f9f7 1085 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
<> 161:2cc1468da177 1086 uint32_t Reserved6; /*!< Reserved 050h */
<> 144:ef7eb2e8f9f7 1087 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
<> 144:ef7eb2e8f9f7 1088 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
<> 144:ef7eb2e8f9f7 1089 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
<> 144:ef7eb2e8f9f7 1090 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
<> 144:ef7eb2e8f9f7 1091 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
<> 144:ef7eb2e8f9f7 1092 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
<> 144:ef7eb2e8f9f7 1093 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
<> 144:ef7eb2e8f9f7 1094 } USB_OTG_GlobalTypeDef;
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096
<> 161:2cc1468da177 1097 /**
<> 144:ef7eb2e8f9f7 1098 * @brief USB_OTG_device_Registers
<> 144:ef7eb2e8f9f7 1099 */
<> 161:2cc1468da177 1100 typedef struct
<> 144:ef7eb2e8f9f7 1101 {
<> 144:ef7eb2e8f9f7 1102 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
<> 144:ef7eb2e8f9f7 1103 __IO uint32_t DCTL; /*!< dev Control Register 804h */
<> 144:ef7eb2e8f9f7 1104 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
<> 144:ef7eb2e8f9f7 1105 uint32_t Reserved0C; /*!< Reserved 80Ch */
<> 144:ef7eb2e8f9f7 1106 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
<> 144:ef7eb2e8f9f7 1107 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
<> 144:ef7eb2e8f9f7 1108 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
<> 144:ef7eb2e8f9f7 1109 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
<> 144:ef7eb2e8f9f7 1110 uint32_t Reserved20; /*!< Reserved 820h */
<> 144:ef7eb2e8f9f7 1111 uint32_t Reserved9; /*!< Reserved 824h */
<> 144:ef7eb2e8f9f7 1112 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
<> 144:ef7eb2e8f9f7 1113 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
<> 144:ef7eb2e8f9f7 1114 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
<> 144:ef7eb2e8f9f7 1115 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
<> 144:ef7eb2e8f9f7 1116 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
<> 161:2cc1468da177 1117 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
<> 144:ef7eb2e8f9f7 1118 uint32_t Reserved40; /*!< dedicated EP mask 840h */
<> 144:ef7eb2e8f9f7 1119 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
<> 144:ef7eb2e8f9f7 1120 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
<> 161:2cc1468da177 1121 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
<> 144:ef7eb2e8f9f7 1122 } USB_OTG_DeviceTypeDef;
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124
<> 161:2cc1468da177 1125 /**
<> 144:ef7eb2e8f9f7 1126 * @brief USB_OTG_IN_Endpoint-Specific_Register
<> 144:ef7eb2e8f9f7 1127 */
<> 161:2cc1468da177 1128 typedef struct
<> 144:ef7eb2e8f9f7 1129 {
<> 144:ef7eb2e8f9f7 1130 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
<> 144:ef7eb2e8f9f7 1131 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
<> 144:ef7eb2e8f9f7 1132 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
<> 144:ef7eb2e8f9f7 1133 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
<> 144:ef7eb2e8f9f7 1134 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
<> 144:ef7eb2e8f9f7 1135 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
<> 144:ef7eb2e8f9f7 1136 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
<> 144:ef7eb2e8f9f7 1137 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
<> 144:ef7eb2e8f9f7 1138 } USB_OTG_INEndpointTypeDef;
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140
<> 161:2cc1468da177 1141 /**
<> 144:ef7eb2e8f9f7 1142 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
<> 144:ef7eb2e8f9f7 1143 */
<> 161:2cc1468da177 1144 typedef struct
<> 144:ef7eb2e8f9f7 1145 {
<> 144:ef7eb2e8f9f7 1146 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
<> 144:ef7eb2e8f9f7 1147 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
<> 144:ef7eb2e8f9f7 1148 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
<> 144:ef7eb2e8f9f7 1149 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
<> 144:ef7eb2e8f9f7 1150 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
<> 144:ef7eb2e8f9f7 1151 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
<> 144:ef7eb2e8f9f7 1152 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
<> 144:ef7eb2e8f9f7 1153 } USB_OTG_OUTEndpointTypeDef;
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155
<> 161:2cc1468da177 1156 /**
<> 144:ef7eb2e8f9f7 1157 * @brief USB_OTG_Host_Mode_Register_Structures
<> 144:ef7eb2e8f9f7 1158 */
<> 161:2cc1468da177 1159 typedef struct
<> 144:ef7eb2e8f9f7 1160 {
<> 144:ef7eb2e8f9f7 1161 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
<> 144:ef7eb2e8f9f7 1162 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
<> 144:ef7eb2e8f9f7 1163 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
<> 144:ef7eb2e8f9f7 1164 uint32_t Reserved40C; /*!< Reserved 40Ch */
<> 144:ef7eb2e8f9f7 1165 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
<> 144:ef7eb2e8f9f7 1166 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
<> 144:ef7eb2e8f9f7 1167 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
<> 144:ef7eb2e8f9f7 1168 } USB_OTG_HostTypeDef;
<> 144:ef7eb2e8f9f7 1169
<> 161:2cc1468da177 1170 /**
<> 144:ef7eb2e8f9f7 1171 * @brief USB_OTG_Host_Channel_Specific_Registers
<> 144:ef7eb2e8f9f7 1172 */
<> 144:ef7eb2e8f9f7 1173 typedef struct
<> 144:ef7eb2e8f9f7 1174 {
<> 144:ef7eb2e8f9f7 1175 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
<> 144:ef7eb2e8f9f7 1176 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
<> 144:ef7eb2e8f9f7 1177 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
<> 144:ef7eb2e8f9f7 1178 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
<> 144:ef7eb2e8f9f7 1179 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
<> 144:ef7eb2e8f9f7 1180 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
<> 144:ef7eb2e8f9f7 1181 uint32_t Reserved[2]; /*!< Reserved */
<> 144:ef7eb2e8f9f7 1182 } USB_OTG_HostChannelTypeDef;
<> 144:ef7eb2e8f9f7 1183 /**
<> 144:ef7eb2e8f9f7 1184 * @}
<> 144:ef7eb2e8f9f7 1185 */
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /**
<> 144:ef7eb2e8f9f7 1188 * @brief JPEG Codec
<> 144:ef7eb2e8f9f7 1189 */
<> 144:ef7eb2e8f9f7 1190 typedef struct
<> 144:ef7eb2e8f9f7 1191 {
<> 144:ef7eb2e8f9f7 1192 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
<> 144:ef7eb2e8f9f7 1193 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
<> 144:ef7eb2e8f9f7 1194 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
<> 161:2cc1468da177 1195 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
<> 161:2cc1468da177 1196 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
<> 161:2cc1468da177 1197 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
<> 161:2cc1468da177 1198 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
<> 144:ef7eb2e8f9f7 1199 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
<> 144:ef7eb2e8f9f7 1200 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
<> 161:2cc1468da177 1201 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
<> 161:2cc1468da177 1202 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
<> 161:2cc1468da177 1203 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
<> 144:ef7eb2e8f9f7 1204 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
<> 144:ef7eb2e8f9f7 1205 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
<> 144:ef7eb2e8f9f7 1206 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
<> 144:ef7eb2e8f9f7 1207 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
<> 144:ef7eb2e8f9f7 1208 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
<> 144:ef7eb2e8f9f7 1209 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
<> 144:ef7eb2e8f9f7 1210 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
<> 144:ef7eb2e8f9f7 1211 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
<> 144:ef7eb2e8f9f7 1212 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
<> 144:ef7eb2e8f9f7 1213 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
<> 144:ef7eb2e8f9f7 1214 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
<> 144:ef7eb2e8f9f7 1215 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
<> 144:ef7eb2e8f9f7 1216 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
<> 144:ef7eb2e8f9f7 1217 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
<> 144:ef7eb2e8f9f7 1218 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
<> 144:ef7eb2e8f9f7 1219 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
<> 144:ef7eb2e8f9f7 1220 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 } JPEG_TypeDef;
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /**
<> 144:ef7eb2e8f9f7 1225 * @brief MDIOS
<> 144:ef7eb2e8f9f7 1226 */
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 typedef struct
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
<> 144:ef7eb2e8f9f7 1231 __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
<> 144:ef7eb2e8f9f7 1232 __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
<> 161:2cc1468da177 1233 __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
<> 161:2cc1468da177 1234 __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
<> 144:ef7eb2e8f9f7 1235 __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
<> 161:2cc1468da177 1236 __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
<> 161:2cc1468da177 1237 uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
<> 161:2cc1468da177 1238 __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
<> 161:2cc1468da177 1239 __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
<> 161:2cc1468da177 1240 __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
<> 161:2cc1468da177 1241 __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
<> 161:2cc1468da177 1242 __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
<> 161:2cc1468da177 1243 __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
<> 161:2cc1468da177 1244 __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
<> 161:2cc1468da177 1245 __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
<> 161:2cc1468da177 1246 __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
<> 161:2cc1468da177 1247 __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
<> 161:2cc1468da177 1248 __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
<> 161:2cc1468da177 1249 __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
<> 161:2cc1468da177 1250 __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
<> 161:2cc1468da177 1251 __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
<> 161:2cc1468da177 1252 __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
<> 161:2cc1468da177 1253 __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
<> 161:2cc1468da177 1254 __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
<> 161:2cc1468da177 1255 __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
<> 161:2cc1468da177 1256 __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
<> 161:2cc1468da177 1257 __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
<> 161:2cc1468da177 1258 __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
<> 161:2cc1468da177 1259 __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
<> 161:2cc1468da177 1260 __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
<> 161:2cc1468da177 1261 __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
<> 161:2cc1468da177 1262 __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
<> 161:2cc1468da177 1263 __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
<> 161:2cc1468da177 1264 __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
<> 161:2cc1468da177 1265 __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
<> 161:2cc1468da177 1266 __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
<> 161:2cc1468da177 1267 __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
<> 161:2cc1468da177 1268 __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
<> 161:2cc1468da177 1269 __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
<> 161:2cc1468da177 1270 __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
<> 161:2cc1468da177 1271 __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
<> 161:2cc1468da177 1272 __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
<> 161:2cc1468da177 1273 __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
<> 161:2cc1468da177 1274 __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
<> 161:2cc1468da177 1275 __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
<> 161:2cc1468da177 1276 __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
<> 144:ef7eb2e8f9f7 1277 __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
<> 144:ef7eb2e8f9f7 1278 __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
<> 144:ef7eb2e8f9f7 1279 __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
<> 144:ef7eb2e8f9f7 1280 __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
<> 144:ef7eb2e8f9f7 1281 __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
<> 144:ef7eb2e8f9f7 1282 __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
<> 144:ef7eb2e8f9f7 1283 __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
<> 144:ef7eb2e8f9f7 1284 __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
<> 144:ef7eb2e8f9f7 1285 __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
<> 144:ef7eb2e8f9f7 1286 __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
<> 144:ef7eb2e8f9f7 1287 __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
<> 144:ef7eb2e8f9f7 1288 __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
<> 144:ef7eb2e8f9f7 1289 __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
<> 144:ef7eb2e8f9f7 1290 __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
<> 144:ef7eb2e8f9f7 1291 __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
<> 144:ef7eb2e8f9f7 1292 __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
<> 144:ef7eb2e8f9f7 1293 __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
<> 144:ef7eb2e8f9f7 1294 __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
<> 144:ef7eb2e8f9f7 1295 __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
<> 144:ef7eb2e8f9f7 1296 __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
<> 144:ef7eb2e8f9f7 1297 __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
<> 144:ef7eb2e8f9f7 1298 __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
<> 144:ef7eb2e8f9f7 1299 __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
<> 144:ef7eb2e8f9f7 1300 __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
<> 144:ef7eb2e8f9f7 1301 __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
<> 144:ef7eb2e8f9f7 1302 } MDIOS_TypeDef;
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /** @addtogroup Peripheral_memory_map
<> 144:ef7eb2e8f9f7 1306 * @{
<> 144:ef7eb2e8f9f7 1307 */
<> 144:ef7eb2e8f9f7 1308 #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
<> 161:2cc1468da177 1309 #define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
<> 161:2cc1468da177 1310 #define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
<> 144:ef7eb2e8f9f7 1311 #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */
<> 144:ef7eb2e8f9f7 1312 #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
<> 144:ef7eb2e8f9f7 1313 #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
<> 144:ef7eb2e8f9f7 1314 #define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
<> 144:ef7eb2e8f9f7 1315 #define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
<> 144:ef7eb2e8f9f7 1316 #define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
<> 144:ef7eb2e8f9f7 1317 #define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
<> 144:ef7eb2e8f9f7 1318 #define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
<> 144:ef7eb2e8f9f7 1319 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
<> 161:2cc1468da177 1320 #define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */
<> 161:2cc1468da177 1321 #define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 /* Legacy define */
<> 144:ef7eb2e8f9f7 1324 #define FLASH_BASE FLASHAXI_BASE
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /*!< Peripheral memory map */
<> 144:ef7eb2e8f9f7 1327 #define APB1PERIPH_BASE PERIPH_BASE
<> 144:ef7eb2e8f9f7 1328 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 144:ef7eb2e8f9f7 1329 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 144:ef7eb2e8f9f7 1330 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
<> 144:ef7eb2e8f9f7 1331
<> 144:ef7eb2e8f9f7 1332 /*!< APB1 peripherals */
<> 144:ef7eb2e8f9f7 1333 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1334 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 1335 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 1336 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 1337 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1338 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 1339 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
<> 144:ef7eb2e8f9f7 1340 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 1341 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 1342 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
<> 144:ef7eb2e8f9f7 1343 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
<> 144:ef7eb2e8f9f7 1344 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 1345 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 1346 #define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
<> 144:ef7eb2e8f9f7 1347 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 1348 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 1349 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
<> 144:ef7eb2e8f9f7 1350 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 1351 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
<> 144:ef7eb2e8f9f7 1352 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
<> 144:ef7eb2e8f9f7 1353 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
<> 144:ef7eb2e8f9f7 1354 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
<> 144:ef7eb2e8f9f7 1355 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
<> 144:ef7eb2e8f9f7 1356 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
<> 144:ef7eb2e8f9f7 1357 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
<> 144:ef7eb2e8f9f7 1358 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
<> 144:ef7eb2e8f9f7 1359 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
<> 144:ef7eb2e8f9f7 1360 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
<> 144:ef7eb2e8f9f7 1361 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
<> 144:ef7eb2e8f9f7 1362 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
<> 144:ef7eb2e8f9f7 1363 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
<> 144:ef7eb2e8f9f7 1364 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
<> 144:ef7eb2e8f9f7 1365
<> 144:ef7eb2e8f9f7 1366 /*!< APB2 peripherals */
<> 144:ef7eb2e8f9f7 1367 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1368 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 1369 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1370 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 1371 #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 1372 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 1373 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
<> 144:ef7eb2e8f9f7 1374 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
<> 144:ef7eb2e8f9f7 1375 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
<> 144:ef7eb2e8f9f7 1376 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 1377 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 1378 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
<> 144:ef7eb2e8f9f7 1379 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 1380 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 1381 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
<> 144:ef7eb2e8f9f7 1382 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 1383 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
<> 144:ef7eb2e8f9f7 1384 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
<> 144:ef7eb2e8f9f7 1385 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
<> 144:ef7eb2e8f9f7 1386 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
<> 144:ef7eb2e8f9f7 1387 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
<> 144:ef7eb2e8f9f7 1388 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
<> 144:ef7eb2e8f9f7 1389 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
<> 144:ef7eb2e8f9f7 1390 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
<> 144:ef7eb2e8f9f7 1391 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
<> 144:ef7eb2e8f9f7 1392 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
<> 144:ef7eb2e8f9f7 1393 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
<> 144:ef7eb2e8f9f7 1394 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
<> 144:ef7eb2e8f9f7 1395 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
<> 144:ef7eb2e8f9f7 1396 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
<> 144:ef7eb2e8f9f7 1397 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
<> 144:ef7eb2e8f9f7 1398 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
<> 144:ef7eb2e8f9f7 1399 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
<> 144:ef7eb2e8f9f7 1400 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
<> 144:ef7eb2e8f9f7 1401 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
<> 144:ef7eb2e8f9f7 1402 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
<> 144:ef7eb2e8f9f7 1403 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
<> 144:ef7eb2e8f9f7 1404 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
<> 144:ef7eb2e8f9f7 1405 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
<> 144:ef7eb2e8f9f7 1406 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
<> 144:ef7eb2e8f9f7 1407 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
<> 144:ef7eb2e8f9f7 1408 #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
<> 144:ef7eb2e8f9f7 1409 /*!< AHB1 peripherals */
<> 144:ef7eb2e8f9f7 1410 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1411 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 1412 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 1413 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 1414 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1415 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 1416 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
<> 144:ef7eb2e8f9f7 1417 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 1418 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 1419 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
<> 144:ef7eb2e8f9f7 1420 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
<> 144:ef7eb2e8f9f7 1421 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 1422 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 1423 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 1424 #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
<> 144:ef7eb2e8f9f7 1425 #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
<> 161:2cc1468da177 1426 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
<> 161:2cc1468da177 1427 /* Legacy define */
<> 161:2cc1468da177 1428 #define PACKAGESIZE_BASE PACKAGE_BASE
<> 161:2cc1468da177 1429
<> 144:ef7eb2e8f9f7 1430 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
<> 144:ef7eb2e8f9f7 1431 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 1432 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 1433 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 1434 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 1435 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 1436 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 1437 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 1438 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 1439 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
<> 144:ef7eb2e8f9f7 1440 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 1441 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 1442 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 1443 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 1444 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 1445 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 1446 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 1447 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 1448 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
<> 144:ef7eb2e8f9f7 1449 #define ETH_MAC_BASE (ETH_BASE)
<> 144:ef7eb2e8f9f7 1450 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
<> 144:ef7eb2e8f9f7 1451 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
<> 144:ef7eb2e8f9f7 1452 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1453 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
<> 144:ef7eb2e8f9f7 1454 /*!< AHB2 peripherals */
<> 144:ef7eb2e8f9f7 1455 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
<> 144:ef7eb2e8f9f7 1456 #define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
<> 144:ef7eb2e8f9f7 1457 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
<> 144:ef7eb2e8f9f7 1458 /*!< FMC Bankx registers base address */
<> 144:ef7eb2e8f9f7 1459 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1460 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
<> 144:ef7eb2e8f9f7 1461 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
<> 144:ef7eb2e8f9f7 1462 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
<> 144:ef7eb2e8f9f7 1463
<> 144:ef7eb2e8f9f7 1464 /* Debug MCU registers base address */
<> 144:ef7eb2e8f9f7 1465 #define DBGMCU_BASE 0xE0042000U
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 /*!< USB registers base address */
<> 144:ef7eb2e8f9f7 1468 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
<> 144:ef7eb2e8f9f7 1469 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 #define USB_OTG_GLOBAL_BASE 0x000U
<> 144:ef7eb2e8f9f7 1472 #define USB_OTG_DEVICE_BASE 0x800U
<> 144:ef7eb2e8f9f7 1473 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
<> 144:ef7eb2e8f9f7 1474 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
<> 144:ef7eb2e8f9f7 1475 #define USB_OTG_EP_REG_SIZE 0x20U
<> 144:ef7eb2e8f9f7 1476 #define USB_OTG_HOST_BASE 0x400U
<> 144:ef7eb2e8f9f7 1477 #define USB_OTG_HOST_PORT_BASE 0x440U
<> 144:ef7eb2e8f9f7 1478 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
<> 144:ef7eb2e8f9f7 1479 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
<> 144:ef7eb2e8f9f7 1480 #define USB_OTG_PCGCCTL_BASE 0xE00U
<> 144:ef7eb2e8f9f7 1481 #define USB_OTG_FIFO_BASE 0x1000U
<> 144:ef7eb2e8f9f7 1482 #define USB_OTG_FIFO_SIZE 0x1000U
<> 144:ef7eb2e8f9f7 1483
<> 144:ef7eb2e8f9f7 1484 /**
<> 144:ef7eb2e8f9f7 1485 * @}
<> 144:ef7eb2e8f9f7 1486 */
<> 161:2cc1468da177 1487
<> 144:ef7eb2e8f9f7 1488 /** @addtogroup Peripheral_declaration
<> 144:ef7eb2e8f9f7 1489 * @{
<> 161:2cc1468da177 1490 */
<> 144:ef7eb2e8f9f7 1491 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 144:ef7eb2e8f9f7 1492 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 144:ef7eb2e8f9f7 1493 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 144:ef7eb2e8f9f7 1494 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
<> 144:ef7eb2e8f9f7 1495 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
<> 144:ef7eb2e8f9f7 1496 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
<> 144:ef7eb2e8f9f7 1497 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
<> 144:ef7eb2e8f9f7 1498 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
<> 144:ef7eb2e8f9f7 1499 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
<> 144:ef7eb2e8f9f7 1500 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
<> 144:ef7eb2e8f9f7 1501 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 144:ef7eb2e8f9f7 1502 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 144:ef7eb2e8f9f7 1503 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 144:ef7eb2e8f9f7 1504 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 144:ef7eb2e8f9f7 1505 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 157:ff67d9f36b67 1506 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
<> 144:ef7eb2e8f9f7 1507 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 144:ef7eb2e8f9f7 1508 #define USART3 ((USART_TypeDef *) USART3_BASE)
<> 144:ef7eb2e8f9f7 1509 #define UART4 ((USART_TypeDef *) UART4_BASE)
<> 144:ef7eb2e8f9f7 1510 #define UART5 ((USART_TypeDef *) UART5_BASE)
<> 144:ef7eb2e8f9f7 1511 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 144:ef7eb2e8f9f7 1512 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 144:ef7eb2e8f9f7 1513 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
<> 144:ef7eb2e8f9f7 1514 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
<> 144:ef7eb2e8f9f7 1515 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
<> 144:ef7eb2e8f9f7 1516 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
<> 144:ef7eb2e8f9f7 1517 #define CEC ((CEC_TypeDef *) CEC_BASE)
<> 144:ef7eb2e8f9f7 1518 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 161:2cc1468da177 1519 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
<> 161:2cc1468da177 1520 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
<> 144:ef7eb2e8f9f7 1521 #define UART7 ((USART_TypeDef *) UART7_BASE)
<> 144:ef7eb2e8f9f7 1522 #define UART8 ((USART_TypeDef *) UART8_BASE)
<> 144:ef7eb2e8f9f7 1523 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
<> 144:ef7eb2e8f9f7 1524 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
<> 144:ef7eb2e8f9f7 1525 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 144:ef7eb2e8f9f7 1526 #define USART6 ((USART_TypeDef *) USART6_BASE)
<> 144:ef7eb2e8f9f7 1527 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
<> 144:ef7eb2e8f9f7 1528 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 144:ef7eb2e8f9f7 1529 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
<> 144:ef7eb2e8f9f7 1530 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
<> 161:2cc1468da177 1531 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
<> 144:ef7eb2e8f9f7 1532 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
<> 161:2cc1468da177 1533 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 144:ef7eb2e8f9f7 1534 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
<> 144:ef7eb2e8f9f7 1535 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 144:ef7eb2e8f9f7 1536 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 144:ef7eb2e8f9f7 1537 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
<> 144:ef7eb2e8f9f7 1538 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
<> 144:ef7eb2e8f9f7 1539 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
<> 144:ef7eb2e8f9f7 1540 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
<> 144:ef7eb2e8f9f7 1541 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
<> 144:ef7eb2e8f9f7 1542 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
<> 144:ef7eb2e8f9f7 1543 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
<> 144:ef7eb2e8f9f7 1544 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
<> 144:ef7eb2e8f9f7 1545 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
<> 144:ef7eb2e8f9f7 1546 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
<> 144:ef7eb2e8f9f7 1547 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
<> 144:ef7eb2e8f9f7 1548 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
<> 144:ef7eb2e8f9f7 1549 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
<> 144:ef7eb2e8f9f7 1550 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
<> 144:ef7eb2e8f9f7 1551 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 144:ef7eb2e8f9f7 1552 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 144:ef7eb2e8f9f7 1553 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 144:ef7eb2e8f9f7 1554 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 144:ef7eb2e8f9f7 1555 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 144:ef7eb2e8f9f7 1556 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
<> 144:ef7eb2e8f9f7 1557 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
<> 144:ef7eb2e8f9f7 1558 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 144:ef7eb2e8f9f7 1559 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
<> 144:ef7eb2e8f9f7 1560 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
<> 144:ef7eb2e8f9f7 1561 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
<> 144:ef7eb2e8f9f7 1562 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 144:ef7eb2e8f9f7 1563 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 144:ef7eb2e8f9f7 1564 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 144:ef7eb2e8f9f7 1565 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 144:ef7eb2e8f9f7 1566 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
<> 144:ef7eb2e8f9f7 1567 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
<> 144:ef7eb2e8f9f7 1568 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
<> 144:ef7eb2e8f9f7 1569 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
<> 144:ef7eb2e8f9f7 1570 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
<> 144:ef7eb2e8f9f7 1571 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
<> 144:ef7eb2e8f9f7 1572 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
<> 144:ef7eb2e8f9f7 1573 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
<> 144:ef7eb2e8f9f7 1574 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 144:ef7eb2e8f9f7 1575 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
<> 144:ef7eb2e8f9f7 1576 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
<> 144:ef7eb2e8f9f7 1577 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
<> 144:ef7eb2e8f9f7 1578 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
<> 144:ef7eb2e8f9f7 1579 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
<> 144:ef7eb2e8f9f7 1580 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
<> 144:ef7eb2e8f9f7 1581 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
<> 144:ef7eb2e8f9f7 1582 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
<> 161:2cc1468da177 1583 #define ETH ((ETH_TypeDef *) ETH_BASE)
<> 144:ef7eb2e8f9f7 1584 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
<> 144:ef7eb2e8f9f7 1585 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
<> 144:ef7eb2e8f9f7 1586 #define RNG ((RNG_TypeDef *) RNG_BASE)
<> 144:ef7eb2e8f9f7 1587 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
<> 144:ef7eb2e8f9f7 1588 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
<> 144:ef7eb2e8f9f7 1589 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
<> 144:ef7eb2e8f9f7 1590 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
<> 144:ef7eb2e8f9f7 1591 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
<> 144:ef7eb2e8f9f7 1592 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 144:ef7eb2e8f9f7 1593 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
<> 144:ef7eb2e8f9f7 1594 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
<> 144:ef7eb2e8f9f7 1595 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
<> 144:ef7eb2e8f9f7 1596 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
<> 144:ef7eb2e8f9f7 1597 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
<> 144:ef7eb2e8f9f7 1598 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
<> 144:ef7eb2e8f9f7 1599 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
<> 144:ef7eb2e8f9f7 1600 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
<> 144:ef7eb2e8f9f7 1601 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
<> 144:ef7eb2e8f9f7 1602 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
<> 144:ef7eb2e8f9f7 1603 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
<> 144:ef7eb2e8f9f7 1604 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
<> 144:ef7eb2e8f9f7 1605 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
<> 144:ef7eb2e8f9f7 1606 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
<> 144:ef7eb2e8f9f7 1607 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
<> 144:ef7eb2e8f9f7 1608 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
<> 144:ef7eb2e8f9f7 1609 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
<> 144:ef7eb2e8f9f7 1610 #define JPEG ((JPEG_TypeDef *) JPEG_BASE)
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 /**
<> 144:ef7eb2e8f9f7 1613 * @}
<> 144:ef7eb2e8f9f7 1614 */
<> 144:ef7eb2e8f9f7 1615
<> 144:ef7eb2e8f9f7 1616 /** @addtogroup Exported_constants
<> 144:ef7eb2e8f9f7 1617 * @{
<> 144:ef7eb2e8f9f7 1618 */
<> 161:2cc1468da177 1619
<> 144:ef7eb2e8f9f7 1620 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 144:ef7eb2e8f9f7 1621 * @{
<> 144:ef7eb2e8f9f7 1622 */
<> 161:2cc1468da177 1623
<> 144:ef7eb2e8f9f7 1624 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1625 /* Peripheral Registers_Bits_Definition */
<> 144:ef7eb2e8f9f7 1626 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1627
<> 144:ef7eb2e8f9f7 1628 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1629 /* */
<> 144:ef7eb2e8f9f7 1630 /* Analog to Digital Converter */
<> 144:ef7eb2e8f9f7 1631 /* */
<> 144:ef7eb2e8f9f7 1632 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1633 /******************** Bit definition for ADC_SR register ********************/
<> 161:2cc1468da177 1634 #define ADC_SR_AWD_Pos (0U)
<> 161:2cc1468da177 1635 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 1636 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
<> 161:2cc1468da177 1637 #define ADC_SR_EOC_Pos (1U)
<> 161:2cc1468da177 1638 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 1639 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
<> 161:2cc1468da177 1640 #define ADC_SR_JEOC_Pos (2U)
<> 161:2cc1468da177 1641 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 1642 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
<> 161:2cc1468da177 1643 #define ADC_SR_JSTRT_Pos (3U)
<> 161:2cc1468da177 1644 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 1645 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
<> 161:2cc1468da177 1646 #define ADC_SR_STRT_Pos (4U)
<> 161:2cc1468da177 1647 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 1648 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
<> 161:2cc1468da177 1649 #define ADC_SR_OVR_Pos (5U)
<> 161:2cc1468da177 1650 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 1651 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
<> 144:ef7eb2e8f9f7 1652
<> 144:ef7eb2e8f9f7 1653 /******************* Bit definition for ADC_CR1 register ********************/
<> 161:2cc1468da177 1654 #define ADC_CR1_AWDCH_Pos (0U)
<> 161:2cc1468da177 1655 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
<> 161:2cc1468da177 1656 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
<> 161:2cc1468da177 1657 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 1658 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 1659 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 1660 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 1661 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 1662 #define ADC_CR1_EOCIE_Pos (5U)
<> 161:2cc1468da177 1663 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 1664 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
<> 161:2cc1468da177 1665 #define ADC_CR1_AWDIE_Pos (6U)
<> 161:2cc1468da177 1666 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 1667 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
<> 161:2cc1468da177 1668 #define ADC_CR1_JEOCIE_Pos (7U)
<> 161:2cc1468da177 1669 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 1670 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
<> 161:2cc1468da177 1671 #define ADC_CR1_SCAN_Pos (8U)
<> 161:2cc1468da177 1672 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 1673 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
<> 161:2cc1468da177 1674 #define ADC_CR1_AWDSGL_Pos (9U)
<> 161:2cc1468da177 1675 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 1676 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
<> 161:2cc1468da177 1677 #define ADC_CR1_JAUTO_Pos (10U)
<> 161:2cc1468da177 1678 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 1679 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
<> 161:2cc1468da177 1680 #define ADC_CR1_DISCEN_Pos (11U)
<> 161:2cc1468da177 1681 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 1682 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
<> 161:2cc1468da177 1683 #define ADC_CR1_JDISCEN_Pos (12U)
<> 161:2cc1468da177 1684 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 1685 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
<> 161:2cc1468da177 1686 #define ADC_CR1_DISCNUM_Pos (13U)
<> 161:2cc1468da177 1687 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
<> 161:2cc1468da177 1688 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
<> 161:2cc1468da177 1689 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 1690 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 1691 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 1692 #define ADC_CR1_JAWDEN_Pos (22U)
<> 161:2cc1468da177 1693 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 1694 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
<> 161:2cc1468da177 1695 #define ADC_CR1_AWDEN_Pos (23U)
<> 161:2cc1468da177 1696 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 1697 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
<> 161:2cc1468da177 1698 #define ADC_CR1_RES_Pos (24U)
<> 161:2cc1468da177 1699 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
<> 161:2cc1468da177 1700 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
<> 161:2cc1468da177 1701 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 1702 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 1703 #define ADC_CR1_OVRIE_Pos (26U)
<> 161:2cc1468da177 1704 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 1705 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
<> 161:2cc1468da177 1706
<> 144:ef7eb2e8f9f7 1707 /******************* Bit definition for ADC_CR2 register ********************/
<> 161:2cc1468da177 1708 #define ADC_CR2_ADON_Pos (0U)
<> 161:2cc1468da177 1709 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 1710 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
<> 161:2cc1468da177 1711 #define ADC_CR2_CONT_Pos (1U)
<> 161:2cc1468da177 1712 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 1713 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
<> 161:2cc1468da177 1714 #define ADC_CR2_DMA_Pos (8U)
<> 161:2cc1468da177 1715 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 1716 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
<> 161:2cc1468da177 1717 #define ADC_CR2_DDS_Pos (9U)
<> 161:2cc1468da177 1718 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 1719 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
<> 161:2cc1468da177 1720 #define ADC_CR2_EOCS_Pos (10U)
<> 161:2cc1468da177 1721 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 1722 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
<> 161:2cc1468da177 1723 #define ADC_CR2_ALIGN_Pos (11U)
<> 161:2cc1468da177 1724 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 1725 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
<> 161:2cc1468da177 1726 #define ADC_CR2_JEXTSEL_Pos (16U)
<> 161:2cc1468da177 1727 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 1728 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
<> 161:2cc1468da177 1729 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 1730 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 1731 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 1732 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 1733 #define ADC_CR2_JEXTEN_Pos (20U)
<> 161:2cc1468da177 1734 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 1735 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
<> 161:2cc1468da177 1736 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 1737 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 1738 #define ADC_CR2_JSWSTART_Pos (22U)
<> 161:2cc1468da177 1739 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 1740 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
<> 161:2cc1468da177 1741 #define ADC_CR2_EXTSEL_Pos (24U)
<> 161:2cc1468da177 1742 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 1743 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
<> 161:2cc1468da177 1744 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 1745 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 1746 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 1747 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 1748 #define ADC_CR2_EXTEN_Pos (28U)
<> 161:2cc1468da177 1749 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 1750 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
<> 161:2cc1468da177 1751 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 1752 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 1753 #define ADC_CR2_SWSTART_Pos (30U)
<> 161:2cc1468da177 1754 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 1755 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
<> 144:ef7eb2e8f9f7 1756
<> 144:ef7eb2e8f9f7 1757 /****************** Bit definition for ADC_SMPR1 register *******************/
<> 161:2cc1468da177 1758 #define ADC_SMPR1_SMP10_Pos (0U)
<> 161:2cc1468da177 1759 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 1760 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
<> 161:2cc1468da177 1761 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 1762 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 1763 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 1764 #define ADC_SMPR1_SMP11_Pos (3U)
<> 161:2cc1468da177 1765 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
<> 161:2cc1468da177 1766 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
<> 161:2cc1468da177 1767 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 1768 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 1769 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 1770 #define ADC_SMPR1_SMP12_Pos (6U)
<> 161:2cc1468da177 1771 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
<> 161:2cc1468da177 1772 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
<> 161:2cc1468da177 1773 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 1774 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 1775 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 1776 #define ADC_SMPR1_SMP13_Pos (9U)
<> 161:2cc1468da177 1777 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
<> 161:2cc1468da177 1778 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
<> 161:2cc1468da177 1779 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 1780 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 1781 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 1782 #define ADC_SMPR1_SMP14_Pos (12U)
<> 161:2cc1468da177 1783 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
<> 161:2cc1468da177 1784 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
<> 161:2cc1468da177 1785 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 1786 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 1787 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 1788 #define ADC_SMPR1_SMP15_Pos (15U)
<> 161:2cc1468da177 1789 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
<> 161:2cc1468da177 1790 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
<> 161:2cc1468da177 1791 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 1792 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 1793 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 1794 #define ADC_SMPR1_SMP16_Pos (18U)
<> 161:2cc1468da177 1795 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
<> 161:2cc1468da177 1796 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
<> 161:2cc1468da177 1797 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 1798 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 1799 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 1800 #define ADC_SMPR1_SMP17_Pos (21U)
<> 161:2cc1468da177 1801 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
<> 161:2cc1468da177 1802 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
<> 161:2cc1468da177 1803 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 1804 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 1805 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 1806 #define ADC_SMPR1_SMP18_Pos (24U)
<> 161:2cc1468da177 1807 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
<> 161:2cc1468da177 1808 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
<> 161:2cc1468da177 1809 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 1810 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 1811 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 /****************** Bit definition for ADC_SMPR2 register *******************/
<> 161:2cc1468da177 1814 #define ADC_SMPR2_SMP0_Pos (0U)
<> 161:2cc1468da177 1815 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 1816 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
<> 161:2cc1468da177 1817 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 1818 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 1819 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 1820 #define ADC_SMPR2_SMP1_Pos (3U)
<> 161:2cc1468da177 1821 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
<> 161:2cc1468da177 1822 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
<> 161:2cc1468da177 1823 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 1824 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 1825 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 1826 #define ADC_SMPR2_SMP2_Pos (6U)
<> 161:2cc1468da177 1827 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
<> 161:2cc1468da177 1828 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
<> 161:2cc1468da177 1829 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 1830 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 1831 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 1832 #define ADC_SMPR2_SMP3_Pos (9U)
<> 161:2cc1468da177 1833 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
<> 161:2cc1468da177 1834 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
<> 161:2cc1468da177 1835 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 1836 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 1837 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 1838 #define ADC_SMPR2_SMP4_Pos (12U)
<> 161:2cc1468da177 1839 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
<> 161:2cc1468da177 1840 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
<> 161:2cc1468da177 1841 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 1842 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 1843 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 1844 #define ADC_SMPR2_SMP5_Pos (15U)
<> 161:2cc1468da177 1845 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
<> 161:2cc1468da177 1846 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
<> 161:2cc1468da177 1847 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 1848 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 1849 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 1850 #define ADC_SMPR2_SMP6_Pos (18U)
<> 161:2cc1468da177 1851 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
<> 161:2cc1468da177 1852 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
<> 161:2cc1468da177 1853 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 1854 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 1855 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 1856 #define ADC_SMPR2_SMP7_Pos (21U)
<> 161:2cc1468da177 1857 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
<> 161:2cc1468da177 1858 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
<> 161:2cc1468da177 1859 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 1860 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 1861 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 1862 #define ADC_SMPR2_SMP8_Pos (24U)
<> 161:2cc1468da177 1863 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
<> 161:2cc1468da177 1864 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
<> 161:2cc1468da177 1865 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 1866 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 1867 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 1868 #define ADC_SMPR2_SMP9_Pos (27U)
<> 161:2cc1468da177 1869 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
<> 161:2cc1468da177 1870 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
<> 161:2cc1468da177 1871 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 1872 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 1873 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 1874
<> 144:ef7eb2e8f9f7 1875 /****************** Bit definition for ADC_JOFR1 register *******************/
<> 161:2cc1468da177 1876 #define ADC_JOFR1_JOFFSET1_Pos (0U)
<> 161:2cc1468da177 1877 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 1878 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
<> 144:ef7eb2e8f9f7 1879
<> 144:ef7eb2e8f9f7 1880 /****************** Bit definition for ADC_JOFR2 register *******************/
<> 161:2cc1468da177 1881 #define ADC_JOFR2_JOFFSET2_Pos (0U)
<> 161:2cc1468da177 1882 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 1883 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
<> 144:ef7eb2e8f9f7 1884
<> 144:ef7eb2e8f9f7 1885 /****************** Bit definition for ADC_JOFR3 register *******************/
<> 161:2cc1468da177 1886 #define ADC_JOFR3_JOFFSET3_Pos (0U)
<> 161:2cc1468da177 1887 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 1888 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
<> 144:ef7eb2e8f9f7 1889
<> 144:ef7eb2e8f9f7 1890 /****************** Bit definition for ADC_JOFR4 register *******************/
<> 161:2cc1468da177 1891 #define ADC_JOFR4_JOFFSET4_Pos (0U)
<> 161:2cc1468da177 1892 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 1893 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
<> 144:ef7eb2e8f9f7 1894
<> 144:ef7eb2e8f9f7 1895 /******************* Bit definition for ADC_HTR register ********************/
<> 161:2cc1468da177 1896 #define ADC_HTR_HT_Pos (0U)
<> 161:2cc1468da177 1897 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 1898 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
<> 144:ef7eb2e8f9f7 1899
<> 144:ef7eb2e8f9f7 1900 /******************* Bit definition for ADC_LTR register ********************/
<> 161:2cc1468da177 1901 #define ADC_LTR_LT_Pos (0U)
<> 161:2cc1468da177 1902 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 1903 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
<> 144:ef7eb2e8f9f7 1904
<> 144:ef7eb2e8f9f7 1905 /******************* Bit definition for ADC_SQR1 register *******************/
<> 161:2cc1468da177 1906 #define ADC_SQR1_SQ13_Pos (0U)
<> 161:2cc1468da177 1907 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
<> 161:2cc1468da177 1908 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
<> 161:2cc1468da177 1909 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 1910 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 1911 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 1912 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 1913 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 1914 #define ADC_SQR1_SQ14_Pos (5U)
<> 161:2cc1468da177 1915 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
<> 161:2cc1468da177 1916 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
<> 161:2cc1468da177 1917 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 1918 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 1919 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 1920 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 1921 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 1922 #define ADC_SQR1_SQ15_Pos (10U)
<> 161:2cc1468da177 1923 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
<> 161:2cc1468da177 1924 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
<> 161:2cc1468da177 1925 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 1926 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 1927 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 1928 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 1929 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 1930 #define ADC_SQR1_SQ16_Pos (15U)
<> 161:2cc1468da177 1931 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
<> 161:2cc1468da177 1932 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
<> 161:2cc1468da177 1933 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 1934 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 1935 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 1936 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 1937 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 1938 #define ADC_SQR1_L_Pos (20U)
<> 161:2cc1468da177 1939 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 1940 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
<> 161:2cc1468da177 1941 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 1942 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 1943 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 1944 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 1945
<> 144:ef7eb2e8f9f7 1946 /******************* Bit definition for ADC_SQR2 register *******************/
<> 161:2cc1468da177 1947 #define ADC_SQR2_SQ7_Pos (0U)
<> 161:2cc1468da177 1948 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
<> 161:2cc1468da177 1949 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
<> 161:2cc1468da177 1950 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 1951 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 1952 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 1953 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 1954 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 1955 #define ADC_SQR2_SQ8_Pos (5U)
<> 161:2cc1468da177 1956 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
<> 161:2cc1468da177 1957 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
<> 161:2cc1468da177 1958 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 1959 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 1960 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 1961 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 1962 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 1963 #define ADC_SQR2_SQ9_Pos (10U)
<> 161:2cc1468da177 1964 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
<> 161:2cc1468da177 1965 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
<> 161:2cc1468da177 1966 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 1967 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 1968 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 1969 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 1970 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 1971 #define ADC_SQR2_SQ10_Pos (15U)
<> 161:2cc1468da177 1972 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
<> 161:2cc1468da177 1973 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
<> 161:2cc1468da177 1974 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 1975 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 1976 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 1977 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 1978 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 1979 #define ADC_SQR2_SQ11_Pos (20U)
<> 161:2cc1468da177 1980 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
<> 161:2cc1468da177 1981 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
<> 161:2cc1468da177 1982 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 1983 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 1984 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 1985 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 1986 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 1987 #define ADC_SQR2_SQ12_Pos (25U)
<> 161:2cc1468da177 1988 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
<> 161:2cc1468da177 1989 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
<> 161:2cc1468da177 1990 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 1991 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 1992 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 1993 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 1994 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 1995
<> 144:ef7eb2e8f9f7 1996 /******************* Bit definition for ADC_SQR3 register *******************/
<> 161:2cc1468da177 1997 #define ADC_SQR3_SQ1_Pos (0U)
<> 161:2cc1468da177 1998 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
<> 161:2cc1468da177 1999 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
<> 161:2cc1468da177 2000 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2001 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2002 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2003 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2004 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2005 #define ADC_SQR3_SQ2_Pos (5U)
<> 161:2cc1468da177 2006 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
<> 161:2cc1468da177 2007 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
<> 161:2cc1468da177 2008 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2009 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 2010 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 2011 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2012 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2013 #define ADC_SQR3_SQ3_Pos (10U)
<> 161:2cc1468da177 2014 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
<> 161:2cc1468da177 2015 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
<> 161:2cc1468da177 2016 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2017 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2018 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 2019 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 2020 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 2021 #define ADC_SQR3_SQ4_Pos (15U)
<> 161:2cc1468da177 2022 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
<> 161:2cc1468da177 2023 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
<> 161:2cc1468da177 2024 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 2025 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 2026 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 2027 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 2028 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 2029 #define ADC_SQR3_SQ5_Pos (20U)
<> 161:2cc1468da177 2030 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
<> 161:2cc1468da177 2031 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
<> 161:2cc1468da177 2032 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 2033 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 2034 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 2035 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 2036 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 2037 #define ADC_SQR3_SQ6_Pos (25U)
<> 161:2cc1468da177 2038 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
<> 161:2cc1468da177 2039 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
<> 161:2cc1468da177 2040 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 2041 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 2042 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 2043 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 2044 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 2045
<> 144:ef7eb2e8f9f7 2046 /******************* Bit definition for ADC_JSQR register *******************/
<> 161:2cc1468da177 2047 #define ADC_JSQR_JSQ1_Pos (0U)
<> 161:2cc1468da177 2048 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
<> 161:2cc1468da177 2049 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
<> 161:2cc1468da177 2050 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2051 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2052 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2053 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2054 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2055 #define ADC_JSQR_JSQ2_Pos (5U)
<> 161:2cc1468da177 2056 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
<> 161:2cc1468da177 2057 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
<> 161:2cc1468da177 2058 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2059 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 2060 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 2061 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2062 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2063 #define ADC_JSQR_JSQ3_Pos (10U)
<> 161:2cc1468da177 2064 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
<> 161:2cc1468da177 2065 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
<> 161:2cc1468da177 2066 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2067 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2068 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 2069 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 2070 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 2071 #define ADC_JSQR_JSQ4_Pos (15U)
<> 161:2cc1468da177 2072 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
<> 161:2cc1468da177 2073 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
<> 161:2cc1468da177 2074 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 2075 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 2076 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 2077 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 2078 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 2079 #define ADC_JSQR_JL_Pos (20U)
<> 161:2cc1468da177 2080 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 2081 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
<> 161:2cc1468da177 2082 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 2083 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 2084
<> 144:ef7eb2e8f9f7 2085 /******************* Bit definition for ADC_JDR1 register *******************/
<> 161:2cc1468da177 2086 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
<> 144:ef7eb2e8f9f7 2087
<> 144:ef7eb2e8f9f7 2088 /******************* Bit definition for ADC_JDR2 register *******************/
<> 161:2cc1468da177 2089 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
<> 144:ef7eb2e8f9f7 2090
<> 144:ef7eb2e8f9f7 2091 /******************* Bit definition for ADC_JDR3 register *******************/
<> 161:2cc1468da177 2092 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
<> 144:ef7eb2e8f9f7 2093
<> 144:ef7eb2e8f9f7 2094 /******************* Bit definition for ADC_JDR4 register *******************/
<> 161:2cc1468da177 2095 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
<> 144:ef7eb2e8f9f7 2096
<> 144:ef7eb2e8f9f7 2097 /******************** Bit definition for ADC_DR register ********************/
<> 161:2cc1468da177 2098 #define ADC_DR_DATA_Pos (0U)
<> 161:2cc1468da177 2099 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 2100 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
<> 161:2cc1468da177 2101 #define ADC_DR_ADC2DATA_Pos (16U)
<> 161:2cc1468da177 2102 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 2103 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
<> 144:ef7eb2e8f9f7 2104
<> 144:ef7eb2e8f9f7 2105 /******************* Bit definition for ADC_CSR register ********************/
<> 161:2cc1468da177 2106 #define ADC_CSR_AWD1_Pos (0U)
<> 161:2cc1468da177 2107 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2108 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
<> 161:2cc1468da177 2109 #define ADC_CSR_EOC1_Pos (1U)
<> 161:2cc1468da177 2110 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2111 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
<> 161:2cc1468da177 2112 #define ADC_CSR_JEOC1_Pos (2U)
<> 161:2cc1468da177 2113 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2114 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
<> 161:2cc1468da177 2115 #define ADC_CSR_JSTRT1_Pos (3U)
<> 161:2cc1468da177 2116 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2117 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
<> 161:2cc1468da177 2118 #define ADC_CSR_STRT1_Pos (4U)
<> 161:2cc1468da177 2119 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2120 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
<> 161:2cc1468da177 2121 #define ADC_CSR_OVR1_Pos (5U)
<> 161:2cc1468da177 2122 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2123 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 Overrun flag */
<> 161:2cc1468da177 2124 #define ADC_CSR_AWD2_Pos (8U)
<> 161:2cc1468da177 2125 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2126 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
<> 161:2cc1468da177 2127 #define ADC_CSR_EOC2_Pos (9U)
<> 161:2cc1468da177 2128 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2129 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
<> 161:2cc1468da177 2130 #define ADC_CSR_JEOC2_Pos (10U)
<> 161:2cc1468da177 2131 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2132 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
<> 161:2cc1468da177 2133 #define ADC_CSR_JSTRT2_Pos (11U)
<> 161:2cc1468da177 2134 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2135 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
<> 161:2cc1468da177 2136 #define ADC_CSR_STRT2_Pos (12U)
<> 161:2cc1468da177 2137 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 2138 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
<> 161:2cc1468da177 2139 #define ADC_CSR_OVR2_Pos (13U)
<> 161:2cc1468da177 2140 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 2141 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 Overrun flag */
<> 161:2cc1468da177 2142 #define ADC_CSR_AWD3_Pos (16U)
<> 161:2cc1468da177 2143 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 2144 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
<> 161:2cc1468da177 2145 #define ADC_CSR_EOC3_Pos (17U)
<> 161:2cc1468da177 2146 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 2147 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
<> 161:2cc1468da177 2148 #define ADC_CSR_JEOC3_Pos (18U)
<> 161:2cc1468da177 2149 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 2150 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
<> 161:2cc1468da177 2151 #define ADC_CSR_JSTRT3_Pos (19U)
<> 161:2cc1468da177 2152 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 2153 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
<> 161:2cc1468da177 2154 #define ADC_CSR_STRT3_Pos (20U)
<> 161:2cc1468da177 2155 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 2156 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
<> 161:2cc1468da177 2157 #define ADC_CSR_OVR3_Pos (21U)
<> 161:2cc1468da177 2158 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 2159 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 Overrun flag */
<> 144:ef7eb2e8f9f7 2160
<> 144:ef7eb2e8f9f7 2161 /* Legacy defines */
<> 144:ef7eb2e8f9f7 2162 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
<> 144:ef7eb2e8f9f7 2163 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
<> 144:ef7eb2e8f9f7 2164 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
<> 144:ef7eb2e8f9f7 2165
<> 144:ef7eb2e8f9f7 2166
<> 144:ef7eb2e8f9f7 2167 /******************* Bit definition for ADC_CCR register ********************/
<> 161:2cc1468da177 2168 #define ADC_CCR_MULTI_Pos (0U)
<> 161:2cc1468da177 2169 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
<> 161:2cc1468da177 2170 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
<> 161:2cc1468da177 2171 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2172 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2173 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2174 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2175 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2176 #define ADC_CCR_DELAY_Pos (8U)
<> 161:2cc1468da177 2177 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 2178 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
<> 161:2cc1468da177 2179 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2180 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2181 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2182 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2183 #define ADC_CCR_DDS_Pos (13U)
<> 161:2cc1468da177 2184 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 2185 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
<> 161:2cc1468da177 2186 #define ADC_CCR_DMA_Pos (14U)
<> 161:2cc1468da177 2187 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 2188 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
<> 161:2cc1468da177 2189 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 2190 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 2191 #define ADC_CCR_ADCPRE_Pos (16U)
<> 161:2cc1468da177 2192 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 2193 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
<> 161:2cc1468da177 2194 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 2195 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 2196 #define ADC_CCR_VBATE_Pos (22U)
<> 161:2cc1468da177 2197 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 2198 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
<> 161:2cc1468da177 2199 #define ADC_CCR_TSVREFE_Pos (23U)
<> 161:2cc1468da177 2200 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 2201 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
<> 144:ef7eb2e8f9f7 2202
<> 144:ef7eb2e8f9f7 2203 /******************* Bit definition for ADC_CDR register ********************/
<> 161:2cc1468da177 2204 #define ADC_CDR_DATA1_Pos (0U)
<> 161:2cc1468da177 2205 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 2206 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
<> 161:2cc1468da177 2207 #define ADC_CDR_DATA2_Pos (16U)
<> 161:2cc1468da177 2208 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 2209 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
<> 161:2cc1468da177 2210
<> 161:2cc1468da177 2211 /* Legacy defines */
<> 161:2cc1468da177 2212 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
<> 161:2cc1468da177 2213 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
<> 144:ef7eb2e8f9f7 2214
<> 144:ef7eb2e8f9f7 2215 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2216 /* */
<> 144:ef7eb2e8f9f7 2217 /* Controller Area Network */
<> 144:ef7eb2e8f9f7 2218 /* */
<> 144:ef7eb2e8f9f7 2219 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2220 /*!<CAN control and status registers */
<> 144:ef7eb2e8f9f7 2221 /******************* Bit definition for CAN_MCR register ********************/
<> 161:2cc1468da177 2222 #define CAN_MCR_INRQ_Pos (0U)
<> 161:2cc1468da177 2223 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2224 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
<> 161:2cc1468da177 2225 #define CAN_MCR_SLEEP_Pos (1U)
<> 161:2cc1468da177 2226 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2227 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
<> 161:2cc1468da177 2228 #define CAN_MCR_TXFP_Pos (2U)
<> 161:2cc1468da177 2229 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2230 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
<> 161:2cc1468da177 2231 #define CAN_MCR_RFLM_Pos (3U)
<> 161:2cc1468da177 2232 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2233 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
<> 161:2cc1468da177 2234 #define CAN_MCR_NART_Pos (4U)
<> 161:2cc1468da177 2235 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2236 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
<> 161:2cc1468da177 2237 #define CAN_MCR_AWUM_Pos (5U)
<> 161:2cc1468da177 2238 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2239 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
<> 161:2cc1468da177 2240 #define CAN_MCR_ABOM_Pos (6U)
<> 161:2cc1468da177 2241 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 2242 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
<> 161:2cc1468da177 2243 #define CAN_MCR_TTCM_Pos (7U)
<> 161:2cc1468da177 2244 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 2245 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
<> 161:2cc1468da177 2246 #define CAN_MCR_RESET_Pos (15U)
<> 161:2cc1468da177 2247 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 2248 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
<> 161:2cc1468da177 2249
<> 144:ef7eb2e8f9f7 2250 /******************* Bit definition for CAN_MSR register ********************/
<> 161:2cc1468da177 2251 #define CAN_MSR_INAK_Pos (0U)
<> 161:2cc1468da177 2252 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2253 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
<> 161:2cc1468da177 2254 #define CAN_MSR_SLAK_Pos (1U)
<> 161:2cc1468da177 2255 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2256 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
<> 161:2cc1468da177 2257 #define CAN_MSR_ERRI_Pos (2U)
<> 161:2cc1468da177 2258 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2259 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
<> 161:2cc1468da177 2260 #define CAN_MSR_WKUI_Pos (3U)
<> 161:2cc1468da177 2261 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2262 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
<> 161:2cc1468da177 2263 #define CAN_MSR_SLAKI_Pos (4U)
<> 161:2cc1468da177 2264 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2265 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
<> 161:2cc1468da177 2266 #define CAN_MSR_TXM_Pos (8U)
<> 161:2cc1468da177 2267 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2268 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
<> 161:2cc1468da177 2269 #define CAN_MSR_RXM_Pos (9U)
<> 161:2cc1468da177 2270 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2271 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
<> 161:2cc1468da177 2272 #define CAN_MSR_SAMP_Pos (10U)
<> 161:2cc1468da177 2273 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2274 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
<> 161:2cc1468da177 2275 #define CAN_MSR_RX_Pos (11U)
<> 161:2cc1468da177 2276 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2277 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
<> 144:ef7eb2e8f9f7 2278
<> 144:ef7eb2e8f9f7 2279 /******************* Bit definition for CAN_TSR register ********************/
<> 161:2cc1468da177 2280 #define CAN_TSR_RQCP0_Pos (0U)
<> 161:2cc1468da177 2281 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2282 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
<> 161:2cc1468da177 2283 #define CAN_TSR_TXOK0_Pos (1U)
<> 161:2cc1468da177 2284 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2285 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
<> 161:2cc1468da177 2286 #define CAN_TSR_ALST0_Pos (2U)
<> 161:2cc1468da177 2287 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2288 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
<> 161:2cc1468da177 2289 #define CAN_TSR_TERR0_Pos (3U)
<> 161:2cc1468da177 2290 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2291 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
<> 161:2cc1468da177 2292 #define CAN_TSR_ABRQ0_Pos (7U)
<> 161:2cc1468da177 2293 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 2294 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
<> 161:2cc1468da177 2295 #define CAN_TSR_RQCP1_Pos (8U)
<> 161:2cc1468da177 2296 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2297 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
<> 161:2cc1468da177 2298 #define CAN_TSR_TXOK1_Pos (9U)
<> 161:2cc1468da177 2299 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2300 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
<> 161:2cc1468da177 2301 #define CAN_TSR_ALST1_Pos (10U)
<> 161:2cc1468da177 2302 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2303 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
<> 161:2cc1468da177 2304 #define CAN_TSR_TERR1_Pos (11U)
<> 161:2cc1468da177 2305 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2306 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
<> 161:2cc1468da177 2307 #define CAN_TSR_ABRQ1_Pos (15U)
<> 161:2cc1468da177 2308 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 2309 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
<> 161:2cc1468da177 2310 #define CAN_TSR_RQCP2_Pos (16U)
<> 161:2cc1468da177 2311 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 2312 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
<> 161:2cc1468da177 2313 #define CAN_TSR_TXOK2_Pos (17U)
<> 161:2cc1468da177 2314 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 2315 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
<> 161:2cc1468da177 2316 #define CAN_TSR_ALST2_Pos (18U)
<> 161:2cc1468da177 2317 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 2318 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
<> 161:2cc1468da177 2319 #define CAN_TSR_TERR2_Pos (19U)
<> 161:2cc1468da177 2320 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 2321 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
<> 161:2cc1468da177 2322 #define CAN_TSR_ABRQ2_Pos (23U)
<> 161:2cc1468da177 2323 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 2324 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
<> 161:2cc1468da177 2325 #define CAN_TSR_CODE_Pos (24U)
<> 161:2cc1468da177 2326 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
<> 161:2cc1468da177 2327 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
<> 161:2cc1468da177 2328
<> 161:2cc1468da177 2329 #define CAN_TSR_TME_Pos (26U)
<> 161:2cc1468da177 2330 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
<> 161:2cc1468da177 2331 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
<> 161:2cc1468da177 2332 #define CAN_TSR_TME0_Pos (26U)
<> 161:2cc1468da177 2333 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 2334 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
<> 161:2cc1468da177 2335 #define CAN_TSR_TME1_Pos (27U)
<> 161:2cc1468da177 2336 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 2337 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
<> 161:2cc1468da177 2338 #define CAN_TSR_TME2_Pos (28U)
<> 161:2cc1468da177 2339 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 2340 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
<> 161:2cc1468da177 2341
<> 161:2cc1468da177 2342 #define CAN_TSR_LOW_Pos (29U)
<> 161:2cc1468da177 2343 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
<> 161:2cc1468da177 2344 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
<> 161:2cc1468da177 2345 #define CAN_TSR_LOW0_Pos (29U)
<> 161:2cc1468da177 2346 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 2347 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
<> 161:2cc1468da177 2348 #define CAN_TSR_LOW1_Pos (30U)
<> 161:2cc1468da177 2349 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 2350 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
<> 161:2cc1468da177 2351 #define CAN_TSR_LOW2_Pos (31U)
<> 161:2cc1468da177 2352 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 2353 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
<> 144:ef7eb2e8f9f7 2354
<> 144:ef7eb2e8f9f7 2355 /******************* Bit definition for CAN_RF0R register *******************/
<> 161:2cc1468da177 2356 #define CAN_RF0R_FMP0_Pos (0U)
<> 161:2cc1468da177 2357 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 2358 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
<> 161:2cc1468da177 2359 #define CAN_RF0R_FULL0_Pos (3U)
<> 161:2cc1468da177 2360 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2361 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
<> 161:2cc1468da177 2362 #define CAN_RF0R_FOVR0_Pos (4U)
<> 161:2cc1468da177 2363 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2364 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
<> 161:2cc1468da177 2365 #define CAN_RF0R_RFOM0_Pos (5U)
<> 161:2cc1468da177 2366 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2367 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
<> 144:ef7eb2e8f9f7 2368
<> 144:ef7eb2e8f9f7 2369 /******************* Bit definition for CAN_RF1R register *******************/
<> 161:2cc1468da177 2370 #define CAN_RF1R_FMP1_Pos (0U)
<> 161:2cc1468da177 2371 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 2372 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
<> 161:2cc1468da177 2373 #define CAN_RF1R_FULL1_Pos (3U)
<> 161:2cc1468da177 2374 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2375 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
<> 161:2cc1468da177 2376 #define CAN_RF1R_FOVR1_Pos (4U)
<> 161:2cc1468da177 2377 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2378 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
<> 161:2cc1468da177 2379 #define CAN_RF1R_RFOM1_Pos (5U)
<> 161:2cc1468da177 2380 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2381 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
<> 144:ef7eb2e8f9f7 2382
<> 144:ef7eb2e8f9f7 2383 /******************** Bit definition for CAN_IER register *******************/
<> 161:2cc1468da177 2384 #define CAN_IER_TMEIE_Pos (0U)
<> 161:2cc1468da177 2385 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2386 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
<> 161:2cc1468da177 2387 #define CAN_IER_FMPIE0_Pos (1U)
<> 161:2cc1468da177 2388 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2389 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
<> 161:2cc1468da177 2390 #define CAN_IER_FFIE0_Pos (2U)
<> 161:2cc1468da177 2391 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2392 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
<> 161:2cc1468da177 2393 #define CAN_IER_FOVIE0_Pos (3U)
<> 161:2cc1468da177 2394 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2395 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
<> 161:2cc1468da177 2396 #define CAN_IER_FMPIE1_Pos (4U)
<> 161:2cc1468da177 2397 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2398 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
<> 161:2cc1468da177 2399 #define CAN_IER_FFIE1_Pos (5U)
<> 161:2cc1468da177 2400 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2401 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
<> 161:2cc1468da177 2402 #define CAN_IER_FOVIE1_Pos (6U)
<> 161:2cc1468da177 2403 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 2404 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
<> 161:2cc1468da177 2405 #define CAN_IER_EWGIE_Pos (8U)
<> 161:2cc1468da177 2406 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2407 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
<> 161:2cc1468da177 2408 #define CAN_IER_EPVIE_Pos (9U)
<> 161:2cc1468da177 2409 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2410 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
<> 161:2cc1468da177 2411 #define CAN_IER_BOFIE_Pos (10U)
<> 161:2cc1468da177 2412 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2413 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
<> 161:2cc1468da177 2414 #define CAN_IER_LECIE_Pos (11U)
<> 161:2cc1468da177 2415 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2416 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
<> 161:2cc1468da177 2417 #define CAN_IER_ERRIE_Pos (15U)
<> 161:2cc1468da177 2418 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 2419 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
<> 161:2cc1468da177 2420 #define CAN_IER_WKUIE_Pos (16U)
<> 161:2cc1468da177 2421 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 2422 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
<> 161:2cc1468da177 2423 #define CAN_IER_SLKIE_Pos (17U)
<> 161:2cc1468da177 2424 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 2425 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
<> 144:ef7eb2e8f9f7 2426
<> 144:ef7eb2e8f9f7 2427 /******************** Bit definition for CAN_ESR register *******************/
<> 161:2cc1468da177 2428 #define CAN_ESR_EWGF_Pos (0U)
<> 161:2cc1468da177 2429 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2430 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
<> 161:2cc1468da177 2431 #define CAN_ESR_EPVF_Pos (1U)
<> 161:2cc1468da177 2432 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2433 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
<> 161:2cc1468da177 2434 #define CAN_ESR_BOFF_Pos (2U)
<> 161:2cc1468da177 2435 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2436 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
<> 161:2cc1468da177 2437
<> 161:2cc1468da177 2438 #define CAN_ESR_LEC_Pos (4U)
<> 161:2cc1468da177 2439 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
<> 161:2cc1468da177 2440 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
<> 161:2cc1468da177 2441 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2442 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2443 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 2444
<> 161:2cc1468da177 2445 #define CAN_ESR_TEC_Pos (16U)
<> 161:2cc1468da177 2446 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2447 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
<> 161:2cc1468da177 2448 #define CAN_ESR_REC_Pos (24U)
<> 161:2cc1468da177 2449 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2450 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
<> 144:ef7eb2e8f9f7 2451
<> 144:ef7eb2e8f9f7 2452 /******************* Bit definition for CAN_BTR register ********************/
<> 161:2cc1468da177 2453 #define CAN_BTR_BRP_Pos (0U)
<> 161:2cc1468da177 2454 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
<> 161:2cc1468da177 2455 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
<> 161:2cc1468da177 2456 #define CAN_BTR_TS1_Pos (16U)
<> 161:2cc1468da177 2457 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 2458 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
<> 161:2cc1468da177 2459 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 2460 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 2461 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 2462 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 2463 #define CAN_BTR_TS2_Pos (20U)
<> 161:2cc1468da177 2464 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
<> 161:2cc1468da177 2465 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
<> 161:2cc1468da177 2466 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 2467 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 2468 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 2469 #define CAN_BTR_SJW_Pos (24U)
<> 161:2cc1468da177 2470 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
<> 161:2cc1468da177 2471 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
<> 161:2cc1468da177 2472 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 2473 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 2474 #define CAN_BTR_LBKM_Pos (30U)
<> 161:2cc1468da177 2475 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 2476 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
<> 161:2cc1468da177 2477 #define CAN_BTR_SILM_Pos (31U)
<> 161:2cc1468da177 2478 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 2479 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
<> 144:ef7eb2e8f9f7 2480
<> 144:ef7eb2e8f9f7 2481 /*!<Mailbox registers */
<> 144:ef7eb2e8f9f7 2482 /****************** Bit definition for CAN_TI0R register ********************/
<> 161:2cc1468da177 2483 #define CAN_TI0R_TXRQ_Pos (0U)
<> 161:2cc1468da177 2484 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2485 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 161:2cc1468da177 2486 #define CAN_TI0R_RTR_Pos (1U)
<> 161:2cc1468da177 2487 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2488 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
<> 161:2cc1468da177 2489 #define CAN_TI0R_IDE_Pos (2U)
<> 161:2cc1468da177 2490 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2491 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
<> 161:2cc1468da177 2492 #define CAN_TI0R_EXID_Pos (3U)
<> 161:2cc1468da177 2493 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
<> 161:2cc1468da177 2494 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
<> 161:2cc1468da177 2495 #define CAN_TI0R_STID_Pos (21U)
<> 161:2cc1468da177 2496 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
<> 161:2cc1468da177 2497 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 2498
<> 144:ef7eb2e8f9f7 2499 /****************** Bit definition for CAN_TDT0R register *******************/
<> 161:2cc1468da177 2500 #define CAN_TDT0R_DLC_Pos (0U)
<> 161:2cc1468da177 2501 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 2502 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
<> 161:2cc1468da177 2503 #define CAN_TDT0R_TGT_Pos (8U)
<> 161:2cc1468da177 2504 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2505 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
<> 161:2cc1468da177 2506 #define CAN_TDT0R_TIME_Pos (16U)
<> 161:2cc1468da177 2507 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 2508 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 2509
<> 144:ef7eb2e8f9f7 2510 /****************** Bit definition for CAN_TDL0R register *******************/
<> 161:2cc1468da177 2511 #define CAN_TDL0R_DATA0_Pos (0U)
<> 161:2cc1468da177 2512 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 2513 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
<> 161:2cc1468da177 2514 #define CAN_TDL0R_DATA1_Pos (8U)
<> 161:2cc1468da177 2515 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2516 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
<> 161:2cc1468da177 2517 #define CAN_TDL0R_DATA2_Pos (16U)
<> 161:2cc1468da177 2518 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2519 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
<> 161:2cc1468da177 2520 #define CAN_TDL0R_DATA3_Pos (24U)
<> 161:2cc1468da177 2521 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2522 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 2523
<> 144:ef7eb2e8f9f7 2524 /****************** Bit definition for CAN_TDH0R register *******************/
<> 161:2cc1468da177 2525 #define CAN_TDH0R_DATA4_Pos (0U)
<> 161:2cc1468da177 2526 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 2527 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
<> 161:2cc1468da177 2528 #define CAN_TDH0R_DATA5_Pos (8U)
<> 161:2cc1468da177 2529 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2530 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
<> 161:2cc1468da177 2531 #define CAN_TDH0R_DATA6_Pos (16U)
<> 161:2cc1468da177 2532 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2533 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
<> 161:2cc1468da177 2534 #define CAN_TDH0R_DATA7_Pos (24U)
<> 161:2cc1468da177 2535 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2536 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 2537
<> 144:ef7eb2e8f9f7 2538 /******************* Bit definition for CAN_TI1R register *******************/
<> 161:2cc1468da177 2539 #define CAN_TI1R_TXRQ_Pos (0U)
<> 161:2cc1468da177 2540 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2541 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 161:2cc1468da177 2542 #define CAN_TI1R_RTR_Pos (1U)
<> 161:2cc1468da177 2543 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2544 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
<> 161:2cc1468da177 2545 #define CAN_TI1R_IDE_Pos (2U)
<> 161:2cc1468da177 2546 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2547 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
<> 161:2cc1468da177 2548 #define CAN_TI1R_EXID_Pos (3U)
<> 161:2cc1468da177 2549 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
<> 161:2cc1468da177 2550 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
<> 161:2cc1468da177 2551 #define CAN_TI1R_STID_Pos (21U)
<> 161:2cc1468da177 2552 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
<> 161:2cc1468da177 2553 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 2554
<> 144:ef7eb2e8f9f7 2555 /******************* Bit definition for CAN_TDT1R register ******************/
<> 161:2cc1468da177 2556 #define CAN_TDT1R_DLC_Pos (0U)
<> 161:2cc1468da177 2557 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 2558 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
<> 161:2cc1468da177 2559 #define CAN_TDT1R_TGT_Pos (8U)
<> 161:2cc1468da177 2560 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2561 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
<> 161:2cc1468da177 2562 #define CAN_TDT1R_TIME_Pos (16U)
<> 161:2cc1468da177 2563 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 2564 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 2565
<> 144:ef7eb2e8f9f7 2566 /******************* Bit definition for CAN_TDL1R register ******************/
<> 161:2cc1468da177 2567 #define CAN_TDL1R_DATA0_Pos (0U)
<> 161:2cc1468da177 2568 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 2569 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
<> 161:2cc1468da177 2570 #define CAN_TDL1R_DATA1_Pos (8U)
<> 161:2cc1468da177 2571 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2572 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
<> 161:2cc1468da177 2573 #define CAN_TDL1R_DATA2_Pos (16U)
<> 161:2cc1468da177 2574 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2575 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
<> 161:2cc1468da177 2576 #define CAN_TDL1R_DATA3_Pos (24U)
<> 161:2cc1468da177 2577 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2578 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 2579
<> 144:ef7eb2e8f9f7 2580 /******************* Bit definition for CAN_TDH1R register ******************/
<> 161:2cc1468da177 2581 #define CAN_TDH1R_DATA4_Pos (0U)
<> 161:2cc1468da177 2582 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 2583 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
<> 161:2cc1468da177 2584 #define CAN_TDH1R_DATA5_Pos (8U)
<> 161:2cc1468da177 2585 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2586 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
<> 161:2cc1468da177 2587 #define CAN_TDH1R_DATA6_Pos (16U)
<> 161:2cc1468da177 2588 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2589 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
<> 161:2cc1468da177 2590 #define CAN_TDH1R_DATA7_Pos (24U)
<> 161:2cc1468da177 2591 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2592 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 2593
<> 144:ef7eb2e8f9f7 2594 /******************* Bit definition for CAN_TI2R register *******************/
<> 161:2cc1468da177 2595 #define CAN_TI2R_TXRQ_Pos (0U)
<> 161:2cc1468da177 2596 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2597 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 161:2cc1468da177 2598 #define CAN_TI2R_RTR_Pos (1U)
<> 161:2cc1468da177 2599 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2600 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
<> 161:2cc1468da177 2601 #define CAN_TI2R_IDE_Pos (2U)
<> 161:2cc1468da177 2602 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2603 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
<> 161:2cc1468da177 2604 #define CAN_TI2R_EXID_Pos (3U)
<> 161:2cc1468da177 2605 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
<> 161:2cc1468da177 2606 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
<> 161:2cc1468da177 2607 #define CAN_TI2R_STID_Pos (21U)
<> 161:2cc1468da177 2608 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
<> 161:2cc1468da177 2609 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 161:2cc1468da177 2610
<> 161:2cc1468da177 2611 /******************* Bit definition for CAN_TDT2R register ******************/
<> 161:2cc1468da177 2612 #define CAN_TDT2R_DLC_Pos (0U)
<> 161:2cc1468da177 2613 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 2614 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
<> 161:2cc1468da177 2615 #define CAN_TDT2R_TGT_Pos (8U)
<> 161:2cc1468da177 2616 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2617 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
<> 161:2cc1468da177 2618 #define CAN_TDT2R_TIME_Pos (16U)
<> 161:2cc1468da177 2619 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 2620 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 2621
<> 144:ef7eb2e8f9f7 2622 /******************* Bit definition for CAN_TDL2R register ******************/
<> 161:2cc1468da177 2623 #define CAN_TDL2R_DATA0_Pos (0U)
<> 161:2cc1468da177 2624 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 2625 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
<> 161:2cc1468da177 2626 #define CAN_TDL2R_DATA1_Pos (8U)
<> 161:2cc1468da177 2627 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2628 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
<> 161:2cc1468da177 2629 #define CAN_TDL2R_DATA2_Pos (16U)
<> 161:2cc1468da177 2630 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2631 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
<> 161:2cc1468da177 2632 #define CAN_TDL2R_DATA3_Pos (24U)
<> 161:2cc1468da177 2633 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2634 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 2635
<> 144:ef7eb2e8f9f7 2636 /******************* Bit definition for CAN_TDH2R register ******************/
<> 161:2cc1468da177 2637 #define CAN_TDH2R_DATA4_Pos (0U)
<> 161:2cc1468da177 2638 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 2639 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
<> 161:2cc1468da177 2640 #define CAN_TDH2R_DATA5_Pos (8U)
<> 161:2cc1468da177 2641 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2642 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
<> 161:2cc1468da177 2643 #define CAN_TDH2R_DATA6_Pos (16U)
<> 161:2cc1468da177 2644 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2645 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
<> 161:2cc1468da177 2646 #define CAN_TDH2R_DATA7_Pos (24U)
<> 161:2cc1468da177 2647 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2648 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 2649
<> 144:ef7eb2e8f9f7 2650 /******************* Bit definition for CAN_RI0R register *******************/
<> 161:2cc1468da177 2651 #define CAN_RI0R_RTR_Pos (1U)
<> 161:2cc1468da177 2652 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2653 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
<> 161:2cc1468da177 2654 #define CAN_RI0R_IDE_Pos (2U)
<> 161:2cc1468da177 2655 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2656 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
<> 161:2cc1468da177 2657 #define CAN_RI0R_EXID_Pos (3U)
<> 161:2cc1468da177 2658 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
<> 161:2cc1468da177 2659 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
<> 161:2cc1468da177 2660 #define CAN_RI0R_STID_Pos (21U)
<> 161:2cc1468da177 2661 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
<> 161:2cc1468da177 2662 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 2663
<> 144:ef7eb2e8f9f7 2664 /******************* Bit definition for CAN_RDT0R register ******************/
<> 161:2cc1468da177 2665 #define CAN_RDT0R_DLC_Pos (0U)
<> 161:2cc1468da177 2666 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 2667 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
<> 161:2cc1468da177 2668 #define CAN_RDT0R_FMI_Pos (8U)
<> 161:2cc1468da177 2669 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2670 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
<> 161:2cc1468da177 2671 #define CAN_RDT0R_TIME_Pos (16U)
<> 161:2cc1468da177 2672 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 2673 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 2674
<> 144:ef7eb2e8f9f7 2675 /******************* Bit definition for CAN_RDL0R register ******************/
<> 161:2cc1468da177 2676 #define CAN_RDL0R_DATA0_Pos (0U)
<> 161:2cc1468da177 2677 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 2678 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
<> 161:2cc1468da177 2679 #define CAN_RDL0R_DATA1_Pos (8U)
<> 161:2cc1468da177 2680 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2681 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
<> 161:2cc1468da177 2682 #define CAN_RDL0R_DATA2_Pos (16U)
<> 161:2cc1468da177 2683 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2684 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
<> 161:2cc1468da177 2685 #define CAN_RDL0R_DATA3_Pos (24U)
<> 161:2cc1468da177 2686 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2687 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 2688
<> 144:ef7eb2e8f9f7 2689 /******************* Bit definition for CAN_RDH0R register ******************/
<> 161:2cc1468da177 2690 #define CAN_RDH0R_DATA4_Pos (0U)
<> 161:2cc1468da177 2691 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 2692 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
<> 161:2cc1468da177 2693 #define CAN_RDH0R_DATA5_Pos (8U)
<> 161:2cc1468da177 2694 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2695 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
<> 161:2cc1468da177 2696 #define CAN_RDH0R_DATA6_Pos (16U)
<> 161:2cc1468da177 2697 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2698 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
<> 161:2cc1468da177 2699 #define CAN_RDH0R_DATA7_Pos (24U)
<> 161:2cc1468da177 2700 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2701 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 2702
<> 144:ef7eb2e8f9f7 2703 /******************* Bit definition for CAN_RI1R register *******************/
<> 161:2cc1468da177 2704 #define CAN_RI1R_RTR_Pos (1U)
<> 161:2cc1468da177 2705 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2706 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
<> 161:2cc1468da177 2707 #define CAN_RI1R_IDE_Pos (2U)
<> 161:2cc1468da177 2708 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2709 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
<> 161:2cc1468da177 2710 #define CAN_RI1R_EXID_Pos (3U)
<> 161:2cc1468da177 2711 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
<> 161:2cc1468da177 2712 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
<> 161:2cc1468da177 2713 #define CAN_RI1R_STID_Pos (21U)
<> 161:2cc1468da177 2714 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
<> 161:2cc1468da177 2715 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 2716
<> 144:ef7eb2e8f9f7 2717 /******************* Bit definition for CAN_RDT1R register ******************/
<> 161:2cc1468da177 2718 #define CAN_RDT1R_DLC_Pos (0U)
<> 161:2cc1468da177 2719 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 2720 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
<> 161:2cc1468da177 2721 #define CAN_RDT1R_FMI_Pos (8U)
<> 161:2cc1468da177 2722 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2723 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
<> 161:2cc1468da177 2724 #define CAN_RDT1R_TIME_Pos (16U)
<> 161:2cc1468da177 2725 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 2726 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 2727
<> 144:ef7eb2e8f9f7 2728 /******************* Bit definition for CAN_RDL1R register ******************/
<> 161:2cc1468da177 2729 #define CAN_RDL1R_DATA0_Pos (0U)
<> 161:2cc1468da177 2730 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 2731 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
<> 161:2cc1468da177 2732 #define CAN_RDL1R_DATA1_Pos (8U)
<> 161:2cc1468da177 2733 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2734 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
<> 161:2cc1468da177 2735 #define CAN_RDL1R_DATA2_Pos (16U)
<> 161:2cc1468da177 2736 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2737 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
<> 161:2cc1468da177 2738 #define CAN_RDL1R_DATA3_Pos (24U)
<> 161:2cc1468da177 2739 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2740 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 2741
<> 144:ef7eb2e8f9f7 2742 /******************* Bit definition for CAN_RDH1R register ******************/
<> 161:2cc1468da177 2743 #define CAN_RDH1R_DATA4_Pos (0U)
<> 161:2cc1468da177 2744 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 2745 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
<> 161:2cc1468da177 2746 #define CAN_RDH1R_DATA5_Pos (8U)
<> 161:2cc1468da177 2747 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 2748 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
<> 161:2cc1468da177 2749 #define CAN_RDH1R_DATA6_Pos (16U)
<> 161:2cc1468da177 2750 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 2751 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
<> 161:2cc1468da177 2752 #define CAN_RDH1R_DATA7_Pos (24U)
<> 161:2cc1468da177 2753 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 2754 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 2755
<> 144:ef7eb2e8f9f7 2756 /*!<CAN filter registers */
<> 144:ef7eb2e8f9f7 2757 /******************* Bit definition for CAN_FMR register ********************/
<> 161:2cc1468da177 2758 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
<> 161:2cc1468da177 2759 #define CAN_FMR_CAN2SB_Pos (8U)
<> 161:2cc1468da177 2760 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
<> 161:2cc1468da177 2761 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
<> 144:ef7eb2e8f9f7 2762
<> 144:ef7eb2e8f9f7 2763 /******************* Bit definition for CAN_FM1R register *******************/
<> 161:2cc1468da177 2764 #define CAN_FM1R_FBM_Pos (0U)
<> 161:2cc1468da177 2765 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
<> 161:2cc1468da177 2766 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
<> 161:2cc1468da177 2767 #define CAN_FM1R_FBM0_Pos (0U)
<> 161:2cc1468da177 2768 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2769 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
<> 161:2cc1468da177 2770 #define CAN_FM1R_FBM1_Pos (1U)
<> 161:2cc1468da177 2771 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2772 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
<> 161:2cc1468da177 2773 #define CAN_FM1R_FBM2_Pos (2U)
<> 161:2cc1468da177 2774 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2775 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
<> 161:2cc1468da177 2776 #define CAN_FM1R_FBM3_Pos (3U)
<> 161:2cc1468da177 2777 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2778 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
<> 161:2cc1468da177 2779 #define CAN_FM1R_FBM4_Pos (4U)
<> 161:2cc1468da177 2780 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2781 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
<> 161:2cc1468da177 2782 #define CAN_FM1R_FBM5_Pos (5U)
<> 161:2cc1468da177 2783 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2784 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
<> 161:2cc1468da177 2785 #define CAN_FM1R_FBM6_Pos (6U)
<> 161:2cc1468da177 2786 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 2787 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
<> 161:2cc1468da177 2788 #define CAN_FM1R_FBM7_Pos (7U)
<> 161:2cc1468da177 2789 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 2790 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
<> 161:2cc1468da177 2791 #define CAN_FM1R_FBM8_Pos (8U)
<> 161:2cc1468da177 2792 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2793 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
<> 161:2cc1468da177 2794 #define CAN_FM1R_FBM9_Pos (9U)
<> 161:2cc1468da177 2795 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2796 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
<> 161:2cc1468da177 2797 #define CAN_FM1R_FBM10_Pos (10U)
<> 161:2cc1468da177 2798 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2799 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
<> 161:2cc1468da177 2800 #define CAN_FM1R_FBM11_Pos (11U)
<> 161:2cc1468da177 2801 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2802 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
<> 161:2cc1468da177 2803 #define CAN_FM1R_FBM12_Pos (12U)
<> 161:2cc1468da177 2804 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 2805 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
<> 161:2cc1468da177 2806 #define CAN_FM1R_FBM13_Pos (13U)
<> 161:2cc1468da177 2807 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 2808 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
<> 144:ef7eb2e8f9f7 2809
<> 144:ef7eb2e8f9f7 2810 /******************* Bit definition for CAN_FS1R register *******************/
<> 161:2cc1468da177 2811 #define CAN_FS1R_FSC_Pos (0U)
<> 161:2cc1468da177 2812 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
<> 161:2cc1468da177 2813 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
<> 161:2cc1468da177 2814 #define CAN_FS1R_FSC0_Pos (0U)
<> 161:2cc1468da177 2815 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2816 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
<> 161:2cc1468da177 2817 #define CAN_FS1R_FSC1_Pos (1U)
<> 161:2cc1468da177 2818 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2819 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
<> 161:2cc1468da177 2820 #define CAN_FS1R_FSC2_Pos (2U)
<> 161:2cc1468da177 2821 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2822 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
<> 161:2cc1468da177 2823 #define CAN_FS1R_FSC3_Pos (3U)
<> 161:2cc1468da177 2824 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2825 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
<> 161:2cc1468da177 2826 #define CAN_FS1R_FSC4_Pos (4U)
<> 161:2cc1468da177 2827 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2828 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
<> 161:2cc1468da177 2829 #define CAN_FS1R_FSC5_Pos (5U)
<> 161:2cc1468da177 2830 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2831 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
<> 161:2cc1468da177 2832 #define CAN_FS1R_FSC6_Pos (6U)
<> 161:2cc1468da177 2833 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 2834 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
<> 161:2cc1468da177 2835 #define CAN_FS1R_FSC7_Pos (7U)
<> 161:2cc1468da177 2836 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 2837 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
<> 161:2cc1468da177 2838 #define CAN_FS1R_FSC8_Pos (8U)
<> 161:2cc1468da177 2839 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2840 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
<> 161:2cc1468da177 2841 #define CAN_FS1R_FSC9_Pos (9U)
<> 161:2cc1468da177 2842 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2843 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
<> 161:2cc1468da177 2844 #define CAN_FS1R_FSC10_Pos (10U)
<> 161:2cc1468da177 2845 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2846 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
<> 161:2cc1468da177 2847 #define CAN_FS1R_FSC11_Pos (11U)
<> 161:2cc1468da177 2848 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2849 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
<> 161:2cc1468da177 2850 #define CAN_FS1R_FSC12_Pos (12U)
<> 161:2cc1468da177 2851 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 2852 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
<> 161:2cc1468da177 2853 #define CAN_FS1R_FSC13_Pos (13U)
<> 161:2cc1468da177 2854 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 2855 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
<> 144:ef7eb2e8f9f7 2856
<> 144:ef7eb2e8f9f7 2857 /****************** Bit definition for CAN_FFA1R register *******************/
<> 161:2cc1468da177 2858 #define CAN_FFA1R_FFA_Pos (0U)
<> 161:2cc1468da177 2859 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
<> 161:2cc1468da177 2860 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
<> 161:2cc1468da177 2861 #define CAN_FFA1R_FFA0_Pos (0U)
<> 161:2cc1468da177 2862 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2863 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
<> 161:2cc1468da177 2864 #define CAN_FFA1R_FFA1_Pos (1U)
<> 161:2cc1468da177 2865 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2866 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
<> 161:2cc1468da177 2867 #define CAN_FFA1R_FFA2_Pos (2U)
<> 161:2cc1468da177 2868 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2869 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
<> 161:2cc1468da177 2870 #define CAN_FFA1R_FFA3_Pos (3U)
<> 161:2cc1468da177 2871 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2872 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
<> 161:2cc1468da177 2873 #define CAN_FFA1R_FFA4_Pos (4U)
<> 161:2cc1468da177 2874 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2875 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
<> 161:2cc1468da177 2876 #define CAN_FFA1R_FFA5_Pos (5U)
<> 161:2cc1468da177 2877 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2878 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
<> 161:2cc1468da177 2879 #define CAN_FFA1R_FFA6_Pos (6U)
<> 161:2cc1468da177 2880 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 2881 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
<> 161:2cc1468da177 2882 #define CAN_FFA1R_FFA7_Pos (7U)
<> 161:2cc1468da177 2883 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 2884 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
<> 161:2cc1468da177 2885 #define CAN_FFA1R_FFA8_Pos (8U)
<> 161:2cc1468da177 2886 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2887 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
<> 161:2cc1468da177 2888 #define CAN_FFA1R_FFA9_Pos (9U)
<> 161:2cc1468da177 2889 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2890 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
<> 161:2cc1468da177 2891 #define CAN_FFA1R_FFA10_Pos (10U)
<> 161:2cc1468da177 2892 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2893 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
<> 161:2cc1468da177 2894 #define CAN_FFA1R_FFA11_Pos (11U)
<> 161:2cc1468da177 2895 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2896 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
<> 161:2cc1468da177 2897 #define CAN_FFA1R_FFA12_Pos (12U)
<> 161:2cc1468da177 2898 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 2899 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
<> 161:2cc1468da177 2900 #define CAN_FFA1R_FFA13_Pos (13U)
<> 161:2cc1468da177 2901 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 2902 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
<> 144:ef7eb2e8f9f7 2903
<> 144:ef7eb2e8f9f7 2904 /******************* Bit definition for CAN_FA1R register *******************/
<> 161:2cc1468da177 2905 #define CAN_FA1R_FACT_Pos (0U)
<> 161:2cc1468da177 2906 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
<> 161:2cc1468da177 2907 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
<> 161:2cc1468da177 2908 #define CAN_FA1R_FACT0_Pos (0U)
<> 161:2cc1468da177 2909 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2910 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
<> 161:2cc1468da177 2911 #define CAN_FA1R_FACT1_Pos (1U)
<> 161:2cc1468da177 2912 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2913 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
<> 161:2cc1468da177 2914 #define CAN_FA1R_FACT2_Pos (2U)
<> 161:2cc1468da177 2915 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2916 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
<> 161:2cc1468da177 2917 #define CAN_FA1R_FACT3_Pos (3U)
<> 161:2cc1468da177 2918 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2919 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
<> 161:2cc1468da177 2920 #define CAN_FA1R_FACT4_Pos (4U)
<> 161:2cc1468da177 2921 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2922 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
<> 161:2cc1468da177 2923 #define CAN_FA1R_FACT5_Pos (5U)
<> 161:2cc1468da177 2924 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2925 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
<> 161:2cc1468da177 2926 #define CAN_FA1R_FACT6_Pos (6U)
<> 161:2cc1468da177 2927 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 2928 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
<> 161:2cc1468da177 2929 #define CAN_FA1R_FACT7_Pos (7U)
<> 161:2cc1468da177 2930 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 2931 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
<> 161:2cc1468da177 2932 #define CAN_FA1R_FACT8_Pos (8U)
<> 161:2cc1468da177 2933 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2934 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
<> 161:2cc1468da177 2935 #define CAN_FA1R_FACT9_Pos (9U)
<> 161:2cc1468da177 2936 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2937 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
<> 161:2cc1468da177 2938 #define CAN_FA1R_FACT10_Pos (10U)
<> 161:2cc1468da177 2939 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2940 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
<> 161:2cc1468da177 2941 #define CAN_FA1R_FACT11_Pos (11U)
<> 161:2cc1468da177 2942 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2943 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
<> 161:2cc1468da177 2944 #define CAN_FA1R_FACT12_Pos (12U)
<> 161:2cc1468da177 2945 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 2946 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
<> 161:2cc1468da177 2947 #define CAN_FA1R_FACT13_Pos (13U)
<> 161:2cc1468da177 2948 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 2949 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
<> 144:ef7eb2e8f9f7 2950
<> 144:ef7eb2e8f9f7 2951 /******************* Bit definition for CAN_F0R1 register *******************/
<> 161:2cc1468da177 2952 #define CAN_F0R1_FB0_Pos (0U)
<> 161:2cc1468da177 2953 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 2954 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 2955 #define CAN_F0R1_FB1_Pos (1U)
<> 161:2cc1468da177 2956 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 2957 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 2958 #define CAN_F0R1_FB2_Pos (2U)
<> 161:2cc1468da177 2959 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 2960 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 2961 #define CAN_F0R1_FB3_Pos (3U)
<> 161:2cc1468da177 2962 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 2963 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 2964 #define CAN_F0R1_FB4_Pos (4U)
<> 161:2cc1468da177 2965 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 2966 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 2967 #define CAN_F0R1_FB5_Pos (5U)
<> 161:2cc1468da177 2968 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 2969 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 2970 #define CAN_F0R1_FB6_Pos (6U)
<> 161:2cc1468da177 2971 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 2972 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 2973 #define CAN_F0R1_FB7_Pos (7U)
<> 161:2cc1468da177 2974 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 2975 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 2976 #define CAN_F0R1_FB8_Pos (8U)
<> 161:2cc1468da177 2977 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 2978 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 2979 #define CAN_F0R1_FB9_Pos (9U)
<> 161:2cc1468da177 2980 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 2981 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 2982 #define CAN_F0R1_FB10_Pos (10U)
<> 161:2cc1468da177 2983 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 2984 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 2985 #define CAN_F0R1_FB11_Pos (11U)
<> 161:2cc1468da177 2986 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 2987 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 2988 #define CAN_F0R1_FB12_Pos (12U)
<> 161:2cc1468da177 2989 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 2990 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 2991 #define CAN_F0R1_FB13_Pos (13U)
<> 161:2cc1468da177 2992 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 2993 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 2994 #define CAN_F0R1_FB14_Pos (14U)
<> 161:2cc1468da177 2995 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 2996 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 2997 #define CAN_F0R1_FB15_Pos (15U)
<> 161:2cc1468da177 2998 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 2999 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3000 #define CAN_F0R1_FB16_Pos (16U)
<> 161:2cc1468da177 3001 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3002 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3003 #define CAN_F0R1_FB17_Pos (17U)
<> 161:2cc1468da177 3004 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3005 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3006 #define CAN_F0R1_FB18_Pos (18U)
<> 161:2cc1468da177 3007 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3008 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3009 #define CAN_F0R1_FB19_Pos (19U)
<> 161:2cc1468da177 3010 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3011 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3012 #define CAN_F0R1_FB20_Pos (20U)
<> 161:2cc1468da177 3013 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3014 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3015 #define CAN_F0R1_FB21_Pos (21U)
<> 161:2cc1468da177 3016 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3017 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3018 #define CAN_F0R1_FB22_Pos (22U)
<> 161:2cc1468da177 3019 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 3020 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 3021 #define CAN_F0R1_FB23_Pos (23U)
<> 161:2cc1468da177 3022 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 3023 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 3024 #define CAN_F0R1_FB24_Pos (24U)
<> 161:2cc1468da177 3025 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 3026 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 3027 #define CAN_F0R1_FB25_Pos (25U)
<> 161:2cc1468da177 3028 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 3029 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 3030 #define CAN_F0R1_FB26_Pos (26U)
<> 161:2cc1468da177 3031 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 3032 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 3033 #define CAN_F0R1_FB27_Pos (27U)
<> 161:2cc1468da177 3034 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 3035 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 3036 #define CAN_F0R1_FB28_Pos (28U)
<> 161:2cc1468da177 3037 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 3038 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 3039 #define CAN_F0R1_FB29_Pos (29U)
<> 161:2cc1468da177 3040 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 3041 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 3042 #define CAN_F0R1_FB30_Pos (30U)
<> 161:2cc1468da177 3043 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 3044 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 3045 #define CAN_F0R1_FB31_Pos (31U)
<> 161:2cc1468da177 3046 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 3047 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3048
<> 144:ef7eb2e8f9f7 3049 /******************* Bit definition for CAN_F1R1 register *******************/
<> 161:2cc1468da177 3050 #define CAN_F1R1_FB0_Pos (0U)
<> 161:2cc1468da177 3051 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 3052 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 3053 #define CAN_F1R1_FB1_Pos (1U)
<> 161:2cc1468da177 3054 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 3055 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 3056 #define CAN_F1R1_FB2_Pos (2U)
<> 161:2cc1468da177 3057 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 3058 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 3059 #define CAN_F1R1_FB3_Pos (3U)
<> 161:2cc1468da177 3060 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 3061 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 3062 #define CAN_F1R1_FB4_Pos (4U)
<> 161:2cc1468da177 3063 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 3064 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 3065 #define CAN_F1R1_FB5_Pos (5U)
<> 161:2cc1468da177 3066 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 3067 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 3068 #define CAN_F1R1_FB6_Pos (6U)
<> 161:2cc1468da177 3069 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 3070 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 3071 #define CAN_F1R1_FB7_Pos (7U)
<> 161:2cc1468da177 3072 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 3073 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 3074 #define CAN_F1R1_FB8_Pos (8U)
<> 161:2cc1468da177 3075 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 3076 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 3077 #define CAN_F1R1_FB9_Pos (9U)
<> 161:2cc1468da177 3078 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 3079 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 3080 #define CAN_F1R1_FB10_Pos (10U)
<> 161:2cc1468da177 3081 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 3082 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 3083 #define CAN_F1R1_FB11_Pos (11U)
<> 161:2cc1468da177 3084 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 3085 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 3086 #define CAN_F1R1_FB12_Pos (12U)
<> 161:2cc1468da177 3087 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 3088 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 3089 #define CAN_F1R1_FB13_Pos (13U)
<> 161:2cc1468da177 3090 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 3091 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 3092 #define CAN_F1R1_FB14_Pos (14U)
<> 161:2cc1468da177 3093 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 3094 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 3095 #define CAN_F1R1_FB15_Pos (15U)
<> 161:2cc1468da177 3096 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 3097 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3098 #define CAN_F1R1_FB16_Pos (16U)
<> 161:2cc1468da177 3099 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3100 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3101 #define CAN_F1R1_FB17_Pos (17U)
<> 161:2cc1468da177 3102 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3103 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3104 #define CAN_F1R1_FB18_Pos (18U)
<> 161:2cc1468da177 3105 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3106 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3107 #define CAN_F1R1_FB19_Pos (19U)
<> 161:2cc1468da177 3108 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3109 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3110 #define CAN_F1R1_FB20_Pos (20U)
<> 161:2cc1468da177 3111 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3112 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3113 #define CAN_F1R1_FB21_Pos (21U)
<> 161:2cc1468da177 3114 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3115 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3116 #define CAN_F1R1_FB22_Pos (22U)
<> 161:2cc1468da177 3117 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 3118 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 3119 #define CAN_F1R1_FB23_Pos (23U)
<> 161:2cc1468da177 3120 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 3121 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 3122 #define CAN_F1R1_FB24_Pos (24U)
<> 161:2cc1468da177 3123 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 3124 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 3125 #define CAN_F1R1_FB25_Pos (25U)
<> 161:2cc1468da177 3126 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 3127 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 3128 #define CAN_F1R1_FB26_Pos (26U)
<> 161:2cc1468da177 3129 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 3130 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 3131 #define CAN_F1R1_FB27_Pos (27U)
<> 161:2cc1468da177 3132 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 3133 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 3134 #define CAN_F1R1_FB28_Pos (28U)
<> 161:2cc1468da177 3135 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 3136 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 3137 #define CAN_F1R1_FB29_Pos (29U)
<> 161:2cc1468da177 3138 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 3139 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 3140 #define CAN_F1R1_FB30_Pos (30U)
<> 161:2cc1468da177 3141 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 3142 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 3143 #define CAN_F1R1_FB31_Pos (31U)
<> 161:2cc1468da177 3144 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 3145 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3146
<> 144:ef7eb2e8f9f7 3147 /******************* Bit definition for CAN_F2R1 register *******************/
<> 161:2cc1468da177 3148 #define CAN_F2R1_FB0_Pos (0U)
<> 161:2cc1468da177 3149 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 3150 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 3151 #define CAN_F2R1_FB1_Pos (1U)
<> 161:2cc1468da177 3152 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 3153 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 3154 #define CAN_F2R1_FB2_Pos (2U)
<> 161:2cc1468da177 3155 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 3156 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 3157 #define CAN_F2R1_FB3_Pos (3U)
<> 161:2cc1468da177 3158 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 3159 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 3160 #define CAN_F2R1_FB4_Pos (4U)
<> 161:2cc1468da177 3161 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 3162 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 3163 #define CAN_F2R1_FB5_Pos (5U)
<> 161:2cc1468da177 3164 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 3165 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 3166 #define CAN_F2R1_FB6_Pos (6U)
<> 161:2cc1468da177 3167 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 3168 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 3169 #define CAN_F2R1_FB7_Pos (7U)
<> 161:2cc1468da177 3170 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 3171 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 3172 #define CAN_F2R1_FB8_Pos (8U)
<> 161:2cc1468da177 3173 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 3174 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 3175 #define CAN_F2R1_FB9_Pos (9U)
<> 161:2cc1468da177 3176 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 3177 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 3178 #define CAN_F2R1_FB10_Pos (10U)
<> 161:2cc1468da177 3179 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 3180 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 3181 #define CAN_F2R1_FB11_Pos (11U)
<> 161:2cc1468da177 3182 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 3183 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 3184 #define CAN_F2R1_FB12_Pos (12U)
<> 161:2cc1468da177 3185 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 3186 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 3187 #define CAN_F2R1_FB13_Pos (13U)
<> 161:2cc1468da177 3188 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 3189 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 3190 #define CAN_F2R1_FB14_Pos (14U)
<> 161:2cc1468da177 3191 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 3192 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 3193 #define CAN_F2R1_FB15_Pos (15U)
<> 161:2cc1468da177 3194 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 3195 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3196 #define CAN_F2R1_FB16_Pos (16U)
<> 161:2cc1468da177 3197 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3198 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3199 #define CAN_F2R1_FB17_Pos (17U)
<> 161:2cc1468da177 3200 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3201 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3202 #define CAN_F2R1_FB18_Pos (18U)
<> 161:2cc1468da177 3203 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3204 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3205 #define CAN_F2R1_FB19_Pos (19U)
<> 161:2cc1468da177 3206 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3207 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3208 #define CAN_F2R1_FB20_Pos (20U)
<> 161:2cc1468da177 3209 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3210 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3211 #define CAN_F2R1_FB21_Pos (21U)
<> 161:2cc1468da177 3212 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3213 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3214 #define CAN_F2R1_FB22_Pos (22U)
<> 161:2cc1468da177 3215 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 3216 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 3217 #define CAN_F2R1_FB23_Pos (23U)
<> 161:2cc1468da177 3218 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 3219 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 3220 #define CAN_F2R1_FB24_Pos (24U)
<> 161:2cc1468da177 3221 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 3222 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 3223 #define CAN_F2R1_FB25_Pos (25U)
<> 161:2cc1468da177 3224 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 3225 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 3226 #define CAN_F2R1_FB26_Pos (26U)
<> 161:2cc1468da177 3227 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 3228 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 3229 #define CAN_F2R1_FB27_Pos (27U)
<> 161:2cc1468da177 3230 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 3231 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 3232 #define CAN_F2R1_FB28_Pos (28U)
<> 161:2cc1468da177 3233 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 3234 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 3235 #define CAN_F2R1_FB29_Pos (29U)
<> 161:2cc1468da177 3236 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 3237 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 3238 #define CAN_F2R1_FB30_Pos (30U)
<> 161:2cc1468da177 3239 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 3240 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 3241 #define CAN_F2R1_FB31_Pos (31U)
<> 161:2cc1468da177 3242 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 3243 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3244
<> 144:ef7eb2e8f9f7 3245 /******************* Bit definition for CAN_F3R1 register *******************/
<> 161:2cc1468da177 3246 #define CAN_F3R1_FB0_Pos (0U)
<> 161:2cc1468da177 3247 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 3248 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 3249 #define CAN_F3R1_FB1_Pos (1U)
<> 161:2cc1468da177 3250 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 3251 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 3252 #define CAN_F3R1_FB2_Pos (2U)
<> 161:2cc1468da177 3253 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 3254 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 3255 #define CAN_F3R1_FB3_Pos (3U)
<> 161:2cc1468da177 3256 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 3257 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 3258 #define CAN_F3R1_FB4_Pos (4U)
<> 161:2cc1468da177 3259 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 3260 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 3261 #define CAN_F3R1_FB5_Pos (5U)
<> 161:2cc1468da177 3262 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 3263 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 3264 #define CAN_F3R1_FB6_Pos (6U)
<> 161:2cc1468da177 3265 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 3266 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 3267 #define CAN_F3R1_FB7_Pos (7U)
<> 161:2cc1468da177 3268 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 3269 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 3270 #define CAN_F3R1_FB8_Pos (8U)
<> 161:2cc1468da177 3271 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 3272 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 3273 #define CAN_F3R1_FB9_Pos (9U)
<> 161:2cc1468da177 3274 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 3275 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 3276 #define CAN_F3R1_FB10_Pos (10U)
<> 161:2cc1468da177 3277 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 3278 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 3279 #define CAN_F3R1_FB11_Pos (11U)
<> 161:2cc1468da177 3280 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 3281 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 3282 #define CAN_F3R1_FB12_Pos (12U)
<> 161:2cc1468da177 3283 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 3284 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 3285 #define CAN_F3R1_FB13_Pos (13U)
<> 161:2cc1468da177 3286 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 3287 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 3288 #define CAN_F3R1_FB14_Pos (14U)
<> 161:2cc1468da177 3289 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 3290 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 3291 #define CAN_F3R1_FB15_Pos (15U)
<> 161:2cc1468da177 3292 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 3293 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3294 #define CAN_F3R1_FB16_Pos (16U)
<> 161:2cc1468da177 3295 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3296 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3297 #define CAN_F3R1_FB17_Pos (17U)
<> 161:2cc1468da177 3298 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3299 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3300 #define CAN_F3R1_FB18_Pos (18U)
<> 161:2cc1468da177 3301 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3302 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3303 #define CAN_F3R1_FB19_Pos (19U)
<> 161:2cc1468da177 3304 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3305 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3306 #define CAN_F3R1_FB20_Pos (20U)
<> 161:2cc1468da177 3307 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3308 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3309 #define CAN_F3R1_FB21_Pos (21U)
<> 161:2cc1468da177 3310 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3311 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3312 #define CAN_F3R1_FB22_Pos (22U)
<> 161:2cc1468da177 3313 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 3314 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 3315 #define CAN_F3R1_FB23_Pos (23U)
<> 161:2cc1468da177 3316 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 3317 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 3318 #define CAN_F3R1_FB24_Pos (24U)
<> 161:2cc1468da177 3319 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 3320 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 3321 #define CAN_F3R1_FB25_Pos (25U)
<> 161:2cc1468da177 3322 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 3323 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 3324 #define CAN_F3R1_FB26_Pos (26U)
<> 161:2cc1468da177 3325 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 3326 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 3327 #define CAN_F3R1_FB27_Pos (27U)
<> 161:2cc1468da177 3328 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 3329 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 3330 #define CAN_F3R1_FB28_Pos (28U)
<> 161:2cc1468da177 3331 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 3332 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 3333 #define CAN_F3R1_FB29_Pos (29U)
<> 161:2cc1468da177 3334 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 3335 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 3336 #define CAN_F3R1_FB30_Pos (30U)
<> 161:2cc1468da177 3337 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 3338 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 3339 #define CAN_F3R1_FB31_Pos (31U)
<> 161:2cc1468da177 3340 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 3341 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3342
<> 144:ef7eb2e8f9f7 3343 /******************* Bit definition for CAN_F4R1 register *******************/
<> 161:2cc1468da177 3344 #define CAN_F4R1_FB0_Pos (0U)
<> 161:2cc1468da177 3345 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 3346 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 3347 #define CAN_F4R1_FB1_Pos (1U)
<> 161:2cc1468da177 3348 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 3349 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 3350 #define CAN_F4R1_FB2_Pos (2U)
<> 161:2cc1468da177 3351 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 3352 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 3353 #define CAN_F4R1_FB3_Pos (3U)
<> 161:2cc1468da177 3354 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 3355 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 3356 #define CAN_F4R1_FB4_Pos (4U)
<> 161:2cc1468da177 3357 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 3358 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 3359 #define CAN_F4R1_FB5_Pos (5U)
<> 161:2cc1468da177 3360 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 3361 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 3362 #define CAN_F4R1_FB6_Pos (6U)
<> 161:2cc1468da177 3363 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 3364 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 3365 #define CAN_F4R1_FB7_Pos (7U)
<> 161:2cc1468da177 3366 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 3367 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 3368 #define CAN_F4R1_FB8_Pos (8U)
<> 161:2cc1468da177 3369 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 3370 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 3371 #define CAN_F4R1_FB9_Pos (9U)
<> 161:2cc1468da177 3372 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 3373 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 3374 #define CAN_F4R1_FB10_Pos (10U)
<> 161:2cc1468da177 3375 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 3376 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 3377 #define CAN_F4R1_FB11_Pos (11U)
<> 161:2cc1468da177 3378 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 3379 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 3380 #define CAN_F4R1_FB12_Pos (12U)
<> 161:2cc1468da177 3381 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 3382 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 3383 #define CAN_F4R1_FB13_Pos (13U)
<> 161:2cc1468da177 3384 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 3385 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 3386 #define CAN_F4R1_FB14_Pos (14U)
<> 161:2cc1468da177 3387 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 3388 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 3389 #define CAN_F4R1_FB15_Pos (15U)
<> 161:2cc1468da177 3390 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 3391 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3392 #define CAN_F4R1_FB16_Pos (16U)
<> 161:2cc1468da177 3393 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3394 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3395 #define CAN_F4R1_FB17_Pos (17U)
<> 161:2cc1468da177 3396 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3397 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3398 #define CAN_F4R1_FB18_Pos (18U)
<> 161:2cc1468da177 3399 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3400 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3401 #define CAN_F4R1_FB19_Pos (19U)
<> 161:2cc1468da177 3402 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3403 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3404 #define CAN_F4R1_FB20_Pos (20U)
<> 161:2cc1468da177 3405 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3406 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3407 #define CAN_F4R1_FB21_Pos (21U)
<> 161:2cc1468da177 3408 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3409 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3410 #define CAN_F4R1_FB22_Pos (22U)
<> 161:2cc1468da177 3411 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 3412 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 3413 #define CAN_F4R1_FB23_Pos (23U)
<> 161:2cc1468da177 3414 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 3415 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 3416 #define CAN_F4R1_FB24_Pos (24U)
<> 161:2cc1468da177 3417 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 3418 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 3419 #define CAN_F4R1_FB25_Pos (25U)
<> 161:2cc1468da177 3420 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 3421 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 3422 #define CAN_F4R1_FB26_Pos (26U)
<> 161:2cc1468da177 3423 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 3424 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 3425 #define CAN_F4R1_FB27_Pos (27U)
<> 161:2cc1468da177 3426 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 3427 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 3428 #define CAN_F4R1_FB28_Pos (28U)
<> 161:2cc1468da177 3429 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 3430 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 3431 #define CAN_F4R1_FB29_Pos (29U)
<> 161:2cc1468da177 3432 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 3433 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 3434 #define CAN_F4R1_FB30_Pos (30U)
<> 161:2cc1468da177 3435 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 3436 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 3437 #define CAN_F4R1_FB31_Pos (31U)
<> 161:2cc1468da177 3438 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 3439 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3440
<> 144:ef7eb2e8f9f7 3441 /******************* Bit definition for CAN_F5R1 register *******************/
<> 161:2cc1468da177 3442 #define CAN_F5R1_FB0_Pos (0U)
<> 161:2cc1468da177 3443 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 3444 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 3445 #define CAN_F5R1_FB1_Pos (1U)
<> 161:2cc1468da177 3446 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 3447 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 3448 #define CAN_F5R1_FB2_Pos (2U)
<> 161:2cc1468da177 3449 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 3450 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 3451 #define CAN_F5R1_FB3_Pos (3U)
<> 161:2cc1468da177 3452 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 3453 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 3454 #define CAN_F5R1_FB4_Pos (4U)
<> 161:2cc1468da177 3455 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 3456 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 3457 #define CAN_F5R1_FB5_Pos (5U)
<> 161:2cc1468da177 3458 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 3459 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 3460 #define CAN_F5R1_FB6_Pos (6U)
<> 161:2cc1468da177 3461 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 3462 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 3463 #define CAN_F5R1_FB7_Pos (7U)
<> 161:2cc1468da177 3464 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 3465 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 3466 #define CAN_F5R1_FB8_Pos (8U)
<> 161:2cc1468da177 3467 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 3468 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 3469 #define CAN_F5R1_FB9_Pos (9U)
<> 161:2cc1468da177 3470 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 3471 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 3472 #define CAN_F5R1_FB10_Pos (10U)
<> 161:2cc1468da177 3473 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 3474 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 3475 #define CAN_F5R1_FB11_Pos (11U)
<> 161:2cc1468da177 3476 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 3477 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 3478 #define CAN_F5R1_FB12_Pos (12U)
<> 161:2cc1468da177 3479 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 3480 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 3481 #define CAN_F5R1_FB13_Pos (13U)
<> 161:2cc1468da177 3482 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 3483 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 3484 #define CAN_F5R1_FB14_Pos (14U)
<> 161:2cc1468da177 3485 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 3486 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 3487 #define CAN_F5R1_FB15_Pos (15U)
<> 161:2cc1468da177 3488 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 3489 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3490 #define CAN_F5R1_FB16_Pos (16U)
<> 161:2cc1468da177 3491 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3492 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3493 #define CAN_F5R1_FB17_Pos (17U)
<> 161:2cc1468da177 3494 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3495 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3496 #define CAN_F5R1_FB18_Pos (18U)
<> 161:2cc1468da177 3497 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3498 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3499 #define CAN_F5R1_FB19_Pos (19U)
<> 161:2cc1468da177 3500 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3501 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3502 #define CAN_F5R1_FB20_Pos (20U)
<> 161:2cc1468da177 3503 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3504 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3505 #define CAN_F5R1_FB21_Pos (21U)
<> 161:2cc1468da177 3506 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3507 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3508 #define CAN_F5R1_FB22_Pos (22U)
<> 161:2cc1468da177 3509 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 3510 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 3511 #define CAN_F5R1_FB23_Pos (23U)
<> 161:2cc1468da177 3512 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 3513 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 3514 #define CAN_F5R1_FB24_Pos (24U)
<> 161:2cc1468da177 3515 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 3516 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 3517 #define CAN_F5R1_FB25_Pos (25U)
<> 161:2cc1468da177 3518 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 3519 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 3520 #define CAN_F5R1_FB26_Pos (26U)
<> 161:2cc1468da177 3521 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 3522 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 3523 #define CAN_F5R1_FB27_Pos (27U)
<> 161:2cc1468da177 3524 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 3525 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 3526 #define CAN_F5R1_FB28_Pos (28U)
<> 161:2cc1468da177 3527 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 3528 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 3529 #define CAN_F5R1_FB29_Pos (29U)
<> 161:2cc1468da177 3530 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 3531 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 3532 #define CAN_F5R1_FB30_Pos (30U)
<> 161:2cc1468da177 3533 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 3534 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 3535 #define CAN_F5R1_FB31_Pos (31U)
<> 161:2cc1468da177 3536 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 3537 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3538
<> 144:ef7eb2e8f9f7 3539 /******************* Bit definition for CAN_F6R1 register *******************/
<> 161:2cc1468da177 3540 #define CAN_F6R1_FB0_Pos (0U)
<> 161:2cc1468da177 3541 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 3542 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 3543 #define CAN_F6R1_FB1_Pos (1U)
<> 161:2cc1468da177 3544 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 3545 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 3546 #define CAN_F6R1_FB2_Pos (2U)
<> 161:2cc1468da177 3547 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 3548 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 3549 #define CAN_F6R1_FB3_Pos (3U)
<> 161:2cc1468da177 3550 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 3551 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 3552 #define CAN_F6R1_FB4_Pos (4U)
<> 161:2cc1468da177 3553 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 3554 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 3555 #define CAN_F6R1_FB5_Pos (5U)
<> 161:2cc1468da177 3556 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 3557 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 3558 #define CAN_F6R1_FB6_Pos (6U)
<> 161:2cc1468da177 3559 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 3560 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 3561 #define CAN_F6R1_FB7_Pos (7U)
<> 161:2cc1468da177 3562 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 3563 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 3564 #define CAN_F6R1_FB8_Pos (8U)
<> 161:2cc1468da177 3565 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 3566 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 3567 #define CAN_F6R1_FB9_Pos (9U)
<> 161:2cc1468da177 3568 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 3569 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 3570 #define CAN_F6R1_FB10_Pos (10U)
<> 161:2cc1468da177 3571 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 3572 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 3573 #define CAN_F6R1_FB11_Pos (11U)
<> 161:2cc1468da177 3574 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 3575 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 3576 #define CAN_F6R1_FB12_Pos (12U)
<> 161:2cc1468da177 3577 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 3578 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 3579 #define CAN_F6R1_FB13_Pos (13U)
<> 161:2cc1468da177 3580 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 3581 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 3582 #define CAN_F6R1_FB14_Pos (14U)
<> 161:2cc1468da177 3583 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 3584 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 3585 #define CAN_F6R1_FB15_Pos (15U)
<> 161:2cc1468da177 3586 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 3587 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3588 #define CAN_F6R1_FB16_Pos (16U)
<> 161:2cc1468da177 3589 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3590 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3591 #define CAN_F6R1_FB17_Pos (17U)
<> 161:2cc1468da177 3592 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3593 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3594 #define CAN_F6R1_FB18_Pos (18U)
<> 161:2cc1468da177 3595 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3596 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3597 #define CAN_F6R1_FB19_Pos (19U)
<> 161:2cc1468da177 3598 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3599 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3600 #define CAN_F6R1_FB20_Pos (20U)
<> 161:2cc1468da177 3601 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3602 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3603 #define CAN_F6R1_FB21_Pos (21U)
<> 161:2cc1468da177 3604 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3605 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3606 #define CAN_F6R1_FB22_Pos (22U)
<> 161:2cc1468da177 3607 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 3608 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 3609 #define CAN_F6R1_FB23_Pos (23U)
<> 161:2cc1468da177 3610 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 3611 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 3612 #define CAN_F6R1_FB24_Pos (24U)
<> 161:2cc1468da177 3613 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 3614 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 3615 #define CAN_F6R1_FB25_Pos (25U)
<> 161:2cc1468da177 3616 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 3617 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 3618 #define CAN_F6R1_FB26_Pos (26U)
<> 161:2cc1468da177 3619 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 3620 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 3621 #define CAN_F6R1_FB27_Pos (27U)
<> 161:2cc1468da177 3622 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 3623 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 3624 #define CAN_F6R1_FB28_Pos (28U)
<> 161:2cc1468da177 3625 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 3626 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 3627 #define CAN_F6R1_FB29_Pos (29U)
<> 161:2cc1468da177 3628 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 3629 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 3630 #define CAN_F6R1_FB30_Pos (30U)
<> 161:2cc1468da177 3631 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 3632 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 3633 #define CAN_F6R1_FB31_Pos (31U)
<> 161:2cc1468da177 3634 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 3635 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3636
<> 144:ef7eb2e8f9f7 3637 /******************* Bit definition for CAN_F7R1 register *******************/
<> 161:2cc1468da177 3638 #define CAN_F7R1_FB0_Pos (0U)
<> 161:2cc1468da177 3639 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 3640 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 3641 #define CAN_F7R1_FB1_Pos (1U)
<> 161:2cc1468da177 3642 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 3643 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 3644 #define CAN_F7R1_FB2_Pos (2U)
<> 161:2cc1468da177 3645 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 3646 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 3647 #define CAN_F7R1_FB3_Pos (3U)
<> 161:2cc1468da177 3648 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 3649 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 3650 #define CAN_F7R1_FB4_Pos (4U)
<> 161:2cc1468da177 3651 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 3652 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 3653 #define CAN_F7R1_FB5_Pos (5U)
<> 161:2cc1468da177 3654 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 3655 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 3656 #define CAN_F7R1_FB6_Pos (6U)
<> 161:2cc1468da177 3657 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 3658 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 3659 #define CAN_F7R1_FB7_Pos (7U)
<> 161:2cc1468da177 3660 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 3661 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 3662 #define CAN_F7R1_FB8_Pos (8U)
<> 161:2cc1468da177 3663 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 3664 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 3665 #define CAN_F7R1_FB9_Pos (9U)
<> 161:2cc1468da177 3666 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 3667 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 3668 #define CAN_F7R1_FB10_Pos (10U)
<> 161:2cc1468da177 3669 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 3670 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 3671 #define CAN_F7R1_FB11_Pos (11U)
<> 161:2cc1468da177 3672 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 3673 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 3674 #define CAN_F7R1_FB12_Pos (12U)
<> 161:2cc1468da177 3675 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 3676 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 3677 #define CAN_F7R1_FB13_Pos (13U)
<> 161:2cc1468da177 3678 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 3679 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 3680 #define CAN_F7R1_FB14_Pos (14U)
<> 161:2cc1468da177 3681 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 3682 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 3683 #define CAN_F7R1_FB15_Pos (15U)
<> 161:2cc1468da177 3684 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 3685 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3686 #define CAN_F7R1_FB16_Pos (16U)
<> 161:2cc1468da177 3687 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3688 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3689 #define CAN_F7R1_FB17_Pos (17U)
<> 161:2cc1468da177 3690 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3691 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3692 #define CAN_F7R1_FB18_Pos (18U)
<> 161:2cc1468da177 3693 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3694 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3695 #define CAN_F7R1_FB19_Pos (19U)
<> 161:2cc1468da177 3696 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3697 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3698 #define CAN_F7R1_FB20_Pos (20U)
<> 161:2cc1468da177 3699 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3700 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3701 #define CAN_F7R1_FB21_Pos (21U)
<> 161:2cc1468da177 3702 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3703 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3704 #define CAN_F7R1_FB22_Pos (22U)
<> 161:2cc1468da177 3705 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 3706 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 3707 #define CAN_F7R1_FB23_Pos (23U)
<> 161:2cc1468da177 3708 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 3709 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 3710 #define CAN_F7R1_FB24_Pos (24U)
<> 161:2cc1468da177 3711 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 3712 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 3713 #define CAN_F7R1_FB25_Pos (25U)
<> 161:2cc1468da177 3714 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 3715 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 3716 #define CAN_F7R1_FB26_Pos (26U)
<> 161:2cc1468da177 3717 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 3718 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 3719 #define CAN_F7R1_FB27_Pos (27U)
<> 161:2cc1468da177 3720 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 3721 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 3722 #define CAN_F7R1_FB28_Pos (28U)
<> 161:2cc1468da177 3723 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 3724 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 3725 #define CAN_F7R1_FB29_Pos (29U)
<> 161:2cc1468da177 3726 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 3727 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 3728 #define CAN_F7R1_FB30_Pos (30U)
<> 161:2cc1468da177 3729 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 3730 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 3731 #define CAN_F7R1_FB31_Pos (31U)
<> 161:2cc1468da177 3732 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 3733 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3734
<> 144:ef7eb2e8f9f7 3735 /******************* Bit definition for CAN_F8R1 register *******************/
<> 161:2cc1468da177 3736 #define CAN_F8R1_FB0_Pos (0U)
<> 161:2cc1468da177 3737 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 3738 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 3739 #define CAN_F8R1_FB1_Pos (1U)
<> 161:2cc1468da177 3740 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 3741 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 3742 #define CAN_F8R1_FB2_Pos (2U)
<> 161:2cc1468da177 3743 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 3744 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 3745 #define CAN_F8R1_FB3_Pos (3U)
<> 161:2cc1468da177 3746 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 3747 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 3748 #define CAN_F8R1_FB4_Pos (4U)
<> 161:2cc1468da177 3749 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 3750 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 3751 #define CAN_F8R1_FB5_Pos (5U)
<> 161:2cc1468da177 3752 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 3753 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 3754 #define CAN_F8R1_FB6_Pos (6U)
<> 161:2cc1468da177 3755 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 3756 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 3757 #define CAN_F8R1_FB7_Pos (7U)
<> 161:2cc1468da177 3758 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 3759 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 3760 #define CAN_F8R1_FB8_Pos (8U)
<> 161:2cc1468da177 3761 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 3762 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 3763 #define CAN_F8R1_FB9_Pos (9U)
<> 161:2cc1468da177 3764 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 3765 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 3766 #define CAN_F8R1_FB10_Pos (10U)
<> 161:2cc1468da177 3767 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 3768 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 3769 #define CAN_F8R1_FB11_Pos (11U)
<> 161:2cc1468da177 3770 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 3771 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 3772 #define CAN_F8R1_FB12_Pos (12U)
<> 161:2cc1468da177 3773 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 3774 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 3775 #define CAN_F8R1_FB13_Pos (13U)
<> 161:2cc1468da177 3776 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 3777 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 3778 #define CAN_F8R1_FB14_Pos (14U)
<> 161:2cc1468da177 3779 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 3780 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 3781 #define CAN_F8R1_FB15_Pos (15U)
<> 161:2cc1468da177 3782 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 3783 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3784 #define CAN_F8R1_FB16_Pos (16U)
<> 161:2cc1468da177 3785 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3786 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3787 #define CAN_F8R1_FB17_Pos (17U)
<> 161:2cc1468da177 3788 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3789 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3790 #define CAN_F8R1_FB18_Pos (18U)
<> 161:2cc1468da177 3791 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3792 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3793 #define CAN_F8R1_FB19_Pos (19U)
<> 161:2cc1468da177 3794 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3795 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3796 #define CAN_F8R1_FB20_Pos (20U)
<> 161:2cc1468da177 3797 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3798 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3799 #define CAN_F8R1_FB21_Pos (21U)
<> 161:2cc1468da177 3800 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3801 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3802 #define CAN_F8R1_FB22_Pos (22U)
<> 161:2cc1468da177 3803 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 3804 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 3805 #define CAN_F8R1_FB23_Pos (23U)
<> 161:2cc1468da177 3806 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 3807 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 3808 #define CAN_F8R1_FB24_Pos (24U)
<> 161:2cc1468da177 3809 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 3810 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 3811 #define CAN_F8R1_FB25_Pos (25U)
<> 161:2cc1468da177 3812 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 3813 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 3814 #define CAN_F8R1_FB26_Pos (26U)
<> 161:2cc1468da177 3815 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 3816 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 3817 #define CAN_F8R1_FB27_Pos (27U)
<> 161:2cc1468da177 3818 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 3819 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 3820 #define CAN_F8R1_FB28_Pos (28U)
<> 161:2cc1468da177 3821 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 3822 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 3823 #define CAN_F8R1_FB29_Pos (29U)
<> 161:2cc1468da177 3824 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 3825 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 3826 #define CAN_F8R1_FB30_Pos (30U)
<> 161:2cc1468da177 3827 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 3828 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 3829 #define CAN_F8R1_FB31_Pos (31U)
<> 161:2cc1468da177 3830 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 3831 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3832
<> 144:ef7eb2e8f9f7 3833 /******************* Bit definition for CAN_F9R1 register *******************/
<> 161:2cc1468da177 3834 #define CAN_F9R1_FB0_Pos (0U)
<> 161:2cc1468da177 3835 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 3836 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 3837 #define CAN_F9R1_FB1_Pos (1U)
<> 161:2cc1468da177 3838 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 3839 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 3840 #define CAN_F9R1_FB2_Pos (2U)
<> 161:2cc1468da177 3841 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 3842 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 3843 #define CAN_F9R1_FB3_Pos (3U)
<> 161:2cc1468da177 3844 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 3845 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 3846 #define CAN_F9R1_FB4_Pos (4U)
<> 161:2cc1468da177 3847 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 3848 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 3849 #define CAN_F9R1_FB5_Pos (5U)
<> 161:2cc1468da177 3850 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 3851 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 3852 #define CAN_F9R1_FB6_Pos (6U)
<> 161:2cc1468da177 3853 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 3854 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 3855 #define CAN_F9R1_FB7_Pos (7U)
<> 161:2cc1468da177 3856 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 3857 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 3858 #define CAN_F9R1_FB8_Pos (8U)
<> 161:2cc1468da177 3859 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 3860 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 3861 #define CAN_F9R1_FB9_Pos (9U)
<> 161:2cc1468da177 3862 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 3863 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 3864 #define CAN_F9R1_FB10_Pos (10U)
<> 161:2cc1468da177 3865 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 3866 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 3867 #define CAN_F9R1_FB11_Pos (11U)
<> 161:2cc1468da177 3868 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 3869 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 3870 #define CAN_F9R1_FB12_Pos (12U)
<> 161:2cc1468da177 3871 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 3872 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 3873 #define CAN_F9R1_FB13_Pos (13U)
<> 161:2cc1468da177 3874 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 3875 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 3876 #define CAN_F9R1_FB14_Pos (14U)
<> 161:2cc1468da177 3877 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 3878 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 3879 #define CAN_F9R1_FB15_Pos (15U)
<> 161:2cc1468da177 3880 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 3881 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3882 #define CAN_F9R1_FB16_Pos (16U)
<> 161:2cc1468da177 3883 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3884 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3885 #define CAN_F9R1_FB17_Pos (17U)
<> 161:2cc1468da177 3886 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3887 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3888 #define CAN_F9R1_FB18_Pos (18U)
<> 161:2cc1468da177 3889 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3890 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3891 #define CAN_F9R1_FB19_Pos (19U)
<> 161:2cc1468da177 3892 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3893 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3894 #define CAN_F9R1_FB20_Pos (20U)
<> 161:2cc1468da177 3895 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3896 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3897 #define CAN_F9R1_FB21_Pos (21U)
<> 161:2cc1468da177 3898 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3899 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3900 #define CAN_F9R1_FB22_Pos (22U)
<> 161:2cc1468da177 3901 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 3902 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 3903 #define CAN_F9R1_FB23_Pos (23U)
<> 161:2cc1468da177 3904 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 3905 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 3906 #define CAN_F9R1_FB24_Pos (24U)
<> 161:2cc1468da177 3907 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 3908 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 3909 #define CAN_F9R1_FB25_Pos (25U)
<> 161:2cc1468da177 3910 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 3911 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 3912 #define CAN_F9R1_FB26_Pos (26U)
<> 161:2cc1468da177 3913 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 3914 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 3915 #define CAN_F9R1_FB27_Pos (27U)
<> 161:2cc1468da177 3916 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 3917 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 3918 #define CAN_F9R1_FB28_Pos (28U)
<> 161:2cc1468da177 3919 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 3920 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 3921 #define CAN_F9R1_FB29_Pos (29U)
<> 161:2cc1468da177 3922 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 3923 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 3924 #define CAN_F9R1_FB30_Pos (30U)
<> 161:2cc1468da177 3925 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 3926 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 3927 #define CAN_F9R1_FB31_Pos (31U)
<> 161:2cc1468da177 3928 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 3929 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3930
<> 144:ef7eb2e8f9f7 3931 /******************* Bit definition for CAN_F10R1 register ******************/
<> 161:2cc1468da177 3932 #define CAN_F10R1_FB0_Pos (0U)
<> 161:2cc1468da177 3933 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 3934 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 3935 #define CAN_F10R1_FB1_Pos (1U)
<> 161:2cc1468da177 3936 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 3937 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 3938 #define CAN_F10R1_FB2_Pos (2U)
<> 161:2cc1468da177 3939 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 3940 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 3941 #define CAN_F10R1_FB3_Pos (3U)
<> 161:2cc1468da177 3942 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 3943 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 3944 #define CAN_F10R1_FB4_Pos (4U)
<> 161:2cc1468da177 3945 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 3946 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 3947 #define CAN_F10R1_FB5_Pos (5U)
<> 161:2cc1468da177 3948 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 3949 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 3950 #define CAN_F10R1_FB6_Pos (6U)
<> 161:2cc1468da177 3951 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 3952 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 3953 #define CAN_F10R1_FB7_Pos (7U)
<> 161:2cc1468da177 3954 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 3955 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 3956 #define CAN_F10R1_FB8_Pos (8U)
<> 161:2cc1468da177 3957 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 3958 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 3959 #define CAN_F10R1_FB9_Pos (9U)
<> 161:2cc1468da177 3960 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 3961 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 3962 #define CAN_F10R1_FB10_Pos (10U)
<> 161:2cc1468da177 3963 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 3964 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 3965 #define CAN_F10R1_FB11_Pos (11U)
<> 161:2cc1468da177 3966 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 3967 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 3968 #define CAN_F10R1_FB12_Pos (12U)
<> 161:2cc1468da177 3969 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 3970 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 3971 #define CAN_F10R1_FB13_Pos (13U)
<> 161:2cc1468da177 3972 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 3973 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 3974 #define CAN_F10R1_FB14_Pos (14U)
<> 161:2cc1468da177 3975 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 3976 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 3977 #define CAN_F10R1_FB15_Pos (15U)
<> 161:2cc1468da177 3978 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 3979 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 3980 #define CAN_F10R1_FB16_Pos (16U)
<> 161:2cc1468da177 3981 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 3982 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 3983 #define CAN_F10R1_FB17_Pos (17U)
<> 161:2cc1468da177 3984 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 3985 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 3986 #define CAN_F10R1_FB18_Pos (18U)
<> 161:2cc1468da177 3987 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 3988 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 3989 #define CAN_F10R1_FB19_Pos (19U)
<> 161:2cc1468da177 3990 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 3991 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 3992 #define CAN_F10R1_FB20_Pos (20U)
<> 161:2cc1468da177 3993 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 3994 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 3995 #define CAN_F10R1_FB21_Pos (21U)
<> 161:2cc1468da177 3996 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 3997 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 3998 #define CAN_F10R1_FB22_Pos (22U)
<> 161:2cc1468da177 3999 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4000 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4001 #define CAN_F10R1_FB23_Pos (23U)
<> 161:2cc1468da177 4002 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4003 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4004 #define CAN_F10R1_FB24_Pos (24U)
<> 161:2cc1468da177 4005 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4006 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4007 #define CAN_F10R1_FB25_Pos (25U)
<> 161:2cc1468da177 4008 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4009 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4010 #define CAN_F10R1_FB26_Pos (26U)
<> 161:2cc1468da177 4011 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4012 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4013 #define CAN_F10R1_FB27_Pos (27U)
<> 161:2cc1468da177 4014 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4015 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4016 #define CAN_F10R1_FB28_Pos (28U)
<> 161:2cc1468da177 4017 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4018 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4019 #define CAN_F10R1_FB29_Pos (29U)
<> 161:2cc1468da177 4020 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 4021 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 4022 #define CAN_F10R1_FB30_Pos (30U)
<> 161:2cc1468da177 4023 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 4024 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 4025 #define CAN_F10R1_FB31_Pos (31U)
<> 161:2cc1468da177 4026 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 4027 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4028
<> 144:ef7eb2e8f9f7 4029 /******************* Bit definition for CAN_F11R1 register ******************/
<> 161:2cc1468da177 4030 #define CAN_F11R1_FB0_Pos (0U)
<> 161:2cc1468da177 4031 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 4032 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 4033 #define CAN_F11R1_FB1_Pos (1U)
<> 161:2cc1468da177 4034 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 4035 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 4036 #define CAN_F11R1_FB2_Pos (2U)
<> 161:2cc1468da177 4037 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 4038 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 4039 #define CAN_F11R1_FB3_Pos (3U)
<> 161:2cc1468da177 4040 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 4041 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 4042 #define CAN_F11R1_FB4_Pos (4U)
<> 161:2cc1468da177 4043 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 4044 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 4045 #define CAN_F11R1_FB5_Pos (5U)
<> 161:2cc1468da177 4046 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 4047 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 4048 #define CAN_F11R1_FB6_Pos (6U)
<> 161:2cc1468da177 4049 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 4050 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 4051 #define CAN_F11R1_FB7_Pos (7U)
<> 161:2cc1468da177 4052 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 4053 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 4054 #define CAN_F11R1_FB8_Pos (8U)
<> 161:2cc1468da177 4055 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 4056 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 4057 #define CAN_F11R1_FB9_Pos (9U)
<> 161:2cc1468da177 4058 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 4059 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 4060 #define CAN_F11R1_FB10_Pos (10U)
<> 161:2cc1468da177 4061 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 4062 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 4063 #define CAN_F11R1_FB11_Pos (11U)
<> 161:2cc1468da177 4064 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 4065 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 4066 #define CAN_F11R1_FB12_Pos (12U)
<> 161:2cc1468da177 4067 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 4068 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 4069 #define CAN_F11R1_FB13_Pos (13U)
<> 161:2cc1468da177 4070 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 4071 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 4072 #define CAN_F11R1_FB14_Pos (14U)
<> 161:2cc1468da177 4073 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 4074 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 4075 #define CAN_F11R1_FB15_Pos (15U)
<> 161:2cc1468da177 4076 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 4077 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 4078 #define CAN_F11R1_FB16_Pos (16U)
<> 161:2cc1468da177 4079 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 4080 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 4081 #define CAN_F11R1_FB17_Pos (17U)
<> 161:2cc1468da177 4082 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 4083 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 4084 #define CAN_F11R1_FB18_Pos (18U)
<> 161:2cc1468da177 4085 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 4086 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 4087 #define CAN_F11R1_FB19_Pos (19U)
<> 161:2cc1468da177 4088 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 4089 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 4090 #define CAN_F11R1_FB20_Pos (20U)
<> 161:2cc1468da177 4091 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 4092 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 4093 #define CAN_F11R1_FB21_Pos (21U)
<> 161:2cc1468da177 4094 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 4095 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 4096 #define CAN_F11R1_FB22_Pos (22U)
<> 161:2cc1468da177 4097 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4098 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4099 #define CAN_F11R1_FB23_Pos (23U)
<> 161:2cc1468da177 4100 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4101 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4102 #define CAN_F11R1_FB24_Pos (24U)
<> 161:2cc1468da177 4103 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4104 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4105 #define CAN_F11R1_FB25_Pos (25U)
<> 161:2cc1468da177 4106 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4107 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4108 #define CAN_F11R1_FB26_Pos (26U)
<> 161:2cc1468da177 4109 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4110 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4111 #define CAN_F11R1_FB27_Pos (27U)
<> 161:2cc1468da177 4112 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4113 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4114 #define CAN_F11R1_FB28_Pos (28U)
<> 161:2cc1468da177 4115 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4116 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4117 #define CAN_F11R1_FB29_Pos (29U)
<> 161:2cc1468da177 4118 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 4119 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 4120 #define CAN_F11R1_FB30_Pos (30U)
<> 161:2cc1468da177 4121 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 4122 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 4123 #define CAN_F11R1_FB31_Pos (31U)
<> 161:2cc1468da177 4124 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 4125 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4126
<> 144:ef7eb2e8f9f7 4127 /******************* Bit definition for CAN_F12R1 register ******************/
<> 161:2cc1468da177 4128 #define CAN_F12R1_FB0_Pos (0U)
<> 161:2cc1468da177 4129 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 4130 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 4131 #define CAN_F12R1_FB1_Pos (1U)
<> 161:2cc1468da177 4132 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 4133 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 4134 #define CAN_F12R1_FB2_Pos (2U)
<> 161:2cc1468da177 4135 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 4136 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 4137 #define CAN_F12R1_FB3_Pos (3U)
<> 161:2cc1468da177 4138 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 4139 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 4140 #define CAN_F12R1_FB4_Pos (4U)
<> 161:2cc1468da177 4141 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 4142 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 4143 #define CAN_F12R1_FB5_Pos (5U)
<> 161:2cc1468da177 4144 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 4145 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 4146 #define CAN_F12R1_FB6_Pos (6U)
<> 161:2cc1468da177 4147 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 4148 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 4149 #define CAN_F12R1_FB7_Pos (7U)
<> 161:2cc1468da177 4150 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 4151 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 4152 #define CAN_F12R1_FB8_Pos (8U)
<> 161:2cc1468da177 4153 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 4154 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 4155 #define CAN_F12R1_FB9_Pos (9U)
<> 161:2cc1468da177 4156 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 4157 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 4158 #define CAN_F12R1_FB10_Pos (10U)
<> 161:2cc1468da177 4159 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 4160 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 4161 #define CAN_F12R1_FB11_Pos (11U)
<> 161:2cc1468da177 4162 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 4163 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 4164 #define CAN_F12R1_FB12_Pos (12U)
<> 161:2cc1468da177 4165 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 4166 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 4167 #define CAN_F12R1_FB13_Pos (13U)
<> 161:2cc1468da177 4168 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 4169 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 4170 #define CAN_F12R1_FB14_Pos (14U)
<> 161:2cc1468da177 4171 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 4172 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 4173 #define CAN_F12R1_FB15_Pos (15U)
<> 161:2cc1468da177 4174 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 4175 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 4176 #define CAN_F12R1_FB16_Pos (16U)
<> 161:2cc1468da177 4177 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 4178 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 4179 #define CAN_F12R1_FB17_Pos (17U)
<> 161:2cc1468da177 4180 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 4181 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 4182 #define CAN_F12R1_FB18_Pos (18U)
<> 161:2cc1468da177 4183 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 4184 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 4185 #define CAN_F12R1_FB19_Pos (19U)
<> 161:2cc1468da177 4186 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 4187 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 4188 #define CAN_F12R1_FB20_Pos (20U)
<> 161:2cc1468da177 4189 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 4190 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 4191 #define CAN_F12R1_FB21_Pos (21U)
<> 161:2cc1468da177 4192 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 4193 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 4194 #define CAN_F12R1_FB22_Pos (22U)
<> 161:2cc1468da177 4195 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4196 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4197 #define CAN_F12R1_FB23_Pos (23U)
<> 161:2cc1468da177 4198 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4199 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4200 #define CAN_F12R1_FB24_Pos (24U)
<> 161:2cc1468da177 4201 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4202 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4203 #define CAN_F12R1_FB25_Pos (25U)
<> 161:2cc1468da177 4204 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4205 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4206 #define CAN_F12R1_FB26_Pos (26U)
<> 161:2cc1468da177 4207 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4208 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4209 #define CAN_F12R1_FB27_Pos (27U)
<> 161:2cc1468da177 4210 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4211 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4212 #define CAN_F12R1_FB28_Pos (28U)
<> 161:2cc1468da177 4213 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4214 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4215 #define CAN_F12R1_FB29_Pos (29U)
<> 161:2cc1468da177 4216 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 4217 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 4218 #define CAN_F12R1_FB30_Pos (30U)
<> 161:2cc1468da177 4219 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 4220 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 4221 #define CAN_F12R1_FB31_Pos (31U)
<> 161:2cc1468da177 4222 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 4223 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4224
<> 144:ef7eb2e8f9f7 4225 /******************* Bit definition for CAN_F13R1 register ******************/
<> 161:2cc1468da177 4226 #define CAN_F13R1_FB0_Pos (0U)
<> 161:2cc1468da177 4227 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 4228 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 4229 #define CAN_F13R1_FB1_Pos (1U)
<> 161:2cc1468da177 4230 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 4231 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 4232 #define CAN_F13R1_FB2_Pos (2U)
<> 161:2cc1468da177 4233 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 4234 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 4235 #define CAN_F13R1_FB3_Pos (3U)
<> 161:2cc1468da177 4236 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 4237 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 4238 #define CAN_F13R1_FB4_Pos (4U)
<> 161:2cc1468da177 4239 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 4240 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 4241 #define CAN_F13R1_FB5_Pos (5U)
<> 161:2cc1468da177 4242 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 4243 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 4244 #define CAN_F13R1_FB6_Pos (6U)
<> 161:2cc1468da177 4245 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 4246 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 4247 #define CAN_F13R1_FB7_Pos (7U)
<> 161:2cc1468da177 4248 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 4249 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 4250 #define CAN_F13R1_FB8_Pos (8U)
<> 161:2cc1468da177 4251 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 4252 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 4253 #define CAN_F13R1_FB9_Pos (9U)
<> 161:2cc1468da177 4254 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 4255 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 4256 #define CAN_F13R1_FB10_Pos (10U)
<> 161:2cc1468da177 4257 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 4258 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 4259 #define CAN_F13R1_FB11_Pos (11U)
<> 161:2cc1468da177 4260 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 4261 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 4262 #define CAN_F13R1_FB12_Pos (12U)
<> 161:2cc1468da177 4263 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 4264 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 4265 #define CAN_F13R1_FB13_Pos (13U)
<> 161:2cc1468da177 4266 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 4267 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 4268 #define CAN_F13R1_FB14_Pos (14U)
<> 161:2cc1468da177 4269 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 4270 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 4271 #define CAN_F13R1_FB15_Pos (15U)
<> 161:2cc1468da177 4272 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 4273 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 4274 #define CAN_F13R1_FB16_Pos (16U)
<> 161:2cc1468da177 4275 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 4276 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 4277 #define CAN_F13R1_FB17_Pos (17U)
<> 161:2cc1468da177 4278 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 4279 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 4280 #define CAN_F13R1_FB18_Pos (18U)
<> 161:2cc1468da177 4281 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 4282 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 4283 #define CAN_F13R1_FB19_Pos (19U)
<> 161:2cc1468da177 4284 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 4285 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 4286 #define CAN_F13R1_FB20_Pos (20U)
<> 161:2cc1468da177 4287 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 4288 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 4289 #define CAN_F13R1_FB21_Pos (21U)
<> 161:2cc1468da177 4290 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 4291 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 4292 #define CAN_F13R1_FB22_Pos (22U)
<> 161:2cc1468da177 4293 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4294 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4295 #define CAN_F13R1_FB23_Pos (23U)
<> 161:2cc1468da177 4296 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4297 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4298 #define CAN_F13R1_FB24_Pos (24U)
<> 161:2cc1468da177 4299 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4300 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4301 #define CAN_F13R1_FB25_Pos (25U)
<> 161:2cc1468da177 4302 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4303 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4304 #define CAN_F13R1_FB26_Pos (26U)
<> 161:2cc1468da177 4305 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4306 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4307 #define CAN_F13R1_FB27_Pos (27U)
<> 161:2cc1468da177 4308 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4309 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4310 #define CAN_F13R1_FB28_Pos (28U)
<> 161:2cc1468da177 4311 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4312 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4313 #define CAN_F13R1_FB29_Pos (29U)
<> 161:2cc1468da177 4314 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 4315 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 4316 #define CAN_F13R1_FB30_Pos (30U)
<> 161:2cc1468da177 4317 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 4318 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 4319 #define CAN_F13R1_FB31_Pos (31U)
<> 161:2cc1468da177 4320 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 4321 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4322
<> 144:ef7eb2e8f9f7 4323 /******************* Bit definition for CAN_F0R2 register *******************/
<> 161:2cc1468da177 4324 #define CAN_F0R2_FB0_Pos (0U)
<> 161:2cc1468da177 4325 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 4326 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 4327 #define CAN_F0R2_FB1_Pos (1U)
<> 161:2cc1468da177 4328 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 4329 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 4330 #define CAN_F0R2_FB2_Pos (2U)
<> 161:2cc1468da177 4331 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 4332 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 4333 #define CAN_F0R2_FB3_Pos (3U)
<> 161:2cc1468da177 4334 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 4335 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 4336 #define CAN_F0R2_FB4_Pos (4U)
<> 161:2cc1468da177 4337 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 4338 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 4339 #define CAN_F0R2_FB5_Pos (5U)
<> 161:2cc1468da177 4340 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 4341 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 4342 #define CAN_F0R2_FB6_Pos (6U)
<> 161:2cc1468da177 4343 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 4344 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 4345 #define CAN_F0R2_FB7_Pos (7U)
<> 161:2cc1468da177 4346 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 4347 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 4348 #define CAN_F0R2_FB8_Pos (8U)
<> 161:2cc1468da177 4349 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 4350 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 4351 #define CAN_F0R2_FB9_Pos (9U)
<> 161:2cc1468da177 4352 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 4353 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 4354 #define CAN_F0R2_FB10_Pos (10U)
<> 161:2cc1468da177 4355 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 4356 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 4357 #define CAN_F0R2_FB11_Pos (11U)
<> 161:2cc1468da177 4358 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 4359 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 4360 #define CAN_F0R2_FB12_Pos (12U)
<> 161:2cc1468da177 4361 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 4362 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 4363 #define CAN_F0R2_FB13_Pos (13U)
<> 161:2cc1468da177 4364 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 4365 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 4366 #define CAN_F0R2_FB14_Pos (14U)
<> 161:2cc1468da177 4367 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 4368 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 4369 #define CAN_F0R2_FB15_Pos (15U)
<> 161:2cc1468da177 4370 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 4371 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 4372 #define CAN_F0R2_FB16_Pos (16U)
<> 161:2cc1468da177 4373 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 4374 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 4375 #define CAN_F0R2_FB17_Pos (17U)
<> 161:2cc1468da177 4376 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 4377 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 4378 #define CAN_F0R2_FB18_Pos (18U)
<> 161:2cc1468da177 4379 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 4380 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 4381 #define CAN_F0R2_FB19_Pos (19U)
<> 161:2cc1468da177 4382 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 4383 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 4384 #define CAN_F0R2_FB20_Pos (20U)
<> 161:2cc1468da177 4385 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 4386 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 4387 #define CAN_F0R2_FB21_Pos (21U)
<> 161:2cc1468da177 4388 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 4389 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 4390 #define CAN_F0R2_FB22_Pos (22U)
<> 161:2cc1468da177 4391 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4392 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4393 #define CAN_F0R2_FB23_Pos (23U)
<> 161:2cc1468da177 4394 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4395 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4396 #define CAN_F0R2_FB24_Pos (24U)
<> 161:2cc1468da177 4397 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4398 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4399 #define CAN_F0R2_FB25_Pos (25U)
<> 161:2cc1468da177 4400 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4401 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4402 #define CAN_F0R2_FB26_Pos (26U)
<> 161:2cc1468da177 4403 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4404 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4405 #define CAN_F0R2_FB27_Pos (27U)
<> 161:2cc1468da177 4406 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4407 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4408 #define CAN_F0R2_FB28_Pos (28U)
<> 161:2cc1468da177 4409 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4410 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4411 #define CAN_F0R2_FB29_Pos (29U)
<> 161:2cc1468da177 4412 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 4413 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 4414 #define CAN_F0R2_FB30_Pos (30U)
<> 161:2cc1468da177 4415 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 4416 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 4417 #define CAN_F0R2_FB31_Pos (31U)
<> 161:2cc1468da177 4418 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 4419 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4420
<> 144:ef7eb2e8f9f7 4421 /******************* Bit definition for CAN_F1R2 register *******************/
<> 161:2cc1468da177 4422 #define CAN_F1R2_FB0_Pos (0U)
<> 161:2cc1468da177 4423 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 4424 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 4425 #define CAN_F1R2_FB1_Pos (1U)
<> 161:2cc1468da177 4426 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 4427 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 4428 #define CAN_F1R2_FB2_Pos (2U)
<> 161:2cc1468da177 4429 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 4430 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 4431 #define CAN_F1R2_FB3_Pos (3U)
<> 161:2cc1468da177 4432 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 4433 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 4434 #define CAN_F1R2_FB4_Pos (4U)
<> 161:2cc1468da177 4435 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 4436 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 4437 #define CAN_F1R2_FB5_Pos (5U)
<> 161:2cc1468da177 4438 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 4439 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 4440 #define CAN_F1R2_FB6_Pos (6U)
<> 161:2cc1468da177 4441 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 4442 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 4443 #define CAN_F1R2_FB7_Pos (7U)
<> 161:2cc1468da177 4444 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 4445 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 4446 #define CAN_F1R2_FB8_Pos (8U)
<> 161:2cc1468da177 4447 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 4448 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 4449 #define CAN_F1R2_FB9_Pos (9U)
<> 161:2cc1468da177 4450 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 4451 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 4452 #define CAN_F1R2_FB10_Pos (10U)
<> 161:2cc1468da177 4453 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 4454 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 4455 #define CAN_F1R2_FB11_Pos (11U)
<> 161:2cc1468da177 4456 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 4457 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 4458 #define CAN_F1R2_FB12_Pos (12U)
<> 161:2cc1468da177 4459 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 4460 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 4461 #define CAN_F1R2_FB13_Pos (13U)
<> 161:2cc1468da177 4462 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 4463 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 4464 #define CAN_F1R2_FB14_Pos (14U)
<> 161:2cc1468da177 4465 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 4466 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 4467 #define CAN_F1R2_FB15_Pos (15U)
<> 161:2cc1468da177 4468 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 4469 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 4470 #define CAN_F1R2_FB16_Pos (16U)
<> 161:2cc1468da177 4471 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 4472 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 4473 #define CAN_F1R2_FB17_Pos (17U)
<> 161:2cc1468da177 4474 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 4475 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 4476 #define CAN_F1R2_FB18_Pos (18U)
<> 161:2cc1468da177 4477 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 4478 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 4479 #define CAN_F1R2_FB19_Pos (19U)
<> 161:2cc1468da177 4480 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 4481 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 4482 #define CAN_F1R2_FB20_Pos (20U)
<> 161:2cc1468da177 4483 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 4484 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 4485 #define CAN_F1R2_FB21_Pos (21U)
<> 161:2cc1468da177 4486 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 4487 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 4488 #define CAN_F1R2_FB22_Pos (22U)
<> 161:2cc1468da177 4489 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4490 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4491 #define CAN_F1R2_FB23_Pos (23U)
<> 161:2cc1468da177 4492 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4493 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4494 #define CAN_F1R2_FB24_Pos (24U)
<> 161:2cc1468da177 4495 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4496 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4497 #define CAN_F1R2_FB25_Pos (25U)
<> 161:2cc1468da177 4498 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4499 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4500 #define CAN_F1R2_FB26_Pos (26U)
<> 161:2cc1468da177 4501 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4502 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4503 #define CAN_F1R2_FB27_Pos (27U)
<> 161:2cc1468da177 4504 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4505 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4506 #define CAN_F1R2_FB28_Pos (28U)
<> 161:2cc1468da177 4507 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4508 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4509 #define CAN_F1R2_FB29_Pos (29U)
<> 161:2cc1468da177 4510 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 4511 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 4512 #define CAN_F1R2_FB30_Pos (30U)
<> 161:2cc1468da177 4513 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 4514 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 4515 #define CAN_F1R2_FB31_Pos (31U)
<> 161:2cc1468da177 4516 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 4517 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4518
<> 144:ef7eb2e8f9f7 4519 /******************* Bit definition for CAN_F2R2 register *******************/
<> 161:2cc1468da177 4520 #define CAN_F2R2_FB0_Pos (0U)
<> 161:2cc1468da177 4521 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 4522 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 4523 #define CAN_F2R2_FB1_Pos (1U)
<> 161:2cc1468da177 4524 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 4525 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 4526 #define CAN_F2R2_FB2_Pos (2U)
<> 161:2cc1468da177 4527 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 4528 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 4529 #define CAN_F2R2_FB3_Pos (3U)
<> 161:2cc1468da177 4530 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 4531 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 4532 #define CAN_F2R2_FB4_Pos (4U)
<> 161:2cc1468da177 4533 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 4534 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 4535 #define CAN_F2R2_FB5_Pos (5U)
<> 161:2cc1468da177 4536 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 4537 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 4538 #define CAN_F2R2_FB6_Pos (6U)
<> 161:2cc1468da177 4539 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 4540 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 4541 #define CAN_F2R2_FB7_Pos (7U)
<> 161:2cc1468da177 4542 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 4543 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 4544 #define CAN_F2R2_FB8_Pos (8U)
<> 161:2cc1468da177 4545 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 4546 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 4547 #define CAN_F2R2_FB9_Pos (9U)
<> 161:2cc1468da177 4548 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 4549 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 4550 #define CAN_F2R2_FB10_Pos (10U)
<> 161:2cc1468da177 4551 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 4552 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 4553 #define CAN_F2R2_FB11_Pos (11U)
<> 161:2cc1468da177 4554 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 4555 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 4556 #define CAN_F2R2_FB12_Pos (12U)
<> 161:2cc1468da177 4557 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 4558 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 4559 #define CAN_F2R2_FB13_Pos (13U)
<> 161:2cc1468da177 4560 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 4561 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 4562 #define CAN_F2R2_FB14_Pos (14U)
<> 161:2cc1468da177 4563 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 4564 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 4565 #define CAN_F2R2_FB15_Pos (15U)
<> 161:2cc1468da177 4566 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 4567 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 4568 #define CAN_F2R2_FB16_Pos (16U)
<> 161:2cc1468da177 4569 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 4570 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 4571 #define CAN_F2R2_FB17_Pos (17U)
<> 161:2cc1468da177 4572 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 4573 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 4574 #define CAN_F2R2_FB18_Pos (18U)
<> 161:2cc1468da177 4575 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 4576 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 4577 #define CAN_F2R2_FB19_Pos (19U)
<> 161:2cc1468da177 4578 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 4579 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 4580 #define CAN_F2R2_FB20_Pos (20U)
<> 161:2cc1468da177 4581 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 4582 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 4583 #define CAN_F2R2_FB21_Pos (21U)
<> 161:2cc1468da177 4584 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 4585 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 4586 #define CAN_F2R2_FB22_Pos (22U)
<> 161:2cc1468da177 4587 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4588 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4589 #define CAN_F2R2_FB23_Pos (23U)
<> 161:2cc1468da177 4590 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4591 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4592 #define CAN_F2R2_FB24_Pos (24U)
<> 161:2cc1468da177 4593 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4594 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4595 #define CAN_F2R2_FB25_Pos (25U)
<> 161:2cc1468da177 4596 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4597 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4598 #define CAN_F2R2_FB26_Pos (26U)
<> 161:2cc1468da177 4599 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4600 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4601 #define CAN_F2R2_FB27_Pos (27U)
<> 161:2cc1468da177 4602 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4603 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4604 #define CAN_F2R2_FB28_Pos (28U)
<> 161:2cc1468da177 4605 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4606 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4607 #define CAN_F2R2_FB29_Pos (29U)
<> 161:2cc1468da177 4608 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 4609 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 4610 #define CAN_F2R2_FB30_Pos (30U)
<> 161:2cc1468da177 4611 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 4612 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 4613 #define CAN_F2R2_FB31_Pos (31U)
<> 161:2cc1468da177 4614 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 4615 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4616
<> 144:ef7eb2e8f9f7 4617 /******************* Bit definition for CAN_F3R2 register *******************/
<> 161:2cc1468da177 4618 #define CAN_F3R2_FB0_Pos (0U)
<> 161:2cc1468da177 4619 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 4620 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 4621 #define CAN_F3R2_FB1_Pos (1U)
<> 161:2cc1468da177 4622 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 4623 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 4624 #define CAN_F3R2_FB2_Pos (2U)
<> 161:2cc1468da177 4625 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 4626 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 4627 #define CAN_F3R2_FB3_Pos (3U)
<> 161:2cc1468da177 4628 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 4629 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 4630 #define CAN_F3R2_FB4_Pos (4U)
<> 161:2cc1468da177 4631 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 4632 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 4633 #define CAN_F3R2_FB5_Pos (5U)
<> 161:2cc1468da177 4634 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 4635 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 4636 #define CAN_F3R2_FB6_Pos (6U)
<> 161:2cc1468da177 4637 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 4638 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 4639 #define CAN_F3R2_FB7_Pos (7U)
<> 161:2cc1468da177 4640 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 4641 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 4642 #define CAN_F3R2_FB8_Pos (8U)
<> 161:2cc1468da177 4643 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 4644 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 4645 #define CAN_F3R2_FB9_Pos (9U)
<> 161:2cc1468da177 4646 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 4647 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 4648 #define CAN_F3R2_FB10_Pos (10U)
<> 161:2cc1468da177 4649 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 4650 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 4651 #define CAN_F3R2_FB11_Pos (11U)
<> 161:2cc1468da177 4652 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 4653 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 4654 #define CAN_F3R2_FB12_Pos (12U)
<> 161:2cc1468da177 4655 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 4656 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 4657 #define CAN_F3R2_FB13_Pos (13U)
<> 161:2cc1468da177 4658 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 4659 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 4660 #define CAN_F3R2_FB14_Pos (14U)
<> 161:2cc1468da177 4661 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 4662 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 4663 #define CAN_F3R2_FB15_Pos (15U)
<> 161:2cc1468da177 4664 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 4665 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 4666 #define CAN_F3R2_FB16_Pos (16U)
<> 161:2cc1468da177 4667 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 4668 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 4669 #define CAN_F3R2_FB17_Pos (17U)
<> 161:2cc1468da177 4670 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 4671 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 4672 #define CAN_F3R2_FB18_Pos (18U)
<> 161:2cc1468da177 4673 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 4674 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 4675 #define CAN_F3R2_FB19_Pos (19U)
<> 161:2cc1468da177 4676 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 4677 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 4678 #define CAN_F3R2_FB20_Pos (20U)
<> 161:2cc1468da177 4679 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 4680 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 4681 #define CAN_F3R2_FB21_Pos (21U)
<> 161:2cc1468da177 4682 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 4683 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 4684 #define CAN_F3R2_FB22_Pos (22U)
<> 161:2cc1468da177 4685 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4686 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4687 #define CAN_F3R2_FB23_Pos (23U)
<> 161:2cc1468da177 4688 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4689 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4690 #define CAN_F3R2_FB24_Pos (24U)
<> 161:2cc1468da177 4691 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4692 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4693 #define CAN_F3R2_FB25_Pos (25U)
<> 161:2cc1468da177 4694 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4695 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4696 #define CAN_F3R2_FB26_Pos (26U)
<> 161:2cc1468da177 4697 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4698 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4699 #define CAN_F3R2_FB27_Pos (27U)
<> 161:2cc1468da177 4700 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4701 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4702 #define CAN_F3R2_FB28_Pos (28U)
<> 161:2cc1468da177 4703 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4704 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4705 #define CAN_F3R2_FB29_Pos (29U)
<> 161:2cc1468da177 4706 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 4707 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 4708 #define CAN_F3R2_FB30_Pos (30U)
<> 161:2cc1468da177 4709 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 4710 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 4711 #define CAN_F3R2_FB31_Pos (31U)
<> 161:2cc1468da177 4712 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 4713 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4714
<> 144:ef7eb2e8f9f7 4715 /******************* Bit definition for CAN_F4R2 register *******************/
<> 161:2cc1468da177 4716 #define CAN_F4R2_FB0_Pos (0U)
<> 161:2cc1468da177 4717 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 4718 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 4719 #define CAN_F4R2_FB1_Pos (1U)
<> 161:2cc1468da177 4720 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 4721 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 4722 #define CAN_F4R2_FB2_Pos (2U)
<> 161:2cc1468da177 4723 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 4724 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 4725 #define CAN_F4R2_FB3_Pos (3U)
<> 161:2cc1468da177 4726 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 4727 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 4728 #define CAN_F4R2_FB4_Pos (4U)
<> 161:2cc1468da177 4729 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 4730 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 4731 #define CAN_F4R2_FB5_Pos (5U)
<> 161:2cc1468da177 4732 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 4733 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 4734 #define CAN_F4R2_FB6_Pos (6U)
<> 161:2cc1468da177 4735 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 4736 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 4737 #define CAN_F4R2_FB7_Pos (7U)
<> 161:2cc1468da177 4738 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 4739 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 4740 #define CAN_F4R2_FB8_Pos (8U)
<> 161:2cc1468da177 4741 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 4742 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 4743 #define CAN_F4R2_FB9_Pos (9U)
<> 161:2cc1468da177 4744 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 4745 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 4746 #define CAN_F4R2_FB10_Pos (10U)
<> 161:2cc1468da177 4747 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 4748 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 4749 #define CAN_F4R2_FB11_Pos (11U)
<> 161:2cc1468da177 4750 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 4751 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 4752 #define CAN_F4R2_FB12_Pos (12U)
<> 161:2cc1468da177 4753 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 4754 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 4755 #define CAN_F4R2_FB13_Pos (13U)
<> 161:2cc1468da177 4756 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 4757 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 4758 #define CAN_F4R2_FB14_Pos (14U)
<> 161:2cc1468da177 4759 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 4760 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 4761 #define CAN_F4R2_FB15_Pos (15U)
<> 161:2cc1468da177 4762 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 4763 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 4764 #define CAN_F4R2_FB16_Pos (16U)
<> 161:2cc1468da177 4765 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 4766 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 4767 #define CAN_F4R2_FB17_Pos (17U)
<> 161:2cc1468da177 4768 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 4769 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 4770 #define CAN_F4R2_FB18_Pos (18U)
<> 161:2cc1468da177 4771 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 4772 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 4773 #define CAN_F4R2_FB19_Pos (19U)
<> 161:2cc1468da177 4774 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 4775 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 4776 #define CAN_F4R2_FB20_Pos (20U)
<> 161:2cc1468da177 4777 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 4778 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 4779 #define CAN_F4R2_FB21_Pos (21U)
<> 161:2cc1468da177 4780 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 4781 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 4782 #define CAN_F4R2_FB22_Pos (22U)
<> 161:2cc1468da177 4783 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4784 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4785 #define CAN_F4R2_FB23_Pos (23U)
<> 161:2cc1468da177 4786 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4787 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4788 #define CAN_F4R2_FB24_Pos (24U)
<> 161:2cc1468da177 4789 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4790 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4791 #define CAN_F4R2_FB25_Pos (25U)
<> 161:2cc1468da177 4792 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4793 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4794 #define CAN_F4R2_FB26_Pos (26U)
<> 161:2cc1468da177 4795 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4796 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4797 #define CAN_F4R2_FB27_Pos (27U)
<> 161:2cc1468da177 4798 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4799 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4800 #define CAN_F4R2_FB28_Pos (28U)
<> 161:2cc1468da177 4801 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4802 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4803 #define CAN_F4R2_FB29_Pos (29U)
<> 161:2cc1468da177 4804 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 4805 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 4806 #define CAN_F4R2_FB30_Pos (30U)
<> 161:2cc1468da177 4807 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 4808 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 4809 #define CAN_F4R2_FB31_Pos (31U)
<> 161:2cc1468da177 4810 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 4811 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4812
<> 144:ef7eb2e8f9f7 4813 /******************* Bit definition for CAN_F5R2 register *******************/
<> 161:2cc1468da177 4814 #define CAN_F5R2_FB0_Pos (0U)
<> 161:2cc1468da177 4815 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 4816 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 4817 #define CAN_F5R2_FB1_Pos (1U)
<> 161:2cc1468da177 4818 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 4819 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 4820 #define CAN_F5R2_FB2_Pos (2U)
<> 161:2cc1468da177 4821 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 4822 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 4823 #define CAN_F5R2_FB3_Pos (3U)
<> 161:2cc1468da177 4824 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 4825 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 4826 #define CAN_F5R2_FB4_Pos (4U)
<> 161:2cc1468da177 4827 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 4828 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 4829 #define CAN_F5R2_FB5_Pos (5U)
<> 161:2cc1468da177 4830 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 4831 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 4832 #define CAN_F5R2_FB6_Pos (6U)
<> 161:2cc1468da177 4833 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 4834 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 4835 #define CAN_F5R2_FB7_Pos (7U)
<> 161:2cc1468da177 4836 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 4837 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 4838 #define CAN_F5R2_FB8_Pos (8U)
<> 161:2cc1468da177 4839 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 4840 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 4841 #define CAN_F5R2_FB9_Pos (9U)
<> 161:2cc1468da177 4842 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 4843 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 4844 #define CAN_F5R2_FB10_Pos (10U)
<> 161:2cc1468da177 4845 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 4846 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 4847 #define CAN_F5R2_FB11_Pos (11U)
<> 161:2cc1468da177 4848 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 4849 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 4850 #define CAN_F5R2_FB12_Pos (12U)
<> 161:2cc1468da177 4851 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 4852 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 4853 #define CAN_F5R2_FB13_Pos (13U)
<> 161:2cc1468da177 4854 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 4855 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 4856 #define CAN_F5R2_FB14_Pos (14U)
<> 161:2cc1468da177 4857 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 4858 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 4859 #define CAN_F5R2_FB15_Pos (15U)
<> 161:2cc1468da177 4860 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 4861 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 4862 #define CAN_F5R2_FB16_Pos (16U)
<> 161:2cc1468da177 4863 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 4864 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 4865 #define CAN_F5R2_FB17_Pos (17U)
<> 161:2cc1468da177 4866 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 4867 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 4868 #define CAN_F5R2_FB18_Pos (18U)
<> 161:2cc1468da177 4869 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 4870 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 4871 #define CAN_F5R2_FB19_Pos (19U)
<> 161:2cc1468da177 4872 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 4873 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 4874 #define CAN_F5R2_FB20_Pos (20U)
<> 161:2cc1468da177 4875 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 4876 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 4877 #define CAN_F5R2_FB21_Pos (21U)
<> 161:2cc1468da177 4878 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 4879 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 4880 #define CAN_F5R2_FB22_Pos (22U)
<> 161:2cc1468da177 4881 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4882 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4883 #define CAN_F5R2_FB23_Pos (23U)
<> 161:2cc1468da177 4884 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4885 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4886 #define CAN_F5R2_FB24_Pos (24U)
<> 161:2cc1468da177 4887 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4888 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4889 #define CAN_F5R2_FB25_Pos (25U)
<> 161:2cc1468da177 4890 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4891 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4892 #define CAN_F5R2_FB26_Pos (26U)
<> 161:2cc1468da177 4893 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4894 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4895 #define CAN_F5R2_FB27_Pos (27U)
<> 161:2cc1468da177 4896 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4897 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4898 #define CAN_F5R2_FB28_Pos (28U)
<> 161:2cc1468da177 4899 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4900 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4901 #define CAN_F5R2_FB29_Pos (29U)
<> 161:2cc1468da177 4902 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 4903 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 4904 #define CAN_F5R2_FB30_Pos (30U)
<> 161:2cc1468da177 4905 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 4906 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 4907 #define CAN_F5R2_FB31_Pos (31U)
<> 161:2cc1468da177 4908 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 4909 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4910
<> 144:ef7eb2e8f9f7 4911 /******************* Bit definition for CAN_F6R2 register *******************/
<> 161:2cc1468da177 4912 #define CAN_F6R2_FB0_Pos (0U)
<> 161:2cc1468da177 4913 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 4914 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 4915 #define CAN_F6R2_FB1_Pos (1U)
<> 161:2cc1468da177 4916 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 4917 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 4918 #define CAN_F6R2_FB2_Pos (2U)
<> 161:2cc1468da177 4919 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 4920 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 4921 #define CAN_F6R2_FB3_Pos (3U)
<> 161:2cc1468da177 4922 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 4923 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 4924 #define CAN_F6R2_FB4_Pos (4U)
<> 161:2cc1468da177 4925 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 4926 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 4927 #define CAN_F6R2_FB5_Pos (5U)
<> 161:2cc1468da177 4928 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 4929 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 4930 #define CAN_F6R2_FB6_Pos (6U)
<> 161:2cc1468da177 4931 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 4932 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 4933 #define CAN_F6R2_FB7_Pos (7U)
<> 161:2cc1468da177 4934 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 4935 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 4936 #define CAN_F6R2_FB8_Pos (8U)
<> 161:2cc1468da177 4937 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 4938 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 4939 #define CAN_F6R2_FB9_Pos (9U)
<> 161:2cc1468da177 4940 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 4941 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 4942 #define CAN_F6R2_FB10_Pos (10U)
<> 161:2cc1468da177 4943 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 4944 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 4945 #define CAN_F6R2_FB11_Pos (11U)
<> 161:2cc1468da177 4946 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 4947 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 4948 #define CAN_F6R2_FB12_Pos (12U)
<> 161:2cc1468da177 4949 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 4950 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 4951 #define CAN_F6R2_FB13_Pos (13U)
<> 161:2cc1468da177 4952 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 4953 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 4954 #define CAN_F6R2_FB14_Pos (14U)
<> 161:2cc1468da177 4955 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 4956 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 4957 #define CAN_F6R2_FB15_Pos (15U)
<> 161:2cc1468da177 4958 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 4959 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 4960 #define CAN_F6R2_FB16_Pos (16U)
<> 161:2cc1468da177 4961 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 4962 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 4963 #define CAN_F6R2_FB17_Pos (17U)
<> 161:2cc1468da177 4964 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 4965 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 4966 #define CAN_F6R2_FB18_Pos (18U)
<> 161:2cc1468da177 4967 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 4968 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 4969 #define CAN_F6R2_FB19_Pos (19U)
<> 161:2cc1468da177 4970 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 4971 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 4972 #define CAN_F6R2_FB20_Pos (20U)
<> 161:2cc1468da177 4973 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 4974 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 4975 #define CAN_F6R2_FB21_Pos (21U)
<> 161:2cc1468da177 4976 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 4977 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 4978 #define CAN_F6R2_FB22_Pos (22U)
<> 161:2cc1468da177 4979 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 4980 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 4981 #define CAN_F6R2_FB23_Pos (23U)
<> 161:2cc1468da177 4982 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 4983 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 4984 #define CAN_F6R2_FB24_Pos (24U)
<> 161:2cc1468da177 4985 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 4986 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 4987 #define CAN_F6R2_FB25_Pos (25U)
<> 161:2cc1468da177 4988 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 4989 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 4990 #define CAN_F6R2_FB26_Pos (26U)
<> 161:2cc1468da177 4991 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 4992 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 4993 #define CAN_F6R2_FB27_Pos (27U)
<> 161:2cc1468da177 4994 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 4995 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 4996 #define CAN_F6R2_FB28_Pos (28U)
<> 161:2cc1468da177 4997 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 4998 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 4999 #define CAN_F6R2_FB29_Pos (29U)
<> 161:2cc1468da177 5000 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 5001 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 5002 #define CAN_F6R2_FB30_Pos (30U)
<> 161:2cc1468da177 5003 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 5004 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 5005 #define CAN_F6R2_FB31_Pos (31U)
<> 161:2cc1468da177 5006 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 5007 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5008
<> 144:ef7eb2e8f9f7 5009 /******************* Bit definition for CAN_F7R2 register *******************/
<> 161:2cc1468da177 5010 #define CAN_F7R2_FB0_Pos (0U)
<> 161:2cc1468da177 5011 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5012 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 5013 #define CAN_F7R2_FB1_Pos (1U)
<> 161:2cc1468da177 5014 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5015 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 5016 #define CAN_F7R2_FB2_Pos (2U)
<> 161:2cc1468da177 5017 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5018 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 5019 #define CAN_F7R2_FB3_Pos (3U)
<> 161:2cc1468da177 5020 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5021 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 5022 #define CAN_F7R2_FB4_Pos (4U)
<> 161:2cc1468da177 5023 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5024 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 5025 #define CAN_F7R2_FB5_Pos (5U)
<> 161:2cc1468da177 5026 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5027 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 5028 #define CAN_F7R2_FB6_Pos (6U)
<> 161:2cc1468da177 5029 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5030 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 5031 #define CAN_F7R2_FB7_Pos (7U)
<> 161:2cc1468da177 5032 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5033 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 5034 #define CAN_F7R2_FB8_Pos (8U)
<> 161:2cc1468da177 5035 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5036 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 5037 #define CAN_F7R2_FB9_Pos (9U)
<> 161:2cc1468da177 5038 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 5039 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 5040 #define CAN_F7R2_FB10_Pos (10U)
<> 161:2cc1468da177 5041 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 5042 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 5043 #define CAN_F7R2_FB11_Pos (11U)
<> 161:2cc1468da177 5044 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 5045 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 5046 #define CAN_F7R2_FB12_Pos (12U)
<> 161:2cc1468da177 5047 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 5048 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 5049 #define CAN_F7R2_FB13_Pos (13U)
<> 161:2cc1468da177 5050 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 5051 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 5052 #define CAN_F7R2_FB14_Pos (14U)
<> 161:2cc1468da177 5053 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 5054 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 5055 #define CAN_F7R2_FB15_Pos (15U)
<> 161:2cc1468da177 5056 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 5057 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 5058 #define CAN_F7R2_FB16_Pos (16U)
<> 161:2cc1468da177 5059 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 5060 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 5061 #define CAN_F7R2_FB17_Pos (17U)
<> 161:2cc1468da177 5062 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 5063 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 5064 #define CAN_F7R2_FB18_Pos (18U)
<> 161:2cc1468da177 5065 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 5066 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 5067 #define CAN_F7R2_FB19_Pos (19U)
<> 161:2cc1468da177 5068 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 5069 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 5070 #define CAN_F7R2_FB20_Pos (20U)
<> 161:2cc1468da177 5071 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 5072 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 5073 #define CAN_F7R2_FB21_Pos (21U)
<> 161:2cc1468da177 5074 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 5075 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 5076 #define CAN_F7R2_FB22_Pos (22U)
<> 161:2cc1468da177 5077 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 5078 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 5079 #define CAN_F7R2_FB23_Pos (23U)
<> 161:2cc1468da177 5080 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 5081 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 5082 #define CAN_F7R2_FB24_Pos (24U)
<> 161:2cc1468da177 5083 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 5084 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 5085 #define CAN_F7R2_FB25_Pos (25U)
<> 161:2cc1468da177 5086 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 5087 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 5088 #define CAN_F7R2_FB26_Pos (26U)
<> 161:2cc1468da177 5089 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 5090 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 5091 #define CAN_F7R2_FB27_Pos (27U)
<> 161:2cc1468da177 5092 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 5093 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 5094 #define CAN_F7R2_FB28_Pos (28U)
<> 161:2cc1468da177 5095 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 5096 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 5097 #define CAN_F7R2_FB29_Pos (29U)
<> 161:2cc1468da177 5098 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 5099 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 5100 #define CAN_F7R2_FB30_Pos (30U)
<> 161:2cc1468da177 5101 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 5102 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 5103 #define CAN_F7R2_FB31_Pos (31U)
<> 161:2cc1468da177 5104 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 5105 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5106
<> 144:ef7eb2e8f9f7 5107 /******************* Bit definition for CAN_F8R2 register *******************/
<> 161:2cc1468da177 5108 #define CAN_F8R2_FB0_Pos (0U)
<> 161:2cc1468da177 5109 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5110 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 5111 #define CAN_F8R2_FB1_Pos (1U)
<> 161:2cc1468da177 5112 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5113 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 5114 #define CAN_F8R2_FB2_Pos (2U)
<> 161:2cc1468da177 5115 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5116 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 5117 #define CAN_F8R2_FB3_Pos (3U)
<> 161:2cc1468da177 5118 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5119 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 5120 #define CAN_F8R2_FB4_Pos (4U)
<> 161:2cc1468da177 5121 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5122 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 5123 #define CAN_F8R2_FB5_Pos (5U)
<> 161:2cc1468da177 5124 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5125 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 5126 #define CAN_F8R2_FB6_Pos (6U)
<> 161:2cc1468da177 5127 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5128 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 5129 #define CAN_F8R2_FB7_Pos (7U)
<> 161:2cc1468da177 5130 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5131 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 5132 #define CAN_F8R2_FB8_Pos (8U)
<> 161:2cc1468da177 5133 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5134 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 5135 #define CAN_F8R2_FB9_Pos (9U)
<> 161:2cc1468da177 5136 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 5137 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 5138 #define CAN_F8R2_FB10_Pos (10U)
<> 161:2cc1468da177 5139 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 5140 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 5141 #define CAN_F8R2_FB11_Pos (11U)
<> 161:2cc1468da177 5142 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 5143 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 5144 #define CAN_F8R2_FB12_Pos (12U)
<> 161:2cc1468da177 5145 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 5146 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 5147 #define CAN_F8R2_FB13_Pos (13U)
<> 161:2cc1468da177 5148 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 5149 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 5150 #define CAN_F8R2_FB14_Pos (14U)
<> 161:2cc1468da177 5151 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 5152 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 5153 #define CAN_F8R2_FB15_Pos (15U)
<> 161:2cc1468da177 5154 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 5155 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 5156 #define CAN_F8R2_FB16_Pos (16U)
<> 161:2cc1468da177 5157 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 5158 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 5159 #define CAN_F8R2_FB17_Pos (17U)
<> 161:2cc1468da177 5160 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 5161 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 5162 #define CAN_F8R2_FB18_Pos (18U)
<> 161:2cc1468da177 5163 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 5164 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 5165 #define CAN_F8R2_FB19_Pos (19U)
<> 161:2cc1468da177 5166 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 5167 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 5168 #define CAN_F8R2_FB20_Pos (20U)
<> 161:2cc1468da177 5169 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 5170 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 5171 #define CAN_F8R2_FB21_Pos (21U)
<> 161:2cc1468da177 5172 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 5173 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 5174 #define CAN_F8R2_FB22_Pos (22U)
<> 161:2cc1468da177 5175 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 5176 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 5177 #define CAN_F8R2_FB23_Pos (23U)
<> 161:2cc1468da177 5178 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 5179 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 5180 #define CAN_F8R2_FB24_Pos (24U)
<> 161:2cc1468da177 5181 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 5182 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 5183 #define CAN_F8R2_FB25_Pos (25U)
<> 161:2cc1468da177 5184 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 5185 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 5186 #define CAN_F8R2_FB26_Pos (26U)
<> 161:2cc1468da177 5187 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 5188 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 5189 #define CAN_F8R2_FB27_Pos (27U)
<> 161:2cc1468da177 5190 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 5191 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 5192 #define CAN_F8R2_FB28_Pos (28U)
<> 161:2cc1468da177 5193 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 5194 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 5195 #define CAN_F8R2_FB29_Pos (29U)
<> 161:2cc1468da177 5196 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 5197 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 5198 #define CAN_F8R2_FB30_Pos (30U)
<> 161:2cc1468da177 5199 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 5200 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 5201 #define CAN_F8R2_FB31_Pos (31U)
<> 161:2cc1468da177 5202 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 5203 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5204
<> 144:ef7eb2e8f9f7 5205 /******************* Bit definition for CAN_F9R2 register *******************/
<> 161:2cc1468da177 5206 #define CAN_F9R2_FB0_Pos (0U)
<> 161:2cc1468da177 5207 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5208 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 5209 #define CAN_F9R2_FB1_Pos (1U)
<> 161:2cc1468da177 5210 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5211 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 5212 #define CAN_F9R2_FB2_Pos (2U)
<> 161:2cc1468da177 5213 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5214 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 5215 #define CAN_F9R2_FB3_Pos (3U)
<> 161:2cc1468da177 5216 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5217 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 5218 #define CAN_F9R2_FB4_Pos (4U)
<> 161:2cc1468da177 5219 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5220 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 5221 #define CAN_F9R2_FB5_Pos (5U)
<> 161:2cc1468da177 5222 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5223 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 5224 #define CAN_F9R2_FB6_Pos (6U)
<> 161:2cc1468da177 5225 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5226 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 5227 #define CAN_F9R2_FB7_Pos (7U)
<> 161:2cc1468da177 5228 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5229 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 5230 #define CAN_F9R2_FB8_Pos (8U)
<> 161:2cc1468da177 5231 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5232 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 5233 #define CAN_F9R2_FB9_Pos (9U)
<> 161:2cc1468da177 5234 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 5235 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 5236 #define CAN_F9R2_FB10_Pos (10U)
<> 161:2cc1468da177 5237 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 5238 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 5239 #define CAN_F9R2_FB11_Pos (11U)
<> 161:2cc1468da177 5240 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 5241 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 5242 #define CAN_F9R2_FB12_Pos (12U)
<> 161:2cc1468da177 5243 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 5244 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 5245 #define CAN_F9R2_FB13_Pos (13U)
<> 161:2cc1468da177 5246 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 5247 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 5248 #define CAN_F9R2_FB14_Pos (14U)
<> 161:2cc1468da177 5249 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 5250 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 5251 #define CAN_F9R2_FB15_Pos (15U)
<> 161:2cc1468da177 5252 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 5253 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 5254 #define CAN_F9R2_FB16_Pos (16U)
<> 161:2cc1468da177 5255 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 5256 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 5257 #define CAN_F9R2_FB17_Pos (17U)
<> 161:2cc1468da177 5258 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 5259 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 5260 #define CAN_F9R2_FB18_Pos (18U)
<> 161:2cc1468da177 5261 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 5262 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 5263 #define CAN_F9R2_FB19_Pos (19U)
<> 161:2cc1468da177 5264 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 5265 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 5266 #define CAN_F9R2_FB20_Pos (20U)
<> 161:2cc1468da177 5267 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 5268 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 5269 #define CAN_F9R2_FB21_Pos (21U)
<> 161:2cc1468da177 5270 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 5271 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 5272 #define CAN_F9R2_FB22_Pos (22U)
<> 161:2cc1468da177 5273 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 5274 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 5275 #define CAN_F9R2_FB23_Pos (23U)
<> 161:2cc1468da177 5276 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 5277 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 5278 #define CAN_F9R2_FB24_Pos (24U)
<> 161:2cc1468da177 5279 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 5280 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 5281 #define CAN_F9R2_FB25_Pos (25U)
<> 161:2cc1468da177 5282 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 5283 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 5284 #define CAN_F9R2_FB26_Pos (26U)
<> 161:2cc1468da177 5285 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 5286 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 5287 #define CAN_F9R2_FB27_Pos (27U)
<> 161:2cc1468da177 5288 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 5289 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 5290 #define CAN_F9R2_FB28_Pos (28U)
<> 161:2cc1468da177 5291 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 5292 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 5293 #define CAN_F9R2_FB29_Pos (29U)
<> 161:2cc1468da177 5294 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 5295 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 5296 #define CAN_F9R2_FB30_Pos (30U)
<> 161:2cc1468da177 5297 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 5298 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 5299 #define CAN_F9R2_FB31_Pos (31U)
<> 161:2cc1468da177 5300 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 5301 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5302
<> 144:ef7eb2e8f9f7 5303 /******************* Bit definition for CAN_F10R2 register ******************/
<> 161:2cc1468da177 5304 #define CAN_F10R2_FB0_Pos (0U)
<> 161:2cc1468da177 5305 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5306 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 5307 #define CAN_F10R2_FB1_Pos (1U)
<> 161:2cc1468da177 5308 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5309 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 5310 #define CAN_F10R2_FB2_Pos (2U)
<> 161:2cc1468da177 5311 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5312 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 5313 #define CAN_F10R2_FB3_Pos (3U)
<> 161:2cc1468da177 5314 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5315 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 5316 #define CAN_F10R2_FB4_Pos (4U)
<> 161:2cc1468da177 5317 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5318 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 5319 #define CAN_F10R2_FB5_Pos (5U)
<> 161:2cc1468da177 5320 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5321 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 5322 #define CAN_F10R2_FB6_Pos (6U)
<> 161:2cc1468da177 5323 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5324 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 5325 #define CAN_F10R2_FB7_Pos (7U)
<> 161:2cc1468da177 5326 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5327 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 5328 #define CAN_F10R2_FB8_Pos (8U)
<> 161:2cc1468da177 5329 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5330 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 5331 #define CAN_F10R2_FB9_Pos (9U)
<> 161:2cc1468da177 5332 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 5333 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 5334 #define CAN_F10R2_FB10_Pos (10U)
<> 161:2cc1468da177 5335 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 5336 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 5337 #define CAN_F10R2_FB11_Pos (11U)
<> 161:2cc1468da177 5338 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 5339 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 5340 #define CAN_F10R2_FB12_Pos (12U)
<> 161:2cc1468da177 5341 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 5342 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 5343 #define CAN_F10R2_FB13_Pos (13U)
<> 161:2cc1468da177 5344 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 5345 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 5346 #define CAN_F10R2_FB14_Pos (14U)
<> 161:2cc1468da177 5347 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 5348 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 5349 #define CAN_F10R2_FB15_Pos (15U)
<> 161:2cc1468da177 5350 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 5351 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 5352 #define CAN_F10R2_FB16_Pos (16U)
<> 161:2cc1468da177 5353 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 5354 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 5355 #define CAN_F10R2_FB17_Pos (17U)
<> 161:2cc1468da177 5356 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 5357 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 5358 #define CAN_F10R2_FB18_Pos (18U)
<> 161:2cc1468da177 5359 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 5360 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 5361 #define CAN_F10R2_FB19_Pos (19U)
<> 161:2cc1468da177 5362 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 5363 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 5364 #define CAN_F10R2_FB20_Pos (20U)
<> 161:2cc1468da177 5365 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 5366 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 5367 #define CAN_F10R2_FB21_Pos (21U)
<> 161:2cc1468da177 5368 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 5369 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 5370 #define CAN_F10R2_FB22_Pos (22U)
<> 161:2cc1468da177 5371 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 5372 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 5373 #define CAN_F10R2_FB23_Pos (23U)
<> 161:2cc1468da177 5374 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 5375 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 5376 #define CAN_F10R2_FB24_Pos (24U)
<> 161:2cc1468da177 5377 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 5378 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 5379 #define CAN_F10R2_FB25_Pos (25U)
<> 161:2cc1468da177 5380 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 5381 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 5382 #define CAN_F10R2_FB26_Pos (26U)
<> 161:2cc1468da177 5383 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 5384 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 5385 #define CAN_F10R2_FB27_Pos (27U)
<> 161:2cc1468da177 5386 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 5387 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 5388 #define CAN_F10R2_FB28_Pos (28U)
<> 161:2cc1468da177 5389 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 5390 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 5391 #define CAN_F10R2_FB29_Pos (29U)
<> 161:2cc1468da177 5392 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 5393 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 5394 #define CAN_F10R2_FB30_Pos (30U)
<> 161:2cc1468da177 5395 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 5396 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 5397 #define CAN_F10R2_FB31_Pos (31U)
<> 161:2cc1468da177 5398 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 5399 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5400
<> 144:ef7eb2e8f9f7 5401 /******************* Bit definition for CAN_F11R2 register ******************/
<> 161:2cc1468da177 5402 #define CAN_F11R2_FB0_Pos (0U)
<> 161:2cc1468da177 5403 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5404 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 5405 #define CAN_F11R2_FB1_Pos (1U)
<> 161:2cc1468da177 5406 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5407 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 5408 #define CAN_F11R2_FB2_Pos (2U)
<> 161:2cc1468da177 5409 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5410 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 5411 #define CAN_F11R2_FB3_Pos (3U)
<> 161:2cc1468da177 5412 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5413 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 5414 #define CAN_F11R2_FB4_Pos (4U)
<> 161:2cc1468da177 5415 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5416 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 5417 #define CAN_F11R2_FB5_Pos (5U)
<> 161:2cc1468da177 5418 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5419 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 5420 #define CAN_F11R2_FB6_Pos (6U)
<> 161:2cc1468da177 5421 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5422 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 5423 #define CAN_F11R2_FB7_Pos (7U)
<> 161:2cc1468da177 5424 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5425 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 5426 #define CAN_F11R2_FB8_Pos (8U)
<> 161:2cc1468da177 5427 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5428 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 5429 #define CAN_F11R2_FB9_Pos (9U)
<> 161:2cc1468da177 5430 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 5431 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 5432 #define CAN_F11R2_FB10_Pos (10U)
<> 161:2cc1468da177 5433 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 5434 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 5435 #define CAN_F11R2_FB11_Pos (11U)
<> 161:2cc1468da177 5436 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 5437 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 5438 #define CAN_F11R2_FB12_Pos (12U)
<> 161:2cc1468da177 5439 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 5440 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 5441 #define CAN_F11R2_FB13_Pos (13U)
<> 161:2cc1468da177 5442 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 5443 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 5444 #define CAN_F11R2_FB14_Pos (14U)
<> 161:2cc1468da177 5445 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 5446 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 5447 #define CAN_F11R2_FB15_Pos (15U)
<> 161:2cc1468da177 5448 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 5449 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 5450 #define CAN_F11R2_FB16_Pos (16U)
<> 161:2cc1468da177 5451 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 5452 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 5453 #define CAN_F11R2_FB17_Pos (17U)
<> 161:2cc1468da177 5454 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 5455 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 5456 #define CAN_F11R2_FB18_Pos (18U)
<> 161:2cc1468da177 5457 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 5458 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 5459 #define CAN_F11R2_FB19_Pos (19U)
<> 161:2cc1468da177 5460 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 5461 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 5462 #define CAN_F11R2_FB20_Pos (20U)
<> 161:2cc1468da177 5463 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 5464 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 5465 #define CAN_F11R2_FB21_Pos (21U)
<> 161:2cc1468da177 5466 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 5467 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 5468 #define CAN_F11R2_FB22_Pos (22U)
<> 161:2cc1468da177 5469 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 5470 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 5471 #define CAN_F11R2_FB23_Pos (23U)
<> 161:2cc1468da177 5472 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 5473 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 5474 #define CAN_F11R2_FB24_Pos (24U)
<> 161:2cc1468da177 5475 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 5476 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 5477 #define CAN_F11R2_FB25_Pos (25U)
<> 161:2cc1468da177 5478 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 5479 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 5480 #define CAN_F11R2_FB26_Pos (26U)
<> 161:2cc1468da177 5481 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 5482 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 5483 #define CAN_F11R2_FB27_Pos (27U)
<> 161:2cc1468da177 5484 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 5485 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 5486 #define CAN_F11R2_FB28_Pos (28U)
<> 161:2cc1468da177 5487 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 5488 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 5489 #define CAN_F11R2_FB29_Pos (29U)
<> 161:2cc1468da177 5490 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 5491 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 5492 #define CAN_F11R2_FB30_Pos (30U)
<> 161:2cc1468da177 5493 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 5494 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 5495 #define CAN_F11R2_FB31_Pos (31U)
<> 161:2cc1468da177 5496 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 5497 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5498
<> 144:ef7eb2e8f9f7 5499 /******************* Bit definition for CAN_F12R2 register ******************/
<> 161:2cc1468da177 5500 #define CAN_F12R2_FB0_Pos (0U)
<> 161:2cc1468da177 5501 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5502 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 5503 #define CAN_F12R2_FB1_Pos (1U)
<> 161:2cc1468da177 5504 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5505 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 5506 #define CAN_F12R2_FB2_Pos (2U)
<> 161:2cc1468da177 5507 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5508 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 5509 #define CAN_F12R2_FB3_Pos (3U)
<> 161:2cc1468da177 5510 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5511 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 5512 #define CAN_F12R2_FB4_Pos (4U)
<> 161:2cc1468da177 5513 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5514 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 5515 #define CAN_F12R2_FB5_Pos (5U)
<> 161:2cc1468da177 5516 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5517 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 5518 #define CAN_F12R2_FB6_Pos (6U)
<> 161:2cc1468da177 5519 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5520 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 5521 #define CAN_F12R2_FB7_Pos (7U)
<> 161:2cc1468da177 5522 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5523 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 5524 #define CAN_F12R2_FB8_Pos (8U)
<> 161:2cc1468da177 5525 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5526 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 5527 #define CAN_F12R2_FB9_Pos (9U)
<> 161:2cc1468da177 5528 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 5529 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 5530 #define CAN_F12R2_FB10_Pos (10U)
<> 161:2cc1468da177 5531 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 5532 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 5533 #define CAN_F12R2_FB11_Pos (11U)
<> 161:2cc1468da177 5534 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 5535 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 5536 #define CAN_F12R2_FB12_Pos (12U)
<> 161:2cc1468da177 5537 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 5538 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 5539 #define CAN_F12R2_FB13_Pos (13U)
<> 161:2cc1468da177 5540 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 5541 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 5542 #define CAN_F12R2_FB14_Pos (14U)
<> 161:2cc1468da177 5543 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 5544 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 5545 #define CAN_F12R2_FB15_Pos (15U)
<> 161:2cc1468da177 5546 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 5547 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 5548 #define CAN_F12R2_FB16_Pos (16U)
<> 161:2cc1468da177 5549 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 5550 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 5551 #define CAN_F12R2_FB17_Pos (17U)
<> 161:2cc1468da177 5552 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 5553 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 5554 #define CAN_F12R2_FB18_Pos (18U)
<> 161:2cc1468da177 5555 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 5556 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 5557 #define CAN_F12R2_FB19_Pos (19U)
<> 161:2cc1468da177 5558 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 5559 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 5560 #define CAN_F12R2_FB20_Pos (20U)
<> 161:2cc1468da177 5561 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 5562 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 5563 #define CAN_F12R2_FB21_Pos (21U)
<> 161:2cc1468da177 5564 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 5565 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 5566 #define CAN_F12R2_FB22_Pos (22U)
<> 161:2cc1468da177 5567 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 5568 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 5569 #define CAN_F12R2_FB23_Pos (23U)
<> 161:2cc1468da177 5570 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 5571 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 5572 #define CAN_F12R2_FB24_Pos (24U)
<> 161:2cc1468da177 5573 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 5574 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 5575 #define CAN_F12R2_FB25_Pos (25U)
<> 161:2cc1468da177 5576 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 5577 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 5578 #define CAN_F12R2_FB26_Pos (26U)
<> 161:2cc1468da177 5579 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 5580 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 5581 #define CAN_F12R2_FB27_Pos (27U)
<> 161:2cc1468da177 5582 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 5583 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 5584 #define CAN_F12R2_FB28_Pos (28U)
<> 161:2cc1468da177 5585 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 5586 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 5587 #define CAN_F12R2_FB29_Pos (29U)
<> 161:2cc1468da177 5588 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 5589 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 5590 #define CAN_F12R2_FB30_Pos (30U)
<> 161:2cc1468da177 5591 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 5592 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 5593 #define CAN_F12R2_FB31_Pos (31U)
<> 161:2cc1468da177 5594 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 5595 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5596
<> 144:ef7eb2e8f9f7 5597 /******************* Bit definition for CAN_F13R2 register ******************/
<> 161:2cc1468da177 5598 #define CAN_F13R2_FB0_Pos (0U)
<> 161:2cc1468da177 5599 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5600 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
<> 161:2cc1468da177 5601 #define CAN_F13R2_FB1_Pos (1U)
<> 161:2cc1468da177 5602 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5603 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
<> 161:2cc1468da177 5604 #define CAN_F13R2_FB2_Pos (2U)
<> 161:2cc1468da177 5605 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5606 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
<> 161:2cc1468da177 5607 #define CAN_F13R2_FB3_Pos (3U)
<> 161:2cc1468da177 5608 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5609 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
<> 161:2cc1468da177 5610 #define CAN_F13R2_FB4_Pos (4U)
<> 161:2cc1468da177 5611 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5612 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
<> 161:2cc1468da177 5613 #define CAN_F13R2_FB5_Pos (5U)
<> 161:2cc1468da177 5614 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5615 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
<> 161:2cc1468da177 5616 #define CAN_F13R2_FB6_Pos (6U)
<> 161:2cc1468da177 5617 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5618 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
<> 161:2cc1468da177 5619 #define CAN_F13R2_FB7_Pos (7U)
<> 161:2cc1468da177 5620 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5621 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
<> 161:2cc1468da177 5622 #define CAN_F13R2_FB8_Pos (8U)
<> 161:2cc1468da177 5623 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5624 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
<> 161:2cc1468da177 5625 #define CAN_F13R2_FB9_Pos (9U)
<> 161:2cc1468da177 5626 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 5627 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
<> 161:2cc1468da177 5628 #define CAN_F13R2_FB10_Pos (10U)
<> 161:2cc1468da177 5629 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 5630 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
<> 161:2cc1468da177 5631 #define CAN_F13R2_FB11_Pos (11U)
<> 161:2cc1468da177 5632 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 5633 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
<> 161:2cc1468da177 5634 #define CAN_F13R2_FB12_Pos (12U)
<> 161:2cc1468da177 5635 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 5636 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
<> 161:2cc1468da177 5637 #define CAN_F13R2_FB13_Pos (13U)
<> 161:2cc1468da177 5638 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 5639 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
<> 161:2cc1468da177 5640 #define CAN_F13R2_FB14_Pos (14U)
<> 161:2cc1468da177 5641 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 5642 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
<> 161:2cc1468da177 5643 #define CAN_F13R2_FB15_Pos (15U)
<> 161:2cc1468da177 5644 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 5645 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
<> 161:2cc1468da177 5646 #define CAN_F13R2_FB16_Pos (16U)
<> 161:2cc1468da177 5647 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 5648 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
<> 161:2cc1468da177 5649 #define CAN_F13R2_FB17_Pos (17U)
<> 161:2cc1468da177 5650 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 5651 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
<> 161:2cc1468da177 5652 #define CAN_F13R2_FB18_Pos (18U)
<> 161:2cc1468da177 5653 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 5654 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
<> 161:2cc1468da177 5655 #define CAN_F13R2_FB19_Pos (19U)
<> 161:2cc1468da177 5656 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 5657 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
<> 161:2cc1468da177 5658 #define CAN_F13R2_FB20_Pos (20U)
<> 161:2cc1468da177 5659 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 5660 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
<> 161:2cc1468da177 5661 #define CAN_F13R2_FB21_Pos (21U)
<> 161:2cc1468da177 5662 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 5663 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
<> 161:2cc1468da177 5664 #define CAN_F13R2_FB22_Pos (22U)
<> 161:2cc1468da177 5665 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 5666 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
<> 161:2cc1468da177 5667 #define CAN_F13R2_FB23_Pos (23U)
<> 161:2cc1468da177 5668 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 5669 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
<> 161:2cc1468da177 5670 #define CAN_F13R2_FB24_Pos (24U)
<> 161:2cc1468da177 5671 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 5672 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
<> 161:2cc1468da177 5673 #define CAN_F13R2_FB25_Pos (25U)
<> 161:2cc1468da177 5674 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 5675 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
<> 161:2cc1468da177 5676 #define CAN_F13R2_FB26_Pos (26U)
<> 161:2cc1468da177 5677 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 5678 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
<> 161:2cc1468da177 5679 #define CAN_F13R2_FB27_Pos (27U)
<> 161:2cc1468da177 5680 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 5681 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
<> 161:2cc1468da177 5682 #define CAN_F13R2_FB28_Pos (28U)
<> 161:2cc1468da177 5683 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 5684 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
<> 161:2cc1468da177 5685 #define CAN_F13R2_FB29_Pos (29U)
<> 161:2cc1468da177 5686 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 5687 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
<> 161:2cc1468da177 5688 #define CAN_F13R2_FB30_Pos (30U)
<> 161:2cc1468da177 5689 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 5690 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
<> 161:2cc1468da177 5691 #define CAN_F13R2_FB31_Pos (31U)
<> 161:2cc1468da177 5692 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 5693 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5694
<> 144:ef7eb2e8f9f7 5695 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5696 /* */
<> 144:ef7eb2e8f9f7 5697 /* HDMI-CEC (CEC) */
<> 144:ef7eb2e8f9f7 5698 /* */
<> 144:ef7eb2e8f9f7 5699 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5700
<> 144:ef7eb2e8f9f7 5701 /******************* Bit definition for CEC_CR register *********************/
<> 161:2cc1468da177 5702 #define CEC_CR_CECEN_Pos (0U)
<> 161:2cc1468da177 5703 #define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5704 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
<> 161:2cc1468da177 5705 #define CEC_CR_TXSOM_Pos (1U)
<> 161:2cc1468da177 5706 #define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5707 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
<> 161:2cc1468da177 5708 #define CEC_CR_TXEOM_Pos (2U)
<> 161:2cc1468da177 5709 #define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5710 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
<> 144:ef7eb2e8f9f7 5711
<> 144:ef7eb2e8f9f7 5712 /******************* Bit definition for CEC_CFGR register *******************/
<> 161:2cc1468da177 5713 #define CEC_CFGR_SFT_Pos (0U)
<> 161:2cc1468da177 5714 #define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 5715 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
<> 161:2cc1468da177 5716 #define CEC_CFGR_RXTOL_Pos (3U)
<> 161:2cc1468da177 5717 #define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5718 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
<> 161:2cc1468da177 5719 #define CEC_CFGR_BRESTP_Pos (4U)
<> 161:2cc1468da177 5720 #define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5721 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
<> 161:2cc1468da177 5722 #define CEC_CFGR_BREGEN_Pos (5U)
<> 161:2cc1468da177 5723 #define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5724 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
<> 161:2cc1468da177 5725 #define CEC_CFGR_LBPEGEN_Pos (6U)
<> 161:2cc1468da177 5726 #define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5727 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Period Error generation */
<> 161:2cc1468da177 5728 #define CEC_CFGR_BRDNOGEN_Pos (7U)
<> 161:2cc1468da177 5729 #define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5730 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast no Error generation */
<> 161:2cc1468da177 5731 #define CEC_CFGR_SFTOPT_Pos (8U)
<> 161:2cc1468da177 5732 #define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5733 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
<> 161:2cc1468da177 5734 #define CEC_CFGR_OAR_Pos (16U)
<> 161:2cc1468da177 5735 #define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
<> 161:2cc1468da177 5736 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
<> 161:2cc1468da177 5737 #define CEC_CFGR_LSTN_Pos (31U)
<> 161:2cc1468da177 5738 #define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 5739 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
<> 144:ef7eb2e8f9f7 5740
<> 144:ef7eb2e8f9f7 5741 /******************* Bit definition for CEC_TXDR register *******************/
<> 161:2cc1468da177 5742 #define CEC_TXDR_TXD_Pos (0U)
<> 161:2cc1468da177 5743 #define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 5744 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
<> 144:ef7eb2e8f9f7 5745
<> 144:ef7eb2e8f9f7 5746 /******************* Bit definition for CEC_RXDR register *******************/
<> 161:2cc1468da177 5747 #define CEC_TXDR_RXD_Pos (0U)
<> 161:2cc1468da177 5748 #define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 5749 #define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
<> 144:ef7eb2e8f9f7 5750
<> 144:ef7eb2e8f9f7 5751 /******************* Bit definition for CEC_ISR register ********************/
<> 161:2cc1468da177 5752 #define CEC_ISR_RXBR_Pos (0U)
<> 161:2cc1468da177 5753 #define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5754 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
<> 161:2cc1468da177 5755 #define CEC_ISR_RXEND_Pos (1U)
<> 161:2cc1468da177 5756 #define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5757 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
<> 161:2cc1468da177 5758 #define CEC_ISR_RXOVR_Pos (2U)
<> 161:2cc1468da177 5759 #define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5760 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
<> 161:2cc1468da177 5761 #define CEC_ISR_BRE_Pos (3U)
<> 161:2cc1468da177 5762 #define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5763 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
<> 161:2cc1468da177 5764 #define CEC_ISR_SBPE_Pos (4U)
<> 161:2cc1468da177 5765 #define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5766 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
<> 161:2cc1468da177 5767 #define CEC_ISR_LBPE_Pos (5U)
<> 161:2cc1468da177 5768 #define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5769 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
<> 161:2cc1468da177 5770 #define CEC_ISR_RXACKE_Pos (6U)
<> 161:2cc1468da177 5771 #define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5772 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
<> 161:2cc1468da177 5773 #define CEC_ISR_ARBLST_Pos (7U)
<> 161:2cc1468da177 5774 #define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5775 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
<> 161:2cc1468da177 5776 #define CEC_ISR_TXBR_Pos (8U)
<> 161:2cc1468da177 5777 #define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5778 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
<> 161:2cc1468da177 5779 #define CEC_ISR_TXEND_Pos (9U)
<> 161:2cc1468da177 5780 #define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 5781 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
<> 161:2cc1468da177 5782 #define CEC_ISR_TXUDR_Pos (10U)
<> 161:2cc1468da177 5783 #define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 5784 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
<> 161:2cc1468da177 5785 #define CEC_ISR_TXERR_Pos (11U)
<> 161:2cc1468da177 5786 #define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 5787 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
<> 161:2cc1468da177 5788 #define CEC_ISR_TXACKE_Pos (12U)
<> 161:2cc1468da177 5789 #define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 5790 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
<> 144:ef7eb2e8f9f7 5791
<> 144:ef7eb2e8f9f7 5792 /******************* Bit definition for CEC_IER register ********************/
<> 161:2cc1468da177 5793 #define CEC_IER_RXBRIE_Pos (0U)
<> 161:2cc1468da177 5794 #define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5795 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
<> 161:2cc1468da177 5796 #define CEC_IER_RXENDIE_Pos (1U)
<> 161:2cc1468da177 5797 #define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5798 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
<> 161:2cc1468da177 5799 #define CEC_IER_RXOVRIE_Pos (2U)
<> 161:2cc1468da177 5800 #define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5801 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
<> 161:2cc1468da177 5802 #define CEC_IER_BREIE_Pos (3U)
<> 161:2cc1468da177 5803 #define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5804 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
<> 161:2cc1468da177 5805 #define CEC_IER_SBPEIE_Pos (4U)
<> 161:2cc1468da177 5806 #define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5807 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
<> 161:2cc1468da177 5808 #define CEC_IER_LBPEIE_Pos (5U)
<> 161:2cc1468da177 5809 #define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5810 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
<> 161:2cc1468da177 5811 #define CEC_IER_RXACKEIE_Pos (6U)
<> 161:2cc1468da177 5812 #define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5813 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
<> 161:2cc1468da177 5814 #define CEC_IER_ARBLSTIE_Pos (7U)
<> 161:2cc1468da177 5815 #define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5816 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
<> 161:2cc1468da177 5817 #define CEC_IER_TXBRIE_Pos (8U)
<> 161:2cc1468da177 5818 #define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5819 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
<> 161:2cc1468da177 5820 #define CEC_IER_TXENDIE_Pos (9U)
<> 161:2cc1468da177 5821 #define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 5822 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
<> 161:2cc1468da177 5823 #define CEC_IER_TXUDRIE_Pos (10U)
<> 161:2cc1468da177 5824 #define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 5825 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
<> 161:2cc1468da177 5826 #define CEC_IER_TXERRIE_Pos (11U)
<> 161:2cc1468da177 5827 #define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 5828 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
<> 161:2cc1468da177 5829 #define CEC_IER_TXACKEIE_Pos (12U)
<> 161:2cc1468da177 5830 #define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 5831 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
<> 144:ef7eb2e8f9f7 5832
<> 144:ef7eb2e8f9f7 5833 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5834 /* */
<> 144:ef7eb2e8f9f7 5835 /* CRC calculation unit */
<> 144:ef7eb2e8f9f7 5836 /* */
<> 144:ef7eb2e8f9f7 5837 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5838 /******************* Bit definition for CRC_DR register *********************/
<> 161:2cc1468da177 5839 #define CRC_DR_DR_Pos (0U)
<> 161:2cc1468da177 5840 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 5841 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
<> 144:ef7eb2e8f9f7 5842
<> 144:ef7eb2e8f9f7 5843 /******************* Bit definition for CRC_IDR register ********************/
<> 161:2cc1468da177 5844 #define CRC_IDR_IDR_Pos (0U)
<> 161:2cc1468da177 5845 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 5846 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
<> 144:ef7eb2e8f9f7 5847
<> 144:ef7eb2e8f9f7 5848 /******************** Bit definition for CRC_CR register ********************/
<> 161:2cc1468da177 5849 #define CRC_CR_RESET_Pos (0U)
<> 161:2cc1468da177 5850 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5851 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
<> 161:2cc1468da177 5852 #define CRC_CR_POLYSIZE_Pos (3U)
<> 161:2cc1468da177 5853 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
<> 161:2cc1468da177 5854 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
<> 161:2cc1468da177 5855 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5856 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5857 #define CRC_CR_REV_IN_Pos (5U)
<> 161:2cc1468da177 5858 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
<> 161:2cc1468da177 5859 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
<> 161:2cc1468da177 5860 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5861 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5862 #define CRC_CR_REV_OUT_Pos (7U)
<> 161:2cc1468da177 5863 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5864 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
<> 144:ef7eb2e8f9f7 5865
<> 144:ef7eb2e8f9f7 5866 /******************* Bit definition for CRC_INIT register *******************/
<> 161:2cc1468da177 5867 #define CRC_INIT_INIT_Pos (0U)
<> 161:2cc1468da177 5868 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 5869 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
<> 144:ef7eb2e8f9f7 5870
<> 144:ef7eb2e8f9f7 5871 /******************* Bit definition for CRC_POL register ********************/
<> 161:2cc1468da177 5872 #define CRC_POL_POL_Pos (0U)
<> 161:2cc1468da177 5873 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 5874 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
<> 144:ef7eb2e8f9f7 5875
<> 144:ef7eb2e8f9f7 5876
<> 144:ef7eb2e8f9f7 5877 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5878 /* */
<> 144:ef7eb2e8f9f7 5879 /* Digital to Analog Converter */
<> 144:ef7eb2e8f9f7 5880 /* */
<> 144:ef7eb2e8f9f7 5881 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5882 /******************** Bit definition for DAC_CR register ********************/
<> 161:2cc1468da177 5883 #define DAC_CR_EN1_Pos (0U)
<> 161:2cc1468da177 5884 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5885 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
<> 161:2cc1468da177 5886 #define DAC_CR_BOFF1_Pos (1U)
<> 161:2cc1468da177 5887 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5888 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
<> 161:2cc1468da177 5889 #define DAC_CR_TEN1_Pos (2U)
<> 161:2cc1468da177 5890 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 5891 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
<> 161:2cc1468da177 5892 #define DAC_CR_TSEL1_Pos (3U)
<> 161:2cc1468da177 5893 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
<> 161:2cc1468da177 5894 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 161:2cc1468da177 5895 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 5896 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 5897 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 5898 #define DAC_CR_WAVE1_Pos (6U)
<> 161:2cc1468da177 5899 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 5900 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
<> 161:2cc1468da177 5901 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 5902 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 5903 #define DAC_CR_MAMP1_Pos (8U)
<> 161:2cc1468da177 5904 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 5905 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 161:2cc1468da177 5906 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 5907 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 5908 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 5909 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 5910 #define DAC_CR_DMAEN1_Pos (12U)
<> 161:2cc1468da177 5911 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 5912 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
<> 161:2cc1468da177 5913 #define DAC_CR_DMAUDRIE1_Pos (13U)
<> 161:2cc1468da177 5914 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 5915 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable */
<> 161:2cc1468da177 5916 #define DAC_CR_EN2_Pos (16U)
<> 161:2cc1468da177 5917 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 5918 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
<> 161:2cc1468da177 5919 #define DAC_CR_BOFF2_Pos (17U)
<> 161:2cc1468da177 5920 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 5921 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
<> 161:2cc1468da177 5922 #define DAC_CR_TEN2_Pos (18U)
<> 161:2cc1468da177 5923 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 5924 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
<> 161:2cc1468da177 5925 #define DAC_CR_TSEL2_Pos (19U)
<> 161:2cc1468da177 5926 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
<> 161:2cc1468da177 5927 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 161:2cc1468da177 5928 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 5929 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 5930 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 5931 #define DAC_CR_WAVE2_Pos (22U)
<> 161:2cc1468da177 5932 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
<> 161:2cc1468da177 5933 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 161:2cc1468da177 5934 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 5935 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 5936 #define DAC_CR_MAMP2_Pos (24U)
<> 161:2cc1468da177 5937 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 5938 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 161:2cc1468da177 5939 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 5940 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 5941 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 5942 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 5943 #define DAC_CR_DMAEN2_Pos (28U)
<> 161:2cc1468da177 5944 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 5945 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enable */
<> 161:2cc1468da177 5946 #define DAC_CR_DMAUDRIE2_Pos (29U)
<> 161:2cc1468da177 5947 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 5948 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */
<> 144:ef7eb2e8f9f7 5949
<> 144:ef7eb2e8f9f7 5950 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 161:2cc1468da177 5951 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
<> 161:2cc1468da177 5952 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 5953 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
<> 161:2cc1468da177 5954 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
<> 161:2cc1468da177 5955 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 5956 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
<> 144:ef7eb2e8f9f7 5957
<> 144:ef7eb2e8f9f7 5958 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 161:2cc1468da177 5959 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
<> 161:2cc1468da177 5960 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 5961 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5962
<> 144:ef7eb2e8f9f7 5963 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 161:2cc1468da177 5964 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
<> 161:2cc1468da177 5965 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 161:2cc1468da177 5966 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 5967
<> 144:ef7eb2e8f9f7 5968 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 161:2cc1468da177 5969 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
<> 161:2cc1468da177 5970 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 5971 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5972
<> 144:ef7eb2e8f9f7 5973 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 161:2cc1468da177 5974 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
<> 161:2cc1468da177 5975 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 5976 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5977
<> 144:ef7eb2e8f9f7 5978 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 161:2cc1468da177 5979 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
<> 161:2cc1468da177 5980 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
<> 161:2cc1468da177 5981 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 5982
<> 144:ef7eb2e8f9f7 5983 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 161:2cc1468da177 5984 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
<> 161:2cc1468da177 5985 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 5986 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5987
<> 144:ef7eb2e8f9f7 5988 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 161:2cc1468da177 5989 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
<> 161:2cc1468da177 5990 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 5991 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
<> 161:2cc1468da177 5992 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
<> 161:2cc1468da177 5993 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
<> 161:2cc1468da177 5994 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5995
<> 144:ef7eb2e8f9f7 5996 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 161:2cc1468da177 5997 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
<> 161:2cc1468da177 5998 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 161:2cc1468da177 5999 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
<> 161:2cc1468da177 6000 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
<> 161:2cc1468da177 6001 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
<> 161:2cc1468da177 6002 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 6003
<> 144:ef7eb2e8f9f7 6004 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 161:2cc1468da177 6005 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
<> 161:2cc1468da177 6006 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 6007 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
<> 161:2cc1468da177 6008 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
<> 161:2cc1468da177 6009 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 6010 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 6011
<> 144:ef7eb2e8f9f7 6012 /******************* Bit definition for DAC_DOR1 register *******************/
<> 161:2cc1468da177 6013 #define DAC_DOR1_DACC1DOR_Pos (0U)
<> 161:2cc1468da177 6014 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 6015 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
<> 144:ef7eb2e8f9f7 6016
<> 144:ef7eb2e8f9f7 6017 /******************* Bit definition for DAC_DOR2 register *******************/
<> 161:2cc1468da177 6018 #define DAC_DOR2_DACC2DOR_Pos (0U)
<> 161:2cc1468da177 6019 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 6020 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
<> 144:ef7eb2e8f9f7 6021
<> 144:ef7eb2e8f9f7 6022 /******************** Bit definition for DAC_SR register ********************/
<> 161:2cc1468da177 6023 #define DAC_SR_DMAUDR1_Pos (13U)
<> 161:2cc1468da177 6024 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 6025 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
<> 161:2cc1468da177 6026 #define DAC_SR_DMAUDR2_Pos (29U)
<> 161:2cc1468da177 6027 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 6028 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
<> 144:ef7eb2e8f9f7 6029
<> 144:ef7eb2e8f9f7 6030 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6031 /* */
<> 144:ef7eb2e8f9f7 6032 /* Digital Filter for Sigma Delta Modulators */
<> 144:ef7eb2e8f9f7 6033 /* */
<> 144:ef7eb2e8f9f7 6034 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6035
<> 144:ef7eb2e8f9f7 6036 /**************** DFSDM channel configuration registers ********************/
<> 144:ef7eb2e8f9f7 6037
<> 144:ef7eb2e8f9f7 6038 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
<> 161:2cc1468da177 6039 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
<> 161:2cc1468da177 6040 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 6041 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
<> 161:2cc1468da177 6042 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
<> 161:2cc1468da177 6043 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 6044 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
<> 161:2cc1468da177 6045 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
<> 161:2cc1468da177 6046 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 6047 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
<> 161:2cc1468da177 6048 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
<> 161:2cc1468da177 6049 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 6050 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
<> 161:2cc1468da177 6051 #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 6052 #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 6053 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
<> 161:2cc1468da177 6054 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
<> 161:2cc1468da177 6055 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
<> 161:2cc1468da177 6056 #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 6057 #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 6058 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
<> 161:2cc1468da177 6059 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 6060 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
<> 161:2cc1468da177 6061 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
<> 161:2cc1468da177 6062 #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 6063 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
<> 161:2cc1468da177 6064 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
<> 161:2cc1468da177 6065 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 6066 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
<> 161:2cc1468da177 6067 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
<> 161:2cc1468da177 6068 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6069 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
<> 161:2cc1468da177 6070 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
<> 161:2cc1468da177 6071 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 6072 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
<> 161:2cc1468da177 6073 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6074 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6075 #define DFSDM_CHCFGR1_SITP_Pos (0U)
<> 161:2cc1468da177 6076 #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 6077 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
<> 161:2cc1468da177 6078 #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6079 #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
<> 144:ef7eb2e8f9f7 6080
<> 144:ef7eb2e8f9f7 6081 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
<> 161:2cc1468da177 6082 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
<> 161:2cc1468da177 6083 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
<> 161:2cc1468da177 6084 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
<> 161:2cc1468da177 6085 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
<> 161:2cc1468da177 6086 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
<> 161:2cc1468da177 6087 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
<> 144:ef7eb2e8f9f7 6088
<> 144:ef7eb2e8f9f7 6089 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
<> 161:2cc1468da177 6090 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
<> 161:2cc1468da177 6091 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
<> 161:2cc1468da177 6092 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
<> 161:2cc1468da177 6093 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 6094 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 6095 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
<> 161:2cc1468da177 6096 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
<> 161:2cc1468da177 6097 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
<> 161:2cc1468da177 6098 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
<> 161:2cc1468da177 6099 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 6100 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
<> 161:2cc1468da177 6101 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
<> 161:2cc1468da177 6102 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 6103 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
<> 144:ef7eb2e8f9f7 6104
<> 144:ef7eb2e8f9f7 6105 /**************** Bit definition for DFSDM_CHWDATR register *******************/
<> 161:2cc1468da177 6106 #define DFSDM_CHWDATR_WDATA_Pos (0U)
<> 161:2cc1468da177 6107 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 6108 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
<> 144:ef7eb2e8f9f7 6109
<> 144:ef7eb2e8f9f7 6110 /**************** Bit definition for DFSDM_CHDATINR register *****************/
<> 161:2cc1468da177 6111 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
<> 161:2cc1468da177 6112 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 6113 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
<> 161:2cc1468da177 6114 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
<> 161:2cc1468da177 6115 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 6116 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
<> 144:ef7eb2e8f9f7 6117
<> 144:ef7eb2e8f9f7 6118 /************************ DFSDM module registers ****************************/
<> 144:ef7eb2e8f9f7 6119
<> 144:ef7eb2e8f9f7 6120 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
<> 161:2cc1468da177 6121 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
<> 161:2cc1468da177 6122 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 6123 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
<> 161:2cc1468da177 6124 #define DFSDM_FLTCR1_FAST_Pos (29U)
<> 161:2cc1468da177 6125 #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 6126 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
<> 161:2cc1468da177 6127 #define DFSDM_FLTCR1_RCH_Pos (24U)
<> 161:2cc1468da177 6128 #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
<> 161:2cc1468da177 6129 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
<> 161:2cc1468da177 6130 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
<> 161:2cc1468da177 6131 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 6132 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
<> 161:2cc1468da177 6133 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
<> 161:2cc1468da177 6134 #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 6135 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
<> 161:2cc1468da177 6136 #define DFSDM_FLTCR1_RCONT_Pos (18U)
<> 161:2cc1468da177 6137 #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 6138 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
<> 161:2cc1468da177 6139 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
<> 161:2cc1468da177 6140 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 6141 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
<> 161:2cc1468da177 6142 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
<> 161:2cc1468da177 6143 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
<> 161:2cc1468da177 6144 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
<> 161:2cc1468da177 6145 #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 6146 #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 6147 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
<> 161:2cc1468da177 6148 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FU << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
<> 161:2cc1468da177 6149 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
<> 161:2cc1468da177 6150 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 6151 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 6152 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 6153 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 6154 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 6155 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
<> 161:2cc1468da177 6156 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6157 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
<> 161:2cc1468da177 6158 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
<> 161:2cc1468da177 6159 #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6160 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
<> 161:2cc1468da177 6161 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
<> 161:2cc1468da177 6162 #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6163 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
<> 161:2cc1468da177 6164 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
<> 161:2cc1468da177 6165 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6166 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
<> 161:2cc1468da177 6167 #define DFSDM_FLTCR1_DFEN_Pos (0U)
<> 161:2cc1468da177 6168 #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6169 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
<> 144:ef7eb2e8f9f7 6170
<> 144:ef7eb2e8f9f7 6171 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
<> 161:2cc1468da177 6172 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
<> 161:2cc1468da177 6173 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 6174 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
<> 161:2cc1468da177 6175 #define DFSDM_FLTCR2_EXCH_Pos (8U)
<> 161:2cc1468da177 6176 #define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 6177 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
<> 161:2cc1468da177 6178 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
<> 161:2cc1468da177 6179 #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 6180 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
<> 161:2cc1468da177 6181 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
<> 161:2cc1468da177 6182 #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6183 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
<> 161:2cc1468da177 6184 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
<> 161:2cc1468da177 6185 #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6186 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
<> 161:2cc1468da177 6187 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
<> 161:2cc1468da177 6188 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6189 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
<> 161:2cc1468da177 6190 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
<> 161:2cc1468da177 6191 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6192 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
<> 161:2cc1468da177 6193 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
<> 161:2cc1468da177 6194 #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6195 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
<> 161:2cc1468da177 6196 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
<> 161:2cc1468da177 6197 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6198 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
<> 144:ef7eb2e8f9f7 6199
<> 144:ef7eb2e8f9f7 6200 /******************** Bit definition for DFSDM_FLTISR register *******************/
<> 161:2cc1468da177 6201 #define DFSDM_FLTISR_SCDF_Pos (24U)
<> 161:2cc1468da177 6202 #define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 6203 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
<> 161:2cc1468da177 6204 #define DFSDM_FLTISR_CKABF_Pos (16U)
<> 161:2cc1468da177 6205 #define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 6206 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
<> 161:2cc1468da177 6207 #define DFSDM_FLTISR_RCIP_Pos (14U)
<> 161:2cc1468da177 6208 #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 6209 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
<> 161:2cc1468da177 6210 #define DFSDM_FLTISR_JCIP_Pos (13U)
<> 161:2cc1468da177 6211 #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 6212 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
<> 161:2cc1468da177 6213 #define DFSDM_FLTISR_AWDF_Pos (4U)
<> 161:2cc1468da177 6214 #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6215 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
<> 161:2cc1468da177 6216 #define DFSDM_FLTISR_ROVRF_Pos (3U)
<> 161:2cc1468da177 6217 #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6218 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
<> 161:2cc1468da177 6219 #define DFSDM_FLTISR_JOVRF_Pos (2U)
<> 161:2cc1468da177 6220 #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6221 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
<> 161:2cc1468da177 6222 #define DFSDM_FLTISR_REOCF_Pos (1U)
<> 161:2cc1468da177 6223 #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6224 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
<> 161:2cc1468da177 6225 #define DFSDM_FLTISR_JEOCF_Pos (0U)
<> 161:2cc1468da177 6226 #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6227 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
<> 144:ef7eb2e8f9f7 6228
<> 144:ef7eb2e8f9f7 6229 /******************** Bit definition for DFSDM_FLTICR register *******************/
<> 161:2cc1468da177 6230 #define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
<> 161:2cc1468da177 6231 #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 6232 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
<> 161:2cc1468da177 6233 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
<> 161:2cc1468da177 6234 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 6235 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
<> 161:2cc1468da177 6236 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
<> 161:2cc1468da177 6237 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6238 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
<> 161:2cc1468da177 6239 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
<> 161:2cc1468da177 6240 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6241 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
<> 144:ef7eb2e8f9f7 6242
<> 144:ef7eb2e8f9f7 6243 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
<> 161:2cc1468da177 6244 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
<> 161:2cc1468da177 6245 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 6246 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
<> 144:ef7eb2e8f9f7 6247
<> 144:ef7eb2e8f9f7 6248 /******************** Bit definition for DFSDM_FLTFCR register *******************/
<> 161:2cc1468da177 6249 #define DFSDM_FLTFCR_FORD_Pos (29U)
<> 161:2cc1468da177 6250 #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
<> 161:2cc1468da177 6251 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
<> 161:2cc1468da177 6252 #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 6253 #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 6254 #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 6255 #define DFSDM_FLTFCR_FOSR_Pos (16U)
<> 161:2cc1468da177 6256 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
<> 161:2cc1468da177 6257 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
<> 161:2cc1468da177 6258 #define DFSDM_FLTFCR_IOSR_Pos (0U)
<> 161:2cc1468da177 6259 #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 6260 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
<> 144:ef7eb2e8f9f7 6261
<> 144:ef7eb2e8f9f7 6262 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
<> 161:2cc1468da177 6263 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
<> 161:2cc1468da177 6264 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
<> 161:2cc1468da177 6265 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
<> 161:2cc1468da177 6266 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
<> 161:2cc1468da177 6267 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 6268 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
<> 144:ef7eb2e8f9f7 6269
<> 144:ef7eb2e8f9f7 6270 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
<> 161:2cc1468da177 6271 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
<> 161:2cc1468da177 6272 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
<> 161:2cc1468da177 6273 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
<> 161:2cc1468da177 6274 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
<> 161:2cc1468da177 6275 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6276 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
<> 161:2cc1468da177 6277 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
<> 161:2cc1468da177 6278 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 6279 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
<> 144:ef7eb2e8f9f7 6280
<> 144:ef7eb2e8f9f7 6281 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
<> 161:2cc1468da177 6282 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
<> 161:2cc1468da177 6283 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
<> 161:2cc1468da177 6284 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
<> 161:2cc1468da177 6285 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
<> 161:2cc1468da177 6286 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 6287 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
<> 144:ef7eb2e8f9f7 6288
<> 144:ef7eb2e8f9f7 6289 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
<> 161:2cc1468da177 6290 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
<> 161:2cc1468da177 6291 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
<> 161:2cc1468da177 6292 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
<> 161:2cc1468da177 6293 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
<> 161:2cc1468da177 6294 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 6295 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
<> 144:ef7eb2e8f9f7 6296
<> 144:ef7eb2e8f9f7 6297 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
<> 161:2cc1468da177 6298 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
<> 161:2cc1468da177 6299 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 6300 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
<> 161:2cc1468da177 6301 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
<> 161:2cc1468da177 6302 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 6303 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
<> 144:ef7eb2e8f9f7 6304
<> 144:ef7eb2e8f9f7 6305 /****************** Bit definition for DFSDM_FLTAWCFR register *****************/
<> 161:2cc1468da177 6306 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
<> 161:2cc1468da177 6307 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 6308 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
<> 161:2cc1468da177 6309 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
<> 161:2cc1468da177 6310 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 6311 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
<> 144:ef7eb2e8f9f7 6312
<> 144:ef7eb2e8f9f7 6313 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
<> 161:2cc1468da177 6314 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
<> 161:2cc1468da177 6315 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
<> 161:2cc1468da177 6316 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
<> 161:2cc1468da177 6317 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
<> 161:2cc1468da177 6318 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 6319 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
<> 144:ef7eb2e8f9f7 6320
<> 144:ef7eb2e8f9f7 6321 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
<> 161:2cc1468da177 6322 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
<> 161:2cc1468da177 6323 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
<> 161:2cc1468da177 6324 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
<> 161:2cc1468da177 6325 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
<> 161:2cc1468da177 6326 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 6327 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
<> 144:ef7eb2e8f9f7 6328
<> 144:ef7eb2e8f9f7 6329 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
<> 161:2cc1468da177 6330 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
<> 161:2cc1468da177 6331 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
<> 161:2cc1468da177 6332 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
<> 144:ef7eb2e8f9f7 6333
<> 144:ef7eb2e8f9f7 6334 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6335 /* */
<> 144:ef7eb2e8f9f7 6336 /* Debug MCU */
<> 144:ef7eb2e8f9f7 6337 /* */
<> 144:ef7eb2e8f9f7 6338 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6339
<> 144:ef7eb2e8f9f7 6340 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6341 /* */
<> 144:ef7eb2e8f9f7 6342 /* DCMI */
<> 144:ef7eb2e8f9f7 6343 /* */
<> 144:ef7eb2e8f9f7 6344 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6345 /******************** Bits definition for DCMI_CR register ******************/
<> 161:2cc1468da177 6346 #define DCMI_CR_CAPTURE_Pos (0U)
<> 161:2cc1468da177 6347 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6348 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
<> 161:2cc1468da177 6349 #define DCMI_CR_CM_Pos (1U)
<> 161:2cc1468da177 6350 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6351 #define DCMI_CR_CM DCMI_CR_CM_Msk
<> 161:2cc1468da177 6352 #define DCMI_CR_CROP_Pos (2U)
<> 161:2cc1468da177 6353 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6354 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
<> 161:2cc1468da177 6355 #define DCMI_CR_JPEG_Pos (3U)
<> 161:2cc1468da177 6356 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6357 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
<> 161:2cc1468da177 6358 #define DCMI_CR_ESS_Pos (4U)
<> 161:2cc1468da177 6359 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6360 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
<> 161:2cc1468da177 6361 #define DCMI_CR_PCKPOL_Pos (5U)
<> 161:2cc1468da177 6362 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6363 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
<> 161:2cc1468da177 6364 #define DCMI_CR_HSPOL_Pos (6U)
<> 161:2cc1468da177 6365 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 6366 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
<> 161:2cc1468da177 6367 #define DCMI_CR_VSPOL_Pos (7U)
<> 161:2cc1468da177 6368 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 6369 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
<> 161:2cc1468da177 6370 #define DCMI_CR_FCRC_0 0x00000100U
<> 161:2cc1468da177 6371 #define DCMI_CR_FCRC_1 0x00000200U
<> 161:2cc1468da177 6372 #define DCMI_CR_EDM_0 0x00000400U
<> 161:2cc1468da177 6373 #define DCMI_CR_EDM_1 0x00000800U
<> 161:2cc1468da177 6374 #define DCMI_CR_CRE_Pos (12U)
<> 161:2cc1468da177 6375 #define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 6376 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
<> 161:2cc1468da177 6377 #define DCMI_CR_ENABLE_Pos (14U)
<> 161:2cc1468da177 6378 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 6379 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
<> 161:2cc1468da177 6380 #define DCMI_CR_BSM_Pos (16U)
<> 161:2cc1468da177 6381 #define DCMI_CR_BSM_Msk (0x3U << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 6382 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
<> 161:2cc1468da177 6383 #define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 6384 #define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 6385 #define DCMI_CR_OEBS_Pos (18U)
<> 161:2cc1468da177 6386 #define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 6387 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
<> 161:2cc1468da177 6388 #define DCMI_CR_LSM_Pos (19U)
<> 161:2cc1468da177 6389 #define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 6390 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
<> 161:2cc1468da177 6391 #define DCMI_CR_OELS_Pos (20U)
<> 161:2cc1468da177 6392 #define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 6393 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
<> 144:ef7eb2e8f9f7 6394
<> 144:ef7eb2e8f9f7 6395 /******************** Bits definition for DCMI_SR register ******************/
<> 161:2cc1468da177 6396 #define DCMI_SR_HSYNC_Pos (0U)
<> 161:2cc1468da177 6397 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6398 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
<> 161:2cc1468da177 6399 #define DCMI_SR_VSYNC_Pos (1U)
<> 161:2cc1468da177 6400 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6401 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
<> 161:2cc1468da177 6402 #define DCMI_SR_FNE_Pos (2U)
<> 161:2cc1468da177 6403 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6404 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
<> 144:ef7eb2e8f9f7 6405
<> 144:ef7eb2e8f9f7 6406 /******************** Bits definition for DCMI_RIS register ****************/
<> 161:2cc1468da177 6407 #define DCMI_RIS_FRAME_RIS_Pos (0U)
<> 161:2cc1468da177 6408 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6409 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
<> 161:2cc1468da177 6410 #define DCMI_RIS_OVR_RIS_Pos (1U)
<> 161:2cc1468da177 6411 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6412 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
<> 161:2cc1468da177 6413 #define DCMI_RIS_ERR_RIS_Pos (2U)
<> 161:2cc1468da177 6414 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6415 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
<> 161:2cc1468da177 6416 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
<> 161:2cc1468da177 6417 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6418 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
<> 161:2cc1468da177 6419 #define DCMI_RIS_LINE_RIS_Pos (4U)
<> 161:2cc1468da177 6420 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6421 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
<> 144:ef7eb2e8f9f7 6422
<> 144:ef7eb2e8f9f7 6423 /* Legacy defines */
<> 144:ef7eb2e8f9f7 6424 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
<> 144:ef7eb2e8f9f7 6425 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
<> 144:ef7eb2e8f9f7 6426 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
<> 144:ef7eb2e8f9f7 6427 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
<> 144:ef7eb2e8f9f7 6428 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
<> 144:ef7eb2e8f9f7 6429
<> 144:ef7eb2e8f9f7 6430 /******************** Bits definition for DCMI_IER register *****************/
<> 161:2cc1468da177 6431 #define DCMI_IER_FRAME_IE_Pos (0U)
<> 161:2cc1468da177 6432 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6433 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
<> 161:2cc1468da177 6434 #define DCMI_IER_OVR_IE_Pos (1U)
<> 161:2cc1468da177 6435 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6436 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
<> 161:2cc1468da177 6437 #define DCMI_IER_ERR_IE_Pos (2U)
<> 161:2cc1468da177 6438 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6439 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
<> 161:2cc1468da177 6440 #define DCMI_IER_VSYNC_IE_Pos (3U)
<> 161:2cc1468da177 6441 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6442 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
<> 161:2cc1468da177 6443 #define DCMI_IER_LINE_IE_Pos (4U)
<> 161:2cc1468da177 6444 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6445 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
<> 144:ef7eb2e8f9f7 6446
<> 144:ef7eb2e8f9f7 6447
<> 144:ef7eb2e8f9f7 6448 /******************** Bits definition for DCMI_MIS register *****************/
<> 161:2cc1468da177 6449 #define DCMI_MIS_FRAME_MIS_Pos (0U)
<> 161:2cc1468da177 6450 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6451 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
<> 161:2cc1468da177 6452 #define DCMI_MIS_OVR_MIS_Pos (1U)
<> 161:2cc1468da177 6453 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6454 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
<> 161:2cc1468da177 6455 #define DCMI_MIS_ERR_MIS_Pos (2U)
<> 161:2cc1468da177 6456 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6457 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
<> 161:2cc1468da177 6458 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
<> 161:2cc1468da177 6459 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6460 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
<> 161:2cc1468da177 6461 #define DCMI_MIS_LINE_MIS_Pos (4U)
<> 161:2cc1468da177 6462 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6463 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
<> 144:ef7eb2e8f9f7 6464
<> 144:ef7eb2e8f9f7 6465
<> 144:ef7eb2e8f9f7 6466 /******************** Bits definition for DCMI_ICR register *****************/
<> 161:2cc1468da177 6467 #define DCMI_ICR_FRAME_ISC_Pos (0U)
<> 161:2cc1468da177 6468 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6469 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
<> 161:2cc1468da177 6470 #define DCMI_ICR_OVR_ISC_Pos (1U)
<> 161:2cc1468da177 6471 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6472 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
<> 161:2cc1468da177 6473 #define DCMI_ICR_ERR_ISC_Pos (2U)
<> 161:2cc1468da177 6474 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6475 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
<> 161:2cc1468da177 6476 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
<> 161:2cc1468da177 6477 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6478 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
<> 161:2cc1468da177 6479 #define DCMI_ICR_LINE_ISC_Pos (4U)
<> 161:2cc1468da177 6480 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6481 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
<> 144:ef7eb2e8f9f7 6482
<> 144:ef7eb2e8f9f7 6483
<> 144:ef7eb2e8f9f7 6484 /******************** Bits definition for DCMI_ESCR register ******************/
<> 161:2cc1468da177 6485 #define DCMI_ESCR_FSC_Pos (0U)
<> 161:2cc1468da177 6486 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 6487 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
<> 161:2cc1468da177 6488 #define DCMI_ESCR_LSC_Pos (8U)
<> 161:2cc1468da177 6489 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 6490 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
<> 161:2cc1468da177 6491 #define DCMI_ESCR_LEC_Pos (16U)
<> 161:2cc1468da177 6492 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 6493 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
<> 161:2cc1468da177 6494 #define DCMI_ESCR_FEC_Pos (24U)
<> 161:2cc1468da177 6495 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 6496 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
<> 144:ef7eb2e8f9f7 6497
<> 144:ef7eb2e8f9f7 6498 /******************** Bits definition for DCMI_ESUR register ******************/
<> 161:2cc1468da177 6499 #define DCMI_ESUR_FSU_Pos (0U)
<> 161:2cc1468da177 6500 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 6501 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
<> 161:2cc1468da177 6502 #define DCMI_ESUR_LSU_Pos (8U)
<> 161:2cc1468da177 6503 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 6504 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
<> 161:2cc1468da177 6505 #define DCMI_ESUR_LEU_Pos (16U)
<> 161:2cc1468da177 6506 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 6507 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
<> 161:2cc1468da177 6508 #define DCMI_ESUR_FEU_Pos (24U)
<> 161:2cc1468da177 6509 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 6510 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
<> 144:ef7eb2e8f9f7 6511
<> 144:ef7eb2e8f9f7 6512 /******************** Bits definition for DCMI_CWSTRT register ******************/
<> 161:2cc1468da177 6513 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
<> 161:2cc1468da177 6514 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
<> 161:2cc1468da177 6515 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
<> 161:2cc1468da177 6516 #define DCMI_CWSTRT_VST_Pos (16U)
<> 161:2cc1468da177 6517 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
<> 161:2cc1468da177 6518 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
<> 144:ef7eb2e8f9f7 6519
<> 144:ef7eb2e8f9f7 6520 /******************** Bits definition for DCMI_CWSIZE register ******************/
<> 161:2cc1468da177 6521 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
<> 161:2cc1468da177 6522 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
<> 161:2cc1468da177 6523 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
<> 161:2cc1468da177 6524 #define DCMI_CWSIZE_VLINE_Pos (16U)
<> 161:2cc1468da177 6525 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
<> 161:2cc1468da177 6526 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
<> 144:ef7eb2e8f9f7 6527
<> 144:ef7eb2e8f9f7 6528 /******************** Bits definition for DCMI_DR register ******************/
<> 161:2cc1468da177 6529 #define DCMI_DR_BYTE0_Pos (0U)
<> 161:2cc1468da177 6530 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 6531 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
<> 161:2cc1468da177 6532 #define DCMI_DR_BYTE1_Pos (8U)
<> 161:2cc1468da177 6533 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 6534 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
<> 161:2cc1468da177 6535 #define DCMI_DR_BYTE2_Pos (16U)
<> 161:2cc1468da177 6536 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 6537 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
<> 161:2cc1468da177 6538 #define DCMI_DR_BYTE3_Pos (24U)
<> 161:2cc1468da177 6539 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 6540 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
<> 144:ef7eb2e8f9f7 6541
<> 144:ef7eb2e8f9f7 6542 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6543 /* */
<> 144:ef7eb2e8f9f7 6544 /* DMA Controller */
<> 144:ef7eb2e8f9f7 6545 /* */
<> 144:ef7eb2e8f9f7 6546 /******************************************************************************/
<> 161:2cc1468da177 6547 /******************** Bits definition for DMA_SxCR register *****************/
<> 161:2cc1468da177 6548 #define DMA_SxCR_CHSEL_Pos (25U)
<> 161:2cc1468da177 6549 #define DMA_SxCR_CHSEL_Msk (0xFU << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
<> 161:2cc1468da177 6550 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
<> 161:2cc1468da177 6551 #define DMA_SxCR_CHSEL_0 (0x1U << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 6552 #define DMA_SxCR_CHSEL_1 (0x2U << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 6553 #define DMA_SxCR_CHSEL_2 (0x4U << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 6554 #define DMA_SxCR_CHSEL_3 (0x8U << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 6555 #define DMA_SxCR_MBURST_Pos (23U)
<> 161:2cc1468da177 6556 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
<> 161:2cc1468da177 6557 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
<> 161:2cc1468da177 6558 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 6559 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 6560 #define DMA_SxCR_PBURST_Pos (21U)
<> 161:2cc1468da177 6561 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
<> 161:2cc1468da177 6562 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
<> 161:2cc1468da177 6563 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 6564 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 6565 #define DMA_SxCR_CT_Pos (19U)
<> 161:2cc1468da177 6566 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 6567 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
<> 161:2cc1468da177 6568 #define DMA_SxCR_DBM_Pos (18U)
<> 161:2cc1468da177 6569 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 6570 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
<> 161:2cc1468da177 6571 #define DMA_SxCR_PL_Pos (16U)
<> 161:2cc1468da177 6572 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 6573 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
<> 161:2cc1468da177 6574 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 6575 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 6576 #define DMA_SxCR_PINCOS_Pos (15U)
<> 161:2cc1468da177 6577 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 6578 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
<> 161:2cc1468da177 6579 #define DMA_SxCR_MSIZE_Pos (13U)
<> 161:2cc1468da177 6580 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
<> 161:2cc1468da177 6581 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
<> 161:2cc1468da177 6582 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 6583 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 6584 #define DMA_SxCR_PSIZE_Pos (11U)
<> 161:2cc1468da177 6585 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
<> 161:2cc1468da177 6586 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
<> 161:2cc1468da177 6587 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 6588 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 6589 #define DMA_SxCR_MINC_Pos (10U)
<> 161:2cc1468da177 6590 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 6591 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
<> 161:2cc1468da177 6592 #define DMA_SxCR_PINC_Pos (9U)
<> 161:2cc1468da177 6593 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 6594 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
<> 161:2cc1468da177 6595 #define DMA_SxCR_CIRC_Pos (8U)
<> 161:2cc1468da177 6596 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 6597 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
<> 161:2cc1468da177 6598 #define DMA_SxCR_DIR_Pos (6U)
<> 161:2cc1468da177 6599 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 6600 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
<> 161:2cc1468da177 6601 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 6602 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 6603 #define DMA_SxCR_PFCTRL_Pos (5U)
<> 161:2cc1468da177 6604 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6605 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
<> 161:2cc1468da177 6606 #define DMA_SxCR_TCIE_Pos (4U)
<> 161:2cc1468da177 6607 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6608 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
<> 161:2cc1468da177 6609 #define DMA_SxCR_HTIE_Pos (3U)
<> 161:2cc1468da177 6610 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6611 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
<> 161:2cc1468da177 6612 #define DMA_SxCR_TEIE_Pos (2U)
<> 161:2cc1468da177 6613 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6614 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
<> 161:2cc1468da177 6615 #define DMA_SxCR_DMEIE_Pos (1U)
<> 161:2cc1468da177 6616 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6617 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
<> 161:2cc1468da177 6618 #define DMA_SxCR_EN_Pos (0U)
<> 161:2cc1468da177 6619 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6620 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
<> 144:ef7eb2e8f9f7 6621
<> 144:ef7eb2e8f9f7 6622 /******************** Bits definition for DMA_SxCNDTR register **************/
<> 161:2cc1468da177 6623 #define DMA_SxNDT_Pos (0U)
<> 161:2cc1468da177 6624 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 6625 #define DMA_SxNDT DMA_SxNDT_Msk
<> 161:2cc1468da177 6626 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6627 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6628 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6629 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6630 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6631 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6632 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 6633 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 6634 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 6635 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 6636 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 6637 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 6638 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 6639 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 6640 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 6641 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 6642
<> 161:2cc1468da177 6643 /******************** Bits definition for DMA_SxFCR register ****************/
<> 161:2cc1468da177 6644 #define DMA_SxFCR_FEIE_Pos (7U)
<> 161:2cc1468da177 6645 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 6646 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
<> 161:2cc1468da177 6647 #define DMA_SxFCR_FS_Pos (3U)
<> 161:2cc1468da177 6648 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
<> 161:2cc1468da177 6649 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
<> 161:2cc1468da177 6650 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6651 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6652 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6653 #define DMA_SxFCR_DMDIS_Pos (2U)
<> 161:2cc1468da177 6654 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6655 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
<> 161:2cc1468da177 6656 #define DMA_SxFCR_FTH_Pos (0U)
<> 161:2cc1468da177 6657 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 6658 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
<> 161:2cc1468da177 6659 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6660 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6661
<> 161:2cc1468da177 6662 /******************** Bits definition for DMA_LISR register *****************/
<> 161:2cc1468da177 6663 #define DMA_LISR_TCIF3_Pos (27U)
<> 161:2cc1468da177 6664 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 6665 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
<> 161:2cc1468da177 6666 #define DMA_LISR_HTIF3_Pos (26U)
<> 161:2cc1468da177 6667 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 6668 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
<> 161:2cc1468da177 6669 #define DMA_LISR_TEIF3_Pos (25U)
<> 161:2cc1468da177 6670 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 6671 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
<> 161:2cc1468da177 6672 #define DMA_LISR_DMEIF3_Pos (24U)
<> 161:2cc1468da177 6673 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 6674 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
<> 161:2cc1468da177 6675 #define DMA_LISR_FEIF3_Pos (22U)
<> 161:2cc1468da177 6676 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 6677 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
<> 161:2cc1468da177 6678 #define DMA_LISR_TCIF2_Pos (21U)
<> 161:2cc1468da177 6679 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 6680 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
<> 161:2cc1468da177 6681 #define DMA_LISR_HTIF2_Pos (20U)
<> 161:2cc1468da177 6682 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 6683 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
<> 161:2cc1468da177 6684 #define DMA_LISR_TEIF2_Pos (19U)
<> 161:2cc1468da177 6685 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 6686 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
<> 161:2cc1468da177 6687 #define DMA_LISR_DMEIF2_Pos (18U)
<> 161:2cc1468da177 6688 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 6689 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
<> 161:2cc1468da177 6690 #define DMA_LISR_FEIF2_Pos (16U)
<> 161:2cc1468da177 6691 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 6692 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
<> 161:2cc1468da177 6693 #define DMA_LISR_TCIF1_Pos (11U)
<> 161:2cc1468da177 6694 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 6695 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
<> 161:2cc1468da177 6696 #define DMA_LISR_HTIF1_Pos (10U)
<> 161:2cc1468da177 6697 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 6698 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
<> 161:2cc1468da177 6699 #define DMA_LISR_TEIF1_Pos (9U)
<> 161:2cc1468da177 6700 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 6701 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
<> 161:2cc1468da177 6702 #define DMA_LISR_DMEIF1_Pos (8U)
<> 161:2cc1468da177 6703 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 6704 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
<> 161:2cc1468da177 6705 #define DMA_LISR_FEIF1_Pos (6U)
<> 161:2cc1468da177 6706 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 6707 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
<> 161:2cc1468da177 6708 #define DMA_LISR_TCIF0_Pos (5U)
<> 161:2cc1468da177 6709 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6710 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
<> 161:2cc1468da177 6711 #define DMA_LISR_HTIF0_Pos (4U)
<> 161:2cc1468da177 6712 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6713 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
<> 161:2cc1468da177 6714 #define DMA_LISR_TEIF0_Pos (3U)
<> 161:2cc1468da177 6715 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6716 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
<> 161:2cc1468da177 6717 #define DMA_LISR_DMEIF0_Pos (2U)
<> 161:2cc1468da177 6718 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6719 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
<> 161:2cc1468da177 6720 #define DMA_LISR_FEIF0_Pos (0U)
<> 161:2cc1468da177 6721 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6722 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
<> 161:2cc1468da177 6723
<> 161:2cc1468da177 6724 /******************** Bits definition for DMA_HISR register *****************/
<> 161:2cc1468da177 6725 #define DMA_HISR_TCIF7_Pos (27U)
<> 161:2cc1468da177 6726 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 6727 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
<> 161:2cc1468da177 6728 #define DMA_HISR_HTIF7_Pos (26U)
<> 161:2cc1468da177 6729 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 6730 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
<> 161:2cc1468da177 6731 #define DMA_HISR_TEIF7_Pos (25U)
<> 161:2cc1468da177 6732 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 6733 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
<> 161:2cc1468da177 6734 #define DMA_HISR_DMEIF7_Pos (24U)
<> 161:2cc1468da177 6735 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 6736 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
<> 161:2cc1468da177 6737 #define DMA_HISR_FEIF7_Pos (22U)
<> 161:2cc1468da177 6738 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 6739 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
<> 161:2cc1468da177 6740 #define DMA_HISR_TCIF6_Pos (21U)
<> 161:2cc1468da177 6741 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 6742 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
<> 161:2cc1468da177 6743 #define DMA_HISR_HTIF6_Pos (20U)
<> 161:2cc1468da177 6744 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 6745 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
<> 161:2cc1468da177 6746 #define DMA_HISR_TEIF6_Pos (19U)
<> 161:2cc1468da177 6747 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 6748 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
<> 161:2cc1468da177 6749 #define DMA_HISR_DMEIF6_Pos (18U)
<> 161:2cc1468da177 6750 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 6751 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
<> 161:2cc1468da177 6752 #define DMA_HISR_FEIF6_Pos (16U)
<> 161:2cc1468da177 6753 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 6754 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
<> 161:2cc1468da177 6755 #define DMA_HISR_TCIF5_Pos (11U)
<> 161:2cc1468da177 6756 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 6757 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
<> 161:2cc1468da177 6758 #define DMA_HISR_HTIF5_Pos (10U)
<> 161:2cc1468da177 6759 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 6760 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
<> 161:2cc1468da177 6761 #define DMA_HISR_TEIF5_Pos (9U)
<> 161:2cc1468da177 6762 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 6763 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
<> 161:2cc1468da177 6764 #define DMA_HISR_DMEIF5_Pos (8U)
<> 161:2cc1468da177 6765 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 6766 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
<> 161:2cc1468da177 6767 #define DMA_HISR_FEIF5_Pos (6U)
<> 161:2cc1468da177 6768 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 6769 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
<> 161:2cc1468da177 6770 #define DMA_HISR_TCIF4_Pos (5U)
<> 161:2cc1468da177 6771 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6772 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
<> 161:2cc1468da177 6773 #define DMA_HISR_HTIF4_Pos (4U)
<> 161:2cc1468da177 6774 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6775 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
<> 161:2cc1468da177 6776 #define DMA_HISR_TEIF4_Pos (3U)
<> 161:2cc1468da177 6777 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6778 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
<> 161:2cc1468da177 6779 #define DMA_HISR_DMEIF4_Pos (2U)
<> 161:2cc1468da177 6780 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6781 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
<> 161:2cc1468da177 6782 #define DMA_HISR_FEIF4_Pos (0U)
<> 161:2cc1468da177 6783 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6784 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
<> 161:2cc1468da177 6785
<> 161:2cc1468da177 6786 /******************** Bits definition for DMA_LIFCR register ****************/
<> 161:2cc1468da177 6787 #define DMA_LIFCR_CTCIF3_Pos (27U)
<> 161:2cc1468da177 6788 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 6789 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
<> 161:2cc1468da177 6790 #define DMA_LIFCR_CHTIF3_Pos (26U)
<> 161:2cc1468da177 6791 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 6792 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
<> 161:2cc1468da177 6793 #define DMA_LIFCR_CTEIF3_Pos (25U)
<> 161:2cc1468da177 6794 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 6795 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
<> 161:2cc1468da177 6796 #define DMA_LIFCR_CDMEIF3_Pos (24U)
<> 161:2cc1468da177 6797 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 6798 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
<> 161:2cc1468da177 6799 #define DMA_LIFCR_CFEIF3_Pos (22U)
<> 161:2cc1468da177 6800 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 6801 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
<> 161:2cc1468da177 6802 #define DMA_LIFCR_CTCIF2_Pos (21U)
<> 161:2cc1468da177 6803 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 6804 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
<> 161:2cc1468da177 6805 #define DMA_LIFCR_CHTIF2_Pos (20U)
<> 161:2cc1468da177 6806 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 6807 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
<> 161:2cc1468da177 6808 #define DMA_LIFCR_CTEIF2_Pos (19U)
<> 161:2cc1468da177 6809 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 6810 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
<> 161:2cc1468da177 6811 #define DMA_LIFCR_CDMEIF2_Pos (18U)
<> 161:2cc1468da177 6812 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 6813 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
<> 161:2cc1468da177 6814 #define DMA_LIFCR_CFEIF2_Pos (16U)
<> 161:2cc1468da177 6815 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 6816 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
<> 161:2cc1468da177 6817 #define DMA_LIFCR_CTCIF1_Pos (11U)
<> 161:2cc1468da177 6818 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 6819 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
<> 161:2cc1468da177 6820 #define DMA_LIFCR_CHTIF1_Pos (10U)
<> 161:2cc1468da177 6821 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 6822 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
<> 161:2cc1468da177 6823 #define DMA_LIFCR_CTEIF1_Pos (9U)
<> 161:2cc1468da177 6824 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 6825 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
<> 161:2cc1468da177 6826 #define DMA_LIFCR_CDMEIF1_Pos (8U)
<> 161:2cc1468da177 6827 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 6828 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
<> 161:2cc1468da177 6829 #define DMA_LIFCR_CFEIF1_Pos (6U)
<> 161:2cc1468da177 6830 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 6831 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
<> 161:2cc1468da177 6832 #define DMA_LIFCR_CTCIF0_Pos (5U)
<> 161:2cc1468da177 6833 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6834 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
<> 161:2cc1468da177 6835 #define DMA_LIFCR_CHTIF0_Pos (4U)
<> 161:2cc1468da177 6836 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6837 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
<> 161:2cc1468da177 6838 #define DMA_LIFCR_CTEIF0_Pos (3U)
<> 161:2cc1468da177 6839 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6840 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
<> 161:2cc1468da177 6841 #define DMA_LIFCR_CDMEIF0_Pos (2U)
<> 161:2cc1468da177 6842 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6843 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
<> 161:2cc1468da177 6844 #define DMA_LIFCR_CFEIF0_Pos (0U)
<> 161:2cc1468da177 6845 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6846 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
<> 161:2cc1468da177 6847
<> 161:2cc1468da177 6848 /******************** Bits definition for DMA_HIFCR register ****************/
<> 161:2cc1468da177 6849 #define DMA_HIFCR_CTCIF7_Pos (27U)
<> 161:2cc1468da177 6850 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 6851 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
<> 161:2cc1468da177 6852 #define DMA_HIFCR_CHTIF7_Pos (26U)
<> 161:2cc1468da177 6853 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 6854 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
<> 161:2cc1468da177 6855 #define DMA_HIFCR_CTEIF7_Pos (25U)
<> 161:2cc1468da177 6856 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 6857 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
<> 161:2cc1468da177 6858 #define DMA_HIFCR_CDMEIF7_Pos (24U)
<> 161:2cc1468da177 6859 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 6860 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
<> 161:2cc1468da177 6861 #define DMA_HIFCR_CFEIF7_Pos (22U)
<> 161:2cc1468da177 6862 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 6863 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
<> 161:2cc1468da177 6864 #define DMA_HIFCR_CTCIF6_Pos (21U)
<> 161:2cc1468da177 6865 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 6866 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
<> 161:2cc1468da177 6867 #define DMA_HIFCR_CHTIF6_Pos (20U)
<> 161:2cc1468da177 6868 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 6869 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
<> 161:2cc1468da177 6870 #define DMA_HIFCR_CTEIF6_Pos (19U)
<> 161:2cc1468da177 6871 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 6872 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
<> 161:2cc1468da177 6873 #define DMA_HIFCR_CDMEIF6_Pos (18U)
<> 161:2cc1468da177 6874 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 6875 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
<> 161:2cc1468da177 6876 #define DMA_HIFCR_CFEIF6_Pos (16U)
<> 161:2cc1468da177 6877 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 6878 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
<> 161:2cc1468da177 6879 #define DMA_HIFCR_CTCIF5_Pos (11U)
<> 161:2cc1468da177 6880 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 6881 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
<> 161:2cc1468da177 6882 #define DMA_HIFCR_CHTIF5_Pos (10U)
<> 161:2cc1468da177 6883 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 6884 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
<> 161:2cc1468da177 6885 #define DMA_HIFCR_CTEIF5_Pos (9U)
<> 161:2cc1468da177 6886 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 6887 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
<> 161:2cc1468da177 6888 #define DMA_HIFCR_CDMEIF5_Pos (8U)
<> 161:2cc1468da177 6889 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 6890 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
<> 161:2cc1468da177 6891 #define DMA_HIFCR_CFEIF5_Pos (6U)
<> 161:2cc1468da177 6892 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 6893 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
<> 161:2cc1468da177 6894 #define DMA_HIFCR_CTCIF4_Pos (5U)
<> 161:2cc1468da177 6895 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6896 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
<> 161:2cc1468da177 6897 #define DMA_HIFCR_CHTIF4_Pos (4U)
<> 161:2cc1468da177 6898 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6899 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
<> 161:2cc1468da177 6900 #define DMA_HIFCR_CTEIF4_Pos (3U)
<> 161:2cc1468da177 6901 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6902 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
<> 161:2cc1468da177 6903 #define DMA_HIFCR_CDMEIF4_Pos (2U)
<> 161:2cc1468da177 6904 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6905 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
<> 161:2cc1468da177 6906 #define DMA_HIFCR_CFEIF4_Pos (0U)
<> 161:2cc1468da177 6907 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6908 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
<> 161:2cc1468da177 6909
<> 161:2cc1468da177 6910 /****************** Bit definition for DMA_SxPAR register ********************/
<> 161:2cc1468da177 6911 #define DMA_SxPAR_PA_Pos (0U)
<> 161:2cc1468da177 6912 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 6913 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
<> 161:2cc1468da177 6914
<> 161:2cc1468da177 6915 /****************** Bit definition for DMA_SxM0AR register ********************/
<> 161:2cc1468da177 6916 #define DMA_SxM0AR_M0A_Pos (0U)
<> 161:2cc1468da177 6917 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 6918 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
<> 161:2cc1468da177 6919
<> 161:2cc1468da177 6920 /****************** Bit definition for DMA_SxM1AR register ********************/
<> 161:2cc1468da177 6921 #define DMA_SxM1AR_M1A_Pos (0U)
<> 161:2cc1468da177 6922 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 6923 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 6924
<> 144:ef7eb2e8f9f7 6925 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6926 /* */
<> 144:ef7eb2e8f9f7 6927 /* AHB Master DMA2D Controller (DMA2D) */
<> 144:ef7eb2e8f9f7 6928 /* */
<> 144:ef7eb2e8f9f7 6929 /******************************************************************************/
<> 161:2cc1468da177 6930 /*
<> 161:2cc1468da177 6931 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
<> 161:2cc1468da177 6932 */
<> 161:2cc1468da177 6933 #define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
<> 144:ef7eb2e8f9f7 6934 /******************** Bit definition for DMA2D_CR register ******************/
<> 144:ef7eb2e8f9f7 6935
<> 161:2cc1468da177 6936 #define DMA2D_CR_START_Pos (0U)
<> 161:2cc1468da177 6937 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6938 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
<> 161:2cc1468da177 6939 #define DMA2D_CR_SUSP_Pos (1U)
<> 161:2cc1468da177 6940 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6941 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
<> 161:2cc1468da177 6942 #define DMA2D_CR_ABORT_Pos (2U)
<> 161:2cc1468da177 6943 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6944 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
<> 161:2cc1468da177 6945 #define DMA2D_CR_TEIE_Pos (8U)
<> 161:2cc1468da177 6946 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 6947 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
<> 161:2cc1468da177 6948 #define DMA2D_CR_TCIE_Pos (9U)
<> 161:2cc1468da177 6949 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 6950 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
<> 161:2cc1468da177 6951 #define DMA2D_CR_TWIE_Pos (10U)
<> 161:2cc1468da177 6952 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 6953 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
<> 161:2cc1468da177 6954 #define DMA2D_CR_CAEIE_Pos (11U)
<> 161:2cc1468da177 6955 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 6956 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
<> 161:2cc1468da177 6957 #define DMA2D_CR_CTCIE_Pos (12U)
<> 161:2cc1468da177 6958 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 6959 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
<> 161:2cc1468da177 6960 #define DMA2D_CR_CEIE_Pos (13U)
<> 161:2cc1468da177 6961 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 6962 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
<> 161:2cc1468da177 6963 #define DMA2D_CR_MODE_Pos (16U)
<> 161:2cc1468da177 6964 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 6965 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
<> 161:2cc1468da177 6966 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 6967 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 6968
<> 144:ef7eb2e8f9f7 6969 /******************** Bit definition for DMA2D_ISR register *****************/
<> 144:ef7eb2e8f9f7 6970
<> 161:2cc1468da177 6971 #define DMA2D_ISR_TEIF_Pos (0U)
<> 161:2cc1468da177 6972 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6973 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
<> 161:2cc1468da177 6974 #define DMA2D_ISR_TCIF_Pos (1U)
<> 161:2cc1468da177 6975 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6976 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
<> 161:2cc1468da177 6977 #define DMA2D_ISR_TWIF_Pos (2U)
<> 161:2cc1468da177 6978 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 6979 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
<> 161:2cc1468da177 6980 #define DMA2D_ISR_CAEIF_Pos (3U)
<> 161:2cc1468da177 6981 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 6982 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
<> 161:2cc1468da177 6983 #define DMA2D_ISR_CTCIF_Pos (4U)
<> 161:2cc1468da177 6984 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 6985 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
<> 161:2cc1468da177 6986 #define DMA2D_ISR_CEIF_Pos (5U)
<> 161:2cc1468da177 6987 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 6988 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 6989
<> 144:ef7eb2e8f9f7 6990 /******************** Bit definition for DMA2D_IFCR register ****************/
<> 144:ef7eb2e8f9f7 6991
<> 161:2cc1468da177 6992 #define DMA2D_IFCR_CTEIF_Pos (0U)
<> 161:2cc1468da177 6993 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 6994 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
<> 161:2cc1468da177 6995 #define DMA2D_IFCR_CTCIF_Pos (1U)
<> 161:2cc1468da177 6996 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 6997 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
<> 161:2cc1468da177 6998 #define DMA2D_IFCR_CTWIF_Pos (2U)
<> 161:2cc1468da177 6999 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7000 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
<> 161:2cc1468da177 7001 #define DMA2D_IFCR_CAECIF_Pos (3U)
<> 161:2cc1468da177 7002 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 7003 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
<> 161:2cc1468da177 7004 #define DMA2D_IFCR_CCTCIF_Pos (4U)
<> 161:2cc1468da177 7005 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7006 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
<> 161:2cc1468da177 7007 #define DMA2D_IFCR_CCEIF_Pos (5U)
<> 161:2cc1468da177 7008 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7009 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 7010
<> 144:ef7eb2e8f9f7 7011 /* Legacy defines */
<> 144:ef7eb2e8f9f7 7012 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 7013 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 7014 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
<> 144:ef7eb2e8f9f7 7015 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 7016 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 7017 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 7018
<> 144:ef7eb2e8f9f7 7019 /******************** Bit definition for DMA2D_FGMAR register ***************/
<> 144:ef7eb2e8f9f7 7020
<> 161:2cc1468da177 7021 #define DMA2D_FGMAR_MA_Pos (0U)
<> 161:2cc1468da177 7022 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 7023 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 7024
<> 144:ef7eb2e8f9f7 7025 /******************** Bit definition for DMA2D_FGOR register ****************/
<> 144:ef7eb2e8f9f7 7026
<> 161:2cc1468da177 7027 #define DMA2D_FGOR_LO_Pos (0U)
<> 161:2cc1468da177 7028 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
<> 161:2cc1468da177 7029 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
<> 144:ef7eb2e8f9f7 7030
<> 144:ef7eb2e8f9f7 7031 /******************** Bit definition for DMA2D_BGMAR register ***************/
<> 144:ef7eb2e8f9f7 7032
<> 161:2cc1468da177 7033 #define DMA2D_BGMAR_MA_Pos (0U)
<> 161:2cc1468da177 7034 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 7035 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 7036
<> 144:ef7eb2e8f9f7 7037 /******************** Bit definition for DMA2D_BGOR register ****************/
<> 144:ef7eb2e8f9f7 7038
<> 161:2cc1468da177 7039 #define DMA2D_BGOR_LO_Pos (0U)
<> 161:2cc1468da177 7040 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
<> 161:2cc1468da177 7041 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
<> 144:ef7eb2e8f9f7 7042
<> 144:ef7eb2e8f9f7 7043 /******************** Bit definition for DMA2D_FGPFCCR register *************/
<> 144:ef7eb2e8f9f7 7044
<> 161:2cc1468da177 7045 #define DMA2D_FGPFCCR_CM_Pos (0U)
<> 161:2cc1468da177 7046 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 7047 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
<> 161:2cc1468da177 7048 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7049 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7050 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7051 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 7052 #define DMA2D_FGPFCCR_CCM_Pos (4U)
<> 161:2cc1468da177 7053 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7054 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
<> 161:2cc1468da177 7055 #define DMA2D_FGPFCCR_START_Pos (5U)
<> 161:2cc1468da177 7056 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7057 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
<> 161:2cc1468da177 7058 #define DMA2D_FGPFCCR_CS_Pos (8U)
<> 161:2cc1468da177 7059 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 7060 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
<> 161:2cc1468da177 7061 #define DMA2D_FGPFCCR_AM_Pos (16U)
<> 161:2cc1468da177 7062 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 7063 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
<> 161:2cc1468da177 7064 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7065 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 7066 #define DMA2D_FGPFCCR_AI_Pos (20U)
<> 161:2cc1468da177 7067 #define DMA2D_FGPFCCR_AI_Msk (0x1U << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 7068 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
<> 161:2cc1468da177 7069 #define DMA2D_FGPFCCR_RBS_Pos (21U)
<> 161:2cc1468da177 7070 #define DMA2D_FGPFCCR_RBS_Msk (0x1U << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 7071 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
<> 161:2cc1468da177 7072 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
<> 161:2cc1468da177 7073 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 7074 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
<> 144:ef7eb2e8f9f7 7075
<> 144:ef7eb2e8f9f7 7076 /******************** Bit definition for DMA2D_FGCOLR register **************/
<> 144:ef7eb2e8f9f7 7077
<> 161:2cc1468da177 7078 #define DMA2D_FGCOLR_BLUE_Pos (0U)
<> 161:2cc1468da177 7079 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 7080 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
<> 161:2cc1468da177 7081 #define DMA2D_FGCOLR_GREEN_Pos (8U)
<> 161:2cc1468da177 7082 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 7083 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
<> 161:2cc1468da177 7084 #define DMA2D_FGCOLR_RED_Pos (16U)
<> 161:2cc1468da177 7085 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 7086 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
<> 144:ef7eb2e8f9f7 7087
<> 144:ef7eb2e8f9f7 7088 /******************** Bit definition for DMA2D_BGPFCCR register *************/
<> 144:ef7eb2e8f9f7 7089
<> 161:2cc1468da177 7090 #define DMA2D_BGPFCCR_CM_Pos (0U)
<> 161:2cc1468da177 7091 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 7092 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
<> 161:2cc1468da177 7093 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7094 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7095 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7096 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
<> 161:2cc1468da177 7097 #define DMA2D_BGPFCCR_CCM_Pos (4U)
<> 161:2cc1468da177 7098 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7099 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
<> 161:2cc1468da177 7100 #define DMA2D_BGPFCCR_START_Pos (5U)
<> 161:2cc1468da177 7101 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7102 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
<> 161:2cc1468da177 7103 #define DMA2D_BGPFCCR_CS_Pos (8U)
<> 161:2cc1468da177 7104 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 7105 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
<> 161:2cc1468da177 7106 #define DMA2D_BGPFCCR_AM_Pos (16U)
<> 161:2cc1468da177 7107 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 7108 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
<> 161:2cc1468da177 7109 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7110 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 7111 #define DMA2D_BGPFCCR_AI_Pos (20U)
<> 161:2cc1468da177 7112 #define DMA2D_BGPFCCR_AI_Msk (0x1U << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 7113 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
<> 161:2cc1468da177 7114 #define DMA2D_BGPFCCR_RBS_Pos (21U)
<> 161:2cc1468da177 7115 #define DMA2D_BGPFCCR_RBS_Msk (0x1U << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 7116 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
<> 161:2cc1468da177 7117 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
<> 161:2cc1468da177 7118 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 7119 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
<> 144:ef7eb2e8f9f7 7120
<> 144:ef7eb2e8f9f7 7121 /******************** Bit definition for DMA2D_BGCOLR register **************/
<> 144:ef7eb2e8f9f7 7122
<> 161:2cc1468da177 7123 #define DMA2D_BGCOLR_BLUE_Pos (0U)
<> 161:2cc1468da177 7124 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 7125 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
<> 161:2cc1468da177 7126 #define DMA2D_BGCOLR_GREEN_Pos (8U)
<> 161:2cc1468da177 7127 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 7128 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
<> 161:2cc1468da177 7129 #define DMA2D_BGCOLR_RED_Pos (16U)
<> 161:2cc1468da177 7130 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 7131 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
<> 144:ef7eb2e8f9f7 7132
<> 144:ef7eb2e8f9f7 7133 /******************** Bit definition for DMA2D_FGCMAR register **************/
<> 144:ef7eb2e8f9f7 7134
<> 161:2cc1468da177 7135 #define DMA2D_FGCMAR_MA_Pos (0U)
<> 161:2cc1468da177 7136 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 7137 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 7138
<> 144:ef7eb2e8f9f7 7139 /******************** Bit definition for DMA2D_BGCMAR register **************/
<> 144:ef7eb2e8f9f7 7140
<> 161:2cc1468da177 7141 #define DMA2D_BGCMAR_MA_Pos (0U)
<> 161:2cc1468da177 7142 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 7143 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 7144
<> 144:ef7eb2e8f9f7 7145 /******************** Bit definition for DMA2D_OPFCCR register **************/
<> 144:ef7eb2e8f9f7 7146
<> 161:2cc1468da177 7147 #define DMA2D_OPFCCR_CM_Pos (0U)
<> 161:2cc1468da177 7148 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 7149 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
<> 161:2cc1468da177 7150 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7151 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7152 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7153 #define DMA2D_OPFCCR_AI_Pos (20U)
<> 161:2cc1468da177 7154 #define DMA2D_OPFCCR_AI_Msk (0x1U << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 7155 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
<> 161:2cc1468da177 7156 #define DMA2D_OPFCCR_RBS_Pos (21U)
<> 161:2cc1468da177 7157 #define DMA2D_OPFCCR_RBS_Msk (0x1U << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 7158 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
<> 144:ef7eb2e8f9f7 7159
<> 144:ef7eb2e8f9f7 7160 /******************** Bit definition for DMA2D_OCOLR register ***************/
<> 144:ef7eb2e8f9f7 7161
<> 144:ef7eb2e8f9f7 7162 /*!<Mode_ARGB8888/RGB888 */
<> 144:ef7eb2e8f9f7 7163
<> 161:2cc1468da177 7164 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
<> 161:2cc1468da177 7165 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
<> 161:2cc1468da177 7166 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
<> 161:2cc1468da177 7167 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
<> 144:ef7eb2e8f9f7 7168
<> 144:ef7eb2e8f9f7 7169 /*!<Mode_RGB565 */
<> 161:2cc1468da177 7170 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
<> 161:2cc1468da177 7171 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
<> 161:2cc1468da177 7172 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
<> 144:ef7eb2e8f9f7 7173
<> 144:ef7eb2e8f9f7 7174 /*!<Mode_ARGB1555 */
<> 161:2cc1468da177 7175 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
<> 161:2cc1468da177 7176 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
<> 161:2cc1468da177 7177 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
<> 161:2cc1468da177 7178 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
<> 144:ef7eb2e8f9f7 7179
<> 144:ef7eb2e8f9f7 7180 /*!<Mode_ARGB4444 */
<> 161:2cc1468da177 7181 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
<> 161:2cc1468da177 7182 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
<> 161:2cc1468da177 7183 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
<> 161:2cc1468da177 7184 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
<> 144:ef7eb2e8f9f7 7185
<> 144:ef7eb2e8f9f7 7186 /******************** Bit definition for DMA2D_OMAR register ****************/
<> 144:ef7eb2e8f9f7 7187
<> 161:2cc1468da177 7188 #define DMA2D_OMAR_MA_Pos (0U)
<> 161:2cc1468da177 7189 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 7190 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 7191
<> 144:ef7eb2e8f9f7 7192 /******************** Bit definition for DMA2D_OOR register *****************/
<> 144:ef7eb2e8f9f7 7193
<> 161:2cc1468da177 7194 #define DMA2D_OOR_LO_Pos (0U)
<> 161:2cc1468da177 7195 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
<> 161:2cc1468da177 7196 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
<> 144:ef7eb2e8f9f7 7197
<> 144:ef7eb2e8f9f7 7198 /******************** Bit definition for DMA2D_NLR register *****************/
<> 144:ef7eb2e8f9f7 7199
<> 161:2cc1468da177 7200 #define DMA2D_NLR_NL_Pos (0U)
<> 161:2cc1468da177 7201 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 7202 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
<> 161:2cc1468da177 7203 #define DMA2D_NLR_PL_Pos (16U)
<> 161:2cc1468da177 7204 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
<> 161:2cc1468da177 7205 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
<> 144:ef7eb2e8f9f7 7206
<> 144:ef7eb2e8f9f7 7207 /******************** Bit definition for DMA2D_LWR register *****************/
<> 144:ef7eb2e8f9f7 7208
<> 161:2cc1468da177 7209 #define DMA2D_LWR_LW_Pos (0U)
<> 161:2cc1468da177 7210 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 7211 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
<> 144:ef7eb2e8f9f7 7212
<> 144:ef7eb2e8f9f7 7213 /******************** Bit definition for DMA2D_AMTCR register ***************/
<> 144:ef7eb2e8f9f7 7214
<> 161:2cc1468da177 7215 #define DMA2D_AMTCR_EN_Pos (0U)
<> 161:2cc1468da177 7216 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7217 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
<> 161:2cc1468da177 7218 #define DMA2D_AMTCR_DT_Pos (8U)
<> 161:2cc1468da177 7219 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 7220 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
<> 144:ef7eb2e8f9f7 7221
<> 144:ef7eb2e8f9f7 7222
<> 144:ef7eb2e8f9f7 7223 /******************** Bit definition for DMA2D_FGCLUT register **************/
<> 161:2cc1468da177 7224
<> 144:ef7eb2e8f9f7 7225 /******************** Bit definition for DMA2D_BGCLUT register **************/
<> 144:ef7eb2e8f9f7 7226
<> 144:ef7eb2e8f9f7 7227 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7228 /* */
<> 144:ef7eb2e8f9f7 7229 /* External Interrupt/Event Controller */
<> 144:ef7eb2e8f9f7 7230 /* */
<> 144:ef7eb2e8f9f7 7231 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7232 /******************* Bit definition for EXTI_IMR register *******************/
<> 161:2cc1468da177 7233 #define EXTI_IMR_MR0_Pos (0U)
<> 161:2cc1468da177 7234 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7235 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
<> 161:2cc1468da177 7236 #define EXTI_IMR_MR1_Pos (1U)
<> 161:2cc1468da177 7237 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7238 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
<> 161:2cc1468da177 7239 #define EXTI_IMR_MR2_Pos (2U)
<> 161:2cc1468da177 7240 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7241 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
<> 161:2cc1468da177 7242 #define EXTI_IMR_MR3_Pos (3U)
<> 161:2cc1468da177 7243 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 7244 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
<> 161:2cc1468da177 7245 #define EXTI_IMR_MR4_Pos (4U)
<> 161:2cc1468da177 7246 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7247 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
<> 161:2cc1468da177 7248 #define EXTI_IMR_MR5_Pos (5U)
<> 161:2cc1468da177 7249 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7250 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
<> 161:2cc1468da177 7251 #define EXTI_IMR_MR6_Pos (6U)
<> 161:2cc1468da177 7252 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 7253 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
<> 161:2cc1468da177 7254 #define EXTI_IMR_MR7_Pos (7U)
<> 161:2cc1468da177 7255 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 7256 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
<> 161:2cc1468da177 7257 #define EXTI_IMR_MR8_Pos (8U)
<> 161:2cc1468da177 7258 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 7259 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
<> 161:2cc1468da177 7260 #define EXTI_IMR_MR9_Pos (9U)
<> 161:2cc1468da177 7261 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 7262 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
<> 161:2cc1468da177 7263 #define EXTI_IMR_MR10_Pos (10U)
<> 161:2cc1468da177 7264 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 7265 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
<> 161:2cc1468da177 7266 #define EXTI_IMR_MR11_Pos (11U)
<> 161:2cc1468da177 7267 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 7268 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
<> 161:2cc1468da177 7269 #define EXTI_IMR_MR12_Pos (12U)
<> 161:2cc1468da177 7270 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 7271 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
<> 161:2cc1468da177 7272 #define EXTI_IMR_MR13_Pos (13U)
<> 161:2cc1468da177 7273 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 7274 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
<> 161:2cc1468da177 7275 #define EXTI_IMR_MR14_Pos (14U)
<> 161:2cc1468da177 7276 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 7277 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
<> 161:2cc1468da177 7278 #define EXTI_IMR_MR15_Pos (15U)
<> 161:2cc1468da177 7279 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 7280 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
<> 161:2cc1468da177 7281 #define EXTI_IMR_MR16_Pos (16U)
<> 161:2cc1468da177 7282 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7283 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
<> 161:2cc1468da177 7284 #define EXTI_IMR_MR17_Pos (17U)
<> 161:2cc1468da177 7285 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 7286 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
<> 161:2cc1468da177 7287 #define EXTI_IMR_MR18_Pos (18U)
<> 161:2cc1468da177 7288 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 7289 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
<> 161:2cc1468da177 7290 #define EXTI_IMR_MR19_Pos (19U)
<> 161:2cc1468da177 7291 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 7292 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
<> 161:2cc1468da177 7293 #define EXTI_IMR_MR20_Pos (20U)
<> 161:2cc1468da177 7294 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 7295 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
<> 161:2cc1468da177 7296 #define EXTI_IMR_MR21_Pos (21U)
<> 161:2cc1468da177 7297 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 7298 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
<> 161:2cc1468da177 7299 #define EXTI_IMR_MR22_Pos (22U)
<> 161:2cc1468da177 7300 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 7301 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
<> 161:2cc1468da177 7302 #define EXTI_IMR_MR23_Pos (23U)
<> 161:2cc1468da177 7303 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 7304 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
<> 161:2cc1468da177 7305 #define EXTI_IMR_MR24_Pos (24U)
<> 161:2cc1468da177 7306 #define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 7307 #define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
<> 144:ef7eb2e8f9f7 7308
<> 144:ef7eb2e8f9f7 7309 /* Reference Defines */
<> 161:2cc1468da177 7310 #define EXTI_IMR_IM0 EXTI_IMR_MR0
<> 161:2cc1468da177 7311 #define EXTI_IMR_IM1 EXTI_IMR_MR1
<> 161:2cc1468da177 7312 #define EXTI_IMR_IM2 EXTI_IMR_MR2
<> 161:2cc1468da177 7313 #define EXTI_IMR_IM3 EXTI_IMR_MR3
<> 161:2cc1468da177 7314 #define EXTI_IMR_IM4 EXTI_IMR_MR4
<> 161:2cc1468da177 7315 #define EXTI_IMR_IM5 EXTI_IMR_MR5
<> 161:2cc1468da177 7316 #define EXTI_IMR_IM6 EXTI_IMR_MR6
<> 161:2cc1468da177 7317 #define EXTI_IMR_IM7 EXTI_IMR_MR7
<> 161:2cc1468da177 7318 #define EXTI_IMR_IM8 EXTI_IMR_MR8
<> 161:2cc1468da177 7319 #define EXTI_IMR_IM9 EXTI_IMR_MR9
<> 144:ef7eb2e8f9f7 7320 #define EXTI_IMR_IM10 EXTI_IMR_MR10
<> 144:ef7eb2e8f9f7 7321 #define EXTI_IMR_IM11 EXTI_IMR_MR11
<> 144:ef7eb2e8f9f7 7322 #define EXTI_IMR_IM12 EXTI_IMR_MR12
<> 144:ef7eb2e8f9f7 7323 #define EXTI_IMR_IM13 EXTI_IMR_MR13
<> 144:ef7eb2e8f9f7 7324 #define EXTI_IMR_IM14 EXTI_IMR_MR14
<> 144:ef7eb2e8f9f7 7325 #define EXTI_IMR_IM15 EXTI_IMR_MR15
<> 144:ef7eb2e8f9f7 7326 #define EXTI_IMR_IM16 EXTI_IMR_MR16
<> 144:ef7eb2e8f9f7 7327 #define EXTI_IMR_IM17 EXTI_IMR_MR17
<> 144:ef7eb2e8f9f7 7328 #define EXTI_IMR_IM18 EXTI_IMR_MR18
<> 144:ef7eb2e8f9f7 7329 #define EXTI_IMR_IM19 EXTI_IMR_MR19
<> 144:ef7eb2e8f9f7 7330 #define EXTI_IMR_IM20 EXTI_IMR_MR20
<> 144:ef7eb2e8f9f7 7331 #define EXTI_IMR_IM21 EXTI_IMR_MR21
<> 144:ef7eb2e8f9f7 7332 #define EXTI_IMR_IM22 EXTI_IMR_MR22
<> 144:ef7eb2e8f9f7 7333 #define EXTI_IMR_IM23 EXTI_IMR_MR23
<> 144:ef7eb2e8f9f7 7334 #define EXTI_IMR_IM24 EXTI_IMR_MR24
<> 144:ef7eb2e8f9f7 7335
<> 161:2cc1468da177 7336 #define EXTI_IMR_IM_Pos (0U)
<> 161:2cc1468da177 7337 #define EXTI_IMR_IM_Msk (0x1FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x01FFFFFF */
<> 161:2cc1468da177 7338 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
<> 144:ef7eb2e8f9f7 7339
<> 144:ef7eb2e8f9f7 7340 /******************* Bit definition for EXTI_EMR register *******************/
<> 161:2cc1468da177 7341 #define EXTI_EMR_MR0_Pos (0U)
<> 161:2cc1468da177 7342 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7343 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
<> 161:2cc1468da177 7344 #define EXTI_EMR_MR1_Pos (1U)
<> 161:2cc1468da177 7345 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7346 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
<> 161:2cc1468da177 7347 #define EXTI_EMR_MR2_Pos (2U)
<> 161:2cc1468da177 7348 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7349 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
<> 161:2cc1468da177 7350 #define EXTI_EMR_MR3_Pos (3U)
<> 161:2cc1468da177 7351 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 7352 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
<> 161:2cc1468da177 7353 #define EXTI_EMR_MR4_Pos (4U)
<> 161:2cc1468da177 7354 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7355 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
<> 161:2cc1468da177 7356 #define EXTI_EMR_MR5_Pos (5U)
<> 161:2cc1468da177 7357 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7358 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
<> 161:2cc1468da177 7359 #define EXTI_EMR_MR6_Pos (6U)
<> 161:2cc1468da177 7360 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 7361 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
<> 161:2cc1468da177 7362 #define EXTI_EMR_MR7_Pos (7U)
<> 161:2cc1468da177 7363 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 7364 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
<> 161:2cc1468da177 7365 #define EXTI_EMR_MR8_Pos (8U)
<> 161:2cc1468da177 7366 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 7367 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
<> 161:2cc1468da177 7368 #define EXTI_EMR_MR9_Pos (9U)
<> 161:2cc1468da177 7369 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 7370 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
<> 161:2cc1468da177 7371 #define EXTI_EMR_MR10_Pos (10U)
<> 161:2cc1468da177 7372 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 7373 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
<> 161:2cc1468da177 7374 #define EXTI_EMR_MR11_Pos (11U)
<> 161:2cc1468da177 7375 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 7376 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
<> 161:2cc1468da177 7377 #define EXTI_EMR_MR12_Pos (12U)
<> 161:2cc1468da177 7378 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 7379 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
<> 161:2cc1468da177 7380 #define EXTI_EMR_MR13_Pos (13U)
<> 161:2cc1468da177 7381 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 7382 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
<> 161:2cc1468da177 7383 #define EXTI_EMR_MR14_Pos (14U)
<> 161:2cc1468da177 7384 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 7385 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
<> 161:2cc1468da177 7386 #define EXTI_EMR_MR15_Pos (15U)
<> 161:2cc1468da177 7387 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 7388 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
<> 161:2cc1468da177 7389 #define EXTI_EMR_MR16_Pos (16U)
<> 161:2cc1468da177 7390 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7391 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
<> 161:2cc1468da177 7392 #define EXTI_EMR_MR17_Pos (17U)
<> 161:2cc1468da177 7393 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 7394 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
<> 161:2cc1468da177 7395 #define EXTI_EMR_MR18_Pos (18U)
<> 161:2cc1468da177 7396 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 7397 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
<> 161:2cc1468da177 7398 #define EXTI_EMR_MR19_Pos (19U)
<> 161:2cc1468da177 7399 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 7400 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
<> 161:2cc1468da177 7401 #define EXTI_EMR_MR20_Pos (20U)
<> 161:2cc1468da177 7402 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 7403 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
<> 161:2cc1468da177 7404 #define EXTI_EMR_MR21_Pos (21U)
<> 161:2cc1468da177 7405 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 7406 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
<> 161:2cc1468da177 7407 #define EXTI_EMR_MR22_Pos (22U)
<> 161:2cc1468da177 7408 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 7409 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
<> 161:2cc1468da177 7410 #define EXTI_EMR_MR23_Pos (23U)
<> 161:2cc1468da177 7411 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 7412 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
<> 161:2cc1468da177 7413 #define EXTI_EMR_MR24_Pos (24U)
<> 161:2cc1468da177 7414 #define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 7415 #define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
<> 144:ef7eb2e8f9f7 7416
<> 144:ef7eb2e8f9f7 7417 /* Reference Defines */
<> 161:2cc1468da177 7418 #define EXTI_EMR_EM0 EXTI_EMR_MR0
<> 161:2cc1468da177 7419 #define EXTI_EMR_EM1 EXTI_EMR_MR1
<> 161:2cc1468da177 7420 #define EXTI_EMR_EM2 EXTI_EMR_MR2
<> 161:2cc1468da177 7421 #define EXTI_EMR_EM3 EXTI_EMR_MR3
<> 161:2cc1468da177 7422 #define EXTI_EMR_EM4 EXTI_EMR_MR4
<> 161:2cc1468da177 7423 #define EXTI_EMR_EM5 EXTI_EMR_MR5
<> 161:2cc1468da177 7424 #define EXTI_EMR_EM6 EXTI_EMR_MR6
<> 161:2cc1468da177 7425 #define EXTI_EMR_EM7 EXTI_EMR_MR7
<> 161:2cc1468da177 7426 #define EXTI_EMR_EM8 EXTI_EMR_MR8
<> 161:2cc1468da177 7427 #define EXTI_EMR_EM9 EXTI_EMR_MR9
<> 144:ef7eb2e8f9f7 7428 #define EXTI_EMR_EM10 EXTI_EMR_MR10
<> 144:ef7eb2e8f9f7 7429 #define EXTI_EMR_EM11 EXTI_EMR_MR11
<> 144:ef7eb2e8f9f7 7430 #define EXTI_EMR_EM12 EXTI_EMR_MR12
<> 144:ef7eb2e8f9f7 7431 #define EXTI_EMR_EM13 EXTI_EMR_MR13
<> 144:ef7eb2e8f9f7 7432 #define EXTI_EMR_EM14 EXTI_EMR_MR14
<> 144:ef7eb2e8f9f7 7433 #define EXTI_EMR_EM15 EXTI_EMR_MR15
<> 144:ef7eb2e8f9f7 7434 #define EXTI_EMR_EM16 EXTI_EMR_MR16
<> 144:ef7eb2e8f9f7 7435 #define EXTI_EMR_EM17 EXTI_EMR_MR17
<> 144:ef7eb2e8f9f7 7436 #define EXTI_EMR_EM18 EXTI_EMR_MR18
<> 144:ef7eb2e8f9f7 7437 #define EXTI_EMR_EM19 EXTI_EMR_MR19
<> 144:ef7eb2e8f9f7 7438 #define EXTI_EMR_EM20 EXTI_EMR_MR20
<> 144:ef7eb2e8f9f7 7439 #define EXTI_EMR_EM21 EXTI_EMR_MR21
<> 144:ef7eb2e8f9f7 7440 #define EXTI_EMR_EM22 EXTI_EMR_MR22
<> 144:ef7eb2e8f9f7 7441 #define EXTI_EMR_EM23 EXTI_EMR_MR23
<> 144:ef7eb2e8f9f7 7442 #define EXTI_EMR_EM24 EXTI_EMR_MR24
<> 144:ef7eb2e8f9f7 7443
<> 144:ef7eb2e8f9f7 7444
<> 144:ef7eb2e8f9f7 7445 /****************** Bit definition for EXTI_RTSR register *******************/
<> 161:2cc1468da177 7446 #define EXTI_RTSR_TR0_Pos (0U)
<> 161:2cc1468da177 7447 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7448 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
<> 161:2cc1468da177 7449 #define EXTI_RTSR_TR1_Pos (1U)
<> 161:2cc1468da177 7450 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7451 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
<> 161:2cc1468da177 7452 #define EXTI_RTSR_TR2_Pos (2U)
<> 161:2cc1468da177 7453 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7454 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
<> 161:2cc1468da177 7455 #define EXTI_RTSR_TR3_Pos (3U)
<> 161:2cc1468da177 7456 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 7457 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
<> 161:2cc1468da177 7458 #define EXTI_RTSR_TR4_Pos (4U)
<> 161:2cc1468da177 7459 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7460 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
<> 161:2cc1468da177 7461 #define EXTI_RTSR_TR5_Pos (5U)
<> 161:2cc1468da177 7462 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7463 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
<> 161:2cc1468da177 7464 #define EXTI_RTSR_TR6_Pos (6U)
<> 161:2cc1468da177 7465 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 7466 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
<> 161:2cc1468da177 7467 #define EXTI_RTSR_TR7_Pos (7U)
<> 161:2cc1468da177 7468 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 7469 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
<> 161:2cc1468da177 7470 #define EXTI_RTSR_TR8_Pos (8U)
<> 161:2cc1468da177 7471 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 7472 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
<> 161:2cc1468da177 7473 #define EXTI_RTSR_TR9_Pos (9U)
<> 161:2cc1468da177 7474 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 7475 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
<> 161:2cc1468da177 7476 #define EXTI_RTSR_TR10_Pos (10U)
<> 161:2cc1468da177 7477 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 7478 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
<> 161:2cc1468da177 7479 #define EXTI_RTSR_TR11_Pos (11U)
<> 161:2cc1468da177 7480 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 7481 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
<> 161:2cc1468da177 7482 #define EXTI_RTSR_TR12_Pos (12U)
<> 161:2cc1468da177 7483 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 7484 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
<> 161:2cc1468da177 7485 #define EXTI_RTSR_TR13_Pos (13U)
<> 161:2cc1468da177 7486 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 7487 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
<> 161:2cc1468da177 7488 #define EXTI_RTSR_TR14_Pos (14U)
<> 161:2cc1468da177 7489 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 7490 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
<> 161:2cc1468da177 7491 #define EXTI_RTSR_TR15_Pos (15U)
<> 161:2cc1468da177 7492 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 7493 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
<> 161:2cc1468da177 7494 #define EXTI_RTSR_TR16_Pos (16U)
<> 161:2cc1468da177 7495 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7496 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
<> 161:2cc1468da177 7497 #define EXTI_RTSR_TR17_Pos (17U)
<> 161:2cc1468da177 7498 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 7499 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
<> 161:2cc1468da177 7500 #define EXTI_RTSR_TR18_Pos (18U)
<> 161:2cc1468da177 7501 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 7502 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
<> 161:2cc1468da177 7503 #define EXTI_RTSR_TR19_Pos (19U)
<> 161:2cc1468da177 7504 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 7505 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
<> 161:2cc1468da177 7506 #define EXTI_RTSR_TR20_Pos (20U)
<> 161:2cc1468da177 7507 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 7508 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
<> 161:2cc1468da177 7509 #define EXTI_RTSR_TR21_Pos (21U)
<> 161:2cc1468da177 7510 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 7511 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
<> 161:2cc1468da177 7512 #define EXTI_RTSR_TR22_Pos (22U)
<> 161:2cc1468da177 7513 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 7514 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
<> 161:2cc1468da177 7515 #define EXTI_RTSR_TR23_Pos (23U)
<> 161:2cc1468da177 7516 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 7517 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
<> 161:2cc1468da177 7518 #define EXTI_RTSR_TR24_Pos (24U)
<> 161:2cc1468da177 7519 #define EXTI_RTSR_TR24_Msk (0x1U << EXTI_RTSR_TR24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 7520 #define EXTI_RTSR_TR24 EXTI_RTSR_TR24_Msk /*!< Rising trigger event configuration bit of line 24 */
<> 144:ef7eb2e8f9f7 7521
<> 144:ef7eb2e8f9f7 7522 /****************** Bit definition for EXTI_FTSR register *******************/
<> 161:2cc1468da177 7523 #define EXTI_FTSR_TR0_Pos (0U)
<> 161:2cc1468da177 7524 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7525 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
<> 161:2cc1468da177 7526 #define EXTI_FTSR_TR1_Pos (1U)
<> 161:2cc1468da177 7527 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7528 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
<> 161:2cc1468da177 7529 #define EXTI_FTSR_TR2_Pos (2U)
<> 161:2cc1468da177 7530 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7531 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
<> 161:2cc1468da177 7532 #define EXTI_FTSR_TR3_Pos (3U)
<> 161:2cc1468da177 7533 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 7534 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
<> 161:2cc1468da177 7535 #define EXTI_FTSR_TR4_Pos (4U)
<> 161:2cc1468da177 7536 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7537 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
<> 161:2cc1468da177 7538 #define EXTI_FTSR_TR5_Pos (5U)
<> 161:2cc1468da177 7539 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7540 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
<> 161:2cc1468da177 7541 #define EXTI_FTSR_TR6_Pos (6U)
<> 161:2cc1468da177 7542 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 7543 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
<> 161:2cc1468da177 7544 #define EXTI_FTSR_TR7_Pos (7U)
<> 161:2cc1468da177 7545 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 7546 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
<> 161:2cc1468da177 7547 #define EXTI_FTSR_TR8_Pos (8U)
<> 161:2cc1468da177 7548 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 7549 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
<> 161:2cc1468da177 7550 #define EXTI_FTSR_TR9_Pos (9U)
<> 161:2cc1468da177 7551 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 7552 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
<> 161:2cc1468da177 7553 #define EXTI_FTSR_TR10_Pos (10U)
<> 161:2cc1468da177 7554 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 7555 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
<> 161:2cc1468da177 7556 #define EXTI_FTSR_TR11_Pos (11U)
<> 161:2cc1468da177 7557 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 7558 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
<> 161:2cc1468da177 7559 #define EXTI_FTSR_TR12_Pos (12U)
<> 161:2cc1468da177 7560 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 7561 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
<> 161:2cc1468da177 7562 #define EXTI_FTSR_TR13_Pos (13U)
<> 161:2cc1468da177 7563 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 7564 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
<> 161:2cc1468da177 7565 #define EXTI_FTSR_TR14_Pos (14U)
<> 161:2cc1468da177 7566 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 7567 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
<> 161:2cc1468da177 7568 #define EXTI_FTSR_TR15_Pos (15U)
<> 161:2cc1468da177 7569 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 7570 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
<> 161:2cc1468da177 7571 #define EXTI_FTSR_TR16_Pos (16U)
<> 161:2cc1468da177 7572 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7573 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
<> 161:2cc1468da177 7574 #define EXTI_FTSR_TR17_Pos (17U)
<> 161:2cc1468da177 7575 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 7576 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
<> 161:2cc1468da177 7577 #define EXTI_FTSR_TR18_Pos (18U)
<> 161:2cc1468da177 7578 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 7579 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
<> 161:2cc1468da177 7580 #define EXTI_FTSR_TR19_Pos (19U)
<> 161:2cc1468da177 7581 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 7582 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
<> 161:2cc1468da177 7583 #define EXTI_FTSR_TR20_Pos (20U)
<> 161:2cc1468da177 7584 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 7585 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
<> 161:2cc1468da177 7586 #define EXTI_FTSR_TR21_Pos (21U)
<> 161:2cc1468da177 7587 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 7588 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
<> 161:2cc1468da177 7589 #define EXTI_FTSR_TR22_Pos (22U)
<> 161:2cc1468da177 7590 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 7591 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
<> 161:2cc1468da177 7592 #define EXTI_FTSR_TR23_Pos (23U)
<> 161:2cc1468da177 7593 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 7594 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
<> 161:2cc1468da177 7595 #define EXTI_FTSR_TR24_Pos (24U)
<> 161:2cc1468da177 7596 #define EXTI_FTSR_TR24_Msk (0x1U << EXTI_FTSR_TR24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 7597 #define EXTI_FTSR_TR24 EXTI_FTSR_TR24_Msk /*!< Falling trigger event configuration bit of line 24 */
<> 144:ef7eb2e8f9f7 7598
<> 144:ef7eb2e8f9f7 7599 /****************** Bit definition for EXTI_SWIER register ******************/
<> 161:2cc1468da177 7600 #define EXTI_SWIER_SWIER0_Pos (0U)
<> 161:2cc1468da177 7601 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7602 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
<> 161:2cc1468da177 7603 #define EXTI_SWIER_SWIER1_Pos (1U)
<> 161:2cc1468da177 7604 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7605 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
<> 161:2cc1468da177 7606 #define EXTI_SWIER_SWIER2_Pos (2U)
<> 161:2cc1468da177 7607 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7608 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
<> 161:2cc1468da177 7609 #define EXTI_SWIER_SWIER3_Pos (3U)
<> 161:2cc1468da177 7610 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 7611 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
<> 161:2cc1468da177 7612 #define EXTI_SWIER_SWIER4_Pos (4U)
<> 161:2cc1468da177 7613 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7614 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
<> 161:2cc1468da177 7615 #define EXTI_SWIER_SWIER5_Pos (5U)
<> 161:2cc1468da177 7616 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7617 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
<> 161:2cc1468da177 7618 #define EXTI_SWIER_SWIER6_Pos (6U)
<> 161:2cc1468da177 7619 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 7620 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
<> 161:2cc1468da177 7621 #define EXTI_SWIER_SWIER7_Pos (7U)
<> 161:2cc1468da177 7622 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 7623 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
<> 161:2cc1468da177 7624 #define EXTI_SWIER_SWIER8_Pos (8U)
<> 161:2cc1468da177 7625 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 7626 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
<> 161:2cc1468da177 7627 #define EXTI_SWIER_SWIER9_Pos (9U)
<> 161:2cc1468da177 7628 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 7629 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
<> 161:2cc1468da177 7630 #define EXTI_SWIER_SWIER10_Pos (10U)
<> 161:2cc1468da177 7631 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 7632 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
<> 161:2cc1468da177 7633 #define EXTI_SWIER_SWIER11_Pos (11U)
<> 161:2cc1468da177 7634 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 7635 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
<> 161:2cc1468da177 7636 #define EXTI_SWIER_SWIER12_Pos (12U)
<> 161:2cc1468da177 7637 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 7638 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
<> 161:2cc1468da177 7639 #define EXTI_SWIER_SWIER13_Pos (13U)
<> 161:2cc1468da177 7640 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 7641 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
<> 161:2cc1468da177 7642 #define EXTI_SWIER_SWIER14_Pos (14U)
<> 161:2cc1468da177 7643 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 7644 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
<> 161:2cc1468da177 7645 #define EXTI_SWIER_SWIER15_Pos (15U)
<> 161:2cc1468da177 7646 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 7647 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
<> 161:2cc1468da177 7648 #define EXTI_SWIER_SWIER16_Pos (16U)
<> 161:2cc1468da177 7649 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7650 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
<> 161:2cc1468da177 7651 #define EXTI_SWIER_SWIER17_Pos (17U)
<> 161:2cc1468da177 7652 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 7653 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
<> 161:2cc1468da177 7654 #define EXTI_SWIER_SWIER18_Pos (18U)
<> 161:2cc1468da177 7655 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 7656 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
<> 161:2cc1468da177 7657 #define EXTI_SWIER_SWIER19_Pos (19U)
<> 161:2cc1468da177 7658 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 7659 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
<> 161:2cc1468da177 7660 #define EXTI_SWIER_SWIER20_Pos (20U)
<> 161:2cc1468da177 7661 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 7662 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
<> 161:2cc1468da177 7663 #define EXTI_SWIER_SWIER21_Pos (21U)
<> 161:2cc1468da177 7664 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 7665 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
<> 161:2cc1468da177 7666 #define EXTI_SWIER_SWIER22_Pos (22U)
<> 161:2cc1468da177 7667 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 7668 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
<> 161:2cc1468da177 7669 #define EXTI_SWIER_SWIER23_Pos (23U)
<> 161:2cc1468da177 7670 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 7671 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
<> 161:2cc1468da177 7672 #define EXTI_SWIER_SWIER24_Pos (24U)
<> 161:2cc1468da177 7673 #define EXTI_SWIER_SWIER24_Msk (0x1U << EXTI_SWIER_SWIER24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 7674 #define EXTI_SWIER_SWIER24 EXTI_SWIER_SWIER24_Msk /*!< Software Interrupt on line 24 */
<> 144:ef7eb2e8f9f7 7675
<> 144:ef7eb2e8f9f7 7676 /******************* Bit definition for EXTI_PR register ********************/
<> 161:2cc1468da177 7677 #define EXTI_PR_PR0_Pos (0U)
<> 161:2cc1468da177 7678 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7679 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
<> 161:2cc1468da177 7680 #define EXTI_PR_PR1_Pos (1U)
<> 161:2cc1468da177 7681 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7682 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
<> 161:2cc1468da177 7683 #define EXTI_PR_PR2_Pos (2U)
<> 161:2cc1468da177 7684 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7685 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
<> 161:2cc1468da177 7686 #define EXTI_PR_PR3_Pos (3U)
<> 161:2cc1468da177 7687 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 7688 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
<> 161:2cc1468da177 7689 #define EXTI_PR_PR4_Pos (4U)
<> 161:2cc1468da177 7690 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7691 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
<> 161:2cc1468da177 7692 #define EXTI_PR_PR5_Pos (5U)
<> 161:2cc1468da177 7693 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7694 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
<> 161:2cc1468da177 7695 #define EXTI_PR_PR6_Pos (6U)
<> 161:2cc1468da177 7696 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 7697 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
<> 161:2cc1468da177 7698 #define EXTI_PR_PR7_Pos (7U)
<> 161:2cc1468da177 7699 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 7700 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
<> 161:2cc1468da177 7701 #define EXTI_PR_PR8_Pos (8U)
<> 161:2cc1468da177 7702 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 7703 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
<> 161:2cc1468da177 7704 #define EXTI_PR_PR9_Pos (9U)
<> 161:2cc1468da177 7705 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 7706 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
<> 161:2cc1468da177 7707 #define EXTI_PR_PR10_Pos (10U)
<> 161:2cc1468da177 7708 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 7709 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
<> 161:2cc1468da177 7710 #define EXTI_PR_PR11_Pos (11U)
<> 161:2cc1468da177 7711 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 7712 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
<> 161:2cc1468da177 7713 #define EXTI_PR_PR12_Pos (12U)
<> 161:2cc1468da177 7714 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 7715 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
<> 161:2cc1468da177 7716 #define EXTI_PR_PR13_Pos (13U)
<> 161:2cc1468da177 7717 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 7718 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
<> 161:2cc1468da177 7719 #define EXTI_PR_PR14_Pos (14U)
<> 161:2cc1468da177 7720 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 7721 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
<> 161:2cc1468da177 7722 #define EXTI_PR_PR15_Pos (15U)
<> 161:2cc1468da177 7723 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 7724 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
<> 161:2cc1468da177 7725 #define EXTI_PR_PR16_Pos (16U)
<> 161:2cc1468da177 7726 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7727 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
<> 161:2cc1468da177 7728 #define EXTI_PR_PR17_Pos (17U)
<> 161:2cc1468da177 7729 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 7730 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
<> 161:2cc1468da177 7731 #define EXTI_PR_PR18_Pos (18U)
<> 161:2cc1468da177 7732 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 7733 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
<> 161:2cc1468da177 7734 #define EXTI_PR_PR19_Pos (19U)
<> 161:2cc1468da177 7735 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 7736 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
<> 161:2cc1468da177 7737 #define EXTI_PR_PR20_Pos (20U)
<> 161:2cc1468da177 7738 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 7739 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
<> 161:2cc1468da177 7740 #define EXTI_PR_PR21_Pos (21U)
<> 161:2cc1468da177 7741 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 7742 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
<> 161:2cc1468da177 7743 #define EXTI_PR_PR22_Pos (22U)
<> 161:2cc1468da177 7744 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 7745 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
<> 161:2cc1468da177 7746 #define EXTI_PR_PR23_Pos (23U)
<> 161:2cc1468da177 7747 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 7748 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
<> 161:2cc1468da177 7749 #define EXTI_PR_PR24_Pos (24U)
<> 161:2cc1468da177 7750 #define EXTI_PR_PR24_Msk (0x1U << EXTI_PR_PR24_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 7751 #define EXTI_PR_PR24 EXTI_PR_PR24_Msk /*!< Pending bit for line 24 */
<> 144:ef7eb2e8f9f7 7752
<> 144:ef7eb2e8f9f7 7753 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7754 /* */
<> 144:ef7eb2e8f9f7 7755 /* FLASH */
<> 144:ef7eb2e8f9f7 7756 /* */
<> 144:ef7eb2e8f9f7 7757 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7758 /*
<> 144:ef7eb2e8f9f7 7759 * @brief FLASH Total Sectors Number
<> 144:ef7eb2e8f9f7 7760 */
<> 144:ef7eb2e8f9f7 7761 #define FLASH_SECTOR_TOTAL 24
<> 144:ef7eb2e8f9f7 7762
<> 144:ef7eb2e8f9f7 7763 /******************* Bits definition for FLASH_ACR register *****************/
<> 161:2cc1468da177 7764 #define FLASH_ACR_LATENCY_Pos (0U)
<> 161:2cc1468da177 7765 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 7766 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
<> 161:2cc1468da177 7767 #define FLASH_ACR_LATENCY_0WS 0x00000000U
<> 161:2cc1468da177 7768 #define FLASH_ACR_LATENCY_1WS 0x00000001U
<> 161:2cc1468da177 7769 #define FLASH_ACR_LATENCY_2WS 0x00000002U
<> 161:2cc1468da177 7770 #define FLASH_ACR_LATENCY_3WS 0x00000003U
<> 161:2cc1468da177 7771 #define FLASH_ACR_LATENCY_4WS 0x00000004U
<> 161:2cc1468da177 7772 #define FLASH_ACR_LATENCY_5WS 0x00000005U
<> 161:2cc1468da177 7773 #define FLASH_ACR_LATENCY_6WS 0x00000006U
<> 161:2cc1468da177 7774 #define FLASH_ACR_LATENCY_7WS 0x00000007U
<> 161:2cc1468da177 7775 #define FLASH_ACR_LATENCY_8WS 0x00000008U
<> 161:2cc1468da177 7776 #define FLASH_ACR_LATENCY_9WS 0x00000009U
<> 161:2cc1468da177 7777 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
<> 161:2cc1468da177 7778 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
<> 161:2cc1468da177 7779 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
<> 161:2cc1468da177 7780 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
<> 161:2cc1468da177 7781 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
<> 161:2cc1468da177 7782 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
<> 161:2cc1468da177 7783 #define FLASH_ACR_PRFTEN_Pos (8U)
<> 161:2cc1468da177 7784 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 7785 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
<> 161:2cc1468da177 7786 #define FLASH_ACR_ARTEN_Pos (9U)
<> 161:2cc1468da177 7787 #define FLASH_ACR_ARTEN_Msk (0x1U << FLASH_ACR_ARTEN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 7788 #define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk
<> 161:2cc1468da177 7789 #define FLASH_ACR_ARTRST_Pos (11U)
<> 161:2cc1468da177 7790 #define FLASH_ACR_ARTRST_Msk (0x1U << FLASH_ACR_ARTRST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 7791 #define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk
<> 144:ef7eb2e8f9f7 7792
<> 144:ef7eb2e8f9f7 7793 /******************* Bits definition for FLASH_SR register ******************/
<> 161:2cc1468da177 7794 #define FLASH_SR_EOP_Pos (0U)
<> 161:2cc1468da177 7795 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7796 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
<> 161:2cc1468da177 7797 #define FLASH_SR_OPERR_Pos (1U)
<> 161:2cc1468da177 7798 #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7799 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
<> 161:2cc1468da177 7800 #define FLASH_SR_WRPERR_Pos (4U)
<> 161:2cc1468da177 7801 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7802 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
<> 161:2cc1468da177 7803 #define FLASH_SR_PGAERR_Pos (5U)
<> 161:2cc1468da177 7804 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7805 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
<> 161:2cc1468da177 7806 #define FLASH_SR_PGPERR_Pos (6U)
<> 161:2cc1468da177 7807 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 7808 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
<> 161:2cc1468da177 7809 #define FLASH_SR_ERSERR_Pos (7U)
<> 161:2cc1468da177 7810 #define FLASH_SR_ERSERR_Msk (0x1U << FLASH_SR_ERSERR_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 7811 #define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk
<> 161:2cc1468da177 7812 #define FLASH_SR_BSY_Pos (16U)
<> 161:2cc1468da177 7813 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7814 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
<> 144:ef7eb2e8f9f7 7815
<> 144:ef7eb2e8f9f7 7816 /******************* Bits definition for FLASH_CR register ******************/
<> 161:2cc1468da177 7817 #define FLASH_CR_PG_Pos (0U)
<> 161:2cc1468da177 7818 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7819 #define FLASH_CR_PG FLASH_CR_PG_Msk
<> 161:2cc1468da177 7820 #define FLASH_CR_SER_Pos (1U)
<> 161:2cc1468da177 7821 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7822 #define FLASH_CR_SER FLASH_CR_SER_Msk
<> 161:2cc1468da177 7823 #define FLASH_CR_MER_Pos (2U)
<> 161:2cc1468da177 7824 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7825 #define FLASH_CR_MER FLASH_CR_MER_Msk
<> 144:ef7eb2e8f9f7 7826 #define FLASH_CR_MER1 FLASH_CR_MER
<> 161:2cc1468da177 7827 #define FLASH_CR_SNB_Pos (3U)
<> 161:2cc1468da177 7828 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
<> 161:2cc1468da177 7829 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
<> 161:2cc1468da177 7830 #define FLASH_CR_SNB_0 0x00000008U
<> 161:2cc1468da177 7831 #define FLASH_CR_SNB_1 0x00000010U
<> 161:2cc1468da177 7832 #define FLASH_CR_SNB_2 0x00000020U
<> 161:2cc1468da177 7833 #define FLASH_CR_SNB_3 0x00000040U
<> 161:2cc1468da177 7834 #define FLASH_CR_SNB_4 0x00000080U
<> 161:2cc1468da177 7835 #define FLASH_CR_PSIZE_Pos (8U)
<> 161:2cc1468da177 7836 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 7837 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
<> 161:2cc1468da177 7838 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 7839 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 7840 #define FLASH_CR_MER2_Pos (15U)
<> 161:2cc1468da177 7841 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 7842 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
<> 161:2cc1468da177 7843 #define FLASH_CR_STRT_Pos (16U)
<> 161:2cc1468da177 7844 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7845 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
<> 161:2cc1468da177 7846 #define FLASH_CR_EOPIE_Pos (24U)
<> 161:2cc1468da177 7847 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 7848 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
<> 161:2cc1468da177 7849 #define FLASH_CR_ERRIE_Pos (25U)
<> 161:2cc1468da177 7850 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 7851 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
<> 161:2cc1468da177 7852 #define FLASH_CR_LOCK_Pos (31U)
<> 161:2cc1468da177 7853 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 7854 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
<> 144:ef7eb2e8f9f7 7855
<> 144:ef7eb2e8f9f7 7856 /******************* Bits definition for FLASH_OPTCR register ***************/
<> 161:2cc1468da177 7857 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
<> 161:2cc1468da177 7858 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7859 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
<> 161:2cc1468da177 7860 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
<> 161:2cc1468da177 7861 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7862 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
<> 161:2cc1468da177 7863 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
<> 161:2cc1468da177 7864 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 7865 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
<> 161:2cc1468da177 7866 #define FLASH_OPTCR_BOR_LEV_0 (0x1U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7867 #define FLASH_OPTCR_BOR_LEV_1 (0x2U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 7868 #define FLASH_OPTCR_WWDG_SW_Pos (4U)
<> 161:2cc1468da177 7869 #define FLASH_OPTCR_WWDG_SW_Msk (0x1U << FLASH_OPTCR_WWDG_SW_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7870 #define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk
<> 161:2cc1468da177 7871 #define FLASH_OPTCR_IWDG_SW_Pos (5U)
<> 161:2cc1468da177 7872 #define FLASH_OPTCR_IWDG_SW_Msk (0x1U << FLASH_OPTCR_IWDG_SW_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7873 #define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk
<> 161:2cc1468da177 7874 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
<> 161:2cc1468da177 7875 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 7876 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
<> 161:2cc1468da177 7877 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
<> 161:2cc1468da177 7878 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 7879 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
<> 161:2cc1468da177 7880 #define FLASH_OPTCR_RDP_Pos (8U)
<> 161:2cc1468da177 7881 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 7882 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
<> 161:2cc1468da177 7883 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 7884 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 7885 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 7886 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 7887 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 7888 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 7889 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 7890 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 7891 #define FLASH_OPTCR_nWRP_Pos (16U)
<> 161:2cc1468da177 7892 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
<> 161:2cc1468da177 7893 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
<> 161:2cc1468da177 7894 #define FLASH_OPTCR_nWRP_0 0x00010000U
<> 161:2cc1468da177 7895 #define FLASH_OPTCR_nWRP_1 0x00020000U
<> 161:2cc1468da177 7896 #define FLASH_OPTCR_nWRP_2 0x00040000U
<> 161:2cc1468da177 7897 #define FLASH_OPTCR_nWRP_3 0x00080000U
<> 161:2cc1468da177 7898 #define FLASH_OPTCR_nWRP_4 0x00100000U
<> 161:2cc1468da177 7899 #define FLASH_OPTCR_nWRP_5 0x00200000U
<> 161:2cc1468da177 7900 #define FLASH_OPTCR_nWRP_6 0x00400000U
<> 161:2cc1468da177 7901 #define FLASH_OPTCR_nWRP_7 0x00800000U
<> 161:2cc1468da177 7902 #define FLASH_OPTCR_nWRP_8 0x01000000U
<> 161:2cc1468da177 7903 #define FLASH_OPTCR_nWRP_9 0x02000000U
<> 161:2cc1468da177 7904 #define FLASH_OPTCR_nWRP_10 0x04000000U
<> 161:2cc1468da177 7905 #define FLASH_OPTCR_nWRP_11 0x08000000U
<> 161:2cc1468da177 7906 #define FLASH_OPTCR_nDBOOT_Pos (28U)
<> 161:2cc1468da177 7907 #define FLASH_OPTCR_nDBOOT_Msk (0x1U << FLASH_OPTCR_nDBOOT_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 7908 #define FLASH_OPTCR_nDBOOT FLASH_OPTCR_nDBOOT_Msk
<> 161:2cc1468da177 7909 #define FLASH_OPTCR_nDBANK_Pos (29U)
<> 161:2cc1468da177 7910 #define FLASH_OPTCR_nDBANK_Msk (0x1U << FLASH_OPTCR_nDBANK_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 7911 #define FLASH_OPTCR_nDBANK FLASH_OPTCR_nDBANK_Msk
<> 161:2cc1468da177 7912 #define FLASH_OPTCR_IWDG_STDBY_Pos (30U)
<> 161:2cc1468da177 7913 #define FLASH_OPTCR_IWDG_STDBY_Msk (0x1U << FLASH_OPTCR_IWDG_STDBY_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 7914 #define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk
<> 161:2cc1468da177 7915 #define FLASH_OPTCR_IWDG_STOP_Pos (31U)
<> 161:2cc1468da177 7916 #define FLASH_OPTCR_IWDG_STOP_Msk (0x1U << FLASH_OPTCR_IWDG_STOP_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 7917 #define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk
<> 144:ef7eb2e8f9f7 7918
<> 144:ef7eb2e8f9f7 7919 /******************* Bits definition for FLASH_OPTCR1 register ***************/
<> 161:2cc1468da177 7920 #define FLASH_OPTCR1_BOOT_ADD0_Pos (0U)
<> 161:2cc1468da177 7921 #define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFU << FLASH_OPTCR1_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 7922 #define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk
<> 161:2cc1468da177 7923 #define FLASH_OPTCR1_BOOT_ADD1_Pos (16U)
<> 161:2cc1468da177 7924 #define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFU << FLASH_OPTCR1_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 7925 #define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk
<> 144:ef7eb2e8f9f7 7926
<> 157:ff67d9f36b67 7927
<> 144:ef7eb2e8f9f7 7928 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7929 /* */
<> 144:ef7eb2e8f9f7 7930 /* Flexible Memory Controller */
<> 144:ef7eb2e8f9f7 7931 /* */
<> 144:ef7eb2e8f9f7 7932 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7933 /****************** Bit definition for FMC_BCR1 register *******************/
<> 161:2cc1468da177 7934 #define FMC_BCR1_MBKEN_Pos (0U)
<> 161:2cc1468da177 7935 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7936 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
<> 161:2cc1468da177 7937 #define FMC_BCR1_MUXEN_Pos (1U)
<> 161:2cc1468da177 7938 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7939 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
<> 161:2cc1468da177 7940 #define FMC_BCR1_MTYP_Pos (2U)
<> 161:2cc1468da177 7941 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 7942 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
<> 161:2cc1468da177 7943 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 7944 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 7945 #define FMC_BCR1_MWID_Pos (4U)
<> 161:2cc1468da177 7946 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 7947 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
<> 161:2cc1468da177 7948 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 7949 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 7950 #define FMC_BCR1_FACCEN_Pos (6U)
<> 161:2cc1468da177 7951 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 7952 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
<> 161:2cc1468da177 7953 #define FMC_BCR1_BURSTEN_Pos (8U)
<> 161:2cc1468da177 7954 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 7955 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
<> 161:2cc1468da177 7956 #define FMC_BCR1_WAITPOL_Pos (9U)
<> 161:2cc1468da177 7957 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 7958 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
<> 161:2cc1468da177 7959 #define FMC_BCR1_WRAPMOD_Pos (10U)
<> 161:2cc1468da177 7960 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 7961 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
<> 161:2cc1468da177 7962 #define FMC_BCR1_WAITCFG_Pos (11U)
<> 161:2cc1468da177 7963 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 7964 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
<> 161:2cc1468da177 7965 #define FMC_BCR1_WREN_Pos (12U)
<> 161:2cc1468da177 7966 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 7967 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
<> 161:2cc1468da177 7968 #define FMC_BCR1_WAITEN_Pos (13U)
<> 161:2cc1468da177 7969 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 7970 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
<> 161:2cc1468da177 7971 #define FMC_BCR1_EXTMOD_Pos (14U)
<> 161:2cc1468da177 7972 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 7973 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
<> 161:2cc1468da177 7974 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
<> 161:2cc1468da177 7975 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 7976 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
<> 161:2cc1468da177 7977 #define FMC_BCR1_CPSIZE_Pos (16U)
<> 161:2cc1468da177 7978 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
<> 161:2cc1468da177 7979 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
<> 161:2cc1468da177 7980 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 7981 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 7982 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 7983 #define FMC_BCR1_CBURSTRW_Pos (19U)
<> 161:2cc1468da177 7984 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 7985 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
<> 161:2cc1468da177 7986 #define FMC_BCR1_CCLKEN_Pos (20U)
<> 161:2cc1468da177 7987 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 7988 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
<> 161:2cc1468da177 7989 #define FMC_BCR1_WFDIS_Pos (21U)
<> 161:2cc1468da177 7990 #define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 7991 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
<> 144:ef7eb2e8f9f7 7992
<> 144:ef7eb2e8f9f7 7993 /****************** Bit definition for FMC_BCR2 register *******************/
<> 161:2cc1468da177 7994 #define FMC_BCR2_MBKEN_Pos (0U)
<> 161:2cc1468da177 7995 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 7996 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
<> 161:2cc1468da177 7997 #define FMC_BCR2_MUXEN_Pos (1U)
<> 161:2cc1468da177 7998 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 7999 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
<> 161:2cc1468da177 8000 #define FMC_BCR2_MTYP_Pos (2U)
<> 161:2cc1468da177 8001 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 8002 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
<> 161:2cc1468da177 8003 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8004 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8005 #define FMC_BCR2_MWID_Pos (4U)
<> 161:2cc1468da177 8006 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 8007 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
<> 161:2cc1468da177 8008 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8009 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8010 #define FMC_BCR2_FACCEN_Pos (6U)
<> 161:2cc1468da177 8011 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8012 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
<> 161:2cc1468da177 8013 #define FMC_BCR2_BURSTEN_Pos (8U)
<> 161:2cc1468da177 8014 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8015 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
<> 161:2cc1468da177 8016 #define FMC_BCR2_WAITPOL_Pos (9U)
<> 161:2cc1468da177 8017 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8018 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
<> 161:2cc1468da177 8019 #define FMC_BCR2_WRAPMOD_Pos (10U)
<> 161:2cc1468da177 8020 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8021 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
<> 161:2cc1468da177 8022 #define FMC_BCR2_WAITCFG_Pos (11U)
<> 161:2cc1468da177 8023 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8024 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
<> 161:2cc1468da177 8025 #define FMC_BCR2_WREN_Pos (12U)
<> 161:2cc1468da177 8026 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8027 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
<> 161:2cc1468da177 8028 #define FMC_BCR2_WAITEN_Pos (13U)
<> 161:2cc1468da177 8029 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8030 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
<> 161:2cc1468da177 8031 #define FMC_BCR2_EXTMOD_Pos (14U)
<> 161:2cc1468da177 8032 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8033 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
<> 161:2cc1468da177 8034 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
<> 161:2cc1468da177 8035 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8036 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
<> 161:2cc1468da177 8037 #define FMC_BCR2_CPSIZE_Pos (16U)
<> 161:2cc1468da177 8038 #define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
<> 161:2cc1468da177 8039 #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
<> 161:2cc1468da177 8040 #define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8041 #define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8042 #define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8043 #define FMC_BCR2_CBURSTRW_Pos (19U)
<> 161:2cc1468da177 8044 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8045 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 8046
<> 144:ef7eb2e8f9f7 8047 /****************** Bit definition for FMC_BCR3 register *******************/
<> 161:2cc1468da177 8048 #define FMC_BCR3_MBKEN_Pos (0U)
<> 161:2cc1468da177 8049 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8050 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
<> 161:2cc1468da177 8051 #define FMC_BCR3_MUXEN_Pos (1U)
<> 161:2cc1468da177 8052 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8053 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
<> 161:2cc1468da177 8054 #define FMC_BCR3_MTYP_Pos (2U)
<> 161:2cc1468da177 8055 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 8056 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
<> 161:2cc1468da177 8057 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8058 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8059 #define FMC_BCR3_MWID_Pos (4U)
<> 161:2cc1468da177 8060 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 8061 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
<> 161:2cc1468da177 8062 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8063 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8064 #define FMC_BCR3_FACCEN_Pos (6U)
<> 161:2cc1468da177 8065 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8066 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
<> 161:2cc1468da177 8067 #define FMC_BCR3_BURSTEN_Pos (8U)
<> 161:2cc1468da177 8068 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8069 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
<> 161:2cc1468da177 8070 #define FMC_BCR3_WAITPOL_Pos (9U)
<> 161:2cc1468da177 8071 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8072 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
<> 161:2cc1468da177 8073 #define FMC_BCR3_WRAPMOD_Pos (10U)
<> 161:2cc1468da177 8074 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8075 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
<> 161:2cc1468da177 8076 #define FMC_BCR3_WAITCFG_Pos (11U)
<> 161:2cc1468da177 8077 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8078 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
<> 161:2cc1468da177 8079 #define FMC_BCR3_WREN_Pos (12U)
<> 161:2cc1468da177 8080 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8081 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
<> 161:2cc1468da177 8082 #define FMC_BCR3_WAITEN_Pos (13U)
<> 161:2cc1468da177 8083 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8084 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
<> 161:2cc1468da177 8085 #define FMC_BCR3_EXTMOD_Pos (14U)
<> 161:2cc1468da177 8086 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8087 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
<> 161:2cc1468da177 8088 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
<> 161:2cc1468da177 8089 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8090 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
<> 161:2cc1468da177 8091 #define FMC_BCR3_CPSIZE_Pos (16U)
<> 161:2cc1468da177 8092 #define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
<> 161:2cc1468da177 8093 #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
<> 161:2cc1468da177 8094 #define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8095 #define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8096 #define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8097 #define FMC_BCR3_CBURSTRW_Pos (19U)
<> 161:2cc1468da177 8098 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8099 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 8100
<> 144:ef7eb2e8f9f7 8101 /****************** Bit definition for FMC_BCR4 register *******************/
<> 161:2cc1468da177 8102 #define FMC_BCR4_MBKEN_Pos (0U)
<> 161:2cc1468da177 8103 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8104 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
<> 161:2cc1468da177 8105 #define FMC_BCR4_MUXEN_Pos (1U)
<> 161:2cc1468da177 8106 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8107 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
<> 161:2cc1468da177 8108 #define FMC_BCR4_MTYP_Pos (2U)
<> 161:2cc1468da177 8109 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 8110 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
<> 161:2cc1468da177 8111 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8112 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8113 #define FMC_BCR4_MWID_Pos (4U)
<> 161:2cc1468da177 8114 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 8115 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
<> 161:2cc1468da177 8116 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8117 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8118 #define FMC_BCR4_FACCEN_Pos (6U)
<> 161:2cc1468da177 8119 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8120 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
<> 161:2cc1468da177 8121 #define FMC_BCR4_BURSTEN_Pos (8U)
<> 161:2cc1468da177 8122 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8123 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
<> 161:2cc1468da177 8124 #define FMC_BCR4_WAITPOL_Pos (9U)
<> 161:2cc1468da177 8125 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8126 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
<> 161:2cc1468da177 8127 #define FMC_BCR4_WRAPMOD_Pos (10U)
<> 161:2cc1468da177 8128 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8129 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
<> 161:2cc1468da177 8130 #define FMC_BCR4_WAITCFG_Pos (11U)
<> 161:2cc1468da177 8131 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8132 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
<> 161:2cc1468da177 8133 #define FMC_BCR4_WREN_Pos (12U)
<> 161:2cc1468da177 8134 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8135 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
<> 161:2cc1468da177 8136 #define FMC_BCR4_WAITEN_Pos (13U)
<> 161:2cc1468da177 8137 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8138 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
<> 161:2cc1468da177 8139 #define FMC_BCR4_EXTMOD_Pos (14U)
<> 161:2cc1468da177 8140 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8141 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
<> 161:2cc1468da177 8142 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
<> 161:2cc1468da177 8143 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8144 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
<> 161:2cc1468da177 8145 #define FMC_BCR4_CPSIZE_Pos (16U)
<> 161:2cc1468da177 8146 #define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
<> 161:2cc1468da177 8147 #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
<> 161:2cc1468da177 8148 #define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8149 #define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8150 #define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8151 #define FMC_BCR4_CBURSTRW_Pos (19U)
<> 161:2cc1468da177 8152 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8153 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 8154
<> 144:ef7eb2e8f9f7 8155 /****************** Bit definition for FMC_BTR1 register ******************/
<> 161:2cc1468da177 8156 #define FMC_BTR1_ADDSET_Pos (0U)
<> 161:2cc1468da177 8157 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 8158 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 161:2cc1468da177 8159 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8160 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8161 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8162 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8163 #define FMC_BTR1_ADDHLD_Pos (4U)
<> 161:2cc1468da177 8164 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 8165 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 161:2cc1468da177 8166 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8167 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8168 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8169 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8170 #define FMC_BTR1_DATAST_Pos (8U)
<> 161:2cc1468da177 8171 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 8172 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 161:2cc1468da177 8173 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8174 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8175 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8176 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8177 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8178 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8179 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8180 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8181 #define FMC_BTR1_BUSTURN_Pos (16U)
<> 161:2cc1468da177 8182 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 8183 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 161:2cc1468da177 8184 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8185 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8186 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8187 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8188 #define FMC_BTR1_CLKDIV_Pos (20U)
<> 161:2cc1468da177 8189 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 8190 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 161:2cc1468da177 8191 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 8192 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 8193 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 8194 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 8195 #define FMC_BTR1_DATLAT_Pos (24U)
<> 161:2cc1468da177 8196 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 8197 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 161:2cc1468da177 8198 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 8199 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 8200 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 8201 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 8202 #define FMC_BTR1_ACCMOD_Pos (28U)
<> 161:2cc1468da177 8203 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 8204 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 161:2cc1468da177 8205 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8206 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 8207
<> 144:ef7eb2e8f9f7 8208 /****************** Bit definition for FMC_BTR2 register *******************/
<> 161:2cc1468da177 8209 #define FMC_BTR2_ADDSET_Pos (0U)
<> 161:2cc1468da177 8210 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 8211 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 161:2cc1468da177 8212 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8213 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8214 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8215 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8216 #define FMC_BTR2_ADDHLD_Pos (4U)
<> 161:2cc1468da177 8217 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 8218 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 161:2cc1468da177 8219 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8220 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8221 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8222 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8223 #define FMC_BTR2_DATAST_Pos (8U)
<> 161:2cc1468da177 8224 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 8225 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 161:2cc1468da177 8226 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8227 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8228 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8229 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8230 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8231 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8232 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8233 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8234 #define FMC_BTR2_BUSTURN_Pos (16U)
<> 161:2cc1468da177 8235 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 8236 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 161:2cc1468da177 8237 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8238 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8239 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8240 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8241 #define FMC_BTR2_CLKDIV_Pos (20U)
<> 161:2cc1468da177 8242 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 8243 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 161:2cc1468da177 8244 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 8245 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 8246 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 8247 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 8248 #define FMC_BTR2_DATLAT_Pos (24U)
<> 161:2cc1468da177 8249 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 8250 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 161:2cc1468da177 8251 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 8252 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 8253 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 8254 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 8255 #define FMC_BTR2_ACCMOD_Pos (28U)
<> 161:2cc1468da177 8256 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 8257 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 161:2cc1468da177 8258 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8259 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 8260
<> 144:ef7eb2e8f9f7 8261 /******************* Bit definition for FMC_BTR3 register *******************/
<> 161:2cc1468da177 8262 #define FMC_BTR3_ADDSET_Pos (0U)
<> 161:2cc1468da177 8263 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 8264 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 161:2cc1468da177 8265 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8266 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8267 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8268 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8269 #define FMC_BTR3_ADDHLD_Pos (4U)
<> 161:2cc1468da177 8270 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 8271 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 161:2cc1468da177 8272 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8273 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8274 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8275 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8276 #define FMC_BTR3_DATAST_Pos (8U)
<> 161:2cc1468da177 8277 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 8278 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 161:2cc1468da177 8279 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8280 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8281 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8282 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8283 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8284 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8285 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8286 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8287 #define FMC_BTR3_BUSTURN_Pos (16U)
<> 161:2cc1468da177 8288 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 8289 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 161:2cc1468da177 8290 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8291 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8292 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8293 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8294 #define FMC_BTR3_CLKDIV_Pos (20U)
<> 161:2cc1468da177 8295 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 8296 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 161:2cc1468da177 8297 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 8298 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 8299 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 8300 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 8301 #define FMC_BTR3_DATLAT_Pos (24U)
<> 161:2cc1468da177 8302 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 8303 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 161:2cc1468da177 8304 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 8305 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 8306 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 8307 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 8308 #define FMC_BTR3_ACCMOD_Pos (28U)
<> 161:2cc1468da177 8309 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 8310 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 161:2cc1468da177 8311 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8312 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 8313
<> 144:ef7eb2e8f9f7 8314 /****************** Bit definition for FMC_BTR4 register *******************/
<> 161:2cc1468da177 8315 #define FMC_BTR4_ADDSET_Pos (0U)
<> 161:2cc1468da177 8316 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 8317 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 161:2cc1468da177 8318 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8319 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8320 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8321 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8322 #define FMC_BTR4_ADDHLD_Pos (4U)
<> 161:2cc1468da177 8323 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 8324 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 161:2cc1468da177 8325 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8326 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8327 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8328 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8329 #define FMC_BTR4_DATAST_Pos (8U)
<> 161:2cc1468da177 8330 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 8331 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 161:2cc1468da177 8332 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8333 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8334 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8335 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8336 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8337 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8338 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8339 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8340 #define FMC_BTR4_BUSTURN_Pos (16U)
<> 161:2cc1468da177 8341 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 8342 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 161:2cc1468da177 8343 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8344 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8345 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8346 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8347 #define FMC_BTR4_CLKDIV_Pos (20U)
<> 161:2cc1468da177 8348 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 8349 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 161:2cc1468da177 8350 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 8351 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 8352 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 8353 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 8354 #define FMC_BTR4_DATLAT_Pos (24U)
<> 161:2cc1468da177 8355 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 8356 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 161:2cc1468da177 8357 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 8358 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 8359 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 8360 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 8361 #define FMC_BTR4_ACCMOD_Pos (28U)
<> 161:2cc1468da177 8362 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 8363 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 161:2cc1468da177 8364 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8365 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 8366
<> 144:ef7eb2e8f9f7 8367 /****************** Bit definition for FMC_BWTR1 register ******************/
<> 161:2cc1468da177 8368 #define FMC_BWTR1_ADDSET_Pos (0U)
<> 161:2cc1468da177 8369 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 8370 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 161:2cc1468da177 8371 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8372 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8373 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8374 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8375 #define FMC_BWTR1_ADDHLD_Pos (4U)
<> 161:2cc1468da177 8376 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 8377 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 161:2cc1468da177 8378 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8379 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8380 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8381 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8382 #define FMC_BWTR1_DATAST_Pos (8U)
<> 161:2cc1468da177 8383 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 8384 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 161:2cc1468da177 8385 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8386 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8387 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8388 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8389 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8390 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8391 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8392 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8393 #define FMC_BWTR1_BUSTURN_Pos (16U)
<> 161:2cc1468da177 8394 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 8395 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 161:2cc1468da177 8396 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8397 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8398 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8399 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8400 #define FMC_BWTR1_ACCMOD_Pos (28U)
<> 161:2cc1468da177 8401 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 8402 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 161:2cc1468da177 8403 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8404 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 8405
<> 144:ef7eb2e8f9f7 8406 /****************** Bit definition for FMC_BWTR2 register ******************/
<> 161:2cc1468da177 8407 #define FMC_BWTR2_ADDSET_Pos (0U)
<> 161:2cc1468da177 8408 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 8409 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 161:2cc1468da177 8410 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8411 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8412 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8413 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8414 #define FMC_BWTR2_ADDHLD_Pos (4U)
<> 161:2cc1468da177 8415 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 8416 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 161:2cc1468da177 8417 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8418 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8419 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8420 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8421 #define FMC_BWTR2_DATAST_Pos (8U)
<> 161:2cc1468da177 8422 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 8423 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 161:2cc1468da177 8424 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8425 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8426 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8427 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8428 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8429 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8430 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8431 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8432 #define FMC_BWTR2_BUSTURN_Pos (16U)
<> 161:2cc1468da177 8433 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 8434 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 161:2cc1468da177 8435 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8436 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8437 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8438 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8439 #define FMC_BWTR2_ACCMOD_Pos (28U)
<> 161:2cc1468da177 8440 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 8441 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 161:2cc1468da177 8442 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8443 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 8444
<> 144:ef7eb2e8f9f7 8445 /****************** Bit definition for FMC_BWTR3 register ******************/
<> 161:2cc1468da177 8446 #define FMC_BWTR3_ADDSET_Pos (0U)
<> 161:2cc1468da177 8447 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 8448 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 161:2cc1468da177 8449 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8450 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8451 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8452 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8453 #define FMC_BWTR3_ADDHLD_Pos (4U)
<> 161:2cc1468da177 8454 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 8455 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 161:2cc1468da177 8456 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8457 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8458 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8459 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8460 #define FMC_BWTR3_DATAST_Pos (8U)
<> 161:2cc1468da177 8461 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 8462 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 161:2cc1468da177 8463 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8464 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8465 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8466 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8467 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8468 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8469 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8470 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8471 #define FMC_BWTR3_BUSTURN_Pos (16U)
<> 161:2cc1468da177 8472 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 8473 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 161:2cc1468da177 8474 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8475 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8476 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8477 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8478 #define FMC_BWTR3_ACCMOD_Pos (28U)
<> 161:2cc1468da177 8479 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 8480 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 161:2cc1468da177 8481 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8482 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 8483
<> 144:ef7eb2e8f9f7 8484 /****************** Bit definition for FMC_BWTR4 register ******************/
<> 161:2cc1468da177 8485 #define FMC_BWTR4_ADDSET_Pos (0U)
<> 161:2cc1468da177 8486 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 8487 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 161:2cc1468da177 8488 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8489 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8490 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8491 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8492 #define FMC_BWTR4_ADDHLD_Pos (4U)
<> 161:2cc1468da177 8493 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 8494 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 161:2cc1468da177 8495 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8496 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8497 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8498 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8499 #define FMC_BWTR4_DATAST_Pos (8U)
<> 161:2cc1468da177 8500 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 8501 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 161:2cc1468da177 8502 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8503 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8504 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8505 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8506 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8507 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8508 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8509 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8510 #define FMC_BWTR4_BUSTURN_Pos (16U)
<> 161:2cc1468da177 8511 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 8512 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 161:2cc1468da177 8513 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8514 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8515 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8516 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8517 #define FMC_BWTR4_ACCMOD_Pos (28U)
<> 161:2cc1468da177 8518 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 8519 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 161:2cc1468da177 8520 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8521 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 8522
<> 144:ef7eb2e8f9f7 8523 /****************** Bit definition for FMC_PCR register *******************/
<> 161:2cc1468da177 8524 #define FMC_PCR_PWAITEN_Pos (1U)
<> 161:2cc1468da177 8525 #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8526 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
<> 161:2cc1468da177 8527 #define FMC_PCR_PBKEN_Pos (2U)
<> 161:2cc1468da177 8528 #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8529 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
<> 161:2cc1468da177 8530 #define FMC_PCR_PTYP_Pos (3U)
<> 161:2cc1468da177 8531 #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8532 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
<> 161:2cc1468da177 8533 #define FMC_PCR_PWID_Pos (4U)
<> 161:2cc1468da177 8534 #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 8535 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 161:2cc1468da177 8536 #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8537 #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8538 #define FMC_PCR_ECCEN_Pos (6U)
<> 161:2cc1468da177 8539 #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8540 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
<> 161:2cc1468da177 8541 #define FMC_PCR_TCLR_Pos (9U)
<> 161:2cc1468da177 8542 #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
<> 161:2cc1468da177 8543 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 161:2cc1468da177 8544 #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8545 #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8546 #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8547 #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8548 #define FMC_PCR_TAR_Pos (13U)
<> 161:2cc1468da177 8549 #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
<> 161:2cc1468da177 8550 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
<> 161:2cc1468da177 8551 #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8552 #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8553 #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8554 #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8555 #define FMC_PCR_ECCPS_Pos (17U)
<> 161:2cc1468da177 8556 #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
<> 161:2cc1468da177 8557 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
<> 161:2cc1468da177 8558 #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8559 #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8560 #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8561
<> 144:ef7eb2e8f9f7 8562 /******************* Bit definition for FMC_SR register *******************/
<> 161:2cc1468da177 8563 #define FMC_SR_IRS_Pos (0U)
<> 161:2cc1468da177 8564 #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8565 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
<> 161:2cc1468da177 8566 #define FMC_SR_ILS_Pos (1U)
<> 161:2cc1468da177 8567 #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8568 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
<> 161:2cc1468da177 8569 #define FMC_SR_IFS_Pos (2U)
<> 161:2cc1468da177 8570 #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8571 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
<> 161:2cc1468da177 8572 #define FMC_SR_IREN_Pos (3U)
<> 161:2cc1468da177 8573 #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8574 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
<> 161:2cc1468da177 8575 #define FMC_SR_ILEN_Pos (4U)
<> 161:2cc1468da177 8576 #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8577 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
<> 161:2cc1468da177 8578 #define FMC_SR_IFEN_Pos (5U)
<> 161:2cc1468da177 8579 #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8580 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
<> 161:2cc1468da177 8581 #define FMC_SR_FEMPT_Pos (6U)
<> 161:2cc1468da177 8582 #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8583 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
<> 144:ef7eb2e8f9f7 8584
<> 144:ef7eb2e8f9f7 8585 /****************** Bit definition for FMC_PMEM register ******************/
<> 161:2cc1468da177 8586 #define FMC_PMEM_MEMSET3_Pos (0U)
<> 161:2cc1468da177 8587 #define FMC_PMEM_MEMSET3_Msk (0xFFU << FMC_PMEM_MEMSET3_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 8588 #define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
<> 161:2cc1468da177 8589 #define FMC_PMEM_MEMSET3_0 (0x01U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8590 #define FMC_PMEM_MEMSET3_1 (0x02U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8591 #define FMC_PMEM_MEMSET3_2 (0x04U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8592 #define FMC_PMEM_MEMSET3_3 (0x08U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8593 #define FMC_PMEM_MEMSET3_4 (0x10U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8594 #define FMC_PMEM_MEMSET3_5 (0x20U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8595 #define FMC_PMEM_MEMSET3_6 (0x40U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8596 #define FMC_PMEM_MEMSET3_7 (0x80U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8597 #define FMC_PMEM_MEMWAIT3_Pos (8U)
<> 161:2cc1468da177 8598 #define FMC_PMEM_MEMWAIT3_Msk (0xFFU << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 8599 #define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
<> 161:2cc1468da177 8600 #define FMC_PMEM_MEMWAIT3_0 (0x01U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8601 #define FMC_PMEM_MEMWAIT3_1 (0x02U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8602 #define FMC_PMEM_MEMWAIT3_2 (0x04U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8603 #define FMC_PMEM_MEMWAIT3_3 (0x08U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8604 #define FMC_PMEM_MEMWAIT3_4 (0x10U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8605 #define FMC_PMEM_MEMWAIT3_5 (0x20U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8606 #define FMC_PMEM_MEMWAIT3_6 (0x40U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8607 #define FMC_PMEM_MEMWAIT3_7 (0x80U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8608 #define FMC_PMEM_MEMHOLD3_Pos (16U)
<> 161:2cc1468da177 8609 #define FMC_PMEM_MEMHOLD3_Msk (0xFFU << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 8610 #define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
<> 161:2cc1468da177 8611 #define FMC_PMEM_MEMHOLD3_0 (0x01U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8612 #define FMC_PMEM_MEMHOLD3_1 (0x02U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8613 #define FMC_PMEM_MEMHOLD3_2 (0x04U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8614 #define FMC_PMEM_MEMHOLD3_3 (0x08U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8615 #define FMC_PMEM_MEMHOLD3_4 (0x10U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 8616 #define FMC_PMEM_MEMHOLD3_5 (0x20U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 8617 #define FMC_PMEM_MEMHOLD3_6 (0x40U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 8618 #define FMC_PMEM_MEMHOLD3_7 (0x80U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 8619 #define FMC_PMEM_MEMHIZ3_Pos (24U)
<> 161:2cc1468da177 8620 #define FMC_PMEM_MEMHIZ3_Msk (0xFFU << FMC_PMEM_MEMHIZ3_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 8621 #define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
<> 161:2cc1468da177 8622 #define FMC_PMEM_MEMHIZ3_0 (0x01U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 8623 #define FMC_PMEM_MEMHIZ3_1 (0x02U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 8624 #define FMC_PMEM_MEMHIZ3_2 (0x04U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 8625 #define FMC_PMEM_MEMHIZ3_3 (0x08U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 8626 #define FMC_PMEM_MEMHIZ3_4 (0x10U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8627 #define FMC_PMEM_MEMHIZ3_5 (0x20U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 8628 #define FMC_PMEM_MEMHIZ3_6 (0x40U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 8629 #define FMC_PMEM_MEMHIZ3_7 (0x80U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8630
<> 144:ef7eb2e8f9f7 8631 /****************** Bit definition for FMC_PATT register ******************/
<> 161:2cc1468da177 8632 #define FMC_PATT_ATTSET3_Pos (0U)
<> 161:2cc1468da177 8633 #define FMC_PATT_ATTSET3_Msk (0xFFU << FMC_PATT_ATTSET3_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 8634 #define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
<> 161:2cc1468da177 8635 #define FMC_PATT_ATTSET3_0 (0x01U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8636 #define FMC_PATT_ATTSET3_1 (0x02U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8637 #define FMC_PATT_ATTSET3_2 (0x04U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8638 #define FMC_PATT_ATTSET3_3 (0x08U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8639 #define FMC_PATT_ATTSET3_4 (0x10U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8640 #define FMC_PATT_ATTSET3_5 (0x20U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8641 #define FMC_PATT_ATTSET3_6 (0x40U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8642 #define FMC_PATT_ATTSET3_7 (0x80U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8643 #define FMC_PATT_ATTWAIT3_Pos (8U)
<> 161:2cc1468da177 8644 #define FMC_PATT_ATTWAIT3_Msk (0xFFU << FMC_PATT_ATTWAIT3_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 8645 #define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
<> 161:2cc1468da177 8646 #define FMC_PATT_ATTWAIT3_0 (0x01U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8647 #define FMC_PATT_ATTWAIT3_1 (0x02U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8648 #define FMC_PATT_ATTWAIT3_2 (0x04U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8649 #define FMC_PATT_ATTWAIT3_3 (0x08U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8650 #define FMC_PATT_ATTWAIT3_4 (0x10U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8651 #define FMC_PATT_ATTWAIT3_5 (0x20U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8652 #define FMC_PATT_ATTWAIT3_6 (0x40U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8653 #define FMC_PATT_ATTWAIT3_7 (0x80U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8654 #define FMC_PATT_ATTHOLD3_Pos (16U)
<> 161:2cc1468da177 8655 #define FMC_PATT_ATTHOLD3_Msk (0xFFU << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 8656 #define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
<> 161:2cc1468da177 8657 #define FMC_PATT_ATTHOLD3_0 (0x01U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8658 #define FMC_PATT_ATTHOLD3_1 (0x02U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8659 #define FMC_PATT_ATTHOLD3_2 (0x04U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8660 #define FMC_PATT_ATTHOLD3_3 (0x08U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8661 #define FMC_PATT_ATTHOLD3_4 (0x10U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 8662 #define FMC_PATT_ATTHOLD3_5 (0x20U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 8663 #define FMC_PATT_ATTHOLD3_6 (0x40U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 8664 #define FMC_PATT_ATTHOLD3_7 (0x80U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 8665 #define FMC_PATT_ATTHIZ3_Pos (24U)
<> 161:2cc1468da177 8666 #define FMC_PATT_ATTHIZ3_Msk (0xFFU << FMC_PATT_ATTHIZ3_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 8667 #define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
<> 161:2cc1468da177 8668 #define FMC_PATT_ATTHIZ3_0 (0x01U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 8669 #define FMC_PATT_ATTHIZ3_1 (0x02U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 8670 #define FMC_PATT_ATTHIZ3_2 (0x04U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 8671 #define FMC_PATT_ATTHIZ3_3 (0x08U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 8672 #define FMC_PATT_ATTHIZ3_4 (0x10U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8673 #define FMC_PATT_ATTHIZ3_5 (0x20U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 8674 #define FMC_PATT_ATTHIZ3_6 (0x40U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 8675 #define FMC_PATT_ATTHIZ3_7 (0x80U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8676
<> 144:ef7eb2e8f9f7 8677 /****************** Bit definition for FMC_ECCR register ******************/
<> 161:2cc1468da177 8678 #define FMC_ECCR_ECC3_Pos (0U)
<> 161:2cc1468da177 8679 #define FMC_ECCR_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR_ECC3_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 8680 #define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk /*!<ECC result */
<> 144:ef7eb2e8f9f7 8681
<> 144:ef7eb2e8f9f7 8682 /****************** Bit definition for FMC_SDCR1 register ******************/
<> 161:2cc1468da177 8683 #define FMC_SDCR1_NC_Pos (0U)
<> 161:2cc1468da177 8684 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 8685 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
<> 161:2cc1468da177 8686 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8687 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8688 #define FMC_SDCR1_NR_Pos (2U)
<> 161:2cc1468da177 8689 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 8690 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
<> 161:2cc1468da177 8691 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8692 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8693 #define FMC_SDCR1_MWID_Pos (4U)
<> 161:2cc1468da177 8694 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 8695 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
<> 161:2cc1468da177 8696 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8697 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8698 #define FMC_SDCR1_NB_Pos (6U)
<> 161:2cc1468da177 8699 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8700 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
<> 161:2cc1468da177 8701 #define FMC_SDCR1_CAS_Pos (7U)
<> 161:2cc1468da177 8702 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
<> 161:2cc1468da177 8703 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
<> 161:2cc1468da177 8704 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8705 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8706 #define FMC_SDCR1_WP_Pos (9U)
<> 161:2cc1468da177 8707 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8708 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
<> 161:2cc1468da177 8709 #define FMC_SDCR1_SDCLK_Pos (10U)
<> 161:2cc1468da177 8710 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 8711 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
<> 161:2cc1468da177 8712 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8713 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8714 #define FMC_SDCR1_RBURST_Pos (12U)
<> 161:2cc1468da177 8715 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8716 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
<> 161:2cc1468da177 8717 #define FMC_SDCR1_RPIPE_Pos (13U)
<> 161:2cc1468da177 8718 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
<> 161:2cc1468da177 8719 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
<> 161:2cc1468da177 8720 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8721 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8722
<> 144:ef7eb2e8f9f7 8723 /****************** Bit definition for FMC_SDCR2 register ******************/
<> 161:2cc1468da177 8724 #define FMC_SDCR2_NC_Pos (0U)
<> 161:2cc1468da177 8725 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 8726 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
<> 161:2cc1468da177 8727 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8728 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8729 #define FMC_SDCR2_NR_Pos (2U)
<> 161:2cc1468da177 8730 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 8731 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
<> 161:2cc1468da177 8732 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8733 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8734 #define FMC_SDCR2_MWID_Pos (4U)
<> 161:2cc1468da177 8735 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 8736 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
<> 161:2cc1468da177 8737 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8738 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8739 #define FMC_SDCR2_NB_Pos (6U)
<> 161:2cc1468da177 8740 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8741 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
<> 161:2cc1468da177 8742 #define FMC_SDCR2_CAS_Pos (7U)
<> 161:2cc1468da177 8743 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
<> 161:2cc1468da177 8744 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
<> 161:2cc1468da177 8745 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8746 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8747 #define FMC_SDCR2_WP_Pos (9U)
<> 161:2cc1468da177 8748 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8749 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
<> 161:2cc1468da177 8750 #define FMC_SDCR2_SDCLK_Pos (10U)
<> 161:2cc1468da177 8751 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 8752 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
<> 161:2cc1468da177 8753 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8754 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8755 #define FMC_SDCR2_RBURST_Pos (12U)
<> 161:2cc1468da177 8756 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8757 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
<> 161:2cc1468da177 8758 #define FMC_SDCR2_RPIPE_Pos (13U)
<> 161:2cc1468da177 8759 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
<> 161:2cc1468da177 8760 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
<> 161:2cc1468da177 8761 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8762 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8763
<> 144:ef7eb2e8f9f7 8764 /****************** Bit definition for FMC_SDTR1 register ******************/
<> 161:2cc1468da177 8765 #define FMC_SDTR1_TMRD_Pos (0U)
<> 161:2cc1468da177 8766 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 8767 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
<> 161:2cc1468da177 8768 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8769 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8770 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8771 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8772 #define FMC_SDTR1_TXSR_Pos (4U)
<> 161:2cc1468da177 8773 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 8774 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
<> 161:2cc1468da177 8775 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8776 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8777 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8778 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8779 #define FMC_SDTR1_TRAS_Pos (8U)
<> 161:2cc1468da177 8780 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 8781 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
<> 161:2cc1468da177 8782 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8783 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8784 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8785 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8786 #define FMC_SDTR1_TRC_Pos (12U)
<> 161:2cc1468da177 8787 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 8788 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
<> 161:2cc1468da177 8789 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8790 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8791 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8792 #define FMC_SDTR1_TWR_Pos (16U)
<> 161:2cc1468da177 8793 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 8794 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
<> 161:2cc1468da177 8795 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8796 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8797 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8798 #define FMC_SDTR1_TRP_Pos (20U)
<> 161:2cc1468da177 8799 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 8800 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
<> 161:2cc1468da177 8801 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 8802 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 8803 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 8804 #define FMC_SDTR1_TRCD_Pos (24U)
<> 161:2cc1468da177 8805 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 8806 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
<> 161:2cc1468da177 8807 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 8808 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 8809 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 8810
<> 144:ef7eb2e8f9f7 8811 /****************** Bit definition for FMC_SDTR2 register ******************/
<> 161:2cc1468da177 8812 #define FMC_SDTR2_TMRD_Pos (0U)
<> 161:2cc1468da177 8813 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 8814 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
<> 161:2cc1468da177 8815 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8816 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8817 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8818 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8819 #define FMC_SDTR2_TXSR_Pos (4U)
<> 161:2cc1468da177 8820 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 8821 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
<> 161:2cc1468da177 8822 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8823 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8824 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8825 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8826 #define FMC_SDTR2_TRAS_Pos (8U)
<> 161:2cc1468da177 8827 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 8828 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
<> 161:2cc1468da177 8829 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8830 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8831 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8832 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8833 #define FMC_SDTR2_TRC_Pos (12U)
<> 161:2cc1468da177 8834 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 8835 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
<> 161:2cc1468da177 8836 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8837 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8838 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8839 #define FMC_SDTR2_TWR_Pos (16U)
<> 161:2cc1468da177 8840 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 8841 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
<> 161:2cc1468da177 8842 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8843 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8844 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8845 #define FMC_SDTR2_TRP_Pos (20U)
<> 161:2cc1468da177 8846 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 8847 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
<> 161:2cc1468da177 8848 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 8849 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 8850 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 8851 #define FMC_SDTR2_TRCD_Pos (24U)
<> 161:2cc1468da177 8852 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 8853 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
<> 161:2cc1468da177 8854 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 8855 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 8856 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 8857
<> 144:ef7eb2e8f9f7 8858 /****************** Bit definition for FMC_SDCMR register ******************/
<> 161:2cc1468da177 8859 #define FMC_SDCMR_MODE_Pos (0U)
<> 161:2cc1468da177 8860 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 8861 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
<> 161:2cc1468da177 8862 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8863 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8864 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8865 #define FMC_SDCMR_CTB2_Pos (3U)
<> 161:2cc1468da177 8866 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8867 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
<> 161:2cc1468da177 8868 #define FMC_SDCMR_CTB1_Pos (4U)
<> 161:2cc1468da177 8869 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8870 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
<> 161:2cc1468da177 8871 #define FMC_SDCMR_NRFS_Pos (5U)
<> 161:2cc1468da177 8872 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
<> 161:2cc1468da177 8873 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
<> 161:2cc1468da177 8874 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8875 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8876 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8877 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8878 #define FMC_SDCMR_MRD_Pos (9U)
<> 161:2cc1468da177 8879 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
<> 161:2cc1468da177 8880 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
<> 144:ef7eb2e8f9f7 8881
<> 144:ef7eb2e8f9f7 8882 /****************** Bit definition for FMC_SDRTR register ******************/
<> 161:2cc1468da177 8883 #define FMC_SDRTR_CRE_Pos (0U)
<> 161:2cc1468da177 8884 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8885 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
<> 161:2cc1468da177 8886 #define FMC_SDRTR_COUNT_Pos (1U)
<> 161:2cc1468da177 8887 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
<> 161:2cc1468da177 8888 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
<> 161:2cc1468da177 8889 #define FMC_SDRTR_REIE_Pos (14U)
<> 161:2cc1468da177 8890 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8891 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
<> 144:ef7eb2e8f9f7 8892
<> 144:ef7eb2e8f9f7 8893 /****************** Bit definition for FMC_SDSR register ******************/
<> 161:2cc1468da177 8894 #define FMC_SDSR_RE_Pos (0U)
<> 161:2cc1468da177 8895 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8896 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
<> 161:2cc1468da177 8897 #define FMC_SDSR_MODES1_Pos (1U)
<> 161:2cc1468da177 8898 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
<> 161:2cc1468da177 8899 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
<> 161:2cc1468da177 8900 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8901 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8902 #define FMC_SDSR_MODES2_Pos (3U)
<> 161:2cc1468da177 8903 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
<> 161:2cc1468da177 8904 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
<> 161:2cc1468da177 8905 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8906 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8907 #define FMC_SDSR_BUSY_Pos (5U)
<> 161:2cc1468da177 8908 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8909 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
<> 144:ef7eb2e8f9f7 8910
<> 144:ef7eb2e8f9f7 8911 /******************************************************************************/
<> 144:ef7eb2e8f9f7 8912 /* */
<> 144:ef7eb2e8f9f7 8913 /* General Purpose I/O */
<> 144:ef7eb2e8f9f7 8914 /* */
<> 144:ef7eb2e8f9f7 8915 /******************************************************************************/
<> 144:ef7eb2e8f9f7 8916 /****************** Bits definition for GPIO_MODER register *****************/
<> 161:2cc1468da177 8917 #define GPIO_MODER_MODER0_Pos (0U)
<> 161:2cc1468da177 8918 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 8919 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
<> 161:2cc1468da177 8920 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 8921 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 8922 #define GPIO_MODER_MODER1_Pos (2U)
<> 161:2cc1468da177 8923 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 8924 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
<> 161:2cc1468da177 8925 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 8926 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 8927 #define GPIO_MODER_MODER2_Pos (4U)
<> 161:2cc1468da177 8928 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 8929 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
<> 161:2cc1468da177 8930 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 8931 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 8932 #define GPIO_MODER_MODER3_Pos (6U)
<> 161:2cc1468da177 8933 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 8934 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
<> 161:2cc1468da177 8935 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 8936 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 8937 #define GPIO_MODER_MODER4_Pos (8U)
<> 161:2cc1468da177 8938 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 8939 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
<> 161:2cc1468da177 8940 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 8941 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 8942 #define GPIO_MODER_MODER5_Pos (10U)
<> 161:2cc1468da177 8943 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 8944 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
<> 161:2cc1468da177 8945 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 8946 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 8947 #define GPIO_MODER_MODER6_Pos (12U)
<> 161:2cc1468da177 8948 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
<> 161:2cc1468da177 8949 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
<> 161:2cc1468da177 8950 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 8951 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 8952 #define GPIO_MODER_MODER7_Pos (14U)
<> 161:2cc1468da177 8953 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 8954 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
<> 161:2cc1468da177 8955 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 8956 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 8957 #define GPIO_MODER_MODER8_Pos (16U)
<> 161:2cc1468da177 8958 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 8959 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
<> 161:2cc1468da177 8960 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 8961 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 8962 #define GPIO_MODER_MODER9_Pos (18U)
<> 161:2cc1468da177 8963 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
<> 161:2cc1468da177 8964 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
<> 161:2cc1468da177 8965 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 8966 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 8967 #define GPIO_MODER_MODER10_Pos (20U)
<> 161:2cc1468da177 8968 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 8969 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
<> 161:2cc1468da177 8970 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 8971 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 8972 #define GPIO_MODER_MODER11_Pos (22U)
<> 161:2cc1468da177 8973 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
<> 161:2cc1468da177 8974 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
<> 161:2cc1468da177 8975 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 8976 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 8977 #define GPIO_MODER_MODER12_Pos (24U)
<> 161:2cc1468da177 8978 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
<> 161:2cc1468da177 8979 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
<> 161:2cc1468da177 8980 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 8981 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 8982 #define GPIO_MODER_MODER13_Pos (26U)
<> 161:2cc1468da177 8983 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
<> 161:2cc1468da177 8984 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
<> 161:2cc1468da177 8985 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 8986 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 8987 #define GPIO_MODER_MODER14_Pos (28U)
<> 161:2cc1468da177 8988 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 8989 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
<> 161:2cc1468da177 8990 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 8991 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 8992 #define GPIO_MODER_MODER15_Pos (30U)
<> 161:2cc1468da177 8993 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
<> 161:2cc1468da177 8994 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
<> 161:2cc1468da177 8995 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 8996 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8997
<> 144:ef7eb2e8f9f7 8998 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 161:2cc1468da177 8999 #define GPIO_OTYPER_OT_0 0x00000001U
<> 161:2cc1468da177 9000 #define GPIO_OTYPER_OT_1 0x00000002U
<> 161:2cc1468da177 9001 #define GPIO_OTYPER_OT_2 0x00000004U
<> 161:2cc1468da177 9002 #define GPIO_OTYPER_OT_3 0x00000008U
<> 161:2cc1468da177 9003 #define GPIO_OTYPER_OT_4 0x00000010U
<> 161:2cc1468da177 9004 #define GPIO_OTYPER_OT_5 0x00000020U
<> 161:2cc1468da177 9005 #define GPIO_OTYPER_OT_6 0x00000040U
<> 161:2cc1468da177 9006 #define GPIO_OTYPER_OT_7 0x00000080U
<> 161:2cc1468da177 9007 #define GPIO_OTYPER_OT_8 0x00000100U
<> 161:2cc1468da177 9008 #define GPIO_OTYPER_OT_9 0x00000200U
<> 161:2cc1468da177 9009 #define GPIO_OTYPER_OT_10 0x00000400U
<> 161:2cc1468da177 9010 #define GPIO_OTYPER_OT_11 0x00000800U
<> 161:2cc1468da177 9011 #define GPIO_OTYPER_OT_12 0x00001000U
<> 161:2cc1468da177 9012 #define GPIO_OTYPER_OT_13 0x00002000U
<> 161:2cc1468da177 9013 #define GPIO_OTYPER_OT_14 0x00004000U
<> 161:2cc1468da177 9014 #define GPIO_OTYPER_OT_15 0x00008000U
<> 144:ef7eb2e8f9f7 9015
<> 144:ef7eb2e8f9f7 9016 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 161:2cc1468da177 9017 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
<> 161:2cc1468da177 9018 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 9019 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
<> 161:2cc1468da177 9020 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9021 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9022 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
<> 161:2cc1468da177 9023 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 9024 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
<> 161:2cc1468da177 9025 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9026 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9027 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
<> 161:2cc1468da177 9028 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 9029 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
<> 161:2cc1468da177 9030 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 9031 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 9032 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
<> 161:2cc1468da177 9033 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 9034 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
<> 161:2cc1468da177 9035 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 9036 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 9037 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
<> 161:2cc1468da177 9038 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 9039 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
<> 161:2cc1468da177 9040 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 9041 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 9042 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
<> 161:2cc1468da177 9043 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 9044 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
<> 161:2cc1468da177 9045 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 9046 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 9047 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
<> 161:2cc1468da177 9048 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
<> 161:2cc1468da177 9049 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
<> 161:2cc1468da177 9050 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 9051 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 9052 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
<> 161:2cc1468da177 9053 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 9054 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
<> 161:2cc1468da177 9055 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 9056 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9057 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
<> 161:2cc1468da177 9058 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 9059 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
<> 161:2cc1468da177 9060 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 9061 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 9062 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
<> 161:2cc1468da177 9063 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
<> 161:2cc1468da177 9064 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
<> 161:2cc1468da177 9065 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 9066 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 9067 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
<> 161:2cc1468da177 9068 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 9069 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
<> 161:2cc1468da177 9070 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 9071 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 9072 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
<> 161:2cc1468da177 9073 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
<> 161:2cc1468da177 9074 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
<> 161:2cc1468da177 9075 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 9076 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 9077 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
<> 161:2cc1468da177 9078 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
<> 161:2cc1468da177 9079 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
<> 161:2cc1468da177 9080 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 9081 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 9082 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
<> 161:2cc1468da177 9083 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
<> 161:2cc1468da177 9084 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
<> 161:2cc1468da177 9085 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 9086 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 9087 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
<> 161:2cc1468da177 9088 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 9089 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
<> 161:2cc1468da177 9090 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 9091 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 9092 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
<> 161:2cc1468da177 9093 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
<> 161:2cc1468da177 9094 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
<> 161:2cc1468da177 9095 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 9096 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 9097
<> 144:ef7eb2e8f9f7 9098 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 161:2cc1468da177 9099 #define GPIO_PUPDR_PUPDR0_Pos (0U)
<> 161:2cc1468da177 9100 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 9101 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
<> 161:2cc1468da177 9102 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9103 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9104 #define GPIO_PUPDR_PUPDR1_Pos (2U)
<> 161:2cc1468da177 9105 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 9106 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
<> 161:2cc1468da177 9107 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9108 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9109 #define GPIO_PUPDR_PUPDR2_Pos (4U)
<> 161:2cc1468da177 9110 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 9111 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
<> 161:2cc1468da177 9112 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 9113 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 9114 #define GPIO_PUPDR_PUPDR3_Pos (6U)
<> 161:2cc1468da177 9115 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 9116 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
<> 161:2cc1468da177 9117 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 9118 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 9119 #define GPIO_PUPDR_PUPDR4_Pos (8U)
<> 161:2cc1468da177 9120 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 9121 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
<> 161:2cc1468da177 9122 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 9123 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 9124 #define GPIO_PUPDR_PUPDR5_Pos (10U)
<> 161:2cc1468da177 9125 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 9126 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
<> 161:2cc1468da177 9127 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 9128 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 9129 #define GPIO_PUPDR_PUPDR6_Pos (12U)
<> 161:2cc1468da177 9130 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
<> 161:2cc1468da177 9131 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
<> 161:2cc1468da177 9132 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 9133 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 9134 #define GPIO_PUPDR_PUPDR7_Pos (14U)
<> 161:2cc1468da177 9135 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 9136 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
<> 161:2cc1468da177 9137 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 9138 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9139 #define GPIO_PUPDR_PUPDR8_Pos (16U)
<> 161:2cc1468da177 9140 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 9141 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
<> 161:2cc1468da177 9142 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 9143 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 9144 #define GPIO_PUPDR_PUPDR9_Pos (18U)
<> 161:2cc1468da177 9145 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
<> 161:2cc1468da177 9146 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
<> 161:2cc1468da177 9147 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 9148 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 9149 #define GPIO_PUPDR_PUPDR10_Pos (20U)
<> 161:2cc1468da177 9150 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 9151 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
<> 161:2cc1468da177 9152 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 9153 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 9154 #define GPIO_PUPDR_PUPDR11_Pos (22U)
<> 161:2cc1468da177 9155 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
<> 161:2cc1468da177 9156 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
<> 161:2cc1468da177 9157 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 9158 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 9159 #define GPIO_PUPDR_PUPDR12_Pos (24U)
<> 161:2cc1468da177 9160 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
<> 161:2cc1468da177 9161 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
<> 161:2cc1468da177 9162 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 9163 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 9164 #define GPIO_PUPDR_PUPDR13_Pos (26U)
<> 161:2cc1468da177 9165 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
<> 161:2cc1468da177 9166 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
<> 161:2cc1468da177 9167 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 9168 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 9169 #define GPIO_PUPDR_PUPDR14_Pos (28U)
<> 161:2cc1468da177 9170 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 9171 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
<> 161:2cc1468da177 9172 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 9173 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 9174 #define GPIO_PUPDR_PUPDR15_Pos (30U)
<> 161:2cc1468da177 9175 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
<> 161:2cc1468da177 9176 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
<> 161:2cc1468da177 9177 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 9178 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 9179
<> 144:ef7eb2e8f9f7 9180 /****************** Bits definition for GPIO_IDR register *******************/
<> 161:2cc1468da177 9181 #define GPIO_IDR_IDR_0 0x00000001U
<> 161:2cc1468da177 9182 #define GPIO_IDR_IDR_1 0x00000002U
<> 161:2cc1468da177 9183 #define GPIO_IDR_IDR_2 0x00000004U
<> 161:2cc1468da177 9184 #define GPIO_IDR_IDR_3 0x00000008U
<> 161:2cc1468da177 9185 #define GPIO_IDR_IDR_4 0x00000010U
<> 161:2cc1468da177 9186 #define GPIO_IDR_IDR_5 0x00000020U
<> 161:2cc1468da177 9187 #define GPIO_IDR_IDR_6 0x00000040U
<> 161:2cc1468da177 9188 #define GPIO_IDR_IDR_7 0x00000080U
<> 161:2cc1468da177 9189 #define GPIO_IDR_IDR_8 0x00000100U
<> 161:2cc1468da177 9190 #define GPIO_IDR_IDR_9 0x00000200U
<> 161:2cc1468da177 9191 #define GPIO_IDR_IDR_10 0x00000400U
<> 161:2cc1468da177 9192 #define GPIO_IDR_IDR_11 0x00000800U
<> 161:2cc1468da177 9193 #define GPIO_IDR_IDR_12 0x00001000U
<> 161:2cc1468da177 9194 #define GPIO_IDR_IDR_13 0x00002000U
<> 161:2cc1468da177 9195 #define GPIO_IDR_IDR_14 0x00004000U
<> 161:2cc1468da177 9196 #define GPIO_IDR_IDR_15 0x00008000U
<> 144:ef7eb2e8f9f7 9197
<> 144:ef7eb2e8f9f7 9198 /****************** Bits definition for GPIO_ODR register *******************/
<> 161:2cc1468da177 9199 #define GPIO_ODR_ODR_0 0x00000001U
<> 161:2cc1468da177 9200 #define GPIO_ODR_ODR_1 0x00000002U
<> 161:2cc1468da177 9201 #define GPIO_ODR_ODR_2 0x00000004U
<> 161:2cc1468da177 9202 #define GPIO_ODR_ODR_3 0x00000008U
<> 161:2cc1468da177 9203 #define GPIO_ODR_ODR_4 0x00000010U
<> 161:2cc1468da177 9204 #define GPIO_ODR_ODR_5 0x00000020U
<> 161:2cc1468da177 9205 #define GPIO_ODR_ODR_6 0x00000040U
<> 161:2cc1468da177 9206 #define GPIO_ODR_ODR_7 0x00000080U
<> 161:2cc1468da177 9207 #define GPIO_ODR_ODR_8 0x00000100U
<> 161:2cc1468da177 9208 #define GPIO_ODR_ODR_9 0x00000200U
<> 161:2cc1468da177 9209 #define GPIO_ODR_ODR_10 0x00000400U
<> 161:2cc1468da177 9210 #define GPIO_ODR_ODR_11 0x00000800U
<> 161:2cc1468da177 9211 #define GPIO_ODR_ODR_12 0x00001000U
<> 161:2cc1468da177 9212 #define GPIO_ODR_ODR_13 0x00002000U
<> 161:2cc1468da177 9213 #define GPIO_ODR_ODR_14 0x00004000U
<> 161:2cc1468da177 9214 #define GPIO_ODR_ODR_15 0x00008000U
<> 144:ef7eb2e8f9f7 9215
<> 144:ef7eb2e8f9f7 9216 /****************** Bits definition for GPIO_BSRR register ******************/
<> 161:2cc1468da177 9217 #define GPIO_BSRR_BS_0 0x00000001U
<> 161:2cc1468da177 9218 #define GPIO_BSRR_BS_1 0x00000002U
<> 161:2cc1468da177 9219 #define GPIO_BSRR_BS_2 0x00000004U
<> 161:2cc1468da177 9220 #define GPIO_BSRR_BS_3 0x00000008U
<> 161:2cc1468da177 9221 #define GPIO_BSRR_BS_4 0x00000010U
<> 161:2cc1468da177 9222 #define GPIO_BSRR_BS_5 0x00000020U
<> 161:2cc1468da177 9223 #define GPIO_BSRR_BS_6 0x00000040U
<> 161:2cc1468da177 9224 #define GPIO_BSRR_BS_7 0x00000080U
<> 161:2cc1468da177 9225 #define GPIO_BSRR_BS_8 0x00000100U
<> 161:2cc1468da177 9226 #define GPIO_BSRR_BS_9 0x00000200U
<> 161:2cc1468da177 9227 #define GPIO_BSRR_BS_10 0x00000400U
<> 161:2cc1468da177 9228 #define GPIO_BSRR_BS_11 0x00000800U
<> 161:2cc1468da177 9229 #define GPIO_BSRR_BS_12 0x00001000U
<> 161:2cc1468da177 9230 #define GPIO_BSRR_BS_13 0x00002000U
<> 161:2cc1468da177 9231 #define GPIO_BSRR_BS_14 0x00004000U
<> 161:2cc1468da177 9232 #define GPIO_BSRR_BS_15 0x00008000U
<> 161:2cc1468da177 9233 #define GPIO_BSRR_BR_0 0x00010000U
<> 161:2cc1468da177 9234 #define GPIO_BSRR_BR_1 0x00020000U
<> 161:2cc1468da177 9235 #define GPIO_BSRR_BR_2 0x00040000U
<> 161:2cc1468da177 9236 #define GPIO_BSRR_BR_3 0x00080000U
<> 161:2cc1468da177 9237 #define GPIO_BSRR_BR_4 0x00100000U
<> 161:2cc1468da177 9238 #define GPIO_BSRR_BR_5 0x00200000U
<> 161:2cc1468da177 9239 #define GPIO_BSRR_BR_6 0x00400000U
<> 161:2cc1468da177 9240 #define GPIO_BSRR_BR_7 0x00800000U
<> 161:2cc1468da177 9241 #define GPIO_BSRR_BR_8 0x01000000U
<> 161:2cc1468da177 9242 #define GPIO_BSRR_BR_9 0x02000000U
<> 161:2cc1468da177 9243 #define GPIO_BSRR_BR_10 0x04000000U
<> 161:2cc1468da177 9244 #define GPIO_BSRR_BR_11 0x08000000U
<> 161:2cc1468da177 9245 #define GPIO_BSRR_BR_12 0x10000000U
<> 161:2cc1468da177 9246 #define GPIO_BSRR_BR_13 0x20000000U
<> 161:2cc1468da177 9247 #define GPIO_BSRR_BR_14 0x40000000U
<> 161:2cc1468da177 9248 #define GPIO_BSRR_BR_15 0x80000000U
<> 144:ef7eb2e8f9f7 9249
<> 144:ef7eb2e8f9f7 9250 /****************** Bit definition for GPIO_LCKR register *********************/
<> 161:2cc1468da177 9251 #define GPIO_LCKR_LCK0_Pos (0U)
<> 161:2cc1468da177 9252 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9253 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
<> 161:2cc1468da177 9254 #define GPIO_LCKR_LCK1_Pos (1U)
<> 161:2cc1468da177 9255 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9256 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
<> 161:2cc1468da177 9257 #define GPIO_LCKR_LCK2_Pos (2U)
<> 161:2cc1468da177 9258 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9259 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
<> 161:2cc1468da177 9260 #define GPIO_LCKR_LCK3_Pos (3U)
<> 161:2cc1468da177 9261 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9262 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
<> 161:2cc1468da177 9263 #define GPIO_LCKR_LCK4_Pos (4U)
<> 161:2cc1468da177 9264 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 9265 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
<> 161:2cc1468da177 9266 #define GPIO_LCKR_LCK5_Pos (5U)
<> 161:2cc1468da177 9267 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 9268 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
<> 161:2cc1468da177 9269 #define GPIO_LCKR_LCK6_Pos (6U)
<> 161:2cc1468da177 9270 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 9271 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
<> 161:2cc1468da177 9272 #define GPIO_LCKR_LCK7_Pos (7U)
<> 161:2cc1468da177 9273 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 9274 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
<> 161:2cc1468da177 9275 #define GPIO_LCKR_LCK8_Pos (8U)
<> 161:2cc1468da177 9276 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 9277 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
<> 161:2cc1468da177 9278 #define GPIO_LCKR_LCK9_Pos (9U)
<> 161:2cc1468da177 9279 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 9280 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
<> 161:2cc1468da177 9281 #define GPIO_LCKR_LCK10_Pos (10U)
<> 161:2cc1468da177 9282 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 9283 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
<> 161:2cc1468da177 9284 #define GPIO_LCKR_LCK11_Pos (11U)
<> 161:2cc1468da177 9285 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 9286 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
<> 161:2cc1468da177 9287 #define GPIO_LCKR_LCK12_Pos (12U)
<> 161:2cc1468da177 9288 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 9289 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
<> 161:2cc1468da177 9290 #define GPIO_LCKR_LCK13_Pos (13U)
<> 161:2cc1468da177 9291 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 9292 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
<> 161:2cc1468da177 9293 #define GPIO_LCKR_LCK14_Pos (14U)
<> 161:2cc1468da177 9294 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 9295 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
<> 161:2cc1468da177 9296 #define GPIO_LCKR_LCK15_Pos (15U)
<> 161:2cc1468da177 9297 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9298 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
<> 161:2cc1468da177 9299 #define GPIO_LCKR_LCKK_Pos (16U)
<> 161:2cc1468da177 9300 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 9301 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
<> 161:2cc1468da177 9302
<> 161:2cc1468da177 9303 /****************** Bit definition for GPIO_AFRL register *********************/
<> 161:2cc1468da177 9304 #define GPIO_AFRL_AFRL0_Pos (0U)
<> 161:2cc1468da177 9305 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 9306 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
<> 161:2cc1468da177 9307 #define GPIO_AFRL_AFRL0_0 (0x1U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9308 #define GPIO_AFRL_AFRL0_1 (0x2U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9309 #define GPIO_AFRL_AFRL0_2 (0x4U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9310 #define GPIO_AFRL_AFRL0_3 (0x8U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9311 #define GPIO_AFRL_AFRL1_Pos (4U)
<> 161:2cc1468da177 9312 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 9313 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
<> 161:2cc1468da177 9314 #define GPIO_AFRL_AFRL1_0 (0x1U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 9315 #define GPIO_AFRL_AFRL1_1 (0x2U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 9316 #define GPIO_AFRL_AFRL1_2 (0x4U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 9317 #define GPIO_AFRL_AFRL1_3 (0x8U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 9318 #define GPIO_AFRL_AFRL2_Pos (8U)
<> 161:2cc1468da177 9319 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 9320 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
<> 161:2cc1468da177 9321 #define GPIO_AFRL_AFRL2_0 (0x1U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 9322 #define GPIO_AFRL_AFRL2_1 (0x2U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 9323 #define GPIO_AFRL_AFRL2_2 (0x4U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 9324 #define GPIO_AFRL_AFRL2_3 (0x8U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 9325 #define GPIO_AFRL_AFRL3_Pos (12U)
<> 161:2cc1468da177 9326 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 9327 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
<> 161:2cc1468da177 9328 #define GPIO_AFRL_AFRL3_0 (0x1U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 9329 #define GPIO_AFRL_AFRL3_1 (0x2U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 9330 #define GPIO_AFRL_AFRL3_2 (0x4U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 9331 #define GPIO_AFRL_AFRL3_3 (0x8U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9332 #define GPIO_AFRL_AFRL4_Pos (16U)
<> 161:2cc1468da177 9333 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 9334 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
<> 161:2cc1468da177 9335 #define GPIO_AFRL_AFRL4_0 (0x1U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 9336 #define GPIO_AFRL_AFRL4_1 (0x2U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 9337 #define GPIO_AFRL_AFRL4_2 (0x4U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 9338 #define GPIO_AFRL_AFRL4_3 (0x8U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 9339 #define GPIO_AFRL_AFRL5_Pos (20U)
<> 161:2cc1468da177 9340 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 9341 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
<> 161:2cc1468da177 9342 #define GPIO_AFRL_AFRL5_0 (0x1U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 9343 #define GPIO_AFRL_AFRL5_1 (0x2U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 9344 #define GPIO_AFRL_AFRL5_2 (0x4U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 9345 #define GPIO_AFRL_AFRL5_3 (0x8U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 9346 #define GPIO_AFRL_AFRL6_Pos (24U)
<> 161:2cc1468da177 9347 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 9348 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
<> 161:2cc1468da177 9349 #define GPIO_AFRL_AFRL6_0 (0x1U << GPIO_AFRL_AFRL6_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 9350 #define GPIO_AFRL_AFRL6_1 (0x2U << GPIO_AFRL_AFRL6_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 9351 #define GPIO_AFRL_AFRL6_2 (0x4U << GPIO_AFRL_AFRL6_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 9352 #define GPIO_AFRL_AFRL6_3 (0x8U << GPIO_AFRL_AFRL6_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 9353 #define GPIO_AFRL_AFRL7_Pos (28U)
<> 161:2cc1468da177 9354 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
<> 161:2cc1468da177 9355 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
<> 161:2cc1468da177 9356 #define GPIO_AFRL_AFRL7_0 (0x1U << GPIO_AFRL_AFRL7_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 9357 #define GPIO_AFRL_AFRL7_1 (0x2U << GPIO_AFRL_AFRL7_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 9358 #define GPIO_AFRL_AFRL7_2 (0x4U << GPIO_AFRL_AFRL7_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 9359 #define GPIO_AFRL_AFRL7_3 (0x8U << GPIO_AFRL_AFRL7_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 9360
<> 161:2cc1468da177 9361 /****************** Bit definition for GPIO_AFRH register *********************/
<> 161:2cc1468da177 9362 #define GPIO_AFRH_AFRH0_Pos (0U)
<> 161:2cc1468da177 9363 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 9364 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
<> 161:2cc1468da177 9365 #define GPIO_AFRH_AFRH0_0 (0x1U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9366 #define GPIO_AFRH_AFRH0_1 (0x2U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9367 #define GPIO_AFRH_AFRH0_2 (0x4U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9368 #define GPIO_AFRH_AFRH0_3 (0x8U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9369 #define GPIO_AFRH_AFRH1_Pos (4U)
<> 161:2cc1468da177 9370 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 9371 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
<> 161:2cc1468da177 9372 #define GPIO_AFRH_AFRH1_0 (0x1U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 9373 #define GPIO_AFRH_AFRH1_1 (0x2U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 9374 #define GPIO_AFRH_AFRH1_2 (0x4U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 9375 #define GPIO_AFRH_AFRH1_3 (0x8U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 9376 #define GPIO_AFRH_AFRH2_Pos (8U)
<> 161:2cc1468da177 9377 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 9378 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
<> 161:2cc1468da177 9379 #define GPIO_AFRH_AFRH2_0 (0x1U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 9380 #define GPIO_AFRH_AFRH2_1 (0x2U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 9381 #define GPIO_AFRH_AFRH2_2 (0x4U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 9382 #define GPIO_AFRH_AFRH2_3 (0x8U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 9383 #define GPIO_AFRH_AFRH3_Pos (12U)
<> 161:2cc1468da177 9384 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 9385 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
<> 161:2cc1468da177 9386 #define GPIO_AFRH_AFRH3_0 (0x1U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 9387 #define GPIO_AFRH_AFRH3_1 (0x2U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 9388 #define GPIO_AFRH_AFRH3_2 (0x4U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 9389 #define GPIO_AFRH_AFRH3_3 (0x8U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9390 #define GPIO_AFRH_AFRH4_Pos (16U)
<> 161:2cc1468da177 9391 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 9392 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
<> 161:2cc1468da177 9393 #define GPIO_AFRH_AFRH4_0 (0x1U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 9394 #define GPIO_AFRH_AFRH4_1 (0x2U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 9395 #define GPIO_AFRH_AFRH4_2 (0x4U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 9396 #define GPIO_AFRH_AFRH4_3 (0x8U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 9397 #define GPIO_AFRH_AFRH5_Pos (20U)
<> 161:2cc1468da177 9398 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 9399 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
<> 161:2cc1468da177 9400 #define GPIO_AFRH_AFRH5_0 (0x1U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 9401 #define GPIO_AFRH_AFRH5_1 (0x2U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 9402 #define GPIO_AFRH_AFRH5_2 (0x4U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 9403 #define GPIO_AFRH_AFRH5_3 (0x8U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 9404 #define GPIO_AFRH_AFRH6_Pos (24U)
<> 161:2cc1468da177 9405 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 9406 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
<> 161:2cc1468da177 9407 #define GPIO_AFRH_AFRH6_0 (0x1U << GPIO_AFRH_AFRH6_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 9408 #define GPIO_AFRH_AFRH6_1 (0x2U << GPIO_AFRH_AFRH6_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 9409 #define GPIO_AFRH_AFRH6_2 (0x4U << GPIO_AFRH_AFRH6_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 9410 #define GPIO_AFRH_AFRH6_3 (0x8U << GPIO_AFRH_AFRH6_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 9411 #define GPIO_AFRH_AFRH7_Pos (28U)
<> 161:2cc1468da177 9412 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
<> 161:2cc1468da177 9413 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
<> 161:2cc1468da177 9414 #define GPIO_AFRH_AFRH7_0 (0x1U << GPIO_AFRH_AFRH7_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 9415 #define GPIO_AFRH_AFRH7_1 (0x2U << GPIO_AFRH_AFRH7_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 9416 #define GPIO_AFRH_AFRH7_2 (0x4U << GPIO_AFRH_AFRH7_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 9417 #define GPIO_AFRH_AFRH7_3 (0x8U << GPIO_AFRH_AFRH7_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 9418
<> 144:ef7eb2e8f9f7 9419
<> 144:ef7eb2e8f9f7 9420 /******************************************************************************/
<> 144:ef7eb2e8f9f7 9421 /* */
<> 144:ef7eb2e8f9f7 9422 /* Inter-integrated Circuit Interface (I2C) */
<> 144:ef7eb2e8f9f7 9423 /* */
<> 144:ef7eb2e8f9f7 9424 /******************************************************************************/
<> 144:ef7eb2e8f9f7 9425 /******************* Bit definition for I2C_CR1 register *******************/
<> 161:2cc1468da177 9426 #define I2C_CR1_PE_Pos (0U)
<> 161:2cc1468da177 9427 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9428 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
<> 161:2cc1468da177 9429 #define I2C_CR1_TXIE_Pos (1U)
<> 161:2cc1468da177 9430 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9431 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
<> 161:2cc1468da177 9432 #define I2C_CR1_RXIE_Pos (2U)
<> 161:2cc1468da177 9433 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9434 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
<> 161:2cc1468da177 9435 #define I2C_CR1_ADDRIE_Pos (3U)
<> 161:2cc1468da177 9436 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9437 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
<> 161:2cc1468da177 9438 #define I2C_CR1_NACKIE_Pos (4U)
<> 161:2cc1468da177 9439 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 9440 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
<> 161:2cc1468da177 9441 #define I2C_CR1_STOPIE_Pos (5U)
<> 161:2cc1468da177 9442 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 9443 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
<> 161:2cc1468da177 9444 #define I2C_CR1_TCIE_Pos (6U)
<> 161:2cc1468da177 9445 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 9446 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 161:2cc1468da177 9447 #define I2C_CR1_ERRIE_Pos (7U)
<> 161:2cc1468da177 9448 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 9449 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
<> 161:2cc1468da177 9450 #define I2C_CR1_DNF_Pos (8U)
<> 161:2cc1468da177 9451 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 9452 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
<> 161:2cc1468da177 9453 #define I2C_CR1_ANFOFF_Pos (12U)
<> 161:2cc1468da177 9454 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 9455 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
<> 161:2cc1468da177 9456 #define I2C_CR1_TXDMAEN_Pos (14U)
<> 161:2cc1468da177 9457 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 9458 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
<> 161:2cc1468da177 9459 #define I2C_CR1_RXDMAEN_Pos (15U)
<> 161:2cc1468da177 9460 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9461 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
<> 161:2cc1468da177 9462 #define I2C_CR1_SBC_Pos (16U)
<> 161:2cc1468da177 9463 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 9464 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
<> 161:2cc1468da177 9465 #define I2C_CR1_NOSTRETCH_Pos (17U)
<> 161:2cc1468da177 9466 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 9467 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
<> 161:2cc1468da177 9468 #define I2C_CR1_GCEN_Pos (19U)
<> 161:2cc1468da177 9469 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 9470 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
<> 161:2cc1468da177 9471 #define I2C_CR1_SMBHEN_Pos (20U)
<> 161:2cc1468da177 9472 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 9473 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
<> 161:2cc1468da177 9474 #define I2C_CR1_SMBDEN_Pos (21U)
<> 161:2cc1468da177 9475 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 9476 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
<> 161:2cc1468da177 9477 #define I2C_CR1_ALERTEN_Pos (22U)
<> 161:2cc1468da177 9478 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 9479 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
<> 161:2cc1468da177 9480 #define I2C_CR1_PECEN_Pos (23U)
<> 161:2cc1468da177 9481 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 9482 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
<> 144:ef7eb2e8f9f7 9483
<> 144:ef7eb2e8f9f7 9484
<> 144:ef7eb2e8f9f7 9485 /****************** Bit definition for I2C_CR2 register ********************/
<> 161:2cc1468da177 9486 #define I2C_CR2_SADD_Pos (0U)
<> 161:2cc1468da177 9487 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
<> 161:2cc1468da177 9488 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
<> 161:2cc1468da177 9489 #define I2C_CR2_RD_WRN_Pos (10U)
<> 161:2cc1468da177 9490 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 9491 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
<> 161:2cc1468da177 9492 #define I2C_CR2_ADD10_Pos (11U)
<> 161:2cc1468da177 9493 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 9494 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
<> 161:2cc1468da177 9495 #define I2C_CR2_HEAD10R_Pos (12U)
<> 161:2cc1468da177 9496 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 9497 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
<> 161:2cc1468da177 9498 #define I2C_CR2_START_Pos (13U)
<> 161:2cc1468da177 9499 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 9500 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
<> 161:2cc1468da177 9501 #define I2C_CR2_STOP_Pos (14U)
<> 161:2cc1468da177 9502 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 9503 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
<> 161:2cc1468da177 9504 #define I2C_CR2_NACK_Pos (15U)
<> 161:2cc1468da177 9505 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9506 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
<> 161:2cc1468da177 9507 #define I2C_CR2_NBYTES_Pos (16U)
<> 161:2cc1468da177 9508 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 9509 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
<> 161:2cc1468da177 9510 #define I2C_CR2_RELOAD_Pos (24U)
<> 161:2cc1468da177 9511 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 9512 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
<> 161:2cc1468da177 9513 #define I2C_CR2_AUTOEND_Pos (25U)
<> 161:2cc1468da177 9514 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 9515 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
<> 161:2cc1468da177 9516 #define I2C_CR2_PECBYTE_Pos (26U)
<> 161:2cc1468da177 9517 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 9518 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
<> 144:ef7eb2e8f9f7 9519
<> 144:ef7eb2e8f9f7 9520 /******************* Bit definition for I2C_OAR1 register ******************/
<> 161:2cc1468da177 9521 #define I2C_OAR1_OA1_Pos (0U)
<> 161:2cc1468da177 9522 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
<> 161:2cc1468da177 9523 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
<> 161:2cc1468da177 9524 #define I2C_OAR1_OA1MODE_Pos (10U)
<> 161:2cc1468da177 9525 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 9526 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
<> 161:2cc1468da177 9527 #define I2C_OAR1_OA1EN_Pos (15U)
<> 161:2cc1468da177 9528 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9529 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
<> 144:ef7eb2e8f9f7 9530
<> 144:ef7eb2e8f9f7 9531 /******************* Bit definition for I2C_OAR2 register ******************/
<> 161:2cc1468da177 9532 #define I2C_OAR2_OA2_Pos (1U)
<> 161:2cc1468da177 9533 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
<> 161:2cc1468da177 9534 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
<> 161:2cc1468da177 9535 #define I2C_OAR2_OA2MSK_Pos (8U)
<> 161:2cc1468da177 9536 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
<> 161:2cc1468da177 9537 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
<> 161:2cc1468da177 9538 #define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */
<> 161:2cc1468da177 9539 #define I2C_OAR2_OA2MASK01_Pos (8U)
<> 161:2cc1468da177 9540 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 9541 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
<> 161:2cc1468da177 9542 #define I2C_OAR2_OA2MASK02_Pos (9U)
<> 161:2cc1468da177 9543 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 9544 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
<> 161:2cc1468da177 9545 #define I2C_OAR2_OA2MASK03_Pos (8U)
<> 161:2cc1468da177 9546 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 9547 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
<> 161:2cc1468da177 9548 #define I2C_OAR2_OA2MASK04_Pos (10U)
<> 161:2cc1468da177 9549 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 9550 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
<> 161:2cc1468da177 9551 #define I2C_OAR2_OA2MASK05_Pos (8U)
<> 161:2cc1468da177 9552 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
<> 161:2cc1468da177 9553 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
<> 161:2cc1468da177 9554 #define I2C_OAR2_OA2MASK06_Pos (9U)
<> 161:2cc1468da177 9555 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
<> 161:2cc1468da177 9556 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
<> 161:2cc1468da177 9557 #define I2C_OAR2_OA2MASK07_Pos (8U)
<> 161:2cc1468da177 9558 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
<> 161:2cc1468da177 9559 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
<> 161:2cc1468da177 9560 #define I2C_OAR2_OA2EN_Pos (15U)
<> 161:2cc1468da177 9561 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9562 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
<> 144:ef7eb2e8f9f7 9563
<> 144:ef7eb2e8f9f7 9564 /******************* Bit definition for I2C_TIMINGR register *******************/
<> 161:2cc1468da177 9565 #define I2C_TIMINGR_SCLL_Pos (0U)
<> 161:2cc1468da177 9566 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 9567 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
<> 161:2cc1468da177 9568 #define I2C_TIMINGR_SCLH_Pos (8U)
<> 161:2cc1468da177 9569 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 9570 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
<> 161:2cc1468da177 9571 #define I2C_TIMINGR_SDADEL_Pos (16U)
<> 161:2cc1468da177 9572 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 9573 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
<> 161:2cc1468da177 9574 #define I2C_TIMINGR_SCLDEL_Pos (20U)
<> 161:2cc1468da177 9575 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 9576 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
<> 161:2cc1468da177 9577 #define I2C_TIMINGR_PRESC_Pos (28U)
<> 161:2cc1468da177 9578 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
<> 161:2cc1468da177 9579 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
<> 144:ef7eb2e8f9f7 9580
<> 144:ef7eb2e8f9f7 9581 /******************* Bit definition for I2C_TIMEOUTR register *******************/
<> 161:2cc1468da177 9582 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
<> 161:2cc1468da177 9583 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 9584 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
<> 161:2cc1468da177 9585 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
<> 161:2cc1468da177 9586 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 9587 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
<> 161:2cc1468da177 9588 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
<> 161:2cc1468da177 9589 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9590 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
<> 161:2cc1468da177 9591 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
<> 161:2cc1468da177 9592 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
<> 161:2cc1468da177 9593 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
<> 161:2cc1468da177 9594 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
<> 161:2cc1468da177 9595 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 9596 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
<> 144:ef7eb2e8f9f7 9597
<> 144:ef7eb2e8f9f7 9598 /****************** Bit definition for I2C_ISR register *********************/
<> 161:2cc1468da177 9599 #define I2C_ISR_TXE_Pos (0U)
<> 161:2cc1468da177 9600 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9601 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
<> 161:2cc1468da177 9602 #define I2C_ISR_TXIS_Pos (1U)
<> 161:2cc1468da177 9603 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9604 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
<> 161:2cc1468da177 9605 #define I2C_ISR_RXNE_Pos (2U)
<> 161:2cc1468da177 9606 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9607 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
<> 161:2cc1468da177 9608 #define I2C_ISR_ADDR_Pos (3U)
<> 161:2cc1468da177 9609 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9610 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
<> 161:2cc1468da177 9611 #define I2C_ISR_NACKF_Pos (4U)
<> 161:2cc1468da177 9612 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 9613 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
<> 161:2cc1468da177 9614 #define I2C_ISR_STOPF_Pos (5U)
<> 161:2cc1468da177 9615 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 9616 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
<> 161:2cc1468da177 9617 #define I2C_ISR_TC_Pos (6U)
<> 161:2cc1468da177 9618 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 9619 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
<> 161:2cc1468da177 9620 #define I2C_ISR_TCR_Pos (7U)
<> 161:2cc1468da177 9621 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 9622 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
<> 161:2cc1468da177 9623 #define I2C_ISR_BERR_Pos (8U)
<> 161:2cc1468da177 9624 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 9625 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
<> 161:2cc1468da177 9626 #define I2C_ISR_ARLO_Pos (9U)
<> 161:2cc1468da177 9627 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 9628 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
<> 161:2cc1468da177 9629 #define I2C_ISR_OVR_Pos (10U)
<> 161:2cc1468da177 9630 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 9631 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
<> 161:2cc1468da177 9632 #define I2C_ISR_PECERR_Pos (11U)
<> 161:2cc1468da177 9633 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 9634 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
<> 161:2cc1468da177 9635 #define I2C_ISR_TIMEOUT_Pos (12U)
<> 161:2cc1468da177 9636 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 9637 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
<> 161:2cc1468da177 9638 #define I2C_ISR_ALERT_Pos (13U)
<> 161:2cc1468da177 9639 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 9640 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
<> 161:2cc1468da177 9641 #define I2C_ISR_BUSY_Pos (15U)
<> 161:2cc1468da177 9642 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 9643 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
<> 161:2cc1468da177 9644 #define I2C_ISR_DIR_Pos (16U)
<> 161:2cc1468da177 9645 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 9646 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
<> 161:2cc1468da177 9647 #define I2C_ISR_ADDCODE_Pos (17U)
<> 161:2cc1468da177 9648 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
<> 161:2cc1468da177 9649 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
<> 144:ef7eb2e8f9f7 9650
<> 144:ef7eb2e8f9f7 9651 /****************** Bit definition for I2C_ICR register *********************/
<> 161:2cc1468da177 9652 #define I2C_ICR_ADDRCF_Pos (3U)
<> 161:2cc1468da177 9653 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9654 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
<> 161:2cc1468da177 9655 #define I2C_ICR_NACKCF_Pos (4U)
<> 161:2cc1468da177 9656 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 9657 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
<> 161:2cc1468da177 9658 #define I2C_ICR_STOPCF_Pos (5U)
<> 161:2cc1468da177 9659 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 9660 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
<> 161:2cc1468da177 9661 #define I2C_ICR_BERRCF_Pos (8U)
<> 161:2cc1468da177 9662 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 9663 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
<> 161:2cc1468da177 9664 #define I2C_ICR_ARLOCF_Pos (9U)
<> 161:2cc1468da177 9665 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 9666 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
<> 161:2cc1468da177 9667 #define I2C_ICR_OVRCF_Pos (10U)
<> 161:2cc1468da177 9668 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 9669 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
<> 161:2cc1468da177 9670 #define I2C_ICR_PECCF_Pos (11U)
<> 161:2cc1468da177 9671 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 9672 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
<> 161:2cc1468da177 9673 #define I2C_ICR_TIMOUTCF_Pos (12U)
<> 161:2cc1468da177 9674 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 9675 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
<> 161:2cc1468da177 9676 #define I2C_ICR_ALERTCF_Pos (13U)
<> 161:2cc1468da177 9677 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 9678 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
<> 144:ef7eb2e8f9f7 9679
<> 144:ef7eb2e8f9f7 9680 /****************** Bit definition for I2C_PECR register *********************/
<> 161:2cc1468da177 9681 #define I2C_PECR_PEC_Pos (0U)
<> 161:2cc1468da177 9682 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 9683 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
<> 144:ef7eb2e8f9f7 9684
<> 144:ef7eb2e8f9f7 9685 /****************** Bit definition for I2C_RXDR register *********************/
<> 161:2cc1468da177 9686 #define I2C_RXDR_RXDATA_Pos (0U)
<> 161:2cc1468da177 9687 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 9688 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
<> 144:ef7eb2e8f9f7 9689
<> 144:ef7eb2e8f9f7 9690 /****************** Bit definition for I2C_TXDR register *********************/
<> 161:2cc1468da177 9691 #define I2C_TXDR_TXDATA_Pos (0U)
<> 161:2cc1468da177 9692 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 9693 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
<> 144:ef7eb2e8f9f7 9694
<> 144:ef7eb2e8f9f7 9695
<> 144:ef7eb2e8f9f7 9696 /******************************************************************************/
<> 144:ef7eb2e8f9f7 9697 /* */
<> 144:ef7eb2e8f9f7 9698 /* Independent WATCHDOG */
<> 144:ef7eb2e8f9f7 9699 /* */
<> 144:ef7eb2e8f9f7 9700 /******************************************************************************/
<> 144:ef7eb2e8f9f7 9701 /******************* Bit definition for IWDG_KR register ********************/
<> 161:2cc1468da177 9702 #define IWDG_KR_KEY_Pos (0U)
<> 161:2cc1468da177 9703 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 9704 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
<> 144:ef7eb2e8f9f7 9705
<> 144:ef7eb2e8f9f7 9706 /******************* Bit definition for IWDG_PR register ********************/
<> 161:2cc1468da177 9707 #define IWDG_PR_PR_Pos (0U)
<> 161:2cc1468da177 9708 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 9709 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
<> 161:2cc1468da177 9710 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
<> 161:2cc1468da177 9711 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
<> 161:2cc1468da177 9712 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
<> 144:ef7eb2e8f9f7 9713
<> 144:ef7eb2e8f9f7 9714 /******************* Bit definition for IWDG_RLR register *******************/
<> 161:2cc1468da177 9715 #define IWDG_RLR_RL_Pos (0U)
<> 161:2cc1468da177 9716 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 9717 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
<> 144:ef7eb2e8f9f7 9718
<> 144:ef7eb2e8f9f7 9719 /******************* Bit definition for IWDG_SR register ********************/
<> 161:2cc1468da177 9720 #define IWDG_SR_PVU_Pos (0U)
<> 161:2cc1468da177 9721 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9722 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
<> 161:2cc1468da177 9723 #define IWDG_SR_RVU_Pos (1U)
<> 161:2cc1468da177 9724 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9725 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
<> 161:2cc1468da177 9726 #define IWDG_SR_WVU_Pos (2U)
<> 161:2cc1468da177 9727 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9728 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
<> 144:ef7eb2e8f9f7 9729
<> 144:ef7eb2e8f9f7 9730 /******************* Bit definition for IWDG_KR register ********************/
<> 161:2cc1468da177 9731 #define IWDG_WINR_WIN_Pos (0U)
<> 161:2cc1468da177 9732 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 9733 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
<> 144:ef7eb2e8f9f7 9734
<> 144:ef7eb2e8f9f7 9735 /******************************************************************************/
<> 144:ef7eb2e8f9f7 9736 /* */
<> 144:ef7eb2e8f9f7 9737 /* LCD-TFT Display Controller (LTDC) */
<> 144:ef7eb2e8f9f7 9738 /* */
<> 144:ef7eb2e8f9f7 9739 /******************************************************************************/
<> 144:ef7eb2e8f9f7 9740
<> 144:ef7eb2e8f9f7 9741 /******************** Bit definition for LTDC_SSCR register *****************/
<> 144:ef7eb2e8f9f7 9742
<> 161:2cc1468da177 9743 #define LTDC_SSCR_VSH_Pos (0U)
<> 161:2cc1468da177 9744 #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
<> 161:2cc1468da177 9745 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
<> 161:2cc1468da177 9746 #define LTDC_SSCR_HSW_Pos (16U)
<> 161:2cc1468da177 9747 #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
<> 161:2cc1468da177 9748 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
<> 144:ef7eb2e8f9f7 9749
<> 144:ef7eb2e8f9f7 9750 /******************** Bit definition for LTDC_BPCR register *****************/
<> 144:ef7eb2e8f9f7 9751
<> 161:2cc1468da177 9752 #define LTDC_BPCR_AVBP_Pos (0U)
<> 161:2cc1468da177 9753 #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
<> 161:2cc1468da177 9754 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
<> 161:2cc1468da177 9755 #define LTDC_BPCR_AHBP_Pos (16U)
<> 161:2cc1468da177 9756 #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
<> 161:2cc1468da177 9757 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
<> 144:ef7eb2e8f9f7 9758
<> 144:ef7eb2e8f9f7 9759 /******************** Bit definition for LTDC_AWCR register *****************/
<> 144:ef7eb2e8f9f7 9760
<> 161:2cc1468da177 9761 #define LTDC_AWCR_AAH_Pos (0U)
<> 161:2cc1468da177 9762 #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
<> 161:2cc1468da177 9763 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
<> 161:2cc1468da177 9764 #define LTDC_AWCR_AAW_Pos (16U)
<> 161:2cc1468da177 9765 #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
<> 161:2cc1468da177 9766 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
<> 144:ef7eb2e8f9f7 9767
<> 144:ef7eb2e8f9f7 9768 /******************** Bit definition for LTDC_TWCR register *****************/
<> 144:ef7eb2e8f9f7 9769
<> 161:2cc1468da177 9770 #define LTDC_TWCR_TOTALH_Pos (0U)
<> 161:2cc1468da177 9771 #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
<> 161:2cc1468da177 9772 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
<> 161:2cc1468da177 9773 #define LTDC_TWCR_TOTALW_Pos (16U)
<> 161:2cc1468da177 9774 #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
<> 161:2cc1468da177 9775 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
<> 144:ef7eb2e8f9f7 9776
<> 144:ef7eb2e8f9f7 9777 /******************** Bit definition for LTDC_GCR register ******************/
<> 144:ef7eb2e8f9f7 9778
<> 161:2cc1468da177 9779 #define LTDC_GCR_LTDCEN_Pos (0U)
<> 161:2cc1468da177 9780 #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9781 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
<> 161:2cc1468da177 9782 #define LTDC_GCR_DBW_Pos (4U)
<> 161:2cc1468da177 9783 #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
<> 161:2cc1468da177 9784 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
<> 161:2cc1468da177 9785 #define LTDC_GCR_DGW_Pos (8U)
<> 161:2cc1468da177 9786 #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
<> 161:2cc1468da177 9787 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
<> 161:2cc1468da177 9788 #define LTDC_GCR_DRW_Pos (12U)
<> 161:2cc1468da177 9789 #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
<> 161:2cc1468da177 9790 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
<> 161:2cc1468da177 9791 #define LTDC_GCR_DEN_Pos (16U)
<> 161:2cc1468da177 9792 #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 9793 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
<> 161:2cc1468da177 9794 #define LTDC_GCR_PCPOL_Pos (28U)
<> 161:2cc1468da177 9795 #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 9796 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
<> 161:2cc1468da177 9797 #define LTDC_GCR_DEPOL_Pos (29U)
<> 161:2cc1468da177 9798 #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 9799 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
<> 161:2cc1468da177 9800 #define LTDC_GCR_VSPOL_Pos (30U)
<> 161:2cc1468da177 9801 #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 9802 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
<> 161:2cc1468da177 9803 #define LTDC_GCR_HSPOL_Pos (31U)
<> 161:2cc1468da177 9804 #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 9805 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
<> 144:ef7eb2e8f9f7 9806
<> 144:ef7eb2e8f9f7 9807
<> 144:ef7eb2e8f9f7 9808 /******************** Bit definition for LTDC_SRCR register *****************/
<> 144:ef7eb2e8f9f7 9809
<> 161:2cc1468da177 9810 #define LTDC_SRCR_IMR_Pos (0U)
<> 161:2cc1468da177 9811 #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9812 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
<> 161:2cc1468da177 9813 #define LTDC_SRCR_VBR_Pos (1U)
<> 161:2cc1468da177 9814 #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9815 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
<> 144:ef7eb2e8f9f7 9816
<> 144:ef7eb2e8f9f7 9817 /******************** Bit definition for LTDC_BCCR register *****************/
<> 144:ef7eb2e8f9f7 9818
<> 161:2cc1468da177 9819 #define LTDC_BCCR_BCBLUE_Pos (0U)
<> 161:2cc1468da177 9820 #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 9821 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
<> 161:2cc1468da177 9822 #define LTDC_BCCR_BCGREEN_Pos (8U)
<> 161:2cc1468da177 9823 #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 9824 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
<> 161:2cc1468da177 9825 #define LTDC_BCCR_BCRED_Pos (16U)
<> 161:2cc1468da177 9826 #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 9827 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
<> 144:ef7eb2e8f9f7 9828
<> 144:ef7eb2e8f9f7 9829 /******************** Bit definition for LTDC_IER register ******************/
<> 144:ef7eb2e8f9f7 9830
<> 161:2cc1468da177 9831 #define LTDC_IER_LIE_Pos (0U)
<> 161:2cc1468da177 9832 #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9833 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
<> 161:2cc1468da177 9834 #define LTDC_IER_FUIE_Pos (1U)
<> 161:2cc1468da177 9835 #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9836 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
<> 161:2cc1468da177 9837 #define LTDC_IER_TERRIE_Pos (2U)
<> 161:2cc1468da177 9838 #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9839 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
<> 161:2cc1468da177 9840 #define LTDC_IER_RRIE_Pos (3U)
<> 161:2cc1468da177 9841 #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9842 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
<> 144:ef7eb2e8f9f7 9843
<> 144:ef7eb2e8f9f7 9844 /******************** Bit definition for LTDC_ISR register ******************/
<> 144:ef7eb2e8f9f7 9845
<> 161:2cc1468da177 9846 #define LTDC_ISR_LIF_Pos (0U)
<> 161:2cc1468da177 9847 #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9848 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
<> 161:2cc1468da177 9849 #define LTDC_ISR_FUIF_Pos (1U)
<> 161:2cc1468da177 9850 #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9851 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
<> 161:2cc1468da177 9852 #define LTDC_ISR_TERRIF_Pos (2U)
<> 161:2cc1468da177 9853 #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9854 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
<> 161:2cc1468da177 9855 #define LTDC_ISR_RRIF_Pos (3U)
<> 161:2cc1468da177 9856 #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9857 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
<> 144:ef7eb2e8f9f7 9858
<> 144:ef7eb2e8f9f7 9859 /******************** Bit definition for LTDC_ICR register ******************/
<> 144:ef7eb2e8f9f7 9860
<> 161:2cc1468da177 9861 #define LTDC_ICR_CLIF_Pos (0U)
<> 161:2cc1468da177 9862 #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9863 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
<> 161:2cc1468da177 9864 #define LTDC_ICR_CFUIF_Pos (1U)
<> 161:2cc1468da177 9865 #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9866 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
<> 161:2cc1468da177 9867 #define LTDC_ICR_CTERRIF_Pos (2U)
<> 161:2cc1468da177 9868 #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9869 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
<> 161:2cc1468da177 9870 #define LTDC_ICR_CRRIF_Pos (3U)
<> 161:2cc1468da177 9871 #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9872 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
<> 144:ef7eb2e8f9f7 9873
<> 144:ef7eb2e8f9f7 9874 /******************** Bit definition for LTDC_LIPCR register ****************/
<> 144:ef7eb2e8f9f7 9875
<> 161:2cc1468da177 9876 #define LTDC_LIPCR_LIPOS_Pos (0U)
<> 161:2cc1468da177 9877 #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
<> 161:2cc1468da177 9878 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
<> 144:ef7eb2e8f9f7 9879
<> 144:ef7eb2e8f9f7 9880 /******************** Bit definition for LTDC_CPSR register *****************/
<> 144:ef7eb2e8f9f7 9881
<> 161:2cc1468da177 9882 #define LTDC_CPSR_CYPOS_Pos (0U)
<> 161:2cc1468da177 9883 #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 9884 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
<> 161:2cc1468da177 9885 #define LTDC_CPSR_CXPOS_Pos (16U)
<> 161:2cc1468da177 9886 #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 9887 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
<> 144:ef7eb2e8f9f7 9888
<> 144:ef7eb2e8f9f7 9889 /******************** Bit definition for LTDC_CDSR register *****************/
<> 144:ef7eb2e8f9f7 9890
<> 161:2cc1468da177 9891 #define LTDC_CDSR_VDES_Pos (0U)
<> 161:2cc1468da177 9892 #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9893 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
<> 161:2cc1468da177 9894 #define LTDC_CDSR_HDES_Pos (1U)
<> 161:2cc1468da177 9895 #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9896 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
<> 161:2cc1468da177 9897 #define LTDC_CDSR_VSYNCS_Pos (2U)
<> 161:2cc1468da177 9898 #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 9899 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
<> 161:2cc1468da177 9900 #define LTDC_CDSR_HSYNCS_Pos (3U)
<> 161:2cc1468da177 9901 #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 9902 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
<> 144:ef7eb2e8f9f7 9903
<> 144:ef7eb2e8f9f7 9904 /******************** Bit definition for LTDC_LxCR register *****************/
<> 144:ef7eb2e8f9f7 9905
<> 161:2cc1468da177 9906 #define LTDC_LxCR_LEN_Pos (0U)
<> 161:2cc1468da177 9907 #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 9908 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
<> 161:2cc1468da177 9909 #define LTDC_LxCR_COLKEN_Pos (1U)
<> 161:2cc1468da177 9910 #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 9911 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
<> 161:2cc1468da177 9912 #define LTDC_LxCR_CLUTEN_Pos (4U)
<> 161:2cc1468da177 9913 #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 9914 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
<> 144:ef7eb2e8f9f7 9915
<> 144:ef7eb2e8f9f7 9916 /******************** Bit definition for LTDC_LxWHPCR register **************/
<> 144:ef7eb2e8f9f7 9917
<> 161:2cc1468da177 9918 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
<> 161:2cc1468da177 9919 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 9920 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
<> 161:2cc1468da177 9921 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
<> 161:2cc1468da177 9922 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 9923 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
<> 144:ef7eb2e8f9f7 9924
<> 144:ef7eb2e8f9f7 9925 /******************** Bit definition for LTDC_LxWVPCR register **************/
<> 144:ef7eb2e8f9f7 9926
<> 161:2cc1468da177 9927 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
<> 161:2cc1468da177 9928 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 9929 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
<> 161:2cc1468da177 9930 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
<> 161:2cc1468da177 9931 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 9932 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
<> 144:ef7eb2e8f9f7 9933
<> 144:ef7eb2e8f9f7 9934 /******************** Bit definition for LTDC_LxCKCR register ***************/
<> 144:ef7eb2e8f9f7 9935
<> 161:2cc1468da177 9936 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
<> 161:2cc1468da177 9937 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 9938 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
<> 161:2cc1468da177 9939 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
<> 161:2cc1468da177 9940 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 9941 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
<> 161:2cc1468da177 9942 #define LTDC_LxCKCR_CKRED_Pos (16U)
<> 161:2cc1468da177 9943 #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 9944 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
<> 144:ef7eb2e8f9f7 9945
<> 144:ef7eb2e8f9f7 9946 /******************** Bit definition for LTDC_LxPFCR register ***************/
<> 144:ef7eb2e8f9f7 9947
<> 161:2cc1468da177 9948 #define LTDC_LxPFCR_PF_Pos (0U)
<> 161:2cc1468da177 9949 #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 9950 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
<> 144:ef7eb2e8f9f7 9951
<> 144:ef7eb2e8f9f7 9952 /******************** Bit definition for LTDC_LxCACR register ***************/
<> 144:ef7eb2e8f9f7 9953
<> 161:2cc1468da177 9954 #define LTDC_LxCACR_CONSTA_Pos (0U)
<> 161:2cc1468da177 9955 #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 9956 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
<> 144:ef7eb2e8f9f7 9957
<> 144:ef7eb2e8f9f7 9958 /******************** Bit definition for LTDC_LxDCCR register ***************/
<> 144:ef7eb2e8f9f7 9959
<> 161:2cc1468da177 9960 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
<> 161:2cc1468da177 9961 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 9962 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
<> 161:2cc1468da177 9963 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
<> 161:2cc1468da177 9964 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 9965 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
<> 161:2cc1468da177 9966 #define LTDC_LxDCCR_DCRED_Pos (16U)
<> 161:2cc1468da177 9967 #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 9968 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
<> 161:2cc1468da177 9969 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
<> 161:2cc1468da177 9970 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 9971 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
<> 161:2cc1468da177 9972
<> 144:ef7eb2e8f9f7 9973 /******************** Bit definition for LTDC_LxBFCR register ***************/
<> 144:ef7eb2e8f9f7 9974
<> 161:2cc1468da177 9975 #define LTDC_LxBFCR_BF2_Pos (0U)
<> 161:2cc1468da177 9976 #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 9977 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
<> 161:2cc1468da177 9978 #define LTDC_LxBFCR_BF1_Pos (8U)
<> 161:2cc1468da177 9979 #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
<> 161:2cc1468da177 9980 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
<> 144:ef7eb2e8f9f7 9981
<> 144:ef7eb2e8f9f7 9982 /******************** Bit definition for LTDC_LxCFBAR register **************/
<> 144:ef7eb2e8f9f7 9983
<> 161:2cc1468da177 9984 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
<> 161:2cc1468da177 9985 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 9986 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
<> 144:ef7eb2e8f9f7 9987
<> 144:ef7eb2e8f9f7 9988 /******************** Bit definition for LTDC_LxCFBLR register **************/
<> 144:ef7eb2e8f9f7 9989
<> 161:2cc1468da177 9990 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
<> 161:2cc1468da177 9991 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
<> 161:2cc1468da177 9992 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
<> 161:2cc1468da177 9993 #define LTDC_LxCFBLR_CFBP_Pos (16U)
<> 161:2cc1468da177 9994 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
<> 161:2cc1468da177 9995 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
<> 144:ef7eb2e8f9f7 9996
<> 144:ef7eb2e8f9f7 9997 /******************** Bit definition for LTDC_LxCFBLNR register *************/
<> 144:ef7eb2e8f9f7 9998
<> 161:2cc1468da177 9999 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
<> 161:2cc1468da177 10000 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
<> 161:2cc1468da177 10001 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
<> 144:ef7eb2e8f9f7 10002
<> 144:ef7eb2e8f9f7 10003 /******************** Bit definition for LTDC_LxCLUTWR register *************/
<> 144:ef7eb2e8f9f7 10004
<> 161:2cc1468da177 10005 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
<> 161:2cc1468da177 10006 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 10007 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
<> 161:2cc1468da177 10008 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
<> 161:2cc1468da177 10009 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 10010 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
<> 161:2cc1468da177 10011 #define LTDC_LxCLUTWR_RED_Pos (16U)
<> 161:2cc1468da177 10012 #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 10013 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
<> 161:2cc1468da177 10014 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
<> 161:2cc1468da177 10015 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 10016 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
<> 144:ef7eb2e8f9f7 10017
<> 144:ef7eb2e8f9f7 10018 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10019 /* */
<> 144:ef7eb2e8f9f7 10020 /* Power Control */
<> 144:ef7eb2e8f9f7 10021 /* */
<> 144:ef7eb2e8f9f7 10022 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10023 /******************** Bit definition for PWR_CR1 register ********************/
<> 161:2cc1468da177 10024 #define PWR_CR1_LPDS_Pos (0U)
<> 161:2cc1468da177 10025 #define PWR_CR1_LPDS_Msk (0x1U << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10026 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low-Power Deepsleep */
<> 161:2cc1468da177 10027 #define PWR_CR1_PDDS_Pos (1U)
<> 161:2cc1468da177 10028 #define PWR_CR1_PDDS_Msk (0x1U << PWR_CR1_PDDS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10029 #define PWR_CR1_PDDS PWR_CR1_PDDS_Msk /*!< Power Down Deepsleep */
<> 161:2cc1468da177 10030 #define PWR_CR1_CSBF_Pos (3U)
<> 161:2cc1468da177 10031 #define PWR_CR1_CSBF_Msk (0x1U << PWR_CR1_CSBF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10032 #define PWR_CR1_CSBF PWR_CR1_CSBF_Msk /*!< Clear Standby Flag */
<> 161:2cc1468da177 10033 #define PWR_CR1_PVDE_Pos (4U)
<> 161:2cc1468da177 10034 #define PWR_CR1_PVDE_Msk (0x1U << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10035 #define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Power Voltage Detector Enable */
<> 161:2cc1468da177 10036 #define PWR_CR1_PLS_Pos (5U)
<> 161:2cc1468da177 10037 #define PWR_CR1_PLS_Msk (0x7U << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
<> 161:2cc1468da177 10038 #define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
<> 161:2cc1468da177 10039 #define PWR_CR1_PLS_0 (0x1U << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10040 #define PWR_CR1_PLS_1 (0x2U << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10041 #define PWR_CR1_PLS_2 (0x4U << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 10042
<> 144:ef7eb2e8f9f7 10043 /*!< PVD level configuration */
<> 161:2cc1468da177 10044 #define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */
<> 161:2cc1468da177 10045 #define PWR_CR1_PLS_LEV1_Pos (5U)
<> 161:2cc1468da177 10046 #define PWR_CR1_PLS_LEV1_Msk (0x1U << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10047 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
<> 161:2cc1468da177 10048 #define PWR_CR1_PLS_LEV2_Pos (6U)
<> 161:2cc1468da177 10049 #define PWR_CR1_PLS_LEV2_Msk (0x1U << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10050 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
<> 161:2cc1468da177 10051 #define PWR_CR1_PLS_LEV3_Pos (5U)
<> 161:2cc1468da177 10052 #define PWR_CR1_PLS_LEV3_Msk (0x3U << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
<> 161:2cc1468da177 10053 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
<> 161:2cc1468da177 10054 #define PWR_CR1_PLS_LEV4_Pos (7U)
<> 161:2cc1468da177 10055 #define PWR_CR1_PLS_LEV4_Msk (0x1U << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10056 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
<> 161:2cc1468da177 10057 #define PWR_CR1_PLS_LEV5_Pos (5U)
<> 161:2cc1468da177 10058 #define PWR_CR1_PLS_LEV5_Msk (0x5U << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
<> 161:2cc1468da177 10059 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
<> 161:2cc1468da177 10060 #define PWR_CR1_PLS_LEV6_Pos (6U)
<> 161:2cc1468da177 10061 #define PWR_CR1_PLS_LEV6_Msk (0x3U << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 10062 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
<> 161:2cc1468da177 10063 #define PWR_CR1_PLS_LEV7_Pos (5U)
<> 161:2cc1468da177 10064 #define PWR_CR1_PLS_LEV7_Msk (0x7U << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
<> 161:2cc1468da177 10065 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
<> 161:2cc1468da177 10066 #define PWR_CR1_DBP_Pos (8U)
<> 161:2cc1468da177 10067 #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10068 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */
<> 161:2cc1468da177 10069 #define PWR_CR1_FPDS_Pos (9U)
<> 161:2cc1468da177 10070 #define PWR_CR1_FPDS_Msk (0x1U << PWR_CR1_FPDS_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10071 #define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down in Stop mode */
<> 161:2cc1468da177 10072 #define PWR_CR1_LPUDS_Pos (10U)
<> 161:2cc1468da177 10073 #define PWR_CR1_LPUDS_Msk (0x1U << PWR_CR1_LPUDS_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10074 #define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk /*!< Low-power regulator in deepsleep under-drive mode */
<> 161:2cc1468da177 10075 #define PWR_CR1_MRUDS_Pos (11U)
<> 161:2cc1468da177 10076 #define PWR_CR1_MRUDS_Msk (0x1U << PWR_CR1_MRUDS_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10077 #define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk /*!< Main regulator in deepsleep under-drive mode */
<> 161:2cc1468da177 10078 #define PWR_CR1_ADCDC1_Pos (13U)
<> 161:2cc1468da177 10079 #define PWR_CR1_ADCDC1_Msk (0x1U << PWR_CR1_ADCDC1_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 10080 #define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
<> 161:2cc1468da177 10081 #define PWR_CR1_VOS_Pos (14U)
<> 161:2cc1468da177 10082 #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 10083 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
<> 161:2cc1468da177 10084 #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 10085 #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 10086 #define PWR_CR1_ODEN_Pos (16U)
<> 161:2cc1468da177 10087 #define PWR_CR1_ODEN_Msk (0x1U << PWR_CR1_ODEN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10088 #define PWR_CR1_ODEN PWR_CR1_ODEN_Msk /*!< Over Drive enable */
<> 161:2cc1468da177 10089 #define PWR_CR1_ODSWEN_Pos (17U)
<> 161:2cc1468da177 10090 #define PWR_CR1_ODSWEN_Msk (0x1U << PWR_CR1_ODSWEN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10091 #define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk /*!< Over Drive switch enabled */
<> 161:2cc1468da177 10092 #define PWR_CR1_UDEN_Pos (18U)
<> 161:2cc1468da177 10093 #define PWR_CR1_UDEN_Msk (0x3U << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
<> 161:2cc1468da177 10094 #define PWR_CR1_UDEN PWR_CR1_UDEN_Msk /*!< Under Drive enable in stop mode */
<> 161:2cc1468da177 10095 #define PWR_CR1_UDEN_0 (0x1U << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 10096 #define PWR_CR1_UDEN_1 (0x2U << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 10097
<> 144:ef7eb2e8f9f7 10098 /******************* Bit definition for PWR_CSR1 register ********************/
<> 161:2cc1468da177 10099 #define PWR_CSR1_WUIF_Pos (0U)
<> 161:2cc1468da177 10100 #define PWR_CSR1_WUIF_Msk (0x1U << PWR_CSR1_WUIF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10101 #define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk /*!< Wake up internal Flag */
<> 161:2cc1468da177 10102 #define PWR_CSR1_SBF_Pos (1U)
<> 161:2cc1468da177 10103 #define PWR_CSR1_SBF_Msk (0x1U << PWR_CSR1_SBF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10104 #define PWR_CSR1_SBF PWR_CSR1_SBF_Msk /*!< Standby Flag */
<> 161:2cc1468da177 10105 #define PWR_CSR1_PVDO_Pos (2U)
<> 161:2cc1468da177 10106 #define PWR_CSR1_PVDO_Msk (0x1U << PWR_CSR1_PVDO_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10107 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< PVD Output */
<> 161:2cc1468da177 10108 #define PWR_CSR1_BRR_Pos (3U)
<> 161:2cc1468da177 10109 #define PWR_CSR1_BRR_Msk (0x1U << PWR_CSR1_BRR_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10110 #define PWR_CSR1_BRR PWR_CSR1_BRR_Msk /*!< Backup regulator ready */
<> 161:2cc1468da177 10111 #define PWR_CSR1_EIWUP_Pos (8U)
<> 161:2cc1468da177 10112 #define PWR_CSR1_EIWUP_Msk (0x1U << PWR_CSR1_EIWUP_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10113 #define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk /*!< Enable internal wakeup */
<> 161:2cc1468da177 10114 #define PWR_CSR1_BRE_Pos (9U)
<> 161:2cc1468da177 10115 #define PWR_CSR1_BRE_Msk (0x1U << PWR_CSR1_BRE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10116 #define PWR_CSR1_BRE PWR_CSR1_BRE_Msk /*!< Backup regulator enable */
<> 161:2cc1468da177 10117 #define PWR_CSR1_VOSRDY_Pos (14U)
<> 161:2cc1468da177 10118 #define PWR_CSR1_VOSRDY_Msk (0x1U << PWR_CSR1_VOSRDY_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 10119 #define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
<> 161:2cc1468da177 10120 #define PWR_CSR1_ODRDY_Pos (16U)
<> 161:2cc1468da177 10121 #define PWR_CSR1_ODRDY_Msk (0x1U << PWR_CSR1_ODRDY_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10122 #define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk /*!< Over Drive generator ready */
<> 161:2cc1468da177 10123 #define PWR_CSR1_ODSWRDY_Pos (17U)
<> 161:2cc1468da177 10124 #define PWR_CSR1_ODSWRDY_Msk (0x1U << PWR_CSR1_ODSWRDY_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10125 #define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk /*!< Over Drive Switch ready */
<> 161:2cc1468da177 10126 #define PWR_CSR1_UDRDY_Pos (18U)
<> 161:2cc1468da177 10127 #define PWR_CSR1_UDRDY_Msk (0x3U << PWR_CSR1_UDRDY_Pos) /*!< 0x000C0000 */
<> 161:2cc1468da177 10128 #define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk /*!< Under Drive ready */
<> 144:ef7eb2e8f9f7 10129
<> 144:ef7eb2e8f9f7 10130
<> 144:ef7eb2e8f9f7 10131 /******************** Bit definition for PWR_CR2 register ********************/
<> 161:2cc1468da177 10132 #define PWR_CR2_CWUPF1_Pos (0U)
<> 161:2cc1468da177 10133 #define PWR_CR2_CWUPF1_Msk (0x1U << PWR_CR2_CWUPF1_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10134 #define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk /*!< Clear Wakeup Pin Flag for PA0 */
<> 161:2cc1468da177 10135 #define PWR_CR2_CWUPF2_Pos (1U)
<> 161:2cc1468da177 10136 #define PWR_CR2_CWUPF2_Msk (0x1U << PWR_CR2_CWUPF2_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10137 #define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk /*!< Clear Wakeup Pin Flag for PA2 */
<> 161:2cc1468da177 10138 #define PWR_CR2_CWUPF3_Pos (2U)
<> 161:2cc1468da177 10139 #define PWR_CR2_CWUPF3_Msk (0x1U << PWR_CR2_CWUPF3_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10140 #define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk /*!< Clear Wakeup Pin Flag for PC1 */
<> 161:2cc1468da177 10141 #define PWR_CR2_CWUPF4_Pos (3U)
<> 161:2cc1468da177 10142 #define PWR_CR2_CWUPF4_Msk (0x1U << PWR_CR2_CWUPF4_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10143 #define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk /*!< Clear Wakeup Pin Flag for PC13 */
<> 161:2cc1468da177 10144 #define PWR_CR2_CWUPF5_Pos (4U)
<> 161:2cc1468da177 10145 #define PWR_CR2_CWUPF5_Msk (0x1U << PWR_CR2_CWUPF5_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10146 #define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk /*!< Clear Wakeup Pin Flag for PI8 */
<> 161:2cc1468da177 10147 #define PWR_CR2_CWUPF6_Pos (5U)
<> 161:2cc1468da177 10148 #define PWR_CR2_CWUPF6_Msk (0x1U << PWR_CR2_CWUPF6_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10149 #define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk /*!< Clear Wakeup Pin Flag for PI11 */
<> 161:2cc1468da177 10150 #define PWR_CR2_WUPP1_Pos (8U)
<> 161:2cc1468da177 10151 #define PWR_CR2_WUPP1_Msk (0x1U << PWR_CR2_WUPP1_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10152 #define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk /*!< Wakeup Pin Polarity bit for PA0 */
<> 161:2cc1468da177 10153 #define PWR_CR2_WUPP2_Pos (9U)
<> 161:2cc1468da177 10154 #define PWR_CR2_WUPP2_Msk (0x1U << PWR_CR2_WUPP2_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10155 #define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk /*!< Wakeup Pin Polarity bit for PA2 */
<> 161:2cc1468da177 10156 #define PWR_CR2_WUPP3_Pos (10U)
<> 161:2cc1468da177 10157 #define PWR_CR2_WUPP3_Msk (0x1U << PWR_CR2_WUPP3_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10158 #define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk /*!< Wakeup Pin Polarity bit for PC1 */
<> 161:2cc1468da177 10159 #define PWR_CR2_WUPP4_Pos (11U)
<> 161:2cc1468da177 10160 #define PWR_CR2_WUPP4_Msk (0x1U << PWR_CR2_WUPP4_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10161 #define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk /*!< Wakeup Pin Polarity bit for PC13 */
<> 161:2cc1468da177 10162 #define PWR_CR2_WUPP5_Pos (12U)
<> 161:2cc1468da177 10163 #define PWR_CR2_WUPP5_Msk (0x1U << PWR_CR2_WUPP5_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10164 #define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk /*!< Wakeup Pin Polarity bit for PI8 */
<> 161:2cc1468da177 10165 #define PWR_CR2_WUPP6_Pos (13U)
<> 161:2cc1468da177 10166 #define PWR_CR2_WUPP6_Msk (0x1U << PWR_CR2_WUPP6_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 10167 #define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk /*!< Wakeup Pin Polarity bit for PI11 */
<> 144:ef7eb2e8f9f7 10168
<> 144:ef7eb2e8f9f7 10169 /******************* Bit definition for PWR_CSR2 register ********************/
<> 161:2cc1468da177 10170 #define PWR_CSR2_WUPF1_Pos (0U)
<> 161:2cc1468da177 10171 #define PWR_CSR2_WUPF1_Msk (0x1U << PWR_CSR2_WUPF1_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10172 #define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk /*!< Wakeup Pin Flag for PA0 */
<> 161:2cc1468da177 10173 #define PWR_CSR2_WUPF2_Pos (1U)
<> 161:2cc1468da177 10174 #define PWR_CSR2_WUPF2_Msk (0x1U << PWR_CSR2_WUPF2_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10175 #define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk /*!< Wakeup Pin Flag for PA2 */
<> 161:2cc1468da177 10176 #define PWR_CSR2_WUPF3_Pos (2U)
<> 161:2cc1468da177 10177 #define PWR_CSR2_WUPF3_Msk (0x1U << PWR_CSR2_WUPF3_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10178 #define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk /*!< Wakeup Pin Flag for PC1 */
<> 161:2cc1468da177 10179 #define PWR_CSR2_WUPF4_Pos (3U)
<> 161:2cc1468da177 10180 #define PWR_CSR2_WUPF4_Msk (0x1U << PWR_CSR2_WUPF4_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10181 #define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk /*!< Wakeup Pin Flag for PC13 */
<> 161:2cc1468da177 10182 #define PWR_CSR2_WUPF5_Pos (4U)
<> 161:2cc1468da177 10183 #define PWR_CSR2_WUPF5_Msk (0x1U << PWR_CSR2_WUPF5_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10184 #define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk /*!< Wakeup Pin Flag for PI8 */
<> 161:2cc1468da177 10185 #define PWR_CSR2_WUPF6_Pos (5U)
<> 161:2cc1468da177 10186 #define PWR_CSR2_WUPF6_Msk (0x1U << PWR_CSR2_WUPF6_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10187 #define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk /*!< Wakeup Pin Flag for PI11 */
<> 161:2cc1468da177 10188 #define PWR_CSR2_EWUP1_Pos (8U)
<> 161:2cc1468da177 10189 #define PWR_CSR2_EWUP1_Msk (0x1U << PWR_CSR2_EWUP1_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10190 #define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk /*!< Enable Wakeup Pin PA0 */
<> 161:2cc1468da177 10191 #define PWR_CSR2_EWUP2_Pos (9U)
<> 161:2cc1468da177 10192 #define PWR_CSR2_EWUP2_Msk (0x1U << PWR_CSR2_EWUP2_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10193 #define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk /*!< Enable Wakeup Pin PA2 */
<> 161:2cc1468da177 10194 #define PWR_CSR2_EWUP3_Pos (10U)
<> 161:2cc1468da177 10195 #define PWR_CSR2_EWUP3_Msk (0x1U << PWR_CSR2_EWUP3_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10196 #define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk /*!< Enable Wakeup Pin PC1 */
<> 161:2cc1468da177 10197 #define PWR_CSR2_EWUP4_Pos (11U)
<> 161:2cc1468da177 10198 #define PWR_CSR2_EWUP4_Msk (0x1U << PWR_CSR2_EWUP4_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10199 #define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk /*!< Enable Wakeup Pin PC13 */
<> 161:2cc1468da177 10200 #define PWR_CSR2_EWUP5_Pos (12U)
<> 161:2cc1468da177 10201 #define PWR_CSR2_EWUP5_Msk (0x1U << PWR_CSR2_EWUP5_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10202 #define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk /*!< Enable Wakeup Pin PI8 */
<> 161:2cc1468da177 10203 #define PWR_CSR2_EWUP6_Pos (13U)
<> 161:2cc1468da177 10204 #define PWR_CSR2_EWUP6_Msk (0x1U << PWR_CSR2_EWUP6_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 10205 #define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk /*!< Enable Wakeup Pin PI11 */
<> 144:ef7eb2e8f9f7 10206
<> 144:ef7eb2e8f9f7 10207 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10208 /* */
<> 144:ef7eb2e8f9f7 10209 /* QUADSPI */
<> 144:ef7eb2e8f9f7 10210 /* */
<> 144:ef7eb2e8f9f7 10211 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10212 /***************** Bit definition for QUADSPI_CR register *******************/
<> 161:2cc1468da177 10213 #define QUADSPI_CR_EN_Pos (0U)
<> 161:2cc1468da177 10214 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10215 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
<> 161:2cc1468da177 10216 #define QUADSPI_CR_ABORT_Pos (1U)
<> 161:2cc1468da177 10217 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10218 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
<> 161:2cc1468da177 10219 #define QUADSPI_CR_DMAEN_Pos (2U)
<> 161:2cc1468da177 10220 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10221 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
<> 161:2cc1468da177 10222 #define QUADSPI_CR_TCEN_Pos (3U)
<> 161:2cc1468da177 10223 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10224 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
<> 161:2cc1468da177 10225 #define QUADSPI_CR_SSHIFT_Pos (4U)
<> 161:2cc1468da177 10226 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10227 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
<> 161:2cc1468da177 10228 #define QUADSPI_CR_DFM_Pos (6U)
<> 161:2cc1468da177 10229 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10230 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
<> 161:2cc1468da177 10231 #define QUADSPI_CR_FSEL_Pos (7U)
<> 161:2cc1468da177 10232 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10233 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
<> 161:2cc1468da177 10234 #define QUADSPI_CR_FTHRES_Pos (8U)
<> 161:2cc1468da177 10235 #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
<> 161:2cc1468da177 10236 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
<> 161:2cc1468da177 10237 #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10238 #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10239 #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10240 #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10241 #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10242 #define QUADSPI_CR_TEIE_Pos (16U)
<> 161:2cc1468da177 10243 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10244 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
<> 161:2cc1468da177 10245 #define QUADSPI_CR_TCIE_Pos (17U)
<> 161:2cc1468da177 10246 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10247 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
<> 161:2cc1468da177 10248 #define QUADSPI_CR_FTIE_Pos (18U)
<> 161:2cc1468da177 10249 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 10250 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
<> 161:2cc1468da177 10251 #define QUADSPI_CR_SMIE_Pos (19U)
<> 161:2cc1468da177 10252 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 10253 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
<> 161:2cc1468da177 10254 #define QUADSPI_CR_TOIE_Pos (20U)
<> 161:2cc1468da177 10255 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 10256 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
<> 161:2cc1468da177 10257 #define QUADSPI_CR_APMS_Pos (22U)
<> 161:2cc1468da177 10258 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 10259 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
<> 161:2cc1468da177 10260 #define QUADSPI_CR_PMM_Pos (23U)
<> 161:2cc1468da177 10261 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 10262 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
<> 161:2cc1468da177 10263 #define QUADSPI_CR_PRESCALER_Pos (24U)
<> 161:2cc1468da177 10264 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 10265 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
<> 161:2cc1468da177 10266 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 10267 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 10268 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 10269 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 10270 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 10271 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 10272 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 10273 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 10274
<> 144:ef7eb2e8f9f7 10275 /***************** Bit definition for QUADSPI_DCR register ******************/
<> 161:2cc1468da177 10276 #define QUADSPI_DCR_CKMODE_Pos (0U)
<> 161:2cc1468da177 10277 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10278 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
<> 161:2cc1468da177 10279 #define QUADSPI_DCR_CSHT_Pos (8U)
<> 161:2cc1468da177 10280 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
<> 161:2cc1468da177 10281 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
<> 161:2cc1468da177 10282 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10283 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10284 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10285 #define QUADSPI_DCR_FSIZE_Pos (16U)
<> 161:2cc1468da177 10286 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
<> 161:2cc1468da177 10287 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
<> 161:2cc1468da177 10288 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10289 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10290 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 10291 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 10292 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10293
<> 144:ef7eb2e8f9f7 10294 /****************** Bit definition for QUADSPI_SR register *******************/
<> 161:2cc1468da177 10295 #define QUADSPI_SR_TEF_Pos (0U)
<> 161:2cc1468da177 10296 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10297 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
<> 161:2cc1468da177 10298 #define QUADSPI_SR_TCF_Pos (1U)
<> 161:2cc1468da177 10299 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10300 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
<> 161:2cc1468da177 10301 #define QUADSPI_SR_FTF_Pos (2U)
<> 161:2cc1468da177 10302 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10303 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
<> 161:2cc1468da177 10304 #define QUADSPI_SR_SMF_Pos (3U)
<> 161:2cc1468da177 10305 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10306 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
<> 161:2cc1468da177 10307 #define QUADSPI_SR_TOF_Pos (4U)
<> 161:2cc1468da177 10308 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10309 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
<> 161:2cc1468da177 10310 #define QUADSPI_SR_BUSY_Pos (5U)
<> 161:2cc1468da177 10311 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10312 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
<> 161:2cc1468da177 10313 #define QUADSPI_SR_FLEVEL_Pos (8U)
<> 161:2cc1468da177 10314 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
<> 161:2cc1468da177 10315 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
<> 161:2cc1468da177 10316 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10317 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10318 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10319 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10320 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 10321
<> 144:ef7eb2e8f9f7 10322 /****************** Bit definition for QUADSPI_FCR register ******************/
<> 161:2cc1468da177 10323 #define QUADSPI_FCR_CTEF_Pos (0U)
<> 161:2cc1468da177 10324 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10325 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
<> 161:2cc1468da177 10326 #define QUADSPI_FCR_CTCF_Pos (1U)
<> 161:2cc1468da177 10327 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10328 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
<> 161:2cc1468da177 10329 #define QUADSPI_FCR_CSMF_Pos (3U)
<> 161:2cc1468da177 10330 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10331 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
<> 161:2cc1468da177 10332 #define QUADSPI_FCR_CTOF_Pos (4U)
<> 161:2cc1468da177 10333 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10334 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
<> 144:ef7eb2e8f9f7 10335
<> 144:ef7eb2e8f9f7 10336 /****************** Bit definition for QUADSPI_DLR register ******************/
<> 161:2cc1468da177 10337 #define QUADSPI_DLR_DL_Pos (0U)
<> 161:2cc1468da177 10338 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 10339 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
<> 144:ef7eb2e8f9f7 10340
<> 144:ef7eb2e8f9f7 10341 /****************** Bit definition for QUADSPI_CCR register ******************/
<> 161:2cc1468da177 10342 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
<> 161:2cc1468da177 10343 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 10344 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
<> 161:2cc1468da177 10345 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10346 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10347 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10348 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10349 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10350 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10351 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10352 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10353 #define QUADSPI_CCR_IMODE_Pos (8U)
<> 161:2cc1468da177 10354 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 10355 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
<> 161:2cc1468da177 10356 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10357 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10358 #define QUADSPI_CCR_ADMODE_Pos (10U)
<> 161:2cc1468da177 10359 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 10360 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
<> 161:2cc1468da177 10361 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10362 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10363 #define QUADSPI_CCR_ADSIZE_Pos (12U)
<> 161:2cc1468da177 10364 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
<> 161:2cc1468da177 10365 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
<> 161:2cc1468da177 10366 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10367 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 10368 #define QUADSPI_CCR_ABMODE_Pos (14U)
<> 161:2cc1468da177 10369 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 10370 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
<> 161:2cc1468da177 10371 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 10372 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 10373 #define QUADSPI_CCR_ABSIZE_Pos (16U)
<> 161:2cc1468da177 10374 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 10375 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
<> 161:2cc1468da177 10376 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10377 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10378 #define QUADSPI_CCR_DCYC_Pos (18U)
<> 161:2cc1468da177 10379 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
<> 161:2cc1468da177 10380 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
<> 161:2cc1468da177 10381 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 10382 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 10383 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 10384 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 10385 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 10386 #define QUADSPI_CCR_DMODE_Pos (24U)
<> 161:2cc1468da177 10387 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
<> 161:2cc1468da177 10388 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
<> 161:2cc1468da177 10389 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 10390 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 10391 #define QUADSPI_CCR_FMODE_Pos (26U)
<> 161:2cc1468da177 10392 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
<> 161:2cc1468da177 10393 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
<> 161:2cc1468da177 10394 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 10395 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 10396 #define QUADSPI_CCR_SIOO_Pos (28U)
<> 161:2cc1468da177 10397 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 10398 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
<> 161:2cc1468da177 10399 #define QUADSPI_CCR_DHHC_Pos (30U)
<> 161:2cc1468da177 10400 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 10401 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
<> 161:2cc1468da177 10402 #define QUADSPI_CCR_DDRM_Pos (31U)
<> 161:2cc1468da177 10403 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 10404 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
<> 144:ef7eb2e8f9f7 10405 /****************** Bit definition for QUADSPI_AR register *******************/
<> 161:2cc1468da177 10406 #define QUADSPI_AR_ADDRESS_Pos (0U)
<> 161:2cc1468da177 10407 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 10408 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
<> 144:ef7eb2e8f9f7 10409
<> 144:ef7eb2e8f9f7 10410 /****************** Bit definition for QUADSPI_ABR register ******************/
<> 161:2cc1468da177 10411 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
<> 161:2cc1468da177 10412 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 10413 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
<> 144:ef7eb2e8f9f7 10414
<> 144:ef7eb2e8f9f7 10415 /****************** Bit definition for QUADSPI_DR register *******************/
<> 161:2cc1468da177 10416 #define QUADSPI_DR_DATA_Pos (0U)
<> 161:2cc1468da177 10417 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 10418 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
<> 144:ef7eb2e8f9f7 10419
<> 144:ef7eb2e8f9f7 10420 /****************** Bit definition for QUADSPI_PSMKR register ****************/
<> 161:2cc1468da177 10421 #define QUADSPI_PSMKR_MASK_Pos (0U)
<> 161:2cc1468da177 10422 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 10423 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
<> 144:ef7eb2e8f9f7 10424
<> 144:ef7eb2e8f9f7 10425 /****************** Bit definition for QUADSPI_PSMAR register ****************/
<> 161:2cc1468da177 10426 #define QUADSPI_PSMAR_MATCH_Pos (0U)
<> 161:2cc1468da177 10427 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 10428 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
<> 144:ef7eb2e8f9f7 10429
<> 144:ef7eb2e8f9f7 10430 /****************** Bit definition for QUADSPI_PIR register *****************/
<> 161:2cc1468da177 10431 #define QUADSPI_PIR_INTERVAL_Pos (0U)
<> 161:2cc1468da177 10432 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 10433 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
<> 144:ef7eb2e8f9f7 10434
<> 144:ef7eb2e8f9f7 10435 /****************** Bit definition for QUADSPI_LPTR register *****************/
<> 161:2cc1468da177 10436 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
<> 161:2cc1468da177 10437 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 10438 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
<> 144:ef7eb2e8f9f7 10439
<> 144:ef7eb2e8f9f7 10440 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10441 /* */
<> 144:ef7eb2e8f9f7 10442 /* Reset and Clock Control */
<> 144:ef7eb2e8f9f7 10443 /* */
<> 144:ef7eb2e8f9f7 10444 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10445 /******************** Bit definition for RCC_CR register ********************/
<> 161:2cc1468da177 10446 #define RCC_CR_HSION_Pos (0U)
<> 161:2cc1468da177 10447 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10448 #define RCC_CR_HSION RCC_CR_HSION_Msk
<> 161:2cc1468da177 10449 #define RCC_CR_HSIRDY_Pos (1U)
<> 161:2cc1468da177 10450 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10451 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
<> 161:2cc1468da177 10452 #define RCC_CR_HSITRIM_Pos (3U)
<> 161:2cc1468da177 10453 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
<> 161:2cc1468da177 10454 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
<> 161:2cc1468da177 10455 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10456 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10457 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10458 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10459 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10460 #define RCC_CR_HSICAL_Pos (8U)
<> 161:2cc1468da177 10461 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 10462 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
<> 161:2cc1468da177 10463 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10464 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10465 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10466 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10467 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10468 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 10469 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 10470 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 10471 #define RCC_CR_HSEON_Pos (16U)
<> 161:2cc1468da177 10472 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10473 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
<> 161:2cc1468da177 10474 #define RCC_CR_HSERDY_Pos (17U)
<> 161:2cc1468da177 10475 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10476 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
<> 161:2cc1468da177 10477 #define RCC_CR_HSEBYP_Pos (18U)
<> 161:2cc1468da177 10478 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 10479 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
<> 161:2cc1468da177 10480 #define RCC_CR_CSSON_Pos (19U)
<> 161:2cc1468da177 10481 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 10482 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
<> 161:2cc1468da177 10483 #define RCC_CR_PLLON_Pos (24U)
<> 161:2cc1468da177 10484 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 10485 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
<> 161:2cc1468da177 10486 #define RCC_CR_PLLRDY_Pos (25U)
<> 161:2cc1468da177 10487 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 10488 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
<> 161:2cc1468da177 10489 #define RCC_CR_PLLI2SON_Pos (26U)
<> 161:2cc1468da177 10490 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 10491 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
<> 161:2cc1468da177 10492 #define RCC_CR_PLLI2SRDY_Pos (27U)
<> 161:2cc1468da177 10493 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 10494 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
<> 161:2cc1468da177 10495 #define RCC_CR_PLLSAION_Pos (28U)
<> 161:2cc1468da177 10496 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 10497 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
<> 161:2cc1468da177 10498 #define RCC_CR_PLLSAIRDY_Pos (29U)
<> 161:2cc1468da177 10499 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 10500 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
<> 144:ef7eb2e8f9f7 10501
<> 144:ef7eb2e8f9f7 10502 /******************** Bit definition for RCC_PLLCFGR register ***************/
<> 161:2cc1468da177 10503 #define RCC_PLLCFGR_PLLM_Pos (0U)
<> 161:2cc1468da177 10504 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
<> 161:2cc1468da177 10505 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
<> 161:2cc1468da177 10506 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10507 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10508 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10509 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10510 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10511 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10512 #define RCC_PLLCFGR_PLLN_Pos (6U)
<> 161:2cc1468da177 10513 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
<> 161:2cc1468da177 10514 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
<> 161:2cc1468da177 10515 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10516 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10517 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10518 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10519 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10520 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10521 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10522 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 10523 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 10524 #define RCC_PLLCFGR_PLLP_Pos (16U)
<> 161:2cc1468da177 10525 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 10526 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
<> 161:2cc1468da177 10527 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10528 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10529 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
<> 161:2cc1468da177 10530 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 10531 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
<> 161:2cc1468da177 10532 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
<> 161:2cc1468da177 10533 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 10534 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
<> 161:2cc1468da177 10535 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
<> 161:2cc1468da177 10536 #define RCC_PLLCFGR_PLLQ_Pos (24U)
<> 161:2cc1468da177 10537 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 10538 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
<> 161:2cc1468da177 10539 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 10540 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 10541 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 10542 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 10543
<> 161:2cc1468da177 10544 #define RCC_PLLCFGR_PLLR_Pos (28U)
<> 161:2cc1468da177 10545 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
<> 161:2cc1468da177 10546 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
<> 161:2cc1468da177 10547 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 10548 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 10549 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 10550
<> 144:ef7eb2e8f9f7 10551 /******************** Bit definition for RCC_CFGR register ******************/
<> 144:ef7eb2e8f9f7 10552 /*!< SW configuration */
<> 161:2cc1468da177 10553 #define RCC_CFGR_SW_Pos (0U)
<> 161:2cc1468da177 10554 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 10555 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
<> 161:2cc1468da177 10556 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10557 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10558 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
<> 161:2cc1468da177 10559 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
<> 161:2cc1468da177 10560 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
<> 144:ef7eb2e8f9f7 10561
<> 144:ef7eb2e8f9f7 10562 /*!< SWS configuration */
<> 161:2cc1468da177 10563 #define RCC_CFGR_SWS_Pos (2U)
<> 161:2cc1468da177 10564 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 10565 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 161:2cc1468da177 10566 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10567 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10568 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
<> 161:2cc1468da177 10569 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
<> 161:2cc1468da177 10570 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
<> 144:ef7eb2e8f9f7 10571
<> 144:ef7eb2e8f9f7 10572 /*!< HPRE configuration */
<> 161:2cc1468da177 10573 #define RCC_CFGR_HPRE_Pos (4U)
<> 161:2cc1468da177 10574 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 10575 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
<> 161:2cc1468da177 10576 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10577 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10578 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10579 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10580
<> 161:2cc1468da177 10581 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
<> 161:2cc1468da177 10582 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
<> 161:2cc1468da177 10583 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
<> 161:2cc1468da177 10584 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
<> 161:2cc1468da177 10585 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
<> 161:2cc1468da177 10586 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
<> 161:2cc1468da177 10587 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
<> 161:2cc1468da177 10588 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
<> 161:2cc1468da177 10589 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
<> 144:ef7eb2e8f9f7 10590
<> 144:ef7eb2e8f9f7 10591 /*!< PPRE1 configuration */
<> 161:2cc1468da177 10592 #define RCC_CFGR_PPRE1_Pos (10U)
<> 161:2cc1468da177 10593 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
<> 161:2cc1468da177 10594 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 161:2cc1468da177 10595 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10596 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10597 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10598
<> 161:2cc1468da177 10599 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
<> 161:2cc1468da177 10600 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
<> 161:2cc1468da177 10601 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
<> 161:2cc1468da177 10602 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
<> 161:2cc1468da177 10603 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 10604
<> 144:ef7eb2e8f9f7 10605 /*!< PPRE2 configuration */
<> 161:2cc1468da177 10606 #define RCC_CFGR_PPRE2_Pos (13U)
<> 161:2cc1468da177 10607 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
<> 161:2cc1468da177 10608 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 161:2cc1468da177 10609 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 10610 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 10611 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 10612
<> 161:2cc1468da177 10613 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
<> 161:2cc1468da177 10614 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
<> 161:2cc1468da177 10615 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
<> 161:2cc1468da177 10616 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
<> 161:2cc1468da177 10617 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 10618
<> 144:ef7eb2e8f9f7 10619 /*!< RTCPRE configuration */
<> 161:2cc1468da177 10620 #define RCC_CFGR_RTCPRE_Pos (16U)
<> 161:2cc1468da177 10621 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
<> 161:2cc1468da177 10622 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
<> 161:2cc1468da177 10623 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10624 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10625 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 10626 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 10627 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10628
<> 144:ef7eb2e8f9f7 10629 /*!< MCO1 configuration */
<> 161:2cc1468da177 10630 #define RCC_CFGR_MCO1_Pos (21U)
<> 161:2cc1468da177 10631 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
<> 161:2cc1468da177 10632 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
<> 161:2cc1468da177 10633 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 10634 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 10635
<> 161:2cc1468da177 10636 #define RCC_CFGR_I2SSRC_Pos (23U)
<> 161:2cc1468da177 10637 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 10638 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
<> 161:2cc1468da177 10639
<> 161:2cc1468da177 10640 #define RCC_CFGR_MCO1PRE_Pos (24U)
<> 161:2cc1468da177 10641 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
<> 161:2cc1468da177 10642 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
<> 161:2cc1468da177 10643 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 10644 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 10645 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 10646
<> 161:2cc1468da177 10647 #define RCC_CFGR_MCO2PRE_Pos (27U)
<> 161:2cc1468da177 10648 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
<> 161:2cc1468da177 10649 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
<> 161:2cc1468da177 10650 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 10651 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 10652 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 10653
<> 161:2cc1468da177 10654 #define RCC_CFGR_MCO2_Pos (30U)
<> 161:2cc1468da177 10655 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
<> 161:2cc1468da177 10656 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
<> 161:2cc1468da177 10657 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 10658 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 10659
<> 144:ef7eb2e8f9f7 10660 /******************** Bit definition for RCC_CIR register *******************/
<> 161:2cc1468da177 10661 #define RCC_CIR_LSIRDYF_Pos (0U)
<> 161:2cc1468da177 10662 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10663 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
<> 161:2cc1468da177 10664 #define RCC_CIR_LSERDYF_Pos (1U)
<> 161:2cc1468da177 10665 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10666 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
<> 161:2cc1468da177 10667 #define RCC_CIR_HSIRDYF_Pos (2U)
<> 161:2cc1468da177 10668 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10669 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
<> 161:2cc1468da177 10670 #define RCC_CIR_HSERDYF_Pos (3U)
<> 161:2cc1468da177 10671 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10672 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
<> 161:2cc1468da177 10673 #define RCC_CIR_PLLRDYF_Pos (4U)
<> 161:2cc1468da177 10674 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10675 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
<> 161:2cc1468da177 10676 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
<> 161:2cc1468da177 10677 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10678 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
<> 161:2cc1468da177 10679 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
<> 161:2cc1468da177 10680 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10681 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
<> 161:2cc1468da177 10682 #define RCC_CIR_CSSF_Pos (7U)
<> 161:2cc1468da177 10683 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10684 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
<> 161:2cc1468da177 10685 #define RCC_CIR_LSIRDYIE_Pos (8U)
<> 161:2cc1468da177 10686 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10687 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
<> 161:2cc1468da177 10688 #define RCC_CIR_LSERDYIE_Pos (9U)
<> 161:2cc1468da177 10689 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10690 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
<> 161:2cc1468da177 10691 #define RCC_CIR_HSIRDYIE_Pos (10U)
<> 161:2cc1468da177 10692 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10693 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
<> 161:2cc1468da177 10694 #define RCC_CIR_HSERDYIE_Pos (11U)
<> 161:2cc1468da177 10695 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10696 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
<> 161:2cc1468da177 10697 #define RCC_CIR_PLLRDYIE_Pos (12U)
<> 161:2cc1468da177 10698 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10699 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
<> 161:2cc1468da177 10700 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
<> 161:2cc1468da177 10701 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 10702 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
<> 161:2cc1468da177 10703 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
<> 161:2cc1468da177 10704 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 10705 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
<> 161:2cc1468da177 10706 #define RCC_CIR_LSIRDYC_Pos (16U)
<> 161:2cc1468da177 10707 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10708 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
<> 161:2cc1468da177 10709 #define RCC_CIR_LSERDYC_Pos (17U)
<> 161:2cc1468da177 10710 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10711 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
<> 161:2cc1468da177 10712 #define RCC_CIR_HSIRDYC_Pos (18U)
<> 161:2cc1468da177 10713 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 10714 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
<> 161:2cc1468da177 10715 #define RCC_CIR_HSERDYC_Pos (19U)
<> 161:2cc1468da177 10716 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 10717 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
<> 161:2cc1468da177 10718 #define RCC_CIR_PLLRDYC_Pos (20U)
<> 161:2cc1468da177 10719 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 10720 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
<> 161:2cc1468da177 10721 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
<> 161:2cc1468da177 10722 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 10723 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
<> 161:2cc1468da177 10724 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
<> 161:2cc1468da177 10725 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 10726 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
<> 161:2cc1468da177 10727 #define RCC_CIR_CSSC_Pos (23U)
<> 161:2cc1468da177 10728 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 10729 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
<> 144:ef7eb2e8f9f7 10730
<> 144:ef7eb2e8f9f7 10731 /******************** Bit definition for RCC_AHB1RSTR register **************/
<> 161:2cc1468da177 10732 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
<> 161:2cc1468da177 10733 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10734 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
<> 161:2cc1468da177 10735 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
<> 161:2cc1468da177 10736 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10737 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
<> 161:2cc1468da177 10738 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
<> 161:2cc1468da177 10739 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10740 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
<> 161:2cc1468da177 10741 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
<> 161:2cc1468da177 10742 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10743 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
<> 161:2cc1468da177 10744 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
<> 161:2cc1468da177 10745 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10746 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
<> 161:2cc1468da177 10747 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
<> 161:2cc1468da177 10748 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10749 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
<> 161:2cc1468da177 10750 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
<> 161:2cc1468da177 10751 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10752 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
<> 161:2cc1468da177 10753 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
<> 161:2cc1468da177 10754 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10755 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
<> 161:2cc1468da177 10756 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
<> 161:2cc1468da177 10757 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10758 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
<> 161:2cc1468da177 10759 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
<> 161:2cc1468da177 10760 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10761 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
<> 161:2cc1468da177 10762 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
<> 161:2cc1468da177 10763 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10764 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
<> 161:2cc1468da177 10765 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
<> 161:2cc1468da177 10766 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10767 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
<> 161:2cc1468da177 10768 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
<> 161:2cc1468da177 10769 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 10770 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
<> 161:2cc1468da177 10771 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
<> 161:2cc1468da177 10772 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 10773 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
<> 161:2cc1468da177 10774 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
<> 161:2cc1468da177 10775 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 10776 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
<> 161:2cc1468da177 10777 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
<> 161:2cc1468da177 10778 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 10779 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
<> 161:2cc1468da177 10780 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
<> 161:2cc1468da177 10781 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 10782 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
<> 144:ef7eb2e8f9f7 10783
<> 144:ef7eb2e8f9f7 10784 /******************** Bit definition for RCC_AHB2RSTR register **************/
<> 161:2cc1468da177 10785 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
<> 161:2cc1468da177 10786 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10787 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
<> 161:2cc1468da177 10788 #define RCC_AHB2RSTR_JPEGRST_Pos (1U)
<> 161:2cc1468da177 10789 #define RCC_AHB2RSTR_JPEGRST_Msk (0x1U << RCC_AHB2RSTR_JPEGRST_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10790 #define RCC_AHB2RSTR_JPEGRST RCC_AHB2RSTR_JPEGRST_Msk
<> 161:2cc1468da177 10791 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
<> 161:2cc1468da177 10792 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10793 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
<> 161:2cc1468da177 10794 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
<> 161:2cc1468da177 10795 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10796 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
<> 144:ef7eb2e8f9f7 10797
<> 144:ef7eb2e8f9f7 10798 /******************** Bit definition for RCC_AHB3RSTR register **************/
<> 144:ef7eb2e8f9f7 10799
<> 161:2cc1468da177 10800 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
<> 161:2cc1468da177 10801 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10802 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
<> 161:2cc1468da177 10803 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
<> 161:2cc1468da177 10804 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10805 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
<> 144:ef7eb2e8f9f7 10806
<> 144:ef7eb2e8f9f7 10807 /******************** Bit definition for RCC_APB1RSTR register **************/
<> 161:2cc1468da177 10808 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
<> 161:2cc1468da177 10809 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10810 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
<> 161:2cc1468da177 10811 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
<> 161:2cc1468da177 10812 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10813 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
<> 161:2cc1468da177 10814 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
<> 161:2cc1468da177 10815 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10816 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
<> 161:2cc1468da177 10817 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
<> 161:2cc1468da177 10818 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10819 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
<> 161:2cc1468da177 10820 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
<> 161:2cc1468da177 10821 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10822 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
<> 161:2cc1468da177 10823 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
<> 161:2cc1468da177 10824 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10825 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
<> 161:2cc1468da177 10826 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
<> 161:2cc1468da177 10827 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10828 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
<> 161:2cc1468da177 10829 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
<> 161:2cc1468da177 10830 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10831 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
<> 161:2cc1468da177 10832 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
<> 161:2cc1468da177 10833 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10834 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
<> 161:2cc1468da177 10835 #define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
<> 161:2cc1468da177 10836 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10837 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
<> 161:2cc1468da177 10838 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
<> 161:2cc1468da177 10839 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10840 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
<> 161:2cc1468da177 10841 #define RCC_APB1RSTR_CAN3RST_Pos (13U)
<> 161:2cc1468da177 10842 #define RCC_APB1RSTR_CAN3RST_Msk (0x1U << RCC_APB1RSTR_CAN3RST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 10843 #define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
<> 161:2cc1468da177 10844 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
<> 161:2cc1468da177 10845 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 10846 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
<> 161:2cc1468da177 10847 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
<> 161:2cc1468da177 10848 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 10849 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
<> 161:2cc1468da177 10850 #define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
<> 161:2cc1468da177 10851 #define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1U << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10852 #define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
<> 161:2cc1468da177 10853 #define RCC_APB1RSTR_USART2RST_Pos (17U)
<> 161:2cc1468da177 10854 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10855 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
<> 161:2cc1468da177 10856 #define RCC_APB1RSTR_USART3RST_Pos (18U)
<> 161:2cc1468da177 10857 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 10858 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
<> 161:2cc1468da177 10859 #define RCC_APB1RSTR_UART4RST_Pos (19U)
<> 161:2cc1468da177 10860 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 10861 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
<> 161:2cc1468da177 10862 #define RCC_APB1RSTR_UART5RST_Pos (20U)
<> 161:2cc1468da177 10863 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 10864 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
<> 161:2cc1468da177 10865 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
<> 161:2cc1468da177 10866 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 10867 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
<> 161:2cc1468da177 10868 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
<> 161:2cc1468da177 10869 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 10870 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
<> 161:2cc1468da177 10871 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
<> 161:2cc1468da177 10872 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 10873 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
<> 161:2cc1468da177 10874 #define RCC_APB1RSTR_I2C4RST_Pos (24U)
<> 161:2cc1468da177 10875 #define RCC_APB1RSTR_I2C4RST_Msk (0x1U << RCC_APB1RSTR_I2C4RST_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 10876 #define RCC_APB1RSTR_I2C4RST RCC_APB1RSTR_I2C4RST_Msk
<> 161:2cc1468da177 10877 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
<> 161:2cc1468da177 10878 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 10879 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
<> 161:2cc1468da177 10880 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
<> 161:2cc1468da177 10881 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 10882 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
<> 161:2cc1468da177 10883 #define RCC_APB1RSTR_CECRST_Pos (27U)
<> 161:2cc1468da177 10884 #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 10885 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
<> 161:2cc1468da177 10886 #define RCC_APB1RSTR_PWRRST_Pos (28U)
<> 161:2cc1468da177 10887 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 10888 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
<> 161:2cc1468da177 10889 #define RCC_APB1RSTR_DACRST_Pos (29U)
<> 161:2cc1468da177 10890 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 10891 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
<> 161:2cc1468da177 10892 #define RCC_APB1RSTR_UART7RST_Pos (30U)
<> 161:2cc1468da177 10893 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 10894 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
<> 161:2cc1468da177 10895 #define RCC_APB1RSTR_UART8RST_Pos (31U)
<> 161:2cc1468da177 10896 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 10897 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
<> 144:ef7eb2e8f9f7 10898
<> 144:ef7eb2e8f9f7 10899 /******************** Bit definition for RCC_APB2RSTR register **************/
<> 161:2cc1468da177 10900 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
<> 161:2cc1468da177 10901 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10902 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
<> 161:2cc1468da177 10903 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
<> 161:2cc1468da177 10904 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10905 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
<> 161:2cc1468da177 10906 #define RCC_APB2RSTR_USART1RST_Pos (4U)
<> 161:2cc1468da177 10907 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10908 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
<> 161:2cc1468da177 10909 #define RCC_APB2RSTR_USART6RST_Pos (5U)
<> 161:2cc1468da177 10910 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10911 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
<> 161:2cc1468da177 10912 #define RCC_APB2RSTR_SDMMC2RST_Pos (7U)
<> 161:2cc1468da177 10913 #define RCC_APB2RSTR_SDMMC2RST_Msk (0x1U << RCC_APB2RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10914 #define RCC_APB2RSTR_SDMMC2RST RCC_APB2RSTR_SDMMC2RST_Msk
<> 161:2cc1468da177 10915 #define RCC_APB2RSTR_ADCRST_Pos (8U)
<> 161:2cc1468da177 10916 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10917 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
<> 161:2cc1468da177 10918 #define RCC_APB2RSTR_SDMMC1RST_Pos (11U)
<> 161:2cc1468da177 10919 #define RCC_APB2RSTR_SDMMC1RST_Msk (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 10920 #define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
<> 161:2cc1468da177 10921 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
<> 161:2cc1468da177 10922 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10923 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
<> 161:2cc1468da177 10924 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
<> 161:2cc1468da177 10925 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 10926 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
<> 161:2cc1468da177 10927 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
<> 161:2cc1468da177 10928 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 10929 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
<> 161:2cc1468da177 10930 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
<> 161:2cc1468da177 10931 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 10932 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
<> 161:2cc1468da177 10933 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
<> 161:2cc1468da177 10934 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 10935 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
<> 161:2cc1468da177 10936 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
<> 161:2cc1468da177 10937 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 10938 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
<> 161:2cc1468da177 10939 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
<> 161:2cc1468da177 10940 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 10941 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
<> 161:2cc1468da177 10942 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
<> 161:2cc1468da177 10943 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 10944 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
<> 161:2cc1468da177 10945 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
<> 161:2cc1468da177 10946 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 10947 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
<> 161:2cc1468da177 10948 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
<> 161:2cc1468da177 10949 #define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 10950 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
<> 161:2cc1468da177 10951 #define RCC_APB2RSTR_LTDCRST_Pos (26U)
<> 161:2cc1468da177 10952 #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 10953 #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
<> 161:2cc1468da177 10954 #define RCC_APB2RSTR_DFSDM1RST_Pos (29U)
<> 161:2cc1468da177 10955 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 10956 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
<> 161:2cc1468da177 10957 #define RCC_APB2RSTR_MDIORST_Pos (30U)
<> 161:2cc1468da177 10958 #define RCC_APB2RSTR_MDIORST_Msk (0x1U << RCC_APB2RSTR_MDIORST_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 10959 #define RCC_APB2RSTR_MDIORST RCC_APB2RSTR_MDIORST_Msk
<> 144:ef7eb2e8f9f7 10960
<> 144:ef7eb2e8f9f7 10961 /******************** Bit definition for RCC_AHB1ENR register ***************/
<> 161:2cc1468da177 10962 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
<> 161:2cc1468da177 10963 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 10964 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
<> 161:2cc1468da177 10965 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
<> 161:2cc1468da177 10966 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 10967 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
<> 161:2cc1468da177 10968 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
<> 161:2cc1468da177 10969 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 10970 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
<> 161:2cc1468da177 10971 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
<> 161:2cc1468da177 10972 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 10973 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
<> 161:2cc1468da177 10974 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
<> 161:2cc1468da177 10975 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 10976 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
<> 161:2cc1468da177 10977 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
<> 161:2cc1468da177 10978 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 10979 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
<> 161:2cc1468da177 10980 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
<> 161:2cc1468da177 10981 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 10982 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
<> 161:2cc1468da177 10983 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
<> 161:2cc1468da177 10984 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 10985 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
<> 161:2cc1468da177 10986 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
<> 161:2cc1468da177 10987 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 10988 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
<> 161:2cc1468da177 10989 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
<> 161:2cc1468da177 10990 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 10991 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
<> 161:2cc1468da177 10992 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
<> 161:2cc1468da177 10993 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 10994 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
<> 161:2cc1468da177 10995 #define RCC_AHB1ENR_CRCEN_Pos (12U)
<> 161:2cc1468da177 10996 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 10997 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
<> 161:2cc1468da177 10998 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
<> 161:2cc1468da177 10999 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 11000 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
<> 161:2cc1468da177 11001 #define RCC_AHB1ENR_DTCMRAMEN_Pos (20U)
<> 161:2cc1468da177 11002 #define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1U << RCC_AHB1ENR_DTCMRAMEN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11003 #define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk
<> 161:2cc1468da177 11004 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
<> 161:2cc1468da177 11005 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11006 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
<> 161:2cc1468da177 11007 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
<> 161:2cc1468da177 11008 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11009 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
<> 161:2cc1468da177 11010 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
<> 161:2cc1468da177 11011 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 11012 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
<> 161:2cc1468da177 11013 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
<> 161:2cc1468da177 11014 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 11015 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
<> 161:2cc1468da177 11016 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
<> 161:2cc1468da177 11017 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11018 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
<> 161:2cc1468da177 11019 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
<> 161:2cc1468da177 11020 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 11021 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
<> 161:2cc1468da177 11022 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
<> 161:2cc1468da177 11023 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 11024 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
<> 161:2cc1468da177 11025 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
<> 161:2cc1468da177 11026 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 11027 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
<> 161:2cc1468da177 11028 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
<> 161:2cc1468da177 11029 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 11030 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
<> 144:ef7eb2e8f9f7 11031
<> 144:ef7eb2e8f9f7 11032 /******************** Bit definition for RCC_AHB2ENR register ***************/
<> 161:2cc1468da177 11033 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
<> 161:2cc1468da177 11034 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11035 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
<> 161:2cc1468da177 11036 #define RCC_AHB2ENR_JPEGEN_Pos (1U)
<> 161:2cc1468da177 11037 #define RCC_AHB2ENR_JPEGEN_Msk (0x1U << RCC_AHB2ENR_JPEGEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11038 #define RCC_AHB2ENR_JPEGEN RCC_AHB2ENR_JPEGEN_Msk
<> 161:2cc1468da177 11039 #define RCC_AHB2ENR_RNGEN_Pos (6U)
<> 161:2cc1468da177 11040 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11041 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
<> 161:2cc1468da177 11042 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
<> 161:2cc1468da177 11043 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11044 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
<> 144:ef7eb2e8f9f7 11045
<> 144:ef7eb2e8f9f7 11046 /******************** Bit definition for RCC_AHB3ENR register ***************/
<> 161:2cc1468da177 11047 #define RCC_AHB3ENR_FMCEN_Pos (0U)
<> 161:2cc1468da177 11048 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11049 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
<> 161:2cc1468da177 11050 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
<> 161:2cc1468da177 11051 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11052 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
<> 144:ef7eb2e8f9f7 11053
<> 144:ef7eb2e8f9f7 11054 /******************** Bit definition for RCC_APB1ENR register ***************/
<> 161:2cc1468da177 11055 #define RCC_APB1ENR_TIM2EN_Pos (0U)
<> 161:2cc1468da177 11056 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11057 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
<> 161:2cc1468da177 11058 #define RCC_APB1ENR_TIM3EN_Pos (1U)
<> 161:2cc1468da177 11059 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11060 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
<> 161:2cc1468da177 11061 #define RCC_APB1ENR_TIM4EN_Pos (2U)
<> 161:2cc1468da177 11062 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11063 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
<> 161:2cc1468da177 11064 #define RCC_APB1ENR_TIM5EN_Pos (3U)
<> 161:2cc1468da177 11065 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 11066 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
<> 161:2cc1468da177 11067 #define RCC_APB1ENR_TIM6EN_Pos (4U)
<> 161:2cc1468da177 11068 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11069 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
<> 161:2cc1468da177 11070 #define RCC_APB1ENR_TIM7EN_Pos (5U)
<> 161:2cc1468da177 11071 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11072 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
<> 161:2cc1468da177 11073 #define RCC_APB1ENR_TIM12EN_Pos (6U)
<> 161:2cc1468da177 11074 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11075 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
<> 161:2cc1468da177 11076 #define RCC_APB1ENR_TIM13EN_Pos (7U)
<> 161:2cc1468da177 11077 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11078 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
<> 161:2cc1468da177 11079 #define RCC_APB1ENR_TIM14EN_Pos (8U)
<> 161:2cc1468da177 11080 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11081 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
<> 161:2cc1468da177 11082 #define RCC_APB1ENR_LPTIM1EN_Pos (9U)
<> 161:2cc1468da177 11083 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11084 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
<> 161:2cc1468da177 11085 #define RCC_APB1ENR_RTCEN_Pos (10U)
<> 161:2cc1468da177 11086 #define RCC_APB1ENR_RTCEN_Msk (0x1U << RCC_APB1ENR_RTCEN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11087 #define RCC_APB1ENR_RTCEN RCC_APB1ENR_RTCEN_Msk
<> 161:2cc1468da177 11088 #define RCC_APB1ENR_WWDGEN_Pos (11U)
<> 161:2cc1468da177 11089 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11090 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
<> 161:2cc1468da177 11091 #define RCC_APB1ENR_CAN3EN_Pos (13U)
<> 161:2cc1468da177 11092 #define RCC_APB1ENR_CAN3EN_Msk (0x1U << RCC_APB1ENR_CAN3EN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11093 #define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
<> 161:2cc1468da177 11094 #define RCC_APB1ENR_SPI2EN_Pos (14U)
<> 161:2cc1468da177 11095 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11096 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
<> 161:2cc1468da177 11097 #define RCC_APB1ENR_SPI3EN_Pos (15U)
<> 161:2cc1468da177 11098 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 11099 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
<> 161:2cc1468da177 11100 #define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
<> 161:2cc1468da177 11101 #define RCC_APB1ENR_SPDIFRXEN_Msk (0x1U << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11102 #define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
<> 161:2cc1468da177 11103 #define RCC_APB1ENR_USART2EN_Pos (17U)
<> 161:2cc1468da177 11104 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11105 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
<> 161:2cc1468da177 11106 #define RCC_APB1ENR_USART3EN_Pos (18U)
<> 161:2cc1468da177 11107 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 11108 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
<> 161:2cc1468da177 11109 #define RCC_APB1ENR_UART4EN_Pos (19U)
<> 161:2cc1468da177 11110 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 11111 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
<> 161:2cc1468da177 11112 #define RCC_APB1ENR_UART5EN_Pos (20U)
<> 161:2cc1468da177 11113 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11114 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
<> 161:2cc1468da177 11115 #define RCC_APB1ENR_I2C1EN_Pos (21U)
<> 161:2cc1468da177 11116 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11117 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
<> 161:2cc1468da177 11118 #define RCC_APB1ENR_I2C2EN_Pos (22U)
<> 161:2cc1468da177 11119 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11120 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
<> 161:2cc1468da177 11121 #define RCC_APB1ENR_I2C3EN_Pos (23U)
<> 161:2cc1468da177 11122 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 11123 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
<> 161:2cc1468da177 11124 #define RCC_APB1ENR_I2C4EN_Pos (24U)
<> 161:2cc1468da177 11125 #define RCC_APB1ENR_I2C4EN_Msk (0x1U << RCC_APB1ENR_I2C4EN_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 11126 #define RCC_APB1ENR_I2C4EN RCC_APB1ENR_I2C4EN_Msk
<> 161:2cc1468da177 11127 #define RCC_APB1ENR_CAN1EN_Pos (25U)
<> 161:2cc1468da177 11128 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 11129 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
<> 161:2cc1468da177 11130 #define RCC_APB1ENR_CAN2EN_Pos (26U)
<> 161:2cc1468da177 11131 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11132 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
<> 161:2cc1468da177 11133 #define RCC_APB1ENR_CECEN_Pos (27U)
<> 161:2cc1468da177 11134 #define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 11135 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
<> 161:2cc1468da177 11136 #define RCC_APB1ENR_PWREN_Pos (28U)
<> 161:2cc1468da177 11137 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 11138 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
<> 161:2cc1468da177 11139 #define RCC_APB1ENR_DACEN_Pos (29U)
<> 161:2cc1468da177 11140 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 11141 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
<> 161:2cc1468da177 11142 #define RCC_APB1ENR_UART7EN_Pos (30U)
<> 161:2cc1468da177 11143 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 11144 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
<> 161:2cc1468da177 11145 #define RCC_APB1ENR_UART8EN_Pos (31U)
<> 161:2cc1468da177 11146 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 11147 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
<> 144:ef7eb2e8f9f7 11148
<> 144:ef7eb2e8f9f7 11149 /******************** Bit definition for RCC_APB2ENR register ***************/
<> 161:2cc1468da177 11150 #define RCC_APB2ENR_TIM1EN_Pos (0U)
<> 161:2cc1468da177 11151 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11152 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
<> 161:2cc1468da177 11153 #define RCC_APB2ENR_TIM8EN_Pos (1U)
<> 161:2cc1468da177 11154 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11155 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
<> 161:2cc1468da177 11156 #define RCC_APB2ENR_USART1EN_Pos (4U)
<> 161:2cc1468da177 11157 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11158 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
<> 161:2cc1468da177 11159 #define RCC_APB2ENR_USART6EN_Pos (5U)
<> 161:2cc1468da177 11160 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11161 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
<> 161:2cc1468da177 11162 #define RCC_APB2ENR_SDMMC2EN_Pos (7U)
<> 161:2cc1468da177 11163 #define RCC_APB2ENR_SDMMC2EN_Msk (0x1U << RCC_APB2ENR_SDMMC2EN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11164 #define RCC_APB2ENR_SDMMC2EN RCC_APB2ENR_SDMMC2EN_Msk
<> 161:2cc1468da177 11165 #define RCC_APB2ENR_ADC1EN_Pos (8U)
<> 161:2cc1468da177 11166 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11167 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
<> 161:2cc1468da177 11168 #define RCC_APB2ENR_ADC2EN_Pos (9U)
<> 161:2cc1468da177 11169 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11170 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
<> 161:2cc1468da177 11171 #define RCC_APB2ENR_ADC3EN_Pos (10U)
<> 161:2cc1468da177 11172 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11173 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
<> 161:2cc1468da177 11174 #define RCC_APB2ENR_SDMMC1EN_Pos (11U)
<> 161:2cc1468da177 11175 #define RCC_APB2ENR_SDMMC1EN_Msk (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11176 #define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
<> 161:2cc1468da177 11177 #define RCC_APB2ENR_SPI1EN_Pos (12U)
<> 161:2cc1468da177 11178 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11179 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
<> 161:2cc1468da177 11180 #define RCC_APB2ENR_SPI4EN_Pos (13U)
<> 161:2cc1468da177 11181 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11182 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
<> 161:2cc1468da177 11183 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
<> 161:2cc1468da177 11184 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11185 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
<> 161:2cc1468da177 11186 #define RCC_APB2ENR_TIM9EN_Pos (16U)
<> 161:2cc1468da177 11187 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11188 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
<> 161:2cc1468da177 11189 #define RCC_APB2ENR_TIM10EN_Pos (17U)
<> 161:2cc1468da177 11190 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11191 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
<> 161:2cc1468da177 11192 #define RCC_APB2ENR_TIM11EN_Pos (18U)
<> 161:2cc1468da177 11193 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 11194 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
<> 161:2cc1468da177 11195 #define RCC_APB2ENR_SPI5EN_Pos (20U)
<> 161:2cc1468da177 11196 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11197 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
<> 161:2cc1468da177 11198 #define RCC_APB2ENR_SPI6EN_Pos (21U)
<> 161:2cc1468da177 11199 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11200 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
<> 161:2cc1468da177 11201 #define RCC_APB2ENR_SAI1EN_Pos (22U)
<> 161:2cc1468da177 11202 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11203 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
<> 161:2cc1468da177 11204 #define RCC_APB2ENR_SAI2EN_Pos (23U)
<> 161:2cc1468da177 11205 #define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 11206 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
<> 161:2cc1468da177 11207 #define RCC_APB2ENR_LTDCEN_Pos (26U)
<> 161:2cc1468da177 11208 #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11209 #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
<> 161:2cc1468da177 11210 #define RCC_APB2ENR_DFSDM1EN_Pos (29U)
<> 161:2cc1468da177 11211 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 11212 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
<> 161:2cc1468da177 11213 #define RCC_APB2ENR_MDIOEN_Pos (30U)
<> 161:2cc1468da177 11214 #define RCC_APB2ENR_MDIOEN_Msk (0x1U << RCC_APB2ENR_MDIOEN_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 11215 #define RCC_APB2ENR_MDIOEN RCC_APB2ENR_MDIOEN_Msk
<> 144:ef7eb2e8f9f7 11216
<> 144:ef7eb2e8f9f7 11217 /******************** Bit definition for RCC_AHB1LPENR register *************/
<> 161:2cc1468da177 11218 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
<> 161:2cc1468da177 11219 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11220 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
<> 161:2cc1468da177 11221 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
<> 161:2cc1468da177 11222 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11223 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
<> 161:2cc1468da177 11224 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
<> 161:2cc1468da177 11225 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11226 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
<> 161:2cc1468da177 11227 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
<> 161:2cc1468da177 11228 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 11229 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
<> 161:2cc1468da177 11230 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
<> 161:2cc1468da177 11231 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11232 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
<> 161:2cc1468da177 11233 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
<> 161:2cc1468da177 11234 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11235 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
<> 161:2cc1468da177 11236 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
<> 161:2cc1468da177 11237 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11238 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
<> 161:2cc1468da177 11239 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
<> 161:2cc1468da177 11240 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11241 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
<> 161:2cc1468da177 11242 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
<> 161:2cc1468da177 11243 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11244 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
<> 161:2cc1468da177 11245 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
<> 161:2cc1468da177 11246 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11247 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
<> 161:2cc1468da177 11248 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
<> 161:2cc1468da177 11249 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11250 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
<> 161:2cc1468da177 11251 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
<> 161:2cc1468da177 11252 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11253 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
<> 161:2cc1468da177 11254 #define RCC_AHB1LPENR_AXILPEN_Pos (13U)
<> 161:2cc1468da177 11255 #define RCC_AHB1LPENR_AXILPEN_Msk (0x1U << RCC_AHB1LPENR_AXILPEN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11256 #define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk
<> 161:2cc1468da177 11257 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
<> 161:2cc1468da177 11258 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 11259 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
<> 161:2cc1468da177 11260 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
<> 161:2cc1468da177 11261 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11262 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
<> 161:2cc1468da177 11263 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
<> 161:2cc1468da177 11264 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11265 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
<> 161:2cc1468da177 11266 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
<> 161:2cc1468da177 11267 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 11268 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
<> 161:2cc1468da177 11269 #define RCC_AHB1LPENR_DTCMLPEN_Pos (20U)
<> 161:2cc1468da177 11270 #define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1U << RCC_AHB1LPENR_DTCMLPEN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11271 #define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk
<> 161:2cc1468da177 11272 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
<> 161:2cc1468da177 11273 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11274 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
<> 161:2cc1468da177 11275 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
<> 161:2cc1468da177 11276 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11277 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
<> 161:2cc1468da177 11278 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
<> 161:2cc1468da177 11279 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 11280 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
<> 161:2cc1468da177 11281 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
<> 161:2cc1468da177 11282 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 11283 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
<> 161:2cc1468da177 11284 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
<> 161:2cc1468da177 11285 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11286 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
<> 161:2cc1468da177 11287 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
<> 161:2cc1468da177 11288 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 11289 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
<> 161:2cc1468da177 11290 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
<> 161:2cc1468da177 11291 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 11292 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
<> 161:2cc1468da177 11293 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
<> 161:2cc1468da177 11294 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 11295 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
<> 161:2cc1468da177 11296 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
<> 161:2cc1468da177 11297 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 11298 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
<> 144:ef7eb2e8f9f7 11299
<> 144:ef7eb2e8f9f7 11300 /******************** Bit definition for RCC_AHB2LPENR register *************/
<> 161:2cc1468da177 11301 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
<> 161:2cc1468da177 11302 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11303 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
<> 161:2cc1468da177 11304 #define RCC_AHB2LPENR_JPEGLPEN_Pos (1U)
<> 161:2cc1468da177 11305 #define RCC_AHB2LPENR_JPEGLPEN_Msk (0x1U << RCC_AHB2LPENR_JPEGLPEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11306 #define RCC_AHB2LPENR_JPEGLPEN RCC_AHB2LPENR_JPEGLPEN_Msk
<> 161:2cc1468da177 11307 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
<> 161:2cc1468da177 11308 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11309 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
<> 161:2cc1468da177 11310 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
<> 161:2cc1468da177 11311 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11312 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
<> 144:ef7eb2e8f9f7 11313
<> 144:ef7eb2e8f9f7 11314 /******************** Bit definition for RCC_AHB3LPENR register *************/
<> 161:2cc1468da177 11315 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
<> 161:2cc1468da177 11316 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11317 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
<> 161:2cc1468da177 11318 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
<> 161:2cc1468da177 11319 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11320 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
<> 144:ef7eb2e8f9f7 11321 /******************** Bit definition for RCC_APB1LPENR register *************/
<> 161:2cc1468da177 11322 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
<> 161:2cc1468da177 11323 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11324 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
<> 161:2cc1468da177 11325 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
<> 161:2cc1468da177 11326 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11327 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
<> 161:2cc1468da177 11328 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
<> 161:2cc1468da177 11329 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11330 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
<> 161:2cc1468da177 11331 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
<> 161:2cc1468da177 11332 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 11333 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
<> 161:2cc1468da177 11334 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
<> 161:2cc1468da177 11335 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11336 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
<> 161:2cc1468da177 11337 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
<> 161:2cc1468da177 11338 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11339 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
<> 161:2cc1468da177 11340 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
<> 161:2cc1468da177 11341 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11342 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
<> 161:2cc1468da177 11343 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
<> 161:2cc1468da177 11344 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11345 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
<> 161:2cc1468da177 11346 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
<> 161:2cc1468da177 11347 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11348 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
<> 161:2cc1468da177 11349 #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
<> 161:2cc1468da177 11350 #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11351 #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
<> 161:2cc1468da177 11352 #define RCC_APB1LPENR_RTCLPEN_Pos (10U)
<> 161:2cc1468da177 11353 #define RCC_APB1LPENR_RTCLPEN_Msk (0x1U << RCC_APB1LPENR_RTCLPEN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11354 #define RCC_APB1LPENR_RTCLPEN RCC_APB1LPENR_RTCLPEN_Msk
<> 161:2cc1468da177 11355 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
<> 161:2cc1468da177 11356 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11357 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
<> 161:2cc1468da177 11358 #define RCC_APB1LPENR_CAN3LPEN_Pos (13U)
<> 161:2cc1468da177 11359 #define RCC_APB1LPENR_CAN3LPEN_Msk (0x1U << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11360 #define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
<> 161:2cc1468da177 11361 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
<> 161:2cc1468da177 11362 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11363 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
<> 161:2cc1468da177 11364 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
<> 161:2cc1468da177 11365 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 11366 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
<> 161:2cc1468da177 11367 #define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
<> 161:2cc1468da177 11368 #define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1U << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11369 #define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
<> 161:2cc1468da177 11370 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
<> 161:2cc1468da177 11371 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11372 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
<> 161:2cc1468da177 11373 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
<> 161:2cc1468da177 11374 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 11375 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
<> 161:2cc1468da177 11376 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
<> 161:2cc1468da177 11377 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 11378 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
<> 161:2cc1468da177 11379 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
<> 161:2cc1468da177 11380 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11381 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
<> 161:2cc1468da177 11382 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
<> 161:2cc1468da177 11383 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11384 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
<> 161:2cc1468da177 11385 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
<> 161:2cc1468da177 11386 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11387 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
<> 161:2cc1468da177 11388 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
<> 161:2cc1468da177 11389 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 11390 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
<> 161:2cc1468da177 11391 #define RCC_APB1LPENR_I2C4LPEN_Pos (24U)
<> 161:2cc1468da177 11392 #define RCC_APB1LPENR_I2C4LPEN_Msk (0x1U << RCC_APB1LPENR_I2C4LPEN_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 11393 #define RCC_APB1LPENR_I2C4LPEN RCC_APB1LPENR_I2C4LPEN_Msk
<> 161:2cc1468da177 11394 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
<> 161:2cc1468da177 11395 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 11396 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
<> 161:2cc1468da177 11397 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
<> 161:2cc1468da177 11398 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11399 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
<> 161:2cc1468da177 11400 #define RCC_APB1LPENR_CECLPEN_Pos (27U)
<> 161:2cc1468da177 11401 #define RCC_APB1LPENR_CECLPEN_Msk (0x1U << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 11402 #define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
<> 161:2cc1468da177 11403 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
<> 161:2cc1468da177 11404 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 11405 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
<> 161:2cc1468da177 11406 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
<> 161:2cc1468da177 11407 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 11408 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
<> 161:2cc1468da177 11409 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
<> 161:2cc1468da177 11410 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 11411 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
<> 161:2cc1468da177 11412 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
<> 161:2cc1468da177 11413 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 11414 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
<> 144:ef7eb2e8f9f7 11415
<> 144:ef7eb2e8f9f7 11416 /******************** Bit definition for RCC_APB2LPENR register *************/
<> 161:2cc1468da177 11417 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
<> 161:2cc1468da177 11418 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11419 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
<> 161:2cc1468da177 11420 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
<> 161:2cc1468da177 11421 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11422 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
<> 161:2cc1468da177 11423 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
<> 161:2cc1468da177 11424 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11425 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
<> 161:2cc1468da177 11426 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
<> 161:2cc1468da177 11427 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11428 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
<> 161:2cc1468da177 11429 #define RCC_APB2LPENR_SDMMC2LPEN_Pos (7U)
<> 161:2cc1468da177 11430 #define RCC_APB2LPENR_SDMMC2LPEN_Msk (0x1U << RCC_APB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11431 #define RCC_APB2LPENR_SDMMC2LPEN RCC_APB2LPENR_SDMMC2LPEN_Msk
<> 161:2cc1468da177 11432 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
<> 161:2cc1468da177 11433 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11434 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
<> 161:2cc1468da177 11435 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
<> 161:2cc1468da177 11436 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11437 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
<> 161:2cc1468da177 11438 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
<> 161:2cc1468da177 11439 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11440 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
<> 161:2cc1468da177 11441 #define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U)
<> 161:2cc1468da177 11442 #define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1U << RCC_APB2LPENR_SDMMC1LPEN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11443 #define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk
<> 161:2cc1468da177 11444 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
<> 161:2cc1468da177 11445 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11446 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
<> 161:2cc1468da177 11447 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
<> 161:2cc1468da177 11448 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11449 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
<> 161:2cc1468da177 11450 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
<> 161:2cc1468da177 11451 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11452 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
<> 161:2cc1468da177 11453 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
<> 161:2cc1468da177 11454 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11455 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
<> 161:2cc1468da177 11456 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
<> 161:2cc1468da177 11457 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11458 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
<> 161:2cc1468da177 11459 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
<> 161:2cc1468da177 11460 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 11461 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
<> 161:2cc1468da177 11462 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
<> 161:2cc1468da177 11463 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11464 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
<> 161:2cc1468da177 11465 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
<> 161:2cc1468da177 11466 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11467 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
<> 161:2cc1468da177 11468 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
<> 161:2cc1468da177 11469 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11470 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
<> 161:2cc1468da177 11471 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
<> 161:2cc1468da177 11472 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1U << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 11473 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
<> 161:2cc1468da177 11474 #define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
<> 161:2cc1468da177 11475 #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11476 #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
<> 161:2cc1468da177 11477 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (29U)
<> 161:2cc1468da177 11478 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 11479 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
<> 161:2cc1468da177 11480 #define RCC_APB2LPENR_MDIOLPEN_Pos (30U)
<> 161:2cc1468da177 11481 #define RCC_APB2LPENR_MDIOLPEN_Msk (0x1U << RCC_APB2LPENR_MDIOLPEN_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 11482 #define RCC_APB2LPENR_MDIOLPEN RCC_APB2LPENR_MDIOLPEN_Msk
<> 144:ef7eb2e8f9f7 11483
<> 144:ef7eb2e8f9f7 11484 /******************** Bit definition for RCC_BDCR register ******************/
<> 161:2cc1468da177 11485 #define RCC_BDCR_LSEON_Pos (0U)
<> 161:2cc1468da177 11486 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11487 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
<> 161:2cc1468da177 11488 #define RCC_BDCR_LSERDY_Pos (1U)
<> 161:2cc1468da177 11489 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11490 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
<> 161:2cc1468da177 11491 #define RCC_BDCR_LSEBYP_Pos (2U)
<> 161:2cc1468da177 11492 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11493 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
<> 161:2cc1468da177 11494 #define RCC_BDCR_LSEDRV_Pos (3U)
<> 161:2cc1468da177 11495 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
<> 161:2cc1468da177 11496 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
<> 161:2cc1468da177 11497 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 11498 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11499 #define RCC_BDCR_RTCSEL_Pos (8U)
<> 161:2cc1468da177 11500 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 11501 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
<> 161:2cc1468da177 11502 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11503 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11504 #define RCC_BDCR_RTCEN_Pos (15U)
<> 161:2cc1468da177 11505 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 11506 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
<> 161:2cc1468da177 11507 #define RCC_BDCR_BDRST_Pos (16U)
<> 161:2cc1468da177 11508 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11509 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
<> 144:ef7eb2e8f9f7 11510
<> 144:ef7eb2e8f9f7 11511 /******************** Bit definition for RCC_CSR register *******************/
<> 161:2cc1468da177 11512 #define RCC_CSR_LSION_Pos (0U)
<> 161:2cc1468da177 11513 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11514 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
<> 161:2cc1468da177 11515 #define RCC_CSR_LSIRDY_Pos (1U)
<> 161:2cc1468da177 11516 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11517 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
<> 161:2cc1468da177 11518 #define RCC_CSR_RMVF_Pos (24U)
<> 161:2cc1468da177 11519 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 11520 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
<> 161:2cc1468da177 11521 #define RCC_CSR_BORRSTF_Pos (25U)
<> 161:2cc1468da177 11522 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 11523 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
<> 161:2cc1468da177 11524 #define RCC_CSR_PINRSTF_Pos (26U)
<> 161:2cc1468da177 11525 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11526 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
<> 161:2cc1468da177 11527 #define RCC_CSR_PORRSTF_Pos (27U)
<> 161:2cc1468da177 11528 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 11529 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
<> 161:2cc1468da177 11530 #define RCC_CSR_SFTRSTF_Pos (28U)
<> 161:2cc1468da177 11531 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 11532 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
<> 161:2cc1468da177 11533 #define RCC_CSR_IWDGRSTF_Pos (29U)
<> 161:2cc1468da177 11534 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 11535 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
<> 161:2cc1468da177 11536 #define RCC_CSR_WWDGRSTF_Pos (30U)
<> 161:2cc1468da177 11537 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 11538 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
<> 161:2cc1468da177 11539 #define RCC_CSR_LPWRRSTF_Pos (31U)
<> 161:2cc1468da177 11540 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 11541 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
<> 144:ef7eb2e8f9f7 11542
<> 144:ef7eb2e8f9f7 11543 /******************** Bit definition for RCC_SSCGR register *****************/
<> 161:2cc1468da177 11544 #define RCC_SSCGR_MODPER_Pos (0U)
<> 161:2cc1468da177 11545 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
<> 161:2cc1468da177 11546 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
<> 161:2cc1468da177 11547 #define RCC_SSCGR_INCSTEP_Pos (13U)
<> 161:2cc1468da177 11548 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
<> 161:2cc1468da177 11549 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
<> 161:2cc1468da177 11550 #define RCC_SSCGR_SPREADSEL_Pos (30U)
<> 161:2cc1468da177 11551 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 11552 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
<> 161:2cc1468da177 11553 #define RCC_SSCGR_SSCGEN_Pos (31U)
<> 161:2cc1468da177 11554 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 11555 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
<> 144:ef7eb2e8f9f7 11556
<> 144:ef7eb2e8f9f7 11557 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
<> 161:2cc1468da177 11558 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
<> 161:2cc1468da177 11559 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
<> 161:2cc1468da177 11560 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
<> 161:2cc1468da177 11561 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11562 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11563 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11564 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11565 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11566 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11567 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11568 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11569 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11570 #define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
<> 161:2cc1468da177 11571 #define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 11572 #define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
<> 161:2cc1468da177 11573 #define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11574 #define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11575 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
<> 161:2cc1468da177 11576 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 11577 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
<> 161:2cc1468da177 11578 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 11579 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 11580 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11581 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 11582 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
<> 161:2cc1468da177 11583 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
<> 161:2cc1468da177 11584 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
<> 161:2cc1468da177 11585 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 11586 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 11587 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 11588
<> 144:ef7eb2e8f9f7 11589 /******************** Bit definition for RCC_PLLSAICFGR register ************/
<> 161:2cc1468da177 11590 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
<> 161:2cc1468da177 11591 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
<> 161:2cc1468da177 11592 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
<> 161:2cc1468da177 11593 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11594 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11595 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11596 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11597 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11598 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11599 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11600 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11601 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11602 #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
<> 161:2cc1468da177 11603 #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 11604 #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
<> 161:2cc1468da177 11605 #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11606 #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11607 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
<> 161:2cc1468da177 11608 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 11609 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
<> 161:2cc1468da177 11610 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 11611 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 11612 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11613 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 11614 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
<> 161:2cc1468da177 11615 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
<> 161:2cc1468da177 11616 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
<> 161:2cc1468da177 11617 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 11618 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 11619 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 11620
<> 144:ef7eb2e8f9f7 11621 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
<> 161:2cc1468da177 11622 #define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U)
<> 161:2cc1468da177 11623 #define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
<> 161:2cc1468da177 11624 #define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk
<> 161:2cc1468da177 11625 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11626 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11627 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11628 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 11629 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11630
<> 161:2cc1468da177 11631 #define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U)
<> 161:2cc1468da177 11632 #define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
<> 161:2cc1468da177 11633 #define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk
<> 161:2cc1468da177 11634 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11635 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11636 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11637 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11638 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11639
<> 161:2cc1468da177 11640 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U)
<> 161:2cc1468da177 11641 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 11642 #define RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR_Msk
<> 161:2cc1468da177 11643 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11644 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11645
<> 161:2cc1468da177 11646 /*
<> 161:2cc1468da177 11647 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
<> 161:2cc1468da177 11648 */
<> 161:2cc1468da177 11649 #define RCC_SAI1SEL_PLLSRC_SUPPORT
<> 161:2cc1468da177 11650 #define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
<> 161:2cc1468da177 11651 #define RCC_DCKCFGR1_SAI1SEL_Msk (0x3U << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 11652 #define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk
<> 161:2cc1468da177 11653 #define RCC_DCKCFGR1_SAI1SEL_0 (0x1U << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11654 #define RCC_DCKCFGR1_SAI1SEL_1 (0x2U << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11655
<> 161:2cc1468da177 11656 /*
<> 161:2cc1468da177 11657 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
<> 161:2cc1468da177 11658 */
<> 161:2cc1468da177 11659 #define RCC_SAI2SEL_PLLSRC_SUPPORT
<> 161:2cc1468da177 11660 #define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
<> 161:2cc1468da177 11661 #define RCC_DCKCFGR1_SAI2SEL_Msk (0x3U << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00C00000 */
<> 161:2cc1468da177 11662 #define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk
<> 161:2cc1468da177 11663 #define RCC_DCKCFGR1_SAI2SEL_0 (0x1U << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11664 #define RCC_DCKCFGR1_SAI2SEL_1 (0x2U << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 11665
<> 161:2cc1468da177 11666 #define RCC_DCKCFGR1_TIMPRE_Pos (24U)
<> 161:2cc1468da177 11667 #define RCC_DCKCFGR1_TIMPRE_Msk (0x1U << RCC_DCKCFGR1_TIMPRE_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 11668 #define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk
<> 161:2cc1468da177 11669 #define RCC_DCKCFGR1_DFSDM1SEL_Pos (25U)
<> 161:2cc1468da177 11670 #define RCC_DCKCFGR1_DFSDM1SEL_Msk (0x1U << RCC_DCKCFGR1_DFSDM1SEL_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 11671 #define RCC_DCKCFGR1_DFSDM1SEL RCC_DCKCFGR1_DFSDM1SEL_Msk
<> 161:2cc1468da177 11672 #define RCC_DCKCFGR1_ADFSDM1SEL_Pos (26U)
<> 161:2cc1468da177 11673 #define RCC_DCKCFGR1_ADFSDM1SEL_Msk (0x1U << RCC_DCKCFGR1_ADFSDM1SEL_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11674 #define RCC_DCKCFGR1_ADFSDM1SEL RCC_DCKCFGR1_ADFSDM1SEL_Msk
<> 144:ef7eb2e8f9f7 11675
<> 144:ef7eb2e8f9f7 11676 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
<> 161:2cc1468da177 11677 #define RCC_DCKCFGR2_USART1SEL_Pos (0U)
<> 161:2cc1468da177 11678 #define RCC_DCKCFGR2_USART1SEL_Msk (0x3U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 11679 #define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk
<> 161:2cc1468da177 11680 #define RCC_DCKCFGR2_USART1SEL_0 (0x1U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11681 #define RCC_DCKCFGR2_USART1SEL_1 (0x2U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11682 #define RCC_DCKCFGR2_USART2SEL_Pos (2U)
<> 161:2cc1468da177 11683 #define RCC_DCKCFGR2_USART2SEL_Msk (0x3U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 11684 #define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk
<> 161:2cc1468da177 11685 #define RCC_DCKCFGR2_USART2SEL_0 (0x1U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11686 #define RCC_DCKCFGR2_USART2SEL_1 (0x2U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 11687 #define RCC_DCKCFGR2_USART3SEL_Pos (4U)
<> 161:2cc1468da177 11688 #define RCC_DCKCFGR2_USART3SEL_Msk (0x3U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 11689 #define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk
<> 161:2cc1468da177 11690 #define RCC_DCKCFGR2_USART3SEL_0 (0x1U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11691 #define RCC_DCKCFGR2_USART3SEL_1 (0x2U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11692 #define RCC_DCKCFGR2_UART4SEL_Pos (6U)
<> 161:2cc1468da177 11693 #define RCC_DCKCFGR2_UART4SEL_Msk (0x3U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 11694 #define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk
<> 161:2cc1468da177 11695 #define RCC_DCKCFGR2_UART4SEL_0 (0x1U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11696 #define RCC_DCKCFGR2_UART4SEL_1 (0x2U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11697 #define RCC_DCKCFGR2_UART5SEL_Pos (8U)
<> 161:2cc1468da177 11698 #define RCC_DCKCFGR2_UART5SEL_Msk (0x3U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 11699 #define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk
<> 161:2cc1468da177 11700 #define RCC_DCKCFGR2_UART5SEL_0 (0x1U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11701 #define RCC_DCKCFGR2_UART5SEL_1 (0x2U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11702 #define RCC_DCKCFGR2_USART6SEL_Pos (10U)
<> 161:2cc1468da177 11703 #define RCC_DCKCFGR2_USART6SEL_Msk (0x3U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 11704 #define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk
<> 161:2cc1468da177 11705 #define RCC_DCKCFGR2_USART6SEL_0 (0x1U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11706 #define RCC_DCKCFGR2_USART6SEL_1 (0x2U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11707 #define RCC_DCKCFGR2_UART7SEL_Pos (12U)
<> 161:2cc1468da177 11708 #define RCC_DCKCFGR2_UART7SEL_Msk (0x3U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00003000 */
<> 161:2cc1468da177 11709 #define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk
<> 161:2cc1468da177 11710 #define RCC_DCKCFGR2_UART7SEL_0 (0x1U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11711 #define RCC_DCKCFGR2_UART7SEL_1 (0x2U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11712 #define RCC_DCKCFGR2_UART8SEL_Pos (14U)
<> 161:2cc1468da177 11713 #define RCC_DCKCFGR2_UART8SEL_Msk (0x3U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 11714 #define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk
<> 161:2cc1468da177 11715 #define RCC_DCKCFGR2_UART8SEL_0 (0x1U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11716 #define RCC_DCKCFGR2_UART8SEL_1 (0x2U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 11717 #define RCC_DCKCFGR2_I2C1SEL_Pos (16U)
<> 161:2cc1468da177 11718 #define RCC_DCKCFGR2_I2C1SEL_Msk (0x3U << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 11719 #define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk
<> 161:2cc1468da177 11720 #define RCC_DCKCFGR2_I2C1SEL_0 (0x1U << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11721 #define RCC_DCKCFGR2_I2C1SEL_1 (0x2U << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11722 #define RCC_DCKCFGR2_I2C2SEL_Pos (18U)
<> 161:2cc1468da177 11723 #define RCC_DCKCFGR2_I2C2SEL_Msk (0x3U << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x000C0000 */
<> 161:2cc1468da177 11724 #define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk
<> 161:2cc1468da177 11725 #define RCC_DCKCFGR2_I2C2SEL_0 (0x1U << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 11726 #define RCC_DCKCFGR2_I2C2SEL_1 (0x2U << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 11727 #define RCC_DCKCFGR2_I2C3SEL_Pos (20U)
<> 161:2cc1468da177 11728 #define RCC_DCKCFGR2_I2C3SEL_Msk (0x3U << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 11729 #define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk
<> 161:2cc1468da177 11730 #define RCC_DCKCFGR2_I2C3SEL_0 (0x1U << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11731 #define RCC_DCKCFGR2_I2C3SEL_1 (0x2U << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11732 #define RCC_DCKCFGR2_I2C4SEL_Pos (22U)
<> 161:2cc1468da177 11733 #define RCC_DCKCFGR2_I2C4SEL_Msk (0x3U << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00C00000 */
<> 161:2cc1468da177 11734 #define RCC_DCKCFGR2_I2C4SEL RCC_DCKCFGR2_I2C4SEL_Msk
<> 161:2cc1468da177 11735 #define RCC_DCKCFGR2_I2C4SEL_0 (0x1U << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11736 #define RCC_DCKCFGR2_I2C4SEL_1 (0x2U << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 11737 #define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U)
<> 161:2cc1468da177 11738 #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x03000000 */
<> 161:2cc1468da177 11739 #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
<> 161:2cc1468da177 11740 #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 11741 #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 11742 #define RCC_DCKCFGR2_CECSEL_Pos (26U)
<> 161:2cc1468da177 11743 #define RCC_DCKCFGR2_CECSEL_Msk (0x1U << RCC_DCKCFGR2_CECSEL_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 11744 #define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
<> 161:2cc1468da177 11745 #define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
<> 161:2cc1468da177 11746 #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 11747 #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
<> 161:2cc1468da177 11748 #define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U)
<> 161:2cc1468da177 11749 #define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1U << RCC_DCKCFGR2_SDMMC1SEL_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 11750 #define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk
<> 161:2cc1468da177 11751 #define RCC_DCKCFGR2_SDMMC2SEL_Pos (29U)
<> 161:2cc1468da177 11752 #define RCC_DCKCFGR2_SDMMC2SEL_Msk (0x1U << RCC_DCKCFGR2_SDMMC2SEL_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 11753 #define RCC_DCKCFGR2_SDMMC2SEL RCC_DCKCFGR2_SDMMC2SEL_Msk
<> 144:ef7eb2e8f9f7 11754
<> 144:ef7eb2e8f9f7 11755 /******************************************************************************/
<> 144:ef7eb2e8f9f7 11756 /* */
<> 144:ef7eb2e8f9f7 11757 /* RNG */
<> 144:ef7eb2e8f9f7 11758 /* */
<> 144:ef7eb2e8f9f7 11759 /******************************************************************************/
<> 144:ef7eb2e8f9f7 11760 /******************** Bits definition for RNG_CR register *******************/
<> 161:2cc1468da177 11761 #define RNG_CR_RNGEN_Pos (2U)
<> 161:2cc1468da177 11762 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11763 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
<> 161:2cc1468da177 11764 #define RNG_CR_IE_Pos (3U)
<> 161:2cc1468da177 11765 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 11766 #define RNG_CR_IE RNG_CR_IE_Msk
<> 144:ef7eb2e8f9f7 11767
<> 144:ef7eb2e8f9f7 11768 /******************** Bits definition for RNG_SR register *******************/
<> 161:2cc1468da177 11769 #define RNG_SR_DRDY_Pos (0U)
<> 161:2cc1468da177 11770 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11771 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
<> 161:2cc1468da177 11772 #define RNG_SR_CECS_Pos (1U)
<> 161:2cc1468da177 11773 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11774 #define RNG_SR_CECS RNG_SR_CECS_Msk
<> 161:2cc1468da177 11775 #define RNG_SR_SECS_Pos (2U)
<> 161:2cc1468da177 11776 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11777 #define RNG_SR_SECS RNG_SR_SECS_Msk
<> 161:2cc1468da177 11778 #define RNG_SR_CEIS_Pos (5U)
<> 161:2cc1468da177 11779 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11780 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
<> 161:2cc1468da177 11781 #define RNG_SR_SEIS_Pos (6U)
<> 161:2cc1468da177 11782 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11783 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
<> 144:ef7eb2e8f9f7 11784
<> 144:ef7eb2e8f9f7 11785 /******************************************************************************/
<> 144:ef7eb2e8f9f7 11786 /* */
<> 144:ef7eb2e8f9f7 11787 /* Real-Time Clock (RTC) */
<> 144:ef7eb2e8f9f7 11788 /* */
<> 144:ef7eb2e8f9f7 11789 /******************************************************************************/
<> 144:ef7eb2e8f9f7 11790 /******************** Bits definition for RTC_TR register *******************/
<> 161:2cc1468da177 11791 #define RTC_TR_PM_Pos (22U)
<> 161:2cc1468da177 11792 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11793 #define RTC_TR_PM RTC_TR_PM_Msk
<> 161:2cc1468da177 11794 #define RTC_TR_HT_Pos (20U)
<> 161:2cc1468da177 11795 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 11796 #define RTC_TR_HT RTC_TR_HT_Msk
<> 161:2cc1468da177 11797 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11798 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11799 #define RTC_TR_HU_Pos (16U)
<> 161:2cc1468da177 11800 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 11801 #define RTC_TR_HU RTC_TR_HU_Msk
<> 161:2cc1468da177 11802 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11803 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11804 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 11805 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 11806 #define RTC_TR_MNT_Pos (12U)
<> 161:2cc1468da177 11807 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
<> 161:2cc1468da177 11808 #define RTC_TR_MNT RTC_TR_MNT_Msk
<> 161:2cc1468da177 11809 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11810 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11811 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11812 #define RTC_TR_MNU_Pos (8U)
<> 161:2cc1468da177 11813 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 11814 #define RTC_TR_MNU RTC_TR_MNU_Msk
<> 161:2cc1468da177 11815 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11816 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11817 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11818 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11819 #define RTC_TR_ST_Pos (4U)
<> 161:2cc1468da177 11820 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
<> 161:2cc1468da177 11821 #define RTC_TR_ST RTC_TR_ST_Msk
<> 161:2cc1468da177 11822 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11823 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11824 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11825 #define RTC_TR_SU_Pos (0U)
<> 161:2cc1468da177 11826 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 11827 #define RTC_TR_SU RTC_TR_SU_Msk
<> 161:2cc1468da177 11828 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11829 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11830 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11831 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 11832
<> 144:ef7eb2e8f9f7 11833 /******************** Bits definition for RTC_DR register *******************/
<> 161:2cc1468da177 11834 #define RTC_DR_YT_Pos (20U)
<> 161:2cc1468da177 11835 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 11836 #define RTC_DR_YT RTC_DR_YT_Msk
<> 161:2cc1468da177 11837 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11838 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11839 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11840 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 11841 #define RTC_DR_YU_Pos (16U)
<> 161:2cc1468da177 11842 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 11843 #define RTC_DR_YU RTC_DR_YU_Msk
<> 161:2cc1468da177 11844 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11845 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11846 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 11847 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 11848 #define RTC_DR_WDU_Pos (13U)
<> 161:2cc1468da177 11849 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
<> 161:2cc1468da177 11850 #define RTC_DR_WDU RTC_DR_WDU_Msk
<> 161:2cc1468da177 11851 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11852 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11853 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 11854 #define RTC_DR_MT_Pos (12U)
<> 161:2cc1468da177 11855 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11856 #define RTC_DR_MT RTC_DR_MT_Msk
<> 161:2cc1468da177 11857 #define RTC_DR_MU_Pos (8U)
<> 161:2cc1468da177 11858 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 11859 #define RTC_DR_MU RTC_DR_MU_Msk
<> 161:2cc1468da177 11860 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11861 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11862 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11863 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11864 #define RTC_DR_DT_Pos (4U)
<> 161:2cc1468da177 11865 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 11866 #define RTC_DR_DT RTC_DR_DT_Msk
<> 161:2cc1468da177 11867 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11868 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11869 #define RTC_DR_DU_Pos (0U)
<> 161:2cc1468da177 11870 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 11871 #define RTC_DR_DU RTC_DR_DU_Msk
<> 161:2cc1468da177 11872 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11873 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11874 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11875 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 11876
<> 144:ef7eb2e8f9f7 11877 /******************** Bits definition for RTC_CR register *******************/
<> 161:2cc1468da177 11878 #define RTC_CR_ITSE_Pos (24U)
<> 161:2cc1468da177 11879 #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 11880 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
<> 161:2cc1468da177 11881 #define RTC_CR_COE_Pos (23U)
<> 161:2cc1468da177 11882 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 11883 #define RTC_CR_COE RTC_CR_COE_Msk
<> 161:2cc1468da177 11884 #define RTC_CR_OSEL_Pos (21U)
<> 161:2cc1468da177 11885 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
<> 161:2cc1468da177 11886 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
<> 161:2cc1468da177 11887 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 11888 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 11889 #define RTC_CR_POL_Pos (20U)
<> 161:2cc1468da177 11890 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 11891 #define RTC_CR_POL RTC_CR_POL_Msk
<> 161:2cc1468da177 11892 #define RTC_CR_COSEL_Pos (19U)
<> 161:2cc1468da177 11893 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 11894 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
<> 161:2cc1468da177 11895 #define RTC_CR_BKP_Pos (18U)
<> 161:2cc1468da177 11896 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 11897 #define RTC_CR_BKP RTC_CR_BKP_Msk
<> 161:2cc1468da177 11898 #define RTC_CR_SUB1H_Pos (17U)
<> 161:2cc1468da177 11899 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11900 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
<> 161:2cc1468da177 11901 #define RTC_CR_ADD1H_Pos (16U)
<> 161:2cc1468da177 11902 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11903 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
<> 161:2cc1468da177 11904 #define RTC_CR_TSIE_Pos (15U)
<> 161:2cc1468da177 11905 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 11906 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
<> 161:2cc1468da177 11907 #define RTC_CR_WUTIE_Pos (14U)
<> 161:2cc1468da177 11908 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11909 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
<> 161:2cc1468da177 11910 #define RTC_CR_ALRBIE_Pos (13U)
<> 161:2cc1468da177 11911 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11912 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
<> 161:2cc1468da177 11913 #define RTC_CR_ALRAIE_Pos (12U)
<> 161:2cc1468da177 11914 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11915 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
<> 161:2cc1468da177 11916 #define RTC_CR_TSE_Pos (11U)
<> 161:2cc1468da177 11917 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11918 #define RTC_CR_TSE RTC_CR_TSE_Msk
<> 161:2cc1468da177 11919 #define RTC_CR_WUTE_Pos (10U)
<> 161:2cc1468da177 11920 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11921 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
<> 161:2cc1468da177 11922 #define RTC_CR_ALRBE_Pos (9U)
<> 161:2cc1468da177 11923 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11924 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
<> 161:2cc1468da177 11925 #define RTC_CR_ALRAE_Pos (8U)
<> 161:2cc1468da177 11926 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11927 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
<> 161:2cc1468da177 11928 #define RTC_CR_FMT_Pos (6U)
<> 161:2cc1468da177 11929 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11930 #define RTC_CR_FMT RTC_CR_FMT_Msk
<> 161:2cc1468da177 11931 #define RTC_CR_BYPSHAD_Pos (5U)
<> 161:2cc1468da177 11932 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11933 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
<> 161:2cc1468da177 11934 #define RTC_CR_REFCKON_Pos (4U)
<> 161:2cc1468da177 11935 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11936 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
<> 161:2cc1468da177 11937 #define RTC_CR_TSEDGE_Pos (3U)
<> 161:2cc1468da177 11938 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 11939 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
<> 161:2cc1468da177 11940 #define RTC_CR_WUCKSEL_Pos (0U)
<> 161:2cc1468da177 11941 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 11942 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
<> 161:2cc1468da177 11943 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 11944 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 11945 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 11946
<> 157:ff67d9f36b67 11947 /* Legacy define */
<> 157:ff67d9f36b67 11948 #define RTC_CR_BCK RTC_CR_BKP
<> 157:ff67d9f36b67 11949
<> 144:ef7eb2e8f9f7 11950 /******************** Bits definition for RTC_ISR register ******************/
<> 161:2cc1468da177 11951 #define RTC_ISR_ITSF_Pos (17U)
<> 161:2cc1468da177 11952 #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 11953 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
<> 161:2cc1468da177 11954 #define RTC_ISR_RECALPF_Pos (16U)
<> 161:2cc1468da177 11955 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 11956 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
<> 161:2cc1468da177 11957 #define RTC_ISR_TAMP3F_Pos (15U)
<> 161:2cc1468da177 11958 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 11959 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
<> 161:2cc1468da177 11960 #define RTC_ISR_TAMP2F_Pos (14U)
<> 161:2cc1468da177 11961 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 11962 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
<> 161:2cc1468da177 11963 #define RTC_ISR_TAMP1F_Pos (13U)
<> 161:2cc1468da177 11964 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 11965 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
<> 161:2cc1468da177 11966 #define RTC_ISR_TSOVF_Pos (12U)
<> 161:2cc1468da177 11967 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 11968 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
<> 161:2cc1468da177 11969 #define RTC_ISR_TSF_Pos (11U)
<> 161:2cc1468da177 11970 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 11971 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
<> 161:2cc1468da177 11972 #define RTC_ISR_WUTF_Pos (10U)
<> 161:2cc1468da177 11973 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 11974 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
<> 161:2cc1468da177 11975 #define RTC_ISR_ALRBF_Pos (9U)
<> 161:2cc1468da177 11976 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 11977 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
<> 161:2cc1468da177 11978 #define RTC_ISR_ALRAF_Pos (8U)
<> 161:2cc1468da177 11979 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 11980 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
<> 161:2cc1468da177 11981 #define RTC_ISR_INIT_Pos (7U)
<> 161:2cc1468da177 11982 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 11983 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
<> 161:2cc1468da177 11984 #define RTC_ISR_INITF_Pos (6U)
<> 161:2cc1468da177 11985 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 11986 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
<> 161:2cc1468da177 11987 #define RTC_ISR_RSF_Pos (5U)
<> 161:2cc1468da177 11988 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 11989 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
<> 161:2cc1468da177 11990 #define RTC_ISR_INITS_Pos (4U)
<> 161:2cc1468da177 11991 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 11992 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
<> 161:2cc1468da177 11993 #define RTC_ISR_SHPF_Pos (3U)
<> 161:2cc1468da177 11994 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 11995 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
<> 161:2cc1468da177 11996 #define RTC_ISR_WUTWF_Pos (2U)
<> 161:2cc1468da177 11997 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 11998 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
<> 161:2cc1468da177 11999 #define RTC_ISR_ALRBWF_Pos (1U)
<> 161:2cc1468da177 12000 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12001 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
<> 161:2cc1468da177 12002 #define RTC_ISR_ALRAWF_Pos (0U)
<> 161:2cc1468da177 12003 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12004 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
<> 144:ef7eb2e8f9f7 12005
<> 144:ef7eb2e8f9f7 12006 /******************** Bits definition for RTC_PRER register *****************/
<> 161:2cc1468da177 12007 #define RTC_PRER_PREDIV_A_Pos (16U)
<> 161:2cc1468da177 12008 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
<> 161:2cc1468da177 12009 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
<> 161:2cc1468da177 12010 #define RTC_PRER_PREDIV_S_Pos (0U)
<> 161:2cc1468da177 12011 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
<> 161:2cc1468da177 12012 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
<> 144:ef7eb2e8f9f7 12013
<> 144:ef7eb2e8f9f7 12014 /******************** Bits definition for RTC_WUTR register *****************/
<> 161:2cc1468da177 12015 #define RTC_WUTR_WUT_Pos (0U)
<> 161:2cc1468da177 12016 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 12017 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
<> 144:ef7eb2e8f9f7 12018
<> 144:ef7eb2e8f9f7 12019 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 161:2cc1468da177 12020 #define RTC_ALRMAR_MSK4_Pos (31U)
<> 161:2cc1468da177 12021 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 12022 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
<> 161:2cc1468da177 12023 #define RTC_ALRMAR_WDSEL_Pos (30U)
<> 161:2cc1468da177 12024 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 12025 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
<> 161:2cc1468da177 12026 #define RTC_ALRMAR_DT_Pos (28U)
<> 161:2cc1468da177 12027 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 12028 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
<> 161:2cc1468da177 12029 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 12030 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 12031 #define RTC_ALRMAR_DU_Pos (24U)
<> 161:2cc1468da177 12032 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 12033 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
<> 161:2cc1468da177 12034 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 12035 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 12036 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 12037 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 12038 #define RTC_ALRMAR_MSK3_Pos (23U)
<> 161:2cc1468da177 12039 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 12040 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
<> 161:2cc1468da177 12041 #define RTC_ALRMAR_PM_Pos (22U)
<> 161:2cc1468da177 12042 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 12043 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
<> 161:2cc1468da177 12044 #define RTC_ALRMAR_HT_Pos (20U)
<> 161:2cc1468da177 12045 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 12046 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
<> 161:2cc1468da177 12047 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 12048 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 12049 #define RTC_ALRMAR_HU_Pos (16U)
<> 161:2cc1468da177 12050 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 12051 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
<> 161:2cc1468da177 12052 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 12053 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 12054 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 12055 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 12056 #define RTC_ALRMAR_MSK2_Pos (15U)
<> 161:2cc1468da177 12057 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 12058 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
<> 161:2cc1468da177 12059 #define RTC_ALRMAR_MNT_Pos (12U)
<> 161:2cc1468da177 12060 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
<> 161:2cc1468da177 12061 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
<> 161:2cc1468da177 12062 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 12063 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 12064 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 12065 #define RTC_ALRMAR_MNU_Pos (8U)
<> 161:2cc1468da177 12066 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 12067 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
<> 161:2cc1468da177 12068 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12069 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 12070 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 12071 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 12072 #define RTC_ALRMAR_MSK1_Pos (7U)
<> 161:2cc1468da177 12073 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 12074 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
<> 161:2cc1468da177 12075 #define RTC_ALRMAR_ST_Pos (4U)
<> 161:2cc1468da177 12076 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
<> 161:2cc1468da177 12077 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
<> 161:2cc1468da177 12078 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12079 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12080 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12081 #define RTC_ALRMAR_SU_Pos (0U)
<> 161:2cc1468da177 12082 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 12083 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
<> 161:2cc1468da177 12084 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12085 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12086 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12087 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 12088
<> 144:ef7eb2e8f9f7 12089 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 161:2cc1468da177 12090 #define RTC_ALRMBR_MSK4_Pos (31U)
<> 161:2cc1468da177 12091 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 12092 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
<> 161:2cc1468da177 12093 #define RTC_ALRMBR_WDSEL_Pos (30U)
<> 161:2cc1468da177 12094 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 12095 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
<> 161:2cc1468da177 12096 #define RTC_ALRMBR_DT_Pos (28U)
<> 161:2cc1468da177 12097 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 12098 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
<> 161:2cc1468da177 12099 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 12100 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 12101 #define RTC_ALRMBR_DU_Pos (24U)
<> 161:2cc1468da177 12102 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 12103 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
<> 161:2cc1468da177 12104 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 12105 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 12106 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 12107 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 12108 #define RTC_ALRMBR_MSK3_Pos (23U)
<> 161:2cc1468da177 12109 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 12110 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
<> 161:2cc1468da177 12111 #define RTC_ALRMBR_PM_Pos (22U)
<> 161:2cc1468da177 12112 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 12113 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
<> 161:2cc1468da177 12114 #define RTC_ALRMBR_HT_Pos (20U)
<> 161:2cc1468da177 12115 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 12116 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
<> 161:2cc1468da177 12117 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 12118 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 12119 #define RTC_ALRMBR_HU_Pos (16U)
<> 161:2cc1468da177 12120 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 12121 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
<> 161:2cc1468da177 12122 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 12123 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 12124 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 12125 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 12126 #define RTC_ALRMBR_MSK2_Pos (15U)
<> 161:2cc1468da177 12127 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 12128 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
<> 161:2cc1468da177 12129 #define RTC_ALRMBR_MNT_Pos (12U)
<> 161:2cc1468da177 12130 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
<> 161:2cc1468da177 12131 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
<> 161:2cc1468da177 12132 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 12133 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 12134 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 12135 #define RTC_ALRMBR_MNU_Pos (8U)
<> 161:2cc1468da177 12136 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 12137 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
<> 161:2cc1468da177 12138 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12139 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 12140 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 12141 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 12142 #define RTC_ALRMBR_MSK1_Pos (7U)
<> 161:2cc1468da177 12143 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 12144 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
<> 161:2cc1468da177 12145 #define RTC_ALRMBR_ST_Pos (4U)
<> 161:2cc1468da177 12146 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
<> 161:2cc1468da177 12147 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
<> 161:2cc1468da177 12148 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12149 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12150 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12151 #define RTC_ALRMBR_SU_Pos (0U)
<> 161:2cc1468da177 12152 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 12153 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
<> 161:2cc1468da177 12154 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12155 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12156 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12157 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 12158
<> 144:ef7eb2e8f9f7 12159 /******************** Bits definition for RTC_WPR register ******************/
<> 161:2cc1468da177 12160 #define RTC_WPR_KEY_Pos (0U)
<> 161:2cc1468da177 12161 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 12162 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
<> 144:ef7eb2e8f9f7 12163
<> 144:ef7eb2e8f9f7 12164 /******************** Bits definition for RTC_SSR register ******************/
<> 161:2cc1468da177 12165 #define RTC_SSR_SS_Pos (0U)
<> 161:2cc1468da177 12166 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 12167 #define RTC_SSR_SS RTC_SSR_SS_Msk
<> 144:ef7eb2e8f9f7 12168
<> 144:ef7eb2e8f9f7 12169 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 161:2cc1468da177 12170 #define RTC_SHIFTR_SUBFS_Pos (0U)
<> 161:2cc1468da177 12171 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
<> 161:2cc1468da177 12172 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
<> 161:2cc1468da177 12173 #define RTC_SHIFTR_ADD1S_Pos (31U)
<> 161:2cc1468da177 12174 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 12175 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
<> 144:ef7eb2e8f9f7 12176
<> 144:ef7eb2e8f9f7 12177 /******************** Bits definition for RTC_TSTR register *****************/
<> 161:2cc1468da177 12178 #define RTC_TSTR_PM_Pos (22U)
<> 161:2cc1468da177 12179 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 12180 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
<> 161:2cc1468da177 12181 #define RTC_TSTR_HT_Pos (20U)
<> 161:2cc1468da177 12182 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 12183 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
<> 161:2cc1468da177 12184 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 12185 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 12186 #define RTC_TSTR_HU_Pos (16U)
<> 161:2cc1468da177 12187 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 12188 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
<> 161:2cc1468da177 12189 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 12190 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 12191 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 12192 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 12193 #define RTC_TSTR_MNT_Pos (12U)
<> 161:2cc1468da177 12194 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
<> 161:2cc1468da177 12195 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
<> 161:2cc1468da177 12196 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 12197 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 12198 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 12199 #define RTC_TSTR_MNU_Pos (8U)
<> 161:2cc1468da177 12200 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 12201 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
<> 161:2cc1468da177 12202 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12203 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 12204 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 12205 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 12206 #define RTC_TSTR_ST_Pos (4U)
<> 161:2cc1468da177 12207 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
<> 161:2cc1468da177 12208 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
<> 161:2cc1468da177 12209 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12210 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12211 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12212 #define RTC_TSTR_SU_Pos (0U)
<> 161:2cc1468da177 12213 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 12214 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
<> 161:2cc1468da177 12215 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12216 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12217 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12218 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 12219
<> 144:ef7eb2e8f9f7 12220 /******************** Bits definition for RTC_TSDR register *****************/
<> 161:2cc1468da177 12221 #define RTC_TSDR_WDU_Pos (13U)
<> 161:2cc1468da177 12222 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
<> 161:2cc1468da177 12223 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
<> 161:2cc1468da177 12224 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 12225 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 12226 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 12227 #define RTC_TSDR_MT_Pos (12U)
<> 161:2cc1468da177 12228 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 12229 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
<> 161:2cc1468da177 12230 #define RTC_TSDR_MU_Pos (8U)
<> 161:2cc1468da177 12231 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 12232 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
<> 161:2cc1468da177 12233 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12234 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 12235 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 12236 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 12237 #define RTC_TSDR_DT_Pos (4U)
<> 161:2cc1468da177 12238 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 12239 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
<> 161:2cc1468da177 12240 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12241 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12242 #define RTC_TSDR_DU_Pos (0U)
<> 161:2cc1468da177 12243 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 12244 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
<> 161:2cc1468da177 12245 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12246 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12247 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12248 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 12249
<> 144:ef7eb2e8f9f7 12250 /******************** Bits definition for RTC_TSSSR register ****************/
<> 161:2cc1468da177 12251 #define RTC_TSSSR_SS_Pos (0U)
<> 161:2cc1468da177 12252 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 12253 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
<> 144:ef7eb2e8f9f7 12254
<> 144:ef7eb2e8f9f7 12255 /******************** Bits definition for RTC_CAL register *****************/
<> 161:2cc1468da177 12256 #define RTC_CALR_CALP_Pos (15U)
<> 161:2cc1468da177 12257 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 12258 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
<> 161:2cc1468da177 12259 #define RTC_CALR_CALW8_Pos (14U)
<> 161:2cc1468da177 12260 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 12261 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
<> 161:2cc1468da177 12262 #define RTC_CALR_CALW16_Pos (13U)
<> 161:2cc1468da177 12263 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 12264 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
<> 161:2cc1468da177 12265 #define RTC_CALR_CALM_Pos (0U)
<> 161:2cc1468da177 12266 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
<> 161:2cc1468da177 12267 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
<> 161:2cc1468da177 12268 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12269 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12270 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12271 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12272 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12273 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12274 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12275 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 12276 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 12277
<> 144:ef7eb2e8f9f7 12278 /******************** Bits definition for RTC_TAMPCR register ****************/
<> 161:2cc1468da177 12279 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
<> 161:2cc1468da177 12280 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 12281 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
<> 161:2cc1468da177 12282 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
<> 161:2cc1468da177 12283 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 12284 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
<> 161:2cc1468da177 12285 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
<> 161:2cc1468da177 12286 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 12287 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
<> 161:2cc1468da177 12288 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
<> 161:2cc1468da177 12289 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 12290 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
<> 161:2cc1468da177 12291 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
<> 161:2cc1468da177 12292 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 12293 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
<> 161:2cc1468da177 12294 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
<> 161:2cc1468da177 12295 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 12296 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
<> 161:2cc1468da177 12297 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
<> 161:2cc1468da177 12298 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 12299 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
<> 161:2cc1468da177 12300 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
<> 161:2cc1468da177 12301 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 12302 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
<> 161:2cc1468da177 12303 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
<> 161:2cc1468da177 12304 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 12305 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
<> 161:2cc1468da177 12306 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
<> 161:2cc1468da177 12307 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 12308 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
<> 161:2cc1468da177 12309 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
<> 161:2cc1468da177 12310 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
<> 161:2cc1468da177 12311 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
<> 161:2cc1468da177 12312 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 12313 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 12314 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
<> 161:2cc1468da177 12315 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
<> 161:2cc1468da177 12316 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
<> 161:2cc1468da177 12317 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 12318 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 12319 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
<> 161:2cc1468da177 12320 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
<> 161:2cc1468da177 12321 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
<> 161:2cc1468da177 12322 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12323 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 12324 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 12325 #define RTC_TAMPCR_TAMPTS_Pos (7U)
<> 161:2cc1468da177 12326 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 12327 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
<> 161:2cc1468da177 12328 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
<> 161:2cc1468da177 12329 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12330 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
<> 161:2cc1468da177 12331 #define RTC_TAMPCR_TAMP3E_Pos (5U)
<> 161:2cc1468da177 12332 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12333 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
<> 161:2cc1468da177 12334 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
<> 161:2cc1468da177 12335 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12336 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
<> 161:2cc1468da177 12337 #define RTC_TAMPCR_TAMP2E_Pos (3U)
<> 161:2cc1468da177 12338 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12339 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
<> 161:2cc1468da177 12340 #define RTC_TAMPCR_TAMPIE_Pos (2U)
<> 161:2cc1468da177 12341 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12342 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
<> 161:2cc1468da177 12343 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
<> 161:2cc1468da177 12344 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12345 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
<> 161:2cc1468da177 12346 #define RTC_TAMPCR_TAMP1E_Pos (0U)
<> 161:2cc1468da177 12347 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12348 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
<> 144:ef7eb2e8f9f7 12349
<> 144:ef7eb2e8f9f7 12350
<> 144:ef7eb2e8f9f7 12351 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 161:2cc1468da177 12352 #define RTC_ALRMASSR_MASKSS_Pos (24U)
<> 161:2cc1468da177 12353 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 12354 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
<> 161:2cc1468da177 12355 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 12356 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 12357 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 12358 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 12359 #define RTC_ALRMASSR_SS_Pos (0U)
<> 161:2cc1468da177 12360 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
<> 161:2cc1468da177 12361 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
<> 144:ef7eb2e8f9f7 12362
<> 144:ef7eb2e8f9f7 12363 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 161:2cc1468da177 12364 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
<> 161:2cc1468da177 12365 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 161:2cc1468da177 12366 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
<> 161:2cc1468da177 12367 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 12368 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 12369 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 12370 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 12371 #define RTC_ALRMBSSR_SS_Pos (0U)
<> 161:2cc1468da177 12372 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
<> 161:2cc1468da177 12373 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
<> 144:ef7eb2e8f9f7 12374
<> 144:ef7eb2e8f9f7 12375 /******************** Bits definition for RTC_OR register ****************/
<> 161:2cc1468da177 12376 #define RTC_OR_TSINSEL_Pos (1U)
<> 161:2cc1468da177 12377 #define RTC_OR_TSINSEL_Msk (0x3U << RTC_OR_TSINSEL_Pos) /*!< 0x00000006 */
<> 161:2cc1468da177 12378 #define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk
<> 161:2cc1468da177 12379 #define RTC_OR_TSINSEL_0 (0x1U << RTC_OR_TSINSEL_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12380 #define RTC_OR_TSINSEL_1 (0x2U << RTC_OR_TSINSEL_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12381 #define RTC_OR_ALARMOUTTYPE_Pos (3U)
<> 161:2cc1468da177 12382 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12383 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
<> 161:2cc1468da177 12384 /* Legacy defines*/
<> 161:2cc1468da177 12385 #define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE
<> 144:ef7eb2e8f9f7 12386
<> 144:ef7eb2e8f9f7 12387 /******************** Bits definition for RTC_BKP0R register ****************/
<> 161:2cc1468da177 12388 #define RTC_BKP0R_Pos (0U)
<> 161:2cc1468da177 12389 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12390 #define RTC_BKP0R RTC_BKP0R_Msk
<> 144:ef7eb2e8f9f7 12391
<> 144:ef7eb2e8f9f7 12392 /******************** Bits definition for RTC_BKP1R register ****************/
<> 161:2cc1468da177 12393 #define RTC_BKP1R_Pos (0U)
<> 161:2cc1468da177 12394 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12395 #define RTC_BKP1R RTC_BKP1R_Msk
<> 144:ef7eb2e8f9f7 12396
<> 144:ef7eb2e8f9f7 12397 /******************** Bits definition for RTC_BKP2R register ****************/
<> 161:2cc1468da177 12398 #define RTC_BKP2R_Pos (0U)
<> 161:2cc1468da177 12399 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12400 #define RTC_BKP2R RTC_BKP2R_Msk
<> 144:ef7eb2e8f9f7 12401
<> 144:ef7eb2e8f9f7 12402 /******************** Bits definition for RTC_BKP3R register ****************/
<> 161:2cc1468da177 12403 #define RTC_BKP3R_Pos (0U)
<> 161:2cc1468da177 12404 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12405 #define RTC_BKP3R RTC_BKP3R_Msk
<> 144:ef7eb2e8f9f7 12406
<> 144:ef7eb2e8f9f7 12407 /******************** Bits definition for RTC_BKP4R register ****************/
<> 161:2cc1468da177 12408 #define RTC_BKP4R_Pos (0U)
<> 161:2cc1468da177 12409 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12410 #define RTC_BKP4R RTC_BKP4R_Msk
<> 144:ef7eb2e8f9f7 12411
<> 144:ef7eb2e8f9f7 12412 /******************** Bits definition for RTC_BKP5R register ****************/
<> 161:2cc1468da177 12413 #define RTC_BKP5R_Pos (0U)
<> 161:2cc1468da177 12414 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12415 #define RTC_BKP5R RTC_BKP5R_Msk
<> 144:ef7eb2e8f9f7 12416
<> 144:ef7eb2e8f9f7 12417 /******************** Bits definition for RTC_BKP6R register ****************/
<> 161:2cc1468da177 12418 #define RTC_BKP6R_Pos (0U)
<> 161:2cc1468da177 12419 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12420 #define RTC_BKP6R RTC_BKP6R_Msk
<> 144:ef7eb2e8f9f7 12421
<> 144:ef7eb2e8f9f7 12422 /******************** Bits definition for RTC_BKP7R register ****************/
<> 161:2cc1468da177 12423 #define RTC_BKP7R_Pos (0U)
<> 161:2cc1468da177 12424 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12425 #define RTC_BKP7R RTC_BKP7R_Msk
<> 144:ef7eb2e8f9f7 12426
<> 144:ef7eb2e8f9f7 12427 /******************** Bits definition for RTC_BKP8R register ****************/
<> 161:2cc1468da177 12428 #define RTC_BKP8R_Pos (0U)
<> 161:2cc1468da177 12429 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12430 #define RTC_BKP8R RTC_BKP8R_Msk
<> 144:ef7eb2e8f9f7 12431
<> 144:ef7eb2e8f9f7 12432 /******************** Bits definition for RTC_BKP9R register ****************/
<> 161:2cc1468da177 12433 #define RTC_BKP9R_Pos (0U)
<> 161:2cc1468da177 12434 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12435 #define RTC_BKP9R RTC_BKP9R_Msk
<> 144:ef7eb2e8f9f7 12436
<> 144:ef7eb2e8f9f7 12437 /******************** Bits definition for RTC_BKP10R register ***************/
<> 161:2cc1468da177 12438 #define RTC_BKP10R_Pos (0U)
<> 161:2cc1468da177 12439 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12440 #define RTC_BKP10R RTC_BKP10R_Msk
<> 144:ef7eb2e8f9f7 12441
<> 144:ef7eb2e8f9f7 12442 /******************** Bits definition for RTC_BKP11R register ***************/
<> 161:2cc1468da177 12443 #define RTC_BKP11R_Pos (0U)
<> 161:2cc1468da177 12444 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12445 #define RTC_BKP11R RTC_BKP11R_Msk
<> 144:ef7eb2e8f9f7 12446
<> 144:ef7eb2e8f9f7 12447 /******************** Bits definition for RTC_BKP12R register ***************/
<> 161:2cc1468da177 12448 #define RTC_BKP12R_Pos (0U)
<> 161:2cc1468da177 12449 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12450 #define RTC_BKP12R RTC_BKP12R_Msk
<> 144:ef7eb2e8f9f7 12451
<> 144:ef7eb2e8f9f7 12452 /******************** Bits definition for RTC_BKP13R register ***************/
<> 161:2cc1468da177 12453 #define RTC_BKP13R_Pos (0U)
<> 161:2cc1468da177 12454 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12455 #define RTC_BKP13R RTC_BKP13R_Msk
<> 144:ef7eb2e8f9f7 12456
<> 144:ef7eb2e8f9f7 12457 /******************** Bits definition for RTC_BKP14R register ***************/
<> 161:2cc1468da177 12458 #define RTC_BKP14R_Pos (0U)
<> 161:2cc1468da177 12459 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12460 #define RTC_BKP14R RTC_BKP14R_Msk
<> 144:ef7eb2e8f9f7 12461
<> 144:ef7eb2e8f9f7 12462 /******************** Bits definition for RTC_BKP15R register ***************/
<> 161:2cc1468da177 12463 #define RTC_BKP15R_Pos (0U)
<> 161:2cc1468da177 12464 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12465 #define RTC_BKP15R RTC_BKP15R_Msk
<> 144:ef7eb2e8f9f7 12466
<> 144:ef7eb2e8f9f7 12467 /******************** Bits definition for RTC_BKP16R register ***************/
<> 161:2cc1468da177 12468 #define RTC_BKP16R_Pos (0U)
<> 161:2cc1468da177 12469 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12470 #define RTC_BKP16R RTC_BKP16R_Msk
<> 144:ef7eb2e8f9f7 12471
<> 144:ef7eb2e8f9f7 12472 /******************** Bits definition for RTC_BKP17R register ***************/
<> 161:2cc1468da177 12473 #define RTC_BKP17R_Pos (0U)
<> 161:2cc1468da177 12474 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12475 #define RTC_BKP17R RTC_BKP17R_Msk
<> 144:ef7eb2e8f9f7 12476
<> 144:ef7eb2e8f9f7 12477 /******************** Bits definition for RTC_BKP18R register ***************/
<> 161:2cc1468da177 12478 #define RTC_BKP18R_Pos (0U)
<> 161:2cc1468da177 12479 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12480 #define RTC_BKP18R RTC_BKP18R_Msk
<> 144:ef7eb2e8f9f7 12481
<> 144:ef7eb2e8f9f7 12482 /******************** Bits definition for RTC_BKP19R register ***************/
<> 161:2cc1468da177 12483 #define RTC_BKP19R_Pos (0U)
<> 161:2cc1468da177 12484 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12485 #define RTC_BKP19R RTC_BKP19R_Msk
<> 144:ef7eb2e8f9f7 12486
<> 144:ef7eb2e8f9f7 12487 /******************** Bits definition for RTC_BKP20R register ***************/
<> 161:2cc1468da177 12488 #define RTC_BKP20R_Pos (0U)
<> 161:2cc1468da177 12489 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12490 #define RTC_BKP20R RTC_BKP20R_Msk
<> 144:ef7eb2e8f9f7 12491
<> 144:ef7eb2e8f9f7 12492 /******************** Bits definition for RTC_BKP21R register ***************/
<> 161:2cc1468da177 12493 #define RTC_BKP21R_Pos (0U)
<> 161:2cc1468da177 12494 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12495 #define RTC_BKP21R RTC_BKP21R_Msk
<> 144:ef7eb2e8f9f7 12496
<> 144:ef7eb2e8f9f7 12497 /******************** Bits definition for RTC_BKP22R register ***************/
<> 161:2cc1468da177 12498 #define RTC_BKP22R_Pos (0U)
<> 161:2cc1468da177 12499 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12500 #define RTC_BKP22R RTC_BKP22R_Msk
<> 144:ef7eb2e8f9f7 12501
<> 144:ef7eb2e8f9f7 12502 /******************** Bits definition for RTC_BKP23R register ***************/
<> 161:2cc1468da177 12503 #define RTC_BKP23R_Pos (0U)
<> 161:2cc1468da177 12504 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12505 #define RTC_BKP23R RTC_BKP23R_Msk
<> 144:ef7eb2e8f9f7 12506
<> 144:ef7eb2e8f9f7 12507 /******************** Bits definition for RTC_BKP24R register ***************/
<> 161:2cc1468da177 12508 #define RTC_BKP24R_Pos (0U)
<> 161:2cc1468da177 12509 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12510 #define RTC_BKP24R RTC_BKP24R_Msk
<> 144:ef7eb2e8f9f7 12511
<> 144:ef7eb2e8f9f7 12512 /******************** Bits definition for RTC_BKP25R register ***************/
<> 161:2cc1468da177 12513 #define RTC_BKP25R_Pos (0U)
<> 161:2cc1468da177 12514 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12515 #define RTC_BKP25R RTC_BKP25R_Msk
<> 144:ef7eb2e8f9f7 12516
<> 144:ef7eb2e8f9f7 12517 /******************** Bits definition for RTC_BKP26R register ***************/
<> 161:2cc1468da177 12518 #define RTC_BKP26R_Pos (0U)
<> 161:2cc1468da177 12519 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12520 #define RTC_BKP26R RTC_BKP26R_Msk
<> 144:ef7eb2e8f9f7 12521
<> 144:ef7eb2e8f9f7 12522 /******************** Bits definition for RTC_BKP27R register ***************/
<> 161:2cc1468da177 12523 #define RTC_BKP27R_Pos (0U)
<> 161:2cc1468da177 12524 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12525 #define RTC_BKP27R RTC_BKP27R_Msk
<> 144:ef7eb2e8f9f7 12526
<> 144:ef7eb2e8f9f7 12527 /******************** Bits definition for RTC_BKP28R register ***************/
<> 161:2cc1468da177 12528 #define RTC_BKP28R_Pos (0U)
<> 161:2cc1468da177 12529 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12530 #define RTC_BKP28R RTC_BKP28R_Msk
<> 144:ef7eb2e8f9f7 12531
<> 144:ef7eb2e8f9f7 12532 /******************** Bits definition for RTC_BKP29R register ***************/
<> 161:2cc1468da177 12533 #define RTC_BKP29R_Pos (0U)
<> 161:2cc1468da177 12534 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12535 #define RTC_BKP29R RTC_BKP29R_Msk
<> 144:ef7eb2e8f9f7 12536
<> 144:ef7eb2e8f9f7 12537 /******************** Bits definition for RTC_BKP30R register ***************/
<> 161:2cc1468da177 12538 #define RTC_BKP30R_Pos (0U)
<> 161:2cc1468da177 12539 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12540 #define RTC_BKP30R RTC_BKP30R_Msk
<> 144:ef7eb2e8f9f7 12541
<> 144:ef7eb2e8f9f7 12542 /******************** Bits definition for RTC_BKP31R register ***************/
<> 161:2cc1468da177 12543 #define RTC_BKP31R_Pos (0U)
<> 161:2cc1468da177 12544 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12545 #define RTC_BKP31R RTC_BKP31R_Msk
<> 144:ef7eb2e8f9f7 12546
<> 144:ef7eb2e8f9f7 12547 /******************** Number of backup registers ******************************/
<> 161:2cc1468da177 12548 #define RTC_BKP_NUMBER 0x00000020U
<> 144:ef7eb2e8f9f7 12549
<> 144:ef7eb2e8f9f7 12550 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12551 /* */
<> 144:ef7eb2e8f9f7 12552 /* Serial Audio Interface */
<> 144:ef7eb2e8f9f7 12553 /* */
<> 144:ef7eb2e8f9f7 12554 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12555 /******************** Bit definition for SAI_GCR register *******************/
<> 161:2cc1468da177 12556 #define SAI_GCR_SYNCIN_Pos (0U)
<> 161:2cc1468da177 12557 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 12558 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
<> 161:2cc1468da177 12559 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12560 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12561
<> 161:2cc1468da177 12562 #define SAI_GCR_SYNCOUT_Pos (4U)
<> 161:2cc1468da177 12563 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 12564 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
<> 161:2cc1468da177 12565 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12566 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 12567
<> 144:ef7eb2e8f9f7 12568 /******************* Bit definition for SAI_xCR1 register *******************/
<> 161:2cc1468da177 12569 #define SAI_xCR1_MODE_Pos (0U)
<> 161:2cc1468da177 12570 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 12571 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
<> 161:2cc1468da177 12572 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12573 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12574
<> 161:2cc1468da177 12575 #define SAI_xCR1_PRTCFG_Pos (2U)
<> 161:2cc1468da177 12576 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 12577 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
<> 161:2cc1468da177 12578 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12579 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12580
<> 161:2cc1468da177 12581 #define SAI_xCR1_DS_Pos (5U)
<> 161:2cc1468da177 12582 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
<> 161:2cc1468da177 12583 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
<> 161:2cc1468da177 12584 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12585 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12586 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 12587
<> 161:2cc1468da177 12588 #define SAI_xCR1_LSBFIRST_Pos (8U)
<> 161:2cc1468da177 12589 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12590 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
<> 161:2cc1468da177 12591 #define SAI_xCR1_CKSTR_Pos (9U)
<> 161:2cc1468da177 12592 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 12593 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
<> 161:2cc1468da177 12594
<> 161:2cc1468da177 12595 #define SAI_xCR1_SYNCEN_Pos (10U)
<> 161:2cc1468da177 12596 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 12597 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
<> 161:2cc1468da177 12598 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 12599 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 12600
<> 161:2cc1468da177 12601 #define SAI_xCR1_MONO_Pos (12U)
<> 161:2cc1468da177 12602 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 12603 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
<> 161:2cc1468da177 12604 #define SAI_xCR1_OUTDRIV_Pos (13U)
<> 161:2cc1468da177 12605 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 12606 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
<> 161:2cc1468da177 12607 #define SAI_xCR1_SAIEN_Pos (16U)
<> 161:2cc1468da177 12608 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 12609 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
<> 161:2cc1468da177 12610 #define SAI_xCR1_DMAEN_Pos (17U)
<> 161:2cc1468da177 12611 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 12612 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
<> 161:2cc1468da177 12613 #define SAI_xCR1_NODIV_Pos (19U)
<> 161:2cc1468da177 12614 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 12615 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
<> 161:2cc1468da177 12616
<> 161:2cc1468da177 12617 #define SAI_xCR1_MCKDIV_Pos (20U)
<> 161:2cc1468da177 12618 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 12619 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
<> 161:2cc1468da177 12620 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 12621 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 12622 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 12623 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 12624
<> 144:ef7eb2e8f9f7 12625 /******************* Bit definition for SAI_xCR2 register *******************/
<> 161:2cc1468da177 12626 #define SAI_xCR2_FTH_Pos (0U)
<> 161:2cc1468da177 12627 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 12628 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
<> 161:2cc1468da177 12629 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12630 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12631 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12632
<> 161:2cc1468da177 12633 #define SAI_xCR2_FFLUSH_Pos (3U)
<> 161:2cc1468da177 12634 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12635 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
<> 161:2cc1468da177 12636 #define SAI_xCR2_TRIS_Pos (4U)
<> 161:2cc1468da177 12637 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12638 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
<> 161:2cc1468da177 12639 #define SAI_xCR2_MUTE_Pos (5U)
<> 161:2cc1468da177 12640 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12641 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
<> 161:2cc1468da177 12642 #define SAI_xCR2_MUTEVAL_Pos (6U)
<> 161:2cc1468da177 12643 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12644 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
<> 161:2cc1468da177 12645
<> 161:2cc1468da177 12646 #define SAI_xCR2_MUTECNT_Pos (7U)
<> 161:2cc1468da177 12647 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
<> 161:2cc1468da177 12648 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
<> 161:2cc1468da177 12649 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 12650 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12651 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 12652 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 12653 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 12654 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 12655
<> 161:2cc1468da177 12656 #define SAI_xCR2_CPL_Pos (13U)
<> 161:2cc1468da177 12657 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 12658 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
<> 161:2cc1468da177 12659
<> 161:2cc1468da177 12660 #define SAI_xCR2_COMP_Pos (14U)
<> 161:2cc1468da177 12661 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 12662 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
<> 161:2cc1468da177 12663 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 12664 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 12665
<> 144:ef7eb2e8f9f7 12666 /****************** Bit definition for SAI_xFRCR register *******************/
<> 161:2cc1468da177 12667 #define SAI_xFRCR_FRL_Pos (0U)
<> 161:2cc1468da177 12668 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 12669 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
<> 161:2cc1468da177 12670 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12671 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12672 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12673 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12674 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12675 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12676 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12677 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 12678
<> 161:2cc1468da177 12679 #define SAI_xFRCR_FSALL_Pos (8U)
<> 161:2cc1468da177 12680 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
<> 161:2cc1468da177 12681 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
<> 161:2cc1468da177 12682 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12683 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 12684 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 12685 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 12686 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 12687 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 12688 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 12689
<> 161:2cc1468da177 12690 #define SAI_xFRCR_FSDEF_Pos (16U)
<> 161:2cc1468da177 12691 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 12692 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
<> 161:2cc1468da177 12693 #define SAI_xFRCR_FSPOL_Pos (17U)
<> 161:2cc1468da177 12694 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 12695 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
<> 161:2cc1468da177 12696 #define SAI_xFRCR_FSOFF_Pos (18U)
<> 161:2cc1468da177 12697 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 12698 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
<> 161:2cc1468da177 12699
<> 161:2cc1468da177 12700 /* Legacy define */
<> 144:ef7eb2e8f9f7 12701 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
<> 144:ef7eb2e8f9f7 12702
<> 144:ef7eb2e8f9f7 12703 /****************** Bit definition for SAI_xSLOTR register *******************/
<> 161:2cc1468da177 12704 #define SAI_xSLOTR_FBOFF_Pos (0U)
<> 161:2cc1468da177 12705 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
<> 161:2cc1468da177 12706 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
<> 161:2cc1468da177 12707 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12708 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12709 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12710 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12711 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12712
<> 161:2cc1468da177 12713 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
<> 161:2cc1468da177 12714 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 12715 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
<> 161:2cc1468da177 12716 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12717 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 12718
<> 161:2cc1468da177 12719 #define SAI_xSLOTR_NBSLOT_Pos (8U)
<> 161:2cc1468da177 12720 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 12721 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
<> 161:2cc1468da177 12722 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12723 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 12724 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 12725 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 12726
<> 161:2cc1468da177 12727 #define SAI_xSLOTR_SLOTEN_Pos (16U)
<> 161:2cc1468da177 12728 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 12729 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
<> 144:ef7eb2e8f9f7 12730
<> 144:ef7eb2e8f9f7 12731 /******************* Bit definition for SAI_xIMR register *******************/
<> 161:2cc1468da177 12732 #define SAI_xIMR_OVRUDRIE_Pos (0U)
<> 161:2cc1468da177 12733 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12734 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
<> 161:2cc1468da177 12735 #define SAI_xIMR_MUTEDETIE_Pos (1U)
<> 161:2cc1468da177 12736 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12737 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
<> 161:2cc1468da177 12738 #define SAI_xIMR_WCKCFGIE_Pos (2U)
<> 161:2cc1468da177 12739 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12740 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
<> 161:2cc1468da177 12741 #define SAI_xIMR_FREQIE_Pos (3U)
<> 161:2cc1468da177 12742 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12743 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
<> 161:2cc1468da177 12744 #define SAI_xIMR_CNRDYIE_Pos (4U)
<> 161:2cc1468da177 12745 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12746 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
<> 161:2cc1468da177 12747 #define SAI_xIMR_AFSDETIE_Pos (5U)
<> 161:2cc1468da177 12748 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12749 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
<> 161:2cc1468da177 12750 #define SAI_xIMR_LFSDETIE_Pos (6U)
<> 161:2cc1468da177 12751 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12752 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
<> 144:ef7eb2e8f9f7 12753
<> 144:ef7eb2e8f9f7 12754 /******************** Bit definition for SAI_xSR register *******************/
<> 161:2cc1468da177 12755 #define SAI_xSR_OVRUDR_Pos (0U)
<> 161:2cc1468da177 12756 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12757 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
<> 161:2cc1468da177 12758 #define SAI_xSR_MUTEDET_Pos (1U)
<> 161:2cc1468da177 12759 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12760 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
<> 161:2cc1468da177 12761 #define SAI_xSR_WCKCFG_Pos (2U)
<> 161:2cc1468da177 12762 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12763 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
<> 161:2cc1468da177 12764 #define SAI_xSR_FREQ_Pos (3U)
<> 161:2cc1468da177 12765 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12766 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
<> 161:2cc1468da177 12767 #define SAI_xSR_CNRDY_Pos (4U)
<> 161:2cc1468da177 12768 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12769 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
<> 161:2cc1468da177 12770 #define SAI_xSR_AFSDET_Pos (5U)
<> 161:2cc1468da177 12771 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12772 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
<> 161:2cc1468da177 12773 #define SAI_xSR_LFSDET_Pos (6U)
<> 161:2cc1468da177 12774 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12775 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
<> 161:2cc1468da177 12776
<> 161:2cc1468da177 12777 #define SAI_xSR_FLVL_Pos (16U)
<> 161:2cc1468da177 12778 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
<> 161:2cc1468da177 12779 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
<> 161:2cc1468da177 12780 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 12781 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 12782 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 12783
<> 144:ef7eb2e8f9f7 12784 /****************** Bit definition for SAI_xCLRFR register ******************/
<> 161:2cc1468da177 12785 #define SAI_xCLRFR_COVRUDR_Pos (0U)
<> 161:2cc1468da177 12786 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12787 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
<> 161:2cc1468da177 12788 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
<> 161:2cc1468da177 12789 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12790 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
<> 161:2cc1468da177 12791 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
<> 161:2cc1468da177 12792 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12793 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
<> 161:2cc1468da177 12794 #define SAI_xCLRFR_CFREQ_Pos (3U)
<> 161:2cc1468da177 12795 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12796 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
<> 161:2cc1468da177 12797 #define SAI_xCLRFR_CCNRDY_Pos (4U)
<> 161:2cc1468da177 12798 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12799 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
<> 161:2cc1468da177 12800 #define SAI_xCLRFR_CAFSDET_Pos (5U)
<> 161:2cc1468da177 12801 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12802 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
<> 161:2cc1468da177 12803 #define SAI_xCLRFR_CLFSDET_Pos (6U)
<> 161:2cc1468da177 12804 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12805 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
<> 144:ef7eb2e8f9f7 12806
<> 144:ef7eb2e8f9f7 12807 /****************** Bit definition for SAI_xDR register *********************/
<> 161:2cc1468da177 12808 #define SAI_xDR_DATA_Pos (0U)
<> 161:2cc1468da177 12809 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 12810 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
<> 144:ef7eb2e8f9f7 12811
<> 144:ef7eb2e8f9f7 12812 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12813 /* */
<> 144:ef7eb2e8f9f7 12814 /* SPDIF-RX Interface */
<> 144:ef7eb2e8f9f7 12815 /* */
<> 144:ef7eb2e8f9f7 12816 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12817 /******************** Bit definition for SPDIF_CR register *******************/
<> 161:2cc1468da177 12818 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
<> 161:2cc1468da177 12819 #define SPDIFRX_CR_SPDIFEN_Msk (0x3U << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 12820 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
<> 161:2cc1468da177 12821 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
<> 161:2cc1468da177 12822 #define SPDIFRX_CR_RXDMAEN_Msk (0x1U << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12823 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
<> 161:2cc1468da177 12824 #define SPDIFRX_CR_RXSTEO_Pos (3U)
<> 161:2cc1468da177 12825 #define SPDIFRX_CR_RXSTEO_Msk (0x1U << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12826 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
<> 161:2cc1468da177 12827 #define SPDIFRX_CR_DRFMT_Pos (4U)
<> 161:2cc1468da177 12828 #define SPDIFRX_CR_DRFMT_Msk (0x3U << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 12829 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
<> 161:2cc1468da177 12830 #define SPDIFRX_CR_PMSK_Pos (6U)
<> 161:2cc1468da177 12831 #define SPDIFRX_CR_PMSK_Msk (0x1U << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12832 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
<> 161:2cc1468da177 12833 #define SPDIFRX_CR_VMSK_Pos (7U)
<> 161:2cc1468da177 12834 #define SPDIFRX_CR_VMSK_Msk (0x1U << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 12835 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
<> 161:2cc1468da177 12836 #define SPDIFRX_CR_CUMSK_Pos (8U)
<> 161:2cc1468da177 12837 #define SPDIFRX_CR_CUMSK_Msk (0x1U << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12838 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
<> 161:2cc1468da177 12839 #define SPDIFRX_CR_PTMSK_Pos (9U)
<> 161:2cc1468da177 12840 #define SPDIFRX_CR_PTMSK_Msk (0x1U << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 12841 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
<> 161:2cc1468da177 12842 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
<> 161:2cc1468da177 12843 #define SPDIFRX_CR_CBDMAEN_Msk (0x1U << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 12844 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
<> 161:2cc1468da177 12845 #define SPDIFRX_CR_CHSEL_Pos (11U)
<> 161:2cc1468da177 12846 #define SPDIFRX_CR_CHSEL_Msk (0x1U << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 12847 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
<> 161:2cc1468da177 12848 #define SPDIFRX_CR_NBTR_Pos (12U)
<> 161:2cc1468da177 12849 #define SPDIFRX_CR_NBTR_Msk (0x3U << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
<> 161:2cc1468da177 12850 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
<> 161:2cc1468da177 12851 #define SPDIFRX_CR_WFA_Pos (14U)
<> 161:2cc1468da177 12852 #define SPDIFRX_CR_WFA_Msk (0x1U << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 12853 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
<> 161:2cc1468da177 12854 #define SPDIFRX_CR_INSEL_Pos (16U)
<> 161:2cc1468da177 12855 #define SPDIFRX_CR_INSEL_Msk (0x7U << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
<> 161:2cc1468da177 12856 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
<> 144:ef7eb2e8f9f7 12857
<> 144:ef7eb2e8f9f7 12858 /******************* Bit definition for SPDIFRX_IMR register *******************/
<> 161:2cc1468da177 12859 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
<> 161:2cc1468da177 12860 #define SPDIFRX_IMR_RXNEIE_Msk (0x1U << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12861 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
<> 161:2cc1468da177 12862 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
<> 161:2cc1468da177 12863 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1U << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12864 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
<> 161:2cc1468da177 12865 #define SPDIFRX_IMR_PERRIE_Pos (2U)
<> 161:2cc1468da177 12866 #define SPDIFRX_IMR_PERRIE_Msk (0x1U << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12867 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
<> 161:2cc1468da177 12868 #define SPDIFRX_IMR_OVRIE_Pos (3U)
<> 161:2cc1468da177 12869 #define SPDIFRX_IMR_OVRIE_Msk (0x1U << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12870 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
<> 161:2cc1468da177 12871 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
<> 161:2cc1468da177 12872 #define SPDIFRX_IMR_SBLKIE_Msk (0x1U << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12873 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
<> 161:2cc1468da177 12874 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
<> 161:2cc1468da177 12875 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1U << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12876 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
<> 161:2cc1468da177 12877 #define SPDIFRX_IMR_IFEIE_Pos (6U)
<> 161:2cc1468da177 12878 #define SPDIFRX_IMR_IFEIE_Msk (0x1U << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12879 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 12880
<> 144:ef7eb2e8f9f7 12881 /******************* Bit definition for SPDIFRX_SR register *******************/
<> 161:2cc1468da177 12882 #define SPDIFRX_SR_RXNE_Pos (0U)
<> 161:2cc1468da177 12883 #define SPDIFRX_SR_RXNE_Msk (0x1U << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12884 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
<> 161:2cc1468da177 12885 #define SPDIFRX_SR_CSRNE_Pos (1U)
<> 161:2cc1468da177 12886 #define SPDIFRX_SR_CSRNE_Msk (0x1U << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12887 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
<> 161:2cc1468da177 12888 #define SPDIFRX_SR_PERR_Pos (2U)
<> 161:2cc1468da177 12889 #define SPDIFRX_SR_PERR_Msk (0x1U << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12890 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
<> 161:2cc1468da177 12891 #define SPDIFRX_SR_OVR_Pos (3U)
<> 161:2cc1468da177 12892 #define SPDIFRX_SR_OVR_Msk (0x1U << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12893 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
<> 161:2cc1468da177 12894 #define SPDIFRX_SR_SBD_Pos (4U)
<> 161:2cc1468da177 12895 #define SPDIFRX_SR_SBD_Msk (0x1U << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12896 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
<> 161:2cc1468da177 12897 #define SPDIFRX_SR_SYNCD_Pos (5U)
<> 161:2cc1468da177 12898 #define SPDIFRX_SR_SYNCD_Msk (0x1U << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12899 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
<> 161:2cc1468da177 12900 #define SPDIFRX_SR_FERR_Pos (6U)
<> 161:2cc1468da177 12901 #define SPDIFRX_SR_FERR_Msk (0x1U << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 12902 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
<> 161:2cc1468da177 12903 #define SPDIFRX_SR_SERR_Pos (7U)
<> 161:2cc1468da177 12904 #define SPDIFRX_SR_SERR_Msk (0x1U << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 12905 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
<> 161:2cc1468da177 12906 #define SPDIFRX_SR_TERR_Pos (8U)
<> 161:2cc1468da177 12907 #define SPDIFRX_SR_TERR_Msk (0x1U << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 12908 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
<> 161:2cc1468da177 12909 #define SPDIFRX_SR_WIDTH5_Pos (16U)
<> 161:2cc1468da177 12910 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
<> 161:2cc1468da177 12911 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
<> 144:ef7eb2e8f9f7 12912
<> 144:ef7eb2e8f9f7 12913 /******************* Bit definition for SPDIFRX_IFCR register *******************/
<> 161:2cc1468da177 12914 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
<> 161:2cc1468da177 12915 #define SPDIFRX_IFCR_PERRCF_Msk (0x1U << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12916 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
<> 161:2cc1468da177 12917 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
<> 161:2cc1468da177 12918 #define SPDIFRX_IFCR_OVRCF_Msk (0x1U << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12919 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
<> 161:2cc1468da177 12920 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
<> 161:2cc1468da177 12921 #define SPDIFRX_IFCR_SBDCF_Msk (0x1U << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 12922 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
<> 161:2cc1468da177 12923 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
<> 161:2cc1468da177 12924 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 12925 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
<> 144:ef7eb2e8f9f7 12926
<> 144:ef7eb2e8f9f7 12927 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
<> 161:2cc1468da177 12928 #define SPDIFRX_DR0_DR_Pos (0U)
<> 161:2cc1468da177 12929 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFU << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
<> 161:2cc1468da177 12930 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
<> 161:2cc1468da177 12931 #define SPDIFRX_DR0_PE_Pos (24U)
<> 161:2cc1468da177 12932 #define SPDIFRX_DR0_PE_Msk (0x1U << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 12933 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
<> 161:2cc1468da177 12934 #define SPDIFRX_DR0_V_Pos (25U)
<> 161:2cc1468da177 12935 #define SPDIFRX_DR0_V_Msk (0x1U << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 12936 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
<> 161:2cc1468da177 12937 #define SPDIFRX_DR0_U_Pos (26U)
<> 161:2cc1468da177 12938 #define SPDIFRX_DR0_U_Msk (0x1U << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 12939 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
<> 161:2cc1468da177 12940 #define SPDIFRX_DR0_C_Pos (27U)
<> 161:2cc1468da177 12941 #define SPDIFRX_DR0_C_Msk (0x1U << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 12942 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
<> 161:2cc1468da177 12943 #define SPDIFRX_DR0_PT_Pos (28U)
<> 161:2cc1468da177 12944 #define SPDIFRX_DR0_PT_Msk (0x3U << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
<> 161:2cc1468da177 12945 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
<> 144:ef7eb2e8f9f7 12946
<> 144:ef7eb2e8f9f7 12947 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
<> 161:2cc1468da177 12948 #define SPDIFRX_DR1_DR_Pos (8U)
<> 161:2cc1468da177 12949 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFU << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
<> 161:2cc1468da177 12950 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
<> 161:2cc1468da177 12951 #define SPDIFRX_DR1_PT_Pos (4U)
<> 161:2cc1468da177 12952 #define SPDIFRX_DR1_PT_Msk (0x3U << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 12953 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
<> 161:2cc1468da177 12954 #define SPDIFRX_DR1_C_Pos (3U)
<> 161:2cc1468da177 12955 #define SPDIFRX_DR1_C_Msk (0x1U << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 12956 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
<> 161:2cc1468da177 12957 #define SPDIFRX_DR1_U_Pos (2U)
<> 161:2cc1468da177 12958 #define SPDIFRX_DR1_U_Msk (0x1U << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 12959 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
<> 161:2cc1468da177 12960 #define SPDIFRX_DR1_V_Pos (1U)
<> 161:2cc1468da177 12961 #define SPDIFRX_DR1_V_Msk (0x1U << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 12962 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
<> 161:2cc1468da177 12963 #define SPDIFRX_DR1_PE_Pos (0U)
<> 161:2cc1468da177 12964 #define SPDIFRX_DR1_PE_Msk (0x1U << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 12965 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
<> 144:ef7eb2e8f9f7 12966
<> 144:ef7eb2e8f9f7 12967 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
<> 161:2cc1468da177 12968 #define SPDIFRX_DR1_DRNL1_Pos (16U)
<> 161:2cc1468da177 12969 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 12970 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
<> 161:2cc1468da177 12971 #define SPDIFRX_DR1_DRNL2_Pos (0U)
<> 161:2cc1468da177 12972 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 12973 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
<> 144:ef7eb2e8f9f7 12974
<> 144:ef7eb2e8f9f7 12975 /******************* Bit definition for SPDIFRX_CSR register *******************/
<> 161:2cc1468da177 12976 #define SPDIFRX_CSR_USR_Pos (0U)
<> 161:2cc1468da177 12977 #define SPDIFRX_CSR_USR_Msk (0xFFFFU << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 12978 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
<> 161:2cc1468da177 12979 #define SPDIFRX_CSR_CS_Pos (16U)
<> 161:2cc1468da177 12980 #define SPDIFRX_CSR_CS_Msk (0xFFU << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 12981 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
<> 161:2cc1468da177 12982 #define SPDIFRX_CSR_SOB_Pos (24U)
<> 161:2cc1468da177 12983 #define SPDIFRX_CSR_SOB_Msk (0x1U << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 12984 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
<> 144:ef7eb2e8f9f7 12985
<> 144:ef7eb2e8f9f7 12986 /******************* Bit definition for SPDIFRX_DIR register *******************/
<> 161:2cc1468da177 12987 #define SPDIFRX_DIR_THI_Pos (0U)
<> 161:2cc1468da177 12988 #define SPDIFRX_DIR_THI_Msk (0x13FFU << SPDIFRX_DIR_THI_Pos) /*!< 0x000013FF */
<> 161:2cc1468da177 12989 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
<> 161:2cc1468da177 12990 #define SPDIFRX_DIR_TLO_Pos (16U)
<> 161:2cc1468da177 12991 #define SPDIFRX_DIR_TLO_Msk (0x1FFFU << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
<> 161:2cc1468da177 12992 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
<> 144:ef7eb2e8f9f7 12993
<> 144:ef7eb2e8f9f7 12994 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12995 /* */
<> 144:ef7eb2e8f9f7 12996 /* SD host Interface */
<> 144:ef7eb2e8f9f7 12997 /* */
<> 144:ef7eb2e8f9f7 12998 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12999 /****************** Bit definition for SDMMC_POWER register ******************/
<> 161:2cc1468da177 13000 #define SDMMC_POWER_PWRCTRL_Pos (0U)
<> 161:2cc1468da177 13001 #define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 13002 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
<> 161:2cc1468da177 13003 #define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x01 */
<> 161:2cc1468da177 13004 #define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x02 */
<> 144:ef7eb2e8f9f7 13005
<> 144:ef7eb2e8f9f7 13006 /****************** Bit definition for SDMMC_CLKCR register ******************/
<> 161:2cc1468da177 13007 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
<> 161:2cc1468da177 13008 #define SDMMC_CLKCR_CLKDIV_Msk (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 13009 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
<> 161:2cc1468da177 13010 #define SDMMC_CLKCR_CLKEN_Pos (8U)
<> 161:2cc1468da177 13011 #define SDMMC_CLKCR_CLKEN_Msk (0x1U << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13012 #define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
<> 161:2cc1468da177 13013 #define SDMMC_CLKCR_PWRSAV_Pos (9U)
<> 161:2cc1468da177 13014 #define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 13015 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
<> 161:2cc1468da177 13016 #define SDMMC_CLKCR_BYPASS_Pos (10U)
<> 161:2cc1468da177 13017 #define SDMMC_CLKCR_BYPASS_Msk (0x1U << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13018 #define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
<> 161:2cc1468da177 13019
<> 161:2cc1468da177 13020 #define SDMMC_CLKCR_WIDBUS_Pos (11U)
<> 161:2cc1468da177 13021 #define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
<> 161:2cc1468da177 13022 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
<> 161:2cc1468da177 13023 #define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
<> 161:2cc1468da177 13024 #define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
<> 161:2cc1468da177 13025
<> 161:2cc1468da177 13026 #define SDMMC_CLKCR_NEGEDGE_Pos (13U)
<> 161:2cc1468da177 13027 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 13028 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
<> 161:2cc1468da177 13029 #define SDMMC_CLKCR_HWFC_EN_Pos (14U)
<> 161:2cc1468da177 13030 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 13031 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
<> 144:ef7eb2e8f9f7 13032
<> 144:ef7eb2e8f9f7 13033 /******************* Bit definition for SDMMC_ARG register *******************/
<> 161:2cc1468da177 13034 #define SDMMC_ARG_CMDARG_Pos (0U)
<> 161:2cc1468da177 13035 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 13036 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
<> 144:ef7eb2e8f9f7 13037
<> 144:ef7eb2e8f9f7 13038 /******************* Bit definition for SDMMC_CMD register *******************/
<> 161:2cc1468da177 13039 #define SDMMC_CMD_CMDINDEX_Pos (0U)
<> 161:2cc1468da177 13040 #define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
<> 161:2cc1468da177 13041 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
<> 161:2cc1468da177 13042
<> 161:2cc1468da177 13043 #define SDMMC_CMD_WAITRESP_Pos (6U)
<> 161:2cc1468da177 13044 #define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 13045 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
<> 161:2cc1468da177 13046 #define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0040 */
<> 161:2cc1468da177 13047 #define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0080 */
<> 161:2cc1468da177 13048
<> 161:2cc1468da177 13049 #define SDMMC_CMD_WAITINT_Pos (8U)
<> 161:2cc1468da177 13050 #define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13051 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
<> 161:2cc1468da177 13052 #define SDMMC_CMD_WAITPEND_Pos (9U)
<> 161:2cc1468da177 13053 #define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 13054 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
<> 161:2cc1468da177 13055 #define SDMMC_CMD_CPSMEN_Pos (10U)
<> 161:2cc1468da177 13056 #define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13057 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
<> 161:2cc1468da177 13058 #define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
<> 161:2cc1468da177 13059 #define SDMMC_CMD_SDIOSUSPEND_Msk (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 13060 #define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
<> 144:ef7eb2e8f9f7 13061
<> 144:ef7eb2e8f9f7 13062 /***************** Bit definition for SDMMC_RESPCMD register *****************/
<> 161:2cc1468da177 13063 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
<> 161:2cc1468da177 13064 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
<> 161:2cc1468da177 13065 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
<> 144:ef7eb2e8f9f7 13066
<> 144:ef7eb2e8f9f7 13067 /****************** Bit definition for SDMMC_RESP0 register ******************/
<> 161:2cc1468da177 13068 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
<> 161:2cc1468da177 13069 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 13070 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
<> 144:ef7eb2e8f9f7 13071
<> 144:ef7eb2e8f9f7 13072 /****************** Bit definition for SDMMC_RESP1 register ******************/
<> 161:2cc1468da177 13073 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
<> 161:2cc1468da177 13074 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 13075 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
<> 144:ef7eb2e8f9f7 13076
<> 144:ef7eb2e8f9f7 13077 /****************** Bit definition for SDMMC_RESP2 register ******************/
<> 161:2cc1468da177 13078 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
<> 161:2cc1468da177 13079 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 13080 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
<> 144:ef7eb2e8f9f7 13081
<> 144:ef7eb2e8f9f7 13082 /****************** Bit definition for SDMMC_RESP3 register ******************/
<> 161:2cc1468da177 13083 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
<> 161:2cc1468da177 13084 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 13085 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
<> 144:ef7eb2e8f9f7 13086
<> 144:ef7eb2e8f9f7 13087 /****************** Bit definition for SDMMC_RESP4 register ******************/
<> 161:2cc1468da177 13088 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
<> 161:2cc1468da177 13089 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 13090 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
<> 144:ef7eb2e8f9f7 13091
<> 144:ef7eb2e8f9f7 13092 /****************** Bit definition for SDMMC_DTIMER register *****************/
<> 161:2cc1468da177 13093 #define SDMMC_DTIMER_DATATIME_Pos (0U)
<> 161:2cc1468da177 13094 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 13095 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
<> 144:ef7eb2e8f9f7 13096
<> 144:ef7eb2e8f9f7 13097 /****************** Bit definition for SDMMC_DLEN register *******************/
<> 161:2cc1468da177 13098 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
<> 161:2cc1468da177 13099 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
<> 161:2cc1468da177 13100 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
<> 144:ef7eb2e8f9f7 13101
<> 144:ef7eb2e8f9f7 13102 /****************** Bit definition for SDMMC_DCTRL register ******************/
<> 161:2cc1468da177 13103 #define SDMMC_DCTRL_DTEN_Pos (0U)
<> 161:2cc1468da177 13104 #define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13105 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
<> 161:2cc1468da177 13106 #define SDMMC_DCTRL_DTDIR_Pos (1U)
<> 161:2cc1468da177 13107 #define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13108 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
<> 161:2cc1468da177 13109 #define SDMMC_DCTRL_DTMODE_Pos (2U)
<> 161:2cc1468da177 13110 #define SDMMC_DCTRL_DTMODE_Msk (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13111 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
<> 161:2cc1468da177 13112 #define SDMMC_DCTRL_DMAEN_Pos (3U)
<> 161:2cc1468da177 13113 #define SDMMC_DCTRL_DMAEN_Msk (0x1U << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13114 #define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
<> 161:2cc1468da177 13115
<> 161:2cc1468da177 13116 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
<> 161:2cc1468da177 13117 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 13118 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
<> 161:2cc1468da177 13119 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
<> 161:2cc1468da177 13120 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
<> 161:2cc1468da177 13121 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
<> 161:2cc1468da177 13122 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
<> 161:2cc1468da177 13123
<> 161:2cc1468da177 13124 #define SDMMC_DCTRL_RWSTART_Pos (8U)
<> 161:2cc1468da177 13125 #define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13126 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
<> 161:2cc1468da177 13127 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
<> 161:2cc1468da177 13128 #define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 13129 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
<> 161:2cc1468da177 13130 #define SDMMC_DCTRL_RWMOD_Pos (10U)
<> 161:2cc1468da177 13131 #define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13132 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
<> 161:2cc1468da177 13133 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
<> 161:2cc1468da177 13134 #define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 13135 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
<> 144:ef7eb2e8f9f7 13136
<> 144:ef7eb2e8f9f7 13137 /****************** Bit definition for SDMMC_DCOUNT register *****************/
<> 161:2cc1468da177 13138 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
<> 161:2cc1468da177 13139 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
<> 161:2cc1468da177 13140 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
<> 144:ef7eb2e8f9f7 13141
<> 144:ef7eb2e8f9f7 13142 /****************** Bit definition for SDMMC_STA registe ********************/
<> 161:2cc1468da177 13143 #define SDMMC_STA_CCRCFAIL_Pos (0U)
<> 161:2cc1468da177 13144 #define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13145 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
<> 161:2cc1468da177 13146 #define SDMMC_STA_DCRCFAIL_Pos (1U)
<> 161:2cc1468da177 13147 #define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13148 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
<> 161:2cc1468da177 13149 #define SDMMC_STA_CTIMEOUT_Pos (2U)
<> 161:2cc1468da177 13150 #define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13151 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
<> 161:2cc1468da177 13152 #define SDMMC_STA_DTIMEOUT_Pos (3U)
<> 161:2cc1468da177 13153 #define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13154 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
<> 161:2cc1468da177 13155 #define SDMMC_STA_TXUNDERR_Pos (4U)
<> 161:2cc1468da177 13156 #define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 13157 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
<> 161:2cc1468da177 13158 #define SDMMC_STA_RXOVERR_Pos (5U)
<> 161:2cc1468da177 13159 #define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 13160 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
<> 161:2cc1468da177 13161 #define SDMMC_STA_CMDREND_Pos (6U)
<> 161:2cc1468da177 13162 #define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 13163 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
<> 161:2cc1468da177 13164 #define SDMMC_STA_CMDSENT_Pos (7U)
<> 161:2cc1468da177 13165 #define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 13166 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
<> 161:2cc1468da177 13167 #define SDMMC_STA_DATAEND_Pos (8U)
<> 161:2cc1468da177 13168 #define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13169 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
<> 161:2cc1468da177 13170 #define SDMMC_STA_DBCKEND_Pos (10U)
<> 161:2cc1468da177 13171 #define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13172 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
<> 161:2cc1468da177 13173 #define SDMMC_STA_CMDACT_Pos (11U)
<> 161:2cc1468da177 13174 #define SDMMC_STA_CMDACT_Msk (0x1U << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 13175 #define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
<> 161:2cc1468da177 13176 #define SDMMC_STA_TXACT_Pos (12U)
<> 161:2cc1468da177 13177 #define SDMMC_STA_TXACT_Msk (0x1U << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 13178 #define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
<> 161:2cc1468da177 13179 #define SDMMC_STA_RXACT_Pos (13U)
<> 161:2cc1468da177 13180 #define SDMMC_STA_RXACT_Msk (0x1U << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 13181 #define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
<> 161:2cc1468da177 13182 #define SDMMC_STA_TXFIFOHE_Pos (14U)
<> 161:2cc1468da177 13183 #define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 13184 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
<> 161:2cc1468da177 13185 #define SDMMC_STA_RXFIFOHF_Pos (15U)
<> 161:2cc1468da177 13186 #define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 13187 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
<> 161:2cc1468da177 13188 #define SDMMC_STA_TXFIFOF_Pos (16U)
<> 161:2cc1468da177 13189 #define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 13190 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
<> 161:2cc1468da177 13191 #define SDMMC_STA_RXFIFOF_Pos (17U)
<> 161:2cc1468da177 13192 #define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 13193 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
<> 161:2cc1468da177 13194 #define SDMMC_STA_TXFIFOE_Pos (18U)
<> 161:2cc1468da177 13195 #define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 13196 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
<> 161:2cc1468da177 13197 #define SDMMC_STA_RXFIFOE_Pos (19U)
<> 161:2cc1468da177 13198 #define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 13199 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
<> 161:2cc1468da177 13200 #define SDMMC_STA_TXDAVL_Pos (20U)
<> 161:2cc1468da177 13201 #define SDMMC_STA_TXDAVL_Msk (0x1U << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 13202 #define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
<> 161:2cc1468da177 13203 #define SDMMC_STA_RXDAVL_Pos (21U)
<> 161:2cc1468da177 13204 #define SDMMC_STA_RXDAVL_Msk (0x1U << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 13205 #define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
<> 161:2cc1468da177 13206 #define SDMMC_STA_SDIOIT_Pos (22U)
<> 161:2cc1468da177 13207 #define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 13208 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDMMC interrupt received */
<> 144:ef7eb2e8f9f7 13209
<> 144:ef7eb2e8f9f7 13210 /******************* Bit definition for SDMMC_ICR register *******************/
<> 161:2cc1468da177 13211 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
<> 161:2cc1468da177 13212 #define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13213 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
<> 161:2cc1468da177 13214 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
<> 161:2cc1468da177 13215 #define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13216 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
<> 161:2cc1468da177 13217 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
<> 161:2cc1468da177 13218 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13219 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
<> 161:2cc1468da177 13220 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
<> 161:2cc1468da177 13221 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13222 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
<> 161:2cc1468da177 13223 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
<> 161:2cc1468da177 13224 #define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 13225 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
<> 161:2cc1468da177 13226 #define SDMMC_ICR_RXOVERRC_Pos (5U)
<> 161:2cc1468da177 13227 #define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 13228 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
<> 161:2cc1468da177 13229 #define SDMMC_ICR_CMDRENDC_Pos (6U)
<> 161:2cc1468da177 13230 #define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 13231 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
<> 161:2cc1468da177 13232 #define SDMMC_ICR_CMDSENTC_Pos (7U)
<> 161:2cc1468da177 13233 #define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 13234 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
<> 161:2cc1468da177 13235 #define SDMMC_ICR_DATAENDC_Pos (8U)
<> 161:2cc1468da177 13236 #define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13237 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
<> 161:2cc1468da177 13238 #define SDMMC_ICR_DBCKENDC_Pos (10U)
<> 161:2cc1468da177 13239 #define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13240 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
<> 161:2cc1468da177 13241 #define SDMMC_ICR_SDIOITC_Pos (22U)
<> 161:2cc1468da177 13242 #define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 13243 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDMMCIT flag clear bit */
<> 144:ef7eb2e8f9f7 13244
<> 144:ef7eb2e8f9f7 13245 /****************** Bit definition for SDMMC_MASK register *******************/
<> 161:2cc1468da177 13246 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
<> 161:2cc1468da177 13247 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13248 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
<> 161:2cc1468da177 13249 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
<> 161:2cc1468da177 13250 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13251 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
<> 161:2cc1468da177 13252 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
<> 161:2cc1468da177 13253 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13254 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
<> 161:2cc1468da177 13255 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
<> 161:2cc1468da177 13256 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13257 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
<> 161:2cc1468da177 13258 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
<> 161:2cc1468da177 13259 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 13260 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
<> 161:2cc1468da177 13261 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
<> 161:2cc1468da177 13262 #define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 13263 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
<> 161:2cc1468da177 13264 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
<> 161:2cc1468da177 13265 #define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 13266 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
<> 161:2cc1468da177 13267 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
<> 161:2cc1468da177 13268 #define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 13269 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
<> 161:2cc1468da177 13270 #define SDMMC_MASK_DATAENDIE_Pos (8U)
<> 161:2cc1468da177 13271 #define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13272 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
<> 161:2cc1468da177 13273 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
<> 161:2cc1468da177 13274 #define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13275 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
<> 161:2cc1468da177 13276 #define SDMMC_MASK_CMDACTIE_Pos (11U)
<> 161:2cc1468da177 13277 #define SDMMC_MASK_CMDACTIE_Msk (0x1U << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 13278 #define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
<> 161:2cc1468da177 13279 #define SDMMC_MASK_TXACTIE_Pos (12U)
<> 161:2cc1468da177 13280 #define SDMMC_MASK_TXACTIE_Msk (0x1U << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 13281 #define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
<> 161:2cc1468da177 13282 #define SDMMC_MASK_RXACTIE_Pos (13U)
<> 161:2cc1468da177 13283 #define SDMMC_MASK_RXACTIE_Msk (0x1U << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 13284 #define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
<> 161:2cc1468da177 13285 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
<> 161:2cc1468da177 13286 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 13287 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
<> 161:2cc1468da177 13288 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
<> 161:2cc1468da177 13289 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 13290 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
<> 161:2cc1468da177 13291 #define SDMMC_MASK_TXFIFOFIE_Pos (16U)
<> 161:2cc1468da177 13292 #define SDMMC_MASK_TXFIFOFIE_Msk (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 13293 #define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
<> 161:2cc1468da177 13294 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
<> 161:2cc1468da177 13295 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 13296 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
<> 161:2cc1468da177 13297 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
<> 161:2cc1468da177 13298 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 13299 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
<> 161:2cc1468da177 13300 #define SDMMC_MASK_RXFIFOEIE_Pos (19U)
<> 161:2cc1468da177 13301 #define SDMMC_MASK_RXFIFOEIE_Msk (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 13302 #define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
<> 161:2cc1468da177 13303 #define SDMMC_MASK_TXDAVLIE_Pos (20U)
<> 161:2cc1468da177 13304 #define SDMMC_MASK_TXDAVLIE_Msk (0x1U << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 13305 #define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
<> 161:2cc1468da177 13306 #define SDMMC_MASK_RXDAVLIE_Pos (21U)
<> 161:2cc1468da177 13307 #define SDMMC_MASK_RXDAVLIE_Msk (0x1U << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 13308 #define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
<> 161:2cc1468da177 13309 #define SDMMC_MASK_SDIOITIE_Pos (22U)
<> 161:2cc1468da177 13310 #define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 13311 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
<> 144:ef7eb2e8f9f7 13312
<> 144:ef7eb2e8f9f7 13313 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
<> 161:2cc1468da177 13314 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
<> 161:2cc1468da177 13315 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
<> 161:2cc1468da177 13316 #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
<> 144:ef7eb2e8f9f7 13317
<> 144:ef7eb2e8f9f7 13318 /****************** Bit definition for SDMMC_FIFO register *******************/
<> 161:2cc1468da177 13319 #define SDMMC_FIFO_FIFODATA_Pos (0U)
<> 161:2cc1468da177 13320 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 13321 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
<> 144:ef7eb2e8f9f7 13322
<> 144:ef7eb2e8f9f7 13323 /******************************************************************************/
<> 144:ef7eb2e8f9f7 13324 /* */
<> 144:ef7eb2e8f9f7 13325 /* Serial Peripheral Interface (SPI) */
<> 144:ef7eb2e8f9f7 13326 /* */
<> 144:ef7eb2e8f9f7 13327 /******************************************************************************/
<> 144:ef7eb2e8f9f7 13328 /******************* Bit definition for SPI_CR1 register ********************/
<> 161:2cc1468da177 13329 #define SPI_CR1_CPHA_Pos (0U)
<> 161:2cc1468da177 13330 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13331 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
<> 161:2cc1468da177 13332 #define SPI_CR1_CPOL_Pos (1U)
<> 161:2cc1468da177 13333 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13334 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
<> 161:2cc1468da177 13335 #define SPI_CR1_MSTR_Pos (2U)
<> 161:2cc1468da177 13336 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13337 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
<> 161:2cc1468da177 13338 #define SPI_CR1_BR_Pos (3U)
<> 161:2cc1468da177 13339 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
<> 161:2cc1468da177 13340 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
<> 161:2cc1468da177 13341 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13342 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 13343 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 13344 #define SPI_CR1_SPE_Pos (6U)
<> 161:2cc1468da177 13345 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 13346 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
<> 161:2cc1468da177 13347 #define SPI_CR1_LSBFIRST_Pos (7U)
<> 161:2cc1468da177 13348 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 13349 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
<> 161:2cc1468da177 13350 #define SPI_CR1_SSI_Pos (8U)
<> 161:2cc1468da177 13351 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13352 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
<> 161:2cc1468da177 13353 #define SPI_CR1_SSM_Pos (9U)
<> 161:2cc1468da177 13354 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 13355 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
<> 161:2cc1468da177 13356 #define SPI_CR1_RXONLY_Pos (10U)
<> 161:2cc1468da177 13357 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13358 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
<> 161:2cc1468da177 13359 #define SPI_CR1_CRCL_Pos (11U)
<> 161:2cc1468da177 13360 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 13361 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
<> 161:2cc1468da177 13362 #define SPI_CR1_CRCNEXT_Pos (12U)
<> 161:2cc1468da177 13363 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 13364 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
<> 161:2cc1468da177 13365 #define SPI_CR1_CRCEN_Pos (13U)
<> 161:2cc1468da177 13366 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 13367 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
<> 161:2cc1468da177 13368 #define SPI_CR1_BIDIOE_Pos (14U)
<> 161:2cc1468da177 13369 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 13370 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
<> 161:2cc1468da177 13371 #define SPI_CR1_BIDIMODE_Pos (15U)
<> 161:2cc1468da177 13372 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 13373 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
<> 144:ef7eb2e8f9f7 13374
<> 144:ef7eb2e8f9f7 13375 /******************* Bit definition for SPI_CR2 register ********************/
<> 161:2cc1468da177 13376 #define SPI_CR2_RXDMAEN_Pos (0U)
<> 161:2cc1468da177 13377 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13378 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
<> 161:2cc1468da177 13379 #define SPI_CR2_TXDMAEN_Pos (1U)
<> 161:2cc1468da177 13380 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13381 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
<> 161:2cc1468da177 13382 #define SPI_CR2_SSOE_Pos (2U)
<> 161:2cc1468da177 13383 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13384 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
<> 161:2cc1468da177 13385 #define SPI_CR2_NSSP_Pos (3U)
<> 161:2cc1468da177 13386 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13387 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
<> 161:2cc1468da177 13388 #define SPI_CR2_FRF_Pos (4U)
<> 161:2cc1468da177 13389 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 13390 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
<> 161:2cc1468da177 13391 #define SPI_CR2_ERRIE_Pos (5U)
<> 161:2cc1468da177 13392 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 13393 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
<> 161:2cc1468da177 13394 #define SPI_CR2_RXNEIE_Pos (6U)
<> 161:2cc1468da177 13395 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 13396 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
<> 161:2cc1468da177 13397 #define SPI_CR2_TXEIE_Pos (7U)
<> 161:2cc1468da177 13398 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 13399 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
<> 161:2cc1468da177 13400 #define SPI_CR2_DS_Pos (8U)
<> 161:2cc1468da177 13401 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 13402 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
<> 161:2cc1468da177 13403 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13404 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 13405 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13406 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 13407 #define SPI_CR2_FRXTH_Pos (12U)
<> 161:2cc1468da177 13408 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 13409 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
<> 161:2cc1468da177 13410 #define SPI_CR2_LDMARX_Pos (13U)
<> 161:2cc1468da177 13411 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 13412 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
<> 161:2cc1468da177 13413 #define SPI_CR2_LDMATX_Pos (14U)
<> 161:2cc1468da177 13414 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 13415 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
<> 144:ef7eb2e8f9f7 13416
<> 144:ef7eb2e8f9f7 13417 /******************** Bit definition for SPI_SR register ********************/
<> 161:2cc1468da177 13418 #define SPI_SR_RXNE_Pos (0U)
<> 161:2cc1468da177 13419 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13420 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
<> 161:2cc1468da177 13421 #define SPI_SR_TXE_Pos (1U)
<> 161:2cc1468da177 13422 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13423 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
<> 161:2cc1468da177 13424 #define SPI_SR_CHSIDE_Pos (2U)
<> 161:2cc1468da177 13425 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13426 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
<> 161:2cc1468da177 13427 #define SPI_SR_UDR_Pos (3U)
<> 161:2cc1468da177 13428 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13429 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
<> 161:2cc1468da177 13430 #define SPI_SR_CRCERR_Pos (4U)
<> 161:2cc1468da177 13431 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 13432 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
<> 161:2cc1468da177 13433 #define SPI_SR_MODF_Pos (5U)
<> 161:2cc1468da177 13434 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 13435 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
<> 161:2cc1468da177 13436 #define SPI_SR_OVR_Pos (6U)
<> 161:2cc1468da177 13437 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 13438 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
<> 161:2cc1468da177 13439 #define SPI_SR_BSY_Pos (7U)
<> 161:2cc1468da177 13440 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 13441 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
<> 161:2cc1468da177 13442 #define SPI_SR_FRE_Pos (8U)
<> 161:2cc1468da177 13443 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13444 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
<> 161:2cc1468da177 13445 #define SPI_SR_FRLVL_Pos (9U)
<> 161:2cc1468da177 13446 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
<> 161:2cc1468da177 13447 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
<> 161:2cc1468da177 13448 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 13449 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13450 #define SPI_SR_FTLVL_Pos (11U)
<> 161:2cc1468da177 13451 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
<> 161:2cc1468da177 13452 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
<> 161:2cc1468da177 13453 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 13454 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 13455
<> 144:ef7eb2e8f9f7 13456 /******************** Bit definition for SPI_DR register ********************/
<> 161:2cc1468da177 13457 #define SPI_DR_DR_Pos (0U)
<> 161:2cc1468da177 13458 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 13459 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
<> 144:ef7eb2e8f9f7 13460
<> 144:ef7eb2e8f9f7 13461 /******************* Bit definition for SPI_CRCPR register ******************/
<> 161:2cc1468da177 13462 #define SPI_CRCPR_CRCPOLY_Pos (0U)
<> 161:2cc1468da177 13463 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 13464 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
<> 144:ef7eb2e8f9f7 13465
<> 144:ef7eb2e8f9f7 13466 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 161:2cc1468da177 13467 #define SPI_RXCRCR_RXCRC_Pos (0U)
<> 161:2cc1468da177 13468 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 13469 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
<> 144:ef7eb2e8f9f7 13470
<> 144:ef7eb2e8f9f7 13471 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 161:2cc1468da177 13472 #define SPI_TXCRCR_TXCRC_Pos (0U)
<> 161:2cc1468da177 13473 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 13474 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
<> 144:ef7eb2e8f9f7 13475
<> 144:ef7eb2e8f9f7 13476 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 161:2cc1468da177 13477 #define SPI_I2SCFGR_CHLEN_Pos (0U)
<> 161:2cc1468da177 13478 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13479 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
<> 161:2cc1468da177 13480 #define SPI_I2SCFGR_DATLEN_Pos (1U)
<> 161:2cc1468da177 13481 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
<> 161:2cc1468da177 13482 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 161:2cc1468da177 13483 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13484 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13485 #define SPI_I2SCFGR_CKPOL_Pos (3U)
<> 161:2cc1468da177 13486 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13487 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
<> 161:2cc1468da177 13488 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
<> 161:2cc1468da177 13489 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 13490 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 161:2cc1468da177 13491 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 13492 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 13493 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
<> 161:2cc1468da177 13494 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 13495 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
<> 161:2cc1468da177 13496 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
<> 161:2cc1468da177 13497 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 13498 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 161:2cc1468da177 13499 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13500 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 13501 #define SPI_I2SCFGR_I2SE_Pos (10U)
<> 161:2cc1468da177 13502 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13503 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
<> 161:2cc1468da177 13504 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
<> 161:2cc1468da177 13505 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 13506 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
<> 161:2cc1468da177 13507 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
<> 161:2cc1468da177 13508 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 13509 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
<> 144:ef7eb2e8f9f7 13510
<> 144:ef7eb2e8f9f7 13511 /****************** Bit definition for SPI_I2SPR register *******************/
<> 161:2cc1468da177 13512 #define SPI_I2SPR_I2SDIV_Pos (0U)
<> 161:2cc1468da177 13513 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 13514 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
<> 161:2cc1468da177 13515 #define SPI_I2SPR_ODD_Pos (8U)
<> 161:2cc1468da177 13516 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13517 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
<> 161:2cc1468da177 13518 #define SPI_I2SPR_MCKOE_Pos (9U)
<> 161:2cc1468da177 13519 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 13520 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
<> 144:ef7eb2e8f9f7 13521
<> 144:ef7eb2e8f9f7 13522
<> 144:ef7eb2e8f9f7 13523 /******************************************************************************/
<> 144:ef7eb2e8f9f7 13524 /* */
<> 144:ef7eb2e8f9f7 13525 /* SYSCFG */
<> 144:ef7eb2e8f9f7 13526 /* */
<> 144:ef7eb2e8f9f7 13527 /******************************************************************************/
<> 161:2cc1468da177 13528 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
<> 161:2cc1468da177 13529 #define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U)
<> 161:2cc1468da177 13530 #define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1U << SYSCFG_MEMRMP_MEM_BOOT_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13531 #define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk /*!< Boot information after Reset */
<> 161:2cc1468da177 13532
<> 161:2cc1468da177 13533 #define SYSCFG_MEMRMP_SWP_FB_Pos (8U)
<> 161:2cc1468da177 13534 #define SYSCFG_MEMRMP_SWP_FB_Msk (0x1U << SYSCFG_MEMRMP_SWP_FB_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13535 #define SYSCFG_MEMRMP_SWP_FB SYSCFG_MEMRMP_SWP_FB_Msk /*!< User Flash Bank swap */
<> 161:2cc1468da177 13536
<> 161:2cc1468da177 13537 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
<> 161:2cc1468da177 13538 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 13539 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC Memory Mapping swapping */
<> 161:2cc1468da177 13540 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13541 #define SYSCFG_MEMRMP_SWP_FMC_1 (0x2U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
<> 144:ef7eb2e8f9f7 13542
<> 144:ef7eb2e8f9f7 13543 /****************** Bit definition for SYSCFG_PMC register ******************/
<> 161:2cc1468da177 13544 #define SYSCFG_PMC_I2C1_FMP_Pos (0U)
<> 161:2cc1468da177 13545 #define SYSCFG_PMC_I2C1_FMP_Msk (0x1U << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13546 #define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
<> 161:2cc1468da177 13547 #define SYSCFG_PMC_I2C2_FMP_Pos (1U)
<> 161:2cc1468da177 13548 #define SYSCFG_PMC_I2C2_FMP_Msk (0x1U << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13549 #define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
<> 161:2cc1468da177 13550 #define SYSCFG_PMC_I2C3_FMP_Pos (2U)
<> 161:2cc1468da177 13551 #define SYSCFG_PMC_I2C3_FMP_Msk (0x1U << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13552 #define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
<> 161:2cc1468da177 13553 #define SYSCFG_PMC_I2C4_FMP_Pos (3U)
<> 161:2cc1468da177 13554 #define SYSCFG_PMC_I2C4_FMP_Msk (0x1U << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13555 #define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
<> 161:2cc1468da177 13556 #define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
<> 161:2cc1468da177 13557 #define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 13558 #define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
<> 161:2cc1468da177 13559 #define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
<> 161:2cc1468da177 13560 #define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 13561 #define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
<> 161:2cc1468da177 13562 #define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
<> 161:2cc1468da177 13563 #define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 13564 #define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
<> 161:2cc1468da177 13565 #define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
<> 161:2cc1468da177 13566 #define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 13567 #define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
<> 161:2cc1468da177 13568
<> 161:2cc1468da177 13569 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
<> 161:2cc1468da177 13570 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
<> 161:2cc1468da177 13571 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
<> 161:2cc1468da177 13572 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
<> 161:2cc1468da177 13573 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 13574 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
<> 161:2cc1468da177 13575 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
<> 161:2cc1468da177 13576 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 13577 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
<> 161:2cc1468da177 13578 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
<> 161:2cc1468da177 13579 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 13580 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
<> 161:2cc1468da177 13581
<> 161:2cc1468da177 13582 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
<> 161:2cc1468da177 13583 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 13584 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
<> 144:ef7eb2e8f9f7 13585
<> 144:ef7eb2e8f9f7 13586 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 161:2cc1468da177 13587 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
<> 161:2cc1468da177 13588 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 13589 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
<> 161:2cc1468da177 13590 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
<> 161:2cc1468da177 13591 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 13592 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
<> 161:2cc1468da177 13593 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
<> 161:2cc1468da177 13594 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 13595 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
<> 161:2cc1468da177 13596 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
<> 161:2cc1468da177 13597 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 13598 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
<> 161:2cc1468da177 13599 /**
<> 161:2cc1468da177 13600 * @brief EXTI0 configuration
<> 161:2cc1468da177 13601 */
<> 161:2cc1468da177 13602 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
<> 161:2cc1468da177 13603 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
<> 161:2cc1468da177 13604 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
<> 161:2cc1468da177 13605 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
<> 161:2cc1468da177 13606 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
<> 161:2cc1468da177 13607 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
<> 161:2cc1468da177 13608 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
<> 161:2cc1468da177 13609 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
<> 161:2cc1468da177 13610 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
<> 161:2cc1468da177 13611 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
<> 161:2cc1468da177 13612 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
<> 161:2cc1468da177 13613
<> 161:2cc1468da177 13614 /**
<> 161:2cc1468da177 13615 * @brief EXTI1 configuration
<> 161:2cc1468da177 13616 */
<> 161:2cc1468da177 13617 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
<> 161:2cc1468da177 13618 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
<> 161:2cc1468da177 13619 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
<> 161:2cc1468da177 13620 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
<> 161:2cc1468da177 13621 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
<> 161:2cc1468da177 13622 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
<> 161:2cc1468da177 13623 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
<> 161:2cc1468da177 13624 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
<> 161:2cc1468da177 13625 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
<> 161:2cc1468da177 13626 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
<> 161:2cc1468da177 13627 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
<> 161:2cc1468da177 13628
<> 161:2cc1468da177 13629 /**
<> 161:2cc1468da177 13630 * @brief EXTI2 configuration
<> 161:2cc1468da177 13631 */
<> 161:2cc1468da177 13632 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
<> 161:2cc1468da177 13633 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
<> 161:2cc1468da177 13634 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
<> 161:2cc1468da177 13635 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
<> 161:2cc1468da177 13636 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
<> 161:2cc1468da177 13637 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
<> 161:2cc1468da177 13638 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
<> 161:2cc1468da177 13639 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
<> 161:2cc1468da177 13640 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
<> 161:2cc1468da177 13641 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
<> 161:2cc1468da177 13642 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
<> 161:2cc1468da177 13643
<> 161:2cc1468da177 13644 /**
<> 161:2cc1468da177 13645 * @brief EXTI3 configuration
<> 161:2cc1468da177 13646 */
<> 161:2cc1468da177 13647 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
<> 161:2cc1468da177 13648 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
<> 161:2cc1468da177 13649 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
<> 161:2cc1468da177 13650 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
<> 161:2cc1468da177 13651 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
<> 161:2cc1468da177 13652 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
<> 161:2cc1468da177 13653 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
<> 161:2cc1468da177 13654 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
<> 161:2cc1468da177 13655 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
<> 161:2cc1468da177 13656 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
<> 161:2cc1468da177 13657 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
<> 144:ef7eb2e8f9f7 13658
<> 144:ef7eb2e8f9f7 13659 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
<> 161:2cc1468da177 13660 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
<> 161:2cc1468da177 13661 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 13662 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
<> 161:2cc1468da177 13663 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
<> 161:2cc1468da177 13664 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 13665 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
<> 161:2cc1468da177 13666 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
<> 161:2cc1468da177 13667 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 13668 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
<> 161:2cc1468da177 13669 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
<> 161:2cc1468da177 13670 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 13671 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
<> 161:2cc1468da177 13672 /**
<> 161:2cc1468da177 13673 * @brief EXTI4 configuration
<> 161:2cc1468da177 13674 */
<> 161:2cc1468da177 13675 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
<> 161:2cc1468da177 13676 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
<> 161:2cc1468da177 13677 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
<> 161:2cc1468da177 13678 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
<> 161:2cc1468da177 13679 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
<> 161:2cc1468da177 13680 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
<> 161:2cc1468da177 13681 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
<> 161:2cc1468da177 13682 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
<> 161:2cc1468da177 13683 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
<> 161:2cc1468da177 13684 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
<> 161:2cc1468da177 13685 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
<> 161:2cc1468da177 13686
<> 161:2cc1468da177 13687 /**
<> 161:2cc1468da177 13688 * @brief EXTI5 configuration
<> 161:2cc1468da177 13689 */
<> 161:2cc1468da177 13690 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
<> 161:2cc1468da177 13691 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
<> 161:2cc1468da177 13692 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
<> 161:2cc1468da177 13693 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
<> 161:2cc1468da177 13694 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
<> 161:2cc1468da177 13695 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
<> 161:2cc1468da177 13696 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
<> 161:2cc1468da177 13697 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
<> 161:2cc1468da177 13698 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
<> 161:2cc1468da177 13699 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
<> 161:2cc1468da177 13700 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
<> 161:2cc1468da177 13701
<> 161:2cc1468da177 13702 /**
<> 161:2cc1468da177 13703 * @brief EXTI6 configuration
<> 161:2cc1468da177 13704 */
<> 161:2cc1468da177 13705 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
<> 161:2cc1468da177 13706 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
<> 161:2cc1468da177 13707 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
<> 161:2cc1468da177 13708 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
<> 161:2cc1468da177 13709 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
<> 161:2cc1468da177 13710 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
<> 161:2cc1468da177 13711 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
<> 161:2cc1468da177 13712 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
<> 161:2cc1468da177 13713 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
<> 161:2cc1468da177 13714 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
<> 161:2cc1468da177 13715 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
<> 161:2cc1468da177 13716
<> 161:2cc1468da177 13717 /**
<> 161:2cc1468da177 13718 * @brief EXTI7 configuration
<> 161:2cc1468da177 13719 */
<> 161:2cc1468da177 13720 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
<> 161:2cc1468da177 13721 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
<> 161:2cc1468da177 13722 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
<> 161:2cc1468da177 13723 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
<> 161:2cc1468da177 13724 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
<> 161:2cc1468da177 13725 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
<> 161:2cc1468da177 13726 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
<> 161:2cc1468da177 13727 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
<> 161:2cc1468da177 13728 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
<> 161:2cc1468da177 13729 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
<> 161:2cc1468da177 13730 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
<> 144:ef7eb2e8f9f7 13731
<> 144:ef7eb2e8f9f7 13732 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
<> 161:2cc1468da177 13733 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
<> 161:2cc1468da177 13734 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 13735 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
<> 161:2cc1468da177 13736 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
<> 161:2cc1468da177 13737 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 13738 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
<> 161:2cc1468da177 13739 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
<> 161:2cc1468da177 13740 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 13741 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
<> 161:2cc1468da177 13742 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
<> 161:2cc1468da177 13743 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 13744 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
<> 161:2cc1468da177 13745
<> 161:2cc1468da177 13746 /**
<> 161:2cc1468da177 13747 * @brief EXTI8 configuration
<> 161:2cc1468da177 13748 */
<> 161:2cc1468da177 13749 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
<> 161:2cc1468da177 13750 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
<> 161:2cc1468da177 13751 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
<> 161:2cc1468da177 13752 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
<> 161:2cc1468da177 13753 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
<> 161:2cc1468da177 13754 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
<> 161:2cc1468da177 13755 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
<> 161:2cc1468da177 13756 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
<> 161:2cc1468da177 13757 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
<> 161:2cc1468da177 13758 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
<> 161:2cc1468da177 13759
<> 161:2cc1468da177 13760 /**
<> 161:2cc1468da177 13761 * @brief EXTI9 configuration
<> 161:2cc1468da177 13762 */
<> 161:2cc1468da177 13763 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
<> 161:2cc1468da177 13764 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
<> 161:2cc1468da177 13765 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
<> 161:2cc1468da177 13766 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
<> 161:2cc1468da177 13767 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
<> 161:2cc1468da177 13768 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
<> 161:2cc1468da177 13769 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
<> 161:2cc1468da177 13770 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
<> 161:2cc1468da177 13771 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
<> 161:2cc1468da177 13772 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
<> 161:2cc1468da177 13773
<> 161:2cc1468da177 13774 /**
<> 161:2cc1468da177 13775 * @brief EXTI10 configuration
<> 161:2cc1468da177 13776 */
<> 161:2cc1468da177 13777 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
<> 161:2cc1468da177 13778 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
<> 161:2cc1468da177 13779 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
<> 161:2cc1468da177 13780 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
<> 161:2cc1468da177 13781 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
<> 161:2cc1468da177 13782 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
<> 161:2cc1468da177 13783 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
<> 161:2cc1468da177 13784 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
<> 161:2cc1468da177 13785 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
<> 161:2cc1468da177 13786 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
<> 161:2cc1468da177 13787
<> 161:2cc1468da177 13788 /**
<> 161:2cc1468da177 13789 * @brief EXTI11 configuration
<> 161:2cc1468da177 13790 */
<> 161:2cc1468da177 13791 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
<> 161:2cc1468da177 13792 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
<> 161:2cc1468da177 13793 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
<> 161:2cc1468da177 13794 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
<> 161:2cc1468da177 13795 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
<> 161:2cc1468da177 13796 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
<> 161:2cc1468da177 13797 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
<> 161:2cc1468da177 13798 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
<> 161:2cc1468da177 13799 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
<> 161:2cc1468da177 13800 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
<> 144:ef7eb2e8f9f7 13801
<> 144:ef7eb2e8f9f7 13802
<> 144:ef7eb2e8f9f7 13803 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
<> 161:2cc1468da177 13804 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
<> 161:2cc1468da177 13805 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 13806 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
<> 161:2cc1468da177 13807 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
<> 161:2cc1468da177 13808 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 13809 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
<> 161:2cc1468da177 13810 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
<> 161:2cc1468da177 13811 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 13812 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
<> 161:2cc1468da177 13813 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
<> 161:2cc1468da177 13814 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 13815 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
<> 161:2cc1468da177 13816 /**
<> 161:2cc1468da177 13817 * @brief EXTI12 configuration
<> 161:2cc1468da177 13818 */
<> 161:2cc1468da177 13819 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
<> 161:2cc1468da177 13820 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
<> 161:2cc1468da177 13821 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
<> 161:2cc1468da177 13822 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
<> 161:2cc1468da177 13823 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
<> 161:2cc1468da177 13824 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
<> 161:2cc1468da177 13825 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
<> 161:2cc1468da177 13826 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
<> 161:2cc1468da177 13827 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
<> 161:2cc1468da177 13828 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
<> 161:2cc1468da177 13829
<> 161:2cc1468da177 13830 /**
<> 161:2cc1468da177 13831 * @brief EXTI13 configuration
<> 161:2cc1468da177 13832 */
<> 161:2cc1468da177 13833 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
<> 161:2cc1468da177 13834 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
<> 161:2cc1468da177 13835 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
<> 161:2cc1468da177 13836 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
<> 161:2cc1468da177 13837 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
<> 161:2cc1468da177 13838 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
<> 161:2cc1468da177 13839 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
<> 161:2cc1468da177 13840 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
<> 161:2cc1468da177 13841 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */
<> 161:2cc1468da177 13842 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */
<> 161:2cc1468da177 13843
<> 161:2cc1468da177 13844 /**
<> 161:2cc1468da177 13845 * @brief EXTI14 configuration
<> 161:2cc1468da177 13846 */
<> 161:2cc1468da177 13847 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
<> 161:2cc1468da177 13848 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
<> 161:2cc1468da177 13849 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
<> 161:2cc1468da177 13850 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
<> 161:2cc1468da177 13851 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
<> 161:2cc1468da177 13852 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
<> 161:2cc1468da177 13853 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
<> 161:2cc1468da177 13854 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
<> 161:2cc1468da177 13855 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
<> 161:2cc1468da177 13856 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
<> 161:2cc1468da177 13857
<> 161:2cc1468da177 13858 /**
<> 161:2cc1468da177 13859 * @brief EXTI15 configuration
<> 161:2cc1468da177 13860 */
<> 161:2cc1468da177 13861 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
<> 161:2cc1468da177 13862 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
<> 161:2cc1468da177 13863 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
<> 161:2cc1468da177 13864 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
<> 161:2cc1468da177 13865 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
<> 161:2cc1468da177 13866 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
<> 161:2cc1468da177 13867 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
<> 161:2cc1468da177 13868 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
<> 161:2cc1468da177 13869 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
<> 161:2cc1468da177 13870 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
<> 161:2cc1468da177 13871
<> 161:2cc1468da177 13872 /****************** Bit definition for SYSCFG_CBR register ******************/
<> 161:2cc1468da177 13873 #define SYSCFG_CBR_CLL_Pos (0U)
<> 161:2cc1468da177 13874 #define SYSCFG_CBR_CLL_Msk (0x1U << SYSCFG_CBR_CLL_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13875 #define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!<Core Lockup Lock */
<> 161:2cc1468da177 13876 #define SYSCFG_CBR_PVDL_Pos (2U)
<> 161:2cc1468da177 13877 #define SYSCFG_CBR_PVDL_Msk (0x1U << SYSCFG_CBR_PVDL_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13878 #define SYSCFG_CBR_PVDL SYSCFG_CBR_PVDL_Msk /*!<PVD Lock */
<> 161:2cc1468da177 13879
<> 161:2cc1468da177 13880 /****************** Bit definition for SYSCFG_CMPCR register ****************/
<> 161:2cc1468da177 13881 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
<> 161:2cc1468da177 13882 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13883 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell power-down */
<> 161:2cc1468da177 13884 #define SYSCFG_CMPCR_READY_Pos (8U)
<> 161:2cc1468da177 13885 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13886 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell ready flag */
<> 144:ef7eb2e8f9f7 13887
<> 144:ef7eb2e8f9f7 13888 /******************************************************************************/
<> 144:ef7eb2e8f9f7 13889 /* */
<> 144:ef7eb2e8f9f7 13890 /* TIM */
<> 144:ef7eb2e8f9f7 13891 /* */
<> 144:ef7eb2e8f9f7 13892 /******************************************************************************/
<> 161:2cc1468da177 13893 /*
<> 161:2cc1468da177 13894 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
<> 161:2cc1468da177 13895 */
<> 161:2cc1468da177 13896 #define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature available on specific devices */
<> 144:ef7eb2e8f9f7 13897 /******************* Bit definition for TIM_CR1 register ********************/
<> 161:2cc1468da177 13898 #define TIM_CR1_CEN_Pos (0U)
<> 161:2cc1468da177 13899 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13900 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
<> 161:2cc1468da177 13901 #define TIM_CR1_UDIS_Pos (1U)
<> 161:2cc1468da177 13902 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13903 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
<> 161:2cc1468da177 13904 #define TIM_CR1_URS_Pos (2U)
<> 161:2cc1468da177 13905 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13906 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
<> 161:2cc1468da177 13907 #define TIM_CR1_OPM_Pos (3U)
<> 161:2cc1468da177 13908 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13909 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
<> 161:2cc1468da177 13910 #define TIM_CR1_DIR_Pos (4U)
<> 161:2cc1468da177 13911 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 13912 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
<> 161:2cc1468da177 13913
<> 161:2cc1468da177 13914 #define TIM_CR1_CMS_Pos (5U)
<> 161:2cc1468da177 13915 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
<> 161:2cc1468da177 13916 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 161:2cc1468da177 13917 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
<> 161:2cc1468da177 13918 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
<> 161:2cc1468da177 13919
<> 161:2cc1468da177 13920 #define TIM_CR1_ARPE_Pos (7U)
<> 161:2cc1468da177 13921 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 13922 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
<> 161:2cc1468da177 13923
<> 161:2cc1468da177 13924 #define TIM_CR1_CKD_Pos (8U)
<> 161:2cc1468da177 13925 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 13926 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
<> 161:2cc1468da177 13927 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
<> 161:2cc1468da177 13928 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
<> 161:2cc1468da177 13929 #define TIM_CR1_UIFREMAP_Pos (11U)
<> 161:2cc1468da177 13930 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 13931 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<UIF status bit */
<> 144:ef7eb2e8f9f7 13932
<> 144:ef7eb2e8f9f7 13933 /******************* Bit definition for TIM_CR2 register ********************/
<> 161:2cc1468da177 13934 #define TIM_CR2_CCPC_Pos (0U)
<> 161:2cc1468da177 13935 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13936 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
<> 161:2cc1468da177 13937 #define TIM_CR2_CCUS_Pos (2U)
<> 161:2cc1468da177 13938 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13939 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
<> 161:2cc1468da177 13940 #define TIM_CR2_CCDS_Pos (3U)
<> 161:2cc1468da177 13941 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 13942 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
<> 161:2cc1468da177 13943
<> 161:2cc1468da177 13944 #define TIM_CR2_OIS5_Pos (16U)
<> 161:2cc1468da177 13945 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 13946 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
<> 161:2cc1468da177 13947 #define TIM_CR2_OIS6_Pos (18U)
<> 161:2cc1468da177 13948 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 13949 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
<> 161:2cc1468da177 13950
<> 161:2cc1468da177 13951 #define TIM_CR2_MMS_Pos (4U)
<> 161:2cc1468da177 13952 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
<> 161:2cc1468da177 13953 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
<> 161:2cc1468da177 13954 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
<> 161:2cc1468da177 13955 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
<> 161:2cc1468da177 13956 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
<> 161:2cc1468da177 13957
<> 161:2cc1468da177 13958 #define TIM_CR2_MMS2_Pos (20U)
<> 161:2cc1468da177 13959 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 13960 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
<> 161:2cc1468da177 13961 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 13962 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 13963 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 13964 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 13965
<> 161:2cc1468da177 13966 #define TIM_CR2_TI1S_Pos (7U)
<> 161:2cc1468da177 13967 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 13968 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
<> 161:2cc1468da177 13969 #define TIM_CR2_OIS1_Pos (8U)
<> 161:2cc1468da177 13970 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 13971 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
<> 161:2cc1468da177 13972 #define TIM_CR2_OIS1N_Pos (9U)
<> 161:2cc1468da177 13973 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 13974 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
<> 161:2cc1468da177 13975 #define TIM_CR2_OIS2_Pos (10U)
<> 161:2cc1468da177 13976 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 13977 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
<> 161:2cc1468da177 13978 #define TIM_CR2_OIS2N_Pos (11U)
<> 161:2cc1468da177 13979 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 13980 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
<> 161:2cc1468da177 13981 #define TIM_CR2_OIS3_Pos (12U)
<> 161:2cc1468da177 13982 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 13983 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
<> 161:2cc1468da177 13984 #define TIM_CR2_OIS3N_Pos (13U)
<> 161:2cc1468da177 13985 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 13986 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
<> 161:2cc1468da177 13987 #define TIM_CR2_OIS4_Pos (14U)
<> 161:2cc1468da177 13988 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 13989 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
<> 144:ef7eb2e8f9f7 13990
<> 144:ef7eb2e8f9f7 13991 /******************* Bit definition for TIM_SMCR register *******************/
<> 161:2cc1468da177 13992 #define TIM_SMCR_SMS_Pos (0U)
<> 161:2cc1468da177 13993 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
<> 161:2cc1468da177 13994 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
<> 161:2cc1468da177 13995 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 13996 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 13997 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 13998 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 13999
<> 161:2cc1468da177 14000 #define TIM_SMCR_TS_Pos (4U)
<> 161:2cc1468da177 14001 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
<> 161:2cc1468da177 14002 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
<> 161:2cc1468da177 14003 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
<> 161:2cc1468da177 14004 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
<> 161:2cc1468da177 14005 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
<> 161:2cc1468da177 14006
<> 161:2cc1468da177 14007 #define TIM_SMCR_MSM_Pos (7U)
<> 161:2cc1468da177 14008 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14009 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
<> 161:2cc1468da177 14010
<> 161:2cc1468da177 14011 #define TIM_SMCR_ETF_Pos (8U)
<> 161:2cc1468da177 14012 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 14013 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
<> 161:2cc1468da177 14014 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
<> 161:2cc1468da177 14015 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
<> 161:2cc1468da177 14016 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
<> 161:2cc1468da177 14017 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
<> 161:2cc1468da177 14018
<> 161:2cc1468da177 14019 #define TIM_SMCR_ETPS_Pos (12U)
<> 161:2cc1468da177 14020 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
<> 161:2cc1468da177 14021 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 161:2cc1468da177 14022 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
<> 161:2cc1468da177 14023 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
<> 161:2cc1468da177 14024
<> 161:2cc1468da177 14025 #define TIM_SMCR_ECE_Pos (14U)
<> 161:2cc1468da177 14026 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 14027 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
<> 161:2cc1468da177 14028 #define TIM_SMCR_ETP_Pos (15U)
<> 161:2cc1468da177 14029 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 14030 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
<> 144:ef7eb2e8f9f7 14031
<> 144:ef7eb2e8f9f7 14032 /******************* Bit definition for TIM_DIER register *******************/
<> 161:2cc1468da177 14033 #define TIM_DIER_UIE_Pos (0U)
<> 161:2cc1468da177 14034 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14035 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
<> 161:2cc1468da177 14036 #define TIM_DIER_CC1IE_Pos (1U)
<> 161:2cc1468da177 14037 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14038 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
<> 161:2cc1468da177 14039 #define TIM_DIER_CC2IE_Pos (2U)
<> 161:2cc1468da177 14040 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14041 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
<> 161:2cc1468da177 14042 #define TIM_DIER_CC3IE_Pos (3U)
<> 161:2cc1468da177 14043 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14044 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
<> 161:2cc1468da177 14045 #define TIM_DIER_CC4IE_Pos (4U)
<> 161:2cc1468da177 14046 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14047 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
<> 161:2cc1468da177 14048 #define TIM_DIER_COMIE_Pos (5U)
<> 161:2cc1468da177 14049 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14050 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
<> 161:2cc1468da177 14051 #define TIM_DIER_TIE_Pos (6U)
<> 161:2cc1468da177 14052 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14053 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
<> 161:2cc1468da177 14054 #define TIM_DIER_BIE_Pos (7U)
<> 161:2cc1468da177 14055 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14056 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
<> 161:2cc1468da177 14057 #define TIM_DIER_UDE_Pos (8U)
<> 161:2cc1468da177 14058 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14059 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
<> 161:2cc1468da177 14060 #define TIM_DIER_CC1DE_Pos (9U)
<> 161:2cc1468da177 14061 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14062 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
<> 161:2cc1468da177 14063 #define TIM_DIER_CC2DE_Pos (10U)
<> 161:2cc1468da177 14064 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14065 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
<> 161:2cc1468da177 14066 #define TIM_DIER_CC3DE_Pos (11U)
<> 161:2cc1468da177 14067 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14068 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
<> 161:2cc1468da177 14069 #define TIM_DIER_CC4DE_Pos (12U)
<> 161:2cc1468da177 14070 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 14071 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
<> 161:2cc1468da177 14072 #define TIM_DIER_COMDE_Pos (13U)
<> 161:2cc1468da177 14073 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14074 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
<> 161:2cc1468da177 14075 #define TIM_DIER_TDE_Pos (14U)
<> 161:2cc1468da177 14076 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 14077 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
<> 144:ef7eb2e8f9f7 14078
<> 144:ef7eb2e8f9f7 14079 /******************** Bit definition for TIM_SR register ********************/
<> 161:2cc1468da177 14080 #define TIM_SR_UIF_Pos (0U)
<> 161:2cc1468da177 14081 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14082 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
<> 161:2cc1468da177 14083 #define TIM_SR_CC1IF_Pos (1U)
<> 161:2cc1468da177 14084 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14085 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
<> 161:2cc1468da177 14086 #define TIM_SR_CC2IF_Pos (2U)
<> 161:2cc1468da177 14087 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14088 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
<> 161:2cc1468da177 14089 #define TIM_SR_CC3IF_Pos (3U)
<> 161:2cc1468da177 14090 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14091 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
<> 161:2cc1468da177 14092 #define TIM_SR_CC4IF_Pos (4U)
<> 161:2cc1468da177 14093 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14094 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
<> 161:2cc1468da177 14095 #define TIM_SR_COMIF_Pos (5U)
<> 161:2cc1468da177 14096 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14097 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
<> 161:2cc1468da177 14098 #define TIM_SR_TIF_Pos (6U)
<> 161:2cc1468da177 14099 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14100 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
<> 161:2cc1468da177 14101 #define TIM_SR_BIF_Pos (7U)
<> 161:2cc1468da177 14102 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14103 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
<> 161:2cc1468da177 14104 #define TIM_SR_B2IF_Pos (8U)
<> 161:2cc1468da177 14105 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14106 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
<> 161:2cc1468da177 14107 #define TIM_SR_CC1OF_Pos (9U)
<> 161:2cc1468da177 14108 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14109 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
<> 161:2cc1468da177 14110 #define TIM_SR_CC2OF_Pos (10U)
<> 161:2cc1468da177 14111 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14112 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
<> 161:2cc1468da177 14113 #define TIM_SR_CC3OF_Pos (11U)
<> 161:2cc1468da177 14114 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14115 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
<> 161:2cc1468da177 14116 #define TIM_SR_CC4OF_Pos (12U)
<> 161:2cc1468da177 14117 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 14118 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
<> 161:2cc1468da177 14119 #define TIM_SR_SBIF_Pos (13U)
<> 161:2cc1468da177 14120 #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14121 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
<> 161:2cc1468da177 14122 #define TIM_SR_CC5IF_Pos (16U)
<> 161:2cc1468da177 14123 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 14124 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
<> 161:2cc1468da177 14125 #define TIM_SR_CC6IF_Pos (17U)
<> 161:2cc1468da177 14126 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 14127 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
<> 144:ef7eb2e8f9f7 14128
<> 144:ef7eb2e8f9f7 14129 /******************* Bit definition for TIM_EGR register ********************/
<> 161:2cc1468da177 14130 #define TIM_EGR_UG_Pos (0U)
<> 161:2cc1468da177 14131 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14132 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
<> 161:2cc1468da177 14133 #define TIM_EGR_CC1G_Pos (1U)
<> 161:2cc1468da177 14134 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14135 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
<> 161:2cc1468da177 14136 #define TIM_EGR_CC2G_Pos (2U)
<> 161:2cc1468da177 14137 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14138 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
<> 161:2cc1468da177 14139 #define TIM_EGR_CC3G_Pos (3U)
<> 161:2cc1468da177 14140 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14141 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
<> 161:2cc1468da177 14142 #define TIM_EGR_CC4G_Pos (4U)
<> 161:2cc1468da177 14143 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14144 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
<> 161:2cc1468da177 14145 #define TIM_EGR_COMG_Pos (5U)
<> 161:2cc1468da177 14146 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14147 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
<> 161:2cc1468da177 14148 #define TIM_EGR_TG_Pos (6U)
<> 161:2cc1468da177 14149 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14150 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
<> 161:2cc1468da177 14151 #define TIM_EGR_BG_Pos (7U)
<> 161:2cc1468da177 14152 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14153 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
<> 161:2cc1468da177 14154 #define TIM_EGR_B2G_Pos (8U)
<> 161:2cc1468da177 14155 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14156 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break2 Generation */
<> 144:ef7eb2e8f9f7 14157
<> 144:ef7eb2e8f9f7 14158 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 161:2cc1468da177 14159 #define TIM_CCMR1_CC1S_Pos (0U)
<> 161:2cc1468da177 14160 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 14161 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 161:2cc1468da177 14162 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14163 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14164
<> 161:2cc1468da177 14165 #define TIM_CCMR1_OC1FE_Pos (2U)
<> 161:2cc1468da177 14166 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14167 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
<> 161:2cc1468da177 14168 #define TIM_CCMR1_OC1PE_Pos (3U)
<> 161:2cc1468da177 14169 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14170 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
<> 161:2cc1468da177 14171
<> 161:2cc1468da177 14172 #define TIM_CCMR1_OC1M_Pos (4U)
<> 161:2cc1468da177 14173 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
<> 161:2cc1468da177 14174 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 161:2cc1468da177 14175 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14176 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14177 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14178 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 14179
<> 161:2cc1468da177 14180 #define TIM_CCMR1_OC1CE_Pos (7U)
<> 161:2cc1468da177 14181 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14182 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
<> 161:2cc1468da177 14183
<> 161:2cc1468da177 14184 #define TIM_CCMR1_CC2S_Pos (8U)
<> 161:2cc1468da177 14185 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 14186 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 161:2cc1468da177 14187 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14188 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14189
<> 161:2cc1468da177 14190 #define TIM_CCMR1_OC2FE_Pos (10U)
<> 161:2cc1468da177 14191 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14192 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
<> 161:2cc1468da177 14193 #define TIM_CCMR1_OC2PE_Pos (11U)
<> 161:2cc1468da177 14194 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14195 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
<> 161:2cc1468da177 14196
<> 161:2cc1468da177 14197 #define TIM_CCMR1_OC2M_Pos (12U)
<> 161:2cc1468da177 14198 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
<> 161:2cc1468da177 14199 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 161:2cc1468da177 14200 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 14201 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14202 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 14203 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 14204
<> 161:2cc1468da177 14205 #define TIM_CCMR1_OC2CE_Pos (15U)
<> 161:2cc1468da177 14206 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 14207 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
<> 144:ef7eb2e8f9f7 14208
<> 144:ef7eb2e8f9f7 14209 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 14210
<> 161:2cc1468da177 14211 #define TIM_CCMR1_IC1PSC_Pos (2U)
<> 161:2cc1468da177 14212 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 14213 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 161:2cc1468da177 14214 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
<> 161:2cc1468da177 14215 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
<> 161:2cc1468da177 14216
<> 161:2cc1468da177 14217 #define TIM_CCMR1_IC1F_Pos (4U)
<> 161:2cc1468da177 14218 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 14219 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 161:2cc1468da177 14220 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
<> 161:2cc1468da177 14221 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
<> 161:2cc1468da177 14222 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
<> 161:2cc1468da177 14223 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
<> 161:2cc1468da177 14224
<> 161:2cc1468da177 14225 #define TIM_CCMR1_IC2PSC_Pos (10U)
<> 161:2cc1468da177 14226 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 14227 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 161:2cc1468da177 14228 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
<> 161:2cc1468da177 14229 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
<> 161:2cc1468da177 14230
<> 161:2cc1468da177 14231 #define TIM_CCMR1_IC2F_Pos (12U)
<> 161:2cc1468da177 14232 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 14233 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 161:2cc1468da177 14234 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
<> 161:2cc1468da177 14235 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
<> 161:2cc1468da177 14236 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
<> 161:2cc1468da177 14237 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
<> 144:ef7eb2e8f9f7 14238
<> 144:ef7eb2e8f9f7 14239 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 161:2cc1468da177 14240 #define TIM_CCMR2_CC3S_Pos (0U)
<> 161:2cc1468da177 14241 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 14242 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 161:2cc1468da177 14243 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14244 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14245
<> 161:2cc1468da177 14246 #define TIM_CCMR2_OC3FE_Pos (2U)
<> 161:2cc1468da177 14247 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14248 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
<> 161:2cc1468da177 14249 #define TIM_CCMR2_OC3PE_Pos (3U)
<> 161:2cc1468da177 14250 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14251 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
<> 161:2cc1468da177 14252
<> 161:2cc1468da177 14253 #define TIM_CCMR2_OC3M_Pos (4U)
<> 161:2cc1468da177 14254 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
<> 161:2cc1468da177 14255 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 161:2cc1468da177 14256 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14257 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14258 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14259 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 14260
<> 161:2cc1468da177 14261
<> 161:2cc1468da177 14262
<> 161:2cc1468da177 14263 #define TIM_CCMR2_OC3CE_Pos (7U)
<> 161:2cc1468da177 14264 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14265 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
<> 161:2cc1468da177 14266
<> 161:2cc1468da177 14267 #define TIM_CCMR2_CC4S_Pos (8U)
<> 161:2cc1468da177 14268 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 14269 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 161:2cc1468da177 14270 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14271 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14272
<> 161:2cc1468da177 14273 #define TIM_CCMR2_OC4FE_Pos (10U)
<> 161:2cc1468da177 14274 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14275 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
<> 161:2cc1468da177 14276 #define TIM_CCMR2_OC4PE_Pos (11U)
<> 161:2cc1468da177 14277 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14278 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
<> 161:2cc1468da177 14279
<> 161:2cc1468da177 14280 #define TIM_CCMR2_OC4M_Pos (12U)
<> 161:2cc1468da177 14281 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
<> 161:2cc1468da177 14282 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 161:2cc1468da177 14283 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 14284 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14285 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 14286 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 14287
<> 161:2cc1468da177 14288 #define TIM_CCMR2_OC4CE_Pos (15U)
<> 161:2cc1468da177 14289 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 14290 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
<> 144:ef7eb2e8f9f7 14291
<> 144:ef7eb2e8f9f7 14292 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 14293
<> 161:2cc1468da177 14294 #define TIM_CCMR2_IC3PSC_Pos (2U)
<> 161:2cc1468da177 14295 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 14296 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 161:2cc1468da177 14297 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
<> 161:2cc1468da177 14298 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
<> 161:2cc1468da177 14299
<> 161:2cc1468da177 14300 #define TIM_CCMR2_IC3F_Pos (4U)
<> 161:2cc1468da177 14301 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 14302 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 161:2cc1468da177 14303 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
<> 161:2cc1468da177 14304 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
<> 161:2cc1468da177 14305 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
<> 161:2cc1468da177 14306 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
<> 161:2cc1468da177 14307
<> 161:2cc1468da177 14308 #define TIM_CCMR2_IC4PSC_Pos (10U)
<> 161:2cc1468da177 14309 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 14310 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 161:2cc1468da177 14311 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
<> 161:2cc1468da177 14312 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
<> 161:2cc1468da177 14313
<> 161:2cc1468da177 14314 #define TIM_CCMR2_IC4F_Pos (12U)
<> 161:2cc1468da177 14315 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 14316 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 161:2cc1468da177 14317 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
<> 161:2cc1468da177 14318 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
<> 161:2cc1468da177 14319 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
<> 161:2cc1468da177 14320 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
<> 144:ef7eb2e8f9f7 14321
<> 144:ef7eb2e8f9f7 14322 /******************* Bit definition for TIM_CCER register *******************/
<> 161:2cc1468da177 14323 #define TIM_CCER_CC1E_Pos (0U)
<> 161:2cc1468da177 14324 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14325 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
<> 161:2cc1468da177 14326 #define TIM_CCER_CC1P_Pos (1U)
<> 161:2cc1468da177 14327 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14328 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
<> 161:2cc1468da177 14329 #define TIM_CCER_CC1NE_Pos (2U)
<> 161:2cc1468da177 14330 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14331 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
<> 161:2cc1468da177 14332 #define TIM_CCER_CC1NP_Pos (3U)
<> 161:2cc1468da177 14333 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14334 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
<> 161:2cc1468da177 14335 #define TIM_CCER_CC2E_Pos (4U)
<> 161:2cc1468da177 14336 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14337 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
<> 161:2cc1468da177 14338 #define TIM_CCER_CC2P_Pos (5U)
<> 161:2cc1468da177 14339 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14340 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
<> 161:2cc1468da177 14341 #define TIM_CCER_CC2NE_Pos (6U)
<> 161:2cc1468da177 14342 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14343 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
<> 161:2cc1468da177 14344 #define TIM_CCER_CC2NP_Pos (7U)
<> 161:2cc1468da177 14345 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14346 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
<> 161:2cc1468da177 14347 #define TIM_CCER_CC3E_Pos (8U)
<> 161:2cc1468da177 14348 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14349 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
<> 161:2cc1468da177 14350 #define TIM_CCER_CC3P_Pos (9U)
<> 161:2cc1468da177 14351 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14352 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
<> 161:2cc1468da177 14353 #define TIM_CCER_CC3NE_Pos (10U)
<> 161:2cc1468da177 14354 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14355 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
<> 161:2cc1468da177 14356 #define TIM_CCER_CC3NP_Pos (11U)
<> 161:2cc1468da177 14357 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14358 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
<> 161:2cc1468da177 14359 #define TIM_CCER_CC4E_Pos (12U)
<> 161:2cc1468da177 14360 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 14361 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
<> 161:2cc1468da177 14362 #define TIM_CCER_CC4P_Pos (13U)
<> 161:2cc1468da177 14363 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14364 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
<> 161:2cc1468da177 14365 #define TIM_CCER_CC4NP_Pos (15U)
<> 161:2cc1468da177 14366 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 14367 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
<> 161:2cc1468da177 14368 #define TIM_CCER_CC5E_Pos (16U)
<> 161:2cc1468da177 14369 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 14370 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
<> 161:2cc1468da177 14371 #define TIM_CCER_CC5P_Pos (17U)
<> 161:2cc1468da177 14372 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 14373 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
<> 161:2cc1468da177 14374 #define TIM_CCER_CC6E_Pos (20U)
<> 161:2cc1468da177 14375 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 14376 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
<> 161:2cc1468da177 14377 #define TIM_CCER_CC6P_Pos (21U)
<> 161:2cc1468da177 14378 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 14379 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
<> 144:ef7eb2e8f9f7 14380
<> 144:ef7eb2e8f9f7 14381
<> 144:ef7eb2e8f9f7 14382 /******************* Bit definition for TIM_CNT register ********************/
<> 161:2cc1468da177 14383 #define TIM_CNT_CNT_Pos (0U)
<> 161:2cc1468da177 14384 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 14385 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
<> 161:2cc1468da177 14386 #define TIM_CNT_UIFCPY_Pos (31U)
<> 161:2cc1468da177 14387 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 14388 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
<> 144:ef7eb2e8f9f7 14389
<> 144:ef7eb2e8f9f7 14390 /******************* Bit definition for TIM_PSC register ********************/
<> 161:2cc1468da177 14391 #define TIM_PSC_PSC_Pos (0U)
<> 161:2cc1468da177 14392 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 14393 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
<> 144:ef7eb2e8f9f7 14394
<> 144:ef7eb2e8f9f7 14395 /******************* Bit definition for TIM_ARR register ********************/
<> 161:2cc1468da177 14396 #define TIM_ARR_ARR_Pos (0U)
<> 161:2cc1468da177 14397 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 14398 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
<> 144:ef7eb2e8f9f7 14399
<> 144:ef7eb2e8f9f7 14400 /******************* Bit definition for TIM_RCR register ********************/
<> 161:2cc1468da177 14401 #define TIM_RCR_REP_Pos (0U)
<> 161:2cc1468da177 14402 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 14403 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
<> 144:ef7eb2e8f9f7 14404
<> 144:ef7eb2e8f9f7 14405 /******************* Bit definition for TIM_CCR1 register *******************/
<> 161:2cc1468da177 14406 #define TIM_CCR1_CCR1_Pos (0U)
<> 161:2cc1468da177 14407 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 14408 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
<> 144:ef7eb2e8f9f7 14409
<> 144:ef7eb2e8f9f7 14410 /******************* Bit definition for TIM_CCR2 register *******************/
<> 161:2cc1468da177 14411 #define TIM_CCR2_CCR2_Pos (0U)
<> 161:2cc1468da177 14412 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 14413 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
<> 144:ef7eb2e8f9f7 14414
<> 144:ef7eb2e8f9f7 14415 /******************* Bit definition for TIM_CCR3 register *******************/
<> 161:2cc1468da177 14416 #define TIM_CCR3_CCR3_Pos (0U)
<> 161:2cc1468da177 14417 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 14418 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
<> 144:ef7eb2e8f9f7 14419
<> 144:ef7eb2e8f9f7 14420 /******************* Bit definition for TIM_CCR4 register *******************/
<> 161:2cc1468da177 14421 #define TIM_CCR4_CCR4_Pos (0U)
<> 161:2cc1468da177 14422 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 14423 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
<> 144:ef7eb2e8f9f7 14424
<> 144:ef7eb2e8f9f7 14425 /******************* Bit definition for TIM_BDTR register *******************/
<> 161:2cc1468da177 14426 #define TIM_BDTR_DTG_Pos (0U)
<> 161:2cc1468da177 14427 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 14428 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
<> 161:2cc1468da177 14429 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14430 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14431 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14432 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14433 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14434 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14435 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14436 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14437
<> 161:2cc1468da177 14438 #define TIM_BDTR_LOCK_Pos (8U)
<> 161:2cc1468da177 14439 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 14440 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
<> 161:2cc1468da177 14441 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14442 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14443
<> 161:2cc1468da177 14444 #define TIM_BDTR_OSSI_Pos (10U)
<> 161:2cc1468da177 14445 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14446 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
<> 161:2cc1468da177 14447 #define TIM_BDTR_OSSR_Pos (11U)
<> 161:2cc1468da177 14448 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14449 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
<> 161:2cc1468da177 14450 #define TIM_BDTR_BKE_Pos (12U)
<> 161:2cc1468da177 14451 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 14452 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
<> 161:2cc1468da177 14453 #define TIM_BDTR_BKP_Pos (13U)
<> 161:2cc1468da177 14454 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14455 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
<> 161:2cc1468da177 14456 #define TIM_BDTR_AOE_Pos (14U)
<> 161:2cc1468da177 14457 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 14458 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
<> 161:2cc1468da177 14459 #define TIM_BDTR_MOE_Pos (15U)
<> 161:2cc1468da177 14460 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 14461 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
<> 161:2cc1468da177 14462 #define TIM_BDTR_BKF_Pos (16U)
<> 161:2cc1468da177 14463 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
<> 161:2cc1468da177 14464 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
<> 161:2cc1468da177 14465 #define TIM_BDTR_BK2F_Pos (20U)
<> 161:2cc1468da177 14466 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
<> 161:2cc1468da177 14467 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
<> 161:2cc1468da177 14468 #define TIM_BDTR_BK2E_Pos (24U)
<> 161:2cc1468da177 14469 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 14470 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
<> 161:2cc1468da177 14471 #define TIM_BDTR_BK2P_Pos (25U)
<> 161:2cc1468da177 14472 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 14473 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
<> 144:ef7eb2e8f9f7 14474
<> 144:ef7eb2e8f9f7 14475 /******************* Bit definition for TIM_DCR register ********************/
<> 161:2cc1468da177 14476 #define TIM_DCR_DBA_Pos (0U)
<> 161:2cc1468da177 14477 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
<> 161:2cc1468da177 14478 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
<> 161:2cc1468da177 14479 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
<> 161:2cc1468da177 14480 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
<> 161:2cc1468da177 14481 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
<> 161:2cc1468da177 14482 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
<> 161:2cc1468da177 14483 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
<> 161:2cc1468da177 14484
<> 161:2cc1468da177 14485 #define TIM_DCR_DBL_Pos (8U)
<> 161:2cc1468da177 14486 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
<> 161:2cc1468da177 14487 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
<> 161:2cc1468da177 14488 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
<> 161:2cc1468da177 14489 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
<> 161:2cc1468da177 14490 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
<> 161:2cc1468da177 14491 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
<> 161:2cc1468da177 14492 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
<> 144:ef7eb2e8f9f7 14493
<> 144:ef7eb2e8f9f7 14494 /******************* Bit definition for TIM_DMAR register *******************/
<> 161:2cc1468da177 14495 #define TIM_DMAR_DMAB_Pos (0U)
<> 161:2cc1468da177 14496 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 14497 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
<> 144:ef7eb2e8f9f7 14498
<> 144:ef7eb2e8f9f7 14499 /******************* Bit definition for TIM_OR regiter *********************/
<> 161:2cc1468da177 14500 #define TIM_OR_TI4_RMP_Pos (6U)
<> 161:2cc1468da177 14501 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 14502 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
<> 161:2cc1468da177 14503 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
<> 161:2cc1468da177 14504 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
<> 161:2cc1468da177 14505 #define TIM_OR_ITR1_RMP_Pos (10U)
<> 161:2cc1468da177 14506 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 14507 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
<> 161:2cc1468da177 14508 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
<> 161:2cc1468da177 14509 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
<> 161:2cc1468da177 14510
<> 161:2cc1468da177 14511 /******************* Bit definition for TIM2_OR register *******************/
<> 161:2cc1468da177 14512 #define TIM2_OR_ITR1_RMP_Pos (10U)
<> 161:2cc1468da177 14513 #define TIM2_OR_ITR1_RMP_Msk (0x3U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 14514 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
<> 161:2cc1468da177 14515 #define TIM2_OR_ITR1_RMP_0 (0x1U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14516 #define TIM2_OR_ITR1_RMP_1 (0x2U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14517
<> 161:2cc1468da177 14518 /******************* Bit definition for TIM5_OR register *******************/
<> 161:2cc1468da177 14519 #define TIM5_OR_TI4_RMP_Pos (6U)
<> 161:2cc1468da177 14520 #define TIM5_OR_TI4_RMP_Msk (0x3U << TIM5_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 14521 #define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input Capture 4 remap) */
<> 161:2cc1468da177 14522 #define TIM5_OR_TI4_RMP_0 (0x1U << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14523 #define TIM5_OR_TI4_RMP_1 (0x2U << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14524
<> 161:2cc1468da177 14525 /******************* Bit definition for TIM11_OR register *******************/
<> 161:2cc1468da177 14526 #define TIM11_OR_TI1_RMP_Pos (0U)
<> 161:2cc1468da177 14527 #define TIM11_OR_TI1_RMP_Msk (0x3U << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 14528 #define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
<> 161:2cc1468da177 14529 #define TIM11_OR_TI1_RMP_0 (0x1U << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14530 #define TIM11_OR_TI1_RMP_1 (0x2U << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 14531
<> 144:ef7eb2e8f9f7 14532 /****************** Bit definition for TIM_CCMR3 register *******************/
<> 161:2cc1468da177 14533 #define TIM_CCMR3_OC5FE_Pos (2U)
<> 161:2cc1468da177 14534 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14535 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
<> 161:2cc1468da177 14536 #define TIM_CCMR3_OC5PE_Pos (3U)
<> 161:2cc1468da177 14537 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14538 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
<> 161:2cc1468da177 14539
<> 161:2cc1468da177 14540 #define TIM_CCMR3_OC5M_Pos (4U)
<> 161:2cc1468da177 14541 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
<> 161:2cc1468da177 14542 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
<> 161:2cc1468da177 14543 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14544 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14545 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14546 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 14547
<> 161:2cc1468da177 14548 #define TIM_CCMR3_OC5CE_Pos (7U)
<> 161:2cc1468da177 14549 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14550 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
<> 161:2cc1468da177 14551
<> 161:2cc1468da177 14552 #define TIM_CCMR3_OC6FE_Pos (10U)
<> 161:2cc1468da177 14553 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14554 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
<> 161:2cc1468da177 14555 #define TIM_CCMR3_OC6PE_Pos (11U)
<> 161:2cc1468da177 14556 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14557 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
<> 161:2cc1468da177 14558
<> 161:2cc1468da177 14559 #define TIM_CCMR3_OC6M_Pos (12U)
<> 161:2cc1468da177 14560 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
<> 161:2cc1468da177 14561 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 161:2cc1468da177 14562 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 14563 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14564 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 14565 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 14566
<> 161:2cc1468da177 14567 #define TIM_CCMR3_OC6CE_Pos (15U)
<> 161:2cc1468da177 14568 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 14569 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
<> 144:ef7eb2e8f9f7 14570
<> 144:ef7eb2e8f9f7 14571 /******************* Bit definition for TIM_CCR5 register *******************/
<> 161:2cc1468da177 14572 #define TIM_CCR5_CCR5_Pos (0U)
<> 161:2cc1468da177 14573 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 14574 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
<> 161:2cc1468da177 14575 #define TIM_CCR5_GC5C1_Pos (29U)
<> 161:2cc1468da177 14576 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 14577 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
<> 161:2cc1468da177 14578 #define TIM_CCR5_GC5C2_Pos (30U)
<> 161:2cc1468da177 14579 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 14580 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
<> 161:2cc1468da177 14581 #define TIM_CCR5_GC5C3_Pos (31U)
<> 161:2cc1468da177 14582 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 14583 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
<> 144:ef7eb2e8f9f7 14584
<> 144:ef7eb2e8f9f7 14585 /******************* Bit definition for TIM_CCR6 register *******************/
<> 161:2cc1468da177 14586 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */
<> 144:ef7eb2e8f9f7 14587
<> 144:ef7eb2e8f9f7 14588 /******************* Bit definition for TIM1_AF1 register *******************/
<> 161:2cc1468da177 14589 #define TIM1_AF1_BKINE_Pos (0U)
<> 161:2cc1468da177 14590 #define TIM1_AF1_BKINE_Msk (0x1U << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14591 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
<> 161:2cc1468da177 14592 #define TIM1_AF1_BKDF1BKE_Pos (8U)
<> 161:2cc1468da177 14593 #define TIM1_AF1_BKDF1BKE_Msk (0x1U << TIM1_AF1_BKDF1BKE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14594 #define TIM1_AF1_BKDF1BKE TIM1_AF1_BKDF1BKE_Msk /*!<BRK DFSDM1_BREAK enable */
<> 161:2cc1468da177 14595 #define TIM1_AF1_BKINP_Pos (9U)
<> 161:2cc1468da177 14596 #define TIM1_AF1_BKINP_Msk (0x1U << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14597 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
<> 144:ef7eb2e8f9f7 14598
<> 144:ef7eb2e8f9f7 14599 /******************* Bit definition for TIM1_AF2 register *******************/
<> 161:2cc1468da177 14600 #define TIM1_AF2_BK2INE_Pos (0U)
<> 161:2cc1468da177 14601 #define TIM1_AF2_BK2INE_Msk (0x1U << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14602 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
<> 161:2cc1468da177 14603 #define TIM1_AF2_BK2DF1BKE_Pos (8U)
<> 161:2cc1468da177 14604 #define TIM1_AF2_BK2DF1BKE_Msk (0x1U << TIM1_AF2_BK2DF1BKE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14605 #define TIM1_AF2_BK2DF1BKE TIM1_AF2_BK2DF1BKE_Msk /*!<BRK2 DFSDM1_BREAK enable */
<> 161:2cc1468da177 14606 #define TIM1_AF2_BK2INP_Pos (9U)
<> 161:2cc1468da177 14607 #define TIM1_AF2_BK2INP_Msk (0x1U << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14608 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK BKIN input polarity */
<> 144:ef7eb2e8f9f7 14609
<> 144:ef7eb2e8f9f7 14610 /******************* Bit definition for TIM8_AF1 register *******************/
<> 161:2cc1468da177 14611 #define TIM8_AF1_BKINE_Pos (0U)
<> 161:2cc1468da177 14612 #define TIM8_AF1_BKINE_Msk (0x1U << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14613 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BRK BKIN input enable */
<> 161:2cc1468da177 14614 #define TIM8_AF1_BKDF1BKE_Pos (8U)
<> 161:2cc1468da177 14615 #define TIM8_AF1_BKDF1BKE_Msk (0x1U << TIM8_AF1_BKDF1BKE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14616 #define TIM8_AF1_BKDF1BKE TIM8_AF1_BKDF1BKE_Msk /*!<BRK DFSDM1_BREAK enable */
<> 161:2cc1468da177 14617 #define TIM8_AF1_BKINP_Pos (9U)
<> 161:2cc1468da177 14618 #define TIM8_AF1_BKINP_Msk (0x1U << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14619 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
<> 144:ef7eb2e8f9f7 14620
<> 144:ef7eb2e8f9f7 14621 /******************* Bit definition for TIM8_AF2 register *******************/
<> 161:2cc1468da177 14622 #define TIM8_AF2_BK2INE_Pos (0U)
<> 161:2cc1468da177 14623 #define TIM8_AF2_BK2INE_Msk (0x1U << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14624 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
<> 161:2cc1468da177 14625 #define TIM8_AF2_BK2DF1BKE_Pos (8U)
<> 161:2cc1468da177 14626 #define TIM8_AF2_BK2DF1BKE_Msk (0x1U << TIM8_AF2_BK2DF1BKE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14627 #define TIM8_AF2_BK2DF1BKE TIM8_AF2_BK2DF1BKE_Msk /*!<BRK2 DFSDM1_BREAK enable */
<> 161:2cc1468da177 14628 #define TIM8_AF2_BK2INP_Pos (9U)
<> 161:2cc1468da177 14629 #define TIM8_AF2_BK2INP_Msk (0x1U << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14630 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRK BKIN input polarity */
<> 161:2cc1468da177 14631
<> 144:ef7eb2e8f9f7 14632
<> 144:ef7eb2e8f9f7 14633 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14634 /* */
<> 144:ef7eb2e8f9f7 14635 /* Low Power Timer (LPTIM) */
<> 144:ef7eb2e8f9f7 14636 /* */
<> 144:ef7eb2e8f9f7 14637 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14638 /****************** Bit definition for LPTIM_ISR register *******************/
<> 161:2cc1468da177 14639 #define LPTIM_ISR_CMPM_Pos (0U)
<> 161:2cc1468da177 14640 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14641 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
<> 161:2cc1468da177 14642 #define LPTIM_ISR_ARRM_Pos (1U)
<> 161:2cc1468da177 14643 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14644 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
<> 161:2cc1468da177 14645 #define LPTIM_ISR_EXTTRIG_Pos (2U)
<> 161:2cc1468da177 14646 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14647 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
<> 161:2cc1468da177 14648 #define LPTIM_ISR_CMPOK_Pos (3U)
<> 161:2cc1468da177 14649 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14650 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
<> 161:2cc1468da177 14651 #define LPTIM_ISR_ARROK_Pos (4U)
<> 161:2cc1468da177 14652 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14653 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
<> 161:2cc1468da177 14654 #define LPTIM_ISR_UP_Pos (5U)
<> 161:2cc1468da177 14655 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14656 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
<> 161:2cc1468da177 14657 #define LPTIM_ISR_DOWN_Pos (6U)
<> 161:2cc1468da177 14658 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14659 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
<> 144:ef7eb2e8f9f7 14660
<> 144:ef7eb2e8f9f7 14661 /****************** Bit definition for LPTIM_ICR register *******************/
<> 161:2cc1468da177 14662 #define LPTIM_ICR_CMPMCF_Pos (0U)
<> 161:2cc1468da177 14663 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14664 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
<> 161:2cc1468da177 14665 #define LPTIM_ICR_ARRMCF_Pos (1U)
<> 161:2cc1468da177 14666 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14667 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
<> 161:2cc1468da177 14668 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
<> 161:2cc1468da177 14669 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14670 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
<> 161:2cc1468da177 14671 #define LPTIM_ICR_CMPOKCF_Pos (3U)
<> 161:2cc1468da177 14672 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14673 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
<> 161:2cc1468da177 14674 #define LPTIM_ICR_ARROKCF_Pos (4U)
<> 161:2cc1468da177 14675 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14676 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
<> 161:2cc1468da177 14677 #define LPTIM_ICR_UPCF_Pos (5U)
<> 161:2cc1468da177 14678 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14679 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
<> 161:2cc1468da177 14680 #define LPTIM_ICR_DOWNCF_Pos (6U)
<> 161:2cc1468da177 14681 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14682 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
<> 144:ef7eb2e8f9f7 14683
<> 144:ef7eb2e8f9f7 14684 /****************** Bit definition for LPTIM_IER register *******************/
<> 161:2cc1468da177 14685 #define LPTIM_IER_CMPMIE_Pos (0U)
<> 161:2cc1468da177 14686 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14687 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
<> 161:2cc1468da177 14688 #define LPTIM_IER_ARRMIE_Pos (1U)
<> 161:2cc1468da177 14689 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14690 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
<> 161:2cc1468da177 14691 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
<> 161:2cc1468da177 14692 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14693 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
<> 161:2cc1468da177 14694 #define LPTIM_IER_CMPOKIE_Pos (3U)
<> 161:2cc1468da177 14695 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14696 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
<> 161:2cc1468da177 14697 #define LPTIM_IER_ARROKIE_Pos (4U)
<> 161:2cc1468da177 14698 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14699 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
<> 161:2cc1468da177 14700 #define LPTIM_IER_UPIE_Pos (5U)
<> 161:2cc1468da177 14701 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14702 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
<> 161:2cc1468da177 14703 #define LPTIM_IER_DOWNIE_Pos (6U)
<> 161:2cc1468da177 14704 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14705 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
<> 144:ef7eb2e8f9f7 14706
<> 144:ef7eb2e8f9f7 14707 /****************** Bit definition for LPTIM_CFGR register*******************/
<> 161:2cc1468da177 14708 #define LPTIM_CFGR_CKSEL_Pos (0U)
<> 161:2cc1468da177 14709 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14710 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
<> 161:2cc1468da177 14711
<> 161:2cc1468da177 14712 #define LPTIM_CFGR_CKPOL_Pos (1U)
<> 161:2cc1468da177 14713 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
<> 161:2cc1468da177 14714 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
<> 161:2cc1468da177 14715 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14716 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14717
<> 161:2cc1468da177 14718 #define LPTIM_CFGR_CKFLT_Pos (3U)
<> 161:2cc1468da177 14719 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
<> 161:2cc1468da177 14720 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
<> 161:2cc1468da177 14721 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14722 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14723
<> 161:2cc1468da177 14724 #define LPTIM_CFGR_TRGFLT_Pos (6U)
<> 161:2cc1468da177 14725 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 14726 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
<> 161:2cc1468da177 14727 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14728 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14729
<> 161:2cc1468da177 14730 #define LPTIM_CFGR_PRESC_Pos (9U)
<> 161:2cc1468da177 14731 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
<> 161:2cc1468da177 14732 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
<> 161:2cc1468da177 14733 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14734 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14735 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14736
<> 161:2cc1468da177 14737 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
<> 161:2cc1468da177 14738 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
<> 161:2cc1468da177 14739 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
<> 161:2cc1468da177 14740 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14741 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 14742 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 14743
<> 161:2cc1468da177 14744 #define LPTIM_CFGR_TRIGEN_Pos (17U)
<> 161:2cc1468da177 14745 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
<> 161:2cc1468da177 14746 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
<> 161:2cc1468da177 14747 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 14748 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 14749
<> 161:2cc1468da177 14750 #define LPTIM_CFGR_TIMOUT_Pos (19U)
<> 161:2cc1468da177 14751 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 14752 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
<> 161:2cc1468da177 14753 #define LPTIM_CFGR_WAVE_Pos (20U)
<> 161:2cc1468da177 14754 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 14755 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
<> 161:2cc1468da177 14756 #define LPTIM_CFGR_WAVPOL_Pos (21U)
<> 161:2cc1468da177 14757 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 14758 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
<> 161:2cc1468da177 14759 #define LPTIM_CFGR_PRELOAD_Pos (22U)
<> 161:2cc1468da177 14760 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 14761 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
<> 161:2cc1468da177 14762 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
<> 161:2cc1468da177 14763 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 14764 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
<> 161:2cc1468da177 14765 #define LPTIM_CFGR_ENC_Pos (24U)
<> 161:2cc1468da177 14766 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 14767 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
<> 144:ef7eb2e8f9f7 14768
<> 144:ef7eb2e8f9f7 14769 /****************** Bit definition for LPTIM_CR register ********************/
<> 161:2cc1468da177 14770 #define LPTIM_CR_ENABLE_Pos (0U)
<> 161:2cc1468da177 14771 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14772 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
<> 161:2cc1468da177 14773 #define LPTIM_CR_SNGSTRT_Pos (1U)
<> 161:2cc1468da177 14774 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14775 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
<> 161:2cc1468da177 14776 #define LPTIM_CR_CNTSTRT_Pos (2U)
<> 161:2cc1468da177 14777 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14778 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
<> 144:ef7eb2e8f9f7 14779
<> 144:ef7eb2e8f9f7 14780 /****************** Bit definition for LPTIM_CMP register *******************/
<> 161:2cc1468da177 14781 #define LPTIM_CMP_CMP_Pos (0U)
<> 161:2cc1468da177 14782 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 14783 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
<> 144:ef7eb2e8f9f7 14784
<> 144:ef7eb2e8f9f7 14785 /****************** Bit definition for LPTIM_ARR register *******************/
<> 161:2cc1468da177 14786 #define LPTIM_ARR_ARR_Pos (0U)
<> 161:2cc1468da177 14787 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 14788 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
<> 144:ef7eb2e8f9f7 14789
<> 144:ef7eb2e8f9f7 14790 /****************** Bit definition for LPTIM_CNT register *******************/
<> 161:2cc1468da177 14791 #define LPTIM_CNT_CNT_Pos (0U)
<> 161:2cc1468da177 14792 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 14793 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
<> 144:ef7eb2e8f9f7 14794 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14795 /* */
<> 144:ef7eb2e8f9f7 14796 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
<> 144:ef7eb2e8f9f7 14797 /* */
<> 144:ef7eb2e8f9f7 14798 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14799 /****************** Bit definition for USART_CR1 register *******************/
<> 161:2cc1468da177 14800 #define USART_CR1_UE_Pos (0U)
<> 161:2cc1468da177 14801 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14802 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
<> 161:2cc1468da177 14803 #define USART_CR1_RE_Pos (2U)
<> 161:2cc1468da177 14804 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14805 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
<> 161:2cc1468da177 14806 #define USART_CR1_TE_Pos (3U)
<> 161:2cc1468da177 14807 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14808 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
<> 161:2cc1468da177 14809 #define USART_CR1_IDLEIE_Pos (4U)
<> 161:2cc1468da177 14810 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14811 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
<> 161:2cc1468da177 14812 #define USART_CR1_RXNEIE_Pos (5U)
<> 161:2cc1468da177 14813 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14814 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
<> 161:2cc1468da177 14815 #define USART_CR1_TCIE_Pos (6U)
<> 161:2cc1468da177 14816 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14817 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
<> 161:2cc1468da177 14818 #define USART_CR1_TXEIE_Pos (7U)
<> 161:2cc1468da177 14819 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14820 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
<> 161:2cc1468da177 14821 #define USART_CR1_PEIE_Pos (8U)
<> 161:2cc1468da177 14822 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14823 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
<> 161:2cc1468da177 14824 #define USART_CR1_PS_Pos (9U)
<> 161:2cc1468da177 14825 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14826 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
<> 161:2cc1468da177 14827 #define USART_CR1_PCE_Pos (10U)
<> 161:2cc1468da177 14828 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14829 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
<> 161:2cc1468da177 14830 #define USART_CR1_WAKE_Pos (11U)
<> 161:2cc1468da177 14831 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14832 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
<> 161:2cc1468da177 14833 #define USART_CR1_M_Pos (12U)
<> 161:2cc1468da177 14834 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
<> 161:2cc1468da177 14835 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
<> 161:2cc1468da177 14836 #define USART_CR1_M0 (0x00001U << USART_CR1_M_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 14837 #define USART_CR1_MME_Pos (13U)
<> 161:2cc1468da177 14838 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14839 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
<> 161:2cc1468da177 14840 #define USART_CR1_CMIE_Pos (14U)
<> 161:2cc1468da177 14841 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 14842 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
<> 161:2cc1468da177 14843 #define USART_CR1_OVER8_Pos (15U)
<> 161:2cc1468da177 14844 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 14845 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
<> 161:2cc1468da177 14846 #define USART_CR1_DEDT_Pos (16U)
<> 161:2cc1468da177 14847 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
<> 161:2cc1468da177 14848 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
<> 161:2cc1468da177 14849 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 14850 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 14851 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 14852 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 14853 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 14854 #define USART_CR1_DEAT_Pos (21U)
<> 161:2cc1468da177 14855 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
<> 161:2cc1468da177 14856 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
<> 161:2cc1468da177 14857 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 14858 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 14859 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 14860 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 14861 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 14862 #define USART_CR1_RTOIE_Pos (26U)
<> 161:2cc1468da177 14863 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 14864 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
<> 161:2cc1468da177 14865 #define USART_CR1_EOBIE_Pos (27U)
<> 161:2cc1468da177 14866 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 14867 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
<> 161:2cc1468da177 14868 #define USART_CR1_M1 0x10000000U /*!< Word length - Bit 1 */
<> 161:2cc1468da177 14869
<> 161:2cc1468da177 14870 /* Legacy defines */
<> 161:2cc1468da177 14871 #define USART_CR1_M_0 USART_CR1_M0 /*!< Word length - Bit 0 */
<> 161:2cc1468da177 14872 #define USART_CR1_M_1 USART_CR1_M1 /*!< Word length - Bit 1 */
<> 144:ef7eb2e8f9f7 14873
<> 144:ef7eb2e8f9f7 14874 /****************** Bit definition for USART_CR2 register *******************/
<> 161:2cc1468da177 14875 #define USART_CR2_ADDM7_Pos (4U)
<> 161:2cc1468da177 14876 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14877 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
<> 161:2cc1468da177 14878 #define USART_CR2_LBDL_Pos (5U)
<> 161:2cc1468da177 14879 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14880 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
<> 161:2cc1468da177 14881 #define USART_CR2_LBDIE_Pos (6U)
<> 161:2cc1468da177 14882 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14883 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
<> 161:2cc1468da177 14884 #define USART_CR2_LBCL_Pos (8U)
<> 161:2cc1468da177 14885 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14886 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
<> 161:2cc1468da177 14887 #define USART_CR2_CPHA_Pos (9U)
<> 161:2cc1468da177 14888 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14889 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
<> 161:2cc1468da177 14890 #define USART_CR2_CPOL_Pos (10U)
<> 161:2cc1468da177 14891 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14892 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
<> 161:2cc1468da177 14893 #define USART_CR2_CLKEN_Pos (11U)
<> 161:2cc1468da177 14894 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14895 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
<> 161:2cc1468da177 14896 #define USART_CR2_STOP_Pos (12U)
<> 161:2cc1468da177 14897 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
<> 161:2cc1468da177 14898 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
<> 161:2cc1468da177 14899 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 14900 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14901 #define USART_CR2_LINEN_Pos (14U)
<> 161:2cc1468da177 14902 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 14903 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
<> 161:2cc1468da177 14904 #define USART_CR2_SWAP_Pos (15U)
<> 161:2cc1468da177 14905 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 14906 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
<> 161:2cc1468da177 14907 #define USART_CR2_RXINV_Pos (16U)
<> 161:2cc1468da177 14908 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 14909 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
<> 161:2cc1468da177 14910 #define USART_CR2_TXINV_Pos (17U)
<> 161:2cc1468da177 14911 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 14912 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
<> 161:2cc1468da177 14913 #define USART_CR2_DATAINV_Pos (18U)
<> 161:2cc1468da177 14914 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 14915 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
<> 161:2cc1468da177 14916 #define USART_CR2_MSBFIRST_Pos (19U)
<> 161:2cc1468da177 14917 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 14918 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
<> 161:2cc1468da177 14919 #define USART_CR2_ABREN_Pos (20U)
<> 161:2cc1468da177 14920 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 14921 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable */
<> 161:2cc1468da177 14922 #define USART_CR2_ABRMODE_Pos (21U)
<> 161:2cc1468da177 14923 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
<> 161:2cc1468da177 14924 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
<> 161:2cc1468da177 14925 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 14926 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 14927 #define USART_CR2_RTOEN_Pos (23U)
<> 161:2cc1468da177 14928 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 14929 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
<> 161:2cc1468da177 14930 #define USART_CR2_ADD_Pos (24U)
<> 161:2cc1468da177 14931 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 14932 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
<> 144:ef7eb2e8f9f7 14933
<> 144:ef7eb2e8f9f7 14934 /****************** Bit definition for USART_CR3 register *******************/
<> 161:2cc1468da177 14935 #define USART_CR3_EIE_Pos (0U)
<> 161:2cc1468da177 14936 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 14937 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
<> 161:2cc1468da177 14938 #define USART_CR3_IREN_Pos (1U)
<> 161:2cc1468da177 14939 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 14940 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
<> 161:2cc1468da177 14941 #define USART_CR3_IRLP_Pos (2U)
<> 161:2cc1468da177 14942 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 14943 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
<> 161:2cc1468da177 14944 #define USART_CR3_HDSEL_Pos (3U)
<> 161:2cc1468da177 14945 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 14946 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
<> 161:2cc1468da177 14947 #define USART_CR3_NACK_Pos (4U)
<> 161:2cc1468da177 14948 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 14949 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
<> 161:2cc1468da177 14950 #define USART_CR3_SCEN_Pos (5U)
<> 161:2cc1468da177 14951 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 14952 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
<> 161:2cc1468da177 14953 #define USART_CR3_DMAR_Pos (6U)
<> 161:2cc1468da177 14954 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 14955 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
<> 161:2cc1468da177 14956 #define USART_CR3_DMAT_Pos (7U)
<> 161:2cc1468da177 14957 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 14958 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
<> 161:2cc1468da177 14959 #define USART_CR3_RTSE_Pos (8U)
<> 161:2cc1468da177 14960 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 14961 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
<> 161:2cc1468da177 14962 #define USART_CR3_CTSE_Pos (9U)
<> 161:2cc1468da177 14963 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 14964 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
<> 161:2cc1468da177 14965 #define USART_CR3_CTSIE_Pos (10U)
<> 161:2cc1468da177 14966 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 14967 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
<> 161:2cc1468da177 14968 #define USART_CR3_ONEBIT_Pos (11U)
<> 161:2cc1468da177 14969 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 14970 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
<> 161:2cc1468da177 14971 #define USART_CR3_OVRDIS_Pos (12U)
<> 161:2cc1468da177 14972 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 14973 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
<> 161:2cc1468da177 14974 #define USART_CR3_DDRE_Pos (13U)
<> 161:2cc1468da177 14975 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 14976 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
<> 161:2cc1468da177 14977 #define USART_CR3_DEM_Pos (14U)
<> 161:2cc1468da177 14978 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 14979 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
<> 161:2cc1468da177 14980 #define USART_CR3_DEP_Pos (15U)
<> 161:2cc1468da177 14981 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 14982 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
<> 161:2cc1468da177 14983 #define USART_CR3_SCARCNT_Pos (17U)
<> 161:2cc1468da177 14984 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
<> 161:2cc1468da177 14985 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
<> 161:2cc1468da177 14986 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 14987 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 14988 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 14989
<> 144:ef7eb2e8f9f7 14990 /****************** Bit definition for USART_BRR register *******************/
<> 161:2cc1468da177 14991 #define USART_BRR_DIV_FRACTION_Pos (0U)
<> 161:2cc1468da177 14992 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 14993 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
<> 161:2cc1468da177 14994 #define USART_BRR_DIV_MANTISSA_Pos (4U)
<> 161:2cc1468da177 14995 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
<> 161:2cc1468da177 14996 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
<> 144:ef7eb2e8f9f7 14997
<> 144:ef7eb2e8f9f7 14998 /****************** Bit definition for USART_GTPR register ******************/
<> 161:2cc1468da177 14999 #define USART_GTPR_PSC_Pos (0U)
<> 161:2cc1468da177 15000 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 15001 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
<> 161:2cc1468da177 15002 #define USART_GTPR_GT_Pos (8U)
<> 161:2cc1468da177 15003 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
<> 161:2cc1468da177 15004 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
<> 144:ef7eb2e8f9f7 15005
<> 144:ef7eb2e8f9f7 15006
<> 144:ef7eb2e8f9f7 15007 /******************* Bit definition for USART_RTOR register *****************/
<> 161:2cc1468da177 15008 #define USART_RTOR_RTO_Pos (0U)
<> 161:2cc1468da177 15009 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
<> 161:2cc1468da177 15010 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
<> 161:2cc1468da177 15011 #define USART_RTOR_BLEN_Pos (24U)
<> 161:2cc1468da177 15012 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 15013 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
<> 144:ef7eb2e8f9f7 15014
<> 144:ef7eb2e8f9f7 15015 /******************* Bit definition for USART_RQR register ******************/
<> 161:2cc1468da177 15016 #define USART_RQR_ABRRQ_Pos (0U)
<> 161:2cc1468da177 15017 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15018 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
<> 161:2cc1468da177 15019 #define USART_RQR_SBKRQ_Pos (1U)
<> 161:2cc1468da177 15020 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15021 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
<> 161:2cc1468da177 15022 #define USART_RQR_MMRQ_Pos (2U)
<> 161:2cc1468da177 15023 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15024 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
<> 161:2cc1468da177 15025 #define USART_RQR_RXFRQ_Pos (3U)
<> 161:2cc1468da177 15026 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15027 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
<> 161:2cc1468da177 15028 #define USART_RQR_TXFRQ_Pos (4U)
<> 161:2cc1468da177 15029 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15030 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
<> 144:ef7eb2e8f9f7 15031
<> 144:ef7eb2e8f9f7 15032 /******************* Bit definition for USART_ISR register ******************/
<> 161:2cc1468da177 15033 #define USART_ISR_PE_Pos (0U)
<> 161:2cc1468da177 15034 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15035 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
<> 161:2cc1468da177 15036 #define USART_ISR_FE_Pos (1U)
<> 161:2cc1468da177 15037 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15038 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
<> 161:2cc1468da177 15039 #define USART_ISR_NE_Pos (2U)
<> 161:2cc1468da177 15040 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15041 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
<> 161:2cc1468da177 15042 #define USART_ISR_ORE_Pos (3U)
<> 161:2cc1468da177 15043 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15044 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
<> 161:2cc1468da177 15045 #define USART_ISR_IDLE_Pos (4U)
<> 161:2cc1468da177 15046 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15047 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
<> 161:2cc1468da177 15048 #define USART_ISR_RXNE_Pos (5U)
<> 161:2cc1468da177 15049 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15050 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
<> 161:2cc1468da177 15051 #define USART_ISR_TC_Pos (6U)
<> 161:2cc1468da177 15052 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 15053 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
<> 161:2cc1468da177 15054 #define USART_ISR_TXE_Pos (7U)
<> 161:2cc1468da177 15055 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 15056 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
<> 161:2cc1468da177 15057 #define USART_ISR_LBDF_Pos (8U)
<> 161:2cc1468da177 15058 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 15059 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
<> 161:2cc1468da177 15060 #define USART_ISR_CTSIF_Pos (9U)
<> 161:2cc1468da177 15061 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15062 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
<> 161:2cc1468da177 15063 #define USART_ISR_CTS_Pos (10U)
<> 161:2cc1468da177 15064 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 15065 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
<> 161:2cc1468da177 15066 #define USART_ISR_RTOF_Pos (11U)
<> 161:2cc1468da177 15067 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 15068 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
<> 161:2cc1468da177 15069 #define USART_ISR_EOBF_Pos (12U)
<> 161:2cc1468da177 15070 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 15071 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
<> 161:2cc1468da177 15072 #define USART_ISR_ABRE_Pos (14U)
<> 161:2cc1468da177 15073 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 15074 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
<> 161:2cc1468da177 15075 #define USART_ISR_ABRF_Pos (15U)
<> 161:2cc1468da177 15076 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 15077 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
<> 161:2cc1468da177 15078 #define USART_ISR_BUSY_Pos (16U)
<> 161:2cc1468da177 15079 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 15080 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
<> 161:2cc1468da177 15081 #define USART_ISR_CMF_Pos (17U)
<> 161:2cc1468da177 15082 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 15083 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
<> 161:2cc1468da177 15084 #define USART_ISR_SBKF_Pos (18U)
<> 161:2cc1468da177 15085 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 15086 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
<> 161:2cc1468da177 15087 #define USART_ISR_RWU_Pos (19U)
<> 161:2cc1468da177 15088 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 15089 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
<> 161:2cc1468da177 15090 #define USART_ISR_TEACK_Pos (21U)
<> 161:2cc1468da177 15091 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 15092 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
<> 144:ef7eb2e8f9f7 15093
<> 144:ef7eb2e8f9f7 15094 /******************* Bit definition for USART_ICR register ******************/
<> 161:2cc1468da177 15095 #define USART_ICR_PECF_Pos (0U)
<> 161:2cc1468da177 15096 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15097 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
<> 161:2cc1468da177 15098 #define USART_ICR_FECF_Pos (1U)
<> 161:2cc1468da177 15099 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15100 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
<> 161:2cc1468da177 15101 #define USART_ICR_NCF_Pos (2U)
<> 161:2cc1468da177 15102 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15103 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
<> 161:2cc1468da177 15104 #define USART_ICR_ORECF_Pos (3U)
<> 161:2cc1468da177 15105 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15106 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
<> 161:2cc1468da177 15107 #define USART_ICR_IDLECF_Pos (4U)
<> 161:2cc1468da177 15108 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15109 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
<> 161:2cc1468da177 15110 #define USART_ICR_TCCF_Pos (6U)
<> 161:2cc1468da177 15111 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 15112 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
<> 161:2cc1468da177 15113 #define USART_ICR_LBDCF_Pos (8U)
<> 161:2cc1468da177 15114 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 15115 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
<> 161:2cc1468da177 15116 #define USART_ICR_CTSCF_Pos (9U)
<> 161:2cc1468da177 15117 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15118 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
<> 161:2cc1468da177 15119 #define USART_ICR_RTOCF_Pos (11U)
<> 161:2cc1468da177 15120 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 15121 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
<> 161:2cc1468da177 15122 #define USART_ICR_EOBCF_Pos (12U)
<> 161:2cc1468da177 15123 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 15124 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
<> 161:2cc1468da177 15125 #define USART_ICR_CMCF_Pos (17U)
<> 161:2cc1468da177 15126 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 15127 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
<> 144:ef7eb2e8f9f7 15128
<> 144:ef7eb2e8f9f7 15129 /******************* Bit definition for USART_RDR register ******************/
<> 161:2cc1468da177 15130 #define USART_RDR_RDR_Pos (0U)
<> 161:2cc1468da177 15131 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
<> 161:2cc1468da177 15132 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
<> 144:ef7eb2e8f9f7 15133
<> 144:ef7eb2e8f9f7 15134 /******************* Bit definition for USART_TDR register ******************/
<> 161:2cc1468da177 15135 #define USART_TDR_TDR_Pos (0U)
<> 161:2cc1468da177 15136 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
<> 161:2cc1468da177 15137 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
<> 144:ef7eb2e8f9f7 15138
<> 144:ef7eb2e8f9f7 15139 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15140 /* */
<> 144:ef7eb2e8f9f7 15141 /* Window WATCHDOG */
<> 144:ef7eb2e8f9f7 15142 /* */
<> 144:ef7eb2e8f9f7 15143 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15144 /******************* Bit definition for WWDG_CR register ********************/
<> 161:2cc1468da177 15145 #define WWDG_CR_T_Pos (0U)
<> 161:2cc1468da177 15146 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
<> 161:2cc1468da177 15147 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 161:2cc1468da177 15148 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
<> 161:2cc1468da177 15149 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
<> 161:2cc1468da177 15150 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
<> 161:2cc1468da177 15151 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
<> 161:2cc1468da177 15152 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
<> 161:2cc1468da177 15153 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
<> 161:2cc1468da177 15154 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
<> 161:2cc1468da177 15155
<> 161:2cc1468da177 15156
<> 161:2cc1468da177 15157 #define WWDG_CR_WDGA_Pos (7U)
<> 161:2cc1468da177 15158 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 15159 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
<> 144:ef7eb2e8f9f7 15160
<> 144:ef7eb2e8f9f7 15161 /******************* Bit definition for WWDG_CFR register *******************/
<> 161:2cc1468da177 15162 #define WWDG_CFR_W_Pos (0U)
<> 161:2cc1468da177 15163 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
<> 161:2cc1468da177 15164 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
<> 161:2cc1468da177 15165 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
<> 161:2cc1468da177 15166 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
<> 161:2cc1468da177 15167 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
<> 161:2cc1468da177 15168 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
<> 161:2cc1468da177 15169 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
<> 161:2cc1468da177 15170 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
<> 161:2cc1468da177 15171 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
<> 161:2cc1468da177 15172
<> 161:2cc1468da177 15173
<> 161:2cc1468da177 15174 #define WWDG_CFR_WDGTB_Pos (7U)
<> 161:2cc1468da177 15175 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
<> 161:2cc1468da177 15176 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
<> 161:2cc1468da177 15177 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
<> 161:2cc1468da177 15178 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
<> 161:2cc1468da177 15179
<> 161:2cc1468da177 15180
<> 161:2cc1468da177 15181 #define WWDG_CFR_EWI_Pos (9U)
<> 161:2cc1468da177 15182 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15183 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
<> 144:ef7eb2e8f9f7 15184
<> 144:ef7eb2e8f9f7 15185 /******************* Bit definition for WWDG_SR register ********************/
<> 161:2cc1468da177 15186 #define WWDG_SR_EWIF_Pos (0U)
<> 161:2cc1468da177 15187 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15188 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
<> 144:ef7eb2e8f9f7 15189
<> 144:ef7eb2e8f9f7 15190 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15191 /* */
<> 144:ef7eb2e8f9f7 15192 /* DBG */
<> 144:ef7eb2e8f9f7 15193 /* */
<> 144:ef7eb2e8f9f7 15194 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15195 /******************** Bit definition for DBGMCU_IDCODE register *************/
<> 161:2cc1468da177 15196 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
<> 161:2cc1468da177 15197 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 15198 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
<> 161:2cc1468da177 15199 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
<> 161:2cc1468da177 15200 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 15201 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
<> 144:ef7eb2e8f9f7 15202
<> 144:ef7eb2e8f9f7 15203 /******************** Bit definition for DBGMCU_CR register *****************/
<> 161:2cc1468da177 15204 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
<> 161:2cc1468da177 15205 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15206 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
<> 161:2cc1468da177 15207 #define DBGMCU_CR_DBG_STOP_Pos (1U)
<> 161:2cc1468da177 15208 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15209 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
<> 161:2cc1468da177 15210 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
<> 161:2cc1468da177 15211 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15212 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
<> 161:2cc1468da177 15213 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
<> 161:2cc1468da177 15214 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15215 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
<> 161:2cc1468da177 15216
<> 161:2cc1468da177 15217 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
<> 161:2cc1468da177 15218 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 15219 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
<> 161:2cc1468da177 15220 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 15221 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 15222
<> 144:ef7eb2e8f9f7 15223 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
<> 161:2cc1468da177 15224 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
<> 161:2cc1468da177 15225 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15226 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
<> 161:2cc1468da177 15227 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
<> 161:2cc1468da177 15228 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15229 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
<> 161:2cc1468da177 15230 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
<> 161:2cc1468da177 15231 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15232 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
<> 161:2cc1468da177 15233 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
<> 161:2cc1468da177 15234 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15235 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
<> 161:2cc1468da177 15236 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
<> 161:2cc1468da177 15237 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15238 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
<> 161:2cc1468da177 15239 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
<> 161:2cc1468da177 15240 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15241 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
<> 161:2cc1468da177 15242 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
<> 161:2cc1468da177 15243 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 15244 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
<> 161:2cc1468da177 15245 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
<> 161:2cc1468da177 15246 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 15247 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
<> 161:2cc1468da177 15248 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
<> 161:2cc1468da177 15249 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 15250 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
<> 161:2cc1468da177 15251 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
<> 161:2cc1468da177 15252 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15253 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
<> 161:2cc1468da177 15254 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
<> 161:2cc1468da177 15255 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 15256 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
<> 161:2cc1468da177 15257 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
<> 161:2cc1468da177 15258 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 15259 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
<> 161:2cc1468da177 15260 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
<> 161:2cc1468da177 15261 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 15262 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
<> 161:2cc1468da177 15263 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (13U)
<> 161:2cc1468da177 15264 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 15265 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
<> 161:2cc1468da177 15266 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
<> 161:2cc1468da177 15267 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 15268 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
<> 161:2cc1468da177 15269 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
<> 161:2cc1468da177 15270 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 15271 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
<> 161:2cc1468da177 15272 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
<> 161:2cc1468da177 15273 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 15274 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
<> 161:2cc1468da177 15275 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
<> 161:2cc1468da177 15276 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 15277 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
<> 161:2cc1468da177 15278 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
<> 161:2cc1468da177 15279 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 15280 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
<> 161:2cc1468da177 15281 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
<> 161:2cc1468da177 15282 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 15283 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
<> 144:ef7eb2e8f9f7 15284
<> 144:ef7eb2e8f9f7 15285 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
<> 161:2cc1468da177 15286 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
<> 161:2cc1468da177 15287 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15288 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
<> 161:2cc1468da177 15289 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
<> 161:2cc1468da177 15290 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15291 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
<> 161:2cc1468da177 15292 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
<> 161:2cc1468da177 15293 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 15294 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
<> 161:2cc1468da177 15295 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
<> 161:2cc1468da177 15296 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 15297 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
<> 161:2cc1468da177 15298 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
<> 161:2cc1468da177 15299 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 15300 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
<> 144:ef7eb2e8f9f7 15301
<> 144:ef7eb2e8f9f7 15302 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15303 /* */
<> 144:ef7eb2e8f9f7 15304 /* Ethernet MAC Registers bits definitions */
<> 144:ef7eb2e8f9f7 15305 /* */
<> 144:ef7eb2e8f9f7 15306 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15307 /* Bit definition for Ethernet MAC Control Register register */
<> 161:2cc1468da177 15308 #define ETH_MACCR_WD_Pos (23U)
<> 161:2cc1468da177 15309 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 15310 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
<> 161:2cc1468da177 15311 #define ETH_MACCR_JD_Pos (22U)
<> 161:2cc1468da177 15312 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 15313 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
<> 161:2cc1468da177 15314 #define ETH_MACCR_IFG_Pos (17U)
<> 161:2cc1468da177 15315 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
<> 161:2cc1468da177 15316 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
<> 161:2cc1468da177 15317 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
<> 161:2cc1468da177 15318 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
<> 161:2cc1468da177 15319 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
<> 161:2cc1468da177 15320 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
<> 161:2cc1468da177 15321 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
<> 161:2cc1468da177 15322 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
<> 161:2cc1468da177 15323 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
<> 161:2cc1468da177 15324 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
<> 161:2cc1468da177 15325 #define ETH_MACCR_CSD_Pos (16U)
<> 161:2cc1468da177 15326 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 15327 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
<> 161:2cc1468da177 15328 #define ETH_MACCR_FES_Pos (14U)
<> 161:2cc1468da177 15329 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 15330 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
<> 161:2cc1468da177 15331 #define ETH_MACCR_ROD_Pos (13U)
<> 161:2cc1468da177 15332 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 15333 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
<> 161:2cc1468da177 15334 #define ETH_MACCR_LM_Pos (12U)
<> 161:2cc1468da177 15335 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 15336 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
<> 161:2cc1468da177 15337 #define ETH_MACCR_DM_Pos (11U)
<> 161:2cc1468da177 15338 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 15339 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
<> 161:2cc1468da177 15340 #define ETH_MACCR_IPCO_Pos (10U)
<> 161:2cc1468da177 15341 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 15342 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
<> 161:2cc1468da177 15343 #define ETH_MACCR_RD_Pos (9U)
<> 161:2cc1468da177 15344 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15345 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
<> 161:2cc1468da177 15346 #define ETH_MACCR_APCS_Pos (7U)
<> 161:2cc1468da177 15347 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 15348 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
<> 161:2cc1468da177 15349 #define ETH_MACCR_BL_Pos (5U)
<> 161:2cc1468da177 15350 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
<> 161:2cc1468da177 15351 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
<> 144:ef7eb2e8f9f7 15352 a transmission attempt during retries after a collision: 0 =< r <2^k */
<> 161:2cc1468da177 15353 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
<> 161:2cc1468da177 15354 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
<> 161:2cc1468da177 15355 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
<> 161:2cc1468da177 15356 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
<> 161:2cc1468da177 15357 #define ETH_MACCR_DC_Pos (4U)
<> 161:2cc1468da177 15358 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15359 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
<> 161:2cc1468da177 15360 #define ETH_MACCR_TE_Pos (3U)
<> 161:2cc1468da177 15361 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15362 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
<> 161:2cc1468da177 15363 #define ETH_MACCR_RE_Pos (2U)
<> 161:2cc1468da177 15364 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15365 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
<> 144:ef7eb2e8f9f7 15366
<> 144:ef7eb2e8f9f7 15367 /* Bit definition for Ethernet MAC Frame Filter Register */
<> 161:2cc1468da177 15368 #define ETH_MACFFR_RA_Pos (31U)
<> 161:2cc1468da177 15369 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 15370 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
<> 161:2cc1468da177 15371 #define ETH_MACFFR_HPF_Pos (10U)
<> 161:2cc1468da177 15372 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 15373 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
<> 161:2cc1468da177 15374 #define ETH_MACFFR_SAF_Pos (9U)
<> 161:2cc1468da177 15375 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15376 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
<> 161:2cc1468da177 15377 #define ETH_MACFFR_SAIF_Pos (8U)
<> 161:2cc1468da177 15378 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 15379 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
<> 161:2cc1468da177 15380 #define ETH_MACFFR_PCF_Pos (6U)
<> 161:2cc1468da177 15381 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 15382 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
<> 161:2cc1468da177 15383 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
<> 161:2cc1468da177 15384 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 15385 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
<> 161:2cc1468da177 15386 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
<> 161:2cc1468da177 15387 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 15388 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
<> 161:2cc1468da177 15389 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
<> 161:2cc1468da177 15390 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 15391 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
<> 161:2cc1468da177 15392 #define ETH_MACFFR_BFD_Pos (5U)
<> 161:2cc1468da177 15393 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15394 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
<> 161:2cc1468da177 15395 #define ETH_MACFFR_PAM_Pos (4U)
<> 161:2cc1468da177 15396 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15397 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
<> 161:2cc1468da177 15398 #define ETH_MACFFR_DAIF_Pos (3U)
<> 161:2cc1468da177 15399 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15400 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
<> 161:2cc1468da177 15401 #define ETH_MACFFR_HM_Pos (2U)
<> 161:2cc1468da177 15402 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15403 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
<> 161:2cc1468da177 15404 #define ETH_MACFFR_HU_Pos (1U)
<> 161:2cc1468da177 15405 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15406 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
<> 161:2cc1468da177 15407 #define ETH_MACFFR_PM_Pos (0U)
<> 161:2cc1468da177 15408 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15409 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
<> 144:ef7eb2e8f9f7 15410
<> 144:ef7eb2e8f9f7 15411 /* Bit definition for Ethernet MAC Hash Table High Register */
<> 161:2cc1468da177 15412 #define ETH_MACHTHR_HTH_Pos (0U)
<> 161:2cc1468da177 15413 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15414 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
<> 144:ef7eb2e8f9f7 15415
<> 144:ef7eb2e8f9f7 15416 /* Bit definition for Ethernet MAC Hash Table Low Register */
<> 161:2cc1468da177 15417 #define ETH_MACHTLR_HTL_Pos (0U)
<> 161:2cc1468da177 15418 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15419 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
<> 144:ef7eb2e8f9f7 15420
<> 144:ef7eb2e8f9f7 15421 /* Bit definition for Ethernet MAC MII Address Register */
<> 161:2cc1468da177 15422 #define ETH_MACMIIAR_PA_Pos (11U)
<> 161:2cc1468da177 15423 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
<> 161:2cc1468da177 15424 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
<> 161:2cc1468da177 15425 #define ETH_MACMIIAR_MR_Pos (6U)
<> 161:2cc1468da177 15426 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
<> 161:2cc1468da177 15427 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
<> 161:2cc1468da177 15428 #define ETH_MACMIIAR_CR_Pos (2U)
<> 161:2cc1468da177 15429 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
<> 161:2cc1468da177 15430 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
<> 161:2cc1468da177 15431 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
<> 161:2cc1468da177 15432 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
<> 161:2cc1468da177 15433 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15434 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
<> 161:2cc1468da177 15435 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
<> 161:2cc1468da177 15436 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15437 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
<> 161:2cc1468da177 15438 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
<> 161:2cc1468da177 15439 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 15440 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
<> 161:2cc1468da177 15441 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
<> 161:2cc1468da177 15442 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15443 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
<> 161:2cc1468da177 15444 #define ETH_MACMIIAR_MW_Pos (1U)
<> 161:2cc1468da177 15445 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15446 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
<> 161:2cc1468da177 15447 #define ETH_MACMIIAR_MB_Pos (0U)
<> 161:2cc1468da177 15448 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15449 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
<> 161:2cc1468da177 15450
<> 144:ef7eb2e8f9f7 15451 /* Bit definition for Ethernet MAC MII Data Register */
<> 161:2cc1468da177 15452 #define ETH_MACMIIDR_MD_Pos (0U)
<> 161:2cc1468da177 15453 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 15454 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
<> 144:ef7eb2e8f9f7 15455
<> 144:ef7eb2e8f9f7 15456 /* Bit definition for Ethernet MAC Flow Control Register */
<> 161:2cc1468da177 15457 #define ETH_MACFCR_PT_Pos (16U)
<> 161:2cc1468da177 15458 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 15459 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
<> 161:2cc1468da177 15460 #define ETH_MACFCR_ZQPD_Pos (7U)
<> 161:2cc1468da177 15461 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 15462 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
<> 161:2cc1468da177 15463 #define ETH_MACFCR_PLT_Pos (4U)
<> 161:2cc1468da177 15464 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 15465 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
<> 161:2cc1468da177 15466 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
<> 161:2cc1468da177 15467 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
<> 161:2cc1468da177 15468 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15469 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
<> 161:2cc1468da177 15470 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
<> 161:2cc1468da177 15471 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15472 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
<> 161:2cc1468da177 15473 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
<> 161:2cc1468da177 15474 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 15475 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
<> 161:2cc1468da177 15476 #define ETH_MACFCR_UPFD_Pos (3U)
<> 161:2cc1468da177 15477 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15478 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
<> 161:2cc1468da177 15479 #define ETH_MACFCR_RFCE_Pos (2U)
<> 161:2cc1468da177 15480 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15481 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
<> 161:2cc1468da177 15482 #define ETH_MACFCR_TFCE_Pos (1U)
<> 161:2cc1468da177 15483 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15484 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
<> 161:2cc1468da177 15485 #define ETH_MACFCR_FCBBPA_Pos (0U)
<> 161:2cc1468da177 15486 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15487 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
<> 144:ef7eb2e8f9f7 15488
<> 144:ef7eb2e8f9f7 15489 /* Bit definition for Ethernet MAC VLAN Tag Register */
<> 161:2cc1468da177 15490 #define ETH_MACVLANTR_VLANTC_Pos (16U)
<> 161:2cc1468da177 15491 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 15492 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
<> 161:2cc1468da177 15493 #define ETH_MACVLANTR_VLANTI_Pos (0U)
<> 161:2cc1468da177 15494 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 15495 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
<> 161:2cc1468da177 15496
<> 161:2cc1468da177 15497 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
<> 161:2cc1468da177 15498 #define ETH_MACRWUFFR_D_Pos (0U)
<> 161:2cc1468da177 15499 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15500 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
<> 144:ef7eb2e8f9f7 15501 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
<> 144:ef7eb2e8f9f7 15502 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
<> 144:ef7eb2e8f9f7 15503 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
<> 144:ef7eb2e8f9f7 15504 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
<> 144:ef7eb2e8f9f7 15505 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
<> 144:ef7eb2e8f9f7 15506 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
<> 161:2cc1468da177 15507 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
<> 144:ef7eb2e8f9f7 15508 RSVD - Filter1 Command - RSVD - Filter0 Command
<> 144:ef7eb2e8f9f7 15509 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
<> 144:ef7eb2e8f9f7 15510 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
<> 144:ef7eb2e8f9f7 15511 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
<> 144:ef7eb2e8f9f7 15512
<> 161:2cc1468da177 15513 /* Bit definition for Ethernet MAC PMT Control and Status Register */
<> 161:2cc1468da177 15514 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
<> 161:2cc1468da177 15515 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 15516 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
<> 161:2cc1468da177 15517 #define ETH_MACPMTCSR_GU_Pos (9U)
<> 161:2cc1468da177 15518 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15519 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
<> 161:2cc1468da177 15520 #define ETH_MACPMTCSR_WFR_Pos (6U)
<> 161:2cc1468da177 15521 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 15522 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
<> 161:2cc1468da177 15523 #define ETH_MACPMTCSR_MPR_Pos (5U)
<> 161:2cc1468da177 15524 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15525 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
<> 161:2cc1468da177 15526 #define ETH_MACPMTCSR_WFE_Pos (2U)
<> 161:2cc1468da177 15527 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15528 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
<> 161:2cc1468da177 15529 #define ETH_MACPMTCSR_MPE_Pos (1U)
<> 161:2cc1468da177 15530 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15531 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
<> 161:2cc1468da177 15532 #define ETH_MACPMTCSR_PD_Pos (0U)
<> 161:2cc1468da177 15533 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15534 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
<> 161:2cc1468da177 15535
<> 161:2cc1468da177 15536 /* Bit definition for Ethernet MAC debug Register */
<> 161:2cc1468da177 15537 #define ETH_MACDBGR_TFF_Pos (25U)
<> 161:2cc1468da177 15538 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 15539 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
<> 161:2cc1468da177 15540 #define ETH_MACDBGR_TFNE_Pos (24U)
<> 161:2cc1468da177 15541 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 15542 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
<> 161:2cc1468da177 15543 #define ETH_MACDBGR_TPWA_Pos (22U)
<> 161:2cc1468da177 15544 #define ETH_MACDBGR_TPWA_Msk (0x1U << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 15545 #define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */
<> 161:2cc1468da177 15546 #define ETH_MACDBGR_TFRS_Pos (20U)
<> 161:2cc1468da177 15547 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 15548 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
<> 161:2cc1468da177 15549 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
<> 161:2cc1468da177 15550 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 15551 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
<> 161:2cc1468da177 15552 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
<> 161:2cc1468da177 15553 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 15554 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
<> 161:2cc1468da177 15555 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
<> 161:2cc1468da177 15556 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 15557 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
<> 161:2cc1468da177 15558 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
<> 161:2cc1468da177 15559 #define ETH_MACDBGR_MTP_Pos (19U)
<> 161:2cc1468da177 15560 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 15561 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
<> 161:2cc1468da177 15562 #define ETH_MACDBGR_MTFCS_Pos (17U)
<> 161:2cc1468da177 15563 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
<> 161:2cc1468da177 15564 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
<> 161:2cc1468da177 15565 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
<> 161:2cc1468da177 15566 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
<> 161:2cc1468da177 15567 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
<> 161:2cc1468da177 15568 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
<> 161:2cc1468da177 15569 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 15570 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
<> 161:2cc1468da177 15571 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
<> 161:2cc1468da177 15572 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 15573 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
<> 161:2cc1468da177 15574 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
<> 161:2cc1468da177 15575 #define ETH_MACDBGR_MMTEA_Pos (16U)
<> 161:2cc1468da177 15576 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 15577 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
<> 161:2cc1468da177 15578 #define ETH_MACDBGR_RFFL_Pos (8U)
<> 161:2cc1468da177 15579 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 15580 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
<> 161:2cc1468da177 15581 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
<> 161:2cc1468da177 15582 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
<> 161:2cc1468da177 15583 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
<> 161:2cc1468da177 15584 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
<> 161:2cc1468da177 15585 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15586 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
<> 161:2cc1468da177 15587 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
<> 161:2cc1468da177 15588 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 15589 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
<> 161:2cc1468da177 15590 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
<> 161:2cc1468da177 15591 #define ETH_MACDBGR_RFRCS_Pos (5U)
<> 161:2cc1468da177 15592 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
<> 161:2cc1468da177 15593 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
<> 161:2cc1468da177 15594 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
<> 161:2cc1468da177 15595 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
<> 161:2cc1468da177 15596 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
<> 161:2cc1468da177 15597 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
<> 161:2cc1468da177 15598 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 15599 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
<> 161:2cc1468da177 15600 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
<> 161:2cc1468da177 15601 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15602 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
<> 161:2cc1468da177 15603 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
<> 161:2cc1468da177 15604 #define ETH_MACDBGR_RFWRA_Pos (4U)
<> 161:2cc1468da177 15605 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15606 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
<> 161:2cc1468da177 15607 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
<> 161:2cc1468da177 15608 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
<> 161:2cc1468da177 15609 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
<> 161:2cc1468da177 15610 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15611 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15612 #define ETH_MACDBGR_MMRPEA_Pos (0U)
<> 161:2cc1468da177 15613 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15614 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
<> 144:ef7eb2e8f9f7 15615
<> 144:ef7eb2e8f9f7 15616 /* Bit definition for Ethernet MAC Status Register */
<> 161:2cc1468da177 15617 #define ETH_MACSR_TSTS_Pos (9U)
<> 161:2cc1468da177 15618 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15619 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
<> 161:2cc1468da177 15620 #define ETH_MACSR_MMCTS_Pos (6U)
<> 161:2cc1468da177 15621 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 15622 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
<> 161:2cc1468da177 15623 #define ETH_MACSR_MMMCRS_Pos (5U)
<> 161:2cc1468da177 15624 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15625 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
<> 161:2cc1468da177 15626 #define ETH_MACSR_MMCS_Pos (4U)
<> 161:2cc1468da177 15627 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15628 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
<> 161:2cc1468da177 15629 #define ETH_MACSR_PMTS_Pos (3U)
<> 161:2cc1468da177 15630 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15631 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
<> 144:ef7eb2e8f9f7 15632
<> 144:ef7eb2e8f9f7 15633 /* Bit definition for Ethernet MAC Interrupt Mask Register */
<> 161:2cc1468da177 15634 #define ETH_MACIMR_TSTIM_Pos (9U)
<> 161:2cc1468da177 15635 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15636 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
<> 161:2cc1468da177 15637 #define ETH_MACIMR_PMTIM_Pos (3U)
<> 161:2cc1468da177 15638 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15639 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
<> 144:ef7eb2e8f9f7 15640
<> 144:ef7eb2e8f9f7 15641 /* Bit definition for Ethernet MAC Address0 High Register */
<> 161:2cc1468da177 15642 #define ETH_MACA0HR_MACA0H_Pos (0U)
<> 161:2cc1468da177 15643 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 15644 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
<> 144:ef7eb2e8f9f7 15645
<> 144:ef7eb2e8f9f7 15646 /* Bit definition for Ethernet MAC Address0 Low Register */
<> 161:2cc1468da177 15647 #define ETH_MACA0LR_MACA0L_Pos (0U)
<> 161:2cc1468da177 15648 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15649 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
<> 144:ef7eb2e8f9f7 15650
<> 144:ef7eb2e8f9f7 15651 /* Bit definition for Ethernet MAC Address1 High Register */
<> 161:2cc1468da177 15652 #define ETH_MACA1HR_AE_Pos (31U)
<> 161:2cc1468da177 15653 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 15654 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
<> 161:2cc1468da177 15655 #define ETH_MACA1HR_SA_Pos (30U)
<> 161:2cc1468da177 15656 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 15657 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
<> 161:2cc1468da177 15658 #define ETH_MACA1HR_MBC_Pos (24U)
<> 161:2cc1468da177 15659 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
<> 161:2cc1468da177 15660 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
<> 161:2cc1468da177 15661 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 161:2cc1468da177 15662 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 161:2cc1468da177 15663 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 161:2cc1468da177 15664 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 161:2cc1468da177 15665 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 161:2cc1468da177 15666 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
<> 161:2cc1468da177 15667 #define ETH_MACA1HR_MACA1H_Pos (0U)
<> 161:2cc1468da177 15668 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 15669 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
<> 144:ef7eb2e8f9f7 15670
<> 144:ef7eb2e8f9f7 15671 /* Bit definition for Ethernet MAC Address1 Low Register */
<> 161:2cc1468da177 15672 #define ETH_MACA1LR_MACA1L_Pos (0U)
<> 161:2cc1468da177 15673 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15674 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
<> 144:ef7eb2e8f9f7 15675
<> 144:ef7eb2e8f9f7 15676 /* Bit definition for Ethernet MAC Address2 High Register */
<> 161:2cc1468da177 15677 #define ETH_MACA2HR_AE_Pos (31U)
<> 161:2cc1468da177 15678 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 15679 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
<> 161:2cc1468da177 15680 #define ETH_MACA2HR_SA_Pos (30U)
<> 161:2cc1468da177 15681 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 15682 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
<> 161:2cc1468da177 15683 #define ETH_MACA2HR_MBC_Pos (24U)
<> 161:2cc1468da177 15684 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
<> 161:2cc1468da177 15685 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
<> 161:2cc1468da177 15686 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 161:2cc1468da177 15687 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 161:2cc1468da177 15688 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 161:2cc1468da177 15689 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 161:2cc1468da177 15690 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 161:2cc1468da177 15691 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
<> 161:2cc1468da177 15692 #define ETH_MACA2HR_MACA2H_Pos (0U)
<> 161:2cc1468da177 15693 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 15694 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
<> 144:ef7eb2e8f9f7 15695
<> 144:ef7eb2e8f9f7 15696 /* Bit definition for Ethernet MAC Address2 Low Register */
<> 161:2cc1468da177 15697 #define ETH_MACA2LR_MACA2L_Pos (0U)
<> 161:2cc1468da177 15698 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15699 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
<> 144:ef7eb2e8f9f7 15700
<> 144:ef7eb2e8f9f7 15701 /* Bit definition for Ethernet MAC Address3 High Register */
<> 161:2cc1468da177 15702 #define ETH_MACA3HR_AE_Pos (31U)
<> 161:2cc1468da177 15703 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 15704 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
<> 161:2cc1468da177 15705 #define ETH_MACA3HR_SA_Pos (30U)
<> 161:2cc1468da177 15706 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 15707 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
<> 161:2cc1468da177 15708 #define ETH_MACA3HR_MBC_Pos (24U)
<> 161:2cc1468da177 15709 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
<> 161:2cc1468da177 15710 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
<> 161:2cc1468da177 15711 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 161:2cc1468da177 15712 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 161:2cc1468da177 15713 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 161:2cc1468da177 15714 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 161:2cc1468da177 15715 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 161:2cc1468da177 15716 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
<> 161:2cc1468da177 15717 #define ETH_MACA3HR_MACA3H_Pos (0U)
<> 161:2cc1468da177 15718 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 15719 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
<> 144:ef7eb2e8f9f7 15720
<> 144:ef7eb2e8f9f7 15721 /* Bit definition for Ethernet MAC Address3 Low Register */
<> 161:2cc1468da177 15722 #define ETH_MACA3LR_MACA3L_Pos (0U)
<> 161:2cc1468da177 15723 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15724 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
<> 144:ef7eb2e8f9f7 15725
<> 144:ef7eb2e8f9f7 15726 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15727 /* Ethernet MMC Registers bits definition */
<> 144:ef7eb2e8f9f7 15728 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15729
<> 144:ef7eb2e8f9f7 15730 /* Bit definition for Ethernet MMC Contol Register */
<> 161:2cc1468da177 15731 #define ETH_MMCCR_MCFHP_Pos (5U)
<> 161:2cc1468da177 15732 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15733 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
<> 161:2cc1468da177 15734 #define ETH_MMCCR_MCP_Pos (4U)
<> 161:2cc1468da177 15735 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15736 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
<> 161:2cc1468da177 15737 #define ETH_MMCCR_MCF_Pos (3U)
<> 161:2cc1468da177 15738 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15739 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
<> 161:2cc1468da177 15740 #define ETH_MMCCR_ROR_Pos (2U)
<> 161:2cc1468da177 15741 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15742 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
<> 161:2cc1468da177 15743 #define ETH_MMCCR_CSR_Pos (1U)
<> 161:2cc1468da177 15744 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15745 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
<> 161:2cc1468da177 15746 #define ETH_MMCCR_CR_Pos (0U)
<> 161:2cc1468da177 15747 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15748 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
<> 144:ef7eb2e8f9f7 15749
<> 144:ef7eb2e8f9f7 15750 /* Bit definition for Ethernet MMC Receive Interrupt Register */
<> 161:2cc1468da177 15751 #define ETH_MMCRIR_RGUFS_Pos (17U)
<> 161:2cc1468da177 15752 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 15753 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
<> 161:2cc1468da177 15754 #define ETH_MMCRIR_RFAES_Pos (6U)
<> 161:2cc1468da177 15755 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 15756 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
<> 161:2cc1468da177 15757 #define ETH_MMCRIR_RFCES_Pos (5U)
<> 161:2cc1468da177 15758 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15759 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 15760
<> 144:ef7eb2e8f9f7 15761 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
<> 161:2cc1468da177 15762 #define ETH_MMCTIR_TGFS_Pos (21U)
<> 161:2cc1468da177 15763 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 15764 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
<> 161:2cc1468da177 15765 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
<> 161:2cc1468da177 15766 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 15767 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
<> 161:2cc1468da177 15768 #define ETH_MMCTIR_TGFSCS_Pos (14U)
<> 161:2cc1468da177 15769 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 15770 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 15771
<> 144:ef7eb2e8f9f7 15772 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
<> 161:2cc1468da177 15773 #define ETH_MMCRIMR_RGUFM_Pos (17U)
<> 161:2cc1468da177 15774 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 15775 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
<> 161:2cc1468da177 15776 #define ETH_MMCRIMR_RFAEM_Pos (6U)
<> 161:2cc1468da177 15777 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 15778 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
<> 161:2cc1468da177 15779 #define ETH_MMCRIMR_RFCEM_Pos (5U)
<> 161:2cc1468da177 15780 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15781 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 15782
<> 144:ef7eb2e8f9f7 15783 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
<> 161:2cc1468da177 15784 #define ETH_MMCTIMR_TGFM_Pos (21U)
<> 161:2cc1468da177 15785 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 15786 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
<> 161:2cc1468da177 15787 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
<> 161:2cc1468da177 15788 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 15789 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
<> 161:2cc1468da177 15790 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
<> 161:2cc1468da177 15791 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 15792 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 15793
<> 144:ef7eb2e8f9f7 15794 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
<> 161:2cc1468da177 15795 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
<> 161:2cc1468da177 15796 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15797 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
<> 144:ef7eb2e8f9f7 15798
<> 144:ef7eb2e8f9f7 15799 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
<> 161:2cc1468da177 15800 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
<> 161:2cc1468da177 15801 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15802 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
<> 144:ef7eb2e8f9f7 15803
<> 144:ef7eb2e8f9f7 15804 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
<> 161:2cc1468da177 15805 #define ETH_MMCTGFCR_TGFC_Pos (0U)
<> 161:2cc1468da177 15806 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15807 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
<> 144:ef7eb2e8f9f7 15808
<> 144:ef7eb2e8f9f7 15809 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
<> 161:2cc1468da177 15810 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
<> 161:2cc1468da177 15811 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15812 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
<> 144:ef7eb2e8f9f7 15813
<> 144:ef7eb2e8f9f7 15814 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
<> 161:2cc1468da177 15815 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
<> 161:2cc1468da177 15816 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15817 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
<> 144:ef7eb2e8f9f7 15818
<> 144:ef7eb2e8f9f7 15819 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
<> 161:2cc1468da177 15820 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
<> 161:2cc1468da177 15821 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15822 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
<> 144:ef7eb2e8f9f7 15823
<> 144:ef7eb2e8f9f7 15824 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15825 /* Ethernet PTP Registers bits definition */
<> 144:ef7eb2e8f9f7 15826 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15827
<> 144:ef7eb2e8f9f7 15828 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
<> 161:2cc1468da177 15829 #define ETH_PTPTSCR_TSCNT_Pos (16U)
<> 161:2cc1468da177 15830 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
<> 161:2cc1468da177 15831 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
<> 161:2cc1468da177 15832 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
<> 161:2cc1468da177 15833 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 15834 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
<> 161:2cc1468da177 15835 #define ETH_PTPTSSR_TSSEME_Pos (14U)
<> 161:2cc1468da177 15836 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 15837 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
<> 161:2cc1468da177 15838 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
<> 161:2cc1468da177 15839 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 15840 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
<> 161:2cc1468da177 15841 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
<> 161:2cc1468da177 15842 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 15843 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
<> 161:2cc1468da177 15844 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
<> 161:2cc1468da177 15845 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 15846 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
<> 161:2cc1468da177 15847 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
<> 161:2cc1468da177 15848 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 15849 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
<> 161:2cc1468da177 15850 #define ETH_PTPTSSR_TSSSR_Pos (9U)
<> 161:2cc1468da177 15851 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 15852 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
<> 161:2cc1468da177 15853 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
<> 161:2cc1468da177 15854 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 15855 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
<> 161:2cc1468da177 15856
<> 161:2cc1468da177 15857 #define ETH_PTPTSCR_TSARU_Pos (5U)
<> 161:2cc1468da177 15858 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15859 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
<> 161:2cc1468da177 15860 #define ETH_PTPTSCR_TSITE_Pos (4U)
<> 161:2cc1468da177 15861 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15862 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
<> 161:2cc1468da177 15863 #define ETH_PTPTSCR_TSSTU_Pos (3U)
<> 161:2cc1468da177 15864 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 15865 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
<> 161:2cc1468da177 15866 #define ETH_PTPTSCR_TSSTI_Pos (2U)
<> 161:2cc1468da177 15867 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 15868 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
<> 161:2cc1468da177 15869 #define ETH_PTPTSCR_TSFCU_Pos (1U)
<> 161:2cc1468da177 15870 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15871 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
<> 161:2cc1468da177 15872 #define ETH_PTPTSCR_TSE_Pos (0U)
<> 161:2cc1468da177 15873 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15874 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
<> 144:ef7eb2e8f9f7 15875
<> 144:ef7eb2e8f9f7 15876 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
<> 161:2cc1468da177 15877 #define ETH_PTPSSIR_STSSI_Pos (0U)
<> 161:2cc1468da177 15878 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
<> 161:2cc1468da177 15879 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
<> 144:ef7eb2e8f9f7 15880
<> 144:ef7eb2e8f9f7 15881 /* Bit definition for Ethernet PTP Time Stamp High Register */
<> 161:2cc1468da177 15882 #define ETH_PTPTSHR_STS_Pos (0U)
<> 161:2cc1468da177 15883 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15884 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
<> 144:ef7eb2e8f9f7 15885
<> 144:ef7eb2e8f9f7 15886 /* Bit definition for Ethernet PTP Time Stamp Low Register */
<> 161:2cc1468da177 15887 #define ETH_PTPTSLR_STPNS_Pos (31U)
<> 161:2cc1468da177 15888 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 15889 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
<> 161:2cc1468da177 15890 #define ETH_PTPTSLR_STSS_Pos (0U)
<> 161:2cc1468da177 15891 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
<> 161:2cc1468da177 15892 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
<> 144:ef7eb2e8f9f7 15893
<> 144:ef7eb2e8f9f7 15894 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
<> 161:2cc1468da177 15895 #define ETH_PTPTSHUR_TSUS_Pos (0U)
<> 161:2cc1468da177 15896 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15897 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
<> 144:ef7eb2e8f9f7 15898
<> 144:ef7eb2e8f9f7 15899 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
<> 161:2cc1468da177 15900 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
<> 161:2cc1468da177 15901 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 15902 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
<> 161:2cc1468da177 15903 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
<> 161:2cc1468da177 15904 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
<> 161:2cc1468da177 15905 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
<> 144:ef7eb2e8f9f7 15906
<> 144:ef7eb2e8f9f7 15907 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
<> 161:2cc1468da177 15908 #define ETH_PTPTSAR_TSA_Pos (0U)
<> 161:2cc1468da177 15909 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15910 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
<> 144:ef7eb2e8f9f7 15911
<> 144:ef7eb2e8f9f7 15912 /* Bit definition for Ethernet PTP Target Time High Register */
<> 161:2cc1468da177 15913 #define ETH_PTPTTHR_TTSH_Pos (0U)
<> 161:2cc1468da177 15914 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15915 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
<> 144:ef7eb2e8f9f7 15916
<> 144:ef7eb2e8f9f7 15917 /* Bit definition for Ethernet PTP Target Time Low Register */
<> 161:2cc1468da177 15918 #define ETH_PTPTTLR_TTSL_Pos (0U)
<> 161:2cc1468da177 15919 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 15920 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
<> 144:ef7eb2e8f9f7 15921
<> 144:ef7eb2e8f9f7 15922 /* Bit definition for Ethernet PTP Time Stamp Status Register */
<> 161:2cc1468da177 15923 #define ETH_PTPTSSR_TSTTR_Pos (5U)
<> 161:2cc1468da177 15924 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 15925 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
<> 161:2cc1468da177 15926 #define ETH_PTPTSSR_TSSO_Pos (4U)
<> 161:2cc1468da177 15927 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 15928 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
<> 144:ef7eb2e8f9f7 15929
<> 144:ef7eb2e8f9f7 15930 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15931 /* Ethernet DMA Registers bits definition */
<> 144:ef7eb2e8f9f7 15932 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15933
<> 144:ef7eb2e8f9f7 15934 /* Bit definition for Ethernet DMA Bus Mode Register */
<> 161:2cc1468da177 15935 #define ETH_DMABMR_AAB_Pos (25U)
<> 161:2cc1468da177 15936 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 15937 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
<> 161:2cc1468da177 15938 #define ETH_DMABMR_FPM_Pos (24U)
<> 161:2cc1468da177 15939 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 15940 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
<> 161:2cc1468da177 15941 #define ETH_DMABMR_USP_Pos (23U)
<> 161:2cc1468da177 15942 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 15943 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
<> 161:2cc1468da177 15944 #define ETH_DMABMR_RDP_Pos (17U)
<> 161:2cc1468da177 15945 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
<> 161:2cc1468da177 15946 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
<> 161:2cc1468da177 15947 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
<> 161:2cc1468da177 15948 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
<> 161:2cc1468da177 15949 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 161:2cc1468da177 15950 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 161:2cc1468da177 15951 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 161:2cc1468da177 15952 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 161:2cc1468da177 15953 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 161:2cc1468da177 15954 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 161:2cc1468da177 15955 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 161:2cc1468da177 15956 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 161:2cc1468da177 15957 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
<> 161:2cc1468da177 15958 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
<> 161:2cc1468da177 15959 #define ETH_DMABMR_FB_Pos (16U)
<> 161:2cc1468da177 15960 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 15961 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
<> 161:2cc1468da177 15962 #define ETH_DMABMR_RTPR_Pos (14U)
<> 161:2cc1468da177 15963 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 15964 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
<> 161:2cc1468da177 15965 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
<> 161:2cc1468da177 15966 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
<> 161:2cc1468da177 15967 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
<> 161:2cc1468da177 15968 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
<> 161:2cc1468da177 15969 #define ETH_DMABMR_PBL_Pos (8U)
<> 161:2cc1468da177 15970 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
<> 161:2cc1468da177 15971 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
<> 161:2cc1468da177 15972 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
<> 161:2cc1468da177 15973 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
<> 161:2cc1468da177 15974 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 161:2cc1468da177 15975 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 161:2cc1468da177 15976 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 161:2cc1468da177 15977 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 161:2cc1468da177 15978 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 161:2cc1468da177 15979 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 161:2cc1468da177 15980 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 161:2cc1468da177 15981 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 161:2cc1468da177 15982 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
<> 161:2cc1468da177 15983 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
<> 161:2cc1468da177 15984 #define ETH_DMABMR_EDE_Pos (7U)
<> 161:2cc1468da177 15985 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 15986 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
<> 161:2cc1468da177 15987 #define ETH_DMABMR_DSL_Pos (2U)
<> 161:2cc1468da177 15988 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
<> 161:2cc1468da177 15989 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
<> 161:2cc1468da177 15990 #define ETH_DMABMR_DA_Pos (1U)
<> 161:2cc1468da177 15991 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 15992 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
<> 161:2cc1468da177 15993 #define ETH_DMABMR_SR_Pos (0U)
<> 161:2cc1468da177 15994 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 15995 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
<> 144:ef7eb2e8f9f7 15996
<> 144:ef7eb2e8f9f7 15997 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
<> 161:2cc1468da177 15998 #define ETH_DMATPDR_TPD_Pos (0U)
<> 161:2cc1468da177 15999 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 16000 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
<> 144:ef7eb2e8f9f7 16001
<> 144:ef7eb2e8f9f7 16002 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
<> 161:2cc1468da177 16003 #define ETH_DMARPDR_RPD_Pos (0U)
<> 161:2cc1468da177 16004 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 16005 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
<> 144:ef7eb2e8f9f7 16006
<> 144:ef7eb2e8f9f7 16007 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
<> 161:2cc1468da177 16008 #define ETH_DMARDLAR_SRL_Pos (0U)
<> 161:2cc1468da177 16009 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 16010 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
<> 144:ef7eb2e8f9f7 16011
<> 144:ef7eb2e8f9f7 16012 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
<> 161:2cc1468da177 16013 #define ETH_DMATDLAR_STL_Pos (0U)
<> 161:2cc1468da177 16014 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 16015 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
<> 144:ef7eb2e8f9f7 16016
<> 144:ef7eb2e8f9f7 16017 /* Bit definition for Ethernet DMA Status Register */
<> 161:2cc1468da177 16018 #define ETH_DMASR_TSTS_Pos (29U)
<> 161:2cc1468da177 16019 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 16020 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
<> 161:2cc1468da177 16021 #define ETH_DMASR_PMTS_Pos (28U)
<> 161:2cc1468da177 16022 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 16023 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
<> 161:2cc1468da177 16024 #define ETH_DMASR_MMCS_Pos (27U)
<> 161:2cc1468da177 16025 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 16026 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
<> 161:2cc1468da177 16027 #define ETH_DMASR_EBS_Pos (23U)
<> 161:2cc1468da177 16028 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
<> 161:2cc1468da177 16029 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
<> 144:ef7eb2e8f9f7 16030 /* combination with EBS[2:0] for GetFlagStatus function */
<> 161:2cc1468da177 16031 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
<> 161:2cc1468da177 16032 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 16033 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
<> 161:2cc1468da177 16034 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
<> 161:2cc1468da177 16035 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 16036 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
<> 161:2cc1468da177 16037 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
<> 161:2cc1468da177 16038 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 16039 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
<> 161:2cc1468da177 16040 #define ETH_DMASR_TPS_Pos (20U)
<> 161:2cc1468da177 16041 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
<> 161:2cc1468da177 16042 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
<> 161:2cc1468da177 16043 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
<> 161:2cc1468da177 16044 #define ETH_DMASR_TPS_Fetching_Pos (20U)
<> 161:2cc1468da177 16045 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16046 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
<> 161:2cc1468da177 16047 #define ETH_DMASR_TPS_Waiting_Pos (21U)
<> 161:2cc1468da177 16048 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 16049 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
<> 161:2cc1468da177 16050 #define ETH_DMASR_TPS_Reading_Pos (20U)
<> 161:2cc1468da177 16051 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 16052 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
<> 161:2cc1468da177 16053 #define ETH_DMASR_TPS_Suspended_Pos (21U)
<> 161:2cc1468da177 16054 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
<> 161:2cc1468da177 16055 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
<> 161:2cc1468da177 16056 #define ETH_DMASR_TPS_Closing_Pos (20U)
<> 161:2cc1468da177 16057 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
<> 161:2cc1468da177 16058 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
<> 161:2cc1468da177 16059 #define ETH_DMASR_RPS_Pos (17U)
<> 161:2cc1468da177 16060 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
<> 161:2cc1468da177 16061 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
<> 161:2cc1468da177 16062 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
<> 161:2cc1468da177 16063 #define ETH_DMASR_RPS_Fetching_Pos (17U)
<> 161:2cc1468da177 16064 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 16065 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
<> 161:2cc1468da177 16066 #define ETH_DMASR_RPS_Waiting_Pos (17U)
<> 161:2cc1468da177 16067 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
<> 161:2cc1468da177 16068 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
<> 161:2cc1468da177 16069 #define ETH_DMASR_RPS_Suspended_Pos (19U)
<> 161:2cc1468da177 16070 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 16071 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
<> 161:2cc1468da177 16072 #define ETH_DMASR_RPS_Closing_Pos (17U)
<> 161:2cc1468da177 16073 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
<> 161:2cc1468da177 16074 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
<> 161:2cc1468da177 16075 #define ETH_DMASR_RPS_Queuing_Pos (17U)
<> 161:2cc1468da177 16076 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
<> 161:2cc1468da177 16077 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
<> 161:2cc1468da177 16078 #define ETH_DMASR_NIS_Pos (16U)
<> 161:2cc1468da177 16079 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 16080 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
<> 161:2cc1468da177 16081 #define ETH_DMASR_AIS_Pos (15U)
<> 161:2cc1468da177 16082 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 16083 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
<> 161:2cc1468da177 16084 #define ETH_DMASR_ERS_Pos (14U)
<> 161:2cc1468da177 16085 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 16086 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
<> 161:2cc1468da177 16087 #define ETH_DMASR_FBES_Pos (13U)
<> 161:2cc1468da177 16088 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 16089 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
<> 161:2cc1468da177 16090 #define ETH_DMASR_ETS_Pos (10U)
<> 161:2cc1468da177 16091 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 16092 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
<> 161:2cc1468da177 16093 #define ETH_DMASR_RWTS_Pos (9U)
<> 161:2cc1468da177 16094 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 16095 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
<> 161:2cc1468da177 16096 #define ETH_DMASR_RPSS_Pos (8U)
<> 161:2cc1468da177 16097 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16098 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
<> 161:2cc1468da177 16099 #define ETH_DMASR_RBUS_Pos (7U)
<> 161:2cc1468da177 16100 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 16101 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
<> 161:2cc1468da177 16102 #define ETH_DMASR_RS_Pos (6U)
<> 161:2cc1468da177 16103 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16104 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
<> 161:2cc1468da177 16105 #define ETH_DMASR_TUS_Pos (5U)
<> 161:2cc1468da177 16106 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16107 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
<> 161:2cc1468da177 16108 #define ETH_DMASR_ROS_Pos (4U)
<> 161:2cc1468da177 16109 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16110 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
<> 161:2cc1468da177 16111 #define ETH_DMASR_TJTS_Pos (3U)
<> 161:2cc1468da177 16112 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16113 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
<> 161:2cc1468da177 16114 #define ETH_DMASR_TBUS_Pos (2U)
<> 161:2cc1468da177 16115 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16116 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
<> 161:2cc1468da177 16117 #define ETH_DMASR_TPSS_Pos (1U)
<> 161:2cc1468da177 16118 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16119 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
<> 161:2cc1468da177 16120 #define ETH_DMASR_TS_Pos (0U)
<> 161:2cc1468da177 16121 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16122 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
<> 144:ef7eb2e8f9f7 16123
<> 144:ef7eb2e8f9f7 16124 /* Bit definition for Ethernet DMA Operation Mode Register */
<> 161:2cc1468da177 16125 #define ETH_DMAOMR_DTCEFD_Pos (26U)
<> 161:2cc1468da177 16126 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 16127 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
<> 161:2cc1468da177 16128 #define ETH_DMAOMR_RSF_Pos (25U)
<> 161:2cc1468da177 16129 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 16130 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
<> 161:2cc1468da177 16131 #define ETH_DMAOMR_DFRF_Pos (24U)
<> 161:2cc1468da177 16132 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 16133 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
<> 161:2cc1468da177 16134 #define ETH_DMAOMR_TSF_Pos (21U)
<> 161:2cc1468da177 16135 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 16136 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
<> 161:2cc1468da177 16137 #define ETH_DMAOMR_FTF_Pos (20U)
<> 161:2cc1468da177 16138 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16139 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
<> 161:2cc1468da177 16140 #define ETH_DMAOMR_TTC_Pos (14U)
<> 161:2cc1468da177 16141 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
<> 161:2cc1468da177 16142 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
<> 161:2cc1468da177 16143 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
<> 161:2cc1468da177 16144 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
<> 161:2cc1468da177 16145 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
<> 161:2cc1468da177 16146 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
<> 161:2cc1468da177 16147 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
<> 161:2cc1468da177 16148 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
<> 161:2cc1468da177 16149 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
<> 161:2cc1468da177 16150 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
<> 161:2cc1468da177 16151 #define ETH_DMAOMR_ST_Pos (13U)
<> 161:2cc1468da177 16152 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 16153 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
<> 161:2cc1468da177 16154 #define ETH_DMAOMR_FEF_Pos (7U)
<> 161:2cc1468da177 16155 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 16156 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
<> 161:2cc1468da177 16157 #define ETH_DMAOMR_FUGF_Pos (6U)
<> 161:2cc1468da177 16158 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16159 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
<> 161:2cc1468da177 16160 #define ETH_DMAOMR_RTC_Pos (3U)
<> 161:2cc1468da177 16161 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
<> 161:2cc1468da177 16162 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
<> 161:2cc1468da177 16163 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
<> 161:2cc1468da177 16164 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
<> 161:2cc1468da177 16165 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
<> 161:2cc1468da177 16166 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
<> 161:2cc1468da177 16167 #define ETH_DMAOMR_OSF_Pos (2U)
<> 161:2cc1468da177 16168 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16169 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
<> 161:2cc1468da177 16170 #define ETH_DMAOMR_SR_Pos (1U)
<> 161:2cc1468da177 16171 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16172 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
<> 144:ef7eb2e8f9f7 16173
<> 144:ef7eb2e8f9f7 16174 /* Bit definition for Ethernet DMA Interrupt Enable Register */
<> 161:2cc1468da177 16175 #define ETH_DMAIER_NISE_Pos (16U)
<> 161:2cc1468da177 16176 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 16177 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
<> 161:2cc1468da177 16178 #define ETH_DMAIER_AISE_Pos (15U)
<> 161:2cc1468da177 16179 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 16180 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
<> 161:2cc1468da177 16181 #define ETH_DMAIER_ERIE_Pos (14U)
<> 161:2cc1468da177 16182 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 16183 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
<> 161:2cc1468da177 16184 #define ETH_DMAIER_FBEIE_Pos (13U)
<> 161:2cc1468da177 16185 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 16186 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
<> 161:2cc1468da177 16187 #define ETH_DMAIER_ETIE_Pos (10U)
<> 161:2cc1468da177 16188 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 16189 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
<> 161:2cc1468da177 16190 #define ETH_DMAIER_RWTIE_Pos (9U)
<> 161:2cc1468da177 16191 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 16192 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
<> 161:2cc1468da177 16193 #define ETH_DMAIER_RPSIE_Pos (8U)
<> 161:2cc1468da177 16194 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16195 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
<> 161:2cc1468da177 16196 #define ETH_DMAIER_RBUIE_Pos (7U)
<> 161:2cc1468da177 16197 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 16198 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
<> 161:2cc1468da177 16199 #define ETH_DMAIER_RIE_Pos (6U)
<> 161:2cc1468da177 16200 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16201 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
<> 161:2cc1468da177 16202 #define ETH_DMAIER_TUIE_Pos (5U)
<> 161:2cc1468da177 16203 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16204 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
<> 161:2cc1468da177 16205 #define ETH_DMAIER_ROIE_Pos (4U)
<> 161:2cc1468da177 16206 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16207 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
<> 161:2cc1468da177 16208 #define ETH_DMAIER_TJTIE_Pos (3U)
<> 161:2cc1468da177 16209 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16210 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
<> 161:2cc1468da177 16211 #define ETH_DMAIER_TBUIE_Pos (2U)
<> 161:2cc1468da177 16212 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16213 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
<> 161:2cc1468da177 16214 #define ETH_DMAIER_TPSIE_Pos (1U)
<> 161:2cc1468da177 16215 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16216 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
<> 161:2cc1468da177 16217 #define ETH_DMAIER_TIE_Pos (0U)
<> 161:2cc1468da177 16218 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16219 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
<> 144:ef7eb2e8f9f7 16220
<> 144:ef7eb2e8f9f7 16221 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
<> 161:2cc1468da177 16222 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
<> 161:2cc1468da177 16223 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 16224 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
<> 161:2cc1468da177 16225 #define ETH_DMAMFBOCR_MFA_Pos (17U)
<> 161:2cc1468da177 16226 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
<> 161:2cc1468da177 16227 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
<> 161:2cc1468da177 16228 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
<> 161:2cc1468da177 16229 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 16230 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
<> 161:2cc1468da177 16231 #define ETH_DMAMFBOCR_MFC_Pos (0U)
<> 161:2cc1468da177 16232 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16233 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
<> 144:ef7eb2e8f9f7 16234
<> 144:ef7eb2e8f9f7 16235 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
<> 161:2cc1468da177 16236 #define ETH_DMACHTDR_HTDAP_Pos (0U)
<> 161:2cc1468da177 16237 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 16238 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
<> 144:ef7eb2e8f9f7 16239
<> 144:ef7eb2e8f9f7 16240 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
<> 161:2cc1468da177 16241 #define ETH_DMACHRDR_HRDAP_Pos (0U)
<> 161:2cc1468da177 16242 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 16243 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
<> 144:ef7eb2e8f9f7 16244
<> 144:ef7eb2e8f9f7 16245 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
<> 161:2cc1468da177 16246 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
<> 161:2cc1468da177 16247 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 16248 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
<> 144:ef7eb2e8f9f7 16249
<> 144:ef7eb2e8f9f7 16250 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
<> 161:2cc1468da177 16251 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
<> 161:2cc1468da177 16252 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 16253 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
<> 144:ef7eb2e8f9f7 16254
<> 144:ef7eb2e8f9f7 16255 /******************************************************************************/
<> 144:ef7eb2e8f9f7 16256 /* */
<> 144:ef7eb2e8f9f7 16257 /* USB_OTG */
<> 144:ef7eb2e8f9f7 16258 /* */
<> 144:ef7eb2e8f9f7 16259 /******************************************************************************/
<> 144:ef7eb2e8f9f7 16260 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
<> 161:2cc1468da177 16261 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
<> 161:2cc1468da177 16262 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16263 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
<> 161:2cc1468da177 16264 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
<> 161:2cc1468da177 16265 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16266 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
<> 161:2cc1468da177 16267 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
<> 161:2cc1468da177 16268 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16269 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
<> 161:2cc1468da177 16270 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
<> 161:2cc1468da177 16271 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16272 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
<> 161:2cc1468da177 16273 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
<> 161:2cc1468da177 16274 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16275 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
<> 161:2cc1468da177 16276 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
<> 161:2cc1468da177 16277 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16278 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
<> 161:2cc1468da177 16279 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
<> 161:2cc1468da177 16280 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16281 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
<> 161:2cc1468da177 16282 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
<> 161:2cc1468da177 16283 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 16284 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
<> 161:2cc1468da177 16285 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
<> 161:2cc1468da177 16286 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16287 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
<> 161:2cc1468da177 16288 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
<> 161:2cc1468da177 16289 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 16290 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
<> 161:2cc1468da177 16291 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
<> 161:2cc1468da177 16292 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 16293 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
<> 161:2cc1468da177 16294 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
<> 161:2cc1468da177 16295 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 16296 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
<> 161:2cc1468da177 16297 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
<> 161:2cc1468da177 16298 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 16299 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
<> 161:2cc1468da177 16300 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
<> 161:2cc1468da177 16301 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 16302 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
<> 161:2cc1468da177 16303 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
<> 161:2cc1468da177 16304 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 16305 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
<> 161:2cc1468da177 16306 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
<> 161:2cc1468da177 16307 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 16308 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
<> 161:2cc1468da177 16309 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
<> 161:2cc1468da177 16310 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 16311 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
<> 161:2cc1468da177 16312 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
<> 161:2cc1468da177 16313 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16314 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
<> 144:ef7eb2e8f9f7 16315
<> 144:ef7eb2e8f9f7 16316 /******************** Bit definition for USB_OTG_HCFG register ********************/
<> 161:2cc1468da177 16317 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
<> 161:2cc1468da177 16318 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 16319 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
<> 161:2cc1468da177 16320 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16321 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16322 #define USB_OTG_HCFG_FSLSS_Pos (2U)
<> 161:2cc1468da177 16323 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16324 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
<> 144:ef7eb2e8f9f7 16325
<> 144:ef7eb2e8f9f7 16326 /******************** Bit definition for USB_OTG_DCFG register ********************/
<> 161:2cc1468da177 16327 #define USB_OTG_DCFG_DSPD_Pos (0U)
<> 161:2cc1468da177 16328 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 16329 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
<> 161:2cc1468da177 16330 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16331 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16332 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
<> 161:2cc1468da177 16333 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16334 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
<> 161:2cc1468da177 16335
<> 161:2cc1468da177 16336 #define USB_OTG_DCFG_DAD_Pos (4U)
<> 161:2cc1468da177 16337 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
<> 161:2cc1468da177 16338 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
<> 161:2cc1468da177 16339 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16340 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16341 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16342 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 16343 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16344 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 16345 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 16346
<> 161:2cc1468da177 16347 #define USB_OTG_DCFG_PFIVL_Pos (11U)
<> 161:2cc1468da177 16348 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
<> 161:2cc1468da177 16349 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
<> 161:2cc1468da177 16350 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 16351 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 16352
<> 161:2cc1468da177 16353 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
<> 161:2cc1468da177 16354 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
<> 161:2cc1468da177 16355 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
<> 161:2cc1468da177 16356 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 16357 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
<> 144:ef7eb2e8f9f7 16358
<> 144:ef7eb2e8f9f7 16359 /******************** Bit definition for USB_OTG_PCGCR register ********************/
<> 161:2cc1468da177 16360 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
<> 161:2cc1468da177 16361 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16362 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
<> 161:2cc1468da177 16363 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
<> 161:2cc1468da177 16364 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16365 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
<> 161:2cc1468da177 16366 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
<> 161:2cc1468da177 16367 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16368 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
<> 144:ef7eb2e8f9f7 16369
<> 144:ef7eb2e8f9f7 16370 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
<> 161:2cc1468da177 16371 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
<> 161:2cc1468da177 16372 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16373 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
<> 161:2cc1468da177 16374 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
<> 161:2cc1468da177 16375 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16376 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
<> 161:2cc1468da177 16377 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
<> 161:2cc1468da177 16378 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 16379 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
<> 161:2cc1468da177 16380 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
<> 161:2cc1468da177 16381 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 16382 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
<> 161:2cc1468da177 16383 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
<> 161:2cc1468da177 16384 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 16385 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
<> 161:2cc1468da177 16386 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
<> 161:2cc1468da177 16387 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 16388 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
<> 161:2cc1468da177 16389 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
<> 161:2cc1468da177 16390 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16391 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
<> 144:ef7eb2e8f9f7 16392
<> 144:ef7eb2e8f9f7 16393 /******************** Bit definition for USB_OTG_DCTL register ********************/
<> 161:2cc1468da177 16394 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
<> 161:2cc1468da177 16395 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16396 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
<> 161:2cc1468da177 16397 #define USB_OTG_DCTL_SDIS_Pos (1U)
<> 161:2cc1468da177 16398 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16399 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
<> 161:2cc1468da177 16400 #define USB_OTG_DCTL_GINSTS_Pos (2U)
<> 161:2cc1468da177 16401 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16402 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
<> 161:2cc1468da177 16403 #define USB_OTG_DCTL_GONSTS_Pos (3U)
<> 161:2cc1468da177 16404 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16405 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
<> 161:2cc1468da177 16406
<> 161:2cc1468da177 16407 #define USB_OTG_DCTL_TCTL_Pos (4U)
<> 161:2cc1468da177 16408 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
<> 161:2cc1468da177 16409 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
<> 161:2cc1468da177 16410 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16411 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16412 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16413 #define USB_OTG_DCTL_SGINAK_Pos (7U)
<> 161:2cc1468da177 16414 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 16415 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
<> 161:2cc1468da177 16416 #define USB_OTG_DCTL_CGINAK_Pos (8U)
<> 161:2cc1468da177 16417 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16418 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
<> 161:2cc1468da177 16419 #define USB_OTG_DCTL_SGONAK_Pos (9U)
<> 161:2cc1468da177 16420 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 16421 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
<> 161:2cc1468da177 16422 #define USB_OTG_DCTL_CGONAK_Pos (10U)
<> 161:2cc1468da177 16423 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 16424 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
<> 161:2cc1468da177 16425 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
<> 161:2cc1468da177 16426 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 16427 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
<> 144:ef7eb2e8f9f7 16428
<> 144:ef7eb2e8f9f7 16429 /******************** Bit definition for USB_OTG_HFIR register ********************/
<> 161:2cc1468da177 16430 #define USB_OTG_HFIR_FRIVL_Pos (0U)
<> 161:2cc1468da177 16431 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16432 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
<> 144:ef7eb2e8f9f7 16433
<> 144:ef7eb2e8f9f7 16434 /******************** Bit definition for USB_OTG_HFNUM register ********************/
<> 161:2cc1468da177 16435 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
<> 161:2cc1468da177 16436 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16437 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
<> 161:2cc1468da177 16438 #define USB_OTG_HFNUM_FTREM_Pos (16U)
<> 161:2cc1468da177 16439 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 16440 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
<> 144:ef7eb2e8f9f7 16441
<> 144:ef7eb2e8f9f7 16442 /******************** Bit definition for USB_OTG_DSTS register ********************/
<> 161:2cc1468da177 16443 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
<> 161:2cc1468da177 16444 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16445 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
<> 161:2cc1468da177 16446
<> 161:2cc1468da177 16447 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
<> 161:2cc1468da177 16448 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
<> 161:2cc1468da177 16449 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
<> 161:2cc1468da177 16450 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16451 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16452 #define USB_OTG_DSTS_EERR_Pos (3U)
<> 161:2cc1468da177 16453 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16454 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
<> 161:2cc1468da177 16455 #define USB_OTG_DSTS_FNSOF_Pos (8U)
<> 161:2cc1468da177 16456 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
<> 161:2cc1468da177 16457 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
<> 144:ef7eb2e8f9f7 16458
<> 144:ef7eb2e8f9f7 16459 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
<> 161:2cc1468da177 16460 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
<> 161:2cc1468da177 16461 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16462 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
<> 161:2cc1468da177 16463 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
<> 161:2cc1468da177 16464 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
<> 161:2cc1468da177 16465 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
<> 161:2cc1468da177 16466 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
<> 161:2cc1468da177 16467 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
<> 161:2cc1468da177 16468 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
<> 161:2cc1468da177 16469 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
<> 161:2cc1468da177 16470 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
<> 161:2cc1468da177 16471 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
<> 161:2cc1468da177 16472 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16473 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
<> 161:2cc1468da177 16474 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
<> 161:2cc1468da177 16475 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 16476 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
<> 161:2cc1468da177 16477 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
<> 161:2cc1468da177 16478 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16479 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
<> 144:ef7eb2e8f9f7 16480
<> 144:ef7eb2e8f9f7 16481 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
<> 161:2cc1468da177 16482 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
<> 161:2cc1468da177 16483 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
<> 161:2cc1468da177 16484 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
<> 161:2cc1468da177 16485 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16486 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16487 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16488 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
<> 161:2cc1468da177 16489 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16490 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
<> 161:2cc1468da177 16491 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
<> 161:2cc1468da177 16492 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16493 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
<> 161:2cc1468da177 16494 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
<> 161:2cc1468da177 16495 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 16496 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
<> 161:2cc1468da177 16497 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
<> 161:2cc1468da177 16498 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
<> 161:2cc1468da177 16499 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
<> 161:2cc1468da177 16500 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 16501 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 16502 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 16503 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 16504 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
<> 161:2cc1468da177 16505 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 16506 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
<> 161:2cc1468da177 16507 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
<> 161:2cc1468da177 16508 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 16509 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
<> 161:2cc1468da177 16510 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
<> 161:2cc1468da177 16511 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 16512 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
<> 161:2cc1468da177 16513 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
<> 161:2cc1468da177 16514 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 16515 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
<> 161:2cc1468da177 16516 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
<> 161:2cc1468da177 16517 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16518 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
<> 161:2cc1468da177 16519 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
<> 161:2cc1468da177 16520 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 16521 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
<> 161:2cc1468da177 16522 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
<> 161:2cc1468da177 16523 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 16524 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
<> 161:2cc1468da177 16525 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
<> 161:2cc1468da177 16526 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 16527 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
<> 161:2cc1468da177 16528 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
<> 161:2cc1468da177 16529 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 16530 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
<> 161:2cc1468da177 16531 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
<> 161:2cc1468da177 16532 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 16533 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
<> 161:2cc1468da177 16534 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
<> 161:2cc1468da177 16535 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 16536 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
<> 161:2cc1468da177 16537 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
<> 161:2cc1468da177 16538 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 16539 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
<> 161:2cc1468da177 16540 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
<> 161:2cc1468da177 16541 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 16542 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
<> 144:ef7eb2e8f9f7 16543
<> 144:ef7eb2e8f9f7 16544 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
<> 161:2cc1468da177 16545 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
<> 161:2cc1468da177 16546 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16547 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
<> 161:2cc1468da177 16548 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
<> 161:2cc1468da177 16549 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16550 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
<> 161:2cc1468da177 16551 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
<> 161:2cc1468da177 16552 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16553 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
<> 161:2cc1468da177 16554 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
<> 161:2cc1468da177 16555 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16556 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
<> 161:2cc1468da177 16557 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
<> 161:2cc1468da177 16558 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16559 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
<> 161:2cc1468da177 16560 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
<> 161:2cc1468da177 16561 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
<> 161:2cc1468da177 16562 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
<> 161:2cc1468da177 16563 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16564 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 16565 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16566 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 16567 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 16568 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
<> 161:2cc1468da177 16569 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 16570 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
<> 161:2cc1468da177 16571 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
<> 161:2cc1468da177 16572 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 16573 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
<> 144:ef7eb2e8f9f7 16574
<> 144:ef7eb2e8f9f7 16575 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
<> 161:2cc1468da177 16576 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
<> 161:2cc1468da177 16577 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16578 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
<> 161:2cc1468da177 16579 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
<> 161:2cc1468da177 16580 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16581 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
<> 161:2cc1468da177 16582 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
<> 161:2cc1468da177 16583 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16584 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
<> 161:2cc1468da177 16585 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
<> 161:2cc1468da177 16586 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16587 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
<> 161:2cc1468da177 16588 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
<> 161:2cc1468da177 16589 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16590 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
<> 161:2cc1468da177 16591 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
<> 161:2cc1468da177 16592 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16593 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
<> 161:2cc1468da177 16594 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
<> 161:2cc1468da177 16595 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16596 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
<> 161:2cc1468da177 16597 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
<> 161:2cc1468da177 16598 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 16599 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 16600
<> 144:ef7eb2e8f9f7 16601 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
<> 161:2cc1468da177 16602 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
<> 161:2cc1468da177 16603 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16604 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
<> 161:2cc1468da177 16605 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
<> 161:2cc1468da177 16606 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 16607 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
<> 161:2cc1468da177 16608 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 16609 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 16610 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 16611 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 16612 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16613 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 16614 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 16615 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 16616
<> 161:2cc1468da177 16617 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
<> 161:2cc1468da177 16618 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
<> 161:2cc1468da177 16619 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
<> 161:2cc1468da177 16620 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 16621 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 16622 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 16623 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 16624 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 16625 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 16626 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 16627 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 16628
<> 144:ef7eb2e8f9f7 16629 /******************** Bit definition for USB_OTG_HAINT register ********************/
<> 161:2cc1468da177 16630 #define USB_OTG_HAINT_HAINT_Pos (0U)
<> 161:2cc1468da177 16631 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16632 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
<> 144:ef7eb2e8f9f7 16633
<> 144:ef7eb2e8f9f7 16634 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
<> 161:2cc1468da177 16635 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
<> 161:2cc1468da177 16636 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16637 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
<> 161:2cc1468da177 16638 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
<> 161:2cc1468da177 16639 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16640 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
<> 161:2cc1468da177 16641 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
<> 161:2cc1468da177 16642 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16643 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
<> 161:2cc1468da177 16644 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
<> 161:2cc1468da177 16645 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16646 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
<> 161:2cc1468da177 16647 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
<> 161:2cc1468da177 16648 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16649 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
<> 161:2cc1468da177 16650 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
<> 161:2cc1468da177 16651 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16652 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
<> 161:2cc1468da177 16653 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
<> 161:2cc1468da177 16654 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 16655 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
<> 161:2cc1468da177 16656 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
<> 161:2cc1468da177 16657 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 16658 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 16659
<> 144:ef7eb2e8f9f7 16660 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
<> 161:2cc1468da177 16661 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
<> 161:2cc1468da177 16662 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16663 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
<> 161:2cc1468da177 16664 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
<> 161:2cc1468da177 16665 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16666 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
<> 161:2cc1468da177 16667 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
<> 161:2cc1468da177 16668 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16669 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
<> 161:2cc1468da177 16670 #define USB_OTG_GINTSTS_SOF_Pos (3U)
<> 161:2cc1468da177 16671 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16672 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
<> 161:2cc1468da177 16673 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
<> 161:2cc1468da177 16674 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16675 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
<> 161:2cc1468da177 16676 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
<> 161:2cc1468da177 16677 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16678 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
<> 161:2cc1468da177 16679 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
<> 161:2cc1468da177 16680 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16681 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
<> 161:2cc1468da177 16682 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
<> 161:2cc1468da177 16683 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 16684 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
<> 161:2cc1468da177 16685 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
<> 161:2cc1468da177 16686 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 16687 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
<> 161:2cc1468da177 16688 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
<> 161:2cc1468da177 16689 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 16690 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
<> 161:2cc1468da177 16691 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
<> 161:2cc1468da177 16692 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 16693 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
<> 161:2cc1468da177 16694 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
<> 161:2cc1468da177 16695 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 16696 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
<> 161:2cc1468da177 16697 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
<> 161:2cc1468da177 16698 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 16699 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
<> 161:2cc1468da177 16700 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
<> 161:2cc1468da177 16701 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 16702 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
<> 161:2cc1468da177 16703 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
<> 161:2cc1468da177 16704 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 16705 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
<> 161:2cc1468da177 16706 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
<> 161:2cc1468da177 16707 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 16708 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
<> 161:2cc1468da177 16709 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
<> 161:2cc1468da177 16710 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16711 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
<> 161:2cc1468da177 16712 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
<> 161:2cc1468da177 16713 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 16714 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
<> 161:2cc1468da177 16715 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
<> 161:2cc1468da177 16716 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 16717 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
<> 161:2cc1468da177 16718 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
<> 161:2cc1468da177 16719 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 16720 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
<> 161:2cc1468da177 16721 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
<> 161:2cc1468da177 16722 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 16723 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
<> 161:2cc1468da177 16724 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
<> 161:2cc1468da177 16725 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 16726 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
<> 161:2cc1468da177 16727 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
<> 161:2cc1468da177 16728 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 16729 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
<> 161:2cc1468da177 16730 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
<> 161:2cc1468da177 16731 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 16732 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
<> 161:2cc1468da177 16733 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
<> 161:2cc1468da177 16734 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 16735 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
<> 161:2cc1468da177 16736 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
<> 161:2cc1468da177 16737 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 16738 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
<> 161:2cc1468da177 16739 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
<> 161:2cc1468da177 16740 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 16741 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
<> 161:2cc1468da177 16742 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
<> 161:2cc1468da177 16743 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 16744 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
<> 144:ef7eb2e8f9f7 16745
<> 144:ef7eb2e8f9f7 16746 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
<> 161:2cc1468da177 16747 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
<> 161:2cc1468da177 16748 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16749 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
<> 161:2cc1468da177 16750 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
<> 161:2cc1468da177 16751 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16752 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
<> 161:2cc1468da177 16753 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
<> 161:2cc1468da177 16754 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16755 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
<> 161:2cc1468da177 16756 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
<> 161:2cc1468da177 16757 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 16758 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
<> 161:2cc1468da177 16759 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
<> 161:2cc1468da177 16760 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 16761 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
<> 161:2cc1468da177 16762 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
<> 161:2cc1468da177 16763 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 16764 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
<> 161:2cc1468da177 16765 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
<> 161:2cc1468da177 16766 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 16767 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
<> 161:2cc1468da177 16768 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
<> 161:2cc1468da177 16769 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 16770 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
<> 161:2cc1468da177 16771 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
<> 161:2cc1468da177 16772 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 16773 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
<> 161:2cc1468da177 16774 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
<> 161:2cc1468da177 16775 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 16776 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
<> 161:2cc1468da177 16777 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
<> 161:2cc1468da177 16778 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 16779 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
<> 161:2cc1468da177 16780 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
<> 161:2cc1468da177 16781 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 16782 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
<> 161:2cc1468da177 16783 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
<> 161:2cc1468da177 16784 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 16785 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
<> 161:2cc1468da177 16786 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
<> 161:2cc1468da177 16787 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 16788 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
<> 161:2cc1468da177 16789 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
<> 161:2cc1468da177 16790 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 16791 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
<> 161:2cc1468da177 16792 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
<> 161:2cc1468da177 16793 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 16794 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
<> 161:2cc1468da177 16795 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
<> 161:2cc1468da177 16796 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16797 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
<> 161:2cc1468da177 16798 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
<> 161:2cc1468da177 16799 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 16800 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
<> 161:2cc1468da177 16801 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
<> 161:2cc1468da177 16802 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 16803 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
<> 161:2cc1468da177 16804 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
<> 161:2cc1468da177 16805 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 16806 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
<> 161:2cc1468da177 16807 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
<> 161:2cc1468da177 16808 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 16809 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
<> 161:2cc1468da177 16810 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
<> 161:2cc1468da177 16811 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 16812 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
<> 161:2cc1468da177 16813 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
<> 161:2cc1468da177 16814 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 16815 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
<> 161:2cc1468da177 16816 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
<> 161:2cc1468da177 16817 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 16818 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
<> 161:2cc1468da177 16819 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
<> 161:2cc1468da177 16820 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 16821 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
<> 161:2cc1468da177 16822 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
<> 161:2cc1468da177 16823 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 16824 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
<> 161:2cc1468da177 16825 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
<> 161:2cc1468da177 16826 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 16827 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
<> 161:2cc1468da177 16828 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
<> 161:2cc1468da177 16829 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 16830 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
<> 144:ef7eb2e8f9f7 16831
<> 144:ef7eb2e8f9f7 16832 /******************** Bit definition for USB_OTG_DAINT register ********************/
<> 161:2cc1468da177 16833 #define USB_OTG_DAINT_IEPINT_Pos (0U)
<> 161:2cc1468da177 16834 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16835 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
<> 161:2cc1468da177 16836 #define USB_OTG_DAINT_OEPINT_Pos (16U)
<> 161:2cc1468da177 16837 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 16838 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
<> 144:ef7eb2e8f9f7 16839
<> 144:ef7eb2e8f9f7 16840 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
<> 161:2cc1468da177 16841 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
<> 161:2cc1468da177 16842 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16843 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
<> 144:ef7eb2e8f9f7 16844
<> 144:ef7eb2e8f9f7 16845 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
<> 161:2cc1468da177 16846 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
<> 161:2cc1468da177 16847 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 16848 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
<> 161:2cc1468da177 16849 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
<> 161:2cc1468da177 16850 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
<> 161:2cc1468da177 16851 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
<> 161:2cc1468da177 16852 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
<> 161:2cc1468da177 16853 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
<> 161:2cc1468da177 16854 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
<> 161:2cc1468da177 16855 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
<> 161:2cc1468da177 16856 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
<> 161:2cc1468da177 16857 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 16858
<> 144:ef7eb2e8f9f7 16859 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
<> 161:2cc1468da177 16860 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
<> 161:2cc1468da177 16861 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16862 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
<> 161:2cc1468da177 16863 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
<> 161:2cc1468da177 16864 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 16865 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 16866
<> 144:ef7eb2e8f9f7 16867 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 16868
<> 161:2cc1468da177 16869 #define USB_OTG_CHNUM_Pos (0U)
<> 161:2cc1468da177 16870 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 16871 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
<> 161:2cc1468da177 16872 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16873 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16874 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16875 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16876 #define USB_OTG_BCNT_Pos (4U)
<> 161:2cc1468da177 16877 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
<> 161:2cc1468da177 16878 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
<> 161:2cc1468da177 16879
<> 161:2cc1468da177 16880 #define USB_OTG_DPID_Pos (15U)
<> 161:2cc1468da177 16881 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
<> 161:2cc1468da177 16882 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
<> 161:2cc1468da177 16883 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 16884 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 16885
<> 161:2cc1468da177 16886 #define USB_OTG_PKTSTS_Pos (17U)
<> 161:2cc1468da177 16887 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
<> 161:2cc1468da177 16888 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
<> 161:2cc1468da177 16889 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 16890 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 16891 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 16892 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16893
<> 161:2cc1468da177 16894 #define USB_OTG_EPNUM_Pos (0U)
<> 161:2cc1468da177 16895 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 16896 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
<> 161:2cc1468da177 16897 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16898 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16899 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16900 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16901
<> 161:2cc1468da177 16902 #define USB_OTG_FRMNUM_Pos (21U)
<> 161:2cc1468da177 16903 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
<> 161:2cc1468da177 16904 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
<> 161:2cc1468da177 16905 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 16906 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 16907 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 16908 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 16909
<> 144:ef7eb2e8f9f7 16910 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 16911
<> 161:2cc1468da177 16912 #define USB_OTG_CHNUM_Pos (0U)
<> 161:2cc1468da177 16913 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 16914 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
<> 161:2cc1468da177 16915 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16916 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16917 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16918 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16919 #define USB_OTG_BCNT_Pos (4U)
<> 161:2cc1468da177 16920 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
<> 161:2cc1468da177 16921 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
<> 161:2cc1468da177 16922
<> 161:2cc1468da177 16923 #define USB_OTG_DPID_Pos (15U)
<> 161:2cc1468da177 16924 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
<> 161:2cc1468da177 16925 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
<> 161:2cc1468da177 16926 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 16927 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 16928
<> 161:2cc1468da177 16929 #define USB_OTG_PKTSTS_Pos (17U)
<> 161:2cc1468da177 16930 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
<> 161:2cc1468da177 16931 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
<> 161:2cc1468da177 16932 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 16933 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 16934 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 16935 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16936
<> 161:2cc1468da177 16937 #define USB_OTG_EPNUM_Pos (0U)
<> 161:2cc1468da177 16938 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
<> 161:2cc1468da177 16939 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
<> 161:2cc1468da177 16940 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 16941 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 16942 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 16943 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 16944
<> 161:2cc1468da177 16945 #define USB_OTG_FRMNUM_Pos (21U)
<> 161:2cc1468da177 16946 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
<> 161:2cc1468da177 16947 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
<> 161:2cc1468da177 16948 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 16949 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 16950 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 16951 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 16952
<> 144:ef7eb2e8f9f7 16953 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
<> 161:2cc1468da177 16954 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
<> 161:2cc1468da177 16955 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16956 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
<> 144:ef7eb2e8f9f7 16957
<> 144:ef7eb2e8f9f7 16958 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
<> 161:2cc1468da177 16959 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
<> 161:2cc1468da177 16960 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16961 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
<> 144:ef7eb2e8f9f7 16962
<> 144:ef7eb2e8f9f7 16963 /******************** Bit definition for OTG register ********************/
<> 161:2cc1468da177 16964 #define USB_OTG_NPTXFSA_Pos (0U)
<> 161:2cc1468da177 16965 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16966 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
<> 161:2cc1468da177 16967 #define USB_OTG_NPTXFD_Pos (16U)
<> 161:2cc1468da177 16968 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 16969 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
<> 161:2cc1468da177 16970 #define USB_OTG_TX0FSA_Pos (0U)
<> 161:2cc1468da177 16971 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16972 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
<> 161:2cc1468da177 16973 #define USB_OTG_TX0FD_Pos (16U)
<> 161:2cc1468da177 16974 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 16975 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
<> 144:ef7eb2e8f9f7 16976
<> 144:ef7eb2e8f9f7 16977 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
<> 161:2cc1468da177 16978 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
<> 161:2cc1468da177 16979 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
<> 161:2cc1468da177 16980 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
<> 144:ef7eb2e8f9f7 16981
<> 144:ef7eb2e8f9f7 16982 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
<> 161:2cc1468da177 16983 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
<> 161:2cc1468da177 16984 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 16985 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
<> 161:2cc1468da177 16986
<> 161:2cc1468da177 16987 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
<> 161:2cc1468da177 16988 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
<> 161:2cc1468da177 16989 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
<> 161:2cc1468da177 16990 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 16991 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 16992 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 16993 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 16994 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 16995 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 16996 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 16997 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 16998
<> 161:2cc1468da177 16999 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
<> 161:2cc1468da177 17000 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
<> 161:2cc1468da177 17001 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
<> 161:2cc1468da177 17002 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 17003 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 17004 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 17005 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 17006 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 17007 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 17008 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 17009
<> 144:ef7eb2e8f9f7 17010 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
<> 161:2cc1468da177 17011 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
<> 161:2cc1468da177 17012 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17013 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
<> 161:2cc1468da177 17014 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
<> 161:2cc1468da177 17015 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17016 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
<> 161:2cc1468da177 17017
<> 161:2cc1468da177 17018 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
<> 161:2cc1468da177 17019 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
<> 161:2cc1468da177 17020 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
<> 161:2cc1468da177 17021 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17022 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17023 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17024 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17025 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17026 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17027 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17028 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17029 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 17030 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
<> 161:2cc1468da177 17031 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 17032 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
<> 161:2cc1468da177 17033
<> 161:2cc1468da177 17034 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
<> 161:2cc1468da177 17035 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
<> 161:2cc1468da177 17036 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
<> 161:2cc1468da177 17037 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 17038 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 17039 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 17040 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 17041 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 17042 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 17043 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 17044 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 17045 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 17046 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
<> 161:2cc1468da177 17047 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 17048 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
<> 144:ef7eb2e8f9f7 17049
<> 144:ef7eb2e8f9f7 17050 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
<> 161:2cc1468da177 17051 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
<> 161:2cc1468da177 17052 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 17053 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
<> 144:ef7eb2e8f9f7 17054
<> 144:ef7eb2e8f9f7 17055 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
<> 161:2cc1468da177 17056 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
<> 161:2cc1468da177 17057 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17058 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
<> 161:2cc1468da177 17059 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
<> 161:2cc1468da177 17060 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 17061 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
<> 144:ef7eb2e8f9f7 17062
<> 144:ef7eb2e8f9f7 17063 /******************** Bit definition for USB_OTG_GCCFG register ********************/
<> 161:2cc1468da177 17064 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
<> 161:2cc1468da177 17065 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 17066 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
<> 161:2cc1468da177 17067 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
<> 161:2cc1468da177 17068 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 17069 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
<> 144:ef7eb2e8f9f7 17070
<> 144:ef7eb2e8f9f7 17071 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
<> 161:2cc1468da177 17072 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
<> 161:2cc1468da177 17073 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1U << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17074 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
<> 161:2cc1468da177 17075 #define USB_OTG_GPWRDN_ADPIF_Pos (23U)
<> 161:2cc1468da177 17076 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1U << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 17077 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
<> 144:ef7eb2e8f9f7 17078
<> 144:ef7eb2e8f9f7 17079 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
<> 161:2cc1468da177 17080 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
<> 161:2cc1468da177 17081 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17082 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
<> 161:2cc1468da177 17083 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
<> 161:2cc1468da177 17084 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 17085 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
<> 161:2cc1468da177 17086
<> 144:ef7eb2e8f9f7 17087 /******************** Bit definition for USB_OTG_CID register ********************/
<> 161:2cc1468da177 17088 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
<> 161:2cc1468da177 17089 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 17090 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
<> 144:ef7eb2e8f9f7 17091
<> 144:ef7eb2e8f9f7 17092 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
<> 161:2cc1468da177 17093 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
<> 161:2cc1468da177 17094 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17095 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
<> 161:2cc1468da177 17096 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
<> 161:2cc1468da177 17097 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17098 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
<> 161:2cc1468da177 17099 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
<> 161:2cc1468da177 17100 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
<> 161:2cc1468da177 17101 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
<> 161:2cc1468da177 17102 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
<> 161:2cc1468da177 17103 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17104 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
<> 161:2cc1468da177 17105 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
<> 161:2cc1468da177 17106 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17107 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
<> 161:2cc1468da177 17108 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
<> 161:2cc1468da177 17109 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 17110 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
<> 161:2cc1468da177 17111 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
<> 161:2cc1468da177 17112 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17113 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
<> 161:2cc1468da177 17114 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
<> 161:2cc1468da177 17115 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
<> 161:2cc1468da177 17116 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
<> 161:2cc1468da177 17117 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
<> 161:2cc1468da177 17118 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 17119 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
<> 161:2cc1468da177 17120 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
<> 161:2cc1468da177 17121 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 17122 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
<> 161:2cc1468da177 17123 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
<> 161:2cc1468da177 17124 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
<> 161:2cc1468da177 17125 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
<> 161:2cc1468da177 17126 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
<> 161:2cc1468da177 17127 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
<> 161:2cc1468da177 17128 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
<> 161:2cc1468da177 17129 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
<> 161:2cc1468da177 17130 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 17131 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
<> 161:2cc1468da177 17132 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
<> 161:2cc1468da177 17133 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
<> 161:2cc1468da177 17134 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
<> 161:2cc1468da177 17135 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
<> 161:2cc1468da177 17136 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 17137 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
<> 144:ef7eb2e8f9f7 17138
<> 144:ef7eb2e8f9f7 17139 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
<> 161:2cc1468da177 17140 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
<> 161:2cc1468da177 17141 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17142 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
<> 161:2cc1468da177 17143 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
<> 161:2cc1468da177 17144 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17145 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
<> 161:2cc1468da177 17146 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
<> 161:2cc1468da177 17147 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17148 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
<> 161:2cc1468da177 17149 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
<> 161:2cc1468da177 17150 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17151 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
<> 161:2cc1468da177 17152 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
<> 161:2cc1468da177 17153 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17154 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
<> 161:2cc1468da177 17155 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
<> 161:2cc1468da177 17156 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17157 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
<> 161:2cc1468da177 17158 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
<> 161:2cc1468da177 17159 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17160 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
<> 161:2cc1468da177 17161 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
<> 161:2cc1468da177 17162 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17163 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
<> 161:2cc1468da177 17164 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
<> 161:2cc1468da177 17165 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17166 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
<> 144:ef7eb2e8f9f7 17167
<> 144:ef7eb2e8f9f7 17168 /******************** Bit definition for USB_OTG_HPRT register ********************/
<> 161:2cc1468da177 17169 #define USB_OTG_HPRT_PCSTS_Pos (0U)
<> 161:2cc1468da177 17170 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17171 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
<> 161:2cc1468da177 17172 #define USB_OTG_HPRT_PCDET_Pos (1U)
<> 161:2cc1468da177 17173 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17174 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
<> 161:2cc1468da177 17175 #define USB_OTG_HPRT_PENA_Pos (2U)
<> 161:2cc1468da177 17176 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17177 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
<> 161:2cc1468da177 17178 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
<> 161:2cc1468da177 17179 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17180 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
<> 161:2cc1468da177 17181 #define USB_OTG_HPRT_POCA_Pos (4U)
<> 161:2cc1468da177 17182 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17183 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
<> 161:2cc1468da177 17184 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
<> 161:2cc1468da177 17185 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17186 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
<> 161:2cc1468da177 17187 #define USB_OTG_HPRT_PRES_Pos (6U)
<> 161:2cc1468da177 17188 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17189 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
<> 161:2cc1468da177 17190 #define USB_OTG_HPRT_PSUSP_Pos (7U)
<> 161:2cc1468da177 17191 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17192 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
<> 161:2cc1468da177 17193 #define USB_OTG_HPRT_PRST_Pos (8U)
<> 161:2cc1468da177 17194 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17195 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
<> 161:2cc1468da177 17196
<> 161:2cc1468da177 17197 #define USB_OTG_HPRT_PLSTS_Pos (10U)
<> 161:2cc1468da177 17198 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
<> 161:2cc1468da177 17199 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
<> 161:2cc1468da177 17200 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 17201 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 17202 #define USB_OTG_HPRT_PPWR_Pos (12U)
<> 161:2cc1468da177 17203 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17204 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
<> 161:2cc1468da177 17205
<> 161:2cc1468da177 17206 #define USB_OTG_HPRT_PTCTL_Pos (13U)
<> 161:2cc1468da177 17207 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
<> 161:2cc1468da177 17208 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
<> 161:2cc1468da177 17209 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17210 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 17211 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 17212 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 17213
<> 161:2cc1468da177 17214 #define USB_OTG_HPRT_PSPD_Pos (17U)
<> 161:2cc1468da177 17215 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
<> 161:2cc1468da177 17216 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
<> 161:2cc1468da177 17217 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 17218 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 17219
<> 144:ef7eb2e8f9f7 17220 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
<> 161:2cc1468da177 17221 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
<> 161:2cc1468da177 17222 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17223 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
<> 161:2cc1468da177 17224 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
<> 161:2cc1468da177 17225 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17226 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
<> 161:2cc1468da177 17227 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
<> 161:2cc1468da177 17228 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17229 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
<> 161:2cc1468da177 17230 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
<> 161:2cc1468da177 17231 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17232 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
<> 161:2cc1468da177 17233 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
<> 161:2cc1468da177 17234 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17235 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
<> 161:2cc1468da177 17236 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
<> 161:2cc1468da177 17237 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17238 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
<> 161:2cc1468da177 17239 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
<> 161:2cc1468da177 17240 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17241 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
<> 161:2cc1468da177 17242 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
<> 161:2cc1468da177 17243 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17244 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
<> 161:2cc1468da177 17245 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
<> 161:2cc1468da177 17246 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17247 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
<> 161:2cc1468da177 17248 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
<> 161:2cc1468da177 17249 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17250 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
<> 161:2cc1468da177 17251 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
<> 161:2cc1468da177 17252 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 17253 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
<> 144:ef7eb2e8f9f7 17254
<> 144:ef7eb2e8f9f7 17255 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
<> 161:2cc1468da177 17256 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
<> 161:2cc1468da177 17257 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 17258 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
<> 161:2cc1468da177 17259 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
<> 161:2cc1468da177 17260 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 17261 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
<> 144:ef7eb2e8f9f7 17262
<> 144:ef7eb2e8f9f7 17263 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
<> 161:2cc1468da177 17264 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
<> 161:2cc1468da177 17265 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
<> 161:2cc1468da177 17266 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
<> 161:2cc1468da177 17267 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
<> 161:2cc1468da177 17268 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 17269 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
<> 161:2cc1468da177 17270 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
<> 161:2cc1468da177 17271 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 17272 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
<> 161:2cc1468da177 17273 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
<> 161:2cc1468da177 17274 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 17275 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
<> 161:2cc1468da177 17276
<> 161:2cc1468da177 17277 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
<> 161:2cc1468da177 17278 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
<> 161:2cc1468da177 17279 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
<> 161:2cc1468da177 17280 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 17281 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 17282 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
<> 161:2cc1468da177 17283 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 17284 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
<> 161:2cc1468da177 17285
<> 161:2cc1468da177 17286 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
<> 161:2cc1468da177 17287 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
<> 161:2cc1468da177 17288 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
<> 161:2cc1468da177 17289 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 17290 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 17291 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 17292 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 17293 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
<> 161:2cc1468da177 17294 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 17295 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
<> 161:2cc1468da177 17296 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
<> 161:2cc1468da177 17297 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 17298 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
<> 161:2cc1468da177 17299 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
<> 161:2cc1468da177 17300 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 17301 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
<> 161:2cc1468da177 17302 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
<> 161:2cc1468da177 17303 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 17304 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
<> 161:2cc1468da177 17305 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
<> 161:2cc1468da177 17306 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 17307 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
<> 161:2cc1468da177 17308 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
<> 161:2cc1468da177 17309 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 17310 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
<> 144:ef7eb2e8f9f7 17311
<> 144:ef7eb2e8f9f7 17312 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
<> 161:2cc1468da177 17313 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
<> 161:2cc1468da177 17314 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
<> 161:2cc1468da177 17315 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
<> 161:2cc1468da177 17316
<> 161:2cc1468da177 17317 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
<> 161:2cc1468da177 17318 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
<> 161:2cc1468da177 17319 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
<> 161:2cc1468da177 17320 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 17321 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17322 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17323 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 17324 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
<> 161:2cc1468da177 17325 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 17326 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
<> 161:2cc1468da177 17327 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
<> 161:2cc1468da177 17328 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 17329 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
<> 161:2cc1468da177 17330
<> 161:2cc1468da177 17331 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
<> 161:2cc1468da177 17332 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
<> 161:2cc1468da177 17333 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
<> 161:2cc1468da177 17334 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 17335 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 17336
<> 161:2cc1468da177 17337 #define USB_OTG_HCCHAR_MC_Pos (20U)
<> 161:2cc1468da177 17338 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
<> 161:2cc1468da177 17339 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
<> 161:2cc1468da177 17340 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 17341 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 17342
<> 161:2cc1468da177 17343 #define USB_OTG_HCCHAR_DAD_Pos (22U)
<> 161:2cc1468da177 17344 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
<> 161:2cc1468da177 17345 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
<> 161:2cc1468da177 17346 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
<> 161:2cc1468da177 17347 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
<> 161:2cc1468da177 17348 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
<> 161:2cc1468da177 17349 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
<> 161:2cc1468da177 17350 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 17351 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 17352 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 17353 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
<> 161:2cc1468da177 17354 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 17355 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
<> 161:2cc1468da177 17356 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
<> 161:2cc1468da177 17357 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 17358 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
<> 161:2cc1468da177 17359 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
<> 161:2cc1468da177 17360 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 17361 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
<> 144:ef7eb2e8f9f7 17362
<> 144:ef7eb2e8f9f7 17363 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
<> 144:ef7eb2e8f9f7 17364
<> 161:2cc1468da177 17365 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
<> 161:2cc1468da177 17366 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
<> 161:2cc1468da177 17367 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
<> 161:2cc1468da177 17368 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17369 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17370 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17371 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17372 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17373 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17374 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17375
<> 161:2cc1468da177 17376 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
<> 161:2cc1468da177 17377 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
<> 161:2cc1468da177 17378 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
<> 161:2cc1468da177 17379 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17380 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17381 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17382 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 17383 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 17384 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17385 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17386
<> 161:2cc1468da177 17387 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
<> 161:2cc1468da177 17388 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
<> 161:2cc1468da177 17389 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
<> 161:2cc1468da177 17390 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 17391 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 17392 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
<> 161:2cc1468da177 17393 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
<> 161:2cc1468da177 17394 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
<> 161:2cc1468da177 17395 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
<> 161:2cc1468da177 17396 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 17397 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
<> 144:ef7eb2e8f9f7 17398
<> 144:ef7eb2e8f9f7 17399 /******************** Bit definition for USB_OTG_HCINT register ********************/
<> 161:2cc1468da177 17400 #define USB_OTG_HCINT_XFRC_Pos (0U)
<> 161:2cc1468da177 17401 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17402 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
<> 161:2cc1468da177 17403 #define USB_OTG_HCINT_CHH_Pos (1U)
<> 161:2cc1468da177 17404 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17405 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
<> 161:2cc1468da177 17406 #define USB_OTG_HCINT_AHBERR_Pos (2U)
<> 161:2cc1468da177 17407 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17408 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
<> 161:2cc1468da177 17409 #define USB_OTG_HCINT_STALL_Pos (3U)
<> 161:2cc1468da177 17410 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17411 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
<> 161:2cc1468da177 17412 #define USB_OTG_HCINT_NAK_Pos (4U)
<> 161:2cc1468da177 17413 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17414 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
<> 161:2cc1468da177 17415 #define USB_OTG_HCINT_ACK_Pos (5U)
<> 161:2cc1468da177 17416 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17417 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
<> 161:2cc1468da177 17418 #define USB_OTG_HCINT_NYET_Pos (6U)
<> 161:2cc1468da177 17419 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17420 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
<> 161:2cc1468da177 17421 #define USB_OTG_HCINT_TXERR_Pos (7U)
<> 161:2cc1468da177 17422 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17423 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
<> 161:2cc1468da177 17424 #define USB_OTG_HCINT_BBERR_Pos (8U)
<> 161:2cc1468da177 17425 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17426 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
<> 161:2cc1468da177 17427 #define USB_OTG_HCINT_FRMOR_Pos (9U)
<> 161:2cc1468da177 17428 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17429 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
<> 161:2cc1468da177 17430 #define USB_OTG_HCINT_DTERR_Pos (10U)
<> 161:2cc1468da177 17431 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 17432 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
<> 144:ef7eb2e8f9f7 17433
<> 144:ef7eb2e8f9f7 17434 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
<> 161:2cc1468da177 17435 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
<> 161:2cc1468da177 17436 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17437 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
<> 161:2cc1468da177 17438 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
<> 161:2cc1468da177 17439 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17440 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
<> 161:2cc1468da177 17441 #define USB_OTG_DIEPINT_TOC_Pos (3U)
<> 161:2cc1468da177 17442 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17443 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
<> 161:2cc1468da177 17444 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
<> 161:2cc1468da177 17445 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17446 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
<> 161:2cc1468da177 17447 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
<> 161:2cc1468da177 17448 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17449 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
<> 161:2cc1468da177 17450 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
<> 161:2cc1468da177 17451 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17452 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
<> 161:2cc1468da177 17453 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
<> 161:2cc1468da177 17454 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17455 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
<> 161:2cc1468da177 17456 #define USB_OTG_DIEPINT_BNA_Pos (9U)
<> 161:2cc1468da177 17457 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17458 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
<> 161:2cc1468da177 17459 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
<> 161:2cc1468da177 17460 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 17461 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
<> 161:2cc1468da177 17462 #define USB_OTG_DIEPINT_BERR_Pos (12U)
<> 161:2cc1468da177 17463 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17464 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
<> 161:2cc1468da177 17465 #define USB_OTG_DIEPINT_NAK_Pos (13U)
<> 161:2cc1468da177 17466 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17467 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
<> 144:ef7eb2e8f9f7 17468
<> 144:ef7eb2e8f9f7 17469 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
<> 161:2cc1468da177 17470 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
<> 161:2cc1468da177 17471 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17472 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
<> 161:2cc1468da177 17473 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
<> 161:2cc1468da177 17474 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17475 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
<> 161:2cc1468da177 17476 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
<> 161:2cc1468da177 17477 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17478 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
<> 161:2cc1468da177 17479 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
<> 161:2cc1468da177 17480 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17481 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
<> 161:2cc1468da177 17482 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
<> 161:2cc1468da177 17483 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17484 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
<> 161:2cc1468da177 17485 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
<> 161:2cc1468da177 17486 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17487 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
<> 161:2cc1468da177 17488 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
<> 161:2cc1468da177 17489 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17490 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
<> 161:2cc1468da177 17491 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
<> 161:2cc1468da177 17492 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17493 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
<> 161:2cc1468da177 17494 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
<> 161:2cc1468da177 17495 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17496 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
<> 161:2cc1468da177 17497 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
<> 161:2cc1468da177 17498 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17499 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
<> 161:2cc1468da177 17500 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
<> 161:2cc1468da177 17501 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 17502 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
<> 144:ef7eb2e8f9f7 17503
<> 144:ef7eb2e8f9f7 17504 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
<> 144:ef7eb2e8f9f7 17505
<> 161:2cc1468da177 17506 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
<> 161:2cc1468da177 17507 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
<> 161:2cc1468da177 17508 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
<> 161:2cc1468da177 17509 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
<> 161:2cc1468da177 17510 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
<> 161:2cc1468da177 17511 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
<> 161:2cc1468da177 17512 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
<> 161:2cc1468da177 17513 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
<> 161:2cc1468da177 17514 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
<> 144:ef7eb2e8f9f7 17515 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
<> 161:2cc1468da177 17516 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
<> 161:2cc1468da177 17517 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
<> 161:2cc1468da177 17518 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
<> 161:2cc1468da177 17519 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
<> 161:2cc1468da177 17520 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
<> 161:2cc1468da177 17521 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
<> 161:2cc1468da177 17522 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
<> 161:2cc1468da177 17523 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 17524 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
<> 161:2cc1468da177 17525 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
<> 161:2cc1468da177 17526 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
<> 161:2cc1468da177 17527 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
<> 161:2cc1468da177 17528 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 17529 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 17530
<> 144:ef7eb2e8f9f7 17531 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
<> 161:2cc1468da177 17532 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
<> 161:2cc1468da177 17533 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 17534 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
<> 144:ef7eb2e8f9f7 17535
<> 144:ef7eb2e8f9f7 17536 /******************** Bit definition for USB_OTG_HCDMA register ********************/
<> 161:2cc1468da177 17537 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
<> 161:2cc1468da177 17538 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 17539 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
<> 144:ef7eb2e8f9f7 17540
<> 144:ef7eb2e8f9f7 17541 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
<> 161:2cc1468da177 17542 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
<> 161:2cc1468da177 17543 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 17544 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
<> 144:ef7eb2e8f9f7 17545
<> 144:ef7eb2e8f9f7 17546 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
<> 161:2cc1468da177 17547 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
<> 161:2cc1468da177 17548 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 17549 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
<> 161:2cc1468da177 17550 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
<> 161:2cc1468da177 17551 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 17552 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
<> 144:ef7eb2e8f9f7 17553
<> 144:ef7eb2e8f9f7 17554 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
<> 161:2cc1468da177 17555 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
<> 161:2cc1468da177 17556 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
<> 161:2cc1468da177 17557 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
<> 161:2cc1468da177 17558 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
<> 161:2cc1468da177 17559 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
<> 161:2cc1468da177 17560 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
<> 161:2cc1468da177 17561 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
<> 161:2cc1468da177 17562 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
<> 161:2cc1468da177 17563 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
<> 161:2cc1468da177 17564 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
<> 161:2cc1468da177 17565 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
<> 161:2cc1468da177 17566 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
<> 161:2cc1468da177 17567 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
<> 161:2cc1468da177 17568 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 17569 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
<> 161:2cc1468da177 17570 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
<> 161:2cc1468da177 17571 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
<> 161:2cc1468da177 17572 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
<> 161:2cc1468da177 17573 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
<> 161:2cc1468da177 17574 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
<> 161:2cc1468da177 17575 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
<> 161:2cc1468da177 17576 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
<> 161:2cc1468da177 17577 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
<> 161:2cc1468da177 17578 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
<> 161:2cc1468da177 17579 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
<> 161:2cc1468da177 17580 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
<> 161:2cc1468da177 17581 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
<> 161:2cc1468da177 17582 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
<> 161:2cc1468da177 17583 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
<> 161:2cc1468da177 17584 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
<> 161:2cc1468da177 17585 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
<> 161:2cc1468da177 17586 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
<> 161:2cc1468da177 17587 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
<> 161:2cc1468da177 17588 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
<> 161:2cc1468da177 17589 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
<> 161:2cc1468da177 17590 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
<> 161:2cc1468da177 17591 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
<> 161:2cc1468da177 17592 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
<> 144:ef7eb2e8f9f7 17593
<> 144:ef7eb2e8f9f7 17594 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
<> 161:2cc1468da177 17595 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
<> 161:2cc1468da177 17596 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17597 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
<> 161:2cc1468da177 17598 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
<> 161:2cc1468da177 17599 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17600 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
<> 161:2cc1468da177 17601 #define USB_OTG_DOEPINT_STUP_Pos (3U)
<> 161:2cc1468da177 17602 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17603 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
<> 161:2cc1468da177 17604 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
<> 161:2cc1468da177 17605 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17606 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
<> 161:2cc1468da177 17607 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
<> 161:2cc1468da177 17608 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17609 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
<> 161:2cc1468da177 17610 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
<> 161:2cc1468da177 17611 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17612 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
<> 161:2cc1468da177 17613 #define USB_OTG_DOEPINT_NYET_Pos (14U)
<> 161:2cc1468da177 17614 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 17615 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
<> 144:ef7eb2e8f9f7 17616
<> 144:ef7eb2e8f9f7 17617 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
<> 161:2cc1468da177 17618 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
<> 161:2cc1468da177 17619 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
<> 161:2cc1468da177 17620 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
<> 161:2cc1468da177 17621 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
<> 161:2cc1468da177 17622 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
<> 161:2cc1468da177 17623 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
<> 161:2cc1468da177 17624
<> 161:2cc1468da177 17625 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
<> 161:2cc1468da177 17626 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
<> 161:2cc1468da177 17627 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
<> 161:2cc1468da177 17628 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
<> 161:2cc1468da177 17629 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 17630
<> 144:ef7eb2e8f9f7 17631 /******************** Bit definition for PCGCCTL register ********************/
<> 161:2cc1468da177 17632 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
<> 161:2cc1468da177 17633 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17634 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
<> 161:2cc1468da177 17635 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
<> 161:2cc1468da177 17636 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17637 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
<> 161:2cc1468da177 17638 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
<> 161:2cc1468da177 17639 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17640 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 17641
<> 157:ff67d9f36b67 17642
<> 144:ef7eb2e8f9f7 17643 /******************************************************************************/
<> 144:ef7eb2e8f9f7 17644 /* */
<> 144:ef7eb2e8f9f7 17645 /* JPEG Encoder/Decoder */
<> 144:ef7eb2e8f9f7 17646 /* */
<> 144:ef7eb2e8f9f7 17647 /******************************************************************************/
<> 144:ef7eb2e8f9f7 17648 /******************** Bit definition for CONFR0 register ********************/
<> 161:2cc1468da177 17649 #define JPEG_CONFR0_START_Pos (0U)
<> 161:2cc1468da177 17650 #define JPEG_CONFR0_START_Msk (0x1U << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17651 #define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
<> 144:ef7eb2e8f9f7 17652
<> 144:ef7eb2e8f9f7 17653 /******************** Bit definition for CONFR1 register *******************/
<> 161:2cc1468da177 17654 #define JPEG_CONFR1_NF_Pos (0U)
<> 161:2cc1468da177 17655 #define JPEG_CONFR1_NF_Msk (0x3U << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
<> 161:2cc1468da177 17656 #define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
<> 161:2cc1468da177 17657 #define JPEG_CONFR1_NF_0 (0x1U << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17658 #define JPEG_CONFR1_NF_1 (0x2U << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17659 #define JPEG_CONFR1_RE_Pos (2U)
<> 161:2cc1468da177 17660 #define JPEG_CONFR1_RE_Msk (0x1U << JPEG_CONFR1_RE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17661 #define JPEG_CONFR1_RE JPEG_CONFR1_RE_Msk /*!<Restart maker Enable */
<> 161:2cc1468da177 17662 #define JPEG_CONFR1_DE_Pos (3U)
<> 161:2cc1468da177 17663 #define JPEG_CONFR1_DE_Msk (0x1U << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17664 #define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
<> 161:2cc1468da177 17665 #define JPEG_CONFR1_COLORSPACE_Pos (4U)
<> 161:2cc1468da177 17666 #define JPEG_CONFR1_COLORSPACE_Msk (0x3U << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
<> 161:2cc1468da177 17667 #define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
<> 161:2cc1468da177 17668 #define JPEG_CONFR1_COLORSPACE_0 (0x1U << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17669 #define JPEG_CONFR1_COLORSPACE_1 (0x2U << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17670 #define JPEG_CONFR1_NS_Pos (6U)
<> 161:2cc1468da177 17671 #define JPEG_CONFR1_NS_Msk (0x3U << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
<> 161:2cc1468da177 17672 #define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
<> 161:2cc1468da177 17673 #define JPEG_CONFR1_NS_0 (0x1U << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17674 #define JPEG_CONFR1_NS_1 (0x2U << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17675 #define JPEG_CONFR1_HDR_Pos (8U)
<> 161:2cc1468da177 17676 #define JPEG_CONFR1_HDR_Msk (0x1U << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17677 #define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
<> 161:2cc1468da177 17678 #define JPEG_CONFR1_YSIZE_Pos (16U)
<> 161:2cc1468da177 17679 #define JPEG_CONFR1_YSIZE_Msk (0xFFFFU << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 17680 #define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
<> 144:ef7eb2e8f9f7 17681
<> 144:ef7eb2e8f9f7 17682 /******************** Bit definition for CONFR2 register *******************/
<> 161:2cc1468da177 17683 #define JPEG_CONFR2_NMCU_Pos (0U)
<> 161:2cc1468da177 17684 #define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFU << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
<> 161:2cc1468da177 17685 #define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
<> 144:ef7eb2e8f9f7 17686
<> 144:ef7eb2e8f9f7 17687 /******************** Bit definition for CONFR3 register *******************/
<> 161:2cc1468da177 17688 #define JPEG_CONFR3_NRST_Pos (0U)
<> 161:2cc1468da177 17689 #define JPEG_CONFR3_NRST_Msk (0xFFFFU << JPEG_CONFR3_NRST_Pos) /*!< 0x0000FFFF */
<> 161:2cc1468da177 17690 #define JPEG_CONFR3_NRST JPEG_CONFR3_NRST_Msk /*!<Number of MCU between two restart makers minus 1 */
<> 161:2cc1468da177 17691 #define JPEG_CONFR3_XSIZE_Pos (16U)
<> 161:2cc1468da177 17692 #define JPEG_CONFR3_XSIZE_Msk (0xFFFFU << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
<> 161:2cc1468da177 17693 #define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
<> 144:ef7eb2e8f9f7 17694
<> 144:ef7eb2e8f9f7 17695 /******************** Bit definition for CONFR4 register *******************/
<> 161:2cc1468da177 17696 #define JPEG_CONFR4_HD_Pos (0U)
<> 161:2cc1468da177 17697 #define JPEG_CONFR4_HD_Msk (0x1U << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17698 #define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
<> 161:2cc1468da177 17699 #define JPEG_CONFR4_HA_Pos (1U)
<> 161:2cc1468da177 17700 #define JPEG_CONFR4_HA_Msk (0x1U << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17701 #define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
<> 161:2cc1468da177 17702 #define JPEG_CONFR4_QT_Pos (2U)
<> 161:2cc1468da177 17703 #define JPEG_CONFR4_QT_Msk (0x3U << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 17704 #define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
<> 161:2cc1468da177 17705 #define JPEG_CONFR4_QT_0 (0x1U << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17706 #define JPEG_CONFR4_QT_1 (0x2U << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17707 #define JPEG_CONFR4_NB_Pos (4U)
<> 161:2cc1468da177 17708 #define JPEG_CONFR4_NB_Msk (0xFU << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 17709 #define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
<> 161:2cc1468da177 17710 #define JPEG_CONFR4_NB_0 (0x1U << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17711 #define JPEG_CONFR4_NB_1 (0x2U << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17712 #define JPEG_CONFR4_NB_2 (0x4U << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17713 #define JPEG_CONFR4_NB_3 (0x8U << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17714 #define JPEG_CONFR4_VSF_Pos (8U)
<> 161:2cc1468da177 17715 #define JPEG_CONFR4_VSF_Msk (0xFU << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 17716 #define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
<> 161:2cc1468da177 17717 #define JPEG_CONFR4_VSF_0 (0x1U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17718 #define JPEG_CONFR4_VSF_1 (0x2U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17719 #define JPEG_CONFR4_VSF_2 (0x4U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 17720 #define JPEG_CONFR4_VSF_3 (0x8U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 17721 #define JPEG_CONFR4_HSF_Pos (12U)
<> 161:2cc1468da177 17722 #define JPEG_CONFR4_HSF_Msk (0xFU << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 17723 #define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
<> 161:2cc1468da177 17724 #define JPEG_CONFR4_HSF_0 (0x1U << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17725 #define JPEG_CONFR4_HSF_1 (0x2U << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17726 #define JPEG_CONFR4_HSF_2 (0x4U << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 17727 #define JPEG_CONFR4_HSF_3 (0x8U << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 17728
<> 144:ef7eb2e8f9f7 17729 /******************** Bit definition for CONFR5 register *******************/
<> 161:2cc1468da177 17730 #define JPEG_CONFR5_HD_Pos (0U)
<> 161:2cc1468da177 17731 #define JPEG_CONFR5_HD_Msk (0x1U << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17732 #define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
<> 161:2cc1468da177 17733 #define JPEG_CONFR5_HA_Pos (1U)
<> 161:2cc1468da177 17734 #define JPEG_CONFR5_HA_Msk (0x1U << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17735 #define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
<> 161:2cc1468da177 17736 #define JPEG_CONFR5_QT_Pos (2U)
<> 161:2cc1468da177 17737 #define JPEG_CONFR5_QT_Msk (0x3U << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 17738 #define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
<> 161:2cc1468da177 17739 #define JPEG_CONFR5_QT_0 (0x1U << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17740 #define JPEG_CONFR5_QT_1 (0x2U << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17741 #define JPEG_CONFR5_NB_Pos (4U)
<> 161:2cc1468da177 17742 #define JPEG_CONFR5_NB_Msk (0xFU << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 17743 #define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
<> 161:2cc1468da177 17744 #define JPEG_CONFR5_NB_0 (0x1U << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17745 #define JPEG_CONFR5_NB_1 (0x2U << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17746 #define JPEG_CONFR5_NB_2 (0x4U << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17747 #define JPEG_CONFR5_NB_3 (0x8U << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17748 #define JPEG_CONFR5_VSF_Pos (8U)
<> 161:2cc1468da177 17749 #define JPEG_CONFR5_VSF_Msk (0xFU << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 17750 #define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
<> 161:2cc1468da177 17751 #define JPEG_CONFR5_VSF_0 (0x1U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17752 #define JPEG_CONFR5_VSF_1 (0x2U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17753 #define JPEG_CONFR5_VSF_2 (0x4U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 17754 #define JPEG_CONFR5_VSF_3 (0x8U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 17755 #define JPEG_CONFR5_HSF_Pos (12U)
<> 161:2cc1468da177 17756 #define JPEG_CONFR5_HSF_Msk (0xFU << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 17757 #define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
<> 161:2cc1468da177 17758 #define JPEG_CONFR5_HSF_0 (0x1U << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17759 #define JPEG_CONFR5_HSF_1 (0x2U << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17760 #define JPEG_CONFR5_HSF_2 (0x4U << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 17761 #define JPEG_CONFR5_HSF_3 (0x8U << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 17762
<> 144:ef7eb2e8f9f7 17763 /******************** Bit definition for CONFR6 register *******************/
<> 161:2cc1468da177 17764 #define JPEG_CONFR6_HD_Pos (0U)
<> 161:2cc1468da177 17765 #define JPEG_CONFR6_HD_Msk (0x1U << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17766 #define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
<> 161:2cc1468da177 17767 #define JPEG_CONFR6_HA_Pos (1U)
<> 161:2cc1468da177 17768 #define JPEG_CONFR6_HA_Msk (0x1U << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17769 #define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
<> 161:2cc1468da177 17770 #define JPEG_CONFR6_QT_Pos (2U)
<> 161:2cc1468da177 17771 #define JPEG_CONFR6_QT_Msk (0x3U << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 17772 #define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
<> 161:2cc1468da177 17773 #define JPEG_CONFR6_QT_0 (0x1U << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17774 #define JPEG_CONFR6_QT_1 (0x2U << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17775 #define JPEG_CONFR6_NB_Pos (4U)
<> 161:2cc1468da177 17776 #define JPEG_CONFR6_NB_Msk (0xFU << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 17777 #define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
<> 161:2cc1468da177 17778 #define JPEG_CONFR6_NB_0 (0x1U << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17779 #define JPEG_CONFR6_NB_1 (0x2U << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17780 #define JPEG_CONFR6_NB_2 (0x4U << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17781 #define JPEG_CONFR6_NB_3 (0x8U << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17782 #define JPEG_CONFR6_VSF_Pos (8U)
<> 161:2cc1468da177 17783 #define JPEG_CONFR6_VSF_Msk (0xFU << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 17784 #define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
<> 161:2cc1468da177 17785 #define JPEG_CONFR6_VSF_0 (0x1U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17786 #define JPEG_CONFR6_VSF_1 (0x2U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17787 #define JPEG_CONFR6_VSF_2 (0x4U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 17788 #define JPEG_CONFR6_VSF_3 (0x8U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 17789 #define JPEG_CONFR6_HSF_Pos (12U)
<> 161:2cc1468da177 17790 #define JPEG_CONFR6_HSF_Msk (0xFU << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 17791 #define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
<> 161:2cc1468da177 17792 #define JPEG_CONFR6_HSF_0 (0x1U << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17793 #define JPEG_CONFR6_HSF_1 (0x2U << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17794 #define JPEG_CONFR6_HSF_2 (0x4U << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 17795 #define JPEG_CONFR6_HSF_3 (0x8U << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 17796
<> 144:ef7eb2e8f9f7 17797 /******************** Bit definition for CONFR7 register *******************/
<> 161:2cc1468da177 17798 #define JPEG_CONFR7_HD_Pos (0U)
<> 161:2cc1468da177 17799 #define JPEG_CONFR7_HD_Msk (0x1U << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17800 #define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
<> 161:2cc1468da177 17801 #define JPEG_CONFR7_HA_Pos (1U)
<> 161:2cc1468da177 17802 #define JPEG_CONFR7_HA_Msk (0x1U << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17803 #define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
<> 161:2cc1468da177 17804 #define JPEG_CONFR7_QT_Pos (2U)
<> 161:2cc1468da177 17805 #define JPEG_CONFR7_QT_Msk (0x3U << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
<> 161:2cc1468da177 17806 #define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
<> 161:2cc1468da177 17807 #define JPEG_CONFR7_QT_0 (0x1U << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17808 #define JPEG_CONFR7_QT_1 (0x2U << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17809 #define JPEG_CONFR7_NB_Pos (4U)
<> 161:2cc1468da177 17810 #define JPEG_CONFR7_NB_Msk (0xFU << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
<> 161:2cc1468da177 17811 #define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
<> 161:2cc1468da177 17812 #define JPEG_CONFR7_NB_0 (0x1U << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17813 #define JPEG_CONFR7_NB_1 (0x2U << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17814 #define JPEG_CONFR7_NB_2 (0x4U << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17815 #define JPEG_CONFR7_NB_3 (0x8U << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17816 #define JPEG_CONFR7_VSF_Pos (8U)
<> 161:2cc1468da177 17817 #define JPEG_CONFR7_VSF_Msk (0xFU << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
<> 161:2cc1468da177 17818 #define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
<> 161:2cc1468da177 17819 #define JPEG_CONFR7_VSF_0 (0x1U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17820 #define JPEG_CONFR7_VSF_1 (0x2U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17821 #define JPEG_CONFR7_VSF_2 (0x4U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 17822 #define JPEG_CONFR7_VSF_3 (0x8U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 17823 #define JPEG_CONFR7_HSF_Pos (12U)
<> 161:2cc1468da177 17824 #define JPEG_CONFR7_HSF_Msk (0xFU << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
<> 161:2cc1468da177 17825 #define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
<> 161:2cc1468da177 17826 #define JPEG_CONFR7_HSF_0 (0x1U << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17827 #define JPEG_CONFR7_HSF_1 (0x2U << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17828 #define JPEG_CONFR7_HSF_2 (0x4U << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 17829 #define JPEG_CONFR7_HSF_3 (0x8U << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 17830
<> 144:ef7eb2e8f9f7 17831 /******************** Bit definition for CR register *******************/
<> 161:2cc1468da177 17832 #define JPEG_CR_JCEN_Pos (0U)
<> 161:2cc1468da177 17833 #define JPEG_CR_JCEN_Msk (0x1U << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17834 #define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
<> 161:2cc1468da177 17835 #define JPEG_CR_IFTIE_Pos (1U)
<> 161:2cc1468da177 17836 #define JPEG_CR_IFTIE_Msk (0x1U << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17837 #define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
<> 161:2cc1468da177 17838 #define JPEG_CR_IFNFIE_Pos (2U)
<> 161:2cc1468da177 17839 #define JPEG_CR_IFNFIE_Msk (0x1U << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17840 #define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
<> 161:2cc1468da177 17841 #define JPEG_CR_OFTIE_Pos (3U)
<> 161:2cc1468da177 17842 #define JPEG_CR_OFTIE_Msk (0x1U << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17843 #define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
<> 161:2cc1468da177 17844 #define JPEG_CR_OFNEIE_Pos (4U)
<> 161:2cc1468da177 17845 #define JPEG_CR_OFNEIE_Msk (0x1U << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
<> 161:2cc1468da177 17846 #define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
<> 161:2cc1468da177 17847 #define JPEG_CR_EOCIE_Pos (5U)
<> 161:2cc1468da177 17848 #define JPEG_CR_EOCIE_Msk (0x1U << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17849 #define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
<> 161:2cc1468da177 17850 #define JPEG_CR_HPDIE_Pos (6U)
<> 161:2cc1468da177 17851 #define JPEG_CR_HPDIE_Msk (0x1U << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17852 #define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
<> 161:2cc1468da177 17853 #define JPEG_CR_IDMAEN_Pos (11U)
<> 161:2cc1468da177 17854 #define JPEG_CR_IDMAEN_Msk (0x1U << JPEG_CR_IDMAEN_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 17855 #define JPEG_CR_IDMAEN JPEG_CR_IDMAEN_Msk /*!<Enable the DMA request generation for the input FIFO */
<> 161:2cc1468da177 17856 #define JPEG_CR_ODMAEN_Pos (12U)
<> 161:2cc1468da177 17857 #define JPEG_CR_ODMAEN_Msk (0x1U << JPEG_CR_ODMAEN_Pos) /*!< 0x00001000 */
<> 161:2cc1468da177 17858 #define JPEG_CR_ODMAEN JPEG_CR_ODMAEN_Msk /*!<Enable the DMA request generation for the output FIFO */
<> 161:2cc1468da177 17859 #define JPEG_CR_IFF_Pos (13U)
<> 161:2cc1468da177 17860 #define JPEG_CR_IFF_Msk (0x1U << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
<> 161:2cc1468da177 17861 #define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
<> 161:2cc1468da177 17862 #define JPEG_CR_OFF_Pos (14U)
<> 161:2cc1468da177 17863 #define JPEG_CR_OFF_Msk (0x1U << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
<> 161:2cc1468da177 17864 #define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
<> 144:ef7eb2e8f9f7 17865
<> 144:ef7eb2e8f9f7 17866 /******************** Bit definition for SR register *******************/
<> 161:2cc1468da177 17867 #define JPEG_SR_IFTF_Pos (1U)
<> 161:2cc1468da177 17868 #define JPEG_SR_IFTF_Msk (0x1U << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17869 #define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
<> 161:2cc1468da177 17870 #define JPEG_SR_IFNFF_Pos (2U)
<> 161:2cc1468da177 17871 #define JPEG_SR_IFNFF_Msk (0x1U << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17872 #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
<> 161:2cc1468da177 17873 #define JPEG_SR_OFTF_Pos (3U)
<> 161:2cc1468da177 17874 #define JPEG_SR_OFTF_Msk (0x1U << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17875 #define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
<> 161:2cc1468da177 17876 #define JPEG_SR_OFNEF_Pos (4U)
<> 161:2cc1468da177 17877 #define JPEG_SR_OFNEF_Msk (0x1U << JPEG_SR_OFNEF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17878 #define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
<> 161:2cc1468da177 17879 #define JPEG_SR_EOCF_Pos (5U)
<> 161:2cc1468da177 17880 #define JPEG_SR_EOCF_Msk (0x1U << JPEG_SR_EOCF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17881 #define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
<> 161:2cc1468da177 17882 #define JPEG_SR_HPDF_Pos (6U)
<> 161:2cc1468da177 17883 #define JPEG_SR_HPDF_Msk (0x1U << JPEG_SR_HPDF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17884 #define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
<> 161:2cc1468da177 17885 #define JPEG_SR_COF_Pos (7U)
<> 161:2cc1468da177 17886 #define JPEG_SR_COF_Msk (0x1U << JPEG_SR_COF_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17887 #define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
<> 144:ef7eb2e8f9f7 17888
<> 144:ef7eb2e8f9f7 17889 /******************** Bit definition for CFR register *******************/
<> 161:2cc1468da177 17890 #define JPEG_CFR_CEOCF_Pos (5U)
<> 161:2cc1468da177 17891 #define JPEG_CFR_CEOCF_Msk (0x1U << JPEG_CFR_CEOCF_Pos) /*!< 0x00000020 */
<> 161:2cc1468da177 17892 #define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
<> 161:2cc1468da177 17893 #define JPEG_CFR_CHPDF_Pos (6U)
<> 161:2cc1468da177 17894 #define JPEG_CFR_CHPDF_Msk (0x1U << JPEG_CFR_CHPDF_Pos) /*!< 0x00000040 */
<> 161:2cc1468da177 17895 #define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
<> 144:ef7eb2e8f9f7 17896
<> 144:ef7eb2e8f9f7 17897 /******************** Bit definition for DIR register ********************/
<> 161:2cc1468da177 17898 #define JPEG_DIR_DATAIN_Pos (0U)
<> 161:2cc1468da177 17899 #define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFU << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 17900 #define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
<> 144:ef7eb2e8f9f7 17901
<> 144:ef7eb2e8f9f7 17902 /******************** Bit definition for DOR register ********************/
<> 161:2cc1468da177 17903 #define JPEG_DOR_DATAOUT_Pos (0U)
<> 161:2cc1468da177 17904 #define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFU << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 17905 #define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
<> 144:ef7eb2e8f9f7 17906
<> 144:ef7eb2e8f9f7 17907 /******************************************************************************/
<> 144:ef7eb2e8f9f7 17908 /* */
<> 144:ef7eb2e8f9f7 17909 /* MDIOS */
<> 144:ef7eb2e8f9f7 17910 /* */
<> 144:ef7eb2e8f9f7 17911 /******************************************************************************/
<> 144:ef7eb2e8f9f7 17912 /******************** Bit definition for MDIOS_CR register *******************/
<> 161:2cc1468da177 17913 #define MDIOS_CR_EN_Pos (0U)
<> 161:2cc1468da177 17914 #define MDIOS_CR_EN_Msk (0x1U << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17915 #define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!<Peripheral enable */
<> 161:2cc1468da177 17916 #define MDIOS_CR_WRIE_Pos (1U)
<> 161:2cc1468da177 17917 #define MDIOS_CR_WRIE_Msk (0x1U << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17918 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!<Register write interrupt enable */
<> 161:2cc1468da177 17919 #define MDIOS_CR_RDIE_Pos (2U)
<> 161:2cc1468da177 17920 #define MDIOS_CR_RDIE_Msk (0x1U << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17921 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!<Register Read Interrupt Enable */
<> 161:2cc1468da177 17922 #define MDIOS_CR_EIE_Pos (3U)
<> 161:2cc1468da177 17923 #define MDIOS_CR_EIE_Msk (0x1U << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
<> 161:2cc1468da177 17924 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!<Error interrupt enable */
<> 161:2cc1468da177 17925 #define MDIOS_CR_DPC_Pos (7U)
<> 161:2cc1468da177 17926 #define MDIOS_CR_DPC_Msk (0x1U << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
<> 161:2cc1468da177 17927 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!<Disable Preamble Check */
<> 161:2cc1468da177 17928 #define MDIOS_CR_PORT_ADDRESS_Pos (8U)
<> 161:2cc1468da177 17929 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FU << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
<> 161:2cc1468da177 17930 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!<PORT_ADDRESS[4:0] bits */
<> 161:2cc1468da177 17931 #define MDIOS_CR_PORT_ADDRESS_0 (0x01U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
<> 161:2cc1468da177 17932 #define MDIOS_CR_PORT_ADDRESS_1 (0x02U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
<> 161:2cc1468da177 17933 #define MDIOS_CR_PORT_ADDRESS_2 (0x04U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
<> 161:2cc1468da177 17934 #define MDIOS_CR_PORT_ADDRESS_3 (0x08U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
<> 161:2cc1468da177 17935 #define MDIOS_CR_PORT_ADDRESS_4 (0x10U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
<> 144:ef7eb2e8f9f7 17936
<> 144:ef7eb2e8f9f7 17937 /******************** Bit definition for MDIOS_WRFR register *******************/
<> 161:2cc1468da177 17938 #define MDIOS_WRFR_WRF_Pos (0U)
<> 161:2cc1468da177 17939 #define MDIOS_WRFR_WRF_Msk (0xFFFFFFFFU << MDIOS_WRFR_WRF_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 17940 #define MDIOS_WRFR_WRF MDIOS_WRFR_WRF_Msk /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
<> 144:ef7eb2e8f9f7 17941
<> 144:ef7eb2e8f9f7 17942 /******************** Bit definition for MDIOS_CWRFR register *******************/
<> 161:2cc1468da177 17943 #define MDIOS_CWRFR_CWRF_Pos (0U)
<> 161:2cc1468da177 17944 #define MDIOS_CWRFR_CWRF_Msk (0xFFFFFFFFU << MDIOS_CWRFR_CWRF_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 17945 #define MDIOS_CWRFR_CWRF MDIOS_CWRFR_CWRF_Msk /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
<> 144:ef7eb2e8f9f7 17946
<> 144:ef7eb2e8f9f7 17947 /******************** Bit definition for MDIOS_RDFR register *******************/
<> 161:2cc1468da177 17948 #define MDIOS_RDFR_RDF_Pos (0U)
<> 161:2cc1468da177 17949 #define MDIOS_RDFR_RDF_Msk (0xFFFFFFFFU << MDIOS_RDFR_RDF_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 17950 #define MDIOS_RDFR_RDF MDIOS_RDFR_RDF_Msk /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
<> 144:ef7eb2e8f9f7 17951
<> 144:ef7eb2e8f9f7 17952 /******************** Bit definition for MDIOS_CRDFR register *******************/
<> 161:2cc1468da177 17953 #define MDIOS_CRDFR_CRDF_Pos (0U)
<> 161:2cc1468da177 17954 #define MDIOS_CRDFR_CRDF_Msk (0xFFFFFFFFU << MDIOS_CRDFR_CRDF_Pos) /*!< 0xFFFFFFFF */
<> 161:2cc1468da177 17955 #define MDIOS_CRDFR_CRDF MDIOS_CRDFR_CRDF_Msk /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
<> 144:ef7eb2e8f9f7 17956
<> 144:ef7eb2e8f9f7 17957 /******************** Bit definition for MDIOS_SR register *******************/
<> 161:2cc1468da177 17958 #define MDIOS_SR_PERF_Pos (0U)
<> 161:2cc1468da177 17959 #define MDIOS_SR_PERF_Msk (0x1U << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17960 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< Preamble error flag */
<> 161:2cc1468da177 17961 #define MDIOS_SR_SERF_Pos (1U)
<> 161:2cc1468da177 17962 #define MDIOS_SR_SERF_Msk (0x1U << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17963 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< Start error flag */
<> 161:2cc1468da177 17964 #define MDIOS_SR_TERF_Pos (2U)
<> 161:2cc1468da177 17965 #define MDIOS_SR_TERF_Msk (0x1U << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17966 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< Turnaround error flag */
<> 144:ef7eb2e8f9f7 17967
<> 144:ef7eb2e8f9f7 17968 /******************** Bit definition for MDIOS_CLRFR register *******************/
<> 161:2cc1468da177 17969 #define MDIOS_CLRFR_CPERF_Pos (0U)
<> 161:2cc1468da177 17970 #define MDIOS_CLRFR_CPERF_Msk (0x1U << MDIOS_CLRFR_CPERF_Pos) /*!< 0x00000001 */
<> 161:2cc1468da177 17971 #define MDIOS_CLRFR_CPERF MDIOS_CLRFR_CPERF_Msk /*!< Clear the preamble error flag */
<> 161:2cc1468da177 17972 #define MDIOS_CLRFR_CSERF_Pos (1U)
<> 161:2cc1468da177 17973 #define MDIOS_CLRFR_CSERF_Msk (0x1U << MDIOS_CLRFR_CSERF_Pos) /*!< 0x00000002 */
<> 161:2cc1468da177 17974 #define MDIOS_CLRFR_CSERF MDIOS_CLRFR_CSERF_Msk /*!< Clear the start error flag */
<> 161:2cc1468da177 17975 #define MDIOS_CLRFR_CTERF_Pos (2U)
<> 161:2cc1468da177 17976 #define MDIOS_CLRFR_CTERF_Msk (0x1U << MDIOS_CLRFR_CTERF_Pos) /*!< 0x00000004 */
<> 161:2cc1468da177 17977 #define MDIOS_CLRFR_CTERF MDIOS_CLRFR_CTERF_Msk /*!< Clear the turnaround error flag */
<> 144:ef7eb2e8f9f7 17978
<> 144:ef7eb2e8f9f7 17979 /**
<> 144:ef7eb2e8f9f7 17980 * @}
<> 144:ef7eb2e8f9f7 17981 */
<> 144:ef7eb2e8f9f7 17982
<> 144:ef7eb2e8f9f7 17983 /**
<> 144:ef7eb2e8f9f7 17984 * @}
<> 144:ef7eb2e8f9f7 17985 */
<> 144:ef7eb2e8f9f7 17986
<> 144:ef7eb2e8f9f7 17987 /** @addtogroup Exported_macros
<> 144:ef7eb2e8f9f7 17988 * @{
<> 144:ef7eb2e8f9f7 17989 */
<> 144:ef7eb2e8f9f7 17990
<> 144:ef7eb2e8f9f7 17991 /******************************* ADC Instances ********************************/
<> 144:ef7eb2e8f9f7 17992 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
<> 144:ef7eb2e8f9f7 17993 ((__INSTANCE__) == ADC2) || \
<> 144:ef7eb2e8f9f7 17994 ((__INSTANCE__) == ADC3))
<> 161:2cc1468da177 17995 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
<> 161:2cc1468da177 17996
<> 161:2cc1468da177 17997 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
<> 144:ef7eb2e8f9f7 17998
<> 144:ef7eb2e8f9f7 17999 /******************************* CAN Instances ********************************/
<> 144:ef7eb2e8f9f7 18000 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
<> 144:ef7eb2e8f9f7 18001 ((__INSTANCE__) == CAN2) || \
<> 144:ef7eb2e8f9f7 18002 ((__INSTANCE__) == CAN3))
<> 144:ef7eb2e8f9f7 18003 /******************************* CRC Instances ********************************/
<> 144:ef7eb2e8f9f7 18004 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
<> 144:ef7eb2e8f9f7 18005
<> 144:ef7eb2e8f9f7 18006 /******************************* DAC Instances ********************************/
<> 161:2cc1468da177 18007 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)
<> 144:ef7eb2e8f9f7 18008
<> 144:ef7eb2e8f9f7 18009 /******************************* DCMI Instances *******************************/
<> 144:ef7eb2e8f9f7 18010 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
<> 144:ef7eb2e8f9f7 18011
<> 144:ef7eb2e8f9f7 18012 /****************************** DFSDM Instances *******************************/
<> 144:ef7eb2e8f9f7 18013 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
<> 144:ef7eb2e8f9f7 18014 ((INSTANCE) == DFSDM1_Filter1) || \
<> 144:ef7eb2e8f9f7 18015 ((INSTANCE) == DFSDM1_Filter2) || \
<> 144:ef7eb2e8f9f7 18016 ((INSTANCE) == DFSDM1_Filter3))
<> 144:ef7eb2e8f9f7 18017
<> 144:ef7eb2e8f9f7 18018 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
<> 144:ef7eb2e8f9f7 18019 ((INSTANCE) == DFSDM1_Channel1) || \
<> 144:ef7eb2e8f9f7 18020 ((INSTANCE) == DFSDM1_Channel2) || \
<> 144:ef7eb2e8f9f7 18021 ((INSTANCE) == DFSDM1_Channel3) || \
<> 144:ef7eb2e8f9f7 18022 ((INSTANCE) == DFSDM1_Channel4) || \
<> 144:ef7eb2e8f9f7 18023 ((INSTANCE) == DFSDM1_Channel5) || \
<> 144:ef7eb2e8f9f7 18024 ((INSTANCE) == DFSDM1_Channel6) || \
<> 144:ef7eb2e8f9f7 18025 ((INSTANCE) == DFSDM1_Channel7))
<> 144:ef7eb2e8f9f7 18026
<> 144:ef7eb2e8f9f7 18027 /******************************* DMA2D Instances *******************************/
<> 144:ef7eb2e8f9f7 18028 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
<> 144:ef7eb2e8f9f7 18029
<> 144:ef7eb2e8f9f7 18030 /******************************** DMA Instances *******************************/
<> 144:ef7eb2e8f9f7 18031 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
<> 144:ef7eb2e8f9f7 18032 ((__INSTANCE__) == DMA1_Stream1) || \
<> 144:ef7eb2e8f9f7 18033 ((__INSTANCE__) == DMA1_Stream2) || \
<> 144:ef7eb2e8f9f7 18034 ((__INSTANCE__) == DMA1_Stream3) || \
<> 144:ef7eb2e8f9f7 18035 ((__INSTANCE__) == DMA1_Stream4) || \
<> 144:ef7eb2e8f9f7 18036 ((__INSTANCE__) == DMA1_Stream5) || \
<> 144:ef7eb2e8f9f7 18037 ((__INSTANCE__) == DMA1_Stream6) || \
<> 144:ef7eb2e8f9f7 18038 ((__INSTANCE__) == DMA1_Stream7) || \
<> 144:ef7eb2e8f9f7 18039 ((__INSTANCE__) == DMA2_Stream0) || \
<> 144:ef7eb2e8f9f7 18040 ((__INSTANCE__) == DMA2_Stream1) || \
<> 144:ef7eb2e8f9f7 18041 ((__INSTANCE__) == DMA2_Stream2) || \
<> 144:ef7eb2e8f9f7 18042 ((__INSTANCE__) == DMA2_Stream3) || \
<> 144:ef7eb2e8f9f7 18043 ((__INSTANCE__) == DMA2_Stream4) || \
<> 144:ef7eb2e8f9f7 18044 ((__INSTANCE__) == DMA2_Stream5) || \
<> 144:ef7eb2e8f9f7 18045 ((__INSTANCE__) == DMA2_Stream6) || \
<> 144:ef7eb2e8f9f7 18046 ((__INSTANCE__) == DMA2_Stream7))
<> 144:ef7eb2e8f9f7 18047
<> 144:ef7eb2e8f9f7 18048 /******************************* GPIO Instances *******************************/
<> 144:ef7eb2e8f9f7 18049 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
<> 157:ff67d9f36b67 18050 ((__INSTANCE__) == GPIOB) || \
<> 157:ff67d9f36b67 18051 ((__INSTANCE__) == GPIOC) || \
<> 157:ff67d9f36b67 18052 ((__INSTANCE__) == GPIOD) || \
<> 157:ff67d9f36b67 18053 ((__INSTANCE__) == GPIOE) || \
<> 157:ff67d9f36b67 18054 ((__INSTANCE__) == GPIOF) || \
<> 157:ff67d9f36b67 18055 ((__INSTANCE__) == GPIOG) || \
<> 157:ff67d9f36b67 18056 ((__INSTANCE__) == GPIOH) || \
<> 157:ff67d9f36b67 18057 ((__INSTANCE__) == GPIOI) || \
<> 157:ff67d9f36b67 18058 ((__INSTANCE__) == GPIOJ) || \
<> 157:ff67d9f36b67 18059 ((__INSTANCE__) == GPIOK))
<> 161:2cc1468da177 18060
<> 144:ef7eb2e8f9f7 18061 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
<> 157:ff67d9f36b67 18062 ((__INSTANCE__) == GPIOB) || \
<> 157:ff67d9f36b67 18063 ((__INSTANCE__) == GPIOC) || \
<> 157:ff67d9f36b67 18064 ((__INSTANCE__) == GPIOD) || \
<> 157:ff67d9f36b67 18065 ((__INSTANCE__) == GPIOE) || \
<> 157:ff67d9f36b67 18066 ((__INSTANCE__) == GPIOF) || \
<> 157:ff67d9f36b67 18067 ((__INSTANCE__) == GPIOG) || \
<> 157:ff67d9f36b67 18068 ((__INSTANCE__) == GPIOH) || \
<> 157:ff67d9f36b67 18069 ((__INSTANCE__) == GPIOI) || \
<> 157:ff67d9f36b67 18070 ((__INSTANCE__) == GPIOJ) || \
<> 157:ff67d9f36b67 18071 ((__INSTANCE__) == GPIOK))
<> 144:ef7eb2e8f9f7 18072
<> 144:ef7eb2e8f9f7 18073 /****************************** CEC Instances *********************************/
<> 144:ef7eb2e8f9f7 18074 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
<> 144:ef7eb2e8f9f7 18075
<> 144:ef7eb2e8f9f7 18076 /****************************** QSPI Instances *********************************/
<> 144:ef7eb2e8f9f7 18077 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
<> 144:ef7eb2e8f9f7 18078
<> 161:2cc1468da177 18079
<> 144:ef7eb2e8f9f7 18080 /******************************** I2C Instances *******************************/
<> 144:ef7eb2e8f9f7 18081 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
<> 157:ff67d9f36b67 18082 ((__INSTANCE__) == I2C2) || \
<> 157:ff67d9f36b67 18083 ((__INSTANCE__) == I2C3) || \
<> 157:ff67d9f36b67 18084 ((__INSTANCE__) == I2C4))
<> 144:ef7eb2e8f9f7 18085
<> 161:2cc1468da177 18086 /****************************** SMBUS Instances *******************************/
<> 161:2cc1468da177 18087 #define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
<> 161:2cc1468da177 18088 ((__INSTANCE__) == I2C2) || \
<> 161:2cc1468da177 18089 ((__INSTANCE__) == I2C3) || \
<> 161:2cc1468da177 18090 ((__INSTANCE__) == I2C4))
<> 161:2cc1468da177 18091
<> 161:2cc1468da177 18092
<> 144:ef7eb2e8f9f7 18093 /******************************** I2S Instances *******************************/
<> 144:ef7eb2e8f9f7 18094 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
<> 157:ff67d9f36b67 18095 ((__INSTANCE__) == SPI2) || \
<> 157:ff67d9f36b67 18096 ((__INSTANCE__) == SPI3))
<> 144:ef7eb2e8f9f7 18097
<> 144:ef7eb2e8f9f7 18098 /******************************* LPTIM Instances ********************************/
<> 144:ef7eb2e8f9f7 18099 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
<> 144:ef7eb2e8f9f7 18100
<> 144:ef7eb2e8f9f7 18101 /****************************** LTDC Instances ********************************/
<> 144:ef7eb2e8f9f7 18102 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
<> 144:ef7eb2e8f9f7 18103
<> 144:ef7eb2e8f9f7 18104 /****************************** MDIOS Instances ********************************/
<> 144:ef7eb2e8f9f7 18105 #define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
<> 144:ef7eb2e8f9f7 18106
<> 144:ef7eb2e8f9f7 18107 /****************************** MDIOS Instances ********************************/
<> 144:ef7eb2e8f9f7 18108 #define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
<> 144:ef7eb2e8f9f7 18109
<> 157:ff67d9f36b67 18110
<> 144:ef7eb2e8f9f7 18111 /******************************* RNG Instances ********************************/
<> 144:ef7eb2e8f9f7 18112 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
<> 144:ef7eb2e8f9f7 18113
<> 144:ef7eb2e8f9f7 18114 /****************************** RTC Instances *********************************/
<> 144:ef7eb2e8f9f7 18115 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
<> 144:ef7eb2e8f9f7 18116
<> 144:ef7eb2e8f9f7 18117 /******************************* SAI Instances ********************************/
<> 144:ef7eb2e8f9f7 18118 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
<> 144:ef7eb2e8f9f7 18119 ((__PERIPH__) == SAI1_Block_B) || \
<> 144:ef7eb2e8f9f7 18120 ((__PERIPH__) == SAI2_Block_A) || \
<> 144:ef7eb2e8f9f7 18121 ((__PERIPH__) == SAI2_Block_B))
<> 144:ef7eb2e8f9f7 18122 /* Legacy define */
<> 144:ef7eb2e8f9f7 18123 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
<> 144:ef7eb2e8f9f7 18124
<> 144:ef7eb2e8f9f7 18125 /******************************** SDMMC Instances *******************************/
<> 144:ef7eb2e8f9f7 18126 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
<> 144:ef7eb2e8f9f7 18127 ((__INSTANCE__) == SDMMC2))
<> 144:ef7eb2e8f9f7 18128
<> 144:ef7eb2e8f9f7 18129 /****************************** SPDIFRX Instances *********************************/
<> 144:ef7eb2e8f9f7 18130 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
<> 161:2cc1468da177 18131
<> 144:ef7eb2e8f9f7 18132 /******************************** SPI Instances *******************************/
<> 144:ef7eb2e8f9f7 18133 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
<> 157:ff67d9f36b67 18134 ((__INSTANCE__) == SPI2) || \
<> 157:ff67d9f36b67 18135 ((__INSTANCE__) == SPI3) || \
<> 157:ff67d9f36b67 18136 ((__INSTANCE__) == SPI4) || \
<> 157:ff67d9f36b67 18137 ((__INSTANCE__) == SPI5) || \
<> 157:ff67d9f36b67 18138 ((__INSTANCE__) == SPI6))
<> 144:ef7eb2e8f9f7 18139
<> 144:ef7eb2e8f9f7 18140 /****************** TIM Instances : All supported instances *******************/
<> 144:ef7eb2e8f9f7 18141 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18142 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18143 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18144 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18145 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18146 ((__INSTANCE__) == TIM6) || \
<> 144:ef7eb2e8f9f7 18147 ((__INSTANCE__) == TIM7) || \
<> 144:ef7eb2e8f9f7 18148 ((__INSTANCE__) == TIM8) || \
<> 144:ef7eb2e8f9f7 18149 ((__INSTANCE__) == TIM9) || \
<> 144:ef7eb2e8f9f7 18150 ((__INSTANCE__) == TIM10) || \
<> 144:ef7eb2e8f9f7 18151 ((__INSTANCE__) == TIM11) || \
<> 144:ef7eb2e8f9f7 18152 ((__INSTANCE__) == TIM12) || \
<> 144:ef7eb2e8f9f7 18153 ((__INSTANCE__) == TIM13) || \
<> 144:ef7eb2e8f9f7 18154 ((__INSTANCE__) == TIM14))
<> 144:ef7eb2e8f9f7 18155
<> 161:2cc1468da177 18156 /****************** TIM Instances : supporting 32 bits counter ****************/
<> 161:2cc1468da177 18157 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
<> 161:2cc1468da177 18158 ((__INSTANCE__) == TIM5))
<> 161:2cc1468da177 18159
<> 161:2cc1468da177 18160 /****************** TIM Instances : supporting the break function *************/
<> 161:2cc1468da177 18161 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 161:2cc1468da177 18162 ((INSTANCE) == TIM8))
<> 161:2cc1468da177 18163
<> 161:2cc1468da177 18164 /************** TIM Instances : supporting Break source selection *************/
<> 161:2cc1468da177 18165 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 161:2cc1468da177 18166 ((INSTANCE) == TIM8))
<> 161:2cc1468da177 18167
<> 161:2cc1468da177 18168 /****************** TIM Instances : supporting 2 break inputs *****************/
<> 161:2cc1468da177 18169 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 161:2cc1468da177 18170 ((INSTANCE) == TIM8))
<> 161:2cc1468da177 18171
<> 144:ef7eb2e8f9f7 18172 /************* TIM Instances : at least 1 capture/compare channel *************/
<> 144:ef7eb2e8f9f7 18173 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18174 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18175 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18176 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18177 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18178 ((__INSTANCE__) == TIM8) || \
<> 144:ef7eb2e8f9f7 18179 ((__INSTANCE__) == TIM9) || \
<> 144:ef7eb2e8f9f7 18180 ((__INSTANCE__) == TIM10) || \
<> 144:ef7eb2e8f9f7 18181 ((__INSTANCE__) == TIM11) || \
<> 144:ef7eb2e8f9f7 18182 ((__INSTANCE__) == TIM12) || \
<> 144:ef7eb2e8f9f7 18183 ((__INSTANCE__) == TIM13) || \
<> 144:ef7eb2e8f9f7 18184 ((__INSTANCE__) == TIM14))
<> 144:ef7eb2e8f9f7 18185
<> 144:ef7eb2e8f9f7 18186 /************ TIM Instances : at least 2 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 18187 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18188 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18189 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18190 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18191 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18192 ((__INSTANCE__) == TIM8) || \
<> 144:ef7eb2e8f9f7 18193 ((__INSTANCE__) == TIM9) || \
<> 144:ef7eb2e8f9f7 18194 ((__INSTANCE__) == TIM12))
<> 144:ef7eb2e8f9f7 18195
<> 144:ef7eb2e8f9f7 18196 /************ TIM Instances : at least 3 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 18197 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18198 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18199 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18200 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18201 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18202 ((__INSTANCE__) == TIM8))
<> 144:ef7eb2e8f9f7 18203
<> 144:ef7eb2e8f9f7 18204 /************ TIM Instances : at least 4 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 18205 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18206 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18207 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18208 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18209 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18210 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18211
<> 161:2cc1468da177 18212 /****************** TIM Instances : at least 5 capture/compare channels *******/
<> 161:2cc1468da177 18213 #define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18214 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18215
<> 161:2cc1468da177 18216 /****************** TIM Instances : at least 6 capture/compare channels *******/
<> 161:2cc1468da177 18217 #define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18218 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18219
<> 161:2cc1468da177 18220 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
<> 161:2cc1468da177 18221 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18222 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18223
<> 161:2cc1468da177 18224 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
<> 161:2cc1468da177 18225 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18226 ((__INSTANCE__) == TIM8) || \
<> 161:2cc1468da177 18227 ((__INSTANCE__) == TIM2) || \
<> 161:2cc1468da177 18228 ((__INSTANCE__) == TIM3) || \
<> 161:2cc1468da177 18229 ((__INSTANCE__) == TIM4) || \
<> 161:2cc1468da177 18230 ((__INSTANCE__) == TIM5) || \
<> 161:2cc1468da177 18231 ((__INSTANCE__) == TIM6) || \
<> 161:2cc1468da177 18232 ((__INSTANCE__) == TIM7))
<> 161:2cc1468da177 18233
<> 161:2cc1468da177 18234 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
<> 161:2cc1468da177 18235 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18236 ((__INSTANCE__) == TIM2) || \
<> 161:2cc1468da177 18237 ((__INSTANCE__) == TIM3) || \
<> 161:2cc1468da177 18238 ((__INSTANCE__) == TIM4) || \
<> 161:2cc1468da177 18239 ((__INSTANCE__) == TIM5) || \
<> 161:2cc1468da177 18240 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18241
<> 161:2cc1468da177 18242 /******************** TIM Instances : DMA burst feature ***********************/
<> 161:2cc1468da177 18243 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18244 ((__INSTANCE__) == TIM2) || \
<> 161:2cc1468da177 18245 ((__INSTANCE__) == TIM3) || \
<> 161:2cc1468da177 18246 ((__INSTANCE__) == TIM4) || \
<> 161:2cc1468da177 18247 ((__INSTANCE__) == TIM5) || \
<> 161:2cc1468da177 18248 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18249
<> 144:ef7eb2e8f9f7 18250 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
<> 144:ef7eb2e8f9f7 18251 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
<> 144:ef7eb2e8f9f7 18252 (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18253 ((__INSTANCE__) == TIM8))
<> 144:ef7eb2e8f9f7 18254
<> 161:2cc1468da177 18255 /****************** TIM Instances : supporting counting mode selection ********/
<> 161:2cc1468da177 18256 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18257 ((__INSTANCE__) == TIM2) || \
<> 161:2cc1468da177 18258 ((__INSTANCE__) == TIM3) || \
<> 161:2cc1468da177 18259 ((__INSTANCE__) == TIM4) || \
<> 161:2cc1468da177 18260 ((__INSTANCE__) == TIM5) || \
<> 161:2cc1468da177 18261 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18262
<> 161:2cc1468da177 18263 /****************** TIM Instances : supporting encoder interface **************/
<> 161:2cc1468da177 18264 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18265 ((__INSTANCE__) == TIM2) || \
<> 161:2cc1468da177 18266 ((__INSTANCE__) == TIM3) || \
<> 161:2cc1468da177 18267 ((__INSTANCE__) == TIM4) || \
<> 161:2cc1468da177 18268 ((__INSTANCE__) == TIM5) || \
<> 161:2cc1468da177 18269 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18270
<> 144:ef7eb2e8f9f7 18271 /****************** TIM Instances : supporting OCxREF clear *******************/
<> 144:ef7eb2e8f9f7 18272 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
<> 161:2cc1468da177 18273 (((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18274 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18275 ((__INSTANCE__) == TIM4) || \
<> 161:2cc1468da177 18276 ((__INSTANCE__) == TIM5))
<> 144:ef7eb2e8f9f7 18277
<> 144:ef7eb2e8f9f7 18278 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
<> 144:ef7eb2e8f9f7 18279 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
<> 144:ef7eb2e8f9f7 18280 (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18281 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18282 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18283 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18284 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18285 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18286
<> 144:ef7eb2e8f9f7 18287 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
<> 144:ef7eb2e8f9f7 18288 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
<> 144:ef7eb2e8f9f7 18289 (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18290 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18291 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18292 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18293 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18294 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18295
<> 144:ef7eb2e8f9f7 18296 /******************** TIM Instances : Advanced-control timers *****************/
<> 144:ef7eb2e8f9f7 18297 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18298 ((__INSTANCE__) == TIM8))
<> 144:ef7eb2e8f9f7 18299
<> 144:ef7eb2e8f9f7 18300 /******************* TIM Instances : Timer input XOR function *****************/
<> 144:ef7eb2e8f9f7 18301 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18302 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18303 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18304 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18305 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18306 ((__INSTANCE__) == TIM8))
<> 144:ef7eb2e8f9f7 18307
<> 144:ef7eb2e8f9f7 18308 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
<> 144:ef7eb2e8f9f7 18309 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18310 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18311 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18312 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18313 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18314 ((__INSTANCE__) == TIM6) || \
<> 144:ef7eb2e8f9f7 18315 ((__INSTANCE__) == TIM7) || \
<> 161:2cc1468da177 18316 ((__INSTANCE__) == TIM8))
<> 144:ef7eb2e8f9f7 18317
<> 144:ef7eb2e8f9f7 18318 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
<> 144:ef7eb2e8f9f7 18319 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18320 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18321 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18322 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18323 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18324 ((__INSTANCE__) == TIM8) || \
<> 144:ef7eb2e8f9f7 18325 ((__INSTANCE__) == TIM9) || \
<> 144:ef7eb2e8f9f7 18326 ((__INSTANCE__) == TIM12))
<> 144:ef7eb2e8f9f7 18327
<> 144:ef7eb2e8f9f7 18328 /***************** TIM Instances : external trigger input available ************/
<> 144:ef7eb2e8f9f7 18329 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18330 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18331 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18332 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18333 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18334 ((__INSTANCE__) == TIM8))
<> 144:ef7eb2e8f9f7 18335
<> 144:ef7eb2e8f9f7 18336 /****************** TIM Instances : remapping capability **********************/
<> 144:ef7eb2e8f9f7 18337 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18338 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18339 ((__INSTANCE__) == TIM11))
<> 144:ef7eb2e8f9f7 18340
<> 144:ef7eb2e8f9f7 18341 /******************* TIM Instances : output(s) available **********************/
<> 144:ef7eb2e8f9f7 18342 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 18343 ((((__INSTANCE__) == TIM1) && \
<> 144:ef7eb2e8f9f7 18344 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 18345 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 18346 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 161:2cc1468da177 18347 ((__CHANNEL__) == TIM_CHANNEL_4) || \
<> 161:2cc1468da177 18348 ((__CHANNEL__) == TIM_CHANNEL_5) || \
<> 161:2cc1468da177 18349 ((__CHANNEL__) == TIM_CHANNEL_6))) \
<> 144:ef7eb2e8f9f7 18350 || \
<> 144:ef7eb2e8f9f7 18351 (((__INSTANCE__) == TIM2) && \
<> 144:ef7eb2e8f9f7 18352 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 18353 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 18354 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 18355 ((__CHANNEL__) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 18356 || \
<> 144:ef7eb2e8f9f7 18357 (((__INSTANCE__) == TIM3) && \
<> 144:ef7eb2e8f9f7 18358 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 18359 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 18360 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 18361 ((__CHANNEL__) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 18362 || \
<> 144:ef7eb2e8f9f7 18363 (((__INSTANCE__) == TIM4) && \
<> 144:ef7eb2e8f9f7 18364 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 18365 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 18366 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 18367 ((__CHANNEL__) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 18368 || \
<> 144:ef7eb2e8f9f7 18369 (((__INSTANCE__) == TIM5) && \
<> 144:ef7eb2e8f9f7 18370 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 18371 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 18372 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 18373 ((__CHANNEL__) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 18374 || \
<> 144:ef7eb2e8f9f7 18375 (((__INSTANCE__) == TIM8) && \
<> 144:ef7eb2e8f9f7 18376 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 18377 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 18378 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 161:2cc1468da177 18379 ((__CHANNEL__) == TIM_CHANNEL_4) || \
<> 161:2cc1468da177 18380 ((__CHANNEL__) == TIM_CHANNEL_5) || \
<> 161:2cc1468da177 18381 ((__CHANNEL__) == TIM_CHANNEL_6))) \
<> 144:ef7eb2e8f9f7 18382 || \
<> 144:ef7eb2e8f9f7 18383 (((__INSTANCE__) == TIM9) && \
<> 144:ef7eb2e8f9f7 18384 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 18385 ((__CHANNEL__) == TIM_CHANNEL_2))) \
<> 144:ef7eb2e8f9f7 18386 || \
<> 144:ef7eb2e8f9f7 18387 (((__INSTANCE__) == TIM10) && \
<> 144:ef7eb2e8f9f7 18388 (((__CHANNEL__) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 18389 || \
<> 144:ef7eb2e8f9f7 18390 (((__INSTANCE__) == TIM11) && \
<> 144:ef7eb2e8f9f7 18391 (((__CHANNEL__) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 18392 || \
<> 144:ef7eb2e8f9f7 18393 (((__INSTANCE__) == TIM12) && \
<> 144:ef7eb2e8f9f7 18394 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 18395 ((__CHANNEL__) == TIM_CHANNEL_2))) \
<> 144:ef7eb2e8f9f7 18396 || \
<> 144:ef7eb2e8f9f7 18397 (((__INSTANCE__) == TIM13) && \
<> 144:ef7eb2e8f9f7 18398 (((__CHANNEL__) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 18399 || \
<> 144:ef7eb2e8f9f7 18400 (((__INSTANCE__) == TIM14) && \
<> 144:ef7eb2e8f9f7 18401 (((__CHANNEL__) == TIM_CHANNEL_1))))
<> 144:ef7eb2e8f9f7 18402
<> 144:ef7eb2e8f9f7 18403 /************ TIM Instances : complementary output(s) available ***************/
<> 144:ef7eb2e8f9f7 18404 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 18405 ((((__INSTANCE__) == TIM1) && \
<> 144:ef7eb2e8f9f7 18406 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 18407 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 18408 ((__CHANNEL__) == TIM_CHANNEL_3))) \
<> 144:ef7eb2e8f9f7 18409 || \
<> 144:ef7eb2e8f9f7 18410 (((__INSTANCE__) == TIM8) && \
<> 144:ef7eb2e8f9f7 18411 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 18412 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 18413 ((__CHANNEL__) == TIM_CHANNEL_3))))
<> 144:ef7eb2e8f9f7 18414
<> 144:ef7eb2e8f9f7 18415 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
<> 144:ef7eb2e8f9f7 18416 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
<> 144:ef7eb2e8f9f7 18417 (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18418 ((__INSTANCE__) == TIM8) )
<> 144:ef7eb2e8f9f7 18419
<> 144:ef7eb2e8f9f7 18420 /****************** TIM Instances : supporting synchronization ****************/
<> 144:ef7eb2e8f9f7 18421 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
<> 144:ef7eb2e8f9f7 18422 (((__INSTANCE__) == TIM1) || \
<> 144:ef7eb2e8f9f7 18423 ((__INSTANCE__) == TIM2) || \
<> 144:ef7eb2e8f9f7 18424 ((__INSTANCE__) == TIM3) || \
<> 144:ef7eb2e8f9f7 18425 ((__INSTANCE__) == TIM4) || \
<> 144:ef7eb2e8f9f7 18426 ((__INSTANCE__) == TIM5) || \
<> 144:ef7eb2e8f9f7 18427 ((__INSTANCE__) == TIM6) || \
<> 144:ef7eb2e8f9f7 18428 ((__INSTANCE__) == TIM7) || \
<> 161:2cc1468da177 18429 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18430
<> 161:2cc1468da177 18431 /****************** TIM Instances : supporting clock division *****************/
<> 161:2cc1468da177 18432 #define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18433 ((__INSTANCE__) == TIM2) || \
<> 161:2cc1468da177 18434 ((__INSTANCE__) == TIM3) || \
<> 161:2cc1468da177 18435 ((__INSTANCE__) == TIM4) || \
<> 161:2cc1468da177 18436 ((__INSTANCE__) == TIM5) || \
<> 161:2cc1468da177 18437 ((__INSTANCE__) == TIM8) || \
<> 161:2cc1468da177 18438 ((__INSTANCE__) == TIM9) || \
<> 161:2cc1468da177 18439 ((__INSTANCE__) == TIM10) || \
<> 161:2cc1468da177 18440 ((__INSTANCE__) == TIM11) || \
<> 161:2cc1468da177 18441 ((__INSTANCE__) == TIM12) || \
<> 161:2cc1468da177 18442 ((__INSTANCE__) == TIM13) || \
<> 161:2cc1468da177 18443 ((__INSTANCE__) == TIM14))
<> 161:2cc1468da177 18444
<> 161:2cc1468da177 18445 /****************** TIM Instances : supporting repetition counter *************/
<> 161:2cc1468da177 18446 #define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18447 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18448
<> 161:2cc1468da177 18449 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
<> 161:2cc1468da177 18450 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18451 ((__INSTANCE__) == TIM2) || \
<> 161:2cc1468da177 18452 ((__INSTANCE__) == TIM3) || \
<> 161:2cc1468da177 18453 ((__INSTANCE__) == TIM4) || \
<> 161:2cc1468da177 18454 ((__INSTANCE__) == TIM5) || \
<> 161:2cc1468da177 18455 ((__INSTANCE__) == TIM8) || \
<> 161:2cc1468da177 18456 ((__INSTANCE__) == TIM9) || \
<> 161:2cc1468da177 18457 ((__INSTANCE__) == TIM12))
<> 161:2cc1468da177 18458
<> 161:2cc1468da177 18459 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
<> 161:2cc1468da177 18460 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18461 ((__INSTANCE__) == TIM2) || \
<> 161:2cc1468da177 18462 ((__INSTANCE__) == TIM3) || \
<> 161:2cc1468da177 18463 ((__INSTANCE__) == TIM4) || \
<> 161:2cc1468da177 18464 ((__INSTANCE__) == TIM5) || \
<> 161:2cc1468da177 18465 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18466
<> 161:2cc1468da177 18467 /****************** TIM Instances : supporting Hall sensor interface **********/
<> 161:2cc1468da177 18468 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18469 ((__INSTANCE__) == TIM2) || \
<> 161:2cc1468da177 18470 ((__INSTANCE__) == TIM3) || \
<> 161:2cc1468da177 18471 ((__INSTANCE__) == TIM4) || \
<> 161:2cc1468da177 18472 ((__INSTANCE__) == TIM5) || \
<> 161:2cc1468da177 18473 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18474
<> 161:2cc1468da177 18475 /****************** TIM Instances : supporting commutation event generation ***/
<> 161:2cc1468da177 18476 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 161:2cc1468da177 18477 ((__INSTANCE__) == TIM8))
<> 161:2cc1468da177 18478
<> 144:ef7eb2e8f9f7 18479 /******************** USART Instances : Synchronous mode **********************/
<> 144:ef7eb2e8f9f7 18480 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 161:2cc1468da177 18481 ((__INSTANCE__) == USART2) || \
<> 161:2cc1468da177 18482 ((__INSTANCE__) == USART3) || \
<> 161:2cc1468da177 18483 ((__INSTANCE__) == USART6))
<> 144:ef7eb2e8f9f7 18484
<> 144:ef7eb2e8f9f7 18485 /******************** UART Instances : Asynchronous mode **********************/
<> 144:ef7eb2e8f9f7 18486 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 144:ef7eb2e8f9f7 18487 ((__INSTANCE__) == USART2) || \
<> 144:ef7eb2e8f9f7 18488 ((__INSTANCE__) == USART3) || \
<> 144:ef7eb2e8f9f7 18489 ((__INSTANCE__) == UART4) || \
<> 144:ef7eb2e8f9f7 18490 ((__INSTANCE__) == UART5) || \
<> 144:ef7eb2e8f9f7 18491 ((__INSTANCE__) == USART6) || \
<> 144:ef7eb2e8f9f7 18492 ((__INSTANCE__) == UART7) || \
<> 144:ef7eb2e8f9f7 18493 ((__INSTANCE__) == UART8))
<> 144:ef7eb2e8f9f7 18494
<> 161:2cc1468da177 18495 /****************** UART Instances : Auto Baud Rate detection ****************/
<> 161:2cc1468da177 18496 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 161:2cc1468da177 18497 ((__INSTANCE__) == USART2) || \
<> 161:2cc1468da177 18498 ((__INSTANCE__) == USART3) || \
<> 161:2cc1468da177 18499 ((__INSTANCE__) == USART6))
<> 161:2cc1468da177 18500
<> 144:ef7eb2e8f9f7 18501 /****************** UART Instances : Driver Enable *****************/
<> 144:ef7eb2e8f9f7 18502 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 144:ef7eb2e8f9f7 18503 ((__INSTANCE__) == USART2) || \
<> 144:ef7eb2e8f9f7 18504 ((__INSTANCE__) == USART3) || \
<> 144:ef7eb2e8f9f7 18505 ((__INSTANCE__) == UART4) || \
<> 144:ef7eb2e8f9f7 18506 ((__INSTANCE__) == UART5) || \
<> 144:ef7eb2e8f9f7 18507 ((__INSTANCE__) == USART6) || \
<> 144:ef7eb2e8f9f7 18508 ((__INSTANCE__) == UART7) || \
<> 144:ef7eb2e8f9f7 18509 ((__INSTANCE__) == UART8))
<> 144:ef7eb2e8f9f7 18510
<> 161:2cc1468da177 18511 /******************** UART Instances : Half-Duplex mode **********************/
<> 161:2cc1468da177 18512 #define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 161:2cc1468da177 18513 ((__INSTANCE__) == USART2) || \
<> 161:2cc1468da177 18514 ((__INSTANCE__) == USART3) || \
<> 161:2cc1468da177 18515 ((__INSTANCE__) == UART4) || \
<> 161:2cc1468da177 18516 ((__INSTANCE__) == UART5) || \
<> 161:2cc1468da177 18517 ((__INSTANCE__) == USART6) || \
<> 161:2cc1468da177 18518 ((__INSTANCE__) == UART7) || \
<> 161:2cc1468da177 18519 ((__INSTANCE__) == UART8))
<> 161:2cc1468da177 18520
<> 144:ef7eb2e8f9f7 18521 /****************** UART Instances : Hardware Flow control ********************/
<> 144:ef7eb2e8f9f7 18522 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 144:ef7eb2e8f9f7 18523 ((__INSTANCE__) == USART2) || \
<> 144:ef7eb2e8f9f7 18524 ((__INSTANCE__) == USART3) || \
<> 144:ef7eb2e8f9f7 18525 ((__INSTANCE__) == UART4) || \
<> 144:ef7eb2e8f9f7 18526 ((__INSTANCE__) == UART5) || \
<> 144:ef7eb2e8f9f7 18527 ((__INSTANCE__) == USART6) || \
<> 144:ef7eb2e8f9f7 18528 ((__INSTANCE__) == UART7) || \
<> 144:ef7eb2e8f9f7 18529 ((__INSTANCE__) == UART8))
<> 144:ef7eb2e8f9f7 18530
<> 161:2cc1468da177 18531 /******************** UART Instances : LIN mode **********************/
<> 161:2cc1468da177 18532 #define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 161:2cc1468da177 18533 ((__INSTANCE__) == USART2) || \
<> 161:2cc1468da177 18534 ((__INSTANCE__) == USART3) || \
<> 161:2cc1468da177 18535 ((__INSTANCE__) == UART4) || \
<> 161:2cc1468da177 18536 ((__INSTANCE__) == UART5) || \
<> 161:2cc1468da177 18537 ((__INSTANCE__) == USART6) || \
<> 161:2cc1468da177 18538 ((__INSTANCE__) == UART7) || \
<> 161:2cc1468da177 18539 ((__INSTANCE__) == UART8))
<> 161:2cc1468da177 18540
<> 144:ef7eb2e8f9f7 18541 /********************* UART Instances : Smart card mode ***********************/
<> 144:ef7eb2e8f9f7 18542 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 144:ef7eb2e8f9f7 18543 ((__INSTANCE__) == USART2) || \
<> 144:ef7eb2e8f9f7 18544 ((__INSTANCE__) == USART3) || \
<> 144:ef7eb2e8f9f7 18545 ((__INSTANCE__) == USART6))
<> 144:ef7eb2e8f9f7 18546
<> 144:ef7eb2e8f9f7 18547 /*********************** UART Instances : IRDA mode ***************************/
<> 144:ef7eb2e8f9f7 18548 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 144:ef7eb2e8f9f7 18549 ((__INSTANCE__) == USART2) || \
<> 144:ef7eb2e8f9f7 18550 ((__INSTANCE__) == USART3) || \
<> 144:ef7eb2e8f9f7 18551 ((__INSTANCE__) == UART4) || \
<> 144:ef7eb2e8f9f7 18552 ((__INSTANCE__) == UART5) || \
<> 144:ef7eb2e8f9f7 18553 ((__INSTANCE__) == USART6) || \
<> 144:ef7eb2e8f9f7 18554 ((__INSTANCE__) == UART7) || \
<> 161:2cc1468da177 18555 ((__INSTANCE__) == UART8))
<> 144:ef7eb2e8f9f7 18556
<> 144:ef7eb2e8f9f7 18557 /****************************** IWDG Instances ********************************/
<> 144:ef7eb2e8f9f7 18558 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
<> 144:ef7eb2e8f9f7 18559
<> 144:ef7eb2e8f9f7 18560 /****************************** WWDG Instances ********************************/
<> 144:ef7eb2e8f9f7 18561 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
<> 144:ef7eb2e8f9f7 18562
<> 144:ef7eb2e8f9f7 18563
<> 144:ef7eb2e8f9f7 18564 /******************************************************************************/
<> 144:ef7eb2e8f9f7 18565 /* For a painless codes migration between the STM32F7xx device product */
<> 144:ef7eb2e8f9f7 18566 /* lines, the aliases defined below are put in place to overcome the */
<> 144:ef7eb2e8f9f7 18567 /* differences in the interrupt handlers and IRQn definitions. */
<> 144:ef7eb2e8f9f7 18568 /* No need to update developed interrupt code when moving across */
<> 144:ef7eb2e8f9f7 18569 /* product lines within the same STM32F7 Family */
<> 144:ef7eb2e8f9f7 18570 /******************************************************************************/
<> 144:ef7eb2e8f9f7 18571
<> 144:ef7eb2e8f9f7 18572 /* Aliases for __IRQn */
<> 144:ef7eb2e8f9f7 18573 #define HASH_RNG_IRQn RNG_IRQn
<> 144:ef7eb2e8f9f7 18574
<> 144:ef7eb2e8f9f7 18575 /* Aliases for __IRQHandler */
<> 144:ef7eb2e8f9f7 18576 #define HASH_RNG_IRQHandler RNG_IRQHandler
<> 144:ef7eb2e8f9f7 18577
<> 144:ef7eb2e8f9f7 18578 /**
<> 144:ef7eb2e8f9f7 18579 * @}
<> 144:ef7eb2e8f9f7 18580 */
<> 144:ef7eb2e8f9f7 18581
<> 144:ef7eb2e8f9f7 18582 /**
<> 144:ef7eb2e8f9f7 18583 * @}
<> 144:ef7eb2e8f9f7 18584 */
<> 144:ef7eb2e8f9f7 18585
<> 144:ef7eb2e8f9f7 18586 /**
<> 144:ef7eb2e8f9f7 18587 * @}
<> 144:ef7eb2e8f9f7 18588 */
<> 161:2cc1468da177 18589
<> 144:ef7eb2e8f9f7 18590 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 18591 }
<> 144:ef7eb2e8f9f7 18592 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 18593
<> 144:ef7eb2e8f9f7 18594 #endif /* __STM32F767xx_H */
<> 144:ef7eb2e8f9f7 18595
<> 144:ef7eb2e8f9f7 18596
<> 144:ef7eb2e8f9f7 18597 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/