mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 182:a56a73fd2a6f

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:e84263d55307	1	/**
AnnaBridge	167:e84263d55307	2	******************************************************************************
AnnaBridge	167:e84263d55307	3	* @file stm32f4xx_ll_dma.h
AnnaBridge	167:e84263d55307	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @brief Header file of DMA LL module.
AnnaBridge	167:e84263d55307	6	******************************************************************************
AnnaBridge	167:e84263d55307	7	* @attention
AnnaBridge	167:e84263d55307	8	*
AnnaBridge	167:e84263d55307	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	167:e84263d55307	10	*
AnnaBridge	167:e84263d55307	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	167:e84263d55307	12	* are permitted provided that the following conditions are met:
AnnaBridge	167:e84263d55307	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	167:e84263d55307	14	* this list of conditions and the following disclaimer.
AnnaBridge	167:e84263d55307	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	167:e84263d55307	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	167:e84263d55307	17	* and/or other materials provided with the distribution.
AnnaBridge	167:e84263d55307	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	167:e84263d55307	19	* may be used to endorse or promote products derived from this software
AnnaBridge	167:e84263d55307	20	* without specific prior written permission.
AnnaBridge	167:e84263d55307	21	*
AnnaBridge	167:e84263d55307	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	167:e84263d55307	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	167:e84263d55307	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	167:e84263d55307	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	167:e84263d55307	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	167:e84263d55307	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	167:e84263d55307	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	167:e84263d55307	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	167:e84263d55307	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	167:e84263d55307	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	167:e84263d55307	32	*
AnnaBridge	167:e84263d55307	33	******************************************************************************
AnnaBridge	167:e84263d55307	34	*/
AnnaBridge	167:e84263d55307	35
AnnaBridge	167:e84263d55307	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	167:e84263d55307	37	#ifndef __STM32F4xx_LL_DMA_H
AnnaBridge	167:e84263d55307	38	#define __STM32F4xx_LL_DMA_H
AnnaBridge	167:e84263d55307	39
AnnaBridge	167:e84263d55307	40	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	41	extern "C" {
AnnaBridge	167:e84263d55307	42	#endif
AnnaBridge	167:e84263d55307	43
AnnaBridge	167:e84263d55307	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	45	#include "stm32f4xx.h"
AnnaBridge	167:e84263d55307	46
AnnaBridge	167:e84263d55307	47	/** @addtogroup STM32F4xx_LL_Driver
AnnaBridge	167:e84263d55307	48	* @{
AnnaBridge	167:e84263d55307	49	*/
AnnaBridge	167:e84263d55307	50
AnnaBridge	167:e84263d55307	51	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	167:e84263d55307	52
AnnaBridge	167:e84263d55307	53	/** @defgroup DMA_LL DMA
AnnaBridge	167:e84263d55307	54	* @{
AnnaBridge	167:e84263d55307	55	*/
AnnaBridge	167:e84263d55307	56
AnnaBridge	167:e84263d55307	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	59	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	167:e84263d55307	60	* @{
AnnaBridge	167:e84263d55307	61	*/
AnnaBridge	167:e84263d55307	62	/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
AnnaBridge	167:e84263d55307	63	static const uint8_t STREAM_OFFSET_TAB[] =
AnnaBridge	167:e84263d55307	64	{
AnnaBridge	167:e84263d55307	65	(uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	66	(uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	67	(uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	68	(uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	69	(uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	70	(uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	71	(uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
AnnaBridge	167:e84263d55307	72	(uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
AnnaBridge	167:e84263d55307	73	};
AnnaBridge	167:e84263d55307	74
AnnaBridge	167:e84263d55307	75	/**
AnnaBridge	167:e84263d55307	76	* @}
AnnaBridge	167:e84263d55307	77	*/
AnnaBridge	167:e84263d55307	78
AnnaBridge	167:e84263d55307	79	/* Private constants ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	80	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
AnnaBridge	167:e84263d55307	81	* @{
AnnaBridge	167:e84263d55307	82	*/
AnnaBridge	167:e84263d55307	83	/**
AnnaBridge	167:e84263d55307	84	* @}
AnnaBridge	167:e84263d55307	85	*/
AnnaBridge	167:e84263d55307	86
AnnaBridge	167:e84263d55307	87
AnnaBridge	167:e84263d55307	88	/* Private macros ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	89	/* Exported types ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	90	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	91	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	167:e84263d55307	92	* @{
AnnaBridge	167:e84263d55307	93	*/
AnnaBridge	167:e84263d55307	94	typedef struct
AnnaBridge	167:e84263d55307	95	{
AnnaBridge	167:e84263d55307	96	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	167:e84263d55307	97	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	167:e84263d55307	98
AnnaBridge	167:e84263d55307	99	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	167:e84263d55307	100
AnnaBridge	167:e84263d55307	101	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	167:e84263d55307	102	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	167:e84263d55307	103
AnnaBridge	167:e84263d55307	104	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	167:e84263d55307	105
AnnaBridge	167:e84263d55307	106	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	167:e84263d55307	107	from memory to memory or from peripheral to memory.
AnnaBridge	167:e84263d55307	108	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	167:e84263d55307	109
AnnaBridge	167:e84263d55307	110	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	167:e84263d55307	111
AnnaBridge	167:e84263d55307	112	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	167:e84263d55307	113	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	167:e84263d55307	114	@note The circular buffer mode cannot be used if the memory to memory
AnnaBridge	167:e84263d55307	115	data transfer direction is configured on the selected Stream
AnnaBridge	167:e84263d55307	116
AnnaBridge	167:e84263d55307	117	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	167:e84263d55307	118
AnnaBridge	167:e84263d55307	119	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	167:e84263d55307	120	is incremented or not.
AnnaBridge	167:e84263d55307	121	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	167:e84263d55307	122
AnnaBridge	167:e84263d55307	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	167:e84263d55307	124
AnnaBridge	167:e84263d55307	125	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	167:e84263d55307	126	is incremented or not.
AnnaBridge	167:e84263d55307	127	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	167:e84263d55307	128
AnnaBridge	167:e84263d55307	129	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	167:e84263d55307	130
AnnaBridge	167:e84263d55307	131	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	167:e84263d55307	132	in case of memory to memory transfer direction.
AnnaBridge	167:e84263d55307	133	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	167:e84263d55307	134
AnnaBridge	167:e84263d55307	135	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	167:e84263d55307	136
AnnaBridge	167:e84263d55307	137	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	167:e84263d55307	138	in case of memory to memory transfer direction.
AnnaBridge	167:e84263d55307	139	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	167:e84263d55307	140
AnnaBridge	167:e84263d55307	141	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	167:e84263d55307	142
AnnaBridge	167:e84263d55307	143	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	167:e84263d55307	144	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	167:e84263d55307	145	or MemorySize parameters depending in the transfer direction.
AnnaBridge	167:e84263d55307	146	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	167:e84263d55307	147
AnnaBridge	167:e84263d55307	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	167:e84263d55307	149
AnnaBridge	167:e84263d55307	150	uint32_t Channel; /*!< Specifies the peripheral channel.
AnnaBridge	167:e84263d55307	151	This parameter can be a value of @ref DMA_LL_EC_CHANNEL
AnnaBridge	167:e84263d55307	152
AnnaBridge	167:e84263d55307	153	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
AnnaBridge	167:e84263d55307	154
AnnaBridge	167:e84263d55307	155	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	167:e84263d55307	156	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	167:e84263d55307	157
AnnaBridge	167:e84263d55307	158	This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
AnnaBridge	167:e84263d55307	159
AnnaBridge	167:e84263d55307	160	uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
AnnaBridge	167:e84263d55307	161	This parameter can be a value of @ref DMA_LL_FIFOMODE
AnnaBridge	167:e84263d55307	162	@note The Direct mode (FIFO mode disabled) cannot be used if the
AnnaBridge	167:e84263d55307	163	memory-to-memory data transfer is configured on the selected stream
AnnaBridge	167:e84263d55307	164
AnnaBridge	167:e84263d55307	165	This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
AnnaBridge	167:e84263d55307	166
AnnaBridge	167:e84263d55307	167	uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
AnnaBridge	167:e84263d55307	168	This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
AnnaBridge	167:e84263d55307	169
AnnaBridge	167:e84263d55307	170	This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
AnnaBridge	167:e84263d55307	171
AnnaBridge	167:e84263d55307	172	uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
AnnaBridge	167:e84263d55307	173	It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge	167:e84263d55307	174	transaction.
AnnaBridge	167:e84263d55307	175	This parameter can be a value of @ref DMA_LL_EC_MBURST
AnnaBridge	167:e84263d55307	176	@note The burst mode is possible only if the address Increment mode is enabled.
AnnaBridge	167:e84263d55307	177
AnnaBridge	167:e84263d55307	178	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
AnnaBridge	167:e84263d55307	179
AnnaBridge	167:e84263d55307	180	uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
AnnaBridge	167:e84263d55307	181	It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge	167:e84263d55307	182	transaction.
AnnaBridge	167:e84263d55307	183	This parameter can be a value of @ref DMA_LL_EC_PBURST
AnnaBridge	167:e84263d55307	184	@note The burst mode is possible only if the address Increment mode is enabled.
AnnaBridge	167:e84263d55307	185
AnnaBridge	167:e84263d55307	186	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
AnnaBridge	167:e84263d55307	187
AnnaBridge	167:e84263d55307	188	} LL_DMA_InitTypeDef;
AnnaBridge	167:e84263d55307	189	/**
AnnaBridge	167:e84263d55307	190	* @}
AnnaBridge	167:e84263d55307	191	*/
AnnaBridge	167:e84263d55307	192	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	167:e84263d55307	193	/* Exported constants --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	194	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	167:e84263d55307	195	* @{
AnnaBridge	167:e84263d55307	196	*/
AnnaBridge	167:e84263d55307	197
AnnaBridge	167:e84263d55307	198	/** @defgroup DMA_LL_EC_STREAM STREAM
AnnaBridge	167:e84263d55307	199	* @{
AnnaBridge	167:e84263d55307	200	*/
AnnaBridge	167:e84263d55307	201	#define LL_DMA_STREAM_0 0x00000000U
AnnaBridge	167:e84263d55307	202	#define LL_DMA_STREAM_1 0x00000001U
AnnaBridge	167:e84263d55307	203	#define LL_DMA_STREAM_2 0x00000002U
AnnaBridge	167:e84263d55307	204	#define LL_DMA_STREAM_3 0x00000003U
AnnaBridge	167:e84263d55307	205	#define LL_DMA_STREAM_4 0x00000004U
AnnaBridge	167:e84263d55307	206	#define LL_DMA_STREAM_5 0x00000005U
AnnaBridge	167:e84263d55307	207	#define LL_DMA_STREAM_6 0x00000006U
AnnaBridge	167:e84263d55307	208	#define LL_DMA_STREAM_7 0x00000007U
AnnaBridge	167:e84263d55307	209	#define LL_DMA_STREAM_ALL 0xFFFF0000U
AnnaBridge	167:e84263d55307	210	/**
AnnaBridge	167:e84263d55307	211	* @}
AnnaBridge	167:e84263d55307	212	*/
AnnaBridge	167:e84263d55307	213
AnnaBridge	167:e84263d55307	214	/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
AnnaBridge	167:e84263d55307	215	* @{
AnnaBridge	167:e84263d55307	216	*/
AnnaBridge	167:e84263d55307	217	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
AnnaBridge	167:e84263d55307	218	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /!< Memory to peripheral direction /
AnnaBridge	167:e84263d55307	219	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /!< Memory to memory direction /
AnnaBridge	167:e84263d55307	220	/**
AnnaBridge	167:e84263d55307	221	* @}
AnnaBridge	167:e84263d55307	222	*/
AnnaBridge	167:e84263d55307	223
AnnaBridge	167:e84263d55307	224	/** @defgroup DMA_LL_EC_MODE MODE
AnnaBridge	167:e84263d55307	225	* @{
AnnaBridge	167:e84263d55307	226	*/
AnnaBridge	167:e84263d55307	227	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
AnnaBridge	167:e84263d55307	228	#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /!< Circular Mode /
AnnaBridge	167:e84263d55307	229	#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /!< Peripheral flow control mode /
AnnaBridge	167:e84263d55307	230	/**
AnnaBridge	167:e84263d55307	231	* @}
AnnaBridge	167:e84263d55307	232	*/
AnnaBridge	167:e84263d55307	233
AnnaBridge	167:e84263d55307	234	/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
AnnaBridge	167:e84263d55307	235	* @{
AnnaBridge	167:e84263d55307	236	*/
AnnaBridge	167:e84263d55307	237	#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /!< Disable double buffering mode /
AnnaBridge	167:e84263d55307	238	#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /!< Enable double buffering mode /
AnnaBridge	167:e84263d55307	239	/**
AnnaBridge	167:e84263d55307	240	* @}
AnnaBridge	167:e84263d55307	241	*/
AnnaBridge	167:e84263d55307	242
AnnaBridge	167:e84263d55307	243	/** @defgroup DMA_LL_EC_PERIPH PERIPH
AnnaBridge	167:e84263d55307	244	* @{
AnnaBridge	167:e84263d55307	245	*/
AnnaBridge	167:e84263d55307	246	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
AnnaBridge	167:e84263d55307	247	#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	167:e84263d55307	248	/**
AnnaBridge	167:e84263d55307	249	* @}
AnnaBridge	167:e84263d55307	250	*/
AnnaBridge	167:e84263d55307	251
AnnaBridge	167:e84263d55307	252	/** @defgroup DMA_LL_EC_MEMORY MEMORY
AnnaBridge	167:e84263d55307	253	* @{
AnnaBridge	167:e84263d55307	254	*/
AnnaBridge	167:e84263d55307	255	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
AnnaBridge	167:e84263d55307	256	#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /!< Memory increment mode Enable /
AnnaBridge	167:e84263d55307	257	/**
AnnaBridge	167:e84263d55307	258	* @}
AnnaBridge	167:e84263d55307	259	*/
AnnaBridge	167:e84263d55307	260
AnnaBridge	167:e84263d55307	261	/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
AnnaBridge	167:e84263d55307	262	* @{
AnnaBridge	167:e84263d55307	263	*/
AnnaBridge	167:e84263d55307	264	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
AnnaBridge	167:e84263d55307	265	#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	167:e84263d55307	266	#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	167:e84263d55307	267	/**
AnnaBridge	167:e84263d55307	268	* @}
AnnaBridge	167:e84263d55307	269	*/
AnnaBridge	167:e84263d55307	270
AnnaBridge	167:e84263d55307	271	/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
AnnaBridge	167:e84263d55307	272	* @{
AnnaBridge	167:e84263d55307	273	*/
AnnaBridge	167:e84263d55307	274	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
AnnaBridge	167:e84263d55307	275	#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	167:e84263d55307	276	#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	167:e84263d55307	277	/**
AnnaBridge	167:e84263d55307	278	* @}
AnnaBridge	167:e84263d55307	279	*/
AnnaBridge	167:e84263d55307	280
AnnaBridge	167:e84263d55307	281	/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
AnnaBridge	167:e84263d55307	282	* @{
AnnaBridge	167:e84263d55307	283	*/
AnnaBridge	167:e84263d55307	284	#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /!< Peripheral increment offset size is linked to the PSIZE /
AnnaBridge	167:e84263d55307	285	#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /!< Peripheral increment offset size is fixed to 4 (32-bit alignment) /
AnnaBridge	167:e84263d55307	286	/**
AnnaBridge	167:e84263d55307	287	* @}
AnnaBridge	167:e84263d55307	288	*/
AnnaBridge	167:e84263d55307	289
AnnaBridge	167:e84263d55307	290	/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
AnnaBridge	167:e84263d55307	291	* @{
AnnaBridge	167:e84263d55307	292	*/
AnnaBridge	167:e84263d55307	293	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
AnnaBridge	167:e84263d55307	294	#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /!< Priority level : Medium /
AnnaBridge	167:e84263d55307	295	#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /!< Priority level : High /
AnnaBridge	167:e84263d55307	296	#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /!< Priority level : Very_High /
AnnaBridge	167:e84263d55307	297	/**
AnnaBridge	167:e84263d55307	298	* @}
AnnaBridge	167:e84263d55307	299	*/
AnnaBridge	167:e84263d55307	300
AnnaBridge	167:e84263d55307	301	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge	167:e84263d55307	302	* @{
AnnaBridge	167:e84263d55307	303	*/
AnnaBridge	167:e84263d55307	304	#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
AnnaBridge	167:e84263d55307	305	#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
AnnaBridge	167:e84263d55307	306	#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
AnnaBridge	167:e84263d55307	307	#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 \| DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
AnnaBridge	167:e84263d55307	308	#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
AnnaBridge	167:e84263d55307	309	#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
AnnaBridge	167:e84263d55307	310	#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
AnnaBridge	167:e84263d55307	311	#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_1 \| DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
AnnaBridge	167:e84263d55307	312	/**
AnnaBridge	167:e84263d55307	313	* @}
AnnaBridge	167:e84263d55307	314	*/
AnnaBridge	167:e84263d55307	315
AnnaBridge	167:e84263d55307	316	/** @defgroup DMA_LL_EC_MBURST MBURST
AnnaBridge	167:e84263d55307	317	* @{
AnnaBridge	167:e84263d55307	318	*/
AnnaBridge	167:e84263d55307	319	#define LL_DMA_MBURST_SINGLE 0x00000000U /!< Memory burst single transfer configuration /
AnnaBridge	167:e84263d55307	320	#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /!< Memory burst of 4 beats transfer configuration /
AnnaBridge	167:e84263d55307	321	#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /!< Memory burst of 8 beats transfer configuration /
AnnaBridge	167:e84263d55307	322	#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 \| DMA_SxCR_MBURST_1) /!< Memory burst of 16 beats transfer configuration /
AnnaBridge	167:e84263d55307	323	/**
AnnaBridge	167:e84263d55307	324	* @}
AnnaBridge	167:e84263d55307	325	*/
AnnaBridge	167:e84263d55307	326
AnnaBridge	167:e84263d55307	327	/** @defgroup DMA_LL_EC_PBURST PBURST
AnnaBridge	167:e84263d55307	328	* @{
AnnaBridge	167:e84263d55307	329	*/
AnnaBridge	167:e84263d55307	330	#define LL_DMA_PBURST_SINGLE 0x00000000U /!< Peripheral burst single transfer configuration /
AnnaBridge	167:e84263d55307	331	#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /!< Peripheral burst of 4 beats transfer configuration /
AnnaBridge	167:e84263d55307	332	#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /!< Peripheral burst of 8 beats transfer configuration /
AnnaBridge	167:e84263d55307	333	#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 \| DMA_SxCR_PBURST_1) /!< Peripheral burst of 16 beats transfer configuration /
AnnaBridge	167:e84263d55307	334	/**
AnnaBridge	167:e84263d55307	335	* @}
AnnaBridge	167:e84263d55307	336	*/
AnnaBridge	167:e84263d55307	337
AnnaBridge	167:e84263d55307	338	/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
AnnaBridge	167:e84263d55307	339	* @{
AnnaBridge	167:e84263d55307	340	*/
AnnaBridge	167:e84263d55307	341	#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /!< FIFO mode disable (direct mode is enabled) /
AnnaBridge	167:e84263d55307	342	#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /!< FIFO mode enable /
AnnaBridge	167:e84263d55307	343	/**
AnnaBridge	167:e84263d55307	344	* @}
AnnaBridge	167:e84263d55307	345	*/
AnnaBridge	167:e84263d55307	346
AnnaBridge	167:e84263d55307	347	/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
AnnaBridge	167:e84263d55307	348	* @{
AnnaBridge	167:e84263d55307	349	*/
AnnaBridge	167:e84263d55307	350	#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /!< 0 < fifo_level < 1/4 /
AnnaBridge	167:e84263d55307	351	#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /!< 1/4 < fifo_level < 1/2 /
AnnaBridge	167:e84263d55307	352	#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /!< 1/2 < fifo_level < 3/4 /
AnnaBridge	167:e84263d55307	353	#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 \| DMA_SxFCR_FS_0) /!< 3/4 < fifo_level < full /
AnnaBridge	167:e84263d55307	354	#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /!< FIFO is empty /
AnnaBridge	167:e84263d55307	355	#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 \| DMA_SxFCR_FS_0) /!< FIFO is full /
AnnaBridge	167:e84263d55307	356	/**
AnnaBridge	167:e84263d55307	357	* @}
AnnaBridge	167:e84263d55307	358	*/
AnnaBridge	167:e84263d55307	359
AnnaBridge	167:e84263d55307	360	/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
AnnaBridge	167:e84263d55307	361	* @{
AnnaBridge	167:e84263d55307	362	*/
AnnaBridge	167:e84263d55307	363	#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /!< FIFO threshold 1 quart full configuration /
AnnaBridge	167:e84263d55307	364	#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /!< FIFO threshold half full configuration /
AnnaBridge	167:e84263d55307	365	#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /!< FIFO threshold 3 quarts full configuration /
AnnaBridge	167:e84263d55307	366	#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /!< FIFO threshold full configuration /
AnnaBridge	167:e84263d55307	367	/**
AnnaBridge	167:e84263d55307	368	* @}
AnnaBridge	167:e84263d55307	369	*/
AnnaBridge	167:e84263d55307	370
AnnaBridge	167:e84263d55307	371	/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
AnnaBridge	167:e84263d55307	372	* @{
AnnaBridge	167:e84263d55307	373	*/
AnnaBridge	167:e84263d55307	374	#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /!< Set CurrentTarget Memory to Memory 0 /
AnnaBridge	167:e84263d55307	375	#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /!< Set CurrentTarget Memory to Memory 1 /
AnnaBridge	167:e84263d55307	376	/**
AnnaBridge	167:e84263d55307	377	* @}
AnnaBridge	167:e84263d55307	378	*/
AnnaBridge	167:e84263d55307	379
AnnaBridge	167:e84263d55307	380	/**
AnnaBridge	167:e84263d55307	381	* @}
AnnaBridge	167:e84263d55307	382	*/
AnnaBridge	167:e84263d55307	383
AnnaBridge	167:e84263d55307	384	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	385	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	167:e84263d55307	386	* @{
AnnaBridge	167:e84263d55307	387	*/
AnnaBridge	167:e84263d55307	388
AnnaBridge	167:e84263d55307	389	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	167:e84263d55307	390	* @{
AnnaBridge	167:e84263d55307	391	*/
AnnaBridge	167:e84263d55307	392	/**
AnnaBridge	167:e84263d55307	393	* @brief Write a value in DMA register
AnnaBridge	167:e84263d55307	394	* @param __INSTANCE__ DMA Instance
AnnaBridge	167:e84263d55307	395	* @param __REG__ Register to be written
AnnaBridge	167:e84263d55307	396	* @param __VALUE__ Value to be written in the register
AnnaBridge	167:e84263d55307	397	* @retval None
AnnaBridge	167:e84263d55307	398	*/
AnnaBridge	167:e84263d55307	399	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	167:e84263d55307	400
AnnaBridge	167:e84263d55307	401	/**
AnnaBridge	167:e84263d55307	402	* @brief Read a value in DMA register
AnnaBridge	167:e84263d55307	403	* @param __INSTANCE__ DMA Instance
AnnaBridge	167:e84263d55307	404	* @param __REG__ Register to be read
AnnaBridge	167:e84263d55307	405	* @retval Register value
AnnaBridge	167:e84263d55307	406	*/
AnnaBridge	167:e84263d55307	407	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	167:e84263d55307	408	/**
AnnaBridge	167:e84263d55307	409	* @}
AnnaBridge	167:e84263d55307	410	*/
AnnaBridge	167:e84263d55307	411
AnnaBridge	167:e84263d55307	412	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
AnnaBridge	167:e84263d55307	413	* @{
AnnaBridge	167:e84263d55307	414	*/
AnnaBridge	167:e84263d55307	415	/**
AnnaBridge	167:e84263d55307	416	* @brief Convert DMAx_Streamy into DMAx
AnnaBridge	167:e84263d55307	417	* @param __STREAM_INSTANCE__ DMAx_Streamy
AnnaBridge	167:e84263d55307	418	* @retval DMAx
AnnaBridge	167:e84263d55307	419	*/
AnnaBridge	167:e84263d55307	420	#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
AnnaBridge	167:e84263d55307	421	(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
AnnaBridge	167:e84263d55307	422
AnnaBridge	167:e84263d55307	423	/**
AnnaBridge	167:e84263d55307	424	* @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
AnnaBridge	167:e84263d55307	425	* @param __STREAM_INSTANCE__ DMAx_Streamy
AnnaBridge	167:e84263d55307	426	* @retval LL_DMA_CHANNEL_y
AnnaBridge	167:e84263d55307	427	*/
AnnaBridge	167:e84263d55307	428	#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
AnnaBridge	167:e84263d55307	429	(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
AnnaBridge	167:e84263d55307	430	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
AnnaBridge	167:e84263d55307	431	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
AnnaBridge	167:e84263d55307	432	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
AnnaBridge	167:e84263d55307	433	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
AnnaBridge	167:e84263d55307	434	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
AnnaBridge	167:e84263d55307	435	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
AnnaBridge	167:e84263d55307	436	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
AnnaBridge	167:e84263d55307	437	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
AnnaBridge	167:e84263d55307	438	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
AnnaBridge	167:e84263d55307	439	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
AnnaBridge	167:e84263d55307	440	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
AnnaBridge	167:e84263d55307	441	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
AnnaBridge	167:e84263d55307	442	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
AnnaBridge	167:e84263d55307	443	LL_DMA_STREAM_7)
AnnaBridge	167:e84263d55307	444
AnnaBridge	167:e84263d55307	445	/**
AnnaBridge	167:e84263d55307	446	* @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
AnnaBridge	167:e84263d55307	447	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	167:e84263d55307	448	* @param __STREAM__ LL_DMA_STREAM_y
AnnaBridge	167:e84263d55307	449	* @retval DMAx_Streamy
AnnaBridge	167:e84263d55307	450	*/
AnnaBridge	167:e84263d55307	451	#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
AnnaBridge	167:e84263d55307	452	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
AnnaBridge	167:e84263d55307	453	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
AnnaBridge	167:e84263d55307	454	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
AnnaBridge	167:e84263d55307	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
AnnaBridge	167:e84263d55307	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
AnnaBridge	167:e84263d55307	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
AnnaBridge	167:e84263d55307	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
AnnaBridge	167:e84263d55307	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
AnnaBridge	167:e84263d55307	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
AnnaBridge	167:e84263d55307	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
AnnaBridge	167:e84263d55307	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
AnnaBridge	167:e84263d55307	463	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
AnnaBridge	167:e84263d55307	464	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
AnnaBridge	167:e84263d55307	465	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
AnnaBridge	167:e84263d55307	466	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
AnnaBridge	167:e84263d55307	467	DMA2_Stream7)
AnnaBridge	167:e84263d55307	468
AnnaBridge	167:e84263d55307	469	/**
AnnaBridge	167:e84263d55307	470	* @}
AnnaBridge	167:e84263d55307	471	*/
AnnaBridge	167:e84263d55307	472
AnnaBridge	167:e84263d55307	473	/**
AnnaBridge	167:e84263d55307	474	* @}
AnnaBridge	167:e84263d55307	475	*/
AnnaBridge	167:e84263d55307	476
AnnaBridge	167:e84263d55307	477
AnnaBridge	167:e84263d55307	478	/* Exported functions --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	479	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	167:e84263d55307	480	* @{
AnnaBridge	167:e84263d55307	481	*/
AnnaBridge	167:e84263d55307	482
AnnaBridge	167:e84263d55307	483	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	167:e84263d55307	484	* @{
AnnaBridge	167:e84263d55307	485	*/
AnnaBridge	167:e84263d55307	486	/**
AnnaBridge	167:e84263d55307	487	* @brief Enable DMA stream.
AnnaBridge	167:e84263d55307	488	* @rmtoll CR EN LL_DMA_EnableStream
AnnaBridge	167:e84263d55307	489	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	490	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	491	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	492	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	493	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	494	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	495	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	496	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	497	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	498	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	499	* @retval None
AnnaBridge	167:e84263d55307	500	*/
AnnaBridge	167:e84263d55307	501	__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	502	{
AnnaBridge	167:e84263d55307	503	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
AnnaBridge	167:e84263d55307	504	}
AnnaBridge	167:e84263d55307	505
AnnaBridge	167:e84263d55307	506	/**
AnnaBridge	167:e84263d55307	507	* @brief Disable DMA stream.
AnnaBridge	167:e84263d55307	508	* @rmtoll CR EN LL_DMA_DisableStream
AnnaBridge	167:e84263d55307	509	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	510	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	511	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	512	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	513	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	514	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	515	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	516	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	517	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	518	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	519	* @retval None
AnnaBridge	167:e84263d55307	520	*/
AnnaBridge	167:e84263d55307	521	__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	522	{
AnnaBridge	167:e84263d55307	523	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
AnnaBridge	167:e84263d55307	524	}
AnnaBridge	167:e84263d55307	525
AnnaBridge	167:e84263d55307	526	/**
AnnaBridge	167:e84263d55307	527	* @brief Check if DMA stream is enabled or disabled.
AnnaBridge	167:e84263d55307	528	* @rmtoll CR EN LL_DMA_IsEnabledStream
AnnaBridge	167:e84263d55307	529	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	530	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	531	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	532	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	533	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	534	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	535	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	536	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	537	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	538	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	539	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	540	*/
AnnaBridge	167:e84263d55307	541	__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	542	{
AnnaBridge	167:e84263d55307	543	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
AnnaBridge	167:e84263d55307	544	}
AnnaBridge	167:e84263d55307	545
AnnaBridge	167:e84263d55307	546	/**
AnnaBridge	167:e84263d55307	547	* @brief Configure all parameters linked to DMA transfer.
AnnaBridge	167:e84263d55307	548	* @rmtoll CR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	549	* CR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	550	* CR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	551	* CR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	552	* CR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	553	* CR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	554	* CR PL LL_DMA_ConfigTransfer\n
AnnaBridge	167:e84263d55307	555	* CR PFCTRL LL_DMA_ConfigTransfer
AnnaBridge	167:e84263d55307	556	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	557	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	558	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	559	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	560	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	561	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	562	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	563	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	564	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	565	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	566	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	167:e84263d55307	567	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	167:e84263d55307	568	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
AnnaBridge	167:e84263d55307	569	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	167:e84263d55307	570	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	167:e84263d55307	571	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	167:e84263d55307	572	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	167:e84263d55307	573	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	167:e84263d55307	574	*@retval None
AnnaBridge	167:e84263d55307	575	*/
AnnaBridge	167:e84263d55307	576	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
AnnaBridge	167:e84263d55307	577	{
AnnaBridge	167:e84263d55307	578	MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
AnnaBridge	167:e84263d55307	579	DMA_SxCR_DIR \| DMA_SxCR_CIRC \| DMA_SxCR_PINC \| DMA_SxCR_MINC \| DMA_SxCR_PSIZE \| DMA_SxCR_MSIZE \| DMA_SxCR_PL \| DMA_SxCR_PFCTRL,
AnnaBridge	167:e84263d55307	580	Configuration);
AnnaBridge	167:e84263d55307	581	}
AnnaBridge	167:e84263d55307	582
AnnaBridge	167:e84263d55307	583	/**
AnnaBridge	167:e84263d55307	584	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	167:e84263d55307	585	* @rmtoll CR DIR LL_DMA_SetDataTransferDirection
AnnaBridge	167:e84263d55307	586	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	587	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	588	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	589	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	590	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	591	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	592	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	593	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	594	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	595	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	596	* @param Direction This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	597	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	167:e84263d55307	598	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	167:e84263d55307	599	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	167:e84263d55307	600	* @retval None
AnnaBridge	167:e84263d55307	601	*/
AnnaBridge	167:e84263d55307	602	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
AnnaBridge	167:e84263d55307	603	{
AnnaBridge	167:e84263d55307	604	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
AnnaBridge	167:e84263d55307	605	}
AnnaBridge	167:e84263d55307	606
AnnaBridge	167:e84263d55307	607	/**
AnnaBridge	167:e84263d55307	608	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	167:e84263d55307	609	* @rmtoll CR DIR LL_DMA_GetDataTransferDirection
AnnaBridge	167:e84263d55307	610	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	611	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	612	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	613	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	614	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	615	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	616	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	617	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	618	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	619	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	620	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	621	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	167:e84263d55307	622	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	167:e84263d55307	623	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	167:e84263d55307	624	*/
AnnaBridge	167:e84263d55307	625	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	626	{
AnnaBridge	167:e84263d55307	627	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
AnnaBridge	167:e84263d55307	628	}
AnnaBridge	167:e84263d55307	629
AnnaBridge	167:e84263d55307	630	/**
AnnaBridge	167:e84263d55307	631	* @brief Set DMA mode normal, circular or peripheral flow control.
AnnaBridge	167:e84263d55307	632	* @rmtoll CR CIRC LL_DMA_SetMode\n
AnnaBridge	167:e84263d55307	633	* CR PFCTRL LL_DMA_SetMode
AnnaBridge	167:e84263d55307	634	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	635	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	636	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	637	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	638	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	639	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	640	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	641	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	642	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	643	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	644	* @param Mode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	645	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	167:e84263d55307	646	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	167:e84263d55307	647	* @arg @ref LL_DMA_MODE_PFCTRL
AnnaBridge	167:e84263d55307	648	* @retval None
AnnaBridge	167:e84263d55307	649	*/
AnnaBridge	167:e84263d55307	650	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
AnnaBridge	167:e84263d55307	651	{
AnnaBridge	167:e84263d55307	652	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL, Mode);
AnnaBridge	167:e84263d55307	653	}
AnnaBridge	167:e84263d55307	654
AnnaBridge	167:e84263d55307	655	/**
AnnaBridge	167:e84263d55307	656	* @brief Get DMA mode normal, circular or peripheral flow control.
AnnaBridge	167:e84263d55307	657	* @rmtoll CR CIRC LL_DMA_GetMode\n
AnnaBridge	167:e84263d55307	658	* CR PFCTRL LL_DMA_GetMode
AnnaBridge	167:e84263d55307	659	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	660	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	661	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	662	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	663	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	664	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	665	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	666	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	667	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	668	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	669	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	670	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	167:e84263d55307	671	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	167:e84263d55307	672	* @arg @ref LL_DMA_MODE_PFCTRL
AnnaBridge	167:e84263d55307	673	*/
AnnaBridge	167:e84263d55307	674	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	675	{
AnnaBridge	167:e84263d55307	676	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL));
AnnaBridge	167:e84263d55307	677	}
AnnaBridge	167:e84263d55307	678
AnnaBridge	167:e84263d55307	679	/**
AnnaBridge	167:e84263d55307	680	* @brief Set Peripheral increment mode.
AnnaBridge	167:e84263d55307	681	* @rmtoll CR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	167:e84263d55307	682	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	683	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	684	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	685	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	686	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	687	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	688	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	689	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	690	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	691	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	692	* @param IncrementMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	693	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	167:e84263d55307	694	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	167:e84263d55307	695	* @retval None
AnnaBridge	167:e84263d55307	696	*/
AnnaBridge	167:e84263d55307	697	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
AnnaBridge	167:e84263d55307	698	{
AnnaBridge	167:e84263d55307	699	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
AnnaBridge	167:e84263d55307	700	}
AnnaBridge	167:e84263d55307	701
AnnaBridge	167:e84263d55307	702	/**
AnnaBridge	167:e84263d55307	703	* @brief Get Peripheral increment mode.
AnnaBridge	167:e84263d55307	704	* @rmtoll CR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	167:e84263d55307	705	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	706	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	707	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	708	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	709	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	710	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	711	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	712	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	713	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	714	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	715	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	716	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	167:e84263d55307	717	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	167:e84263d55307	718	*/
AnnaBridge	167:e84263d55307	719	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	720	{
AnnaBridge	167:e84263d55307	721	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
AnnaBridge	167:e84263d55307	722	}
AnnaBridge	167:e84263d55307	723
AnnaBridge	167:e84263d55307	724	/**
AnnaBridge	167:e84263d55307	725	* @brief Set Memory increment mode.
AnnaBridge	167:e84263d55307	726	* @rmtoll CR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	167:e84263d55307	727	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	728	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	729	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	730	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	731	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	732	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	733	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	734	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	735	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	736	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	737	* @param IncrementMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	738	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	167:e84263d55307	739	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	167:e84263d55307	740	* @retval None
AnnaBridge	167:e84263d55307	741	*/
AnnaBridge	167:e84263d55307	742	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
AnnaBridge	167:e84263d55307	743	{
AnnaBridge	167:e84263d55307	744	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
AnnaBridge	167:e84263d55307	745	}
AnnaBridge	167:e84263d55307	746
AnnaBridge	167:e84263d55307	747	/**
AnnaBridge	167:e84263d55307	748	* @brief Get Memory increment mode.
AnnaBridge	167:e84263d55307	749	* @rmtoll CR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	167:e84263d55307	750	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	751	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	752	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	753	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	754	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	755	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	756	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	757	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	758	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	759	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	760	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	761	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	167:e84263d55307	762	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	167:e84263d55307	763	*/
AnnaBridge	167:e84263d55307	764	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	765	{
AnnaBridge	167:e84263d55307	766	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
AnnaBridge	167:e84263d55307	767	}
AnnaBridge	167:e84263d55307	768
AnnaBridge	167:e84263d55307	769	/**
AnnaBridge	167:e84263d55307	770	* @brief Set Peripheral size.
AnnaBridge	167:e84263d55307	771	* @rmtoll CR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	167:e84263d55307	772	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	773	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	774	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	775	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	776	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	777	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	778	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	779	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	780	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	781	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	782	* @param Size This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	783	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	167:e84263d55307	784	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	167:e84263d55307	785	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	167:e84263d55307	786	* @retval None
AnnaBridge	167:e84263d55307	787	*/
AnnaBridge	167:e84263d55307	788	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
AnnaBridge	167:e84263d55307	789	{
AnnaBridge	167:e84263d55307	790	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
AnnaBridge	167:e84263d55307	791	}
AnnaBridge	167:e84263d55307	792
AnnaBridge	167:e84263d55307	793	/**
AnnaBridge	167:e84263d55307	794	* @brief Get Peripheral size.
AnnaBridge	167:e84263d55307	795	* @rmtoll CR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	167:e84263d55307	796	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	797	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	798	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	799	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	800	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	801	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	802	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	803	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	804	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	805	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	806	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	807	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	167:e84263d55307	808	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	167:e84263d55307	809	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	167:e84263d55307	810	*/
AnnaBridge	167:e84263d55307	811	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	812	{
AnnaBridge	167:e84263d55307	813	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
AnnaBridge	167:e84263d55307	814	}
AnnaBridge	167:e84263d55307	815
AnnaBridge	167:e84263d55307	816	/**
AnnaBridge	167:e84263d55307	817	* @brief Set Memory size.
AnnaBridge	167:e84263d55307	818	* @rmtoll CR MSIZE LL_DMA_SetMemorySize
AnnaBridge	167:e84263d55307	819	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	820	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	821	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	822	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	823	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	824	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	825	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	826	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	827	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	828	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	829	* @param Size This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	830	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	167:e84263d55307	831	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	167:e84263d55307	832	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	167:e84263d55307	833	* @retval None
AnnaBridge	167:e84263d55307	834	*/
AnnaBridge	167:e84263d55307	835	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
AnnaBridge	167:e84263d55307	836	{
AnnaBridge	167:e84263d55307	837	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
AnnaBridge	167:e84263d55307	838	}
AnnaBridge	167:e84263d55307	839
AnnaBridge	167:e84263d55307	840	/**
AnnaBridge	167:e84263d55307	841	* @brief Get Memory size.
AnnaBridge	167:e84263d55307	842	* @rmtoll CR MSIZE LL_DMA_GetMemorySize
AnnaBridge	167:e84263d55307	843	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	844	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	845	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	846	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	847	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	848	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	849	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	850	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	851	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	852	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	853	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	854	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	167:e84263d55307	855	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	167:e84263d55307	856	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	167:e84263d55307	857	*/
AnnaBridge	167:e84263d55307	858	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	859	{
AnnaBridge	167:e84263d55307	860	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
AnnaBridge	167:e84263d55307	861	}
AnnaBridge	167:e84263d55307	862
AnnaBridge	167:e84263d55307	863	/**
AnnaBridge	167:e84263d55307	864	* @brief Set Peripheral increment offset size.
AnnaBridge	167:e84263d55307	865	* @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
AnnaBridge	167:e84263d55307	866	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	867	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	868	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	869	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	870	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	871	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	872	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	873	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	874	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	875	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	876	* @param OffsetSize This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	877	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
AnnaBridge	167:e84263d55307	878	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
AnnaBridge	167:e84263d55307	879	* @retval None
AnnaBridge	167:e84263d55307	880	*/
AnnaBridge	167:e84263d55307	881	__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
AnnaBridge	167:e84263d55307	882	{
AnnaBridge	167:e84263d55307	883	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
AnnaBridge	167:e84263d55307	884	}
AnnaBridge	167:e84263d55307	885
AnnaBridge	167:e84263d55307	886	/**
AnnaBridge	167:e84263d55307	887	* @brief Get Peripheral increment offset size.
AnnaBridge	167:e84263d55307	888	* @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
AnnaBridge	167:e84263d55307	889	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	890	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	891	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	892	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	893	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	894	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	895	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	896	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	897	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	898	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	899	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	900	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
AnnaBridge	167:e84263d55307	901	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
AnnaBridge	167:e84263d55307	902	*/
AnnaBridge	167:e84263d55307	903	__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	904	{
AnnaBridge	167:e84263d55307	905	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
AnnaBridge	167:e84263d55307	906	}
AnnaBridge	167:e84263d55307	907
AnnaBridge	167:e84263d55307	908	/**
AnnaBridge	167:e84263d55307	909	* @brief Set Stream priority level.
AnnaBridge	167:e84263d55307	910	* @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
AnnaBridge	167:e84263d55307	911	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	912	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	913	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	914	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	915	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	916	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	917	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	918	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	919	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	920	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	921	* @param Priority This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	922	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	167:e84263d55307	923	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	167:e84263d55307	924	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	167:e84263d55307	925	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	167:e84263d55307	926	* @retval None
AnnaBridge	167:e84263d55307	927	*/
AnnaBridge	167:e84263d55307	928	__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
AnnaBridge	167:e84263d55307	929	{
AnnaBridge	167:e84263d55307	930	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
AnnaBridge	167:e84263d55307	931	}
AnnaBridge	167:e84263d55307	932
AnnaBridge	167:e84263d55307	933	/**
AnnaBridge	167:e84263d55307	934	* @brief Get Stream priority level.
AnnaBridge	167:e84263d55307	935	* @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
AnnaBridge	167:e84263d55307	936	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	937	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	938	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	939	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	940	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	941	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	942	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	943	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	944	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	945	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	946	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	947	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	167:e84263d55307	948	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	167:e84263d55307	949	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	167:e84263d55307	950	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	167:e84263d55307	951	*/
AnnaBridge	167:e84263d55307	952	__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	953	{
AnnaBridge	167:e84263d55307	954	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
AnnaBridge	167:e84263d55307	955	}
AnnaBridge	167:e84263d55307	956
AnnaBridge	167:e84263d55307	957	/**
AnnaBridge	167:e84263d55307	958	* @brief Set Number of data to transfer.
AnnaBridge	167:e84263d55307	959	* @rmtoll NDTR NDT LL_DMA_SetDataLength
AnnaBridge	167:e84263d55307	960	* @note This action has no effect if
AnnaBridge	167:e84263d55307	961	* stream is enabled.
AnnaBridge	167:e84263d55307	962	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	963	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	964	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	965	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	966	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	967	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	968	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	969	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	970	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	971	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	972	* @param NbData Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	973	* @retval None
AnnaBridge	167:e84263d55307	974	*/
AnnaBridge	167:e84263d55307	975	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
AnnaBridge	167:e84263d55307	976	{
AnnaBridge	167:e84263d55307	977	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
AnnaBridge	167:e84263d55307	978	}
AnnaBridge	167:e84263d55307	979
AnnaBridge	167:e84263d55307	980	/**
AnnaBridge	167:e84263d55307	981	* @brief Get Number of data to transfer.
AnnaBridge	167:e84263d55307	982	* @rmtoll NDTR NDT LL_DMA_GetDataLength
AnnaBridge	167:e84263d55307	983	* @note Once the stream is enabled, the return value indicate the
AnnaBridge	167:e84263d55307	984	* remaining bytes to be transmitted.
AnnaBridge	167:e84263d55307	985	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	986	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	987	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	988	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	989	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	990	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	991	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	992	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	993	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	994	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	995	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	996	*/
AnnaBridge	167:e84263d55307	997	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	998	{
AnnaBridge	167:e84263d55307	999	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
AnnaBridge	167:e84263d55307	1000	}
AnnaBridge	167:e84263d55307	1001
AnnaBridge	167:e84263d55307	1002	/**
AnnaBridge	167:e84263d55307	1003	* @brief Select Channel number associated to the Stream.
AnnaBridge	167:e84263d55307	1004	* @rmtoll CR CHSEL LL_DMA_SetChannelSelection
AnnaBridge	167:e84263d55307	1005	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1006	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1007	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1008	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1009	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1010	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1011	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1012	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1013	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1014	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1015	* @param Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1016	* @arg @ref LL_DMA_CHANNEL_0
AnnaBridge	167:e84263d55307	1017	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	167:e84263d55307	1018	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	167:e84263d55307	1019	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	167:e84263d55307	1020	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	167:e84263d55307	1021	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	167:e84263d55307	1022	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	167:e84263d55307	1023	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	167:e84263d55307	1024	* @retval None
AnnaBridge	167:e84263d55307	1025	*/
AnnaBridge	167:e84263d55307	1026	__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
AnnaBridge	167:e84263d55307	1027	{
AnnaBridge	167:e84263d55307	1028	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
AnnaBridge	167:e84263d55307	1029	}
AnnaBridge	167:e84263d55307	1030
AnnaBridge	167:e84263d55307	1031	/**
AnnaBridge	167:e84263d55307	1032	* @brief Get the Channel number associated to the Stream.
AnnaBridge	167:e84263d55307	1033	* @rmtoll CR CHSEL LL_DMA_GetChannelSelection
AnnaBridge	167:e84263d55307	1034	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1035	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1036	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1037	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1038	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1039	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1040	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1041	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1042	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1043	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1044	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1045	* @arg @ref LL_DMA_CHANNEL_0
AnnaBridge	167:e84263d55307	1046	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	167:e84263d55307	1047	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	167:e84263d55307	1048	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	167:e84263d55307	1049	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	167:e84263d55307	1050	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	167:e84263d55307	1051	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	167:e84263d55307	1052	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	167:e84263d55307	1053	*/
AnnaBridge	167:e84263d55307	1054	__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1055	{
AnnaBridge	167:e84263d55307	1056	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
AnnaBridge	167:e84263d55307	1057	}
AnnaBridge	167:e84263d55307	1058
AnnaBridge	167:e84263d55307	1059	/**
AnnaBridge	167:e84263d55307	1060	* @brief Set Memory burst transfer configuration.
AnnaBridge	167:e84263d55307	1061	* @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
AnnaBridge	167:e84263d55307	1062	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1063	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1064	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1065	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1066	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1067	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1068	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1069	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1070	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1071	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1072	* @param Mburst This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1073	* @arg @ref LL_DMA_MBURST_SINGLE
AnnaBridge	167:e84263d55307	1074	* @arg @ref LL_DMA_MBURST_INC4
AnnaBridge	167:e84263d55307	1075	* @arg @ref LL_DMA_MBURST_INC8
AnnaBridge	167:e84263d55307	1076	* @arg @ref LL_DMA_MBURST_INC16
AnnaBridge	167:e84263d55307	1077	* @retval None
AnnaBridge	167:e84263d55307	1078	*/
AnnaBridge	167:e84263d55307	1079	__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
AnnaBridge	167:e84263d55307	1080	{
AnnaBridge	167:e84263d55307	1081	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
AnnaBridge	167:e84263d55307	1082	}
AnnaBridge	167:e84263d55307	1083
AnnaBridge	167:e84263d55307	1084	/**
AnnaBridge	167:e84263d55307	1085	* @brief Get Memory burst transfer configuration.
AnnaBridge	167:e84263d55307	1086	* @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
AnnaBridge	167:e84263d55307	1087	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1088	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1089	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1090	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1091	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1092	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1093	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1094	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1095	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1096	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1097	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1098	* @arg @ref LL_DMA_MBURST_SINGLE
AnnaBridge	167:e84263d55307	1099	* @arg @ref LL_DMA_MBURST_INC4
AnnaBridge	167:e84263d55307	1100	* @arg @ref LL_DMA_MBURST_INC8
AnnaBridge	167:e84263d55307	1101	* @arg @ref LL_DMA_MBURST_INC16
AnnaBridge	167:e84263d55307	1102	*/
AnnaBridge	167:e84263d55307	1103	__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1104	{
AnnaBridge	167:e84263d55307	1105	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
AnnaBridge	167:e84263d55307	1106	}
AnnaBridge	167:e84263d55307	1107
AnnaBridge	167:e84263d55307	1108	/**
AnnaBridge	167:e84263d55307	1109	* @brief Set Peripheral burst transfer configuration.
AnnaBridge	167:e84263d55307	1110	* @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
AnnaBridge	167:e84263d55307	1111	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1112	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1113	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1114	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1115	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1116	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1117	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1118	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1119	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1120	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1121	* @param Pburst This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1122	* @arg @ref LL_DMA_PBURST_SINGLE
AnnaBridge	167:e84263d55307	1123	* @arg @ref LL_DMA_PBURST_INC4
AnnaBridge	167:e84263d55307	1124	* @arg @ref LL_DMA_PBURST_INC8
AnnaBridge	167:e84263d55307	1125	* @arg @ref LL_DMA_PBURST_INC16
AnnaBridge	167:e84263d55307	1126	* @retval None
AnnaBridge	167:e84263d55307	1127	*/
AnnaBridge	167:e84263d55307	1128	__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
AnnaBridge	167:e84263d55307	1129	{
AnnaBridge	167:e84263d55307	1130	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
AnnaBridge	167:e84263d55307	1131	}
AnnaBridge	167:e84263d55307	1132
AnnaBridge	167:e84263d55307	1133	/**
AnnaBridge	167:e84263d55307	1134	* @brief Get Peripheral burst transfer configuration.
AnnaBridge	167:e84263d55307	1135	* @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
AnnaBridge	167:e84263d55307	1136	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1137	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1138	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1139	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1140	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1141	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1142	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1143	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1144	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1145	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1146	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1147	* @arg @ref LL_DMA_PBURST_SINGLE
AnnaBridge	167:e84263d55307	1148	* @arg @ref LL_DMA_PBURST_INC4
AnnaBridge	167:e84263d55307	1149	* @arg @ref LL_DMA_PBURST_INC8
AnnaBridge	167:e84263d55307	1150	* @arg @ref LL_DMA_PBURST_INC16
AnnaBridge	167:e84263d55307	1151	*/
AnnaBridge	167:e84263d55307	1152	__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1153	{
AnnaBridge	167:e84263d55307	1154	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
AnnaBridge	167:e84263d55307	1155	}
AnnaBridge	167:e84263d55307	1156
AnnaBridge	167:e84263d55307	1157	/**
AnnaBridge	167:e84263d55307	1158	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
AnnaBridge	167:e84263d55307	1159	* @rmtoll CR CT LL_DMA_SetCurrentTargetMem
AnnaBridge	167:e84263d55307	1160	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1161	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1162	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1163	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1164	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1165	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1166	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1167	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1168	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1169	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1170	* @param CurrentMemory This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1171	* @arg @ref LL_DMA_CURRENTTARGETMEM0
AnnaBridge	167:e84263d55307	1172	* @arg @ref LL_DMA_CURRENTTARGETMEM1
AnnaBridge	167:e84263d55307	1173	* @retval None
AnnaBridge	167:e84263d55307	1174	*/
AnnaBridge	167:e84263d55307	1175	__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
AnnaBridge	167:e84263d55307	1176	{
AnnaBridge	167:e84263d55307	1177	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
AnnaBridge	167:e84263d55307	1178	}
AnnaBridge	167:e84263d55307	1179
AnnaBridge	167:e84263d55307	1180	/**
AnnaBridge	167:e84263d55307	1181	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
AnnaBridge	167:e84263d55307	1182	* @rmtoll CR CT LL_DMA_GetCurrentTargetMem
AnnaBridge	167:e84263d55307	1183	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1184	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1185	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1186	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1187	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1188	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1189	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1190	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1191	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1192	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1193	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1194	* @arg @ref LL_DMA_CURRENTTARGETMEM0
AnnaBridge	167:e84263d55307	1195	* @arg @ref LL_DMA_CURRENTTARGETMEM1
AnnaBridge	167:e84263d55307	1196	*/
AnnaBridge	167:e84263d55307	1197	__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1198	{
AnnaBridge	167:e84263d55307	1199	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
AnnaBridge	167:e84263d55307	1200	}
AnnaBridge	167:e84263d55307	1201
AnnaBridge	167:e84263d55307	1202	/**
AnnaBridge	167:e84263d55307	1203	* @brief Enable the double buffer mode.
AnnaBridge	167:e84263d55307	1204	* @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
AnnaBridge	167:e84263d55307	1205	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1206	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1207	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1208	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1209	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1210	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1211	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1212	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1213	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1214	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1215	* @retval None
AnnaBridge	167:e84263d55307	1216	*/
AnnaBridge	167:e84263d55307	1217	__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1218	{
AnnaBridge	167:e84263d55307	1219	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
AnnaBridge	167:e84263d55307	1220	}
AnnaBridge	167:e84263d55307	1221
AnnaBridge	167:e84263d55307	1222	/**
AnnaBridge	167:e84263d55307	1223	* @brief Disable the double buffer mode.
AnnaBridge	167:e84263d55307	1224	* @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
AnnaBridge	167:e84263d55307	1225	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1226	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1227	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1228	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1229	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1230	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1231	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1232	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1233	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1234	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1235	* @retval None
AnnaBridge	167:e84263d55307	1236	*/
AnnaBridge	167:e84263d55307	1237	__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1238	{
AnnaBridge	167:e84263d55307	1239	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
AnnaBridge	167:e84263d55307	1240	}
AnnaBridge	167:e84263d55307	1241
AnnaBridge	167:e84263d55307	1242	/**
AnnaBridge	167:e84263d55307	1243	* @brief Get FIFO status.
AnnaBridge	167:e84263d55307	1244	* @rmtoll FCR FS LL_DMA_GetFIFOStatus
AnnaBridge	167:e84263d55307	1245	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1246	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1247	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1248	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1249	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1250	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1251	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1252	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1253	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1254	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1255	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1256	* @arg @ref LL_DMA_FIFOSTATUS_0_25
AnnaBridge	167:e84263d55307	1257	* @arg @ref LL_DMA_FIFOSTATUS_25_50
AnnaBridge	167:e84263d55307	1258	* @arg @ref LL_DMA_FIFOSTATUS_50_75
AnnaBridge	167:e84263d55307	1259	* @arg @ref LL_DMA_FIFOSTATUS_75_100
AnnaBridge	167:e84263d55307	1260	* @arg @ref LL_DMA_FIFOSTATUS_EMPTY
AnnaBridge	167:e84263d55307	1261	* @arg @ref LL_DMA_FIFOSTATUS_FULL
AnnaBridge	167:e84263d55307	1262	*/
AnnaBridge	167:e84263d55307	1263	__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1264	{
AnnaBridge	167:e84263d55307	1265	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
AnnaBridge	167:e84263d55307	1266	}
AnnaBridge	167:e84263d55307	1267
AnnaBridge	167:e84263d55307	1268	/**
AnnaBridge	167:e84263d55307	1269	* @brief Disable Fifo mode.
AnnaBridge	167:e84263d55307	1270	* @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
AnnaBridge	167:e84263d55307	1271	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1272	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1273	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1274	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1275	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1276	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1277	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1278	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1279	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1280	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1281	* @retval None
AnnaBridge	167:e84263d55307	1282	*/
AnnaBridge	167:e84263d55307	1283	__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1284	{
AnnaBridge	167:e84263d55307	1285	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
AnnaBridge	167:e84263d55307	1286	}
AnnaBridge	167:e84263d55307	1287
AnnaBridge	167:e84263d55307	1288	/**
AnnaBridge	167:e84263d55307	1289	* @brief Enable Fifo mode.
AnnaBridge	167:e84263d55307	1290	* @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
AnnaBridge	167:e84263d55307	1291	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1292	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1293	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1294	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1295	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1296	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1297	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1298	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1299	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1300	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1301	* @retval None
AnnaBridge	167:e84263d55307	1302	*/
AnnaBridge	167:e84263d55307	1303	__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1304	{
AnnaBridge	167:e84263d55307	1305	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
AnnaBridge	167:e84263d55307	1306	}
AnnaBridge	167:e84263d55307	1307
AnnaBridge	167:e84263d55307	1308	/**
AnnaBridge	167:e84263d55307	1309	* @brief Select FIFO threshold.
AnnaBridge	167:e84263d55307	1310	* @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
AnnaBridge	167:e84263d55307	1311	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1312	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1313	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1314	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1315	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1316	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1317	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1318	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1319	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1320	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1321	* @param Threshold This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1322	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	167:e84263d55307	1323	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	167:e84263d55307	1324	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	167:e84263d55307	1325	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	167:e84263d55307	1326	* @retval None
AnnaBridge	167:e84263d55307	1327	*/
AnnaBridge	167:e84263d55307	1328	__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
AnnaBridge	167:e84263d55307	1329	{
AnnaBridge	167:e84263d55307	1330	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
AnnaBridge	167:e84263d55307	1331	}
AnnaBridge	167:e84263d55307	1332
AnnaBridge	167:e84263d55307	1333	/**
AnnaBridge	167:e84263d55307	1334	* @brief Get FIFO threshold.
AnnaBridge	167:e84263d55307	1335	* @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
AnnaBridge	167:e84263d55307	1336	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1337	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1338	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1339	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1340	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1341	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1342	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1343	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1344	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1345	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1346	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1347	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	167:e84263d55307	1348	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	167:e84263d55307	1349	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	167:e84263d55307	1350	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	167:e84263d55307	1351	*/
AnnaBridge	167:e84263d55307	1352	__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1353	{
AnnaBridge	167:e84263d55307	1354	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
AnnaBridge	167:e84263d55307	1355	}
AnnaBridge	167:e84263d55307	1356
AnnaBridge	167:e84263d55307	1357	/**
AnnaBridge	167:e84263d55307	1358	* @brief Configure the FIFO .
AnnaBridge	167:e84263d55307	1359	* @rmtoll FCR FTH LL_DMA_ConfigFifo\n
AnnaBridge	167:e84263d55307	1360	* FCR DMDIS LL_DMA_ConfigFifo
AnnaBridge	167:e84263d55307	1361	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1362	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1363	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1364	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1365	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1366	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1367	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1368	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1369	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1370	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1371	* @param FifoMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1372	* @arg @ref LL_DMA_FIFOMODE_ENABLE
AnnaBridge	167:e84263d55307	1373	* @arg @ref LL_DMA_FIFOMODE_DISABLE
AnnaBridge	167:e84263d55307	1374	* @param FifoThreshold This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1375	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	167:e84263d55307	1376	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	167:e84263d55307	1377	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	167:e84263d55307	1378	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	167:e84263d55307	1379	* @retval None
AnnaBridge	167:e84263d55307	1380	*/
AnnaBridge	167:e84263d55307	1381	__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
AnnaBridge	167:e84263d55307	1382	{
AnnaBridge	167:e84263d55307	1383	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH\|DMA_SxFCR_DMDIS, FifoMode\|FifoThreshold);
AnnaBridge	167:e84263d55307	1384	}
AnnaBridge	167:e84263d55307	1385
AnnaBridge	167:e84263d55307	1386	/**
AnnaBridge	167:e84263d55307	1387	* @brief Configure the Source and Destination addresses.
AnnaBridge	167:e84263d55307	1388	* @note This API must not be called when the DMA stream is enabled.
AnnaBridge	167:e84263d55307	1389	* @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
AnnaBridge	167:e84263d55307	1390	* PAR PA LL_DMA_ConfigAddresses
AnnaBridge	167:e84263d55307	1391	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1392	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1393	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1394	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1395	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1396	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1397	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1398	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1399	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1400	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1401	* @param SrcAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1402	* @param DstAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1403	* @param Direction This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1404	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	167:e84263d55307	1405	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	167:e84263d55307	1406	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	167:e84263d55307	1407	* @retval None
AnnaBridge	167:e84263d55307	1408	*/
AnnaBridge	167:e84263d55307	1409	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
AnnaBridge	167:e84263d55307	1410	{
AnnaBridge	167:e84263d55307	1411	/* Direction Memory to Periph */
AnnaBridge	167:e84263d55307	1412	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	167:e84263d55307	1413	{
AnnaBridge	167:e84263d55307	1414	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
AnnaBridge	167:e84263d55307	1415	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
AnnaBridge	167:e84263d55307	1416	}
AnnaBridge	167:e84263d55307	1417	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	167:e84263d55307	1418	else
AnnaBridge	167:e84263d55307	1419	{
AnnaBridge	167:e84263d55307	1420	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
AnnaBridge	167:e84263d55307	1421	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
AnnaBridge	167:e84263d55307	1422	}
AnnaBridge	167:e84263d55307	1423	}
AnnaBridge	167:e84263d55307	1424
AnnaBridge	167:e84263d55307	1425	/**
AnnaBridge	167:e84263d55307	1426	* @brief Set the Memory address.
AnnaBridge	167:e84263d55307	1427	* @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
AnnaBridge	167:e84263d55307	1428	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	167:e84263d55307	1429	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	167:e84263d55307	1430	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1431	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1432	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1433	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1434	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1435	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1436	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1437	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1438	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1439	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1440	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1441	* @retval None
AnnaBridge	167:e84263d55307	1442	*/
AnnaBridge	167:e84263d55307	1443	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	167:e84263d55307	1444	{
AnnaBridge	167:e84263d55307	1445	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
AnnaBridge	167:e84263d55307	1446	}
AnnaBridge	167:e84263d55307	1447
AnnaBridge	167:e84263d55307	1448	/**
AnnaBridge	167:e84263d55307	1449	* @brief Set the Peripheral address.
AnnaBridge	167:e84263d55307	1450	* @rmtoll PAR PA LL_DMA_SetPeriphAddress
AnnaBridge	167:e84263d55307	1451	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	167:e84263d55307	1452	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	167:e84263d55307	1453	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1454	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1455	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1456	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1457	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1458	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1459	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1460	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1461	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1462	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1463	* @param PeriphAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1464	* @retval None
AnnaBridge	167:e84263d55307	1465	*/
AnnaBridge	167:e84263d55307	1466	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
AnnaBridge	167:e84263d55307	1467	{
AnnaBridge	167:e84263d55307	1468	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
AnnaBridge	167:e84263d55307	1469	}
AnnaBridge	167:e84263d55307	1470
AnnaBridge	167:e84263d55307	1471	/**
AnnaBridge	167:e84263d55307	1472	* @brief Get the Memory address.
AnnaBridge	167:e84263d55307	1473	* @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
AnnaBridge	167:e84263d55307	1474	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	167:e84263d55307	1475	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1476	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1477	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1478	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1479	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1480	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1481	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1482	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1483	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1484	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1485	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1486	*/
AnnaBridge	167:e84263d55307	1487	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1488	{
AnnaBridge	167:e84263d55307	1489	return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
AnnaBridge	167:e84263d55307	1490	}
AnnaBridge	167:e84263d55307	1491
AnnaBridge	167:e84263d55307	1492	/**
AnnaBridge	167:e84263d55307	1493	* @brief Get the Peripheral address.
AnnaBridge	167:e84263d55307	1494	* @rmtoll PAR PA LL_DMA_GetPeriphAddress
AnnaBridge	167:e84263d55307	1495	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	167:e84263d55307	1496	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1497	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1498	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1499	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1500	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1501	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1502	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1503	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1504	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1505	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1506	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1507	*/
AnnaBridge	167:e84263d55307	1508	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1509	{
AnnaBridge	167:e84263d55307	1510	return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
AnnaBridge	167:e84263d55307	1511	}
AnnaBridge	167:e84263d55307	1512
AnnaBridge	167:e84263d55307	1513	/**
AnnaBridge	167:e84263d55307	1514	* @brief Set the Memory to Memory Source address.
AnnaBridge	167:e84263d55307	1515	* @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	167:e84263d55307	1516	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	167:e84263d55307	1517	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	167:e84263d55307	1518	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1519	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1520	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1521	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1522	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1523	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1524	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1525	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1526	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1527	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1528	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1529	* @retval None
AnnaBridge	167:e84263d55307	1530	*/
AnnaBridge	167:e84263d55307	1531	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	167:e84263d55307	1532	{
AnnaBridge	167:e84263d55307	1533	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
AnnaBridge	167:e84263d55307	1534	}
AnnaBridge	167:e84263d55307	1535
AnnaBridge	167:e84263d55307	1536	/**
AnnaBridge	167:e84263d55307	1537	* @brief Set the Memory to Memory Destination address.
AnnaBridge	167:e84263d55307	1538	* @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
AnnaBridge	167:e84263d55307	1539	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	167:e84263d55307	1540	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	167:e84263d55307	1541	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1542	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1543	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1544	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1545	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1546	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1547	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1548	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1549	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1550	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1551	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1552	* @retval None
AnnaBridge	167:e84263d55307	1553	*/
AnnaBridge	167:e84263d55307	1554	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	167:e84263d55307	1555	{
AnnaBridge	167:e84263d55307	1556	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
AnnaBridge	167:e84263d55307	1557	}
AnnaBridge	167:e84263d55307	1558
AnnaBridge	167:e84263d55307	1559	/**
AnnaBridge	167:e84263d55307	1560	* @brief Get the Memory to Memory Source address.
AnnaBridge	167:e84263d55307	1561	* @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	167:e84263d55307	1562	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	167:e84263d55307	1563	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1564	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1565	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1566	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1567	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1568	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1569	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1570	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1571	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1572	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1573	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1574	*/
AnnaBridge	167:e84263d55307	1575	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1576	{
AnnaBridge	167:e84263d55307	1577	return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
AnnaBridge	167:e84263d55307	1578	}
AnnaBridge	167:e84263d55307	1579
AnnaBridge	167:e84263d55307	1580	/**
AnnaBridge	167:e84263d55307	1581	* @brief Get the Memory to Memory Destination address.
AnnaBridge	167:e84263d55307	1582	* @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
AnnaBridge	167:e84263d55307	1583	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	167:e84263d55307	1584	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1585	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1586	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1587	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1588	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1589	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1590	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1591	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1592	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1593	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1594	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1595	*/
AnnaBridge	167:e84263d55307	1596	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1597	{
AnnaBridge	167:e84263d55307	1598	return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
AnnaBridge	167:e84263d55307	1599	}
AnnaBridge	167:e84263d55307	1600
AnnaBridge	167:e84263d55307	1601	/**
AnnaBridge	167:e84263d55307	1602	* @brief Set Memory 1 address (used in case of Double buffer mode).
AnnaBridge	167:e84263d55307	1603	* @rmtoll M1AR M1A LL_DMA_SetMemory1Address
AnnaBridge	167:e84263d55307	1604	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1605	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1606	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1607	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1608	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1609	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1610	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1611	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1612	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1613	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1614	* @param Address Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1615	* @retval None
AnnaBridge	167:e84263d55307	1616	*/
AnnaBridge	167:e84263d55307	1617	__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
AnnaBridge	167:e84263d55307	1618	{
AnnaBridge	167:e84263d55307	1619	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
AnnaBridge	167:e84263d55307	1620	}
AnnaBridge	167:e84263d55307	1621
AnnaBridge	167:e84263d55307	1622	/**
AnnaBridge	167:e84263d55307	1623	* @brief Get Memory 1 address (used in case of Double buffer mode).
AnnaBridge	167:e84263d55307	1624	* @rmtoll M1AR M1A LL_DMA_GetMemory1Address
AnnaBridge	167:e84263d55307	1625	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1626	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1627	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	1628	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	1629	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	1630	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	1631	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	1632	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	1633	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	1634	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	1635	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	167:e84263d55307	1636	*/
AnnaBridge	167:e84263d55307	1637	__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	1638	{
AnnaBridge	167:e84263d55307	1639	return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
AnnaBridge	167:e84263d55307	1640	}
AnnaBridge	167:e84263d55307	1641
AnnaBridge	167:e84263d55307	1642	/**
AnnaBridge	167:e84263d55307	1643	* @}
AnnaBridge	167:e84263d55307	1644	*/
AnnaBridge	167:e84263d55307	1645
AnnaBridge	167:e84263d55307	1646	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	167:e84263d55307	1647	* @{
AnnaBridge	167:e84263d55307	1648	*/
AnnaBridge	167:e84263d55307	1649
AnnaBridge	167:e84263d55307	1650	/**
AnnaBridge	167:e84263d55307	1651	* @brief Get Stream 0 half transfer flag.
AnnaBridge	167:e84263d55307	1652	* @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
AnnaBridge	167:e84263d55307	1653	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1654	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1655	*/
AnnaBridge	167:e84263d55307	1656	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1657	{
AnnaBridge	167:e84263d55307	1658	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
AnnaBridge	167:e84263d55307	1659	}
AnnaBridge	167:e84263d55307	1660
AnnaBridge	167:e84263d55307	1661	/**
AnnaBridge	167:e84263d55307	1662	* @brief Get Stream 1 half transfer flag.
AnnaBridge	167:e84263d55307	1663	* @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	167:e84263d55307	1664	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1665	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1666	*/
AnnaBridge	167:e84263d55307	1667	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1668	{
AnnaBridge	167:e84263d55307	1669	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
AnnaBridge	167:e84263d55307	1670	}
AnnaBridge	167:e84263d55307	1671
AnnaBridge	167:e84263d55307	1672	/**
AnnaBridge	167:e84263d55307	1673	* @brief Get Stream 2 half transfer flag.
AnnaBridge	167:e84263d55307	1674	* @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	167:e84263d55307	1675	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1676	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1677	*/
AnnaBridge	167:e84263d55307	1678	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1679	{
AnnaBridge	167:e84263d55307	1680	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
AnnaBridge	167:e84263d55307	1681	}
AnnaBridge	167:e84263d55307	1682
AnnaBridge	167:e84263d55307	1683	/**
AnnaBridge	167:e84263d55307	1684	* @brief Get Stream 3 half transfer flag.
AnnaBridge	167:e84263d55307	1685	* @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	167:e84263d55307	1686	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1687	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1688	*/
AnnaBridge	167:e84263d55307	1689	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1690	{
AnnaBridge	167:e84263d55307	1691	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
AnnaBridge	167:e84263d55307	1692	}
AnnaBridge	167:e84263d55307	1693
AnnaBridge	167:e84263d55307	1694	/**
AnnaBridge	167:e84263d55307	1695	* @brief Get Stream 4 half transfer flag.
AnnaBridge	167:e84263d55307	1696	* @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	167:e84263d55307	1697	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1698	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1699	*/
AnnaBridge	167:e84263d55307	1700	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1701	{
AnnaBridge	167:e84263d55307	1702	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
AnnaBridge	167:e84263d55307	1703	}
AnnaBridge	167:e84263d55307	1704
AnnaBridge	167:e84263d55307	1705	/**
AnnaBridge	167:e84263d55307	1706	* @brief Get Stream 5 half transfer flag.
AnnaBridge	167:e84263d55307	1707	* @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
AnnaBridge	167:e84263d55307	1708	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1709	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1710	*/
AnnaBridge	167:e84263d55307	1711	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1712	{
AnnaBridge	167:e84263d55307	1713	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
AnnaBridge	167:e84263d55307	1714	}
AnnaBridge	167:e84263d55307	1715
AnnaBridge	167:e84263d55307	1716	/**
AnnaBridge	167:e84263d55307	1717	* @brief Get Stream 6 half transfer flag.
AnnaBridge	167:e84263d55307	1718	* @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	167:e84263d55307	1719	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1720	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1721	*/
AnnaBridge	167:e84263d55307	1722	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1723	{
AnnaBridge	167:e84263d55307	1724	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
AnnaBridge	167:e84263d55307	1725	}
AnnaBridge	167:e84263d55307	1726
AnnaBridge	167:e84263d55307	1727	/**
AnnaBridge	167:e84263d55307	1728	* @brief Get Stream 7 half transfer flag.
AnnaBridge	167:e84263d55307	1729	* @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	167:e84263d55307	1730	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1731	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1732	*/
AnnaBridge	167:e84263d55307	1733	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1734	{
AnnaBridge	167:e84263d55307	1735	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
AnnaBridge	167:e84263d55307	1736	}
AnnaBridge	167:e84263d55307	1737
AnnaBridge	167:e84263d55307	1738	/**
AnnaBridge	167:e84263d55307	1739	* @brief Get Stream 0 transfer complete flag.
AnnaBridge	167:e84263d55307	1740	* @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
AnnaBridge	167:e84263d55307	1741	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1742	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1743	*/
AnnaBridge	167:e84263d55307	1744	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1745	{
AnnaBridge	167:e84263d55307	1746	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
AnnaBridge	167:e84263d55307	1747	}
AnnaBridge	167:e84263d55307	1748
AnnaBridge	167:e84263d55307	1749	/**
AnnaBridge	167:e84263d55307	1750	* @brief Get Stream 1 transfer complete flag.
AnnaBridge	167:e84263d55307	1751	* @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	167:e84263d55307	1752	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1753	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1754	*/
AnnaBridge	167:e84263d55307	1755	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1756	{
AnnaBridge	167:e84263d55307	1757	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
AnnaBridge	167:e84263d55307	1758	}
AnnaBridge	167:e84263d55307	1759
AnnaBridge	167:e84263d55307	1760	/**
AnnaBridge	167:e84263d55307	1761	* @brief Get Stream 2 transfer complete flag.
AnnaBridge	167:e84263d55307	1762	* @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	167:e84263d55307	1763	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1764	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1765	*/
AnnaBridge	167:e84263d55307	1766	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1767	{
AnnaBridge	167:e84263d55307	1768	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
AnnaBridge	167:e84263d55307	1769	}
AnnaBridge	167:e84263d55307	1770
AnnaBridge	167:e84263d55307	1771	/**
AnnaBridge	167:e84263d55307	1772	* @brief Get Stream 3 transfer complete flag.
AnnaBridge	167:e84263d55307	1773	* @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	167:e84263d55307	1774	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1775	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1776	*/
AnnaBridge	167:e84263d55307	1777	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1778	{
AnnaBridge	167:e84263d55307	1779	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
AnnaBridge	167:e84263d55307	1780	}
AnnaBridge	167:e84263d55307	1781
AnnaBridge	167:e84263d55307	1782	/**
AnnaBridge	167:e84263d55307	1783	* @brief Get Stream 4 transfer complete flag.
AnnaBridge	167:e84263d55307	1784	* @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	167:e84263d55307	1785	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1786	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1787	*/
AnnaBridge	167:e84263d55307	1788	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1789	{
AnnaBridge	167:e84263d55307	1790	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
AnnaBridge	167:e84263d55307	1791	}
AnnaBridge	167:e84263d55307	1792
AnnaBridge	167:e84263d55307	1793	/**
AnnaBridge	167:e84263d55307	1794	* @brief Get Stream 5 transfer complete flag.
AnnaBridge	167:e84263d55307	1795	* @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
AnnaBridge	167:e84263d55307	1796	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1797	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1798	*/
AnnaBridge	167:e84263d55307	1799	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1800	{
AnnaBridge	167:e84263d55307	1801	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
AnnaBridge	167:e84263d55307	1802	}
AnnaBridge	167:e84263d55307	1803
AnnaBridge	167:e84263d55307	1804	/**
AnnaBridge	167:e84263d55307	1805	* @brief Get Stream 6 transfer complete flag.
AnnaBridge	167:e84263d55307	1806	* @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	167:e84263d55307	1807	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1808	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1809	*/
AnnaBridge	167:e84263d55307	1810	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1811	{
AnnaBridge	167:e84263d55307	1812	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
AnnaBridge	167:e84263d55307	1813	}
AnnaBridge	167:e84263d55307	1814
AnnaBridge	167:e84263d55307	1815	/**
AnnaBridge	167:e84263d55307	1816	* @brief Get Stream 7 transfer complete flag.
AnnaBridge	167:e84263d55307	1817	* @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	167:e84263d55307	1818	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1819	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1820	*/
AnnaBridge	167:e84263d55307	1821	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1822	{
AnnaBridge	167:e84263d55307	1823	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
AnnaBridge	167:e84263d55307	1824	}
AnnaBridge	167:e84263d55307	1825
AnnaBridge	167:e84263d55307	1826	/**
AnnaBridge	167:e84263d55307	1827	* @brief Get Stream 0 transfer error flag.
AnnaBridge	167:e84263d55307	1828	* @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
AnnaBridge	167:e84263d55307	1829	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1830	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1831	*/
AnnaBridge	167:e84263d55307	1832	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1833	{
AnnaBridge	167:e84263d55307	1834	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
AnnaBridge	167:e84263d55307	1835	}
AnnaBridge	167:e84263d55307	1836
AnnaBridge	167:e84263d55307	1837	/**
AnnaBridge	167:e84263d55307	1838	* @brief Get Stream 1 transfer error flag.
AnnaBridge	167:e84263d55307	1839	* @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	167:e84263d55307	1840	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1841	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1842	*/
AnnaBridge	167:e84263d55307	1843	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1844	{
AnnaBridge	167:e84263d55307	1845	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
AnnaBridge	167:e84263d55307	1846	}
AnnaBridge	167:e84263d55307	1847
AnnaBridge	167:e84263d55307	1848	/**
AnnaBridge	167:e84263d55307	1849	* @brief Get Stream 2 transfer error flag.
AnnaBridge	167:e84263d55307	1850	* @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	167:e84263d55307	1851	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1852	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1853	*/
AnnaBridge	167:e84263d55307	1854	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1855	{
AnnaBridge	167:e84263d55307	1856	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
AnnaBridge	167:e84263d55307	1857	}
AnnaBridge	167:e84263d55307	1858
AnnaBridge	167:e84263d55307	1859	/**
AnnaBridge	167:e84263d55307	1860	* @brief Get Stream 3 transfer error flag.
AnnaBridge	167:e84263d55307	1861	* @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	167:e84263d55307	1862	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1863	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1864	*/
AnnaBridge	167:e84263d55307	1865	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1866	{
AnnaBridge	167:e84263d55307	1867	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
AnnaBridge	167:e84263d55307	1868	}
AnnaBridge	167:e84263d55307	1869
AnnaBridge	167:e84263d55307	1870	/**
AnnaBridge	167:e84263d55307	1871	* @brief Get Stream 4 transfer error flag.
AnnaBridge	167:e84263d55307	1872	* @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	167:e84263d55307	1873	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1874	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1875	*/
AnnaBridge	167:e84263d55307	1876	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1877	{
AnnaBridge	167:e84263d55307	1878	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
AnnaBridge	167:e84263d55307	1879	}
AnnaBridge	167:e84263d55307	1880
AnnaBridge	167:e84263d55307	1881	/**
AnnaBridge	167:e84263d55307	1882	* @brief Get Stream 5 transfer error flag.
AnnaBridge	167:e84263d55307	1883	* @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
AnnaBridge	167:e84263d55307	1884	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1885	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1886	*/
AnnaBridge	167:e84263d55307	1887	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1888	{
AnnaBridge	167:e84263d55307	1889	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
AnnaBridge	167:e84263d55307	1890	}
AnnaBridge	167:e84263d55307	1891
AnnaBridge	167:e84263d55307	1892	/**
AnnaBridge	167:e84263d55307	1893	* @brief Get Stream 6 transfer error flag.
AnnaBridge	167:e84263d55307	1894	* @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	167:e84263d55307	1895	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1896	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1897	*/
AnnaBridge	167:e84263d55307	1898	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1899	{
AnnaBridge	167:e84263d55307	1900	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
AnnaBridge	167:e84263d55307	1901	}
AnnaBridge	167:e84263d55307	1902
AnnaBridge	167:e84263d55307	1903	/**
AnnaBridge	167:e84263d55307	1904	* @brief Get Stream 7 transfer error flag.
AnnaBridge	167:e84263d55307	1905	* @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	167:e84263d55307	1906	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1907	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1908	*/
AnnaBridge	167:e84263d55307	1909	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1910	{
AnnaBridge	167:e84263d55307	1911	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
AnnaBridge	167:e84263d55307	1912	}
AnnaBridge	167:e84263d55307	1913
AnnaBridge	167:e84263d55307	1914	/**
AnnaBridge	167:e84263d55307	1915	* @brief Get Stream 0 direct mode error flag.
AnnaBridge	167:e84263d55307	1916	* @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
AnnaBridge	167:e84263d55307	1917	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1918	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1919	*/
AnnaBridge	167:e84263d55307	1920	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1921	{
AnnaBridge	167:e84263d55307	1922	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
AnnaBridge	167:e84263d55307	1923	}
AnnaBridge	167:e84263d55307	1924
AnnaBridge	167:e84263d55307	1925	/**
AnnaBridge	167:e84263d55307	1926	* @brief Get Stream 1 direct mode error flag.
AnnaBridge	167:e84263d55307	1927	* @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
AnnaBridge	167:e84263d55307	1928	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1929	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1930	*/
AnnaBridge	167:e84263d55307	1931	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1932	{
AnnaBridge	167:e84263d55307	1933	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
AnnaBridge	167:e84263d55307	1934	}
AnnaBridge	167:e84263d55307	1935
AnnaBridge	167:e84263d55307	1936	/**
AnnaBridge	167:e84263d55307	1937	* @brief Get Stream 2 direct mode error flag.
AnnaBridge	167:e84263d55307	1938	* @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
AnnaBridge	167:e84263d55307	1939	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1940	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1941	*/
AnnaBridge	167:e84263d55307	1942	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1943	{
AnnaBridge	167:e84263d55307	1944	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
AnnaBridge	167:e84263d55307	1945	}
AnnaBridge	167:e84263d55307	1946
AnnaBridge	167:e84263d55307	1947	/**
AnnaBridge	167:e84263d55307	1948	* @brief Get Stream 3 direct mode error flag.
AnnaBridge	167:e84263d55307	1949	* @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
AnnaBridge	167:e84263d55307	1950	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1951	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1952	*/
AnnaBridge	167:e84263d55307	1953	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1954	{
AnnaBridge	167:e84263d55307	1955	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
AnnaBridge	167:e84263d55307	1956	}
AnnaBridge	167:e84263d55307	1957
AnnaBridge	167:e84263d55307	1958	/**
AnnaBridge	167:e84263d55307	1959	* @brief Get Stream 4 direct mode error flag.
AnnaBridge	167:e84263d55307	1960	* @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
AnnaBridge	167:e84263d55307	1961	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1962	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1963	*/
AnnaBridge	167:e84263d55307	1964	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1965	{
AnnaBridge	167:e84263d55307	1966	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
AnnaBridge	167:e84263d55307	1967	}
AnnaBridge	167:e84263d55307	1968
AnnaBridge	167:e84263d55307	1969	/**
AnnaBridge	167:e84263d55307	1970	* @brief Get Stream 5 direct mode error flag.
AnnaBridge	167:e84263d55307	1971	* @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
AnnaBridge	167:e84263d55307	1972	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1973	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1974	*/
AnnaBridge	167:e84263d55307	1975	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1976	{
AnnaBridge	167:e84263d55307	1977	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
AnnaBridge	167:e84263d55307	1978	}
AnnaBridge	167:e84263d55307	1979
AnnaBridge	167:e84263d55307	1980	/**
AnnaBridge	167:e84263d55307	1981	* @brief Get Stream 6 direct mode error flag.
AnnaBridge	167:e84263d55307	1982	* @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
AnnaBridge	167:e84263d55307	1983	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1984	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1985	*/
AnnaBridge	167:e84263d55307	1986	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1987	{
AnnaBridge	167:e84263d55307	1988	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
AnnaBridge	167:e84263d55307	1989	}
AnnaBridge	167:e84263d55307	1990
AnnaBridge	167:e84263d55307	1991	/**
AnnaBridge	167:e84263d55307	1992	* @brief Get Stream 7 direct mode error flag.
AnnaBridge	167:e84263d55307	1993	* @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
AnnaBridge	167:e84263d55307	1994	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	1995	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1996	*/
AnnaBridge	167:e84263d55307	1997	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	1998	{
AnnaBridge	167:e84263d55307	1999	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
AnnaBridge	167:e84263d55307	2000	}
AnnaBridge	167:e84263d55307	2001
AnnaBridge	167:e84263d55307	2002	/**
AnnaBridge	167:e84263d55307	2003	* @brief Get Stream 0 FIFO error flag.
AnnaBridge	167:e84263d55307	2004	* @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
AnnaBridge	167:e84263d55307	2005	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2006	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2007	*/
AnnaBridge	167:e84263d55307	2008	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2009	{
AnnaBridge	167:e84263d55307	2010	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
AnnaBridge	167:e84263d55307	2011	}
AnnaBridge	167:e84263d55307	2012
AnnaBridge	167:e84263d55307	2013	/**
AnnaBridge	167:e84263d55307	2014	* @brief Get Stream 1 FIFO error flag.
AnnaBridge	167:e84263d55307	2015	* @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
AnnaBridge	167:e84263d55307	2016	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2017	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2018	*/
AnnaBridge	167:e84263d55307	2019	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2020	{
AnnaBridge	167:e84263d55307	2021	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
AnnaBridge	167:e84263d55307	2022	}
AnnaBridge	167:e84263d55307	2023
AnnaBridge	167:e84263d55307	2024	/**
AnnaBridge	167:e84263d55307	2025	* @brief Get Stream 2 FIFO error flag.
AnnaBridge	167:e84263d55307	2026	* @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
AnnaBridge	167:e84263d55307	2027	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2028	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2029	*/
AnnaBridge	167:e84263d55307	2030	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2031	{
AnnaBridge	167:e84263d55307	2032	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
AnnaBridge	167:e84263d55307	2033	}
AnnaBridge	167:e84263d55307	2034
AnnaBridge	167:e84263d55307	2035	/**
AnnaBridge	167:e84263d55307	2036	* @brief Get Stream 3 FIFO error flag.
AnnaBridge	167:e84263d55307	2037	* @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
AnnaBridge	167:e84263d55307	2038	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2039	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2040	*/
AnnaBridge	167:e84263d55307	2041	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2042	{
AnnaBridge	167:e84263d55307	2043	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
AnnaBridge	167:e84263d55307	2044	}
AnnaBridge	167:e84263d55307	2045
AnnaBridge	167:e84263d55307	2046	/**
AnnaBridge	167:e84263d55307	2047	* @brief Get Stream 4 FIFO error flag.
AnnaBridge	167:e84263d55307	2048	* @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
AnnaBridge	167:e84263d55307	2049	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2050	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2051	*/
AnnaBridge	167:e84263d55307	2052	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2053	{
AnnaBridge	167:e84263d55307	2054	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
AnnaBridge	167:e84263d55307	2055	}
AnnaBridge	167:e84263d55307	2056
AnnaBridge	167:e84263d55307	2057	/**
AnnaBridge	167:e84263d55307	2058	* @brief Get Stream 5 FIFO error flag.
AnnaBridge	167:e84263d55307	2059	* @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
AnnaBridge	167:e84263d55307	2060	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2061	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2062	*/
AnnaBridge	167:e84263d55307	2063	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2064	{
AnnaBridge	167:e84263d55307	2065	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
AnnaBridge	167:e84263d55307	2066	}
AnnaBridge	167:e84263d55307	2067
AnnaBridge	167:e84263d55307	2068	/**
AnnaBridge	167:e84263d55307	2069	* @brief Get Stream 6 FIFO error flag.
AnnaBridge	167:e84263d55307	2070	* @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
AnnaBridge	167:e84263d55307	2071	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2072	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2073	*/
AnnaBridge	167:e84263d55307	2074	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2075	{
AnnaBridge	167:e84263d55307	2076	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
AnnaBridge	167:e84263d55307	2077	}
AnnaBridge	167:e84263d55307	2078
AnnaBridge	167:e84263d55307	2079	/**
AnnaBridge	167:e84263d55307	2080	* @brief Get Stream 7 FIFO error flag.
AnnaBridge	167:e84263d55307	2081	* @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
AnnaBridge	167:e84263d55307	2082	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2083	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2084	*/
AnnaBridge	167:e84263d55307	2085	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2086	{
AnnaBridge	167:e84263d55307	2087	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
AnnaBridge	167:e84263d55307	2088	}
AnnaBridge	167:e84263d55307	2089
AnnaBridge	167:e84263d55307	2090	/**
AnnaBridge	167:e84263d55307	2091	* @brief Clear Stream 0 half transfer flag.
AnnaBridge	167:e84263d55307	2092	* @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
AnnaBridge	167:e84263d55307	2093	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2094	* @retval None
AnnaBridge	167:e84263d55307	2095	*/
AnnaBridge	167:e84263d55307	2096	__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2097	{
AnnaBridge	182:a56a73fd2a6f	2098	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
AnnaBridge	167:e84263d55307	2099	}
AnnaBridge	167:e84263d55307	2100
AnnaBridge	167:e84263d55307	2101	/**
AnnaBridge	167:e84263d55307	2102	* @brief Clear Stream 1 half transfer flag.
AnnaBridge	167:e84263d55307	2103	* @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	167:e84263d55307	2104	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2105	* @retval None
AnnaBridge	167:e84263d55307	2106	*/
AnnaBridge	167:e84263d55307	2107	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2108	{
AnnaBridge	182:a56a73fd2a6f	2109	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
AnnaBridge	167:e84263d55307	2110	}
AnnaBridge	167:e84263d55307	2111
AnnaBridge	167:e84263d55307	2112	/**
AnnaBridge	167:e84263d55307	2113	* @brief Clear Stream 2 half transfer flag.
AnnaBridge	167:e84263d55307	2114	* @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	167:e84263d55307	2115	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2116	* @retval None
AnnaBridge	167:e84263d55307	2117	*/
AnnaBridge	167:e84263d55307	2118	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2119	{
AnnaBridge	182:a56a73fd2a6f	2120	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
AnnaBridge	167:e84263d55307	2121	}
AnnaBridge	167:e84263d55307	2122
AnnaBridge	167:e84263d55307	2123	/**
AnnaBridge	167:e84263d55307	2124	* @brief Clear Stream 3 half transfer flag.
AnnaBridge	167:e84263d55307	2125	* @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	167:e84263d55307	2126	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2127	* @retval None
AnnaBridge	167:e84263d55307	2128	*/
AnnaBridge	167:e84263d55307	2129	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2130	{
AnnaBridge	182:a56a73fd2a6f	2131	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
AnnaBridge	167:e84263d55307	2132	}
AnnaBridge	167:e84263d55307	2133
AnnaBridge	167:e84263d55307	2134	/**
AnnaBridge	167:e84263d55307	2135	* @brief Clear Stream 4 half transfer flag.
AnnaBridge	167:e84263d55307	2136	* @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	167:e84263d55307	2137	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2138	* @retval None
AnnaBridge	167:e84263d55307	2139	*/
AnnaBridge	167:e84263d55307	2140	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2141	{
AnnaBridge	182:a56a73fd2a6f	2142	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
AnnaBridge	167:e84263d55307	2143	}
AnnaBridge	167:e84263d55307	2144
AnnaBridge	167:e84263d55307	2145	/**
AnnaBridge	167:e84263d55307	2146	* @brief Clear Stream 5 half transfer flag.
AnnaBridge	167:e84263d55307	2147	* @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	167:e84263d55307	2148	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2149	* @retval None
AnnaBridge	167:e84263d55307	2150	*/
AnnaBridge	167:e84263d55307	2151	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2152	{
AnnaBridge	182:a56a73fd2a6f	2153	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
AnnaBridge	167:e84263d55307	2154	}
AnnaBridge	167:e84263d55307	2155
AnnaBridge	167:e84263d55307	2156	/**
AnnaBridge	167:e84263d55307	2157	* @brief Clear Stream 6 half transfer flag.
AnnaBridge	167:e84263d55307	2158	* @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	167:e84263d55307	2159	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2160	* @retval None
AnnaBridge	167:e84263d55307	2161	*/
AnnaBridge	167:e84263d55307	2162	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2163	{
AnnaBridge	182:a56a73fd2a6f	2164	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
AnnaBridge	167:e84263d55307	2165	}
AnnaBridge	167:e84263d55307	2166
AnnaBridge	167:e84263d55307	2167	/**
AnnaBridge	167:e84263d55307	2168	* @brief Clear Stream 7 half transfer flag.
AnnaBridge	167:e84263d55307	2169	* @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	167:e84263d55307	2170	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2171	* @retval None
AnnaBridge	167:e84263d55307	2172	*/
AnnaBridge	167:e84263d55307	2173	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2174	{
AnnaBridge	182:a56a73fd2a6f	2175	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
AnnaBridge	167:e84263d55307	2176	}
AnnaBridge	167:e84263d55307	2177
AnnaBridge	167:e84263d55307	2178	/**
AnnaBridge	167:e84263d55307	2179	* @brief Clear Stream 0 transfer complete flag.
AnnaBridge	167:e84263d55307	2180	* @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
AnnaBridge	167:e84263d55307	2181	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2182	* @retval None
AnnaBridge	167:e84263d55307	2183	*/
AnnaBridge	167:e84263d55307	2184	__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2185	{
AnnaBridge	182:a56a73fd2a6f	2186	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
AnnaBridge	167:e84263d55307	2187	}
AnnaBridge	167:e84263d55307	2188
AnnaBridge	167:e84263d55307	2189	/**
AnnaBridge	167:e84263d55307	2190	* @brief Clear Stream 1 transfer complete flag.
AnnaBridge	167:e84263d55307	2191	* @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	167:e84263d55307	2192	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2193	* @retval None
AnnaBridge	167:e84263d55307	2194	*/
AnnaBridge	167:e84263d55307	2195	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2196	{
AnnaBridge	182:a56a73fd2a6f	2197	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
AnnaBridge	167:e84263d55307	2198	}
AnnaBridge	167:e84263d55307	2199
AnnaBridge	167:e84263d55307	2200	/**
AnnaBridge	167:e84263d55307	2201	* @brief Clear Stream 2 transfer complete flag.
AnnaBridge	167:e84263d55307	2202	* @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	167:e84263d55307	2203	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2204	* @retval None
AnnaBridge	167:e84263d55307	2205	*/
AnnaBridge	167:e84263d55307	2206	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2207	{
AnnaBridge	182:a56a73fd2a6f	2208	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
AnnaBridge	167:e84263d55307	2209	}
AnnaBridge	167:e84263d55307	2210
AnnaBridge	167:e84263d55307	2211	/**
AnnaBridge	167:e84263d55307	2212	* @brief Clear Stream 3 transfer complete flag.
AnnaBridge	167:e84263d55307	2213	* @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	167:e84263d55307	2214	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2215	* @retval None
AnnaBridge	167:e84263d55307	2216	*/
AnnaBridge	167:e84263d55307	2217	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2218	{
AnnaBridge	182:a56a73fd2a6f	2219	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
AnnaBridge	167:e84263d55307	2220	}
AnnaBridge	167:e84263d55307	2221
AnnaBridge	167:e84263d55307	2222	/**
AnnaBridge	167:e84263d55307	2223	* @brief Clear Stream 4 transfer complete flag.
AnnaBridge	167:e84263d55307	2224	* @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	167:e84263d55307	2225	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2226	* @retval None
AnnaBridge	167:e84263d55307	2227	*/
AnnaBridge	167:e84263d55307	2228	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2229	{
AnnaBridge	182:a56a73fd2a6f	2230	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
AnnaBridge	167:e84263d55307	2231	}
AnnaBridge	167:e84263d55307	2232
AnnaBridge	167:e84263d55307	2233	/**
AnnaBridge	167:e84263d55307	2234	* @brief Clear Stream 5 transfer complete flag.
AnnaBridge	167:e84263d55307	2235	* @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	167:e84263d55307	2236	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2237	* @retval None
AnnaBridge	167:e84263d55307	2238	*/
AnnaBridge	167:e84263d55307	2239	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2240	{
AnnaBridge	182:a56a73fd2a6f	2241	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
AnnaBridge	167:e84263d55307	2242	}
AnnaBridge	167:e84263d55307	2243
AnnaBridge	167:e84263d55307	2244	/**
AnnaBridge	167:e84263d55307	2245	* @brief Clear Stream 6 transfer complete flag.
AnnaBridge	167:e84263d55307	2246	* @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	167:e84263d55307	2247	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2248	* @retval None
AnnaBridge	167:e84263d55307	2249	*/
AnnaBridge	167:e84263d55307	2250	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2251	{
AnnaBridge	182:a56a73fd2a6f	2252	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
AnnaBridge	167:e84263d55307	2253	}
AnnaBridge	167:e84263d55307	2254
AnnaBridge	167:e84263d55307	2255	/**
AnnaBridge	167:e84263d55307	2256	* @brief Clear Stream 7 transfer complete flag.
AnnaBridge	167:e84263d55307	2257	* @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	167:e84263d55307	2258	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2259	* @retval None
AnnaBridge	167:e84263d55307	2260	*/
AnnaBridge	167:e84263d55307	2261	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2262	{
AnnaBridge	182:a56a73fd2a6f	2263	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
AnnaBridge	167:e84263d55307	2264	}
AnnaBridge	167:e84263d55307	2265
AnnaBridge	167:e84263d55307	2266	/**
AnnaBridge	167:e84263d55307	2267	* @brief Clear Stream 0 transfer error flag.
AnnaBridge	167:e84263d55307	2268	* @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
AnnaBridge	167:e84263d55307	2269	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2270	* @retval None
AnnaBridge	167:e84263d55307	2271	*/
AnnaBridge	167:e84263d55307	2272	__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2273	{
AnnaBridge	182:a56a73fd2a6f	2274	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
AnnaBridge	167:e84263d55307	2275	}
AnnaBridge	167:e84263d55307	2276
AnnaBridge	167:e84263d55307	2277	/**
AnnaBridge	167:e84263d55307	2278	* @brief Clear Stream 1 transfer error flag.
AnnaBridge	167:e84263d55307	2279	* @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	167:e84263d55307	2280	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2281	* @retval None
AnnaBridge	167:e84263d55307	2282	*/
AnnaBridge	167:e84263d55307	2283	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2284	{
AnnaBridge	182:a56a73fd2a6f	2285	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
AnnaBridge	167:e84263d55307	2286	}
AnnaBridge	167:e84263d55307	2287
AnnaBridge	167:e84263d55307	2288	/**
AnnaBridge	167:e84263d55307	2289	* @brief Clear Stream 2 transfer error flag.
AnnaBridge	167:e84263d55307	2290	* @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	167:e84263d55307	2291	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2292	* @retval None
AnnaBridge	167:e84263d55307	2293	*/
AnnaBridge	167:e84263d55307	2294	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2295	{
AnnaBridge	182:a56a73fd2a6f	2296	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
AnnaBridge	167:e84263d55307	2297	}
AnnaBridge	167:e84263d55307	2298
AnnaBridge	167:e84263d55307	2299	/**
AnnaBridge	167:e84263d55307	2300	* @brief Clear Stream 3 transfer error flag.
AnnaBridge	167:e84263d55307	2301	* @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	167:e84263d55307	2302	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2303	* @retval None
AnnaBridge	167:e84263d55307	2304	*/
AnnaBridge	167:e84263d55307	2305	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2306	{
AnnaBridge	182:a56a73fd2a6f	2307	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
AnnaBridge	167:e84263d55307	2308	}
AnnaBridge	167:e84263d55307	2309
AnnaBridge	167:e84263d55307	2310	/**
AnnaBridge	167:e84263d55307	2311	* @brief Clear Stream 4 transfer error flag.
AnnaBridge	167:e84263d55307	2312	* @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	167:e84263d55307	2313	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2314	* @retval None
AnnaBridge	167:e84263d55307	2315	*/
AnnaBridge	167:e84263d55307	2316	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2317	{
AnnaBridge	182:a56a73fd2a6f	2318	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
AnnaBridge	167:e84263d55307	2319	}
AnnaBridge	167:e84263d55307	2320
AnnaBridge	167:e84263d55307	2321	/**
AnnaBridge	167:e84263d55307	2322	* @brief Clear Stream 5 transfer error flag.
AnnaBridge	167:e84263d55307	2323	* @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	167:e84263d55307	2324	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2325	* @retval None
AnnaBridge	167:e84263d55307	2326	*/
AnnaBridge	167:e84263d55307	2327	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2328	{
AnnaBridge	182:a56a73fd2a6f	2329	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
AnnaBridge	167:e84263d55307	2330	}
AnnaBridge	167:e84263d55307	2331
AnnaBridge	167:e84263d55307	2332	/**
AnnaBridge	167:e84263d55307	2333	* @brief Clear Stream 6 transfer error flag.
AnnaBridge	167:e84263d55307	2334	* @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	167:e84263d55307	2335	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2336	* @retval None
AnnaBridge	167:e84263d55307	2337	*/
AnnaBridge	167:e84263d55307	2338	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2339	{
AnnaBridge	182:a56a73fd2a6f	2340	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
AnnaBridge	167:e84263d55307	2341	}
AnnaBridge	167:e84263d55307	2342
AnnaBridge	167:e84263d55307	2343	/**
AnnaBridge	167:e84263d55307	2344	* @brief Clear Stream 7 transfer error flag.
AnnaBridge	167:e84263d55307	2345	* @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	167:e84263d55307	2346	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2347	* @retval None
AnnaBridge	167:e84263d55307	2348	*/
AnnaBridge	167:e84263d55307	2349	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2350	{
AnnaBridge	182:a56a73fd2a6f	2351	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
AnnaBridge	167:e84263d55307	2352	}
AnnaBridge	167:e84263d55307	2353
AnnaBridge	167:e84263d55307	2354	/**
AnnaBridge	167:e84263d55307	2355	* @brief Clear Stream 0 direct mode error flag.
AnnaBridge	167:e84263d55307	2356	* @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
AnnaBridge	167:e84263d55307	2357	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2358	* @retval None
AnnaBridge	167:e84263d55307	2359	*/
AnnaBridge	167:e84263d55307	2360	__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2361	{
AnnaBridge	182:a56a73fd2a6f	2362	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
AnnaBridge	167:e84263d55307	2363	}
AnnaBridge	167:e84263d55307	2364
AnnaBridge	167:e84263d55307	2365	/**
AnnaBridge	167:e84263d55307	2366	* @brief Clear Stream 1 direct mode error flag.
AnnaBridge	167:e84263d55307	2367	* @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
AnnaBridge	167:e84263d55307	2368	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2369	* @retval None
AnnaBridge	167:e84263d55307	2370	*/
AnnaBridge	167:e84263d55307	2371	__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2372	{
AnnaBridge	182:a56a73fd2a6f	2373	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
AnnaBridge	167:e84263d55307	2374	}
AnnaBridge	167:e84263d55307	2375
AnnaBridge	167:e84263d55307	2376	/**
AnnaBridge	167:e84263d55307	2377	* @brief Clear Stream 2 direct mode error flag.
AnnaBridge	167:e84263d55307	2378	* @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
AnnaBridge	167:e84263d55307	2379	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2380	* @retval None
AnnaBridge	167:e84263d55307	2381	*/
AnnaBridge	167:e84263d55307	2382	__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2383	{
AnnaBridge	182:a56a73fd2a6f	2384	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
AnnaBridge	167:e84263d55307	2385	}
AnnaBridge	167:e84263d55307	2386
AnnaBridge	167:e84263d55307	2387	/**
AnnaBridge	167:e84263d55307	2388	* @brief Clear Stream 3 direct mode error flag.
AnnaBridge	167:e84263d55307	2389	* @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
AnnaBridge	167:e84263d55307	2390	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2391	* @retval None
AnnaBridge	167:e84263d55307	2392	*/
AnnaBridge	167:e84263d55307	2393	__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2394	{
AnnaBridge	182:a56a73fd2a6f	2395	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
AnnaBridge	167:e84263d55307	2396	}
AnnaBridge	167:e84263d55307	2397
AnnaBridge	167:e84263d55307	2398	/**
AnnaBridge	167:e84263d55307	2399	* @brief Clear Stream 4 direct mode error flag.
AnnaBridge	167:e84263d55307	2400	* @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
AnnaBridge	167:e84263d55307	2401	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2402	* @retval None
AnnaBridge	167:e84263d55307	2403	*/
AnnaBridge	167:e84263d55307	2404	__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2405	{
AnnaBridge	182:a56a73fd2a6f	2406	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
AnnaBridge	167:e84263d55307	2407	}
AnnaBridge	167:e84263d55307	2408
AnnaBridge	167:e84263d55307	2409	/**
AnnaBridge	167:e84263d55307	2410	* @brief Clear Stream 5 direct mode error flag.
AnnaBridge	167:e84263d55307	2411	* @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
AnnaBridge	167:e84263d55307	2412	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2413	* @retval None
AnnaBridge	167:e84263d55307	2414	*/
AnnaBridge	167:e84263d55307	2415	__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2416	{
AnnaBridge	182:a56a73fd2a6f	2417	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
AnnaBridge	167:e84263d55307	2418	}
AnnaBridge	167:e84263d55307	2419
AnnaBridge	167:e84263d55307	2420	/**
AnnaBridge	167:e84263d55307	2421	* @brief Clear Stream 6 direct mode error flag.
AnnaBridge	167:e84263d55307	2422	* @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
AnnaBridge	167:e84263d55307	2423	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2424	* @retval None
AnnaBridge	167:e84263d55307	2425	*/
AnnaBridge	167:e84263d55307	2426	__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2427	{
AnnaBridge	182:a56a73fd2a6f	2428	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
AnnaBridge	167:e84263d55307	2429	}
AnnaBridge	167:e84263d55307	2430
AnnaBridge	167:e84263d55307	2431	/**
AnnaBridge	167:e84263d55307	2432	* @brief Clear Stream 7 direct mode error flag.
AnnaBridge	167:e84263d55307	2433	* @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
AnnaBridge	167:e84263d55307	2434	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2435	* @retval None
AnnaBridge	167:e84263d55307	2436	*/
AnnaBridge	167:e84263d55307	2437	__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2438	{
AnnaBridge	182:a56a73fd2a6f	2439	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
AnnaBridge	167:e84263d55307	2440	}
AnnaBridge	167:e84263d55307	2441
AnnaBridge	167:e84263d55307	2442	/**
AnnaBridge	167:e84263d55307	2443	* @brief Clear Stream 0 FIFO error flag.
AnnaBridge	167:e84263d55307	2444	* @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
AnnaBridge	167:e84263d55307	2445	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2446	* @retval None
AnnaBridge	167:e84263d55307	2447	*/
AnnaBridge	167:e84263d55307	2448	__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2449	{
AnnaBridge	182:a56a73fd2a6f	2450	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
AnnaBridge	167:e84263d55307	2451	}
AnnaBridge	167:e84263d55307	2452
AnnaBridge	167:e84263d55307	2453	/**
AnnaBridge	167:e84263d55307	2454	* @brief Clear Stream 1 FIFO error flag.
AnnaBridge	167:e84263d55307	2455	* @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
AnnaBridge	167:e84263d55307	2456	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2457	* @retval None
AnnaBridge	167:e84263d55307	2458	*/
AnnaBridge	167:e84263d55307	2459	__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2460	{
AnnaBridge	182:a56a73fd2a6f	2461	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
AnnaBridge	167:e84263d55307	2462	}
AnnaBridge	167:e84263d55307	2463
AnnaBridge	167:e84263d55307	2464	/**
AnnaBridge	167:e84263d55307	2465	* @brief Clear Stream 2 FIFO error flag.
AnnaBridge	167:e84263d55307	2466	* @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
AnnaBridge	167:e84263d55307	2467	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2468	* @retval None
AnnaBridge	167:e84263d55307	2469	*/
AnnaBridge	167:e84263d55307	2470	__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2471	{
AnnaBridge	182:a56a73fd2a6f	2472	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
AnnaBridge	167:e84263d55307	2473	}
AnnaBridge	167:e84263d55307	2474
AnnaBridge	167:e84263d55307	2475	/**
AnnaBridge	167:e84263d55307	2476	* @brief Clear Stream 3 FIFO error flag.
AnnaBridge	167:e84263d55307	2477	* @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
AnnaBridge	167:e84263d55307	2478	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2479	* @retval None
AnnaBridge	167:e84263d55307	2480	*/
AnnaBridge	167:e84263d55307	2481	__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2482	{
AnnaBridge	182:a56a73fd2a6f	2483	WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
AnnaBridge	167:e84263d55307	2484	}
AnnaBridge	167:e84263d55307	2485
AnnaBridge	167:e84263d55307	2486	/**
AnnaBridge	167:e84263d55307	2487	* @brief Clear Stream 4 FIFO error flag.
AnnaBridge	167:e84263d55307	2488	* @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
AnnaBridge	167:e84263d55307	2489	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2490	* @retval None
AnnaBridge	167:e84263d55307	2491	*/
AnnaBridge	167:e84263d55307	2492	__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2493	{
AnnaBridge	182:a56a73fd2a6f	2494	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
AnnaBridge	167:e84263d55307	2495	}
AnnaBridge	167:e84263d55307	2496
AnnaBridge	167:e84263d55307	2497	/**
AnnaBridge	167:e84263d55307	2498	* @brief Clear Stream 5 FIFO error flag.
AnnaBridge	167:e84263d55307	2499	* @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
AnnaBridge	167:e84263d55307	2500	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2501	* @retval None
AnnaBridge	167:e84263d55307	2502	*/
AnnaBridge	167:e84263d55307	2503	__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2504	{
AnnaBridge	182:a56a73fd2a6f	2505	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
AnnaBridge	167:e84263d55307	2506	}
AnnaBridge	167:e84263d55307	2507
AnnaBridge	167:e84263d55307	2508	/**
AnnaBridge	167:e84263d55307	2509	* @brief Clear Stream 6 FIFO error flag.
AnnaBridge	167:e84263d55307	2510	* @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
AnnaBridge	167:e84263d55307	2511	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2512	* @retval None
AnnaBridge	167:e84263d55307	2513	*/
AnnaBridge	167:e84263d55307	2514	__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2515	{
AnnaBridge	182:a56a73fd2a6f	2516	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
AnnaBridge	167:e84263d55307	2517	}
AnnaBridge	167:e84263d55307	2518
AnnaBridge	167:e84263d55307	2519	/**
AnnaBridge	167:e84263d55307	2520	* @brief Clear Stream 7 FIFO error flag.
AnnaBridge	167:e84263d55307	2521	* @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
AnnaBridge	167:e84263d55307	2522	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2523	* @retval None
AnnaBridge	167:e84263d55307	2524	*/
AnnaBridge	167:e84263d55307	2525	__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
AnnaBridge	167:e84263d55307	2526	{
AnnaBridge	182:a56a73fd2a6f	2527	WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
AnnaBridge	167:e84263d55307	2528	}
AnnaBridge	167:e84263d55307	2529
AnnaBridge	167:e84263d55307	2530	/**
AnnaBridge	167:e84263d55307	2531	* @}
AnnaBridge	167:e84263d55307	2532	*/
AnnaBridge	167:e84263d55307	2533
AnnaBridge	167:e84263d55307	2534	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	167:e84263d55307	2535	* @{
AnnaBridge	167:e84263d55307	2536	*/
AnnaBridge	167:e84263d55307	2537
AnnaBridge	167:e84263d55307	2538	/**
AnnaBridge	167:e84263d55307	2539	* @brief Enable Half transfer interrupt.
AnnaBridge	167:e84263d55307	2540	* @rmtoll CR HTIE LL_DMA_EnableIT_HT
AnnaBridge	167:e84263d55307	2541	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2542	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2543	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2544	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2545	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2546	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2547	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2548	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2549	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2550	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2551	* @retval None
AnnaBridge	167:e84263d55307	2552	*/
AnnaBridge	167:e84263d55307	2553	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2554	{
AnnaBridge	167:e84263d55307	2555	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
AnnaBridge	167:e84263d55307	2556	}
AnnaBridge	167:e84263d55307	2557
AnnaBridge	167:e84263d55307	2558	/**
AnnaBridge	167:e84263d55307	2559	* @brief Enable Transfer error interrupt.
AnnaBridge	167:e84263d55307	2560	* @rmtoll CR TEIE LL_DMA_EnableIT_TE
AnnaBridge	167:e84263d55307	2561	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2562	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2563	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2564	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2565	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2566	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2567	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2568	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2569	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2570	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2571	* @retval None
AnnaBridge	167:e84263d55307	2572	*/
AnnaBridge	167:e84263d55307	2573	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2574	{
AnnaBridge	167:e84263d55307	2575	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
AnnaBridge	167:e84263d55307	2576	}
AnnaBridge	167:e84263d55307	2577
AnnaBridge	167:e84263d55307	2578	/**
AnnaBridge	167:e84263d55307	2579	* @brief Enable Transfer complete interrupt.
AnnaBridge	167:e84263d55307	2580	* @rmtoll CR TCIE LL_DMA_EnableIT_TC
AnnaBridge	167:e84263d55307	2581	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2582	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2583	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2584	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2585	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2586	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2587	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2588	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2589	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2590	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2591	* @retval None
AnnaBridge	167:e84263d55307	2592	*/
AnnaBridge	167:e84263d55307	2593	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2594	{
AnnaBridge	167:e84263d55307	2595	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
AnnaBridge	167:e84263d55307	2596	}
AnnaBridge	167:e84263d55307	2597
AnnaBridge	167:e84263d55307	2598	/**
AnnaBridge	167:e84263d55307	2599	* @brief Enable Direct mode error interrupt.
AnnaBridge	167:e84263d55307	2600	* @rmtoll CR DMEIE LL_DMA_EnableIT_DME
AnnaBridge	167:e84263d55307	2601	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2602	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2603	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2604	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2605	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2606	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2607	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2608	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2609	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2610	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2611	* @retval None
AnnaBridge	167:e84263d55307	2612	*/
AnnaBridge	167:e84263d55307	2613	__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2614	{
AnnaBridge	167:e84263d55307	2615	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
AnnaBridge	167:e84263d55307	2616	}
AnnaBridge	167:e84263d55307	2617
AnnaBridge	167:e84263d55307	2618	/**
AnnaBridge	167:e84263d55307	2619	* @brief Enable FIFO error interrupt.
AnnaBridge	167:e84263d55307	2620	* @rmtoll FCR FEIE LL_DMA_EnableIT_FE
AnnaBridge	167:e84263d55307	2621	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2622	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2623	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2624	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2625	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2626	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2627	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2628	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2629	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2630	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2631	* @retval None
AnnaBridge	167:e84263d55307	2632	*/
AnnaBridge	167:e84263d55307	2633	__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2634	{
AnnaBridge	167:e84263d55307	2635	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
AnnaBridge	167:e84263d55307	2636	}
AnnaBridge	167:e84263d55307	2637
AnnaBridge	167:e84263d55307	2638	/**
AnnaBridge	167:e84263d55307	2639	* @brief Disable Half transfer interrupt.
AnnaBridge	167:e84263d55307	2640	* @rmtoll CR HTIE LL_DMA_DisableIT_HT
AnnaBridge	167:e84263d55307	2641	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2642	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2643	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2644	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2645	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2646	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2647	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2648	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2649	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2650	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2651	* @retval None
AnnaBridge	167:e84263d55307	2652	*/
AnnaBridge	167:e84263d55307	2653	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2654	{
AnnaBridge	167:e84263d55307	2655	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
AnnaBridge	167:e84263d55307	2656	}
AnnaBridge	167:e84263d55307	2657
AnnaBridge	167:e84263d55307	2658	/**
AnnaBridge	167:e84263d55307	2659	* @brief Disable Transfer error interrupt.
AnnaBridge	167:e84263d55307	2660	* @rmtoll CR TEIE LL_DMA_DisableIT_TE
AnnaBridge	167:e84263d55307	2661	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2662	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2663	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2664	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2665	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2666	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2667	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2668	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2669	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2670	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2671	* @retval None
AnnaBridge	167:e84263d55307	2672	*/
AnnaBridge	167:e84263d55307	2673	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2674	{
AnnaBridge	167:e84263d55307	2675	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
AnnaBridge	167:e84263d55307	2676	}
AnnaBridge	167:e84263d55307	2677
AnnaBridge	167:e84263d55307	2678	/**
AnnaBridge	167:e84263d55307	2679	* @brief Disable Transfer complete interrupt.
AnnaBridge	167:e84263d55307	2680	* @rmtoll CR TCIE LL_DMA_DisableIT_TC
AnnaBridge	167:e84263d55307	2681	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2682	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2683	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2684	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2685	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2686	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2687	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2688	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2689	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2690	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2691	* @retval None
AnnaBridge	167:e84263d55307	2692	*/
AnnaBridge	167:e84263d55307	2693	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2694	{
AnnaBridge	167:e84263d55307	2695	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
AnnaBridge	167:e84263d55307	2696	}
AnnaBridge	167:e84263d55307	2697
AnnaBridge	167:e84263d55307	2698	/**
AnnaBridge	167:e84263d55307	2699	* @brief Disable Direct mode error interrupt.
AnnaBridge	167:e84263d55307	2700	* @rmtoll CR DMEIE LL_DMA_DisableIT_DME
AnnaBridge	167:e84263d55307	2701	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2702	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2703	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2704	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2705	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2706	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2707	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2708	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2709	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2710	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2711	* @retval None
AnnaBridge	167:e84263d55307	2712	*/
AnnaBridge	167:e84263d55307	2713	__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2714	{
AnnaBridge	167:e84263d55307	2715	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
AnnaBridge	167:e84263d55307	2716	}
AnnaBridge	167:e84263d55307	2717
AnnaBridge	167:e84263d55307	2718	/**
AnnaBridge	167:e84263d55307	2719	* @brief Disable FIFO error interrupt.
AnnaBridge	167:e84263d55307	2720	* @rmtoll FCR FEIE LL_DMA_DisableIT_FE
AnnaBridge	167:e84263d55307	2721	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2722	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2723	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2724	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2725	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2726	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2727	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2728	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2729	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2730	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2731	* @retval None
AnnaBridge	167:e84263d55307	2732	*/
AnnaBridge	167:e84263d55307	2733	__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2734	{
AnnaBridge	167:e84263d55307	2735	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
AnnaBridge	167:e84263d55307	2736	}
AnnaBridge	167:e84263d55307	2737
AnnaBridge	167:e84263d55307	2738	/**
AnnaBridge	167:e84263d55307	2739	* @brief Check if Half transfer interrup is enabled.
AnnaBridge	167:e84263d55307	2740	* @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	167:e84263d55307	2741	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2742	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2743	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2744	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2745	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2746	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2747	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2748	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2749	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2750	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2751	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2752	*/
AnnaBridge	167:e84263d55307	2753	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2754	{
AnnaBridge	167:e84263d55307	2755	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
AnnaBridge	167:e84263d55307	2756	}
AnnaBridge	167:e84263d55307	2757
AnnaBridge	167:e84263d55307	2758	/**
AnnaBridge	167:e84263d55307	2759	* @brief Check if Transfer error nterrup is enabled.
AnnaBridge	167:e84263d55307	2760	* @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	167:e84263d55307	2761	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2762	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2763	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2764	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2765	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2766	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2767	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2768	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2769	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2770	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2771	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2772	*/
AnnaBridge	167:e84263d55307	2773	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2774	{
AnnaBridge	167:e84263d55307	2775	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
AnnaBridge	167:e84263d55307	2776	}
AnnaBridge	167:e84263d55307	2777
AnnaBridge	167:e84263d55307	2778	/**
AnnaBridge	167:e84263d55307	2779	* @brief Check if Transfer complete interrup is enabled.
AnnaBridge	167:e84263d55307	2780	* @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	167:e84263d55307	2781	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2782	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2783	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2784	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2785	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2786	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2787	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2788	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2789	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2790	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2791	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2792	*/
AnnaBridge	167:e84263d55307	2793	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2794	{
AnnaBridge	167:e84263d55307	2795	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
AnnaBridge	167:e84263d55307	2796	}
AnnaBridge	167:e84263d55307	2797
AnnaBridge	167:e84263d55307	2798	/**
AnnaBridge	167:e84263d55307	2799	* @brief Check if Direct mode error interrupt is enabled.
AnnaBridge	167:e84263d55307	2800	* @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
AnnaBridge	167:e84263d55307	2801	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2802	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2803	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2804	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2805	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2806	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2807	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2808	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2809	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2810	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2811	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2812	*/
AnnaBridge	167:e84263d55307	2813	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2814	{
AnnaBridge	167:e84263d55307	2815	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
AnnaBridge	167:e84263d55307	2816	}
AnnaBridge	167:e84263d55307	2817
AnnaBridge	167:e84263d55307	2818	/**
AnnaBridge	167:e84263d55307	2819	* @brief Check if FIFO error interrup is enabled.
AnnaBridge	167:e84263d55307	2820	* @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
AnnaBridge	167:e84263d55307	2821	* @param DMAx DMAx Instance
AnnaBridge	167:e84263d55307	2822	* @param Stream This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	2823	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	167:e84263d55307	2824	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	167:e84263d55307	2825	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	167:e84263d55307	2826	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	167:e84263d55307	2827	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	167:e84263d55307	2828	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	167:e84263d55307	2829	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	167:e84263d55307	2830	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	167:e84263d55307	2831	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	2832	*/
AnnaBridge	167:e84263d55307	2833	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	167:e84263d55307	2834	{
AnnaBridge	167:e84263d55307	2835	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
AnnaBridge	167:e84263d55307	2836	}
AnnaBridge	167:e84263d55307	2837
AnnaBridge	167:e84263d55307	2838	/**
AnnaBridge	167:e84263d55307	2839	* @}
AnnaBridge	167:e84263d55307	2840	*/
AnnaBridge	167:e84263d55307	2841
AnnaBridge	167:e84263d55307	2842	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	2843	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	167:e84263d55307	2844	* @{
AnnaBridge	167:e84263d55307	2845	*/
AnnaBridge	167:e84263d55307	2846
AnnaBridge	167:e84263d55307	2847	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Stream, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	167:e84263d55307	2848	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
AnnaBridge	167:e84263d55307	2849	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	167:e84263d55307	2850
AnnaBridge	167:e84263d55307	2851	/**
AnnaBridge	167:e84263d55307	2852	* @}
AnnaBridge	167:e84263d55307	2853	*/
AnnaBridge	167:e84263d55307	2854	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	2855
AnnaBridge	167:e84263d55307	2856	/**
AnnaBridge	167:e84263d55307	2857	* @}
AnnaBridge	167:e84263d55307	2858	*/
AnnaBridge	167:e84263d55307	2859
AnnaBridge	167:e84263d55307	2860	/**
AnnaBridge	167:e84263d55307	2861	* @}
AnnaBridge	167:e84263d55307	2862	*/
AnnaBridge	167:e84263d55307	2863
AnnaBridge	167:e84263d55307	2864	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	167:e84263d55307	2865
AnnaBridge	167:e84263d55307	2866	/**
AnnaBridge	167:e84263d55307	2867	* @}
AnnaBridge	167:e84263d55307	2868	*/
AnnaBridge	167:e84263d55307	2869
AnnaBridge	167:e84263d55307	2870	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	2871	}
AnnaBridge	167:e84263d55307	2872	#endif
AnnaBridge	167:e84263d55307	2873
AnnaBridge	167:e84263d55307	2874	#endif /* __STM32F4xx_LL_DMA_H */
AnnaBridge	167:e84263d55307	2875
AnnaBridge	167:e84263d55307	2876	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/