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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
182:a56a73fd2a6f 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f4xx_hal_irda.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of IRDA HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
AnnaBridge 167:e84263d55307 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F4xx_HAL_IRDA_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F4xx_HAL_IRDA_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f4xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup IRDA
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /** @defgroup IRDA_Exported_Types IRDA Exported Types
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59 /**
<> 144:ef7eb2e8f9f7 60 * @brief IRDA Init Structure definition
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 typedef struct
<> 144:ef7eb2e8f9f7 63 {
<> 144:ef7eb2e8f9f7 64 uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
<> 144:ef7eb2e8f9f7 65 The baud rate is computed using the following formula:
<> 144:ef7eb2e8f9f7 66 - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
<> 144:ef7eb2e8f9f7 67 - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref IRDA_Word_Length */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t Parity; /*!< Specifies the parity mode.
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref IRDA_Parity
<> 144:ef7eb2e8f9f7 74 @note When parity is enabled, the computed parity is inserted
<> 144:ef7eb2e8f9f7 75 at the MSB position of the transmitted data (9th bit when
<> 144:ef7eb2e8f9f7 76 the word length is set to 9 data bits; 8th bit when the
<> 144:ef7eb2e8f9f7 77 word length is set to 8 data bits). */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref IRDA_Mode */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint8_t Prescaler; /*!< Specifies the Prescaler */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t IrDAMode; /*!< Specifies the IrDA mode
<> 144:ef7eb2e8f9f7 85 This parameter can be a value of @ref IRDA_Low_Power */
<> 144:ef7eb2e8f9f7 86 }IRDA_InitTypeDef;
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /**
<> 144:ef7eb2e8f9f7 89 * @brief HAL IRDA State structures definition
<> 144:ef7eb2e8f9f7 90 * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
<> 144:ef7eb2e8f9f7 91 * - gState contains IRDA state information related to global Handle management
<> 144:ef7eb2e8f9f7 92 * and also information related to Tx operations.
<> 144:ef7eb2e8f9f7 93 * gState value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 94 * b7-b6 Error information
<> 144:ef7eb2e8f9f7 95 * 00 : No Error
<> 144:ef7eb2e8f9f7 96 * 01 : (Not Used)
<> 144:ef7eb2e8f9f7 97 * 10 : Timeout
<> 144:ef7eb2e8f9f7 98 * 11 : Error
<> 144:ef7eb2e8f9f7 99 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 100 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 101 * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
<> 144:ef7eb2e8f9f7 102 * b4-b3 (not used)
<> 144:ef7eb2e8f9f7 103 * xx : Should be set to 00
<> 144:ef7eb2e8f9f7 104 * b2 Intrinsic process state
<> 144:ef7eb2e8f9f7 105 * 0 : Ready
<> 144:ef7eb2e8f9f7 106 * 1 : Busy (IP busy with some configuration or internal operations)
<> 144:ef7eb2e8f9f7 107 * b1 (not used)
<> 144:ef7eb2e8f9f7 108 * x : Should be set to 0
<> 144:ef7eb2e8f9f7 109 * b0 Tx state
<> 144:ef7eb2e8f9f7 110 * 0 : Ready (no Tx operation ongoing)
<> 144:ef7eb2e8f9f7 111 * 1 : Busy (Tx operation ongoing)
<> 144:ef7eb2e8f9f7 112 * - RxState contains information related to Rx operations.
<> 144:ef7eb2e8f9f7 113 * RxState value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 114 * b7-b6 (not used)
<> 144:ef7eb2e8f9f7 115 * xx : Should be set to 00
<> 144:ef7eb2e8f9f7 116 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 117 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 118 * 1 : Init done (IP not initialized)
<> 144:ef7eb2e8f9f7 119 * b4-b2 (not used)
<> 144:ef7eb2e8f9f7 120 * xxx : Should be set to 000
<> 144:ef7eb2e8f9f7 121 * b1 Rx state
<> 144:ef7eb2e8f9f7 122 * 0 : Ready (no Rx operation ongoing)
<> 144:ef7eb2e8f9f7 123 * 1 : Busy (Rx operation ongoing)
<> 144:ef7eb2e8f9f7 124 * b0 (not used)
<> 144:ef7eb2e8f9f7 125 * x : Should be set to 0.
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 typedef enum
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
<> 144:ef7eb2e8f9f7 130 Value is allowed for gState and RxState */
<> 144:ef7eb2e8f9f7 131 HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
<> 144:ef7eb2e8f9f7 132 Value is allowed for gState and RxState */
<> 144:ef7eb2e8f9f7 133 HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
<> 144:ef7eb2e8f9f7 134 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 135 HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
<> 144:ef7eb2e8f9f7 136 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 137 HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
<> 144:ef7eb2e8f9f7 138 Value is allowed for RxState only */
<> 144:ef7eb2e8f9f7 139 HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
<> 144:ef7eb2e8f9f7 140 Not to be used for neither gState nor RxState.
<> 144:ef7eb2e8f9f7 141 Value is result of combination (Or) between gState and RxState values */
<> 144:ef7eb2e8f9f7 142 HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
<> 144:ef7eb2e8f9f7 143 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 144 HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
<> 144:ef7eb2e8f9f7 145 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 146 }HAL_IRDA_StateTypeDef;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /**
<> 144:ef7eb2e8f9f7 149 * @brief IRDA handle Structure definition
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 typedef struct
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 USART_TypeDef *Instance; /* USART registers base address */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 IRDA_InitTypeDef Init; /* IRDA communication parameters */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 uint16_t TxXferSize; /* IRDA Tx Transfer size */
<> 144:ef7eb2e8f9f7 160
AnnaBridge 167:e84263d55307 161 __IO uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 uint16_t RxXferSize; /* IRDA Rx Transfer size */
<> 144:ef7eb2e8f9f7 166
AnnaBridge 167:e84263d55307 167 __IO uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 HAL_LockTypeDef Lock; /* Locking object */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 __IO HAL_IRDA_StateTypeDef gState; /* IRDA state information related to global Handle management
<> 144:ef7eb2e8f9f7 176 and also related to Tx operations.
<> 144:ef7eb2e8f9f7 177 This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 __IO HAL_IRDA_StateTypeDef RxState; /* IRDA state information related to Rx operations.
<> 144:ef7eb2e8f9f7 180 This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 __IO uint32_t ErrorCode; /* IRDA Error code */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 }IRDA_HandleTypeDef;
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @}
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 190 /** @defgroup IRDA_Exported_Constants IRDA Exported constants
<> 144:ef7eb2e8f9f7 191 * @{
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193 /** @defgroup IRDA_Error_Code IRDA Error Code
<> 144:ef7eb2e8f9f7 194 * @brief IRDA Error Code
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
AnnaBridge 167:e84263d55307 197 #define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 167:e84263d55307 198 #define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
AnnaBridge 167:e84263d55307 199 #define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
AnnaBridge 167:e84263d55307 200 #define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
AnnaBridge 167:e84263d55307 201 #define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
AnnaBridge 167:e84263d55307 202 #define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @}
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /** @defgroup IRDA_Word_Length IRDA Word Length
<> 144:ef7eb2e8f9f7 208 * @{
<> 144:ef7eb2e8f9f7 209 */
AnnaBridge 167:e84263d55307 210 #define IRDA_WORDLENGTH_8B 0x00000000U
<> 144:ef7eb2e8f9f7 211 #define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @}
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /** @defgroup IRDA_Parity IRDA Parity
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
AnnaBridge 167:e84263d55307 219 #define IRDA_PARITY_NONE 0x00000000U
<> 144:ef7eb2e8f9f7 220 #define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
<> 144:ef7eb2e8f9f7 221 #define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @}
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /** @defgroup IRDA_Mode IRDA Transfer Mode
<> 144:ef7eb2e8f9f7 227 * @{
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 #define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
<> 144:ef7eb2e8f9f7 230 #define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
<> 144:ef7eb2e8f9f7 231 #define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @}
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /** @defgroup IRDA_Low_Power IRDA Low Power
<> 144:ef7eb2e8f9f7 237 * @{
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 #define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
AnnaBridge 167:e84263d55307 240 #define IRDA_POWERMODE_NORMAL 0x00000000U
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @}
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /** @defgroup IRDA_Flags IRDA Flags
<> 144:ef7eb2e8f9f7 246 * Elements values convention: 0xXXXX
<> 144:ef7eb2e8f9f7 247 * - 0xXXXX : Flag mask in the SR register
<> 144:ef7eb2e8f9f7 248 * @{
<> 144:ef7eb2e8f9f7 249 */
AnnaBridge 167:e84263d55307 250 #define IRDA_FLAG_TXE 0x00000080U
AnnaBridge 167:e84263d55307 251 #define IRDA_FLAG_TC 0x00000040U
AnnaBridge 167:e84263d55307 252 #define IRDA_FLAG_RXNE 0x00000020U
AnnaBridge 167:e84263d55307 253 #define IRDA_FLAG_IDLE 0x00000010U
AnnaBridge 167:e84263d55307 254 #define IRDA_FLAG_ORE 0x00000008U
AnnaBridge 167:e84263d55307 255 #define IRDA_FLAG_NE 0x00000004U
AnnaBridge 167:e84263d55307 256 #define IRDA_FLAG_FE 0x00000002U
AnnaBridge 167:e84263d55307 257 #define IRDA_FLAG_PE 0x00000001U
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @}
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
<> 144:ef7eb2e8f9f7 263 * Elements values convention: 0xY000XXXX
<> 144:ef7eb2e8f9f7 264 * - XXXX : Interrupt mask in the XX register
<> 144:ef7eb2e8f9f7 265 * - Y : Interrupt source register (2bits)
<> 144:ef7eb2e8f9f7 266 * - 01: CR1 register
<> 144:ef7eb2e8f9f7 267 * - 10: CR2 register
<> 144:ef7eb2e8f9f7 268 * - 11: CR3 register
<> 144:ef7eb2e8f9f7 269 * @{
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 #define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
<> 144:ef7eb2e8f9f7 272 #define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
<> 144:ef7eb2e8f9f7 273 #define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
<> 144:ef7eb2e8f9f7 274 #define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
<> 144:ef7eb2e8f9f7 275 #define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 #define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 #define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
<> 144:ef7eb2e8f9f7 280 #define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @}
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 290 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
<> 144:ef7eb2e8f9f7 291 * @{
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /** @brief Reset IRDA handle gstate & RxState
AnnaBridge 182:a56a73fd2a6f 295 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 296 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 297 * UART peripheral.
<> 144:ef7eb2e8f9f7 298 * @retval None
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
<> 144:ef7eb2e8f9f7 301 (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
<> 144:ef7eb2e8f9f7 302 (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
AnnaBridge 167:e84263d55307 303 } while(0U)
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /** @brief Flushs the IRDA DR register
AnnaBridge 182:a56a73fd2a6f 306 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 307 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 308 * UART peripheral.
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /** @brief Checks whether the specified IRDA flag is set or not.
AnnaBridge 182:a56a73fd2a6f 313 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 314 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 315 * UART peripheral.
AnnaBridge 182:a56a73fd2a6f 316 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 317 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 318 * @arg IRDA_FLAG_TXE: Transmit data register empty flag
<> 144:ef7eb2e8f9f7 319 * @arg IRDA_FLAG_TC: Transmission Complete flag
<> 144:ef7eb2e8f9f7 320 * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
<> 144:ef7eb2e8f9f7 321 * @arg IRDA_FLAG_IDLE: Idle Line detection flag
<> 144:ef7eb2e8f9f7 322 * @arg IRDA_FLAG_ORE: OverRun Error flag
<> 144:ef7eb2e8f9f7 323 * @arg IRDA_FLAG_NE: Noise Error flag
<> 144:ef7eb2e8f9f7 324 * @arg IRDA_FLAG_FE: Framing Error flag
<> 144:ef7eb2e8f9f7 325 * @arg IRDA_FLAG_PE: Parity Error flag
<> 144:ef7eb2e8f9f7 326 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @brief Clears the specified IRDA pending flag.
AnnaBridge 182:a56a73fd2a6f 331 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 332 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 333 * UART peripheral.
AnnaBridge 182:a56a73fd2a6f 334 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 335 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 336 * @arg IRDA_FLAG_TC: Transmission Complete flag.
<> 144:ef7eb2e8f9f7 337 * @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
<> 144:ef7eb2e8f9f7 338 *
<> 144:ef7eb2e8f9f7 339 * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
<> 144:ef7eb2e8f9f7 340 * error) and IDLE (Idle line detected) flags are cleared by software
<> 144:ef7eb2e8f9f7 341 * sequence: a read operation to USART_SR register followed by a read
<> 144:ef7eb2e8f9f7 342 * operation to USART_DR register.
<> 144:ef7eb2e8f9f7 343 * @note RXNE flag can be also cleared by a read to the USART_DR register.
<> 144:ef7eb2e8f9f7 344 * @note TC flag can be also cleared by software sequence: a read operation to
<> 144:ef7eb2e8f9f7 345 * USART_SR register followed by a write operation to USART_DR register.
<> 144:ef7eb2e8f9f7 346 * @note TXE flag is cleared only by a write to the USART_DR register.
<> 144:ef7eb2e8f9f7 347 *
<> 144:ef7eb2e8f9f7 348 * @retval None
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /** @brief Clear the IRDA PE pending flag.
AnnaBridge 182:a56a73fd2a6f 353 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 354 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 355 * UART peripheral.
<> 144:ef7eb2e8f9f7 356 * @retval None
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 359 do{ \
<> 144:ef7eb2e8f9f7 360 __IO uint32_t tmpreg = 0x00U; \
<> 144:ef7eb2e8f9f7 361 tmpreg = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 362 UNUSED(tmpreg); \
AnnaBridge 167:e84263d55307 363 } while(0U)
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @brief Clear the IRDA FE pending flag.
AnnaBridge 182:a56a73fd2a6f 366 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 367 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 368 * UART peripheral.
<> 144:ef7eb2e8f9f7 369 * @retval None
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /** @brief Clear the IRDA NE pending flag.
AnnaBridge 182:a56a73fd2a6f 374 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 375 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 376 * UART peripheral.
<> 144:ef7eb2e8f9f7 377 * @retval None
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /** @brief Clear the IRDA ORE pending flag.
AnnaBridge 182:a56a73fd2a6f 382 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 383 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 384 * UART peripheral.
<> 144:ef7eb2e8f9f7 385 * @retval None
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /** @brief Clear the IRDA IDLE pending flag.
AnnaBridge 182:a56a73fd2a6f 390 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 391 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 392 * UART peripheral.
<> 144:ef7eb2e8f9f7 393 * @retval None
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /** @brief Enables or disables the specified IRDA interrupt.
AnnaBridge 182:a56a73fd2a6f 398 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 399 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 400 * UART peripheral.
AnnaBridge 182:a56a73fd2a6f 401 * @param __INTERRUPT__ specifies the IRDA interrupt source to check.
<> 144:ef7eb2e8f9f7 402 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 403 * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
<> 144:ef7eb2e8f9f7 404 * @arg IRDA_IT_TC: Transmission complete interrupt
<> 144:ef7eb2e8f9f7 405 * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
<> 144:ef7eb2e8f9f7 406 * @arg IRDA_IT_IDLE: Idle line detection interrupt
<> 144:ef7eb2e8f9f7 407 * @arg IRDA_IT_PE: Parity Error interrupt
<> 144:ef7eb2e8f9f7 408 * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 409 * @retval None
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
<> 144:ef7eb2e8f9f7 412 (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
<> 144:ef7eb2e8f9f7 413 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
<> 144:ef7eb2e8f9f7 414 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
<> 144:ef7eb2e8f9f7 415 (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
<> 144:ef7eb2e8f9f7 416 ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /** @brief Checks whether the specified IRDA interrupt has occurred or not.
AnnaBridge 182:a56a73fd2a6f 419 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 420 * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
<> 144:ef7eb2e8f9f7 421 * UART peripheral.
AnnaBridge 182:a56a73fd2a6f 422 * @param __IT__ specifies the IRDA interrupt source to check.
<> 144:ef7eb2e8f9f7 423 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 424 * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
<> 144:ef7eb2e8f9f7 425 * @arg IRDA_IT_TC: Transmission complete interrupt
<> 144:ef7eb2e8f9f7 426 * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
<> 144:ef7eb2e8f9f7 427 * @arg IRDA_IT_IDLE: Idle line detection interrupt
<> 144:ef7eb2e8f9f7 428 * @arg USART_IT_ERR: Error interrupt
<> 144:ef7eb2e8f9f7 429 * @arg IRDA_IT_PE: Parity Error interrupt
<> 144:ef7eb2e8f9f7 430 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
<> 144:ef7eb2e8f9f7 433 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /** @brief Macro to enable the IRDA's one bit sample method
AnnaBridge 182:a56a73fd2a6f 436 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 437 * @retval None
<> 144:ef7eb2e8f9f7 438 */
<> 144:ef7eb2e8f9f7 439 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /** @brief Macro to disable the IRDA's one bit sample method
AnnaBridge 182:a56a73fd2a6f 442 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 443 * @retval None
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /** @brief Enable UART/USART associated to IRDA Handle
AnnaBridge 182:a56a73fd2a6f 448 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 449 * IRDA Handle selects the USARTx or UARTy peripheral
<> 144:ef7eb2e8f9f7 450 * (USART,UART availability and x,y values depending on device).
<> 144:ef7eb2e8f9f7 451 * @retval None
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /** @brief Disable UART/USART associated to IRDA Handle
AnnaBridge 182:a56a73fd2a6f 456 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 457 * IRDA Handle selects the USARTx or UARTy peripheral
<> 144:ef7eb2e8f9f7 458 * (USART,UART availability and x,y values depending on device).
<> 144:ef7eb2e8f9f7 459 * @retval None
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 #define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /**
<> 144:ef7eb2e8f9f7 464 * @}
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 468 /** @addtogroup IRDA_Exported_Functions
<> 144:ef7eb2e8f9f7 469 * @{
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /** @addtogroup IRDA_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 473 * @{
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 476 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 477 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 478 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 479 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @}
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /** @addtogroup IRDA_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 485 * @{
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487 /* IO operation functions *******************************************************/
<> 144:ef7eb2e8f9f7 488 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 489 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 490 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 491 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 492 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 493 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 494 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 495 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 496 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
AnnaBridge 167:e84263d55307 497 /* Transfer Abort functions */
AnnaBridge 167:e84263d55307 498 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
AnnaBridge 167:e84263d55307 499 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
AnnaBridge 167:e84263d55307 500 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
AnnaBridge 167:e84263d55307 501 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
AnnaBridge 167:e84263d55307 502 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
AnnaBridge 167:e84263d55307 503 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 506 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 507 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 508 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 509 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 510 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
AnnaBridge 167:e84263d55307 511 void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
AnnaBridge 167:e84263d55307 512 void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
AnnaBridge 167:e84263d55307 513 void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 514 /**
<> 144:ef7eb2e8f9f7 515 * @}
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /** @addtogroup IRDA_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 519 * @{
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 /* Peripheral State functions **************************************************/
<> 144:ef7eb2e8f9f7 522 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 523 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 524 /**
<> 144:ef7eb2e8f9f7 525 * @}
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /**
<> 144:ef7eb2e8f9f7 529 * @}
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 533 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 534 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 535 /** @defgroup IRDA_Private_Constants IRDA Private Constants
<> 144:ef7eb2e8f9f7 536 * @{
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /** @brief IRDA interruptions flag mask
<> 144:ef7eb2e8f9f7 540 *
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542 #define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
<> 144:ef7eb2e8f9f7 543 USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 #define IRDA_CR1_REG_INDEX 1U
<> 144:ef7eb2e8f9f7 546 #define IRDA_CR2_REG_INDEX 2U
<> 144:ef7eb2e8f9f7 547 #define IRDA_CR3_REG_INDEX 3U
<> 144:ef7eb2e8f9f7 548 /**
<> 144:ef7eb2e8f9f7 549 * @}
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Private macros --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 553 /** @defgroup IRDA_Private_Macros IRDA Private Macros
<> 144:ef7eb2e8f9f7 554 * @{
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556 #define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
<> 144:ef7eb2e8f9f7 557 ((LENGTH) == IRDA_WORDLENGTH_9B))
<> 144:ef7eb2e8f9f7 558 #define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
<> 144:ef7eb2e8f9f7 559 ((PARITY) == IRDA_PARITY_EVEN) || \
<> 144:ef7eb2e8f9f7 560 ((PARITY) == IRDA_PARITY_ODD))
AnnaBridge 167:e84263d55307 561 #define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
<> 144:ef7eb2e8f9f7 562 #define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
<> 144:ef7eb2e8f9f7 563 ((MODE) == IRDA_POWERMODE_NORMAL))
<> 144:ef7eb2e8f9f7 564 #define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 #define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
<> 144:ef7eb2e8f9f7 567 #define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
<> 144:ef7eb2e8f9f7 568 #define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
<> 144:ef7eb2e8f9f7 569 /* UART BRR = mantissa + overflow + fraction
<> 144:ef7eb2e8f9f7 570 = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
<> 144:ef7eb2e8f9f7 571 #define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
<> 144:ef7eb2e8f9f7 572 (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
<> 144:ef7eb2e8f9f7 573 (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /**
<> 144:ef7eb2e8f9f7 576 * @}
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 580 /** @defgroup IRDA_Private_Functions IRDA Private Functions
<> 144:ef7eb2e8f9f7 581 * @{
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /**
<> 144:ef7eb2e8f9f7 585 * @}
<> 144:ef7eb2e8f9f7 586 */
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /**
<> 144:ef7eb2e8f9f7 589 * @}
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /**
<> 144:ef7eb2e8f9f7 593 * @}
<> 144:ef7eb2e8f9f7 594 */
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598 #endif
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 #endif /* __STM32F4xx_HAL_IRDA_H */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/