mbed official
mbed library sources. Supersedes mbed-src.
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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 182:a56a73fd2a6f
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 19:112740acecfa | 1 | /** |
| mbed_official | 19:112740acecfa | 2 | ****************************************************************************** |
| mbed_official | 19:112740acecfa | 3 | * @file stm32f469xx.h |
| mbed_official | 19:112740acecfa | 4 | * @author MCD Application Team |
| mbed_official | 19:112740acecfa | 5 | * @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File. |
| mbed_official | 19:112740acecfa | 6 | * |
| mbed_official | 19:112740acecfa | 7 | * This file contains: |
| mbed_official | 19:112740acecfa | 8 | * - Data structures and the address mapping for all peripherals |
| <> | 144:ef7eb2e8f9f7 | 9 | * - peripherals registers declarations and bits definition |
| <> | 144:ef7eb2e8f9f7 | 10 | * - Macros to access peripheral's registers hardware |
| mbed_official | 19:112740acecfa | 11 | * |
| mbed_official | 19:112740acecfa | 12 | ****************************************************************************** |
| mbed_official | 19:112740acecfa | 13 | * @attention |
| mbed_official | 19:112740acecfa | 14 | * |
| AnnaBridge | 167:e84263d55307 | 15 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| mbed_official | 19:112740acecfa | 16 | * |
| mbed_official | 19:112740acecfa | 17 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 19:112740acecfa | 18 | * are permitted provided that the following conditions are met: |
| mbed_official | 19:112740acecfa | 19 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 19:112740acecfa | 20 | * this list of conditions and the following disclaimer. |
| mbed_official | 19:112740acecfa | 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 19:112740acecfa | 22 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 19:112740acecfa | 23 | * and/or other materials provided with the distribution. |
| mbed_official | 19:112740acecfa | 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 19:112740acecfa | 25 | * may be used to endorse or promote products derived from this software |
| mbed_official | 19:112740acecfa | 26 | * without specific prior written permission. |
| mbed_official | 19:112740acecfa | 27 | * |
| mbed_official | 19:112740acecfa | 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 19:112740acecfa | 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 19:112740acecfa | 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 19:112740acecfa | 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 19:112740acecfa | 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 19:112740acecfa | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 19:112740acecfa | 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 19:112740acecfa | 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 19:112740acecfa | 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 19:112740acecfa | 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 19:112740acecfa | 38 | * |
| mbed_official | 19:112740acecfa | 39 | ****************************************************************************** |
| mbed_official | 19:112740acecfa | 40 | */ |
| mbed_official | 19:112740acecfa | 41 | |
| mbed_official | 19:112740acecfa | 42 | /** @addtogroup CMSIS_Device |
| mbed_official | 19:112740acecfa | 43 | * @{ |
| mbed_official | 19:112740acecfa | 44 | */ |
| mbed_official | 19:112740acecfa | 45 | |
| mbed_official | 19:112740acecfa | 46 | /** @addtogroup stm32f469xx |
| mbed_official | 19:112740acecfa | 47 | * @{ |
| mbed_official | 19:112740acecfa | 48 | */ |
| mbed_official | 19:112740acecfa | 49 | |
| mbed_official | 19:112740acecfa | 50 | #ifndef __STM32F469xx_H |
| mbed_official | 19:112740acecfa | 51 | #define __STM32F469xx_H |
| mbed_official | 19:112740acecfa | 52 | |
| mbed_official | 19:112740acecfa | 53 | #ifdef __cplusplus |
| mbed_official | 19:112740acecfa | 54 | extern "C" { |
| mbed_official | 19:112740acecfa | 55 | #endif /* __cplusplus */ |
| AnnaBridge | 167:e84263d55307 | 56 | |
| mbed_official | 19:112740acecfa | 57 | /** @addtogroup Configuration_section_for_CMSIS |
| mbed_official | 19:112740acecfa | 58 | * @{ |
| mbed_official | 19:112740acecfa | 59 | */ |
| mbed_official | 19:112740acecfa | 60 | |
| mbed_official | 19:112740acecfa | 61 | /** |
| mbed_official | 19:112740acecfa | 62 | * @brief Configuration of the Cortex-M4 Processor and Core Peripherals |
| mbed_official | 19:112740acecfa | 63 | */ |
| <> | 144:ef7eb2e8f9f7 | 64 | #define __CM4_REV 0x0001U /*!< Core revision r0p1 */ |
| <> | 144:ef7eb2e8f9f7 | 65 | #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ |
| <> | 144:ef7eb2e8f9f7 | 66 | #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ |
| <> | 144:ef7eb2e8f9f7 | 67 | #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ |
| AnnaBridge | 182:a56a73fd2a6f | 68 | /* MBED */ |
| <> | 144:ef7eb2e8f9f7 | 69 | #ifndef __FPU_PRESENT |
| <> | 144:ef7eb2e8f9f7 | 70 | #define __FPU_PRESENT 1U /*!< FPU present */ |
| <> | 144:ef7eb2e8f9f7 | 71 | #endif /* __FPU_PRESENT */ |
| AnnaBridge | 182:a56a73fd2a6f | 72 | /* MBED */ |
| mbed_official | 19:112740acecfa | 73 | |
| mbed_official | 19:112740acecfa | 74 | /** |
| mbed_official | 19:112740acecfa | 75 | * @} |
| mbed_official | 19:112740acecfa | 76 | */ |
| AnnaBridge | 167:e84263d55307 | 77 | |
| mbed_official | 19:112740acecfa | 78 | /** @addtogroup Peripheral_interrupt_number_definition |
| mbed_official | 19:112740acecfa | 79 | * @{ |
| mbed_official | 19:112740acecfa | 80 | */ |
| mbed_official | 19:112740acecfa | 81 | |
| mbed_official | 19:112740acecfa | 82 | /** |
| mbed_official | 19:112740acecfa | 83 | * @brief STM32F4XX Interrupt Number Definition, according to the selected device |
| mbed_official | 19:112740acecfa | 84 | * in @ref Library_configuration_section |
| mbed_official | 19:112740acecfa | 85 | */ |
| mbed_official | 19:112740acecfa | 86 | typedef enum |
| mbed_official | 19:112740acecfa | 87 | { |
| mbed_official | 19:112740acecfa | 88 | /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ |
| mbed_official | 19:112740acecfa | 89 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| mbed_official | 19:112740acecfa | 90 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
| mbed_official | 19:112740acecfa | 91 | BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
| mbed_official | 19:112740acecfa | 92 | UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
| mbed_official | 19:112740acecfa | 93 | SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
| mbed_official | 19:112740acecfa | 94 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
| mbed_official | 19:112740acecfa | 95 | PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
| mbed_official | 19:112740acecfa | 96 | SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
| mbed_official | 19:112740acecfa | 97 | /****** STM32 specific Interrupt Numbers **********************************************************************/ |
| mbed_official | 19:112740acecfa | 98 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| mbed_official | 19:112740acecfa | 99 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
| mbed_official | 19:112740acecfa | 100 | TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ |
| mbed_official | 19:112740acecfa | 101 | RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ |
| mbed_official | 19:112740acecfa | 102 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| mbed_official | 19:112740acecfa | 103 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| mbed_official | 19:112740acecfa | 104 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| mbed_official | 19:112740acecfa | 105 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| mbed_official | 19:112740acecfa | 106 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
| mbed_official | 19:112740acecfa | 107 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| mbed_official | 19:112740acecfa | 108 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| mbed_official | 19:112740acecfa | 109 | DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ |
| mbed_official | 19:112740acecfa | 110 | DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ |
| mbed_official | 19:112740acecfa | 111 | DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ |
| mbed_official | 19:112740acecfa | 112 | DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ |
| mbed_official | 19:112740acecfa | 113 | DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ |
| mbed_official | 19:112740acecfa | 114 | DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ |
| mbed_official | 19:112740acecfa | 115 | DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ |
| mbed_official | 19:112740acecfa | 116 | ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ |
| mbed_official | 19:112740acecfa | 117 | CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ |
| mbed_official | 19:112740acecfa | 118 | CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ |
| mbed_official | 19:112740acecfa | 119 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| mbed_official | 19:112740acecfa | 120 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| mbed_official | 19:112740acecfa | 121 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 19:112740acecfa | 122 | TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ |
| mbed_official | 19:112740acecfa | 123 | TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ |
| mbed_official | 19:112740acecfa | 124 | TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ |
| mbed_official | 19:112740acecfa | 125 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 19:112740acecfa | 126 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 19:112740acecfa | 127 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 19:112740acecfa | 128 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| mbed_official | 19:112740acecfa | 129 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 19:112740acecfa | 130 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 19:112740acecfa | 131 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 132 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| mbed_official | 19:112740acecfa | 133 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 19:112740acecfa | 134 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| mbed_official | 19:112740acecfa | 135 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 19:112740acecfa | 136 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 19:112740acecfa | 137 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| mbed_official | 19:112740acecfa | 138 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 19:112740acecfa | 139 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 140 | OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ |
| mbed_official | 19:112740acecfa | 141 | TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ |
| mbed_official | 19:112740acecfa | 142 | TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ |
| mbed_official | 19:112740acecfa | 143 | TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ |
| mbed_official | 19:112740acecfa | 144 | TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */ |
| mbed_official | 19:112740acecfa | 145 | DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ |
| mbed_official | 19:112740acecfa | 146 | FMC_IRQn = 48, /*!< FMC global Interrupt */ |
| mbed_official | 19:112740acecfa | 147 | SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
| mbed_official | 19:112740acecfa | 148 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| mbed_official | 19:112740acecfa | 149 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| mbed_official | 19:112740acecfa | 150 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| mbed_official | 19:112740acecfa | 151 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| mbed_official | 19:112740acecfa | 152 | TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ |
| mbed_official | 19:112740acecfa | 153 | TIM7_IRQn = 55, /*!< TIM7 global interrupt */ |
| mbed_official | 19:112740acecfa | 154 | DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ |
| mbed_official | 19:112740acecfa | 155 | DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ |
| mbed_official | 19:112740acecfa | 156 | DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ |
| mbed_official | 19:112740acecfa | 157 | DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ |
| mbed_official | 19:112740acecfa | 158 | DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ |
| mbed_official | 19:112740acecfa | 159 | ETH_IRQn = 61, /*!< Ethernet global Interrupt */ |
| mbed_official | 19:112740acecfa | 160 | ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ |
| mbed_official | 19:112740acecfa | 161 | CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ |
| mbed_official | 19:112740acecfa | 162 | CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ |
| mbed_official | 19:112740acecfa | 163 | CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ |
| mbed_official | 19:112740acecfa | 164 | CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ |
| mbed_official | 19:112740acecfa | 165 | OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ |
| mbed_official | 19:112740acecfa | 166 | DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ |
| mbed_official | 19:112740acecfa | 167 | DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ |
| mbed_official | 19:112740acecfa | 168 | DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ |
| mbed_official | 19:112740acecfa | 169 | USART6_IRQn = 71, /*!< USART6 global interrupt */ |
| mbed_official | 19:112740acecfa | 170 | I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ |
| mbed_official | 19:112740acecfa | 171 | I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ |
| mbed_official | 19:112740acecfa | 172 | OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ |
| mbed_official | 19:112740acecfa | 173 | OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ |
| mbed_official | 19:112740acecfa | 174 | OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ |
| mbed_official | 19:112740acecfa | 175 | OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ |
| mbed_official | 19:112740acecfa | 176 | DCMI_IRQn = 78, /*!< DCMI global interrupt */ |
| mbed_official | 19:112740acecfa | 177 | HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ |
| mbed_official | 19:112740acecfa | 178 | FPU_IRQn = 81, /*!< FPU global interrupt */ |
| mbed_official | 19:112740acecfa | 179 | UART7_IRQn = 82, /*!< UART7 global interrupt */ |
| mbed_official | 19:112740acecfa | 180 | UART8_IRQn = 83, /*!< UART8 global interrupt */ |
| mbed_official | 19:112740acecfa | 181 | SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ |
| mbed_official | 19:112740acecfa | 182 | SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ |
| mbed_official | 19:112740acecfa | 183 | SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ |
| mbed_official | 19:112740acecfa | 184 | SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ |
| mbed_official | 19:112740acecfa | 185 | LTDC_IRQn = 88, /*!< LTDC global Interrupt */ |
| mbed_official | 19:112740acecfa | 186 | LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ |
| mbed_official | 19:112740acecfa | 187 | DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ |
| mbed_official | 19:112740acecfa | 188 | QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */ |
| mbed_official | 19:112740acecfa | 189 | DSI_IRQn = 92 /*!< DSI global Interrupt */ |
| mbed_official | 19:112740acecfa | 190 | } IRQn_Type; |
| mbed_official | 19:112740acecfa | 191 | |
| mbed_official | 19:112740acecfa | 192 | /** |
| mbed_official | 19:112740acecfa | 193 | * @} |
| mbed_official | 19:112740acecfa | 194 | */ |
| mbed_official | 19:112740acecfa | 195 | |
| mbed_official | 19:112740acecfa | 196 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
| mbed_official | 19:112740acecfa | 197 | #include "system_stm32f4xx.h" |
| mbed_official | 19:112740acecfa | 198 | #include <stdint.h> |
| mbed_official | 19:112740acecfa | 199 | |
| mbed_official | 19:112740acecfa | 200 | /** @addtogroup Peripheral_registers_structures |
| mbed_official | 19:112740acecfa | 201 | * @{ |
| mbed_official | 19:112740acecfa | 202 | */ |
| mbed_official | 19:112740acecfa | 203 | |
| mbed_official | 19:112740acecfa | 204 | /** |
| mbed_official | 19:112740acecfa | 205 | * @brief Analog to Digital Converter |
| mbed_official | 19:112740acecfa | 206 | */ |
| mbed_official | 19:112740acecfa | 207 | |
| mbed_official | 19:112740acecfa | 208 | typedef struct |
| mbed_official | 19:112740acecfa | 209 | { |
| mbed_official | 19:112740acecfa | 210 | __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ |
| AnnaBridge | 167:e84263d55307 | 211 | __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 212 | __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 213 | __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 214 | __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 215 | __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 216 | __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 217 | __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 218 | __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 219 | __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ |
| mbed_official | 19:112740acecfa | 220 | __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ |
| mbed_official | 19:112740acecfa | 221 | __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ |
| mbed_official | 19:112740acecfa | 222 | __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ |
| mbed_official | 19:112740acecfa | 223 | __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ |
| mbed_official | 19:112740acecfa | 224 | __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ |
| mbed_official | 19:112740acecfa | 225 | __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ |
| mbed_official | 19:112740acecfa | 226 | __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ |
| mbed_official | 19:112740acecfa | 227 | __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ |
| mbed_official | 19:112740acecfa | 228 | __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ |
| mbed_official | 19:112740acecfa | 229 | __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ |
| mbed_official | 19:112740acecfa | 230 | } ADC_TypeDef; |
| mbed_official | 19:112740acecfa | 231 | |
| mbed_official | 19:112740acecfa | 232 | typedef struct |
| mbed_official | 19:112740acecfa | 233 | { |
| mbed_official | 19:112740acecfa | 234 | __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ |
| mbed_official | 19:112740acecfa | 235 | __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ |
| mbed_official | 19:112740acecfa | 236 | __IO uint32_t CDR; /*!< ADC common regular data register for dual |
| mbed_official | 19:112740acecfa | 237 | AND triple modes, Address offset: ADC1 base address + 0x308 */ |
| mbed_official | 19:112740acecfa | 238 | } ADC_Common_TypeDef; |
| mbed_official | 19:112740acecfa | 239 | |
| mbed_official | 19:112740acecfa | 240 | |
| mbed_official | 19:112740acecfa | 241 | /** |
| mbed_official | 19:112740acecfa | 242 | * @brief Controller Area Network TxMailBox |
| mbed_official | 19:112740acecfa | 243 | */ |
| mbed_official | 19:112740acecfa | 244 | |
| mbed_official | 19:112740acecfa | 245 | typedef struct |
| mbed_official | 19:112740acecfa | 246 | { |
| mbed_official | 19:112740acecfa | 247 | __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ |
| mbed_official | 19:112740acecfa | 248 | __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ |
| mbed_official | 19:112740acecfa | 249 | __IO uint32_t TDLR; /*!< CAN mailbox data low register */ |
| mbed_official | 19:112740acecfa | 250 | __IO uint32_t TDHR; /*!< CAN mailbox data high register */ |
| mbed_official | 19:112740acecfa | 251 | } CAN_TxMailBox_TypeDef; |
| mbed_official | 19:112740acecfa | 252 | |
| mbed_official | 19:112740acecfa | 253 | /** |
| mbed_official | 19:112740acecfa | 254 | * @brief Controller Area Network FIFOMailBox |
| mbed_official | 19:112740acecfa | 255 | */ |
| mbed_official | 19:112740acecfa | 256 | |
| mbed_official | 19:112740acecfa | 257 | typedef struct |
| mbed_official | 19:112740acecfa | 258 | { |
| mbed_official | 19:112740acecfa | 259 | __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ |
| mbed_official | 19:112740acecfa | 260 | __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ |
| mbed_official | 19:112740acecfa | 261 | __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ |
| mbed_official | 19:112740acecfa | 262 | __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ |
| mbed_official | 19:112740acecfa | 263 | } CAN_FIFOMailBox_TypeDef; |
| mbed_official | 19:112740acecfa | 264 | |
| mbed_official | 19:112740acecfa | 265 | /** |
| mbed_official | 19:112740acecfa | 266 | * @brief Controller Area Network FilterRegister |
| mbed_official | 19:112740acecfa | 267 | */ |
| mbed_official | 19:112740acecfa | 268 | |
| mbed_official | 19:112740acecfa | 269 | typedef struct |
| mbed_official | 19:112740acecfa | 270 | { |
| mbed_official | 19:112740acecfa | 271 | __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ |
| mbed_official | 19:112740acecfa | 272 | __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ |
| mbed_official | 19:112740acecfa | 273 | } CAN_FilterRegister_TypeDef; |
| mbed_official | 19:112740acecfa | 274 | |
| mbed_official | 19:112740acecfa | 275 | /** |
| mbed_official | 19:112740acecfa | 276 | * @brief Controller Area Network |
| mbed_official | 19:112740acecfa | 277 | */ |
| mbed_official | 19:112740acecfa | 278 | |
| mbed_official | 19:112740acecfa | 279 | typedef struct |
| mbed_official | 19:112740acecfa | 280 | { |
| mbed_official | 19:112740acecfa | 281 | __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 282 | __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 283 | __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 284 | __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 285 | __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 286 | __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 287 | __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 288 | __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 289 | uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
| mbed_official | 19:112740acecfa | 290 | CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
| mbed_official | 19:112740acecfa | 291 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
| mbed_official | 19:112740acecfa | 292 | uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
| mbed_official | 19:112740acecfa | 293 | __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
| mbed_official | 19:112740acecfa | 294 | __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
| mbed_official | 19:112740acecfa | 295 | uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
| mbed_official | 19:112740acecfa | 296 | __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
| mbed_official | 19:112740acecfa | 297 | uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
| mbed_official | 19:112740acecfa | 298 | __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
| mbed_official | 19:112740acecfa | 299 | uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
| mbed_official | 19:112740acecfa | 300 | __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
| mbed_official | 19:112740acecfa | 301 | uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
| mbed_official | 19:112740acecfa | 302 | CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ |
| mbed_official | 19:112740acecfa | 303 | } CAN_TypeDef; |
| mbed_official | 19:112740acecfa | 304 | |
| mbed_official | 19:112740acecfa | 305 | /** |
| mbed_official | 19:112740acecfa | 306 | * @brief CRC calculation unit |
| mbed_official | 19:112740acecfa | 307 | */ |
| mbed_official | 19:112740acecfa | 308 | |
| mbed_official | 19:112740acecfa | 309 | typedef struct |
| mbed_official | 19:112740acecfa | 310 | { |
| mbed_official | 19:112740acecfa | 311 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 312 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 313 | uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
| mbed_official | 19:112740acecfa | 314 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| mbed_official | 19:112740acecfa | 315 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 316 | } CRC_TypeDef; |
| mbed_official | 19:112740acecfa | 317 | |
| mbed_official | 19:112740acecfa | 318 | /** |
| mbed_official | 19:112740acecfa | 319 | * @brief Digital to Analog Converter |
| mbed_official | 19:112740acecfa | 320 | */ |
| mbed_official | 19:112740acecfa | 321 | |
| mbed_official | 19:112740acecfa | 322 | typedef struct |
| mbed_official | 19:112740acecfa | 323 | { |
| mbed_official | 19:112740acecfa | 324 | __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 325 | __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 326 | __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 327 | __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 328 | __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 329 | __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 330 | __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 331 | __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 332 | __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 333 | __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ |
| mbed_official | 19:112740acecfa | 334 | __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ |
| mbed_official | 19:112740acecfa | 335 | __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ |
| mbed_official | 19:112740acecfa | 336 | __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ |
| mbed_official | 19:112740acecfa | 337 | __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ |
| mbed_official | 19:112740acecfa | 338 | } DAC_TypeDef; |
| mbed_official | 19:112740acecfa | 339 | |
| mbed_official | 19:112740acecfa | 340 | /** |
| mbed_official | 19:112740acecfa | 341 | * @brief Debug MCU |
| mbed_official | 19:112740acecfa | 342 | */ |
| mbed_official | 19:112740acecfa | 343 | |
| mbed_official | 19:112740acecfa | 344 | typedef struct |
| mbed_official | 19:112740acecfa | 345 | { |
| mbed_official | 19:112740acecfa | 346 | __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 347 | __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 348 | __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 349 | __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 350 | }DBGMCU_TypeDef; |
| mbed_official | 19:112740acecfa | 351 | |
| mbed_official | 19:112740acecfa | 352 | /** |
| mbed_official | 19:112740acecfa | 353 | * @brief DCMI |
| mbed_official | 19:112740acecfa | 354 | */ |
| mbed_official | 19:112740acecfa | 355 | |
| mbed_official | 19:112740acecfa | 356 | typedef struct |
| mbed_official | 19:112740acecfa | 357 | { |
| mbed_official | 19:112740acecfa | 358 | __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 359 | __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 360 | __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 361 | __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 362 | __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 363 | __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 364 | __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 365 | __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 366 | __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 367 | __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ |
| mbed_official | 19:112740acecfa | 368 | __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ |
| mbed_official | 19:112740acecfa | 369 | } DCMI_TypeDef; |
| mbed_official | 19:112740acecfa | 370 | |
| mbed_official | 19:112740acecfa | 371 | /** |
| mbed_official | 19:112740acecfa | 372 | * @brief DMA Controller |
| mbed_official | 19:112740acecfa | 373 | */ |
| mbed_official | 19:112740acecfa | 374 | |
| mbed_official | 19:112740acecfa | 375 | typedef struct |
| mbed_official | 19:112740acecfa | 376 | { |
| mbed_official | 19:112740acecfa | 377 | __IO uint32_t CR; /*!< DMA stream x configuration register */ |
| mbed_official | 19:112740acecfa | 378 | __IO uint32_t NDTR; /*!< DMA stream x number of data register */ |
| mbed_official | 19:112740acecfa | 379 | __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ |
| mbed_official | 19:112740acecfa | 380 | __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ |
| mbed_official | 19:112740acecfa | 381 | __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ |
| mbed_official | 19:112740acecfa | 382 | __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ |
| mbed_official | 19:112740acecfa | 383 | } DMA_Stream_TypeDef; |
| mbed_official | 19:112740acecfa | 384 | |
| mbed_official | 19:112740acecfa | 385 | typedef struct |
| mbed_official | 19:112740acecfa | 386 | { |
| mbed_official | 19:112740acecfa | 387 | __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 388 | __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 389 | __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 390 | __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 391 | } DMA_TypeDef; |
| mbed_official | 19:112740acecfa | 392 | |
| mbed_official | 19:112740acecfa | 393 | /** |
| mbed_official | 19:112740acecfa | 394 | * @brief DMA2D Controller |
| mbed_official | 19:112740acecfa | 395 | */ |
| mbed_official | 19:112740acecfa | 396 | |
| mbed_official | 19:112740acecfa | 397 | typedef struct |
| mbed_official | 19:112740acecfa | 398 | { |
| mbed_official | 19:112740acecfa | 399 | __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 400 | __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 401 | __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 402 | __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 403 | __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 404 | __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 405 | __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 406 | __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 407 | __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 408 | __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ |
| mbed_official | 19:112740acecfa | 409 | __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ |
| mbed_official | 19:112740acecfa | 410 | __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ |
| mbed_official | 19:112740acecfa | 411 | __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ |
| mbed_official | 19:112740acecfa | 412 | __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ |
| mbed_official | 19:112740acecfa | 413 | __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ |
| mbed_official | 19:112740acecfa | 414 | __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ |
| mbed_official | 19:112740acecfa | 415 | __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ |
| mbed_official | 19:112740acecfa | 416 | __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ |
| mbed_official | 19:112740acecfa | 417 | __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ |
| mbed_official | 19:112740acecfa | 418 | __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ |
| mbed_official | 19:112740acecfa | 419 | uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ |
| mbed_official | 19:112740acecfa | 420 | __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ |
| mbed_official | 19:112740acecfa | 421 | __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ |
| mbed_official | 19:112740acecfa | 422 | } DMA2D_TypeDef; |
| mbed_official | 19:112740acecfa | 423 | |
| mbed_official | 19:112740acecfa | 424 | /** |
| mbed_official | 19:112740acecfa | 425 | * @brief DSI Controller |
| mbed_official | 19:112740acecfa | 426 | */ |
| mbed_official | 19:112740acecfa | 427 | |
| mbed_official | 19:112740acecfa | 428 | typedef struct |
| mbed_official | 19:112740acecfa | 429 | { |
| AnnaBridge | 167:e84263d55307 | 430 | __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ |
| AnnaBridge | 167:e84263d55307 | 431 | __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ |
| AnnaBridge | 167:e84263d55307 | 432 | __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ |
| AnnaBridge | 167:e84263d55307 | 433 | __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ |
| AnnaBridge | 167:e84263d55307 | 434 | __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ |
| AnnaBridge | 167:e84263d55307 | 435 | __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ |
| AnnaBridge | 167:e84263d55307 | 436 | __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ |
| AnnaBridge | 167:e84263d55307 | 437 | uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ |
| AnnaBridge | 167:e84263d55307 | 438 | __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ |
| AnnaBridge | 167:e84263d55307 | 439 | __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ |
| AnnaBridge | 167:e84263d55307 | 440 | __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ |
| AnnaBridge | 167:e84263d55307 | 441 | __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ |
| AnnaBridge | 167:e84263d55307 | 442 | __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ |
| AnnaBridge | 167:e84263d55307 | 443 | __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ |
| AnnaBridge | 167:e84263d55307 | 444 | __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ |
| AnnaBridge | 167:e84263d55307 | 445 | __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ |
| AnnaBridge | 167:e84263d55307 | 446 | __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ |
| AnnaBridge | 167:e84263d55307 | 447 | __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ |
| AnnaBridge | 167:e84263d55307 | 448 | __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ |
| AnnaBridge | 167:e84263d55307 | 449 | __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ |
| AnnaBridge | 167:e84263d55307 | 450 | __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ |
| AnnaBridge | 167:e84263d55307 | 451 | __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ |
| AnnaBridge | 167:e84263d55307 | 452 | __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ |
| AnnaBridge | 167:e84263d55307 | 453 | __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ |
| AnnaBridge | 167:e84263d55307 | 454 | __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ |
| AnnaBridge | 167:e84263d55307 | 455 | __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ |
| AnnaBridge | 167:e84263d55307 | 456 | __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ |
| AnnaBridge | 167:e84263d55307 | 457 | __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ |
| AnnaBridge | 167:e84263d55307 | 458 | __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ |
| AnnaBridge | 167:e84263d55307 | 459 | __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ |
| AnnaBridge | 167:e84263d55307 | 460 | __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ |
| AnnaBridge | 167:e84263d55307 | 461 | __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ |
| AnnaBridge | 167:e84263d55307 | 462 | __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ |
| AnnaBridge | 167:e84263d55307 | 463 | __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ |
| AnnaBridge | 167:e84263d55307 | 464 | __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ |
| AnnaBridge | 167:e84263d55307 | 465 | __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ |
| AnnaBridge | 167:e84263d55307 | 466 | __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ |
| AnnaBridge | 167:e84263d55307 | 467 | uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ |
| AnnaBridge | 167:e84263d55307 | 468 | __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ |
| AnnaBridge | 167:e84263d55307 | 469 | __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ |
| AnnaBridge | 167:e84263d55307 | 470 | uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ |
| AnnaBridge | 167:e84263d55307 | 471 | __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ |
| AnnaBridge | 167:e84263d55307 | 472 | uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ |
| AnnaBridge | 167:e84263d55307 | 473 | __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ |
| AnnaBridge | 167:e84263d55307 | 474 | uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ |
| AnnaBridge | 167:e84263d55307 | 475 | __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ |
| AnnaBridge | 167:e84263d55307 | 476 | __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ |
| AnnaBridge | 167:e84263d55307 | 477 | uint32_t RESERVED5; /*!< Reserved, 0x114 */ |
| AnnaBridge | 167:e84263d55307 | 478 | __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ |
| AnnaBridge | 167:e84263d55307 | 479 | uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ |
| AnnaBridge | 167:e84263d55307 | 480 | __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ |
| AnnaBridge | 167:e84263d55307 | 481 | __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ |
| AnnaBridge | 167:e84263d55307 | 482 | __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ |
| AnnaBridge | 167:e84263d55307 | 483 | __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ |
| AnnaBridge | 167:e84263d55307 | 484 | __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ |
| AnnaBridge | 167:e84263d55307 | 485 | __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ |
| AnnaBridge | 167:e84263d55307 | 486 | __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ |
| AnnaBridge | 167:e84263d55307 | 487 | __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ |
| AnnaBridge | 167:e84263d55307 | 488 | __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ |
| AnnaBridge | 167:e84263d55307 | 489 | __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ |
| AnnaBridge | 167:e84263d55307 | 490 | __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ |
| AnnaBridge | 167:e84263d55307 | 491 | uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ |
| AnnaBridge | 167:e84263d55307 | 492 | __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ |
| mbed_official | 19:112740acecfa | 493 | uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ |
| mbed_official | 19:112740acecfa | 494 | __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ |
| mbed_official | 19:112740acecfa | 495 | __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ |
| mbed_official | 19:112740acecfa | 496 | __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ |
| mbed_official | 19:112740acecfa | 497 | __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ |
| mbed_official | 19:112740acecfa | 498 | __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ |
| mbed_official | 19:112740acecfa | 499 | uint32_t RESERVED9; /*!< Reserved, 0x414 */ |
| mbed_official | 19:112740acecfa | 500 | __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ |
| mbed_official | 19:112740acecfa | 501 | uint32_t RESERVED10; /*!< Reserved, 0x42C */ |
| mbed_official | 19:112740acecfa | 502 | __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ |
| mbed_official | 19:112740acecfa | 503 | } DSI_TypeDef; |
| mbed_official | 19:112740acecfa | 504 | |
| mbed_official | 19:112740acecfa | 505 | /** |
| mbed_official | 19:112740acecfa | 506 | * @brief Ethernet MAC |
| mbed_official | 19:112740acecfa | 507 | */ |
| mbed_official | 19:112740acecfa | 508 | |
| mbed_official | 19:112740acecfa | 509 | typedef struct |
| mbed_official | 19:112740acecfa | 510 | { |
| mbed_official | 19:112740acecfa | 511 | __IO uint32_t MACCR; |
| mbed_official | 19:112740acecfa | 512 | __IO uint32_t MACFFR; |
| mbed_official | 19:112740acecfa | 513 | __IO uint32_t MACHTHR; |
| mbed_official | 19:112740acecfa | 514 | __IO uint32_t MACHTLR; |
| mbed_official | 19:112740acecfa | 515 | __IO uint32_t MACMIIAR; |
| mbed_official | 19:112740acecfa | 516 | __IO uint32_t MACMIIDR; |
| mbed_official | 19:112740acecfa | 517 | __IO uint32_t MACFCR; |
| mbed_official | 19:112740acecfa | 518 | __IO uint32_t MACVLANTR; /* 8 */ |
| mbed_official | 19:112740acecfa | 519 | uint32_t RESERVED0[2]; |
| mbed_official | 19:112740acecfa | 520 | __IO uint32_t MACRWUFFR; /* 11 */ |
| mbed_official | 19:112740acecfa | 521 | __IO uint32_t MACPMTCSR; |
| AnnaBridge | 167:e84263d55307 | 522 | uint32_t RESERVED1; |
| AnnaBridge | 167:e84263d55307 | 523 | __IO uint32_t MACDBGR; |
| mbed_official | 19:112740acecfa | 524 | __IO uint32_t MACSR; /* 15 */ |
| mbed_official | 19:112740acecfa | 525 | __IO uint32_t MACIMR; |
| mbed_official | 19:112740acecfa | 526 | __IO uint32_t MACA0HR; |
| mbed_official | 19:112740acecfa | 527 | __IO uint32_t MACA0LR; |
| mbed_official | 19:112740acecfa | 528 | __IO uint32_t MACA1HR; |
| mbed_official | 19:112740acecfa | 529 | __IO uint32_t MACA1LR; |
| mbed_official | 19:112740acecfa | 530 | __IO uint32_t MACA2HR; |
| mbed_official | 19:112740acecfa | 531 | __IO uint32_t MACA2LR; |
| mbed_official | 19:112740acecfa | 532 | __IO uint32_t MACA3HR; |
| mbed_official | 19:112740acecfa | 533 | __IO uint32_t MACA3LR; /* 24 */ |
| mbed_official | 19:112740acecfa | 534 | uint32_t RESERVED2[40]; |
| mbed_official | 19:112740acecfa | 535 | __IO uint32_t MMCCR; /* 65 */ |
| mbed_official | 19:112740acecfa | 536 | __IO uint32_t MMCRIR; |
| mbed_official | 19:112740acecfa | 537 | __IO uint32_t MMCTIR; |
| mbed_official | 19:112740acecfa | 538 | __IO uint32_t MMCRIMR; |
| mbed_official | 19:112740acecfa | 539 | __IO uint32_t MMCTIMR; /* 69 */ |
| mbed_official | 19:112740acecfa | 540 | uint32_t RESERVED3[14]; |
| mbed_official | 19:112740acecfa | 541 | __IO uint32_t MMCTGFSCCR; /* 84 */ |
| mbed_official | 19:112740acecfa | 542 | __IO uint32_t MMCTGFMSCCR; |
| mbed_official | 19:112740acecfa | 543 | uint32_t RESERVED4[5]; |
| mbed_official | 19:112740acecfa | 544 | __IO uint32_t MMCTGFCR; |
| mbed_official | 19:112740acecfa | 545 | uint32_t RESERVED5[10]; |
| mbed_official | 19:112740acecfa | 546 | __IO uint32_t MMCRFCECR; |
| mbed_official | 19:112740acecfa | 547 | __IO uint32_t MMCRFAECR; |
| mbed_official | 19:112740acecfa | 548 | uint32_t RESERVED6[10]; |
| mbed_official | 19:112740acecfa | 549 | __IO uint32_t MMCRGUFCR; |
| mbed_official | 19:112740acecfa | 550 | uint32_t RESERVED7[334]; |
| mbed_official | 19:112740acecfa | 551 | __IO uint32_t PTPTSCR; |
| mbed_official | 19:112740acecfa | 552 | __IO uint32_t PTPSSIR; |
| mbed_official | 19:112740acecfa | 553 | __IO uint32_t PTPTSHR; |
| mbed_official | 19:112740acecfa | 554 | __IO uint32_t PTPTSLR; |
| mbed_official | 19:112740acecfa | 555 | __IO uint32_t PTPTSHUR; |
| mbed_official | 19:112740acecfa | 556 | __IO uint32_t PTPTSLUR; |
| mbed_official | 19:112740acecfa | 557 | __IO uint32_t PTPTSAR; |
| mbed_official | 19:112740acecfa | 558 | __IO uint32_t PTPTTHR; |
| mbed_official | 19:112740acecfa | 559 | __IO uint32_t PTPTTLR; |
| mbed_official | 19:112740acecfa | 560 | __IO uint32_t RESERVED8; |
| mbed_official | 19:112740acecfa | 561 | __IO uint32_t PTPTSSR; |
| mbed_official | 19:112740acecfa | 562 | uint32_t RESERVED9[565]; |
| mbed_official | 19:112740acecfa | 563 | __IO uint32_t DMABMR; |
| mbed_official | 19:112740acecfa | 564 | __IO uint32_t DMATPDR; |
| mbed_official | 19:112740acecfa | 565 | __IO uint32_t DMARPDR; |
| mbed_official | 19:112740acecfa | 566 | __IO uint32_t DMARDLAR; |
| mbed_official | 19:112740acecfa | 567 | __IO uint32_t DMATDLAR; |
| mbed_official | 19:112740acecfa | 568 | __IO uint32_t DMASR; |
| mbed_official | 19:112740acecfa | 569 | __IO uint32_t DMAOMR; |
| mbed_official | 19:112740acecfa | 570 | __IO uint32_t DMAIER; |
| mbed_official | 19:112740acecfa | 571 | __IO uint32_t DMAMFBOCR; |
| mbed_official | 19:112740acecfa | 572 | __IO uint32_t DMARSWTR; |
| mbed_official | 19:112740acecfa | 573 | uint32_t RESERVED10[8]; |
| mbed_official | 19:112740acecfa | 574 | __IO uint32_t DMACHTDR; |
| mbed_official | 19:112740acecfa | 575 | __IO uint32_t DMACHRDR; |
| mbed_official | 19:112740acecfa | 576 | __IO uint32_t DMACHTBAR; |
| mbed_official | 19:112740acecfa | 577 | __IO uint32_t DMACHRBAR; |
| mbed_official | 19:112740acecfa | 578 | } ETH_TypeDef; |
| mbed_official | 19:112740acecfa | 579 | |
| mbed_official | 19:112740acecfa | 580 | /** |
| mbed_official | 19:112740acecfa | 581 | * @brief External Interrupt/Event Controller |
| mbed_official | 19:112740acecfa | 582 | */ |
| mbed_official | 19:112740acecfa | 583 | |
| mbed_official | 19:112740acecfa | 584 | typedef struct |
| mbed_official | 19:112740acecfa | 585 | { |
| mbed_official | 19:112740acecfa | 586 | __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 587 | __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 588 | __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 589 | __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 590 | __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 591 | __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 592 | } EXTI_TypeDef; |
| mbed_official | 19:112740acecfa | 593 | |
| mbed_official | 19:112740acecfa | 594 | /** |
| mbed_official | 19:112740acecfa | 595 | * @brief FLASH Registers |
| mbed_official | 19:112740acecfa | 596 | */ |
| mbed_official | 19:112740acecfa | 597 | |
| mbed_official | 19:112740acecfa | 598 | typedef struct |
| mbed_official | 19:112740acecfa | 599 | { |
| mbed_official | 19:112740acecfa | 600 | __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 601 | __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 602 | __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 603 | __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 604 | __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 605 | __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 606 | __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 607 | } FLASH_TypeDef; |
| mbed_official | 19:112740acecfa | 608 | |
| mbed_official | 19:112740acecfa | 609 | /** |
| mbed_official | 19:112740acecfa | 610 | * @brief Flexible Memory Controller |
| mbed_official | 19:112740acecfa | 611 | */ |
| mbed_official | 19:112740acecfa | 612 | |
| mbed_official | 19:112740acecfa | 613 | typedef struct |
| mbed_official | 19:112740acecfa | 614 | { |
| AnnaBridge | 167:e84263d55307 | 615 | __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ |
| mbed_official | 19:112740acecfa | 616 | } FMC_Bank1_TypeDef; |
| mbed_official | 19:112740acecfa | 617 | |
| mbed_official | 19:112740acecfa | 618 | /** |
| mbed_official | 19:112740acecfa | 619 | * @brief Flexible Memory Controller Bank1E |
| mbed_official | 19:112740acecfa | 620 | */ |
| mbed_official | 19:112740acecfa | 621 | |
| mbed_official | 19:112740acecfa | 622 | typedef struct |
| mbed_official | 19:112740acecfa | 623 | { |
| mbed_official | 19:112740acecfa | 624 | __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ |
| mbed_official | 19:112740acecfa | 625 | } FMC_Bank1E_TypeDef; |
| mbed_official | 19:112740acecfa | 626 | |
| mbed_official | 19:112740acecfa | 627 | /** |
| mbed_official | 19:112740acecfa | 628 | * @brief Flexible Memory Controller Bank3 |
| mbed_official | 19:112740acecfa | 629 | */ |
| mbed_official | 19:112740acecfa | 630 | |
| mbed_official | 19:112740acecfa | 631 | typedef struct |
| mbed_official | 19:112740acecfa | 632 | { |
| mbed_official | 19:112740acecfa | 633 | __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ |
| mbed_official | 19:112740acecfa | 634 | __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ |
| mbed_official | 19:112740acecfa | 635 | __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ |
| mbed_official | 19:112740acecfa | 636 | __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ |
| mbed_official | 19:112740acecfa | 637 | uint32_t RESERVED; /*!< Reserved, 0x90 */ |
| mbed_official | 19:112740acecfa | 638 | __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ |
| mbed_official | 19:112740acecfa | 639 | } FMC_Bank3_TypeDef; |
| mbed_official | 19:112740acecfa | 640 | |
| mbed_official | 19:112740acecfa | 641 | /** |
| mbed_official | 19:112740acecfa | 642 | * @brief Flexible Memory Controller Bank5_6 |
| mbed_official | 19:112740acecfa | 643 | */ |
| mbed_official | 19:112740acecfa | 644 | |
| mbed_official | 19:112740acecfa | 645 | typedef struct |
| mbed_official | 19:112740acecfa | 646 | { |
| mbed_official | 19:112740acecfa | 647 | __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ |
| mbed_official | 19:112740acecfa | 648 | __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ |
| AnnaBridge | 167:e84263d55307 | 649 | __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ |
| AnnaBridge | 167:e84263d55307 | 650 | __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ |
| AnnaBridge | 167:e84263d55307 | 651 | __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ |
| AnnaBridge | 167:e84263d55307 | 652 | } FMC_Bank5_6_TypeDef; |
| mbed_official | 19:112740acecfa | 653 | |
| mbed_official | 19:112740acecfa | 654 | /** |
| mbed_official | 19:112740acecfa | 655 | * @brief General Purpose I/O |
| mbed_official | 19:112740acecfa | 656 | */ |
| mbed_official | 19:112740acecfa | 657 | |
| mbed_official | 19:112740acecfa | 658 | typedef struct |
| mbed_official | 19:112740acecfa | 659 | { |
| mbed_official | 19:112740acecfa | 660 | __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 661 | __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 662 | __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 663 | __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 664 | __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 665 | __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 666 | __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 667 | __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 668 | __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ |
| mbed_official | 19:112740acecfa | 669 | } GPIO_TypeDef; |
| mbed_official | 19:112740acecfa | 670 | |
| mbed_official | 19:112740acecfa | 671 | /** |
| mbed_official | 19:112740acecfa | 672 | * @brief System configuration controller |
| mbed_official | 19:112740acecfa | 673 | */ |
| AnnaBridge | 167:e84263d55307 | 674 | |
| mbed_official | 19:112740acecfa | 675 | typedef struct |
| mbed_official | 19:112740acecfa | 676 | { |
| mbed_official | 19:112740acecfa | 677 | __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 678 | __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 679 | __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ |
| AnnaBridge | 167:e84263d55307 | 680 | uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ |
| mbed_official | 19:112740acecfa | 681 | __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 682 | } SYSCFG_TypeDef; |
| mbed_official | 19:112740acecfa | 683 | |
| mbed_official | 19:112740acecfa | 684 | /** |
| mbed_official | 19:112740acecfa | 685 | * @brief Inter-integrated Circuit Interface |
| mbed_official | 19:112740acecfa | 686 | */ |
| mbed_official | 19:112740acecfa | 687 | |
| mbed_official | 19:112740acecfa | 688 | typedef struct |
| mbed_official | 19:112740acecfa | 689 | { |
| mbed_official | 19:112740acecfa | 690 | __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 691 | __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 692 | __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 693 | __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 694 | __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 695 | __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 696 | __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 697 | __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 698 | __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 699 | __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ |
| mbed_official | 19:112740acecfa | 700 | } I2C_TypeDef; |
| mbed_official | 19:112740acecfa | 701 | |
| mbed_official | 19:112740acecfa | 702 | /** |
| mbed_official | 19:112740acecfa | 703 | * @brief Independent WATCHDOG |
| mbed_official | 19:112740acecfa | 704 | */ |
| mbed_official | 19:112740acecfa | 705 | |
| mbed_official | 19:112740acecfa | 706 | typedef struct |
| mbed_official | 19:112740acecfa | 707 | { |
| mbed_official | 19:112740acecfa | 708 | __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 709 | __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 710 | __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 711 | __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 712 | } IWDG_TypeDef; |
| mbed_official | 19:112740acecfa | 713 | |
| mbed_official | 19:112740acecfa | 714 | /** |
| mbed_official | 19:112740acecfa | 715 | * @brief LCD-TFT Display Controller |
| mbed_official | 19:112740acecfa | 716 | */ |
| mbed_official | 19:112740acecfa | 717 | |
| mbed_official | 19:112740acecfa | 718 | typedef struct |
| mbed_official | 19:112740acecfa | 719 | { |
| AnnaBridge | 167:e84263d55307 | 720 | uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ |
| mbed_official | 19:112740acecfa | 721 | __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 722 | __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 723 | __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 724 | __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 725 | __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ |
| AnnaBridge | 167:e84263d55307 | 726 | uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ |
| mbed_official | 19:112740acecfa | 727 | __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ |
| AnnaBridge | 167:e84263d55307 | 728 | uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ |
| mbed_official | 19:112740acecfa | 729 | __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ |
| AnnaBridge | 167:e84263d55307 | 730 | uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ |
| mbed_official | 19:112740acecfa | 731 | __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ |
| mbed_official | 19:112740acecfa | 732 | __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ |
| mbed_official | 19:112740acecfa | 733 | __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ |
| mbed_official | 19:112740acecfa | 734 | __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ |
| mbed_official | 19:112740acecfa | 735 | __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ |
| AnnaBridge | 167:e84263d55307 | 736 | __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ |
| AnnaBridge | 167:e84263d55307 | 737 | } LTDC_TypeDef; |
| mbed_official | 19:112740acecfa | 738 | |
| mbed_official | 19:112740acecfa | 739 | /** |
| mbed_official | 19:112740acecfa | 740 | * @brief LCD-TFT Display layer x Controller |
| mbed_official | 19:112740acecfa | 741 | */ |
| AnnaBridge | 167:e84263d55307 | 742 | |
| mbed_official | 19:112740acecfa | 743 | typedef struct |
| AnnaBridge | 167:e84263d55307 | 744 | { |
| mbed_official | 19:112740acecfa | 745 | __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ |
| mbed_official | 19:112740acecfa | 746 | __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ |
| mbed_official | 19:112740acecfa | 747 | __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ |
| mbed_official | 19:112740acecfa | 748 | __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ |
| mbed_official | 19:112740acecfa | 749 | __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ |
| mbed_official | 19:112740acecfa | 750 | __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ |
| mbed_official | 19:112740acecfa | 751 | __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ |
| mbed_official | 19:112740acecfa | 752 | __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ |
| AnnaBridge | 167:e84263d55307 | 753 | uint32_t RESERVED0[2]; /*!< Reserved */ |
| mbed_official | 19:112740acecfa | 754 | __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ |
| mbed_official | 19:112740acecfa | 755 | __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ |
| mbed_official | 19:112740acecfa | 756 | __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ |
| AnnaBridge | 167:e84263d55307 | 757 | uint32_t RESERVED1[3]; /*!< Reserved */ |
| AnnaBridge | 167:e84263d55307 | 758 | __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/ |
| mbed_official | 19:112740acecfa | 759 | } LTDC_Layer_TypeDef; |
| mbed_official | 19:112740acecfa | 760 | |
| mbed_official | 19:112740acecfa | 761 | /** |
| mbed_official | 19:112740acecfa | 762 | * @brief Power Control |
| mbed_official | 19:112740acecfa | 763 | */ |
| mbed_official | 19:112740acecfa | 764 | |
| mbed_official | 19:112740acecfa | 765 | typedef struct |
| mbed_official | 19:112740acecfa | 766 | { |
| mbed_official | 19:112740acecfa | 767 | __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 768 | __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 769 | } PWR_TypeDef; |
| mbed_official | 19:112740acecfa | 770 | |
| mbed_official | 19:112740acecfa | 771 | /** |
| mbed_official | 19:112740acecfa | 772 | * @brief Reset and Clock Control |
| mbed_official | 19:112740acecfa | 773 | */ |
| mbed_official | 19:112740acecfa | 774 | |
| mbed_official | 19:112740acecfa | 775 | typedef struct |
| mbed_official | 19:112740acecfa | 776 | { |
| mbed_official | 19:112740acecfa | 777 | __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 778 | __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 779 | __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 780 | __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 781 | __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 782 | __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 783 | __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 784 | uint32_t RESERVED0; /*!< Reserved, 0x1C */ |
| mbed_official | 19:112740acecfa | 785 | __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 786 | __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ |
| mbed_official | 19:112740acecfa | 787 | uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ |
| mbed_official | 19:112740acecfa | 788 | __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ |
| mbed_official | 19:112740acecfa | 789 | __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ |
| mbed_official | 19:112740acecfa | 790 | __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ |
| mbed_official | 19:112740acecfa | 791 | uint32_t RESERVED2; /*!< Reserved, 0x3C */ |
| mbed_official | 19:112740acecfa | 792 | __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ |
| mbed_official | 19:112740acecfa | 793 | __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ |
| mbed_official | 19:112740acecfa | 794 | uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ |
| mbed_official | 19:112740acecfa | 795 | __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ |
| mbed_official | 19:112740acecfa | 796 | __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ |
| mbed_official | 19:112740acecfa | 797 | __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ |
| mbed_official | 19:112740acecfa | 798 | uint32_t RESERVED4; /*!< Reserved, 0x5C */ |
| mbed_official | 19:112740acecfa | 799 | __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ |
| mbed_official | 19:112740acecfa | 800 | __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ |
| mbed_official | 19:112740acecfa | 801 | uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ |
| mbed_official | 19:112740acecfa | 802 | __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ |
| mbed_official | 19:112740acecfa | 803 | __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ |
| mbed_official | 19:112740acecfa | 804 | uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ |
| mbed_official | 19:112740acecfa | 805 | __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ |
| mbed_official | 19:112740acecfa | 806 | __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ |
| mbed_official | 19:112740acecfa | 807 | __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ |
| mbed_official | 19:112740acecfa | 808 | __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ |
| mbed_official | 19:112740acecfa | 809 | } RCC_TypeDef; |
| mbed_official | 19:112740acecfa | 810 | |
| mbed_official | 19:112740acecfa | 811 | /** |
| mbed_official | 19:112740acecfa | 812 | * @brief Real-Time Clock |
| mbed_official | 19:112740acecfa | 813 | */ |
| mbed_official | 19:112740acecfa | 814 | |
| mbed_official | 19:112740acecfa | 815 | typedef struct |
| mbed_official | 19:112740acecfa | 816 | { |
| mbed_official | 19:112740acecfa | 817 | __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 818 | __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 819 | __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 820 | __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 821 | __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 822 | __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 823 | __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 824 | __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 825 | __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 826 | __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| mbed_official | 19:112740acecfa | 827 | __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| mbed_official | 19:112740acecfa | 828 | __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| mbed_official | 19:112740acecfa | 829 | __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| mbed_official | 19:112740acecfa | 830 | __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| mbed_official | 19:112740acecfa | 831 | __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| mbed_official | 19:112740acecfa | 832 | __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| mbed_official | 19:112740acecfa | 833 | __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ |
| mbed_official | 19:112740acecfa | 834 | __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| mbed_official | 19:112740acecfa | 835 | __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ |
| mbed_official | 19:112740acecfa | 836 | uint32_t RESERVED7; /*!< Reserved, 0x4C */ |
| mbed_official | 19:112740acecfa | 837 | __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ |
| mbed_official | 19:112740acecfa | 838 | __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| mbed_official | 19:112740acecfa | 839 | __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| mbed_official | 19:112740acecfa | 840 | __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| mbed_official | 19:112740acecfa | 841 | __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| mbed_official | 19:112740acecfa | 842 | __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ |
| mbed_official | 19:112740acecfa | 843 | __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ |
| mbed_official | 19:112740acecfa | 844 | __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ |
| mbed_official | 19:112740acecfa | 845 | __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ |
| mbed_official | 19:112740acecfa | 846 | __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ |
| mbed_official | 19:112740acecfa | 847 | __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ |
| mbed_official | 19:112740acecfa | 848 | __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ |
| mbed_official | 19:112740acecfa | 849 | __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ |
| mbed_official | 19:112740acecfa | 850 | __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ |
| mbed_official | 19:112740acecfa | 851 | __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ |
| mbed_official | 19:112740acecfa | 852 | __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ |
| mbed_official | 19:112740acecfa | 853 | __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ |
| mbed_official | 19:112740acecfa | 854 | __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ |
| mbed_official | 19:112740acecfa | 855 | __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ |
| mbed_official | 19:112740acecfa | 856 | __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ |
| mbed_official | 19:112740acecfa | 857 | } RTC_TypeDef; |
| mbed_official | 19:112740acecfa | 858 | |
| mbed_official | 19:112740acecfa | 859 | /** |
| mbed_official | 19:112740acecfa | 860 | * @brief Serial Audio Interface |
| mbed_official | 19:112740acecfa | 861 | */ |
| mbed_official | 19:112740acecfa | 862 | |
| mbed_official | 19:112740acecfa | 863 | typedef struct |
| mbed_official | 19:112740acecfa | 864 | { |
| mbed_official | 19:112740acecfa | 865 | __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 866 | } SAI_TypeDef; |
| mbed_official | 19:112740acecfa | 867 | |
| mbed_official | 19:112740acecfa | 868 | typedef struct |
| mbed_official | 19:112740acecfa | 869 | { |
| mbed_official | 19:112740acecfa | 870 | __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 871 | __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 872 | __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 873 | __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 874 | __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 875 | __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 876 | __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 877 | __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 878 | } SAI_Block_TypeDef; |
| mbed_official | 19:112740acecfa | 879 | |
| mbed_official | 19:112740acecfa | 880 | /** |
| mbed_official | 19:112740acecfa | 881 | * @brief SD host Interface |
| mbed_official | 19:112740acecfa | 882 | */ |
| mbed_official | 19:112740acecfa | 883 | |
| mbed_official | 19:112740acecfa | 884 | typedef struct |
| mbed_official | 19:112740acecfa | 885 | { |
| AnnaBridge | 167:e84263d55307 | 886 | __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ |
| AnnaBridge | 167:e84263d55307 | 887 | __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ |
| AnnaBridge | 167:e84263d55307 | 888 | __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ |
| AnnaBridge | 167:e84263d55307 | 889 | __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ |
| AnnaBridge | 167:e84263d55307 | 890 | __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ |
| AnnaBridge | 167:e84263d55307 | 891 | __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ |
| AnnaBridge | 167:e84263d55307 | 892 | __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ |
| AnnaBridge | 167:e84263d55307 | 893 | __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ |
| AnnaBridge | 167:e84263d55307 | 894 | __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ |
| AnnaBridge | 167:e84263d55307 | 895 | __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ |
| AnnaBridge | 167:e84263d55307 | 896 | __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ |
| AnnaBridge | 167:e84263d55307 | 897 | __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ |
| AnnaBridge | 167:e84263d55307 | 898 | __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ |
| AnnaBridge | 167:e84263d55307 | 899 | __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ |
| AnnaBridge | 167:e84263d55307 | 900 | __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ |
| AnnaBridge | 167:e84263d55307 | 901 | __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ |
| AnnaBridge | 167:e84263d55307 | 902 | uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ |
| AnnaBridge | 167:e84263d55307 | 903 | __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ |
| AnnaBridge | 167:e84263d55307 | 904 | uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ |
| AnnaBridge | 167:e84263d55307 | 905 | __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ |
| mbed_official | 19:112740acecfa | 906 | } SDIO_TypeDef; |
| mbed_official | 19:112740acecfa | 907 | |
| mbed_official | 19:112740acecfa | 908 | /** |
| mbed_official | 19:112740acecfa | 909 | * @brief Serial Peripheral Interface |
| mbed_official | 19:112740acecfa | 910 | */ |
| mbed_official | 19:112740acecfa | 911 | |
| mbed_official | 19:112740acecfa | 912 | typedef struct |
| mbed_official | 19:112740acecfa | 913 | { |
| mbed_official | 19:112740acecfa | 914 | __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 915 | __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 916 | __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 917 | __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 918 | __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 919 | __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 920 | __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 921 | __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 922 | __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 923 | } SPI_TypeDef; |
| mbed_official | 19:112740acecfa | 924 | |
| mbed_official | 19:112740acecfa | 925 | /** |
| mbed_official | 19:112740acecfa | 926 | * @brief QUAD Serial Peripheral Interface |
| mbed_official | 19:112740acecfa | 927 | */ |
| mbed_official | 19:112740acecfa | 928 | |
| mbed_official | 19:112740acecfa | 929 | typedef struct |
| mbed_official | 19:112740acecfa | 930 | { |
| mbed_official | 19:112740acecfa | 931 | __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 932 | __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 933 | __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 934 | __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 935 | __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 936 | __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 937 | __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 938 | __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 939 | __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 940 | __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ |
| AnnaBridge | 167:e84263d55307 | 941 | __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ |
| mbed_official | 19:112740acecfa | 942 | __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ |
| AnnaBridge | 167:e84263d55307 | 943 | __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ |
| mbed_official | 19:112740acecfa | 944 | } QUADSPI_TypeDef; |
| mbed_official | 19:112740acecfa | 945 | |
| mbed_official | 19:112740acecfa | 946 | /** |
| mbed_official | 19:112740acecfa | 947 | * @brief TIM |
| mbed_official | 19:112740acecfa | 948 | */ |
| mbed_official | 19:112740acecfa | 949 | |
| mbed_official | 19:112740acecfa | 950 | typedef struct |
| mbed_official | 19:112740acecfa | 951 | { |
| mbed_official | 19:112740acecfa | 952 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 953 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 954 | __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 955 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 956 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 957 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 958 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 959 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| mbed_official | 19:112740acecfa | 960 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| mbed_official | 19:112740acecfa | 961 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| mbed_official | 19:112740acecfa | 962 | __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ |
| mbed_official | 19:112740acecfa | 963 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| mbed_official | 19:112740acecfa | 964 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| mbed_official | 19:112740acecfa | 965 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| mbed_official | 19:112740acecfa | 966 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| mbed_official | 19:112740acecfa | 967 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| mbed_official | 19:112740acecfa | 968 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| mbed_official | 19:112740acecfa | 969 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| mbed_official | 19:112740acecfa | 970 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| mbed_official | 19:112740acecfa | 971 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
| mbed_official | 19:112740acecfa | 972 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| mbed_official | 19:112740acecfa | 973 | } TIM_TypeDef; |
| mbed_official | 19:112740acecfa | 974 | |
| mbed_official | 19:112740acecfa | 975 | /** |
| mbed_official | 19:112740acecfa | 976 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| mbed_official | 19:112740acecfa | 977 | */ |
| mbed_official | 19:112740acecfa | 978 | |
| mbed_official | 19:112740acecfa | 979 | typedef struct |
| mbed_official | 19:112740acecfa | 980 | { |
| mbed_official | 19:112740acecfa | 981 | __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 982 | __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 983 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 984 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
| mbed_official | 19:112740acecfa | 985 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
| mbed_official | 19:112740acecfa | 986 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
| mbed_official | 19:112740acecfa | 987 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
| mbed_official | 19:112740acecfa | 988 | } USART_TypeDef; |
| mbed_official | 19:112740acecfa | 989 | |
| mbed_official | 19:112740acecfa | 990 | /** |
| mbed_official | 19:112740acecfa | 991 | * @brief Window WATCHDOG |
| mbed_official | 19:112740acecfa | 992 | */ |
| mbed_official | 19:112740acecfa | 993 | |
| mbed_official | 19:112740acecfa | 994 | typedef struct |
| mbed_official | 19:112740acecfa | 995 | { |
| mbed_official | 19:112740acecfa | 996 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 997 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 998 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 999 | } WWDG_TypeDef; |
| mbed_official | 19:112740acecfa | 1000 | |
| mbed_official | 19:112740acecfa | 1001 | /** |
| mbed_official | 19:112740acecfa | 1002 | * @brief RNG |
| mbed_official | 19:112740acecfa | 1003 | */ |
| mbed_official | 19:112740acecfa | 1004 | |
| mbed_official | 19:112740acecfa | 1005 | typedef struct |
| mbed_official | 19:112740acecfa | 1006 | { |
| mbed_official | 19:112740acecfa | 1007 | __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ |
| mbed_official | 19:112740acecfa | 1008 | __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ |
| mbed_official | 19:112740acecfa | 1009 | __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ |
| mbed_official | 19:112740acecfa | 1010 | } RNG_TypeDef; |
| mbed_official | 19:112740acecfa | 1011 | |
| mbed_official | 19:112740acecfa | 1012 | /** |
| mbed_official | 19:112740acecfa | 1013 | * @brief USB_OTG_Core_Registers |
| mbed_official | 19:112740acecfa | 1014 | */ |
| mbed_official | 19:112740acecfa | 1015 | typedef struct |
| mbed_official | 19:112740acecfa | 1016 | { |
| AnnaBridge | 167:e84263d55307 | 1017 | __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ |
| mbed_official | 19:112740acecfa | 1018 | __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ |
| mbed_official | 19:112740acecfa | 1019 | __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ |
| mbed_official | 19:112740acecfa | 1020 | __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ |
| mbed_official | 19:112740acecfa | 1021 | __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ |
| mbed_official | 19:112740acecfa | 1022 | __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ |
| mbed_official | 19:112740acecfa | 1023 | __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ |
| mbed_official | 19:112740acecfa | 1024 | __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ |
| mbed_official | 19:112740acecfa | 1025 | __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ |
| mbed_official | 19:112740acecfa | 1026 | __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ |
| mbed_official | 19:112740acecfa | 1027 | __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ |
| mbed_official | 19:112740acecfa | 1028 | __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ |
| mbed_official | 19:112740acecfa | 1029 | uint32_t Reserved30[2]; /*!< Reserved 030h */ |
| mbed_official | 19:112740acecfa | 1030 | __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ |
| mbed_official | 19:112740acecfa | 1031 | __IO uint32_t CID; /*!< User ID Register 03Ch */ |
| mbed_official | 19:112740acecfa | 1032 | uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ |
| mbed_official | 19:112740acecfa | 1033 | __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ |
| AnnaBridge | 167:e84263d55307 | 1034 | uint32_t Reserved6; /*!< Reserved 050h */ |
| mbed_official | 19:112740acecfa | 1035 | __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ |
| <> | 144:ef7eb2e8f9f7 | 1036 | uint32_t Reserved; /*!< Reserved 058h */ |
| mbed_official | 19:112740acecfa | 1037 | __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ |
| <> | 144:ef7eb2e8f9f7 | 1038 | uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */ |
| mbed_official | 19:112740acecfa | 1039 | __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ |
| AnnaBridge | 167:e84263d55307 | 1040 | __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ |
| mbed_official | 19:112740acecfa | 1041 | } USB_OTG_GlobalTypeDef; |
| mbed_official | 19:112740acecfa | 1042 | |
| mbed_official | 19:112740acecfa | 1043 | /** |
| mbed_official | 19:112740acecfa | 1044 | * @brief USB_OTG_device_Registers |
| mbed_official | 19:112740acecfa | 1045 | */ |
| mbed_official | 19:112740acecfa | 1046 | typedef struct |
| mbed_official | 19:112740acecfa | 1047 | { |
| mbed_official | 19:112740acecfa | 1048 | __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ |
| mbed_official | 19:112740acecfa | 1049 | __IO uint32_t DCTL; /*!< dev Control Register 804h */ |
| mbed_official | 19:112740acecfa | 1050 | __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ |
| mbed_official | 19:112740acecfa | 1051 | uint32_t Reserved0C; /*!< Reserved 80Ch */ |
| mbed_official | 19:112740acecfa | 1052 | __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ |
| mbed_official | 19:112740acecfa | 1053 | __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ |
| mbed_official | 19:112740acecfa | 1054 | __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ |
| mbed_official | 19:112740acecfa | 1055 | __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ |
| mbed_official | 19:112740acecfa | 1056 | uint32_t Reserved20; /*!< Reserved 820h */ |
| mbed_official | 19:112740acecfa | 1057 | uint32_t Reserved9; /*!< Reserved 824h */ |
| mbed_official | 19:112740acecfa | 1058 | __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ |
| mbed_official | 19:112740acecfa | 1059 | __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ |
| mbed_official | 19:112740acecfa | 1060 | __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ |
| mbed_official | 19:112740acecfa | 1061 | __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ |
| mbed_official | 19:112740acecfa | 1062 | __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ |
| AnnaBridge | 167:e84263d55307 | 1063 | __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ |
| mbed_official | 19:112740acecfa | 1064 | uint32_t Reserved40; /*!< dedicated EP mask 840h */ |
| mbed_official | 19:112740acecfa | 1065 | __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ |
| mbed_official | 19:112740acecfa | 1066 | uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ |
| AnnaBridge | 167:e84263d55307 | 1067 | __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ |
| mbed_official | 19:112740acecfa | 1068 | } USB_OTG_DeviceTypeDef; |
| mbed_official | 19:112740acecfa | 1069 | |
| mbed_official | 19:112740acecfa | 1070 | /** |
| mbed_official | 19:112740acecfa | 1071 | * @brief USB_OTG_IN_Endpoint-Specific_Register |
| mbed_official | 19:112740acecfa | 1072 | */ |
| mbed_official | 19:112740acecfa | 1073 | typedef struct |
| mbed_official | 19:112740acecfa | 1074 | { |
| mbed_official | 19:112740acecfa | 1075 | __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ |
| mbed_official | 19:112740acecfa | 1076 | uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ |
| mbed_official | 19:112740acecfa | 1077 | __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ |
| mbed_official | 19:112740acecfa | 1078 | uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ |
| mbed_official | 19:112740acecfa | 1079 | __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ |
| mbed_official | 19:112740acecfa | 1080 | __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ |
| mbed_official | 19:112740acecfa | 1081 | __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ |
| mbed_official | 19:112740acecfa | 1082 | uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ |
| mbed_official | 19:112740acecfa | 1083 | } USB_OTG_INEndpointTypeDef; |
| mbed_official | 19:112740acecfa | 1084 | |
| mbed_official | 19:112740acecfa | 1085 | /** |
| mbed_official | 19:112740acecfa | 1086 | * @brief USB_OTG_OUT_Endpoint-Specific_Registers |
| mbed_official | 19:112740acecfa | 1087 | */ |
| mbed_official | 19:112740acecfa | 1088 | typedef struct |
| mbed_official | 19:112740acecfa | 1089 | { |
| mbed_official | 19:112740acecfa | 1090 | __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ |
| mbed_official | 19:112740acecfa | 1091 | uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ |
| mbed_official | 19:112740acecfa | 1092 | __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ |
| mbed_official | 19:112740acecfa | 1093 | uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ |
| mbed_official | 19:112740acecfa | 1094 | __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ |
| mbed_official | 19:112740acecfa | 1095 | __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ |
| mbed_official | 19:112740acecfa | 1096 | uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ |
| mbed_official | 19:112740acecfa | 1097 | } USB_OTG_OUTEndpointTypeDef; |
| mbed_official | 19:112740acecfa | 1098 | |
| mbed_official | 19:112740acecfa | 1099 | /** |
| mbed_official | 19:112740acecfa | 1100 | * @brief USB_OTG_Host_Mode_Register_Structures |
| mbed_official | 19:112740acecfa | 1101 | */ |
| mbed_official | 19:112740acecfa | 1102 | typedef struct |
| mbed_official | 19:112740acecfa | 1103 | { |
| mbed_official | 19:112740acecfa | 1104 | __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ |
| mbed_official | 19:112740acecfa | 1105 | __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ |
| mbed_official | 19:112740acecfa | 1106 | __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ |
| mbed_official | 19:112740acecfa | 1107 | uint32_t Reserved40C; /*!< Reserved 40Ch */ |
| mbed_official | 19:112740acecfa | 1108 | __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ |
| mbed_official | 19:112740acecfa | 1109 | __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ |
| mbed_official | 19:112740acecfa | 1110 | __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ |
| mbed_official | 19:112740acecfa | 1111 | } USB_OTG_HostTypeDef; |
| mbed_official | 19:112740acecfa | 1112 | |
| mbed_official | 19:112740acecfa | 1113 | /** |
| mbed_official | 19:112740acecfa | 1114 | * @brief USB_OTG_Host_Channel_Specific_Registers |
| mbed_official | 19:112740acecfa | 1115 | */ |
| mbed_official | 19:112740acecfa | 1116 | typedef struct |
| mbed_official | 19:112740acecfa | 1117 | { |
| mbed_official | 19:112740acecfa | 1118 | __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ |
| mbed_official | 19:112740acecfa | 1119 | __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ |
| mbed_official | 19:112740acecfa | 1120 | __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ |
| mbed_official | 19:112740acecfa | 1121 | __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ |
| mbed_official | 19:112740acecfa | 1122 | __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ |
| mbed_official | 19:112740acecfa | 1123 | __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ |
| mbed_official | 19:112740acecfa | 1124 | uint32_t Reserved[2]; /*!< Reserved */ |
| mbed_official | 19:112740acecfa | 1125 | } USB_OTG_HostChannelTypeDef; |
| mbed_official | 19:112740acecfa | 1126 | |
| mbed_official | 19:112740acecfa | 1127 | /** |
| mbed_official | 19:112740acecfa | 1128 | * @} |
| mbed_official | 19:112740acecfa | 1129 | */ |
| AnnaBridge | 167:e84263d55307 | 1130 | |
| mbed_official | 19:112740acecfa | 1131 | /** @addtogroup Peripheral_memory_map |
| mbed_official | 19:112740acecfa | 1132 | * @{ |
| mbed_official | 19:112740acecfa | 1133 | */ |
| <> | 144:ef7eb2e8f9f7 | 1134 | #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ |
| <> | 144:ef7eb2e8f9f7 | 1135 | #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ |
| <> | 144:ef7eb2e8f9f7 | 1136 | #define SRAM1_BASE 0x20000000U /*!< SRAM1(160 KB) base address in the alias region */ |
| <> | 144:ef7eb2e8f9f7 | 1137 | #define SRAM2_BASE 0x20028000U /*!< SRAM2(32 KB) base address in the alias region */ |
| <> | 144:ef7eb2e8f9f7 | 1138 | #define SRAM3_BASE 0x20030000U /*!< SRAM3(128 KB) base address in the alias region */ |
| <> | 144:ef7eb2e8f9f7 | 1139 | #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ |
| <> | 144:ef7eb2e8f9f7 | 1140 | #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */ |
| <> | 144:ef7eb2e8f9f7 | 1141 | #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */ |
| AnnaBridge | 167:e84263d55307 | 1142 | #define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */ |
| AnnaBridge | 167:e84263d55307 | 1143 | #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */ |
| AnnaBridge | 167:e84263d55307 | 1144 | #define SRAM2_BB_BASE 0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region */ |
| AnnaBridge | 167:e84263d55307 | 1145 | #define SRAM3_BB_BASE 0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region */ |
| AnnaBridge | 167:e84263d55307 | 1146 | #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ |
| AnnaBridge | 167:e84263d55307 | 1147 | #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ |
| AnnaBridge | 167:e84263d55307 | 1148 | #define FLASH_END 0x081FFFFFU /*!< FLASH end address */ |
| AnnaBridge | 167:e84263d55307 | 1149 | #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ |
| AnnaBridge | 167:e84263d55307 | 1150 | #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ |
| AnnaBridge | 167:e84263d55307 | 1151 | #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */ |
| mbed_official | 19:112740acecfa | 1152 | |
| mbed_official | 19:112740acecfa | 1153 | /* Legacy defines */ |
| mbed_official | 19:112740acecfa | 1154 | #define SRAM_BASE SRAM1_BASE |
| mbed_official | 19:112740acecfa | 1155 | #define SRAM_BB_BASE SRAM1_BB_BASE |
| mbed_official | 19:112740acecfa | 1156 | |
| mbed_official | 19:112740acecfa | 1157 | /*!< Peripheral memory map */ |
| mbed_official | 19:112740acecfa | 1158 | #define APB1PERIPH_BASE PERIPH_BASE |
| <> | 144:ef7eb2e8f9f7 | 1159 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) |
| <> | 144:ef7eb2e8f9f7 | 1160 | #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) |
| <> | 144:ef7eb2e8f9f7 | 1161 | #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) |
| mbed_official | 19:112740acecfa | 1162 | |
| mbed_official | 19:112740acecfa | 1163 | /*!< APB1 peripherals */ |
| <> | 144:ef7eb2e8f9f7 | 1164 | #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) |
| <> | 144:ef7eb2e8f9f7 | 1165 | #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) |
| <> | 144:ef7eb2e8f9f7 | 1166 | #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) |
| <> | 144:ef7eb2e8f9f7 | 1167 | #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) |
| <> | 144:ef7eb2e8f9f7 | 1168 | #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) |
| <> | 144:ef7eb2e8f9f7 | 1169 | #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) |
| <> | 144:ef7eb2e8f9f7 | 1170 | #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) |
| <> | 144:ef7eb2e8f9f7 | 1171 | #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) |
| <> | 144:ef7eb2e8f9f7 | 1172 | #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) |
| <> | 144:ef7eb2e8f9f7 | 1173 | #define RTC_BASE (APB1PERIPH_BASE + 0x2800U) |
| <> | 144:ef7eb2e8f9f7 | 1174 | #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) |
| <> | 144:ef7eb2e8f9f7 | 1175 | #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) |
| <> | 144:ef7eb2e8f9f7 | 1176 | #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U) |
| <> | 144:ef7eb2e8f9f7 | 1177 | #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) |
| <> | 144:ef7eb2e8f9f7 | 1178 | #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) |
| <> | 144:ef7eb2e8f9f7 | 1179 | #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U) |
| <> | 144:ef7eb2e8f9f7 | 1180 | #define USART2_BASE (APB1PERIPH_BASE + 0x4400U) |
| <> | 144:ef7eb2e8f9f7 | 1181 | #define USART3_BASE (APB1PERIPH_BASE + 0x4800U) |
| <> | 144:ef7eb2e8f9f7 | 1182 | #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) |
| <> | 144:ef7eb2e8f9f7 | 1183 | #define UART5_BASE (APB1PERIPH_BASE + 0x5000U) |
| <> | 144:ef7eb2e8f9f7 | 1184 | #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) |
| <> | 144:ef7eb2e8f9f7 | 1185 | #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) |
| <> | 144:ef7eb2e8f9f7 | 1186 | #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) |
| <> | 144:ef7eb2e8f9f7 | 1187 | #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) |
| <> | 144:ef7eb2e8f9f7 | 1188 | #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) |
| <> | 144:ef7eb2e8f9f7 | 1189 | #define PWR_BASE (APB1PERIPH_BASE + 0x7000U) |
| <> | 144:ef7eb2e8f9f7 | 1190 | #define DAC_BASE (APB1PERIPH_BASE + 0x7400U) |
| <> | 144:ef7eb2e8f9f7 | 1191 | #define UART7_BASE (APB1PERIPH_BASE + 0x7800U) |
| <> | 144:ef7eb2e8f9f7 | 1192 | #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) |
| mbed_official | 19:112740acecfa | 1193 | |
| mbed_official | 19:112740acecfa | 1194 | /*!< APB2 peripherals */ |
| <> | 144:ef7eb2e8f9f7 | 1195 | #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) |
| <> | 144:ef7eb2e8f9f7 | 1196 | #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) |
| <> | 144:ef7eb2e8f9f7 | 1197 | #define USART1_BASE (APB2PERIPH_BASE + 0x1000U) |
| <> | 144:ef7eb2e8f9f7 | 1198 | #define USART6_BASE (APB2PERIPH_BASE + 0x1400U) |
| <> | 144:ef7eb2e8f9f7 | 1199 | #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) |
| <> | 144:ef7eb2e8f9f7 | 1200 | #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) |
| <> | 144:ef7eb2e8f9f7 | 1201 | #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) |
| AnnaBridge | 167:e84263d55307 | 1202 | #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U) |
| AnnaBridge | 167:e84263d55307 | 1203 | /* Legacy define */ |
| AnnaBridge | 167:e84263d55307 | 1204 | #define ADC_BASE ADC123_COMMON_BASE |
| <> | 144:ef7eb2e8f9f7 | 1205 | #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U) |
| <> | 144:ef7eb2e8f9f7 | 1206 | #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) |
| <> | 144:ef7eb2e8f9f7 | 1207 | #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) |
| <> | 144:ef7eb2e8f9f7 | 1208 | #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) |
| <> | 144:ef7eb2e8f9f7 | 1209 | #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) |
| <> | 144:ef7eb2e8f9f7 | 1210 | #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) |
| <> | 144:ef7eb2e8f9f7 | 1211 | #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) |
| <> | 144:ef7eb2e8f9f7 | 1212 | #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) |
| <> | 144:ef7eb2e8f9f7 | 1213 | #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) |
| <> | 144:ef7eb2e8f9f7 | 1214 | #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U) |
| <> | 144:ef7eb2e8f9f7 | 1215 | #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) |
| <> | 144:ef7eb2e8f9f7 | 1216 | #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) |
| <> | 144:ef7eb2e8f9f7 | 1217 | #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) |
| <> | 144:ef7eb2e8f9f7 | 1218 | #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U) |
| <> | 144:ef7eb2e8f9f7 | 1219 | #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U) |
| <> | 144:ef7eb2e8f9f7 | 1220 | #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U) |
| <> | 144:ef7eb2e8f9f7 | 1221 | #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U) |
| mbed_official | 19:112740acecfa | 1222 | |
| mbed_official | 19:112740acecfa | 1223 | /*!< AHB1 peripherals */ |
| <> | 144:ef7eb2e8f9f7 | 1224 | #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) |
| <> | 144:ef7eb2e8f9f7 | 1225 | #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) |
| <> | 144:ef7eb2e8f9f7 | 1226 | #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) |
| <> | 144:ef7eb2e8f9f7 | 1227 | #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) |
| <> | 144:ef7eb2e8f9f7 | 1228 | #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) |
| <> | 144:ef7eb2e8f9f7 | 1229 | #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) |
| <> | 144:ef7eb2e8f9f7 | 1230 | #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) |
| <> | 144:ef7eb2e8f9f7 | 1231 | #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) |
| <> | 144:ef7eb2e8f9f7 | 1232 | #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) |
| <> | 144:ef7eb2e8f9f7 | 1233 | #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U) |
| <> | 144:ef7eb2e8f9f7 | 1234 | #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U) |
| <> | 144:ef7eb2e8f9f7 | 1235 | #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) |
| <> | 144:ef7eb2e8f9f7 | 1236 | #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) |
| <> | 144:ef7eb2e8f9f7 | 1237 | #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) |
| <> | 144:ef7eb2e8f9f7 | 1238 | #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) |
| <> | 144:ef7eb2e8f9f7 | 1239 | #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) |
| <> | 144:ef7eb2e8f9f7 | 1240 | #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) |
| <> | 144:ef7eb2e8f9f7 | 1241 | #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) |
| <> | 144:ef7eb2e8f9f7 | 1242 | #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) |
| <> | 144:ef7eb2e8f9f7 | 1243 | #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) |
| <> | 144:ef7eb2e8f9f7 | 1244 | #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) |
| <> | 144:ef7eb2e8f9f7 | 1245 | #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) |
| <> | 144:ef7eb2e8f9f7 | 1246 | #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) |
| <> | 144:ef7eb2e8f9f7 | 1247 | #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) |
| <> | 144:ef7eb2e8f9f7 | 1248 | #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) |
| <> | 144:ef7eb2e8f9f7 | 1249 | #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) |
| <> | 144:ef7eb2e8f9f7 | 1250 | #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) |
| <> | 144:ef7eb2e8f9f7 | 1251 | #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) |
| <> | 144:ef7eb2e8f9f7 | 1252 | #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) |
| <> | 144:ef7eb2e8f9f7 | 1253 | #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) |
| <> | 144:ef7eb2e8f9f7 | 1254 | #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) |
| <> | 144:ef7eb2e8f9f7 | 1255 | #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) |
| <> | 144:ef7eb2e8f9f7 | 1256 | #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U) |
| mbed_official | 19:112740acecfa | 1257 | #define ETH_MAC_BASE (ETH_BASE) |
| <> | 144:ef7eb2e8f9f7 | 1258 | #define ETH_MMC_BASE (ETH_BASE + 0x0100U) |
| <> | 144:ef7eb2e8f9f7 | 1259 | #define ETH_PTP_BASE (ETH_BASE + 0x0700U) |
| <> | 144:ef7eb2e8f9f7 | 1260 | #define ETH_DMA_BASE (ETH_BASE + 0x1000U) |
| <> | 144:ef7eb2e8f9f7 | 1261 | #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) |
| mbed_official | 19:112740acecfa | 1262 | |
| mbed_official | 19:112740acecfa | 1263 | /*!< AHB2 peripherals */ |
| <> | 144:ef7eb2e8f9f7 | 1264 | #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U) |
| <> | 144:ef7eb2e8f9f7 | 1265 | #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) |
| mbed_official | 19:112740acecfa | 1266 | |
| mbed_official | 19:112740acecfa | 1267 | /*!< FMC Bankx registers base address */ |
| <> | 144:ef7eb2e8f9f7 | 1268 | #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) |
| <> | 144:ef7eb2e8f9f7 | 1269 | #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) |
| <> | 144:ef7eb2e8f9f7 | 1270 | #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) |
| <> | 144:ef7eb2e8f9f7 | 1271 | #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) |
| mbed_official | 19:112740acecfa | 1272 | |
| AnnaBridge | 167:e84263d55307 | 1273 | |
| mbed_official | 19:112740acecfa | 1274 | /*!< Debug MCU registers base address */ |
| <> | 144:ef7eb2e8f9f7 | 1275 | #define DBGMCU_BASE 0xE0042000U |
| mbed_official | 19:112740acecfa | 1276 | /*!< USB registers base address */ |
| <> | 144:ef7eb2e8f9f7 | 1277 | #define USB_OTG_HS_PERIPH_BASE 0x40040000U |
| <> | 144:ef7eb2e8f9f7 | 1278 | #define USB_OTG_FS_PERIPH_BASE 0x50000000U |
| <> | 144:ef7eb2e8f9f7 | 1279 | |
| <> | 144:ef7eb2e8f9f7 | 1280 | #define USB_OTG_GLOBAL_BASE 0x000U |
| <> | 144:ef7eb2e8f9f7 | 1281 | #define USB_OTG_DEVICE_BASE 0x800U |
| <> | 144:ef7eb2e8f9f7 | 1282 | #define USB_OTG_IN_ENDPOINT_BASE 0x900U |
| <> | 144:ef7eb2e8f9f7 | 1283 | #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U |
| <> | 144:ef7eb2e8f9f7 | 1284 | #define USB_OTG_EP_REG_SIZE 0x20U |
| <> | 144:ef7eb2e8f9f7 | 1285 | #define USB_OTG_HOST_BASE 0x400U |
| <> | 144:ef7eb2e8f9f7 | 1286 | #define USB_OTG_HOST_PORT_BASE 0x440U |
| <> | 144:ef7eb2e8f9f7 | 1287 | #define USB_OTG_HOST_CHANNEL_BASE 0x500U |
| <> | 144:ef7eb2e8f9f7 | 1288 | #define USB_OTG_HOST_CHANNEL_SIZE 0x20U |
| <> | 144:ef7eb2e8f9f7 | 1289 | #define USB_OTG_PCGCCTL_BASE 0xE00U |
| <> | 144:ef7eb2e8f9f7 | 1290 | #define USB_OTG_FIFO_BASE 0x1000U |
| <> | 144:ef7eb2e8f9f7 | 1291 | #define USB_OTG_FIFO_SIZE 0x1000U |
| mbed_official | 19:112740acecfa | 1292 | |
| AnnaBridge | 167:e84263d55307 | 1293 | #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */ |
| AnnaBridge | 167:e84263d55307 | 1294 | #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */ |
| AnnaBridge | 167:e84263d55307 | 1295 | #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ |
| mbed_official | 19:112740acecfa | 1296 | /** |
| mbed_official | 19:112740acecfa | 1297 | * @} |
| mbed_official | 19:112740acecfa | 1298 | */ |
| AnnaBridge | 167:e84263d55307 | 1299 | |
| mbed_official | 19:112740acecfa | 1300 | /** @addtogroup Peripheral_declaration |
| mbed_official | 19:112740acecfa | 1301 | * @{ |
| mbed_official | 19:112740acecfa | 1302 | */ |
| mbed_official | 19:112740acecfa | 1303 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| mbed_official | 19:112740acecfa | 1304 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| mbed_official | 19:112740acecfa | 1305 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
| mbed_official | 19:112740acecfa | 1306 | #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
| mbed_official | 19:112740acecfa | 1307 | #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
| mbed_official | 19:112740acecfa | 1308 | #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
| mbed_official | 19:112740acecfa | 1309 | #define TIM12 ((TIM_TypeDef *) TIM12_BASE) |
| mbed_official | 19:112740acecfa | 1310 | #define TIM13 ((TIM_TypeDef *) TIM13_BASE) |
| mbed_official | 19:112740acecfa | 1311 | #define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
| mbed_official | 19:112740acecfa | 1312 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
| mbed_official | 19:112740acecfa | 1313 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| mbed_official | 19:112740acecfa | 1314 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| mbed_official | 19:112740acecfa | 1315 | #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) |
| mbed_official | 19:112740acecfa | 1316 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
| mbed_official | 19:112740acecfa | 1317 | #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
| mbed_official | 19:112740acecfa | 1318 | #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) |
| mbed_official | 19:112740acecfa | 1319 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
| mbed_official | 19:112740acecfa | 1320 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
| mbed_official | 19:112740acecfa | 1321 | #define UART4 ((USART_TypeDef *) UART4_BASE) |
| mbed_official | 19:112740acecfa | 1322 | #define UART5 ((USART_TypeDef *) UART5_BASE) |
| mbed_official | 19:112740acecfa | 1323 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| mbed_official | 19:112740acecfa | 1324 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
| mbed_official | 19:112740acecfa | 1325 | #define I2C3 ((I2C_TypeDef *) I2C3_BASE) |
| mbed_official | 19:112740acecfa | 1326 | #define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
| mbed_official | 19:112740acecfa | 1327 | #define CAN2 ((CAN_TypeDef *) CAN2_BASE) |
| mbed_official | 19:112740acecfa | 1328 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
| AnnaBridge | 167:e84263d55307 | 1329 | #define DAC1 ((DAC_TypeDef *) DAC_BASE) |
| AnnaBridge | 167:e84263d55307 | 1330 | #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ |
| mbed_official | 19:112740acecfa | 1331 | #define UART7 ((USART_TypeDef *) UART7_BASE) |
| mbed_official | 19:112740acecfa | 1332 | #define UART8 ((USART_TypeDef *) UART8_BASE) |
| mbed_official | 19:112740acecfa | 1333 | #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| mbed_official | 19:112740acecfa | 1334 | #define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
| mbed_official | 19:112740acecfa | 1335 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
| mbed_official | 19:112740acecfa | 1336 | #define USART6 ((USART_TypeDef *) USART6_BASE) |
| mbed_official | 19:112740acecfa | 1337 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| mbed_official | 19:112740acecfa | 1338 | #define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
| mbed_official | 19:112740acecfa | 1339 | #define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
| AnnaBridge | 167:e84263d55307 | 1340 | #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) |
| AnnaBridge | 167:e84263d55307 | 1341 | /* Legacy define */ |
| AnnaBridge | 167:e84263d55307 | 1342 | #define ADC ADC123_COMMON |
| mbed_official | 19:112740acecfa | 1343 | #define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
| AnnaBridge | 167:e84263d55307 | 1344 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| mbed_official | 19:112740acecfa | 1345 | #define SPI4 ((SPI_TypeDef *) SPI4_BASE) |
| mbed_official | 19:112740acecfa | 1346 | #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| mbed_official | 19:112740acecfa | 1347 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| mbed_official | 19:112740acecfa | 1348 | #define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
| mbed_official | 19:112740acecfa | 1349 | #define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
| mbed_official | 19:112740acecfa | 1350 | #define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
| mbed_official | 19:112740acecfa | 1351 | #define SPI5 ((SPI_TypeDef *) SPI5_BASE) |
| mbed_official | 19:112740acecfa | 1352 | #define SPI6 ((SPI_TypeDef *) SPI6_BASE) |
| mbed_official | 19:112740acecfa | 1353 | #define SAI1 ((SAI_TypeDef *) SAI1_BASE) |
| mbed_official | 19:112740acecfa | 1354 | #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) |
| mbed_official | 19:112740acecfa | 1355 | #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) |
| mbed_official | 19:112740acecfa | 1356 | #define LTDC ((LTDC_TypeDef *)LTDC_BASE) |
| mbed_official | 19:112740acecfa | 1357 | #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) |
| mbed_official | 19:112740acecfa | 1358 | #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) |
| mbed_official | 19:112740acecfa | 1359 | #define DSI ((DSI_TypeDef *)DSI_BASE) |
| mbed_official | 19:112740acecfa | 1360 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| mbed_official | 19:112740acecfa | 1361 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| mbed_official | 19:112740acecfa | 1362 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| mbed_official | 19:112740acecfa | 1363 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| mbed_official | 19:112740acecfa | 1364 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
| mbed_official | 19:112740acecfa | 1365 | #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
| mbed_official | 19:112740acecfa | 1366 | #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
| mbed_official | 19:112740acecfa | 1367 | #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
| mbed_official | 19:112740acecfa | 1368 | #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) |
| mbed_official | 19:112740acecfa | 1369 | #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) |
| mbed_official | 19:112740acecfa | 1370 | #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) |
| mbed_official | 19:112740acecfa | 1371 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
| mbed_official | 19:112740acecfa | 1372 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
| mbed_official | 19:112740acecfa | 1373 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| mbed_official | 19:112740acecfa | 1374 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| mbed_official | 19:112740acecfa | 1375 | #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) |
| mbed_official | 19:112740acecfa | 1376 | #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) |
| mbed_official | 19:112740acecfa | 1377 | #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) |
| mbed_official | 19:112740acecfa | 1378 | #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) |
| mbed_official | 19:112740acecfa | 1379 | #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) |
| mbed_official | 19:112740acecfa | 1380 | #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) |
| mbed_official | 19:112740acecfa | 1381 | #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) |
| mbed_official | 19:112740acecfa | 1382 | #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) |
| mbed_official | 19:112740acecfa | 1383 | #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
| mbed_official | 19:112740acecfa | 1384 | #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) |
| mbed_official | 19:112740acecfa | 1385 | #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) |
| mbed_official | 19:112740acecfa | 1386 | #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) |
| mbed_official | 19:112740acecfa | 1387 | #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) |
| mbed_official | 19:112740acecfa | 1388 | #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) |
| mbed_official | 19:112740acecfa | 1389 | #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) |
| mbed_official | 19:112740acecfa | 1390 | #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) |
| mbed_official | 19:112740acecfa | 1391 | #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) |
| mbed_official | 19:112740acecfa | 1392 | #define ETH ((ETH_TypeDef *) ETH_BASE) |
| mbed_official | 19:112740acecfa | 1393 | #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) |
| mbed_official | 19:112740acecfa | 1394 | #define DCMI ((DCMI_TypeDef *) DCMI_BASE) |
| mbed_official | 19:112740acecfa | 1395 | #define RNG ((RNG_TypeDef *) RNG_BASE) |
| mbed_official | 19:112740acecfa | 1396 | #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) |
| mbed_official | 19:112740acecfa | 1397 | #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) |
| mbed_official | 19:112740acecfa | 1398 | #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) |
| mbed_official | 19:112740acecfa | 1399 | #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) |
| mbed_official | 19:112740acecfa | 1400 | #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) |
| mbed_official | 19:112740acecfa | 1401 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| mbed_official | 19:112740acecfa | 1402 | #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) |
| mbed_official | 19:112740acecfa | 1403 | #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) |
| mbed_official | 19:112740acecfa | 1404 | |
| mbed_official | 19:112740acecfa | 1405 | /** |
| mbed_official | 19:112740acecfa | 1406 | * @} |
| mbed_official | 19:112740acecfa | 1407 | */ |
| mbed_official | 19:112740acecfa | 1408 | |
| mbed_official | 19:112740acecfa | 1409 | /** @addtogroup Exported_constants |
| mbed_official | 19:112740acecfa | 1410 | * @{ |
| mbed_official | 19:112740acecfa | 1411 | */ |
| mbed_official | 19:112740acecfa | 1412 | |
| mbed_official | 19:112740acecfa | 1413 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| mbed_official | 19:112740acecfa | 1414 | * @{ |
| mbed_official | 19:112740acecfa | 1415 | */ |
| mbed_official | 19:112740acecfa | 1416 | |
| mbed_official | 19:112740acecfa | 1417 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 1418 | /* Peripheral Registers_Bits_Definition */ |
| mbed_official | 19:112740acecfa | 1419 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 1420 | |
| mbed_official | 19:112740acecfa | 1421 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 1422 | /* */ |
| mbed_official | 19:112740acecfa | 1423 | /* Analog to Digital Converter */ |
| mbed_official | 19:112740acecfa | 1424 | /* */ |
| mbed_official | 19:112740acecfa | 1425 | /******************************************************************************/ |
| AnnaBridge | 167:e84263d55307 | 1426 | /* |
| AnnaBridge | 167:e84263d55307 | 1427 | * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) |
| AnnaBridge | 167:e84263d55307 | 1428 | */ |
| AnnaBridge | 167:e84263d55307 | 1429 | #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */ |
| AnnaBridge | 167:e84263d55307 | 1430 | |
| mbed_official | 19:112740acecfa | 1431 | /******************** Bit definition for ADC_SR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 1432 | #define ADC_SR_AWD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1433 | #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1434 | #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */ |
| AnnaBridge | 167:e84263d55307 | 1435 | #define ADC_SR_EOC_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 1436 | #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1437 | #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */ |
| AnnaBridge | 167:e84263d55307 | 1438 | #define ADC_SR_JEOC_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 1439 | #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 1440 | #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */ |
| AnnaBridge | 167:e84263d55307 | 1441 | #define ADC_SR_JSTRT_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 1442 | #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 1443 | #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */ |
| AnnaBridge | 167:e84263d55307 | 1444 | #define ADC_SR_STRT_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 1445 | #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 1446 | #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */ |
| AnnaBridge | 167:e84263d55307 | 1447 | #define ADC_SR_OVR_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 1448 | #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 1449 | #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */ |
| mbed_official | 19:112740acecfa | 1450 | |
| mbed_official | 19:112740acecfa | 1451 | /******************* Bit definition for ADC_CR1 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 1452 | #define ADC_CR1_AWDCH_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1453 | #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 167:e84263d55307 | 1454 | #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
| AnnaBridge | 167:e84263d55307 | 1455 | #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1456 | #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1457 | #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 1458 | #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 1459 | #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 1460 | #define ADC_CR1_EOCIE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 1461 | #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 1462 | #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */ |
| AnnaBridge | 167:e84263d55307 | 1463 | #define ADC_CR1_AWDIE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 1464 | #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 1465 | #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 1466 | #define ADC_CR1_JEOCIE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 1467 | #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 1468 | #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */ |
| AnnaBridge | 167:e84263d55307 | 1469 | #define ADC_CR1_SCAN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 1470 | #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 1471 | #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */ |
| AnnaBridge | 167:e84263d55307 | 1472 | #define ADC_CR1_AWDSGL_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 1473 | #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 1474 | #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */ |
| AnnaBridge | 167:e84263d55307 | 1475 | #define ADC_CR1_JAUTO_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 1476 | #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 1477 | #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */ |
| AnnaBridge | 167:e84263d55307 | 1478 | #define ADC_CR1_DISCEN_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 1479 | #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 1480 | #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */ |
| AnnaBridge | 167:e84263d55307 | 1481 | #define ADC_CR1_JDISCEN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 1482 | #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 1483 | #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */ |
| AnnaBridge | 167:e84263d55307 | 1484 | #define ADC_CR1_DISCNUM_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 1485 | #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ |
| AnnaBridge | 167:e84263d55307 | 1486 | #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
| AnnaBridge | 167:e84263d55307 | 1487 | #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 1488 | #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 1489 | #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 1490 | #define ADC_CR1_JAWDEN_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 1491 | #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 1492 | #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */ |
| AnnaBridge | 167:e84263d55307 | 1493 | #define ADC_CR1_AWDEN_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 1494 | #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 1495 | #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */ |
| AnnaBridge | 167:e84263d55307 | 1496 | #define ADC_CR1_RES_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 1497 | #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 167:e84263d55307 | 1498 | #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */ |
| AnnaBridge | 167:e84263d55307 | 1499 | #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 1500 | #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 1501 | #define ADC_CR1_OVRIE_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 1502 | #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 1503 | #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */ |
| mbed_official | 19:112740acecfa | 1504 | |
| mbed_official | 19:112740acecfa | 1505 | /******************* Bit definition for ADC_CR2 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 1506 | #define ADC_CR2_ADON_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1507 | #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1508 | #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */ |
| AnnaBridge | 167:e84263d55307 | 1509 | #define ADC_CR2_CONT_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 1510 | #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1511 | #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */ |
| AnnaBridge | 167:e84263d55307 | 1512 | #define ADC_CR2_DMA_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 1513 | #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 1514 | #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */ |
| AnnaBridge | 167:e84263d55307 | 1515 | #define ADC_CR2_DDS_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 1516 | #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 1517 | #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */ |
| AnnaBridge | 167:e84263d55307 | 1518 | #define ADC_CR2_EOCS_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 1519 | #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 1520 | #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */ |
| AnnaBridge | 167:e84263d55307 | 1521 | #define ADC_CR2_ALIGN_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 1522 | #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 1523 | #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */ |
| AnnaBridge | 167:e84263d55307 | 1524 | #define ADC_CR2_JEXTSEL_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 1525 | #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 1526 | #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */ |
| AnnaBridge | 167:e84263d55307 | 1527 | #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 1528 | #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 1529 | #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 1530 | #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 1531 | #define ADC_CR2_JEXTEN_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 1532 | #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 1533 | #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ |
| AnnaBridge | 167:e84263d55307 | 1534 | #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 1535 | #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 1536 | #define ADC_CR2_JSWSTART_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 1537 | #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 1538 | #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */ |
| AnnaBridge | 167:e84263d55307 | 1539 | #define ADC_CR2_EXTSEL_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 1540 | #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 1541 | #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ |
| AnnaBridge | 167:e84263d55307 | 1542 | #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 1543 | #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 1544 | #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 1545 | #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 1546 | #define ADC_CR2_EXTEN_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 1547 | #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 1548 | #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ |
| AnnaBridge | 167:e84263d55307 | 1549 | #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 1550 | #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 1551 | #define ADC_CR2_SWSTART_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 1552 | #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 1553 | #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */ |
| mbed_official | 19:112740acecfa | 1554 | |
| mbed_official | 19:112740acecfa | 1555 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1556 | #define ADC_SMPR1_SMP10_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1557 | #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 1558 | #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1559 | #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1560 | #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1561 | #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 1562 | #define ADC_SMPR1_SMP11_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 1563 | #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 167:e84263d55307 | 1564 | #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1565 | #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 1566 | #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 1567 | #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 1568 | #define ADC_SMPR1_SMP12_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 1569 | #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ |
| AnnaBridge | 167:e84263d55307 | 1570 | #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1571 | #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 1572 | #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 1573 | #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 1574 | #define ADC_SMPR1_SMP13_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 1575 | #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ |
| AnnaBridge | 167:e84263d55307 | 1576 | #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1577 | #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 1578 | #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 1579 | #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 1580 | #define ADC_SMPR1_SMP14_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 1581 | #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 167:e84263d55307 | 1582 | #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1583 | #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 1584 | #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 1585 | #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 1586 | #define ADC_SMPR1_SMP15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 1587 | #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ |
| AnnaBridge | 167:e84263d55307 | 1588 | #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1589 | #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 1590 | #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 1591 | #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 1592 | #define ADC_SMPR1_SMP16_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 1593 | #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ |
| AnnaBridge | 167:e84263d55307 | 1594 | #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1595 | #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 1596 | #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 1597 | #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 1598 | #define ADC_SMPR1_SMP17_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 1599 | #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ |
| AnnaBridge | 167:e84263d55307 | 1600 | #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1601 | #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 1602 | #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 1603 | #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 1604 | #define ADC_SMPR1_SMP18_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 1605 | #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 167:e84263d55307 | 1606 | #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1607 | #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 1608 | #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 1609 | #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */ |
| mbed_official | 19:112740acecfa | 1610 | |
| mbed_official | 19:112740acecfa | 1611 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1612 | #define ADC_SMPR2_SMP0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1613 | #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 1614 | #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1615 | #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1616 | #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1617 | #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 1618 | #define ADC_SMPR2_SMP1_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 1619 | #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 167:e84263d55307 | 1620 | #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1621 | #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 1622 | #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 1623 | #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 1624 | #define ADC_SMPR2_SMP2_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 1625 | #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ |
| AnnaBridge | 167:e84263d55307 | 1626 | #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1627 | #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 1628 | #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 1629 | #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 1630 | #define ADC_SMPR2_SMP3_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 1631 | #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ |
| AnnaBridge | 167:e84263d55307 | 1632 | #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1633 | #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 1634 | #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 1635 | #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 1636 | #define ADC_SMPR2_SMP4_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 1637 | #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 167:e84263d55307 | 1638 | #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1639 | #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 1640 | #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 1641 | #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 1642 | #define ADC_SMPR2_SMP5_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 1643 | #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ |
| AnnaBridge | 167:e84263d55307 | 1644 | #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1645 | #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 1646 | #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 1647 | #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 1648 | #define ADC_SMPR2_SMP6_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 1649 | #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ |
| AnnaBridge | 167:e84263d55307 | 1650 | #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1651 | #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 1652 | #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 1653 | #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 1654 | #define ADC_SMPR2_SMP7_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 1655 | #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ |
| AnnaBridge | 167:e84263d55307 | 1656 | #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1657 | #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 1658 | #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 1659 | #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 1660 | #define ADC_SMPR2_SMP8_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 1661 | #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 167:e84263d55307 | 1662 | #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1663 | #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 1664 | #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 1665 | #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 1666 | #define ADC_SMPR2_SMP9_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 1667 | #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ |
| AnnaBridge | 167:e84263d55307 | 1668 | #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ |
| AnnaBridge | 167:e84263d55307 | 1669 | #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 1670 | #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 1671 | #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 1672 | |
| mbed_official | 19:112740acecfa | 1673 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1674 | #define ADC_JOFR1_JOFFSET1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1675 | #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 1676 | #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */ |
| mbed_official | 19:112740acecfa | 1677 | |
| mbed_official | 19:112740acecfa | 1678 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1679 | #define ADC_JOFR2_JOFFSET2_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1680 | #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 1681 | #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */ |
| mbed_official | 19:112740acecfa | 1682 | |
| mbed_official | 19:112740acecfa | 1683 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1684 | #define ADC_JOFR3_JOFFSET3_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1685 | #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 1686 | #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */ |
| mbed_official | 19:112740acecfa | 1687 | |
| mbed_official | 19:112740acecfa | 1688 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1689 | #define ADC_JOFR4_JOFFSET4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1690 | #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 1691 | #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */ |
| mbed_official | 19:112740acecfa | 1692 | |
| mbed_official | 19:112740acecfa | 1693 | /******************* Bit definition for ADC_HTR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 1694 | #define ADC_HTR_HT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1695 | #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 1696 | #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */ |
| mbed_official | 19:112740acecfa | 1697 | |
| mbed_official | 19:112740acecfa | 1698 | /******************* Bit definition for ADC_LTR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 1699 | #define ADC_LTR_LT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1700 | #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 1701 | #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */ |
| mbed_official | 19:112740acecfa | 1702 | |
| mbed_official | 19:112740acecfa | 1703 | /******************* Bit definition for ADC_SQR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1704 | #define ADC_SQR1_SQ13_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1705 | #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 167:e84263d55307 | 1706 | #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1707 | #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1708 | #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1709 | #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 1710 | #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 1711 | #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 1712 | #define ADC_SQR1_SQ14_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 1713 | #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ |
| AnnaBridge | 167:e84263d55307 | 1714 | #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1715 | #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 1716 | #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 1717 | #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 1718 | #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 1719 | #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 1720 | #define ADC_SQR1_SQ15_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 1721 | #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ |
| AnnaBridge | 167:e84263d55307 | 1722 | #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1723 | #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 1724 | #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 1725 | #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 1726 | #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 1727 | #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 1728 | #define ADC_SQR1_SQ16_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 1729 | #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ |
| AnnaBridge | 167:e84263d55307 | 1730 | #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1731 | #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 1732 | #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 1733 | #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 1734 | #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 1735 | #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 1736 | #define ADC_SQR1_L_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 1737 | #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 1738 | #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */ |
| AnnaBridge | 167:e84263d55307 | 1739 | #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 1740 | #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 1741 | #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 1742 | #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ |
| mbed_official | 19:112740acecfa | 1743 | |
| mbed_official | 19:112740acecfa | 1744 | /******************* Bit definition for ADC_SQR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1745 | #define ADC_SQR2_SQ7_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1746 | #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 167:e84263d55307 | 1747 | #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1748 | #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1749 | #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1750 | #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 1751 | #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 1752 | #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 1753 | #define ADC_SQR2_SQ8_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 1754 | #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ |
| AnnaBridge | 167:e84263d55307 | 1755 | #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1756 | #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 1757 | #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 1758 | #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 1759 | #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 1760 | #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 1761 | #define ADC_SQR2_SQ9_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 1762 | #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ |
| AnnaBridge | 167:e84263d55307 | 1763 | #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1764 | #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 1765 | #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 1766 | #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 1767 | #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 1768 | #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 1769 | #define ADC_SQR2_SQ10_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 1770 | #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ |
| AnnaBridge | 167:e84263d55307 | 1771 | #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1772 | #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 1773 | #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 1774 | #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 1775 | #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 1776 | #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 1777 | #define ADC_SQR2_SQ11_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 1778 | #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ |
| AnnaBridge | 167:e84263d55307 | 1779 | #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1780 | #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 1781 | #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 1782 | #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 1783 | #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 1784 | #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 1785 | #define ADC_SQR2_SQ12_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 1786 | #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ |
| AnnaBridge | 167:e84263d55307 | 1787 | #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1788 | #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 1789 | #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 1790 | #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 1791 | #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 1792 | #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 1793 | |
| mbed_official | 19:112740acecfa | 1794 | /******************* Bit definition for ADC_SQR3 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1795 | #define ADC_SQR3_SQ1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1796 | #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 167:e84263d55307 | 1797 | #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1798 | #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1799 | #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1800 | #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 1801 | #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 1802 | #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 1803 | #define ADC_SQR3_SQ2_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 1804 | #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ |
| AnnaBridge | 167:e84263d55307 | 1805 | #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1806 | #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 1807 | #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 1808 | #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 1809 | #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 1810 | #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 1811 | #define ADC_SQR3_SQ3_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 1812 | #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ |
| AnnaBridge | 167:e84263d55307 | 1813 | #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1814 | #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 1815 | #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 1816 | #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 1817 | #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 1818 | #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 1819 | #define ADC_SQR3_SQ4_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 1820 | #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ |
| AnnaBridge | 167:e84263d55307 | 1821 | #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1822 | #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 1823 | #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 1824 | #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 1825 | #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 1826 | #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 1827 | #define ADC_SQR3_SQ5_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 1828 | #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ |
| AnnaBridge | 167:e84263d55307 | 1829 | #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1830 | #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 1831 | #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 1832 | #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 1833 | #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 1834 | #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 1835 | #define ADC_SQR3_SQ6_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 1836 | #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ |
| AnnaBridge | 167:e84263d55307 | 1837 | #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1838 | #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 1839 | #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 1840 | #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 1841 | #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 1842 | #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 1843 | |
| mbed_official | 19:112740acecfa | 1844 | /******************* Bit definition for ADC_JSQR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1845 | #define ADC_JSQR_JSQ1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1846 | #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 167:e84263d55307 | 1847 | #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1848 | #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1849 | #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1850 | #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 1851 | #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 1852 | #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 1853 | #define ADC_JSQR_JSQ2_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 1854 | #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ |
| AnnaBridge | 167:e84263d55307 | 1855 | #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1856 | #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 1857 | #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 1858 | #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 1859 | #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 1860 | #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 1861 | #define ADC_JSQR_JSQ3_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 1862 | #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ |
| AnnaBridge | 167:e84263d55307 | 1863 | #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1864 | #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 1865 | #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 1866 | #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 1867 | #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 1868 | #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 1869 | #define ADC_JSQR_JSQ4_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 1870 | #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ |
| AnnaBridge | 167:e84263d55307 | 1871 | #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ |
| AnnaBridge | 167:e84263d55307 | 1872 | #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 1873 | #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 1874 | #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 1875 | #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 1876 | #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 1877 | #define ADC_JSQR_JL_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 1878 | #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 1879 | #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */ |
| AnnaBridge | 167:e84263d55307 | 1880 | #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 1881 | #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ |
| mbed_official | 19:112740acecfa | 1882 | |
| mbed_official | 19:112740acecfa | 1883 | /******************* Bit definition for ADC_JDR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1884 | #define ADC_JDR1_JDATA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1885 | #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 1886 | #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */ |
| mbed_official | 19:112740acecfa | 1887 | |
| mbed_official | 19:112740acecfa | 1888 | /******************* Bit definition for ADC_JDR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1889 | #define ADC_JDR2_JDATA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1890 | #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 1891 | #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */ |
| mbed_official | 19:112740acecfa | 1892 | |
| mbed_official | 19:112740acecfa | 1893 | /******************* Bit definition for ADC_JDR3 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1894 | #define ADC_JDR3_JDATA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1895 | #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 1896 | #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */ |
| mbed_official | 19:112740acecfa | 1897 | |
| mbed_official | 19:112740acecfa | 1898 | /******************* Bit definition for ADC_JDR4 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 1899 | #define ADC_JDR4_JDATA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1900 | #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 1901 | #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */ |
| mbed_official | 19:112740acecfa | 1902 | |
| mbed_official | 19:112740acecfa | 1903 | /******************** Bit definition for ADC_DR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 1904 | #define ADC_DR_DATA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1905 | #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 1906 | #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */ |
| AnnaBridge | 167:e84263d55307 | 1907 | #define ADC_DR_ADC2DATA_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 1908 | #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 1909 | #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */ |
| mbed_official | 19:112740acecfa | 1910 | |
| mbed_official | 19:112740acecfa | 1911 | /******************* Bit definition for ADC_CSR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 1912 | #define ADC_CSR_AWD1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1913 | #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1914 | #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */ |
| AnnaBridge | 167:e84263d55307 | 1915 | #define ADC_CSR_EOC1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 1916 | #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1917 | #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */ |
| AnnaBridge | 167:e84263d55307 | 1918 | #define ADC_CSR_JEOC1_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 1919 | #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 1920 | #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */ |
| AnnaBridge | 167:e84263d55307 | 1921 | #define ADC_CSR_JSTRT1_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 1922 | #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 1923 | #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */ |
| AnnaBridge | 167:e84263d55307 | 1924 | #define ADC_CSR_STRT1_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 1925 | #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 1926 | #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */ |
| AnnaBridge | 167:e84263d55307 | 1927 | #define ADC_CSR_OVR1_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 1928 | #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 1929 | #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */ |
| AnnaBridge | 167:e84263d55307 | 1930 | #define ADC_CSR_AWD2_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 1931 | #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 1932 | #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */ |
| AnnaBridge | 167:e84263d55307 | 1933 | #define ADC_CSR_EOC2_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 1934 | #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 1935 | #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */ |
| AnnaBridge | 167:e84263d55307 | 1936 | #define ADC_CSR_JEOC2_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 1937 | #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 1938 | #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */ |
| AnnaBridge | 167:e84263d55307 | 1939 | #define ADC_CSR_JSTRT2_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 1940 | #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 1941 | #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */ |
| AnnaBridge | 167:e84263d55307 | 1942 | #define ADC_CSR_STRT2_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 1943 | #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 1944 | #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */ |
| AnnaBridge | 167:e84263d55307 | 1945 | #define ADC_CSR_OVR2_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 1946 | #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 1947 | #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */ |
| AnnaBridge | 167:e84263d55307 | 1948 | #define ADC_CSR_AWD3_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 1949 | #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 1950 | #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */ |
| AnnaBridge | 167:e84263d55307 | 1951 | #define ADC_CSR_EOC3_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 1952 | #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 1953 | #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */ |
| AnnaBridge | 167:e84263d55307 | 1954 | #define ADC_CSR_JEOC3_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 1955 | #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 1956 | #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */ |
| AnnaBridge | 167:e84263d55307 | 1957 | #define ADC_CSR_JSTRT3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 1958 | #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 1959 | #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */ |
| AnnaBridge | 167:e84263d55307 | 1960 | #define ADC_CSR_STRT3_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 1961 | #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 1962 | #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */ |
| AnnaBridge | 167:e84263d55307 | 1963 | #define ADC_CSR_OVR3_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 1964 | #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 1965 | #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */ |
| <> | 144:ef7eb2e8f9f7 | 1966 | |
| <> | 144:ef7eb2e8f9f7 | 1967 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 1968 | #define ADC_CSR_DOVR1 ADC_CSR_OVR1 |
| <> | 144:ef7eb2e8f9f7 | 1969 | #define ADC_CSR_DOVR2 ADC_CSR_OVR2 |
| <> | 144:ef7eb2e8f9f7 | 1970 | #define ADC_CSR_DOVR3 ADC_CSR_OVR3 |
| mbed_official | 19:112740acecfa | 1971 | |
| mbed_official | 19:112740acecfa | 1972 | /******************* Bit definition for ADC_CCR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 1973 | #define ADC_CCR_MULTI_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 1974 | #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 167:e84263d55307 | 1975 | #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ |
| AnnaBridge | 167:e84263d55307 | 1976 | #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 1977 | #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 1978 | #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 1979 | #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 1980 | #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 1981 | #define ADC_CCR_DELAY_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 1982 | #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 1983 | #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ |
| AnnaBridge | 167:e84263d55307 | 1984 | #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 1985 | #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 1986 | #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 1987 | #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 1988 | #define ADC_CCR_DDS_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 1989 | #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 1990 | #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */ |
| AnnaBridge | 167:e84263d55307 | 1991 | #define ADC_CCR_DMA_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 1992 | #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 1993 | #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ |
| AnnaBridge | 167:e84263d55307 | 1994 | #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 1995 | #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 1996 | #define ADC_CCR_ADCPRE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 1997 | #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 1998 | #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */ |
| AnnaBridge | 167:e84263d55307 | 1999 | #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 2000 | #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 2001 | #define ADC_CCR_VBATE_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 2002 | #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 2003 | #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */ |
| AnnaBridge | 167:e84263d55307 | 2004 | #define ADC_CCR_TSVREFE_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 2005 | #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 2006 | #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */ |
| mbed_official | 19:112740acecfa | 2007 | |
| mbed_official | 19:112740acecfa | 2008 | /******************* Bit definition for ADC_CDR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 2009 | #define ADC_CDR_DATA1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2010 | #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 2011 | #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */ |
| AnnaBridge | 167:e84263d55307 | 2012 | #define ADC_CDR_DATA2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2013 | #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2014 | #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */ |
| AnnaBridge | 167:e84263d55307 | 2015 | |
| AnnaBridge | 167:e84263d55307 | 2016 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 2017 | #define ADC_CDR_RDATA_MST ADC_CDR_DATA1 |
| AnnaBridge | 167:e84263d55307 | 2018 | #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2 |
| mbed_official | 19:112740acecfa | 2019 | |
| mbed_official | 19:112740acecfa | 2020 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 2021 | /* */ |
| mbed_official | 19:112740acecfa | 2022 | /* Controller Area Network */ |
| mbed_official | 19:112740acecfa | 2023 | /* */ |
| mbed_official | 19:112740acecfa | 2024 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 2025 | /*!<CAN control and status registers */ |
| mbed_official | 19:112740acecfa | 2026 | /******************* Bit definition for CAN_MCR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 2027 | #define CAN_MCR_INRQ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2028 | #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2029 | #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */ |
| AnnaBridge | 167:e84263d55307 | 2030 | #define CAN_MCR_SLEEP_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2031 | #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2032 | #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */ |
| AnnaBridge | 167:e84263d55307 | 2033 | #define CAN_MCR_TXFP_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2034 | #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2035 | #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */ |
| AnnaBridge | 167:e84263d55307 | 2036 | #define CAN_MCR_RFLM_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2037 | #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2038 | #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */ |
| AnnaBridge | 167:e84263d55307 | 2039 | #define CAN_MCR_NART_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2040 | #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2041 | #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */ |
| AnnaBridge | 167:e84263d55307 | 2042 | #define CAN_MCR_AWUM_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 2043 | #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 2044 | #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */ |
| AnnaBridge | 167:e84263d55307 | 2045 | #define CAN_MCR_ABOM_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 2046 | #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 2047 | #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */ |
| AnnaBridge | 167:e84263d55307 | 2048 | #define CAN_MCR_TTCM_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 2049 | #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 2050 | #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */ |
| AnnaBridge | 167:e84263d55307 | 2051 | #define CAN_MCR_RESET_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 2052 | #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 2053 | #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */ |
| AnnaBridge | 167:e84263d55307 | 2054 | #define CAN_MCR_DBF_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2055 | #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 2056 | #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */ |
| mbed_official | 19:112740acecfa | 2057 | /******************* Bit definition for CAN_MSR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 2058 | #define CAN_MSR_INAK_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2059 | #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2060 | #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */ |
| AnnaBridge | 167:e84263d55307 | 2061 | #define CAN_MSR_SLAK_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2062 | #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2063 | #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */ |
| AnnaBridge | 167:e84263d55307 | 2064 | #define CAN_MSR_ERRI_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2065 | #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2066 | #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 2067 | #define CAN_MSR_WKUI_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2068 | #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2069 | #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 2070 | #define CAN_MSR_SLAKI_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2071 | #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2072 | #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 2073 | #define CAN_MSR_TXM_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2074 | #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2075 | #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */ |
| AnnaBridge | 167:e84263d55307 | 2076 | #define CAN_MSR_RXM_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 2077 | #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 2078 | #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */ |
| AnnaBridge | 167:e84263d55307 | 2079 | #define CAN_MSR_SAMP_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 2080 | #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 2081 | #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */ |
| AnnaBridge | 167:e84263d55307 | 2082 | #define CAN_MSR_RX_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 2083 | #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 2084 | #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */ |
| mbed_official | 19:112740acecfa | 2085 | |
| mbed_official | 19:112740acecfa | 2086 | /******************* Bit definition for CAN_TSR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 2087 | #define CAN_TSR_RQCP0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2088 | #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2089 | #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */ |
| AnnaBridge | 167:e84263d55307 | 2090 | #define CAN_TSR_TXOK0_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2091 | #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2092 | #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */ |
| AnnaBridge | 167:e84263d55307 | 2093 | #define CAN_TSR_ALST0_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2094 | #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2095 | #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */ |
| AnnaBridge | 167:e84263d55307 | 2096 | #define CAN_TSR_TERR0_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2097 | #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2098 | #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */ |
| AnnaBridge | 167:e84263d55307 | 2099 | #define CAN_TSR_ABRQ0_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 2100 | #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 2101 | #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */ |
| AnnaBridge | 167:e84263d55307 | 2102 | #define CAN_TSR_RQCP1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2103 | #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2104 | #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */ |
| AnnaBridge | 167:e84263d55307 | 2105 | #define CAN_TSR_TXOK1_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 2106 | #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 2107 | #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */ |
| AnnaBridge | 167:e84263d55307 | 2108 | #define CAN_TSR_ALST1_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 2109 | #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 2110 | #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */ |
| AnnaBridge | 167:e84263d55307 | 2111 | #define CAN_TSR_TERR1_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 2112 | #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 2113 | #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */ |
| AnnaBridge | 167:e84263d55307 | 2114 | #define CAN_TSR_ABRQ1_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 2115 | #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 2116 | #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */ |
| AnnaBridge | 167:e84263d55307 | 2117 | #define CAN_TSR_RQCP2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2118 | #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 2119 | #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */ |
| AnnaBridge | 167:e84263d55307 | 2120 | #define CAN_TSR_TXOK2_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 2121 | #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 2122 | #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */ |
| AnnaBridge | 167:e84263d55307 | 2123 | #define CAN_TSR_ALST2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 2124 | #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 2125 | #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */ |
| AnnaBridge | 167:e84263d55307 | 2126 | #define CAN_TSR_TERR2_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 2127 | #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 2128 | #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */ |
| AnnaBridge | 167:e84263d55307 | 2129 | #define CAN_TSR_ABRQ2_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 2130 | #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 2131 | #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */ |
| AnnaBridge | 167:e84263d55307 | 2132 | #define CAN_TSR_CODE_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2133 | #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 167:e84263d55307 | 2134 | #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */ |
| AnnaBridge | 167:e84263d55307 | 2135 | |
| AnnaBridge | 167:e84263d55307 | 2136 | #define CAN_TSR_TME_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 2137 | #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ |
| AnnaBridge | 167:e84263d55307 | 2138 | #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */ |
| AnnaBridge | 167:e84263d55307 | 2139 | #define CAN_TSR_TME0_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 2140 | #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 2141 | #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */ |
| AnnaBridge | 167:e84263d55307 | 2142 | #define CAN_TSR_TME1_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 2143 | #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 2144 | #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */ |
| AnnaBridge | 167:e84263d55307 | 2145 | #define CAN_TSR_TME2_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 2146 | #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 2147 | #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */ |
| AnnaBridge | 167:e84263d55307 | 2148 | |
| AnnaBridge | 167:e84263d55307 | 2149 | #define CAN_TSR_LOW_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 2150 | #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ |
| AnnaBridge | 167:e84263d55307 | 2151 | #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */ |
| AnnaBridge | 167:e84263d55307 | 2152 | #define CAN_TSR_LOW0_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 2153 | #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 2154 | #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */ |
| AnnaBridge | 167:e84263d55307 | 2155 | #define CAN_TSR_LOW1_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 2156 | #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 2157 | #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */ |
| AnnaBridge | 167:e84263d55307 | 2158 | #define CAN_TSR_LOW2_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 2159 | #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 2160 | #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */ |
| mbed_official | 19:112740acecfa | 2161 | |
| mbed_official | 19:112740acecfa | 2162 | /******************* Bit definition for CAN_RF0R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2163 | #define CAN_RF0R_FMP0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2164 | #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 2165 | #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */ |
| AnnaBridge | 167:e84263d55307 | 2166 | #define CAN_RF0R_FULL0_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2167 | #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2168 | #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */ |
| AnnaBridge | 167:e84263d55307 | 2169 | #define CAN_RF0R_FOVR0_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2170 | #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2171 | #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */ |
| AnnaBridge | 167:e84263d55307 | 2172 | #define CAN_RF0R_RFOM0_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 2173 | #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 2174 | #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */ |
| mbed_official | 19:112740acecfa | 2175 | |
| mbed_official | 19:112740acecfa | 2176 | /******************* Bit definition for CAN_RF1R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2177 | #define CAN_RF1R_FMP1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2178 | #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 2179 | #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */ |
| AnnaBridge | 167:e84263d55307 | 2180 | #define CAN_RF1R_FULL1_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2181 | #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2182 | #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */ |
| AnnaBridge | 167:e84263d55307 | 2183 | #define CAN_RF1R_FOVR1_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2184 | #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2185 | #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */ |
| AnnaBridge | 167:e84263d55307 | 2186 | #define CAN_RF1R_RFOM1_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 2187 | #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 2188 | #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */ |
| mbed_official | 19:112740acecfa | 2189 | |
| mbed_official | 19:112740acecfa | 2190 | /******************** Bit definition for CAN_IER register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2191 | #define CAN_IER_TMEIE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2192 | #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2193 | #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2194 | #define CAN_IER_FMPIE0_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2195 | #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2196 | #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2197 | #define CAN_IER_FFIE0_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2198 | #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2199 | #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2200 | #define CAN_IER_FOVIE0_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2201 | #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2202 | #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2203 | #define CAN_IER_FMPIE1_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2204 | #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2205 | #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2206 | #define CAN_IER_FFIE1_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 2207 | #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 2208 | #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2209 | #define CAN_IER_FOVIE1_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 2210 | #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 2211 | #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2212 | #define CAN_IER_EWGIE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2213 | #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2214 | #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2215 | #define CAN_IER_EPVIE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 2216 | #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 2217 | #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2218 | #define CAN_IER_BOFIE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 2219 | #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 2220 | #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2221 | #define CAN_IER_LECIE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 2222 | #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 2223 | #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2224 | #define CAN_IER_ERRIE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 2225 | #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 2226 | #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2227 | #define CAN_IER_WKUIE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2228 | #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 2229 | #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2230 | #define CAN_IER_SLKIE_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 2231 | #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 2232 | #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 2233 | #define CAN_IER_EWGIE_Pos (8U) |
| mbed_official | 19:112740acecfa | 2234 | |
| mbed_official | 19:112740acecfa | 2235 | /******************** Bit definition for CAN_ESR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2236 | #define CAN_ESR_EWGF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2237 | #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2238 | #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */ |
| AnnaBridge | 167:e84263d55307 | 2239 | #define CAN_ESR_EPVF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2240 | #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2241 | #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */ |
| AnnaBridge | 167:e84263d55307 | 2242 | #define CAN_ESR_BOFF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2243 | #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2244 | #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */ |
| AnnaBridge | 167:e84263d55307 | 2245 | |
| AnnaBridge | 167:e84263d55307 | 2246 | #define CAN_ESR_LEC_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2247 | #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 2248 | #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */ |
| AnnaBridge | 167:e84263d55307 | 2249 | #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2250 | #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 2251 | #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 2252 | |
| AnnaBridge | 167:e84263d55307 | 2253 | #define CAN_ESR_TEC_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2254 | #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2255 | #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
| AnnaBridge | 167:e84263d55307 | 2256 | #define CAN_ESR_REC_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2257 | #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2258 | #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */ |
| mbed_official | 19:112740acecfa | 2259 | |
| mbed_official | 19:112740acecfa | 2260 | /******************* Bit definition for CAN_BTR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 2261 | #define CAN_BTR_BRP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2262 | #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 167:e84263d55307 | 2263 | #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ |
| AnnaBridge | 167:e84263d55307 | 2264 | #define CAN_BTR_TS1_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2265 | #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 2266 | #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ |
| AnnaBridge | 167:e84263d55307 | 2267 | #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 2268 | #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 2269 | #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 2270 | #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 2271 | #define CAN_BTR_TS2_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 2272 | #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ |
| AnnaBridge | 167:e84263d55307 | 2273 | #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ |
| AnnaBridge | 167:e84263d55307 | 2274 | #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 2275 | #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 2276 | #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 2277 | #define CAN_BTR_SJW_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2278 | #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 167:e84263d55307 | 2279 | #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ |
| AnnaBridge | 167:e84263d55307 | 2280 | #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 2281 | #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 2282 | #define CAN_BTR_LBKM_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 2283 | #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 2284 | #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ |
| AnnaBridge | 167:e84263d55307 | 2285 | #define CAN_BTR_SILM_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 2286 | #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 2287 | #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ |
| mbed_official | 19:112740acecfa | 2288 | |
| mbed_official | 19:112740acecfa | 2289 | |
| mbed_official | 19:112740acecfa | 2290 | /*!<Mailbox registers */ |
| mbed_official | 19:112740acecfa | 2291 | /****************** Bit definition for CAN_TI0R register ********************/ |
| AnnaBridge | 167:e84263d55307 | 2292 | #define CAN_TI0R_TXRQ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2293 | #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2294 | #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| AnnaBridge | 167:e84263d55307 | 2295 | #define CAN_TI0R_RTR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2296 | #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2297 | #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 167:e84263d55307 | 2298 | #define CAN_TI0R_IDE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2299 | #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2300 | #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 167:e84263d55307 | 2301 | #define CAN_TI0R_EXID_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2302 | #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 167:e84263d55307 | 2303 | #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */ |
| AnnaBridge | 167:e84263d55307 | 2304 | #define CAN_TI0R_STID_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 2305 | #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 167:e84263d55307 | 2306 | #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 19:112740acecfa | 2307 | |
| mbed_official | 19:112740acecfa | 2308 | /****************** Bit definition for CAN_TDT0R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2309 | #define CAN_TDT0R_DLC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2310 | #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 2311 | #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 167:e84263d55307 | 2312 | #define CAN_TDT0R_TGT_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2313 | #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2314 | #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */ |
| AnnaBridge | 167:e84263d55307 | 2315 | #define CAN_TDT0R_TIME_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2316 | #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2317 | #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */ |
| mbed_official | 19:112740acecfa | 2318 | |
| mbed_official | 19:112740acecfa | 2319 | /****************** Bit definition for CAN_TDL0R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2320 | #define CAN_TDL0R_DATA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2321 | #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 2322 | #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 167:e84263d55307 | 2323 | #define CAN_TDL0R_DATA1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2324 | #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2325 | #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 167:e84263d55307 | 2326 | #define CAN_TDL0R_DATA2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2327 | #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2328 | #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 167:e84263d55307 | 2329 | #define CAN_TDL0R_DATA3_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2330 | #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2331 | #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */ |
| mbed_official | 19:112740acecfa | 2332 | |
| mbed_official | 19:112740acecfa | 2333 | /****************** Bit definition for CAN_TDH0R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2334 | #define CAN_TDH0R_DATA4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2335 | #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 2336 | #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 167:e84263d55307 | 2337 | #define CAN_TDH0R_DATA5_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2338 | #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2339 | #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 167:e84263d55307 | 2340 | #define CAN_TDH0R_DATA6_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2341 | #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2342 | #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 167:e84263d55307 | 2343 | #define CAN_TDH0R_DATA7_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2344 | #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2345 | #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */ |
| mbed_official | 19:112740acecfa | 2346 | |
| mbed_official | 19:112740acecfa | 2347 | /******************* Bit definition for CAN_TI1R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2348 | #define CAN_TI1R_TXRQ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2349 | #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2350 | #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| AnnaBridge | 167:e84263d55307 | 2351 | #define CAN_TI1R_RTR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2352 | #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2353 | #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 167:e84263d55307 | 2354 | #define CAN_TI1R_IDE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2355 | #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2356 | #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 167:e84263d55307 | 2357 | #define CAN_TI1R_EXID_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2358 | #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 167:e84263d55307 | 2359 | #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */ |
| AnnaBridge | 167:e84263d55307 | 2360 | #define CAN_TI1R_STID_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 2361 | #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 167:e84263d55307 | 2362 | #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 19:112740acecfa | 2363 | |
| mbed_official | 19:112740acecfa | 2364 | /******************* Bit definition for CAN_TDT1R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2365 | #define CAN_TDT1R_DLC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2366 | #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 2367 | #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 167:e84263d55307 | 2368 | #define CAN_TDT1R_TGT_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2369 | #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2370 | #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */ |
| AnnaBridge | 167:e84263d55307 | 2371 | #define CAN_TDT1R_TIME_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2372 | #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2373 | #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */ |
| mbed_official | 19:112740acecfa | 2374 | |
| mbed_official | 19:112740acecfa | 2375 | /******************* Bit definition for CAN_TDL1R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2376 | #define CAN_TDL1R_DATA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2377 | #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 2378 | #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 167:e84263d55307 | 2379 | #define CAN_TDL1R_DATA1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2380 | #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2381 | #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 167:e84263d55307 | 2382 | #define CAN_TDL1R_DATA2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2383 | #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2384 | #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 167:e84263d55307 | 2385 | #define CAN_TDL1R_DATA3_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2386 | #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2387 | #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */ |
| mbed_official | 19:112740acecfa | 2388 | |
| mbed_official | 19:112740acecfa | 2389 | /******************* Bit definition for CAN_TDH1R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2390 | #define CAN_TDH1R_DATA4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2391 | #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 2392 | #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 167:e84263d55307 | 2393 | #define CAN_TDH1R_DATA5_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2394 | #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2395 | #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 167:e84263d55307 | 2396 | #define CAN_TDH1R_DATA6_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2397 | #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2398 | #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 167:e84263d55307 | 2399 | #define CAN_TDH1R_DATA7_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2400 | #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2401 | #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */ |
| mbed_official | 19:112740acecfa | 2402 | |
| mbed_official | 19:112740acecfa | 2403 | /******************* Bit definition for CAN_TI2R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2404 | #define CAN_TI2R_TXRQ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2405 | #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2406 | #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| AnnaBridge | 167:e84263d55307 | 2407 | #define CAN_TI2R_RTR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2408 | #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2409 | #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 167:e84263d55307 | 2410 | #define CAN_TI2R_IDE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2411 | #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2412 | #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 167:e84263d55307 | 2413 | #define CAN_TI2R_EXID_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2414 | #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 167:e84263d55307 | 2415 | #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */ |
| AnnaBridge | 167:e84263d55307 | 2416 | #define CAN_TI2R_STID_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 2417 | #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 167:e84263d55307 | 2418 | #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 19:112740acecfa | 2419 | |
| mbed_official | 19:112740acecfa | 2420 | /******************* Bit definition for CAN_TDT2R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2421 | #define CAN_TDT2R_DLC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2422 | #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 2423 | #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 167:e84263d55307 | 2424 | #define CAN_TDT2R_TGT_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2425 | #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2426 | #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */ |
| AnnaBridge | 167:e84263d55307 | 2427 | #define CAN_TDT2R_TIME_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2428 | #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2429 | #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */ |
| mbed_official | 19:112740acecfa | 2430 | |
| mbed_official | 19:112740acecfa | 2431 | /******************* Bit definition for CAN_TDL2R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2432 | #define CAN_TDL2R_DATA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2433 | #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 2434 | #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 167:e84263d55307 | 2435 | #define CAN_TDL2R_DATA1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2436 | #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2437 | #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 167:e84263d55307 | 2438 | #define CAN_TDL2R_DATA2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2439 | #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2440 | #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 167:e84263d55307 | 2441 | #define CAN_TDL2R_DATA3_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2442 | #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2443 | #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */ |
| mbed_official | 19:112740acecfa | 2444 | |
| mbed_official | 19:112740acecfa | 2445 | /******************* Bit definition for CAN_TDH2R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2446 | #define CAN_TDH2R_DATA4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2447 | #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 2448 | #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 167:e84263d55307 | 2449 | #define CAN_TDH2R_DATA5_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2450 | #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2451 | #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 167:e84263d55307 | 2452 | #define CAN_TDH2R_DATA6_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2453 | #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2454 | #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 167:e84263d55307 | 2455 | #define CAN_TDH2R_DATA7_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2456 | #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2457 | #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */ |
| mbed_official | 19:112740acecfa | 2458 | |
| mbed_official | 19:112740acecfa | 2459 | /******************* Bit definition for CAN_RI0R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2460 | #define CAN_RI0R_RTR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2461 | #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2462 | #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 167:e84263d55307 | 2463 | #define CAN_RI0R_IDE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2464 | #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2465 | #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 167:e84263d55307 | 2466 | #define CAN_RI0R_EXID_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2467 | #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 167:e84263d55307 | 2468 | #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */ |
| AnnaBridge | 167:e84263d55307 | 2469 | #define CAN_RI0R_STID_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 2470 | #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 167:e84263d55307 | 2471 | #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 19:112740acecfa | 2472 | |
| mbed_official | 19:112740acecfa | 2473 | /******************* Bit definition for CAN_RDT0R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2474 | #define CAN_RDT0R_DLC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2475 | #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 2476 | #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 167:e84263d55307 | 2477 | #define CAN_RDT0R_FMI_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2478 | #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2479 | #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */ |
| AnnaBridge | 167:e84263d55307 | 2480 | #define CAN_RDT0R_TIME_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2481 | #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2482 | #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */ |
| mbed_official | 19:112740acecfa | 2483 | |
| mbed_official | 19:112740acecfa | 2484 | /******************* Bit definition for CAN_RDL0R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2485 | #define CAN_RDL0R_DATA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2486 | #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 2487 | #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 167:e84263d55307 | 2488 | #define CAN_RDL0R_DATA1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2489 | #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2490 | #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 167:e84263d55307 | 2491 | #define CAN_RDL0R_DATA2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2492 | #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2493 | #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 167:e84263d55307 | 2494 | #define CAN_RDL0R_DATA3_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2495 | #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2496 | #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */ |
| mbed_official | 19:112740acecfa | 2497 | |
| mbed_official | 19:112740acecfa | 2498 | /******************* Bit definition for CAN_RDH0R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2499 | #define CAN_RDH0R_DATA4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2500 | #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 2501 | #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 167:e84263d55307 | 2502 | #define CAN_RDH0R_DATA5_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2503 | #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2504 | #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 167:e84263d55307 | 2505 | #define CAN_RDH0R_DATA6_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2506 | #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2507 | #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 167:e84263d55307 | 2508 | #define CAN_RDH0R_DATA7_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2509 | #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2510 | #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */ |
| mbed_official | 19:112740acecfa | 2511 | |
| mbed_official | 19:112740acecfa | 2512 | /******************* Bit definition for CAN_RI1R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2513 | #define CAN_RI1R_RTR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2514 | #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2515 | #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 167:e84263d55307 | 2516 | #define CAN_RI1R_IDE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2517 | #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2518 | #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 167:e84263d55307 | 2519 | #define CAN_RI1R_EXID_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2520 | #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 167:e84263d55307 | 2521 | #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */ |
| AnnaBridge | 167:e84263d55307 | 2522 | #define CAN_RI1R_STID_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 2523 | #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 167:e84263d55307 | 2524 | #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 19:112740acecfa | 2525 | |
| mbed_official | 19:112740acecfa | 2526 | /******************* Bit definition for CAN_RDT1R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2527 | #define CAN_RDT1R_DLC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2528 | #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 2529 | #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 167:e84263d55307 | 2530 | #define CAN_RDT1R_FMI_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2531 | #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2532 | #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */ |
| AnnaBridge | 167:e84263d55307 | 2533 | #define CAN_RDT1R_TIME_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2534 | #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2535 | #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */ |
| mbed_official | 19:112740acecfa | 2536 | |
| mbed_official | 19:112740acecfa | 2537 | /******************* Bit definition for CAN_RDL1R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2538 | #define CAN_RDL1R_DATA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2539 | #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 2540 | #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 167:e84263d55307 | 2541 | #define CAN_RDL1R_DATA1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2542 | #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2543 | #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 167:e84263d55307 | 2544 | #define CAN_RDL1R_DATA2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2545 | #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2546 | #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 167:e84263d55307 | 2547 | #define CAN_RDL1R_DATA3_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2548 | #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2549 | #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */ |
| mbed_official | 19:112740acecfa | 2550 | |
| mbed_official | 19:112740acecfa | 2551 | /******************* Bit definition for CAN_RDH1R register ******************/ |
| AnnaBridge | 167:e84263d55307 | 2552 | #define CAN_RDH1R_DATA4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2553 | #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 2554 | #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 167:e84263d55307 | 2555 | #define CAN_RDH1R_DATA5_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2556 | #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 2557 | #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 167:e84263d55307 | 2558 | #define CAN_RDH1R_DATA6_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2559 | #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 2560 | #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 167:e84263d55307 | 2561 | #define CAN_RDH1R_DATA7_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2562 | #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 2563 | #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */ |
| mbed_official | 19:112740acecfa | 2564 | |
| mbed_official | 19:112740acecfa | 2565 | /*!<CAN filter registers */ |
| mbed_official | 19:112740acecfa | 2566 | /******************* Bit definition for CAN_FMR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 2567 | #define CAN_FMR_FINIT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2568 | #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2569 | #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */ |
| AnnaBridge | 167:e84263d55307 | 2570 | #define CAN_FMR_CAN2SB_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2571 | #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ |
| AnnaBridge | 167:e84263d55307 | 2572 | #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */ |
| mbed_official | 19:112740acecfa | 2573 | |
| mbed_official | 19:112740acecfa | 2574 | /******************* Bit definition for CAN_FM1R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2575 | #define CAN_FM1R_FBM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2576 | #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 2577 | #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */ |
| AnnaBridge | 167:e84263d55307 | 2578 | #define CAN_FM1R_FBM0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2579 | #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2580 | #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 2581 | #define CAN_FM1R_FBM1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2582 | #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2583 | #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 2584 | #define CAN_FM1R_FBM2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2585 | #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2586 | #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 2587 | #define CAN_FM1R_FBM3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2588 | #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2589 | #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 2590 | #define CAN_FM1R_FBM4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2591 | #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2592 | #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 2593 | #define CAN_FM1R_FBM5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 2594 | #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 2595 | #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 2596 | #define CAN_FM1R_FBM6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 2597 | #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 2598 | #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 2599 | #define CAN_FM1R_FBM7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 2600 | #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 2601 | #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 2602 | #define CAN_FM1R_FBM8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2603 | #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2604 | #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 2605 | #define CAN_FM1R_FBM9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 2606 | #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 2607 | #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 2608 | #define CAN_FM1R_FBM10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 2609 | #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 2610 | #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 2611 | #define CAN_FM1R_FBM11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 2612 | #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 2613 | #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 2614 | #define CAN_FM1R_FBM12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 2615 | #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 2616 | #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 2617 | #define CAN_FM1R_FBM13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 2618 | #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 2619 | #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 2620 | #define CAN_FM1R_FBM14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 2621 | #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 2622 | #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 2623 | #define CAN_FM1R_FBM15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 2624 | #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 2625 | #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 2626 | #define CAN_FM1R_FBM16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2627 | #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 2628 | #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 2629 | #define CAN_FM1R_FBM17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 2630 | #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 2631 | #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 2632 | #define CAN_FM1R_FBM18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 2633 | #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 2634 | #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 2635 | #define CAN_FM1R_FBM19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 2636 | #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 2637 | #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 2638 | #define CAN_FM1R_FBM20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 2639 | #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 2640 | #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 2641 | #define CAN_FM1R_FBM21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 2642 | #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 2643 | #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 2644 | #define CAN_FM1R_FBM22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 2645 | #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 2646 | #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 2647 | #define CAN_FM1R_FBM23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 2648 | #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 2649 | #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 2650 | #define CAN_FM1R_FBM24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2651 | #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 2652 | #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 2653 | #define CAN_FM1R_FBM25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 2654 | #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 2655 | #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 2656 | #define CAN_FM1R_FBM26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 2657 | #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 2658 | #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 2659 | #define CAN_FM1R_FBM27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 2660 | #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 2661 | #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */ |
| mbed_official | 19:112740acecfa | 2662 | |
| mbed_official | 19:112740acecfa | 2663 | /******************* Bit definition for CAN_FS1R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2664 | #define CAN_FS1R_FSC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2665 | #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 2666 | #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */ |
| AnnaBridge | 167:e84263d55307 | 2667 | #define CAN_FS1R_FSC0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2668 | #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2669 | #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 2670 | #define CAN_FS1R_FSC1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2671 | #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2672 | #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 2673 | #define CAN_FS1R_FSC2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2674 | #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2675 | #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 2676 | #define CAN_FS1R_FSC3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2677 | #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2678 | #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 2679 | #define CAN_FS1R_FSC4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2680 | #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2681 | #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 2682 | #define CAN_FS1R_FSC5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 2683 | #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 2684 | #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 2685 | #define CAN_FS1R_FSC6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 2686 | #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 2687 | #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 2688 | #define CAN_FS1R_FSC7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 2689 | #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 2690 | #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 2691 | #define CAN_FS1R_FSC8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2692 | #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2693 | #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 2694 | #define CAN_FS1R_FSC9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 2695 | #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 2696 | #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 2697 | #define CAN_FS1R_FSC10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 2698 | #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 2699 | #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 2700 | #define CAN_FS1R_FSC11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 2701 | #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 2702 | #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 2703 | #define CAN_FS1R_FSC12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 2704 | #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 2705 | #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 2706 | #define CAN_FS1R_FSC13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 2707 | #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 2708 | #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 2709 | #define CAN_FS1R_FSC14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 2710 | #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 2711 | #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 2712 | #define CAN_FS1R_FSC15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 2713 | #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 2714 | #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 2715 | #define CAN_FS1R_FSC16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2716 | #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 2717 | #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 2718 | #define CAN_FS1R_FSC17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 2719 | #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 2720 | #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 2721 | #define CAN_FS1R_FSC18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 2722 | #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 2723 | #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 2724 | #define CAN_FS1R_FSC19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 2725 | #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 2726 | #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 2727 | #define CAN_FS1R_FSC20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 2728 | #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 2729 | #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 2730 | #define CAN_FS1R_FSC21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 2731 | #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 2732 | #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 2733 | #define CAN_FS1R_FSC22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 2734 | #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 2735 | #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 2736 | #define CAN_FS1R_FSC23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 2737 | #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 2738 | #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 2739 | #define CAN_FS1R_FSC24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2740 | #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 2741 | #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 2742 | #define CAN_FS1R_FSC25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 2743 | #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 2744 | #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 2745 | #define CAN_FS1R_FSC26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 2746 | #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 2747 | #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 2748 | #define CAN_FS1R_FSC27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 2749 | #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 2750 | #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */ |
| mbed_official | 19:112740acecfa | 2751 | |
| mbed_official | 19:112740acecfa | 2752 | /****************** Bit definition for CAN_FFA1R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2753 | #define CAN_FFA1R_FFA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2754 | #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 2755 | #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */ |
| AnnaBridge | 167:e84263d55307 | 2756 | #define CAN_FFA1R_FFA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2757 | #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2758 | #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 2759 | #define CAN_FFA1R_FFA1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2760 | #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2761 | #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 2762 | #define CAN_FFA1R_FFA2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2763 | #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2764 | #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 2765 | #define CAN_FFA1R_FFA3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2766 | #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2767 | #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 2768 | #define CAN_FFA1R_FFA4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2769 | #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2770 | #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 2771 | #define CAN_FFA1R_FFA5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 2772 | #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 2773 | #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 2774 | #define CAN_FFA1R_FFA6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 2775 | #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 2776 | #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 2777 | #define CAN_FFA1R_FFA7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 2778 | #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 2779 | #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 2780 | #define CAN_FFA1R_FFA8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2781 | #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2782 | #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 2783 | #define CAN_FFA1R_FFA9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 2784 | #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 2785 | #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 2786 | #define CAN_FFA1R_FFA10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 2787 | #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 2788 | #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 2789 | #define CAN_FFA1R_FFA11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 2790 | #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 2791 | #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 2792 | #define CAN_FFA1R_FFA12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 2793 | #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 2794 | #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 2795 | #define CAN_FFA1R_FFA13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 2796 | #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 2797 | #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 2798 | #define CAN_FFA1R_FFA14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 2799 | #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 2800 | #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 2801 | #define CAN_FFA1R_FFA15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 2802 | #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 2803 | #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 2804 | #define CAN_FFA1R_FFA16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2805 | #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 2806 | #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 2807 | #define CAN_FFA1R_FFA17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 2808 | #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 2809 | #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 2810 | #define CAN_FFA1R_FFA18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 2811 | #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 2812 | #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 2813 | #define CAN_FFA1R_FFA19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 2814 | #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 2815 | #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 2816 | #define CAN_FFA1R_FFA20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 2817 | #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 2818 | #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 2819 | #define CAN_FFA1R_FFA21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 2820 | #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 2821 | #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 2822 | #define CAN_FFA1R_FFA22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 2823 | #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 2824 | #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 2825 | #define CAN_FFA1R_FFA23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 2826 | #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 2827 | #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 2828 | #define CAN_FFA1R_FFA24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2829 | #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 2830 | #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 2831 | #define CAN_FFA1R_FFA25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 2832 | #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 2833 | #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 2834 | #define CAN_FFA1R_FFA26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 2835 | #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 2836 | #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 2837 | #define CAN_FFA1R_FFA27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 2838 | #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 2839 | #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */ |
| mbed_official | 19:112740acecfa | 2840 | |
| mbed_official | 19:112740acecfa | 2841 | /******************* Bit definition for CAN_FA1R register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2842 | #define CAN_FA1R_FACT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2843 | #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 2844 | #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */ |
| AnnaBridge | 167:e84263d55307 | 2845 | #define CAN_FA1R_FACT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2846 | #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2847 | #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 2848 | #define CAN_FA1R_FACT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2849 | #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2850 | #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 2851 | #define CAN_FA1R_FACT2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2852 | #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2853 | #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 2854 | #define CAN_FA1R_FACT3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2855 | #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2856 | #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 2857 | #define CAN_FA1R_FACT4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2858 | #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2859 | #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 2860 | #define CAN_FA1R_FACT5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 2861 | #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 2862 | #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 2863 | #define CAN_FA1R_FACT6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 2864 | #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 2865 | #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 2866 | #define CAN_FA1R_FACT7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 2867 | #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 2868 | #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 2869 | #define CAN_FA1R_FACT8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2870 | #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2871 | #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 2872 | #define CAN_FA1R_FACT9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 2873 | #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 2874 | #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 2875 | #define CAN_FA1R_FACT10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 2876 | #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 2877 | #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 2878 | #define CAN_FA1R_FACT11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 2879 | #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 2880 | #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 2881 | #define CAN_FA1R_FACT12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 2882 | #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 2883 | #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 2884 | #define CAN_FA1R_FACT13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 2885 | #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 2886 | #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 2887 | #define CAN_FA1R_FACT14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 2888 | #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 2889 | #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 2890 | #define CAN_FA1R_FACT15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 2891 | #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 2892 | #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 2893 | #define CAN_FA1R_FACT16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2894 | #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 2895 | #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 2896 | #define CAN_FA1R_FACT17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 2897 | #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 2898 | #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 2899 | #define CAN_FA1R_FACT18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 2900 | #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 2901 | #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 2902 | #define CAN_FA1R_FACT19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 2903 | #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 2904 | #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 2905 | #define CAN_FA1R_FACT20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 2906 | #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 2907 | #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 2908 | #define CAN_FA1R_FACT21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 2909 | #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 2910 | #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 2911 | #define CAN_FA1R_FACT22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 2912 | #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 2913 | #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 2914 | #define CAN_FA1R_FACT23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 2915 | #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 2916 | #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 2917 | #define CAN_FA1R_FACT24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 2918 | #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 2919 | #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 2920 | #define CAN_FA1R_FACT25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 2921 | #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 2922 | #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 2923 | #define CAN_FA1R_FACT26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 2924 | #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 2925 | #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 2926 | #define CAN_FA1R_FACT27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 2927 | #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 2928 | #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */ |
| mbed_official | 19:112740acecfa | 2929 | |
| mbed_official | 19:112740acecfa | 2930 | |
| mbed_official | 19:112740acecfa | 2931 | /******************* Bit definition for CAN_F0R1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 2932 | #define CAN_F0R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 2933 | #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 2934 | #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 2935 | #define CAN_F0R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 2936 | #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 2937 | #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 2938 | #define CAN_F0R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 2939 | #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 2940 | #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 2941 | #define CAN_F0R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 2942 | #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 2943 | #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 2944 | #define CAN_F0R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 2945 | #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 2946 | #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 2947 | #define CAN_F0R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 2948 | #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 2949 | #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 2950 | #define CAN_F0R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 2951 | #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 2952 | #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 2953 | #define CAN_F0R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 2954 | #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 2955 | #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 2956 | #define CAN_F0R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 2957 | #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 2958 | #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 2959 | #define CAN_F0R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 2960 | #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 2961 | #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 2962 | #define CAN_F0R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 2963 | #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 2964 | #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 2965 | #define CAN_F0R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 2966 | #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 2967 | #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 2968 | #define CAN_F0R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 2969 | #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 2970 | #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 2971 | #define CAN_F0R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 2972 | #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 2973 | #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 2974 | #define CAN_F0R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 2975 | #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 2976 | #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 2977 | #define CAN_F0R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 2978 | #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 2979 | #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 2980 | #define CAN_F0R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 2981 | #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 2982 | #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 2983 | #define CAN_F0R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 2984 | #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 2985 | #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 2986 | #define CAN_F0R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 2987 | #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 2988 | #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 2989 | #define CAN_F0R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 2990 | #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 2991 | #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 2992 | #define CAN_F0R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 2993 | #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 2994 | #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 2995 | #define CAN_F0R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 2996 | #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 2997 | #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 2998 | #define CAN_F0R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 2999 | #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3000 | #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3001 | #define CAN_F0R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3002 | #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3003 | #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3004 | #define CAN_F0R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3005 | #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3006 | #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3007 | #define CAN_F0R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3008 | #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3009 | #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3010 | #define CAN_F0R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3011 | #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3012 | #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3013 | #define CAN_F0R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3014 | #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3015 | #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3016 | #define CAN_F0R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3017 | #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3018 | #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3019 | #define CAN_F0R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 3020 | #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 3021 | #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 3022 | #define CAN_F0R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 3023 | #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 3024 | #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 3025 | #define CAN_F0R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 3026 | #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 3027 | #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 3028 | |
| mbed_official | 19:112740acecfa | 3029 | /******************* Bit definition for CAN_F1R1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 3030 | #define CAN_F1R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 3031 | #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 3032 | #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 3033 | #define CAN_F1R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 3034 | #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 3035 | #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 3036 | #define CAN_F1R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 3037 | #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 3038 | #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 3039 | #define CAN_F1R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 3040 | #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 3041 | #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 3042 | #define CAN_F1R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 3043 | #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 3044 | #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 3045 | #define CAN_F1R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 3046 | #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 3047 | #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 3048 | #define CAN_F1R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 3049 | #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 3050 | #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 3051 | #define CAN_F1R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 3052 | #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 3053 | #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 3054 | #define CAN_F1R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 3055 | #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 3056 | #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 3057 | #define CAN_F1R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 3058 | #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 3059 | #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 3060 | #define CAN_F1R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 3061 | #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 3062 | #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 3063 | #define CAN_F1R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 3064 | #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 3065 | #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 3066 | #define CAN_F1R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 3067 | #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 3068 | #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 3069 | #define CAN_F1R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 3070 | #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 3071 | #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 3072 | #define CAN_F1R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 3073 | #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 3074 | #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 3075 | #define CAN_F1R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 3076 | #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 3077 | #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 3078 | #define CAN_F1R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 3079 | #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 3080 | #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 3081 | #define CAN_F1R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 3082 | #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 3083 | #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 3084 | #define CAN_F1R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 3085 | #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 3086 | #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 3087 | #define CAN_F1R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 3088 | #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 3089 | #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 3090 | #define CAN_F1R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 3091 | #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 3092 | #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 3093 | #define CAN_F1R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 3094 | #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 3095 | #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 3096 | #define CAN_F1R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 3097 | #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3098 | #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3099 | #define CAN_F1R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3100 | #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3101 | #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3102 | #define CAN_F1R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3103 | #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3104 | #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3105 | #define CAN_F1R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3106 | #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3107 | #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3108 | #define CAN_F1R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3109 | #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3110 | #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3111 | #define CAN_F1R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3112 | #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3113 | #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3114 | #define CAN_F1R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3115 | #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3116 | #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3117 | #define CAN_F1R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 3118 | #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 3119 | #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 3120 | #define CAN_F1R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 3121 | #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 3122 | #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 3123 | #define CAN_F1R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 3124 | #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 3125 | #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 3126 | |
| mbed_official | 19:112740acecfa | 3127 | /******************* Bit definition for CAN_F2R1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 3128 | #define CAN_F2R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 3129 | #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 3130 | #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 3131 | #define CAN_F2R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 3132 | #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 3133 | #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 3134 | #define CAN_F2R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 3135 | #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 3136 | #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 3137 | #define CAN_F2R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 3138 | #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 3139 | #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 3140 | #define CAN_F2R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 3141 | #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 3142 | #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 3143 | #define CAN_F2R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 3144 | #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 3145 | #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 3146 | #define CAN_F2R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 3147 | #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 3148 | #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 3149 | #define CAN_F2R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 3150 | #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 3151 | #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 3152 | #define CAN_F2R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 3153 | #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 3154 | #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 3155 | #define CAN_F2R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 3156 | #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 3157 | #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 3158 | #define CAN_F2R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 3159 | #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 3160 | #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 3161 | #define CAN_F2R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 3162 | #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 3163 | #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 3164 | #define CAN_F2R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 3165 | #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 3166 | #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 3167 | #define CAN_F2R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 3168 | #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 3169 | #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 3170 | #define CAN_F2R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 3171 | #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 3172 | #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 3173 | #define CAN_F2R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 3174 | #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 3175 | #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 3176 | #define CAN_F2R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 3177 | #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 3178 | #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 3179 | #define CAN_F2R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 3180 | #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 3181 | #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 3182 | #define CAN_F2R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 3183 | #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 3184 | #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 3185 | #define CAN_F2R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 3186 | #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 3187 | #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 3188 | #define CAN_F2R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 3189 | #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 3190 | #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 3191 | #define CAN_F2R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 3192 | #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 3193 | #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 3194 | #define CAN_F2R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 3195 | #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3196 | #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3197 | #define CAN_F2R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3198 | #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3199 | #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3200 | #define CAN_F2R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3201 | #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3202 | #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3203 | #define CAN_F2R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3204 | #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3205 | #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3206 | #define CAN_F2R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3207 | #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3208 | #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3209 | #define CAN_F2R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3210 | #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3211 | #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3212 | #define CAN_F2R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3213 | #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3214 | #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3215 | #define CAN_F2R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 3216 | #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 3217 | #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 3218 | #define CAN_F2R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 3219 | #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 3220 | #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 3221 | #define CAN_F2R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 3222 | #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 3223 | #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 3224 | |
| mbed_official | 19:112740acecfa | 3225 | /******************* Bit definition for CAN_F3R1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 3226 | #define CAN_F3R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 3227 | #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 3228 | #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 3229 | #define CAN_F3R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 3230 | #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 3231 | #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 3232 | #define CAN_F3R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 3233 | #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 3234 | #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 3235 | #define CAN_F3R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 3236 | #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 3237 | #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 3238 | #define CAN_F3R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 3239 | #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 3240 | #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 3241 | #define CAN_F3R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 3242 | #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 3243 | #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 3244 | #define CAN_F3R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 3245 | #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 3246 | #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 3247 | #define CAN_F3R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 3248 | #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 3249 | #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 3250 | #define CAN_F3R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 3251 | #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 3252 | #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 3253 | #define CAN_F3R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 3254 | #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 3255 | #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 3256 | #define CAN_F3R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 3257 | #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 3258 | #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 3259 | #define CAN_F3R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 3260 | #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 3261 | #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 3262 | #define CAN_F3R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 3263 | #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 3264 | #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 3265 | #define CAN_F3R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 3266 | #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 3267 | #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 3268 | #define CAN_F3R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 3269 | #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 3270 | #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 3271 | #define CAN_F3R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 3272 | #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 3273 | #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 3274 | #define CAN_F3R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 3275 | #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 3276 | #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 3277 | #define CAN_F3R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 3278 | #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 3279 | #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 3280 | #define CAN_F3R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 3281 | #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 3282 | #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 3283 | #define CAN_F3R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 3284 | #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 3285 | #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 3286 | #define CAN_F3R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 3287 | #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 3288 | #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 3289 | #define CAN_F3R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 3290 | #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 3291 | #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 3292 | #define CAN_F3R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 3293 | #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3294 | #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3295 | #define CAN_F3R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3296 | #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3297 | #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3298 | #define CAN_F3R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3299 | #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3300 | #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3301 | #define CAN_F3R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3302 | #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3303 | #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3304 | #define CAN_F3R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3305 | #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3306 | #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3307 | #define CAN_F3R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3308 | #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3309 | #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3310 | #define CAN_F3R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3311 | #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3312 | #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3313 | #define CAN_F3R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 3314 | #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 3315 | #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 3316 | #define CAN_F3R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 3317 | #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 3318 | #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 3319 | #define CAN_F3R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 3320 | #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 3321 | #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 3322 | |
| mbed_official | 19:112740acecfa | 3323 | /******************* Bit definition for CAN_F4R1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 3324 | #define CAN_F4R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 3325 | #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 3326 | #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 3327 | #define CAN_F4R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 3328 | #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 3329 | #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 3330 | #define CAN_F4R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 3331 | #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 3332 | #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 3333 | #define CAN_F4R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 3334 | #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 3335 | #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 3336 | #define CAN_F4R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 3337 | #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 3338 | #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 3339 | #define CAN_F4R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 3340 | #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 3341 | #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 3342 | #define CAN_F4R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 3343 | #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 3344 | #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 3345 | #define CAN_F4R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 3346 | #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 3347 | #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 3348 | #define CAN_F4R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 3349 | #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 3350 | #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 3351 | #define CAN_F4R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 3352 | #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 3353 | #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 3354 | #define CAN_F4R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 3355 | #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 3356 | #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 3357 | #define CAN_F4R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 3358 | #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 3359 | #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 3360 | #define CAN_F4R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 3361 | #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 3362 | #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 3363 | #define CAN_F4R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 3364 | #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 3365 | #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 3366 | #define CAN_F4R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 3367 | #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 3368 | #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 3369 | #define CAN_F4R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 3370 | #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 3371 | #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 3372 | #define CAN_F4R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 3373 | #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 3374 | #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 3375 | #define CAN_F4R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 3376 | #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 3377 | #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 3378 | #define CAN_F4R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 3379 | #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 3380 | #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 3381 | #define CAN_F4R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 3382 | #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 3383 | #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 3384 | #define CAN_F4R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 3385 | #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 3386 | #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 3387 | #define CAN_F4R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 3388 | #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 3389 | #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 3390 | #define CAN_F4R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 3391 | #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3392 | #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3393 | #define CAN_F4R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3394 | #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3395 | #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3396 | #define CAN_F4R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3397 | #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3398 | #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3399 | #define CAN_F4R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3400 | #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3401 | #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3402 | #define CAN_F4R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3403 | #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3404 | #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3405 | #define CAN_F4R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3406 | #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3407 | #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3408 | #define CAN_F4R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3409 | #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3410 | #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3411 | #define CAN_F4R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 3412 | #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 3413 | #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 3414 | #define CAN_F4R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 3415 | #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 3416 | #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 3417 | #define CAN_F4R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 3418 | #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 3419 | #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 3420 | |
| mbed_official | 19:112740acecfa | 3421 | /******************* Bit definition for CAN_F5R1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 3422 | #define CAN_F5R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 3423 | #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 3424 | #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 3425 | #define CAN_F5R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 3426 | #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 3427 | #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 3428 | #define CAN_F5R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 3429 | #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 3430 | #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 3431 | #define CAN_F5R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 3432 | #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 3433 | #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 3434 | #define CAN_F5R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 3435 | #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 3436 | #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 3437 | #define CAN_F5R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 3438 | #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 3439 | #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 3440 | #define CAN_F5R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 3441 | #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 3442 | #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 3443 | #define CAN_F5R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 3444 | #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 3445 | #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 3446 | #define CAN_F5R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 3447 | #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 3448 | #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 3449 | #define CAN_F5R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 3450 | #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 3451 | #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 3452 | #define CAN_F5R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 3453 | #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 3454 | #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 3455 | #define CAN_F5R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 3456 | #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 3457 | #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 3458 | #define CAN_F5R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 3459 | #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 3460 | #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 3461 | #define CAN_F5R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 3462 | #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 3463 | #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 3464 | #define CAN_F5R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 3465 | #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 3466 | #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 3467 | #define CAN_F5R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 3468 | #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 3469 | #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 3470 | #define CAN_F5R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 3471 | #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 3472 | #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 3473 | #define CAN_F5R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 3474 | #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 3475 | #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 3476 | #define CAN_F5R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 3477 | #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 3478 | #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 3479 | #define CAN_F5R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 3480 | #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 3481 | #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 3482 | #define CAN_F5R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 3483 | #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 3484 | #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 3485 | #define CAN_F5R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 3486 | #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 3487 | #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 3488 | #define CAN_F5R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 3489 | #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3490 | #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3491 | #define CAN_F5R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3492 | #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3493 | #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3494 | #define CAN_F5R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3495 | #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3496 | #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3497 | #define CAN_F5R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3498 | #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3499 | #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3500 | #define CAN_F5R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3501 | #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3502 | #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3503 | #define CAN_F5R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3504 | #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3505 | #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3506 | #define CAN_F5R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3507 | #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3508 | #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3509 | #define CAN_F5R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 3510 | #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 3511 | #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 3512 | #define CAN_F5R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 3513 | #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 3514 | #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 3515 | #define CAN_F5R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 3516 | #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 3517 | #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 3518 | |
| mbed_official | 19:112740acecfa | 3519 | /******************* Bit definition for CAN_F6R1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 3520 | #define CAN_F6R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 3521 | #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 3522 | #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 3523 | #define CAN_F6R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 3524 | #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 3525 | #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 3526 | #define CAN_F6R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 3527 | #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 3528 | #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 3529 | #define CAN_F6R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 3530 | #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 3531 | #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 3532 | #define CAN_F6R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 3533 | #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 3534 | #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 3535 | #define CAN_F6R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 3536 | #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 3537 | #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 3538 | #define CAN_F6R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 3539 | #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 3540 | #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 3541 | #define CAN_F6R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 3542 | #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 3543 | #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 3544 | #define CAN_F6R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 3545 | #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 3546 | #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 3547 | #define CAN_F6R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 3548 | #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 3549 | #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 3550 | #define CAN_F6R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 3551 | #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 3552 | #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 3553 | #define CAN_F6R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 3554 | #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 3555 | #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 3556 | #define CAN_F6R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 3557 | #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 3558 | #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 3559 | #define CAN_F6R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 3560 | #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 3561 | #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 3562 | #define CAN_F6R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 3563 | #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 3564 | #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 3565 | #define CAN_F6R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 3566 | #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 3567 | #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 3568 | #define CAN_F6R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 3569 | #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 3570 | #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 3571 | #define CAN_F6R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 3572 | #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 3573 | #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 3574 | #define CAN_F6R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 3575 | #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 3576 | #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 3577 | #define CAN_F6R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 3578 | #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 3579 | #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 3580 | #define CAN_F6R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 3581 | #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 3582 | #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 3583 | #define CAN_F6R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 3584 | #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 3585 | #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 3586 | #define CAN_F6R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 3587 | #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3588 | #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3589 | #define CAN_F6R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3590 | #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3591 | #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3592 | #define CAN_F6R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3593 | #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3594 | #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3595 | #define CAN_F6R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3596 | #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3597 | #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3598 | #define CAN_F6R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3599 | #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3600 | #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3601 | #define CAN_F6R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3602 | #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3603 | #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3604 | #define CAN_F6R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3605 | #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3606 | #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3607 | #define CAN_F6R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 3608 | #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 3609 | #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 3610 | #define CAN_F6R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 3611 | #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 3612 | #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 3613 | #define CAN_F6R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 3614 | #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 3615 | #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 3616 | |
| mbed_official | 19:112740acecfa | 3617 | /******************* Bit definition for CAN_F7R1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 3618 | #define CAN_F7R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 3619 | #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 3620 | #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 3621 | #define CAN_F7R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 3622 | #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 3623 | #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 3624 | #define CAN_F7R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 3625 | #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 3626 | #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 3627 | #define CAN_F7R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 3628 | #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 3629 | #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 3630 | #define CAN_F7R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 3631 | #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 3632 | #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 3633 | #define CAN_F7R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 3634 | #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 3635 | #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 3636 | #define CAN_F7R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 3637 | #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 3638 | #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 3639 | #define CAN_F7R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 3640 | #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 3641 | #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 3642 | #define CAN_F7R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 3643 | #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 3644 | #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 3645 | #define CAN_F7R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 3646 | #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 3647 | #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 3648 | #define CAN_F7R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 3649 | #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 3650 | #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 3651 | #define CAN_F7R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 3652 | #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 3653 | #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 3654 | #define CAN_F7R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 3655 | #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 3656 | #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 3657 | #define CAN_F7R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 3658 | #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 3659 | #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 3660 | #define CAN_F7R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 3661 | #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 3662 | #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 3663 | #define CAN_F7R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 3664 | #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 3665 | #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 3666 | #define CAN_F7R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 3667 | #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 3668 | #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 3669 | #define CAN_F7R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 3670 | #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 3671 | #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 3672 | #define CAN_F7R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 3673 | #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 3674 | #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 3675 | #define CAN_F7R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 3676 | #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 3677 | #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 3678 | #define CAN_F7R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 3679 | #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 3680 | #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 3681 | #define CAN_F7R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 3682 | #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 3683 | #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 3684 | #define CAN_F7R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 3685 | #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3686 | #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3687 | #define CAN_F7R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3688 | #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3689 | #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3690 | #define CAN_F7R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3691 | #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3692 | #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3693 | #define CAN_F7R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3694 | #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3695 | #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3696 | #define CAN_F7R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3697 | #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3698 | #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3699 | #define CAN_F7R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3700 | #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3701 | #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3702 | #define CAN_F7R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3703 | #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3704 | #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3705 | #define CAN_F7R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 3706 | #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 3707 | #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 3708 | #define CAN_F7R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 3709 | #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 3710 | #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 3711 | #define CAN_F7R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 3712 | #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 3713 | #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 3714 | |
| mbed_official | 19:112740acecfa | 3715 | /******************* Bit definition for CAN_F8R1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 3716 | #define CAN_F8R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 3717 | #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 3718 | #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 3719 | #define CAN_F8R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 3720 | #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 3721 | #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 3722 | #define CAN_F8R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 3723 | #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 3724 | #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 3725 | #define CAN_F8R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 3726 | #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 3727 | #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 3728 | #define CAN_F8R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 3729 | #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 3730 | #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 3731 | #define CAN_F8R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 3732 | #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 3733 | #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 3734 | #define CAN_F8R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 3735 | #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 3736 | #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 3737 | #define CAN_F8R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 3738 | #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 3739 | #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 3740 | #define CAN_F8R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 3741 | #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 3742 | #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 3743 | #define CAN_F8R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 3744 | #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 3745 | #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 3746 | #define CAN_F8R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 3747 | #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 3748 | #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 3749 | #define CAN_F8R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 3750 | #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 3751 | #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 3752 | #define CAN_F8R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 3753 | #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 3754 | #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 3755 | #define CAN_F8R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 3756 | #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 3757 | #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 3758 | #define CAN_F8R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 3759 | #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 3760 | #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 3761 | #define CAN_F8R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 3762 | #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 3763 | #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 3764 | #define CAN_F8R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 3765 | #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 3766 | #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 3767 | #define CAN_F8R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 3768 | #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 3769 | #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 3770 | #define CAN_F8R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 3771 | #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 3772 | #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 3773 | #define CAN_F8R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 3774 | #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 3775 | #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 3776 | #define CAN_F8R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 3777 | #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 3778 | #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 3779 | #define CAN_F8R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 3780 | #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 3781 | #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 3782 | #define CAN_F8R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 3783 | #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3784 | #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3785 | #define CAN_F8R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3786 | #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3787 | #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3788 | #define CAN_F8R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3789 | #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3790 | #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3791 | #define CAN_F8R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3792 | #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3793 | #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3794 | #define CAN_F8R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3795 | #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3796 | #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3797 | #define CAN_F8R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3798 | #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3799 | #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3800 | #define CAN_F8R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3801 | #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3802 | #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3803 | #define CAN_F8R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 3804 | #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 3805 | #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 3806 | #define CAN_F8R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 3807 | #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 3808 | #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 3809 | #define CAN_F8R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 3810 | #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 3811 | #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 3812 | |
| mbed_official | 19:112740acecfa | 3813 | /******************* Bit definition for CAN_F9R1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 3814 | #define CAN_F9R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 3815 | #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 3816 | #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 3817 | #define CAN_F9R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 3818 | #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 3819 | #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 3820 | #define CAN_F9R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 3821 | #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 3822 | #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 3823 | #define CAN_F9R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 3824 | #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 3825 | #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 3826 | #define CAN_F9R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 3827 | #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 3828 | #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 3829 | #define CAN_F9R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 3830 | #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 3831 | #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 3832 | #define CAN_F9R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 3833 | #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 3834 | #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 3835 | #define CAN_F9R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 3836 | #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 3837 | #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 3838 | #define CAN_F9R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 3839 | #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 3840 | #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 3841 | #define CAN_F9R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 3842 | #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 3843 | #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 3844 | #define CAN_F9R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 3845 | #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 3846 | #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 3847 | #define CAN_F9R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 3848 | #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 3849 | #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 3850 | #define CAN_F9R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 3851 | #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 3852 | #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 3853 | #define CAN_F9R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 3854 | #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 3855 | #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 3856 | #define CAN_F9R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 3857 | #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 3858 | #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 3859 | #define CAN_F9R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 3860 | #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 3861 | #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 3862 | #define CAN_F9R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 3863 | #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 3864 | #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 3865 | #define CAN_F9R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 3866 | #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 3867 | #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 3868 | #define CAN_F9R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 3869 | #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 3870 | #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 3871 | #define CAN_F9R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 3872 | #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 3873 | #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 3874 | #define CAN_F9R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 3875 | #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 3876 | #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 3877 | #define CAN_F9R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 3878 | #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 3879 | #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 3880 | #define CAN_F9R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 3881 | #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3882 | #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3883 | #define CAN_F9R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3884 | #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3885 | #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3886 | #define CAN_F9R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3887 | #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3888 | #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3889 | #define CAN_F9R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3890 | #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3891 | #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3892 | #define CAN_F9R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3893 | #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3894 | #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3895 | #define CAN_F9R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3896 | #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3897 | #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3898 | #define CAN_F9R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3899 | #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3900 | #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3901 | #define CAN_F9R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 3902 | #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 3903 | #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 3904 | #define CAN_F9R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 3905 | #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 3906 | #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 3907 | #define CAN_F9R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 3908 | #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 3909 | #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 3910 | |
| mbed_official | 19:112740acecfa | 3911 | /******************* Bit definition for CAN_F10R1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 3912 | #define CAN_F10R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 3913 | #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 3914 | #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 3915 | #define CAN_F10R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 3916 | #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 3917 | #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 3918 | #define CAN_F10R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 3919 | #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 3920 | #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 3921 | #define CAN_F10R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 3922 | #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 3923 | #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 3924 | #define CAN_F10R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 3925 | #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 3926 | #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 3927 | #define CAN_F10R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 3928 | #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 3929 | #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 3930 | #define CAN_F10R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 3931 | #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 3932 | #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 3933 | #define CAN_F10R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 3934 | #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 3935 | #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 3936 | #define CAN_F10R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 3937 | #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 3938 | #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 3939 | #define CAN_F10R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 3940 | #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 3941 | #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 3942 | #define CAN_F10R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 3943 | #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 3944 | #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 3945 | #define CAN_F10R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 3946 | #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 3947 | #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 3948 | #define CAN_F10R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 3949 | #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 3950 | #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 3951 | #define CAN_F10R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 3952 | #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 3953 | #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 3954 | #define CAN_F10R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 3955 | #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 3956 | #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 3957 | #define CAN_F10R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 3958 | #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 3959 | #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 3960 | #define CAN_F10R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 3961 | #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 3962 | #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 3963 | #define CAN_F10R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 3964 | #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 3965 | #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 3966 | #define CAN_F10R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 3967 | #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 3968 | #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 3969 | #define CAN_F10R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 3970 | #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 3971 | #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 3972 | #define CAN_F10R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 3973 | #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 3974 | #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 3975 | #define CAN_F10R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 3976 | #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 3977 | #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 3978 | #define CAN_F10R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 3979 | #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 3980 | #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 3981 | #define CAN_F10R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 3982 | #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 3983 | #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 3984 | #define CAN_F10R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 3985 | #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 3986 | #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 3987 | #define CAN_F10R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 3988 | #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 3989 | #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 3990 | #define CAN_F10R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 3991 | #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 3992 | #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 3993 | #define CAN_F10R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 3994 | #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 3995 | #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 3996 | #define CAN_F10R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 3997 | #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 3998 | #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 3999 | #define CAN_F10R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4000 | #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4001 | #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4002 | #define CAN_F10R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4003 | #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4004 | #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4005 | #define CAN_F10R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4006 | #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4007 | #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4008 | |
| mbed_official | 19:112740acecfa | 4009 | /******************* Bit definition for CAN_F11R1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 4010 | #define CAN_F11R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4011 | #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4012 | #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4013 | #define CAN_F11R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4014 | #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4015 | #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4016 | #define CAN_F11R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4017 | #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4018 | #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4019 | #define CAN_F11R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 4020 | #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 4021 | #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 4022 | #define CAN_F11R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 4023 | #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 4024 | #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 4025 | #define CAN_F11R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 4026 | #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 4027 | #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 4028 | #define CAN_F11R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 4029 | #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 4030 | #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 4031 | #define CAN_F11R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 4032 | #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 4033 | #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 4034 | #define CAN_F11R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 4035 | #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 4036 | #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 4037 | #define CAN_F11R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 4038 | #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 4039 | #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 4040 | #define CAN_F11R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 4041 | #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 4042 | #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 4043 | #define CAN_F11R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 4044 | #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 4045 | #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 4046 | #define CAN_F11R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 4047 | #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 4048 | #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 4049 | #define CAN_F11R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 4050 | #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 4051 | #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 4052 | #define CAN_F11R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 4053 | #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 4054 | #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 4055 | #define CAN_F11R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 4056 | #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 4057 | #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 4058 | #define CAN_F11R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 4059 | #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 4060 | #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 4061 | #define CAN_F11R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 4062 | #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 4063 | #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 4064 | #define CAN_F11R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 4065 | #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 4066 | #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 4067 | #define CAN_F11R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 4068 | #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 4069 | #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 4070 | #define CAN_F11R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 4071 | #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 4072 | #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 4073 | #define CAN_F11R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 4074 | #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 4075 | #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 4076 | #define CAN_F11R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 4077 | #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 4078 | #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 4079 | #define CAN_F11R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 4080 | #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 4081 | #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 4082 | #define CAN_F11R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 4083 | #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 4084 | #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 4085 | #define CAN_F11R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 4086 | #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 4087 | #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 4088 | #define CAN_F11R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 4089 | #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 4090 | #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 4091 | #define CAN_F11R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 4092 | #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 4093 | #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 4094 | #define CAN_F11R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 4095 | #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 4096 | #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 4097 | #define CAN_F11R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4098 | #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4099 | #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4100 | #define CAN_F11R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4101 | #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4102 | #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4103 | #define CAN_F11R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4104 | #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4105 | #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4106 | |
| mbed_official | 19:112740acecfa | 4107 | /******************* Bit definition for CAN_F12R1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 4108 | #define CAN_F12R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4109 | #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4110 | #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4111 | #define CAN_F12R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4112 | #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4113 | #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4114 | #define CAN_F12R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4115 | #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4116 | #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4117 | #define CAN_F12R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 4118 | #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 4119 | #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 4120 | #define CAN_F12R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 4121 | #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 4122 | #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 4123 | #define CAN_F12R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 4124 | #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 4125 | #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 4126 | #define CAN_F12R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 4127 | #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 4128 | #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 4129 | #define CAN_F12R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 4130 | #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 4131 | #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 4132 | #define CAN_F12R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 4133 | #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 4134 | #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 4135 | #define CAN_F12R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 4136 | #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 4137 | #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 4138 | #define CAN_F12R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 4139 | #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 4140 | #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 4141 | #define CAN_F12R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 4142 | #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 4143 | #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 4144 | #define CAN_F12R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 4145 | #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 4146 | #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 4147 | #define CAN_F12R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 4148 | #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 4149 | #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 4150 | #define CAN_F12R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 4151 | #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 4152 | #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 4153 | #define CAN_F12R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 4154 | #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 4155 | #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 4156 | #define CAN_F12R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 4157 | #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 4158 | #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 4159 | #define CAN_F12R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 4160 | #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 4161 | #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 4162 | #define CAN_F12R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 4163 | #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 4164 | #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 4165 | #define CAN_F12R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 4166 | #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 4167 | #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 4168 | #define CAN_F12R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 4169 | #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 4170 | #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 4171 | #define CAN_F12R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 4172 | #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 4173 | #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 4174 | #define CAN_F12R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 4175 | #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 4176 | #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 4177 | #define CAN_F12R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 4178 | #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 4179 | #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 4180 | #define CAN_F12R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 4181 | #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 4182 | #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 4183 | #define CAN_F12R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 4184 | #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 4185 | #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 4186 | #define CAN_F12R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 4187 | #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 4188 | #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 4189 | #define CAN_F12R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 4190 | #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 4191 | #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 4192 | #define CAN_F12R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 4193 | #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 4194 | #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 4195 | #define CAN_F12R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4196 | #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4197 | #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4198 | #define CAN_F12R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4199 | #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4200 | #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4201 | #define CAN_F12R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4202 | #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4203 | #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4204 | |
| mbed_official | 19:112740acecfa | 4205 | /******************* Bit definition for CAN_F13R1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 4206 | #define CAN_F13R1_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4207 | #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4208 | #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4209 | #define CAN_F13R1_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4210 | #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4211 | #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4212 | #define CAN_F13R1_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4213 | #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4214 | #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4215 | #define CAN_F13R1_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 4216 | #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 4217 | #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 4218 | #define CAN_F13R1_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 4219 | #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 4220 | #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 4221 | #define CAN_F13R1_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 4222 | #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 4223 | #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 4224 | #define CAN_F13R1_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 4225 | #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 4226 | #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 4227 | #define CAN_F13R1_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 4228 | #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 4229 | #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 4230 | #define CAN_F13R1_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 4231 | #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 4232 | #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 4233 | #define CAN_F13R1_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 4234 | #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 4235 | #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 4236 | #define CAN_F13R1_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 4237 | #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 4238 | #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 4239 | #define CAN_F13R1_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 4240 | #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 4241 | #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 4242 | #define CAN_F13R1_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 4243 | #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 4244 | #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 4245 | #define CAN_F13R1_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 4246 | #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 4247 | #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 4248 | #define CAN_F13R1_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 4249 | #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 4250 | #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 4251 | #define CAN_F13R1_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 4252 | #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 4253 | #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 4254 | #define CAN_F13R1_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 4255 | #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 4256 | #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 4257 | #define CAN_F13R1_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 4258 | #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 4259 | #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 4260 | #define CAN_F13R1_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 4261 | #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 4262 | #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 4263 | #define CAN_F13R1_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 4264 | #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 4265 | #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 4266 | #define CAN_F13R1_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 4267 | #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 4268 | #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 4269 | #define CAN_F13R1_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 4270 | #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 4271 | #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 4272 | #define CAN_F13R1_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 4273 | #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 4274 | #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 4275 | #define CAN_F13R1_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 4276 | #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 4277 | #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 4278 | #define CAN_F13R1_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 4279 | #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 4280 | #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 4281 | #define CAN_F13R1_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 4282 | #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 4283 | #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 4284 | #define CAN_F13R1_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 4285 | #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 4286 | #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 4287 | #define CAN_F13R1_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 4288 | #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 4289 | #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 4290 | #define CAN_F13R1_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 4291 | #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 4292 | #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 4293 | #define CAN_F13R1_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4294 | #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4295 | #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4296 | #define CAN_F13R1_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4297 | #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4298 | #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4299 | #define CAN_F13R1_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4300 | #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4301 | #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4302 | |
| mbed_official | 19:112740acecfa | 4303 | /******************* Bit definition for CAN_F0R2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 4304 | #define CAN_F0R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4305 | #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4306 | #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4307 | #define CAN_F0R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4308 | #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4309 | #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4310 | #define CAN_F0R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4311 | #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4312 | #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4313 | #define CAN_F0R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 4314 | #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 4315 | #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 4316 | #define CAN_F0R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 4317 | #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 4318 | #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 4319 | #define CAN_F0R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 4320 | #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 4321 | #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 4322 | #define CAN_F0R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 4323 | #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 4324 | #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 4325 | #define CAN_F0R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 4326 | #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 4327 | #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 4328 | #define CAN_F0R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 4329 | #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 4330 | #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 4331 | #define CAN_F0R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 4332 | #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 4333 | #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 4334 | #define CAN_F0R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 4335 | #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 4336 | #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 4337 | #define CAN_F0R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 4338 | #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 4339 | #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 4340 | #define CAN_F0R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 4341 | #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 4342 | #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 4343 | #define CAN_F0R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 4344 | #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 4345 | #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 4346 | #define CAN_F0R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 4347 | #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 4348 | #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 4349 | #define CAN_F0R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 4350 | #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 4351 | #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 4352 | #define CAN_F0R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 4353 | #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 4354 | #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 4355 | #define CAN_F0R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 4356 | #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 4357 | #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 4358 | #define CAN_F0R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 4359 | #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 4360 | #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 4361 | #define CAN_F0R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 4362 | #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 4363 | #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 4364 | #define CAN_F0R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 4365 | #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 4366 | #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 4367 | #define CAN_F0R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 4368 | #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 4369 | #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 4370 | #define CAN_F0R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 4371 | #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 4372 | #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 4373 | #define CAN_F0R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 4374 | #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 4375 | #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 4376 | #define CAN_F0R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 4377 | #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 4378 | #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 4379 | #define CAN_F0R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 4380 | #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 4381 | #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 4382 | #define CAN_F0R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 4383 | #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 4384 | #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 4385 | #define CAN_F0R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 4386 | #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 4387 | #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 4388 | #define CAN_F0R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 4389 | #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 4390 | #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 4391 | #define CAN_F0R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4392 | #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4393 | #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4394 | #define CAN_F0R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4395 | #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4396 | #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4397 | #define CAN_F0R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4398 | #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4399 | #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4400 | |
| mbed_official | 19:112740acecfa | 4401 | /******************* Bit definition for CAN_F1R2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 4402 | #define CAN_F1R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4403 | #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4404 | #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4405 | #define CAN_F1R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4406 | #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4407 | #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4408 | #define CAN_F1R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4409 | #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4410 | #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4411 | #define CAN_F1R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 4412 | #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 4413 | #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 4414 | #define CAN_F1R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 4415 | #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 4416 | #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 4417 | #define CAN_F1R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 4418 | #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 4419 | #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 4420 | #define CAN_F1R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 4421 | #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 4422 | #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 4423 | #define CAN_F1R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 4424 | #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 4425 | #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 4426 | #define CAN_F1R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 4427 | #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 4428 | #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 4429 | #define CAN_F1R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 4430 | #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 4431 | #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 4432 | #define CAN_F1R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 4433 | #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 4434 | #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 4435 | #define CAN_F1R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 4436 | #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 4437 | #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 4438 | #define CAN_F1R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 4439 | #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 4440 | #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 4441 | #define CAN_F1R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 4442 | #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 4443 | #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 4444 | #define CAN_F1R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 4445 | #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 4446 | #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 4447 | #define CAN_F1R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 4448 | #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 4449 | #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 4450 | #define CAN_F1R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 4451 | #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 4452 | #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 4453 | #define CAN_F1R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 4454 | #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 4455 | #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 4456 | #define CAN_F1R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 4457 | #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 4458 | #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 4459 | #define CAN_F1R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 4460 | #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 4461 | #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 4462 | #define CAN_F1R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 4463 | #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 4464 | #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 4465 | #define CAN_F1R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 4466 | #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 4467 | #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 4468 | #define CAN_F1R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 4469 | #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 4470 | #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 4471 | #define CAN_F1R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 4472 | #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 4473 | #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 4474 | #define CAN_F1R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 4475 | #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 4476 | #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 4477 | #define CAN_F1R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 4478 | #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 4479 | #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 4480 | #define CAN_F1R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 4481 | #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 4482 | #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 4483 | #define CAN_F1R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 4484 | #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 4485 | #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 4486 | #define CAN_F1R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 4487 | #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 4488 | #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 4489 | #define CAN_F1R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4490 | #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4491 | #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4492 | #define CAN_F1R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4493 | #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4494 | #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4495 | #define CAN_F1R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4496 | #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4497 | #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4498 | |
| mbed_official | 19:112740acecfa | 4499 | /******************* Bit definition for CAN_F2R2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 4500 | #define CAN_F2R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4501 | #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4502 | #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4503 | #define CAN_F2R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4504 | #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4505 | #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4506 | #define CAN_F2R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4507 | #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4508 | #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4509 | #define CAN_F2R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 4510 | #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 4511 | #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 4512 | #define CAN_F2R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 4513 | #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 4514 | #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 4515 | #define CAN_F2R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 4516 | #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 4517 | #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 4518 | #define CAN_F2R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 4519 | #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 4520 | #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 4521 | #define CAN_F2R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 4522 | #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 4523 | #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 4524 | #define CAN_F2R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 4525 | #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 4526 | #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 4527 | #define CAN_F2R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 4528 | #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 4529 | #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 4530 | #define CAN_F2R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 4531 | #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 4532 | #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 4533 | #define CAN_F2R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 4534 | #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 4535 | #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 4536 | #define CAN_F2R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 4537 | #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 4538 | #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 4539 | #define CAN_F2R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 4540 | #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 4541 | #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 4542 | #define CAN_F2R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 4543 | #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 4544 | #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 4545 | #define CAN_F2R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 4546 | #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 4547 | #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 4548 | #define CAN_F2R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 4549 | #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 4550 | #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 4551 | #define CAN_F2R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 4552 | #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 4553 | #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 4554 | #define CAN_F2R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 4555 | #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 4556 | #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 4557 | #define CAN_F2R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 4558 | #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 4559 | #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 4560 | #define CAN_F2R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 4561 | #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 4562 | #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 4563 | #define CAN_F2R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 4564 | #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 4565 | #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 4566 | #define CAN_F2R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 4567 | #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 4568 | #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 4569 | #define CAN_F2R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 4570 | #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 4571 | #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 4572 | #define CAN_F2R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 4573 | #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 4574 | #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 4575 | #define CAN_F2R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 4576 | #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 4577 | #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 4578 | #define CAN_F2R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 4579 | #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 4580 | #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 4581 | #define CAN_F2R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 4582 | #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 4583 | #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 4584 | #define CAN_F2R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 4585 | #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 4586 | #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 4587 | #define CAN_F2R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4588 | #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4589 | #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4590 | #define CAN_F2R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4591 | #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4592 | #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4593 | #define CAN_F2R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4594 | #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4595 | #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4596 | |
| mbed_official | 19:112740acecfa | 4597 | /******************* Bit definition for CAN_F3R2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 4598 | #define CAN_F3R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4599 | #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4600 | #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4601 | #define CAN_F3R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4602 | #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4603 | #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4604 | #define CAN_F3R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4605 | #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4606 | #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4607 | #define CAN_F3R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 4608 | #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 4609 | #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 4610 | #define CAN_F3R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 4611 | #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 4612 | #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 4613 | #define CAN_F3R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 4614 | #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 4615 | #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 4616 | #define CAN_F3R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 4617 | #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 4618 | #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 4619 | #define CAN_F3R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 4620 | #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 4621 | #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 4622 | #define CAN_F3R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 4623 | #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 4624 | #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 4625 | #define CAN_F3R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 4626 | #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 4627 | #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 4628 | #define CAN_F3R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 4629 | #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 4630 | #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 4631 | #define CAN_F3R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 4632 | #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 4633 | #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 4634 | #define CAN_F3R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 4635 | #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 4636 | #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 4637 | #define CAN_F3R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 4638 | #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 4639 | #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 4640 | #define CAN_F3R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 4641 | #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 4642 | #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 4643 | #define CAN_F3R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 4644 | #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 4645 | #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 4646 | #define CAN_F3R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 4647 | #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 4648 | #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 4649 | #define CAN_F3R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 4650 | #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 4651 | #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 4652 | #define CAN_F3R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 4653 | #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 4654 | #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 4655 | #define CAN_F3R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 4656 | #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 4657 | #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 4658 | #define CAN_F3R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 4659 | #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 4660 | #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 4661 | #define CAN_F3R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 4662 | #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 4663 | #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 4664 | #define CAN_F3R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 4665 | #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 4666 | #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 4667 | #define CAN_F3R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 4668 | #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 4669 | #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 4670 | #define CAN_F3R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 4671 | #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 4672 | #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 4673 | #define CAN_F3R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 4674 | #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 4675 | #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 4676 | #define CAN_F3R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 4677 | #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 4678 | #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 4679 | #define CAN_F3R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 4680 | #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 4681 | #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 4682 | #define CAN_F3R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 4683 | #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 4684 | #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 4685 | #define CAN_F3R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4686 | #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4687 | #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4688 | #define CAN_F3R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4689 | #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4690 | #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4691 | #define CAN_F3R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4692 | #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4693 | #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4694 | |
| mbed_official | 19:112740acecfa | 4695 | /******************* Bit definition for CAN_F4R2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 4696 | #define CAN_F4R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4697 | #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4698 | #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4699 | #define CAN_F4R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4700 | #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4701 | #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4702 | #define CAN_F4R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4703 | #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4704 | #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4705 | #define CAN_F4R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 4706 | #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 4707 | #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 4708 | #define CAN_F4R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 4709 | #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 4710 | #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 4711 | #define CAN_F4R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 4712 | #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 4713 | #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 4714 | #define CAN_F4R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 4715 | #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 4716 | #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 4717 | #define CAN_F4R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 4718 | #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 4719 | #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 4720 | #define CAN_F4R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 4721 | #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 4722 | #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 4723 | #define CAN_F4R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 4724 | #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 4725 | #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 4726 | #define CAN_F4R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 4727 | #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 4728 | #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 4729 | #define CAN_F4R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 4730 | #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 4731 | #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 4732 | #define CAN_F4R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 4733 | #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 4734 | #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 4735 | #define CAN_F4R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 4736 | #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 4737 | #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 4738 | #define CAN_F4R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 4739 | #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 4740 | #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 4741 | #define CAN_F4R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 4742 | #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 4743 | #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 4744 | #define CAN_F4R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 4745 | #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 4746 | #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 4747 | #define CAN_F4R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 4748 | #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 4749 | #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 4750 | #define CAN_F4R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 4751 | #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 4752 | #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 4753 | #define CAN_F4R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 4754 | #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 4755 | #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 4756 | #define CAN_F4R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 4757 | #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 4758 | #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 4759 | #define CAN_F4R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 4760 | #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 4761 | #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 4762 | #define CAN_F4R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 4763 | #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 4764 | #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 4765 | #define CAN_F4R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 4766 | #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 4767 | #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 4768 | #define CAN_F4R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 4769 | #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 4770 | #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 4771 | #define CAN_F4R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 4772 | #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 4773 | #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 4774 | #define CAN_F4R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 4775 | #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 4776 | #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 4777 | #define CAN_F4R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 4778 | #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 4779 | #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 4780 | #define CAN_F4R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 4781 | #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 4782 | #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 4783 | #define CAN_F4R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4784 | #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4785 | #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4786 | #define CAN_F4R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4787 | #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4788 | #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4789 | #define CAN_F4R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4790 | #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4791 | #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4792 | |
| mbed_official | 19:112740acecfa | 4793 | /******************* Bit definition for CAN_F5R2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 4794 | #define CAN_F5R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4795 | #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4796 | #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4797 | #define CAN_F5R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4798 | #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4799 | #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4800 | #define CAN_F5R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4801 | #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4802 | #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4803 | #define CAN_F5R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 4804 | #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 4805 | #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 4806 | #define CAN_F5R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 4807 | #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 4808 | #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 4809 | #define CAN_F5R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 4810 | #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 4811 | #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 4812 | #define CAN_F5R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 4813 | #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 4814 | #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 4815 | #define CAN_F5R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 4816 | #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 4817 | #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 4818 | #define CAN_F5R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 4819 | #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 4820 | #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 4821 | #define CAN_F5R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 4822 | #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 4823 | #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 4824 | #define CAN_F5R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 4825 | #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 4826 | #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 4827 | #define CAN_F5R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 4828 | #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 4829 | #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 4830 | #define CAN_F5R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 4831 | #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 4832 | #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 4833 | #define CAN_F5R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 4834 | #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 4835 | #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 4836 | #define CAN_F5R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 4837 | #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 4838 | #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 4839 | #define CAN_F5R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 4840 | #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 4841 | #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 4842 | #define CAN_F5R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 4843 | #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 4844 | #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 4845 | #define CAN_F5R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 4846 | #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 4847 | #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 4848 | #define CAN_F5R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 4849 | #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 4850 | #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 4851 | #define CAN_F5R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 4852 | #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 4853 | #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 4854 | #define CAN_F5R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 4855 | #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 4856 | #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 4857 | #define CAN_F5R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 4858 | #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 4859 | #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 4860 | #define CAN_F5R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 4861 | #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 4862 | #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 4863 | #define CAN_F5R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 4864 | #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 4865 | #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 4866 | #define CAN_F5R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 4867 | #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 4868 | #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 4869 | #define CAN_F5R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 4870 | #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 4871 | #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 4872 | #define CAN_F5R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 4873 | #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 4874 | #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 4875 | #define CAN_F5R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 4876 | #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 4877 | #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 4878 | #define CAN_F5R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 4879 | #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 4880 | #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 4881 | #define CAN_F5R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4882 | #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4883 | #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4884 | #define CAN_F5R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4885 | #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4886 | #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4887 | #define CAN_F5R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4888 | #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4889 | #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4890 | |
| mbed_official | 19:112740acecfa | 4891 | /******************* Bit definition for CAN_F6R2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 4892 | #define CAN_F6R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4893 | #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4894 | #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4895 | #define CAN_F6R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4896 | #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4897 | #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4898 | #define CAN_F6R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4899 | #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4900 | #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4901 | #define CAN_F6R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 4902 | #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 4903 | #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 4904 | #define CAN_F6R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 4905 | #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 4906 | #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 4907 | #define CAN_F6R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 4908 | #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 4909 | #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 4910 | #define CAN_F6R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 4911 | #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 4912 | #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 4913 | #define CAN_F6R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 4914 | #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 4915 | #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 4916 | #define CAN_F6R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 4917 | #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 4918 | #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 4919 | #define CAN_F6R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 4920 | #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 4921 | #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 4922 | #define CAN_F6R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 4923 | #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 4924 | #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 4925 | #define CAN_F6R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 4926 | #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 4927 | #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 4928 | #define CAN_F6R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 4929 | #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 4930 | #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 4931 | #define CAN_F6R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 4932 | #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 4933 | #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 4934 | #define CAN_F6R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 4935 | #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 4936 | #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 4937 | #define CAN_F6R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 4938 | #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 4939 | #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 4940 | #define CAN_F6R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 4941 | #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 4942 | #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 4943 | #define CAN_F6R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 4944 | #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 4945 | #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 4946 | #define CAN_F6R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 4947 | #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 4948 | #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 4949 | #define CAN_F6R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 4950 | #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 4951 | #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 4952 | #define CAN_F6R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 4953 | #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 4954 | #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 4955 | #define CAN_F6R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 4956 | #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 4957 | #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 4958 | #define CAN_F6R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 4959 | #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 4960 | #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 4961 | #define CAN_F6R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 4962 | #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 4963 | #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 4964 | #define CAN_F6R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 4965 | #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 4966 | #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 4967 | #define CAN_F6R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 4968 | #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 4969 | #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 4970 | #define CAN_F6R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 4971 | #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 4972 | #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 4973 | #define CAN_F6R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 4974 | #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 4975 | #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 4976 | #define CAN_F6R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 4977 | #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 4978 | #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 4979 | #define CAN_F6R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 4980 | #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 4981 | #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 4982 | #define CAN_F6R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 4983 | #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 4984 | #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 4985 | #define CAN_F6R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 4986 | #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 4987 | #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 4988 | |
| mbed_official | 19:112740acecfa | 4989 | /******************* Bit definition for CAN_F7R2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 4990 | #define CAN_F7R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 4991 | #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 4992 | #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 4993 | #define CAN_F7R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 4994 | #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 4995 | #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 4996 | #define CAN_F7R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 4997 | #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 4998 | #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 4999 | #define CAN_F7R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5000 | #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5001 | #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 5002 | #define CAN_F7R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5003 | #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5004 | #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 5005 | #define CAN_F7R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 5006 | #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 5007 | #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 5008 | #define CAN_F7R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 5009 | #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 5010 | #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 5011 | #define CAN_F7R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 5012 | #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 5013 | #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 5014 | #define CAN_F7R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 5015 | #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 5016 | #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 5017 | #define CAN_F7R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 5018 | #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 5019 | #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 5020 | #define CAN_F7R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 5021 | #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 5022 | #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 5023 | #define CAN_F7R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 5024 | #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 5025 | #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 5026 | #define CAN_F7R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 5027 | #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 5028 | #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 5029 | #define CAN_F7R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 5030 | #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 5031 | #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 5032 | #define CAN_F7R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 5033 | #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 5034 | #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 5035 | #define CAN_F7R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 5036 | #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 5037 | #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 5038 | #define CAN_F7R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 5039 | #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 5040 | #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 5041 | #define CAN_F7R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 5042 | #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 5043 | #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 5044 | #define CAN_F7R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 5045 | #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 5046 | #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 5047 | #define CAN_F7R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 5048 | #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 5049 | #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 5050 | #define CAN_F7R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 5051 | #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 5052 | #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 5053 | #define CAN_F7R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 5054 | #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 5055 | #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 5056 | #define CAN_F7R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 5057 | #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 5058 | #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 5059 | #define CAN_F7R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 5060 | #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 5061 | #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 5062 | #define CAN_F7R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 5063 | #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 5064 | #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 5065 | #define CAN_F7R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 5066 | #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 5067 | #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 5068 | #define CAN_F7R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 5069 | #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 5070 | #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 5071 | #define CAN_F7R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 5072 | #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 5073 | #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 5074 | #define CAN_F7R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 5075 | #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 5076 | #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 5077 | #define CAN_F7R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 5078 | #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 5079 | #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 5080 | #define CAN_F7R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 5081 | #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 5082 | #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 5083 | #define CAN_F7R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 5084 | #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 5085 | #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 5086 | |
| mbed_official | 19:112740acecfa | 5087 | /******************* Bit definition for CAN_F8R2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 5088 | #define CAN_F8R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5089 | #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5090 | #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 5091 | #define CAN_F8R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5092 | #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5093 | #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 5094 | #define CAN_F8R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5095 | #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5096 | #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 5097 | #define CAN_F8R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5098 | #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5099 | #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 5100 | #define CAN_F8R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5101 | #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5102 | #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 5103 | #define CAN_F8R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 5104 | #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 5105 | #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 5106 | #define CAN_F8R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 5107 | #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 5108 | #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 5109 | #define CAN_F8R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 5110 | #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 5111 | #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 5112 | #define CAN_F8R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 5113 | #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 5114 | #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 5115 | #define CAN_F8R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 5116 | #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 5117 | #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 5118 | #define CAN_F8R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 5119 | #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 5120 | #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 5121 | #define CAN_F8R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 5122 | #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 5123 | #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 5124 | #define CAN_F8R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 5125 | #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 5126 | #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 5127 | #define CAN_F8R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 5128 | #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 5129 | #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 5130 | #define CAN_F8R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 5131 | #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 5132 | #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 5133 | #define CAN_F8R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 5134 | #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 5135 | #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 5136 | #define CAN_F8R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 5137 | #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 5138 | #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 5139 | #define CAN_F8R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 5140 | #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 5141 | #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 5142 | #define CAN_F8R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 5143 | #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 5144 | #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 5145 | #define CAN_F8R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 5146 | #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 5147 | #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 5148 | #define CAN_F8R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 5149 | #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 5150 | #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 5151 | #define CAN_F8R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 5152 | #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 5153 | #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 5154 | #define CAN_F8R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 5155 | #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 5156 | #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 5157 | #define CAN_F8R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 5158 | #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 5159 | #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 5160 | #define CAN_F8R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 5161 | #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 5162 | #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 5163 | #define CAN_F8R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 5164 | #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 5165 | #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 5166 | #define CAN_F8R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 5167 | #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 5168 | #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 5169 | #define CAN_F8R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 5170 | #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 5171 | #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 5172 | #define CAN_F8R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 5173 | #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 5174 | #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 5175 | #define CAN_F8R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 5176 | #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 5177 | #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 5178 | #define CAN_F8R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 5179 | #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 5180 | #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 5181 | #define CAN_F8R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 5182 | #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 5183 | #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 5184 | |
| mbed_official | 19:112740acecfa | 5185 | /******************* Bit definition for CAN_F9R2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 5186 | #define CAN_F9R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5187 | #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5188 | #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 5189 | #define CAN_F9R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5190 | #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5191 | #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 5192 | #define CAN_F9R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5193 | #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5194 | #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 5195 | #define CAN_F9R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5196 | #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5197 | #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 5198 | #define CAN_F9R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5199 | #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5200 | #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 5201 | #define CAN_F9R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 5202 | #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 5203 | #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 5204 | #define CAN_F9R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 5205 | #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 5206 | #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 5207 | #define CAN_F9R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 5208 | #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 5209 | #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 5210 | #define CAN_F9R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 5211 | #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 5212 | #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 5213 | #define CAN_F9R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 5214 | #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 5215 | #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 5216 | #define CAN_F9R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 5217 | #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 5218 | #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 5219 | #define CAN_F9R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 5220 | #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 5221 | #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 5222 | #define CAN_F9R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 5223 | #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 5224 | #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 5225 | #define CAN_F9R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 5226 | #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 5227 | #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 5228 | #define CAN_F9R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 5229 | #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 5230 | #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 5231 | #define CAN_F9R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 5232 | #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 5233 | #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 5234 | #define CAN_F9R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 5235 | #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 5236 | #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 5237 | #define CAN_F9R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 5238 | #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 5239 | #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 5240 | #define CAN_F9R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 5241 | #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 5242 | #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 5243 | #define CAN_F9R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 5244 | #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 5245 | #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 5246 | #define CAN_F9R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 5247 | #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 5248 | #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 5249 | #define CAN_F9R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 5250 | #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 5251 | #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 5252 | #define CAN_F9R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 5253 | #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 5254 | #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 5255 | #define CAN_F9R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 5256 | #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 5257 | #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 5258 | #define CAN_F9R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 5259 | #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 5260 | #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 5261 | #define CAN_F9R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 5262 | #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 5263 | #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 5264 | #define CAN_F9R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 5265 | #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 5266 | #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 5267 | #define CAN_F9R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 5268 | #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 5269 | #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 5270 | #define CAN_F9R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 5271 | #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 5272 | #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 5273 | #define CAN_F9R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 5274 | #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 5275 | #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 5276 | #define CAN_F9R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 5277 | #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 5278 | #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 5279 | #define CAN_F9R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 5280 | #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 5281 | #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 5282 | |
| mbed_official | 19:112740acecfa | 5283 | /******************* Bit definition for CAN_F10R2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5284 | #define CAN_F10R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5285 | #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5286 | #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 5287 | #define CAN_F10R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5288 | #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5289 | #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 5290 | #define CAN_F10R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5291 | #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5292 | #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 5293 | #define CAN_F10R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5294 | #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5295 | #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 5296 | #define CAN_F10R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5297 | #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5298 | #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 5299 | #define CAN_F10R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 5300 | #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 5301 | #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 5302 | #define CAN_F10R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 5303 | #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 5304 | #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 5305 | #define CAN_F10R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 5306 | #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 5307 | #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 5308 | #define CAN_F10R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 5309 | #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 5310 | #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 5311 | #define CAN_F10R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 5312 | #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 5313 | #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 5314 | #define CAN_F10R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 5315 | #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 5316 | #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 5317 | #define CAN_F10R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 5318 | #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 5319 | #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 5320 | #define CAN_F10R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 5321 | #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 5322 | #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 5323 | #define CAN_F10R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 5324 | #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 5325 | #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 5326 | #define CAN_F10R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 5327 | #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 5328 | #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 5329 | #define CAN_F10R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 5330 | #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 5331 | #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 5332 | #define CAN_F10R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 5333 | #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 5334 | #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 5335 | #define CAN_F10R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 5336 | #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 5337 | #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 5338 | #define CAN_F10R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 5339 | #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 5340 | #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 5341 | #define CAN_F10R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 5342 | #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 5343 | #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 5344 | #define CAN_F10R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 5345 | #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 5346 | #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 5347 | #define CAN_F10R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 5348 | #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 5349 | #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 5350 | #define CAN_F10R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 5351 | #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 5352 | #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 5353 | #define CAN_F10R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 5354 | #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 5355 | #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 5356 | #define CAN_F10R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 5357 | #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 5358 | #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 5359 | #define CAN_F10R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 5360 | #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 5361 | #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 5362 | #define CAN_F10R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 5363 | #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 5364 | #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 5365 | #define CAN_F10R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 5366 | #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 5367 | #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 5368 | #define CAN_F10R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 5369 | #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 5370 | #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 5371 | #define CAN_F10R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 5372 | #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 5373 | #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 5374 | #define CAN_F10R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 5375 | #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 5376 | #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 5377 | #define CAN_F10R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 5378 | #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 5379 | #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 5380 | |
| mbed_official | 19:112740acecfa | 5381 | /******************* Bit definition for CAN_F11R2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5382 | #define CAN_F11R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5383 | #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5384 | #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 5385 | #define CAN_F11R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5386 | #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5387 | #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 5388 | #define CAN_F11R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5389 | #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5390 | #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 5391 | #define CAN_F11R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5392 | #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5393 | #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 5394 | #define CAN_F11R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5395 | #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5396 | #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 5397 | #define CAN_F11R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 5398 | #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 5399 | #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 5400 | #define CAN_F11R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 5401 | #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 5402 | #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 5403 | #define CAN_F11R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 5404 | #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 5405 | #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 5406 | #define CAN_F11R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 5407 | #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 5408 | #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 5409 | #define CAN_F11R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 5410 | #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 5411 | #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 5412 | #define CAN_F11R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 5413 | #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 5414 | #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 5415 | #define CAN_F11R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 5416 | #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 5417 | #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 5418 | #define CAN_F11R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 5419 | #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 5420 | #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 5421 | #define CAN_F11R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 5422 | #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 5423 | #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 5424 | #define CAN_F11R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 5425 | #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 5426 | #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 5427 | #define CAN_F11R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 5428 | #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 5429 | #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 5430 | #define CAN_F11R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 5431 | #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 5432 | #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 5433 | #define CAN_F11R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 5434 | #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 5435 | #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 5436 | #define CAN_F11R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 5437 | #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 5438 | #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 5439 | #define CAN_F11R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 5440 | #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 5441 | #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 5442 | #define CAN_F11R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 5443 | #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 5444 | #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 5445 | #define CAN_F11R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 5446 | #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 5447 | #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 5448 | #define CAN_F11R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 5449 | #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 5450 | #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 5451 | #define CAN_F11R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 5452 | #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 5453 | #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 5454 | #define CAN_F11R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 5455 | #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 5456 | #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 5457 | #define CAN_F11R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 5458 | #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 5459 | #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 5460 | #define CAN_F11R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 5461 | #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 5462 | #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 5463 | #define CAN_F11R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 5464 | #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 5465 | #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 5466 | #define CAN_F11R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 5467 | #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 5468 | #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 5469 | #define CAN_F11R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 5470 | #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 5471 | #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 5472 | #define CAN_F11R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 5473 | #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 5474 | #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 5475 | #define CAN_F11R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 5476 | #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 5477 | #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 5478 | |
| mbed_official | 19:112740acecfa | 5479 | /******************* Bit definition for CAN_F12R2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5480 | #define CAN_F12R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5481 | #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5482 | #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 5483 | #define CAN_F12R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5484 | #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5485 | #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 5486 | #define CAN_F12R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5487 | #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5488 | #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 5489 | #define CAN_F12R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5490 | #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5491 | #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 5492 | #define CAN_F12R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5493 | #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5494 | #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 5495 | #define CAN_F12R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 5496 | #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 5497 | #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 5498 | #define CAN_F12R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 5499 | #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 5500 | #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 5501 | #define CAN_F12R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 5502 | #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 5503 | #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 5504 | #define CAN_F12R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 5505 | #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 5506 | #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 5507 | #define CAN_F12R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 5508 | #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 5509 | #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 5510 | #define CAN_F12R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 5511 | #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 5512 | #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 5513 | #define CAN_F12R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 5514 | #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 5515 | #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 5516 | #define CAN_F12R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 5517 | #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 5518 | #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 5519 | #define CAN_F12R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 5520 | #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 5521 | #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 5522 | #define CAN_F12R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 5523 | #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 5524 | #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 5525 | #define CAN_F12R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 5526 | #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 5527 | #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 5528 | #define CAN_F12R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 5529 | #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 5530 | #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 5531 | #define CAN_F12R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 5532 | #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 5533 | #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 5534 | #define CAN_F12R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 5535 | #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 5536 | #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 5537 | #define CAN_F12R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 5538 | #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 5539 | #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 5540 | #define CAN_F12R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 5541 | #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 5542 | #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 5543 | #define CAN_F12R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 5544 | #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 5545 | #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 5546 | #define CAN_F12R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 5547 | #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 5548 | #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 5549 | #define CAN_F12R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 5550 | #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 5551 | #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 5552 | #define CAN_F12R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 5553 | #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 5554 | #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 5555 | #define CAN_F12R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 5556 | #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 5557 | #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 5558 | #define CAN_F12R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 5559 | #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 5560 | #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 5561 | #define CAN_F12R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 5562 | #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 5563 | #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 5564 | #define CAN_F12R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 5565 | #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 5566 | #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 5567 | #define CAN_F12R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 5568 | #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 5569 | #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 5570 | #define CAN_F12R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 5571 | #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 5572 | #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 5573 | #define CAN_F12R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 5574 | #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 5575 | #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 5576 | |
| mbed_official | 19:112740acecfa | 5577 | /******************* Bit definition for CAN_F13R2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5578 | #define CAN_F13R2_FB0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5579 | #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5580 | #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 5581 | #define CAN_F13R2_FB1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5582 | #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5583 | #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 5584 | #define CAN_F13R2_FB2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5585 | #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5586 | #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 5587 | #define CAN_F13R2_FB3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5588 | #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5589 | #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 5590 | #define CAN_F13R2_FB4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5591 | #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5592 | #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 5593 | #define CAN_F13R2_FB5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 5594 | #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 5595 | #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 5596 | #define CAN_F13R2_FB6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 5597 | #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 5598 | #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 5599 | #define CAN_F13R2_FB7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 5600 | #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 5601 | #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 5602 | #define CAN_F13R2_FB8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 5603 | #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 5604 | #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 5605 | #define CAN_F13R2_FB9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 5606 | #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 5607 | #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 5608 | #define CAN_F13R2_FB10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 5609 | #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 5610 | #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 167:e84263d55307 | 5611 | #define CAN_F13R2_FB11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 5612 | #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 5613 | #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 167:e84263d55307 | 5614 | #define CAN_F13R2_FB12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 5615 | #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 5616 | #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 167:e84263d55307 | 5617 | #define CAN_F13R2_FB13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 5618 | #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 5619 | #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 167:e84263d55307 | 5620 | #define CAN_F13R2_FB14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 5621 | #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 5622 | #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 167:e84263d55307 | 5623 | #define CAN_F13R2_FB15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 5624 | #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 5625 | #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 167:e84263d55307 | 5626 | #define CAN_F13R2_FB16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 5627 | #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 5628 | #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 167:e84263d55307 | 5629 | #define CAN_F13R2_FB17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 5630 | #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 5631 | #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 167:e84263d55307 | 5632 | #define CAN_F13R2_FB18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 5633 | #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 5634 | #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 167:e84263d55307 | 5635 | #define CAN_F13R2_FB19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 5636 | #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 5637 | #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 167:e84263d55307 | 5638 | #define CAN_F13R2_FB20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 5639 | #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 5640 | #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 167:e84263d55307 | 5641 | #define CAN_F13R2_FB21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 5642 | #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 5643 | #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 167:e84263d55307 | 5644 | #define CAN_F13R2_FB22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 5645 | #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 5646 | #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 167:e84263d55307 | 5647 | #define CAN_F13R2_FB23_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 5648 | #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 5649 | #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 167:e84263d55307 | 5650 | #define CAN_F13R2_FB24_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 5651 | #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 5652 | #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 167:e84263d55307 | 5653 | #define CAN_F13R2_FB25_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 5654 | #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 5655 | #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 167:e84263d55307 | 5656 | #define CAN_F13R2_FB26_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 5657 | #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 5658 | #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 167:e84263d55307 | 5659 | #define CAN_F13R2_FB27_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 5660 | #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 5661 | #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 167:e84263d55307 | 5662 | #define CAN_F13R2_FB28_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 5663 | #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 5664 | #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 167:e84263d55307 | 5665 | #define CAN_F13R2_FB29_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 5666 | #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 5667 | #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 167:e84263d55307 | 5668 | #define CAN_F13R2_FB30_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 5669 | #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 5670 | #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 167:e84263d55307 | 5671 | #define CAN_F13R2_FB31_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 5672 | #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 5673 | #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */ |
| mbed_official | 19:112740acecfa | 5674 | |
| mbed_official | 19:112740acecfa | 5675 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 5676 | /* */ |
| mbed_official | 19:112740acecfa | 5677 | /* CRC calculation unit */ |
| mbed_official | 19:112740acecfa | 5678 | /* */ |
| mbed_official | 19:112740acecfa | 5679 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 5680 | /******************* Bit definition for CRC_DR register *********************/ |
| AnnaBridge | 167:e84263d55307 | 5681 | #define CRC_DR_DR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5682 | #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 5683 | #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
| mbed_official | 19:112740acecfa | 5684 | |
| mbed_official | 19:112740acecfa | 5685 | |
| mbed_official | 19:112740acecfa | 5686 | /******************* Bit definition for CRC_IDR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 5687 | #define CRC_IDR_IDR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5688 | #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 5689 | #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ |
| mbed_official | 19:112740acecfa | 5690 | |
| mbed_official | 19:112740acecfa | 5691 | |
| mbed_official | 19:112740acecfa | 5692 | /******************** Bit definition for CRC_CR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 5693 | #define CRC_CR_RESET_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5694 | #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5695 | #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ |
| mbed_official | 19:112740acecfa | 5696 | |
| mbed_official | 19:112740acecfa | 5697 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 5698 | /* */ |
| mbed_official | 19:112740acecfa | 5699 | /* Digital to Analog Converter */ |
| mbed_official | 19:112740acecfa | 5700 | /* */ |
| mbed_official | 19:112740acecfa | 5701 | /******************************************************************************/ |
| AnnaBridge | 167:e84263d55307 | 5702 | /* |
| AnnaBridge | 167:e84263d55307 | 5703 | * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) |
| AnnaBridge | 167:e84263d55307 | 5704 | */ |
| AnnaBridge | 167:e84263d55307 | 5705 | #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */ |
| mbed_official | 19:112740acecfa | 5706 | /******************** Bit definition for DAC_CR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 5707 | #define DAC_CR_EN1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5708 | #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5709 | #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ |
| AnnaBridge | 167:e84263d55307 | 5710 | #define DAC_CR_BOFF1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5711 | #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5712 | #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */ |
| AnnaBridge | 167:e84263d55307 | 5713 | #define DAC_CR_TEN1_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5714 | #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5715 | #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ |
| AnnaBridge | 167:e84263d55307 | 5716 | |
| AnnaBridge | 167:e84263d55307 | 5717 | #define DAC_CR_TSEL1_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5718 | #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 167:e84263d55307 | 5719 | #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ |
| AnnaBridge | 167:e84263d55307 | 5720 | #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5721 | #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5722 | #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 5723 | |
| AnnaBridge | 167:e84263d55307 | 5724 | #define DAC_CR_WAVE1_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 5725 | #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 5726 | #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
| AnnaBridge | 167:e84263d55307 | 5727 | #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 5728 | #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 5729 | |
| AnnaBridge | 167:e84263d55307 | 5730 | #define DAC_CR_MAMP1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 5731 | #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 5732 | #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
| AnnaBridge | 167:e84263d55307 | 5733 | #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 5734 | #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 5735 | #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 5736 | #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 5737 | |
| AnnaBridge | 167:e84263d55307 | 5738 | #define DAC_CR_DMAEN1_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 5739 | #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 5740 | #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ |
| AnnaBridge | 167:e84263d55307 | 5741 | #define DAC_CR_DMAUDRIE1_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 5742 | #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 5743 | #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/ |
| AnnaBridge | 167:e84263d55307 | 5744 | #define DAC_CR_EN2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 5745 | #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 5746 | #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ |
| AnnaBridge | 167:e84263d55307 | 5747 | #define DAC_CR_BOFF2_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 5748 | #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 5749 | #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */ |
| AnnaBridge | 167:e84263d55307 | 5750 | #define DAC_CR_TEN2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 5751 | #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 5752 | #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ |
| AnnaBridge | 167:e84263d55307 | 5753 | |
| AnnaBridge | 167:e84263d55307 | 5754 | #define DAC_CR_TSEL2_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 5755 | #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ |
| AnnaBridge | 167:e84263d55307 | 5756 | #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ |
| AnnaBridge | 167:e84263d55307 | 5757 | #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 5758 | #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 5759 | #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 5760 | |
| AnnaBridge | 167:e84263d55307 | 5761 | #define DAC_CR_WAVE2_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 5762 | #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 167:e84263d55307 | 5763 | #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
| AnnaBridge | 167:e84263d55307 | 5764 | #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 5765 | #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 5766 | |
| AnnaBridge | 167:e84263d55307 | 5767 | #define DAC_CR_MAMP2_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 5768 | #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 5769 | #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
| AnnaBridge | 167:e84263d55307 | 5770 | #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 5771 | #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 5772 | #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 5773 | #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 5774 | |
| AnnaBridge | 167:e84263d55307 | 5775 | #define DAC_CR_DMAEN2_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 5776 | #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 5777 | #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ |
| AnnaBridge | 167:e84263d55307 | 5778 | #define DAC_CR_DMAUDRIE2_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 5779 | #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 5780 | #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/ |
| mbed_official | 19:112740acecfa | 5781 | |
| mbed_official | 19:112740acecfa | 5782 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5783 | #define DAC_SWTRIGR_SWTRIG1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5784 | #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5785 | #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ |
| AnnaBridge | 167:e84263d55307 | 5786 | #define DAC_SWTRIGR_SWTRIG2_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5787 | #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5788 | #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ |
| mbed_official | 19:112740acecfa | 5789 | |
| mbed_official | 19:112740acecfa | 5790 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5791 | #define DAC_DHR12R1_DACC1DHR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5792 | #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 5793 | #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ |
| mbed_official | 19:112740acecfa | 5794 | |
| mbed_official | 19:112740acecfa | 5795 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5796 | #define DAC_DHR12L1_DACC1DHR_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5797 | #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 167:e84263d55307 | 5798 | #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ |
| mbed_official | 19:112740acecfa | 5799 | |
| mbed_official | 19:112740acecfa | 5800 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5801 | #define DAC_DHR8R1_DACC1DHR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5802 | #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 5803 | #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ |
| mbed_official | 19:112740acecfa | 5804 | |
| mbed_official | 19:112740acecfa | 5805 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5806 | #define DAC_DHR12R2_DACC2DHR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5807 | #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 5808 | #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ |
| mbed_official | 19:112740acecfa | 5809 | |
| mbed_official | 19:112740acecfa | 5810 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5811 | #define DAC_DHR12L2_DACC2DHR_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5812 | #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 167:e84263d55307 | 5813 | #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ |
| mbed_official | 19:112740acecfa | 5814 | |
| mbed_official | 19:112740acecfa | 5815 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5816 | #define DAC_DHR8R2_DACC2DHR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5817 | #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 5818 | #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ |
| mbed_official | 19:112740acecfa | 5819 | |
| mbed_official | 19:112740acecfa | 5820 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5821 | #define DAC_DHR12RD_DACC1DHR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5822 | #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 5823 | #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ |
| AnnaBridge | 167:e84263d55307 | 5824 | #define DAC_DHR12RD_DACC2DHR_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 5825 | #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 5826 | #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ |
| mbed_official | 19:112740acecfa | 5827 | |
| mbed_official | 19:112740acecfa | 5828 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5829 | #define DAC_DHR12LD_DACC1DHR_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5830 | #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 167:e84263d55307 | 5831 | #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ |
| AnnaBridge | 167:e84263d55307 | 5832 | #define DAC_DHR12LD_DACC2DHR_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 5833 | #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ |
| AnnaBridge | 167:e84263d55307 | 5834 | #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ |
| mbed_official | 19:112740acecfa | 5835 | |
| mbed_official | 19:112740acecfa | 5836 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5837 | #define DAC_DHR8RD_DACC1DHR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5838 | #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 5839 | #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ |
| AnnaBridge | 167:e84263d55307 | 5840 | #define DAC_DHR8RD_DACC2DHR_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 5841 | #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 5842 | #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ |
| mbed_official | 19:112740acecfa | 5843 | |
| mbed_official | 19:112740acecfa | 5844 | /******************* Bit definition for DAC_DOR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 5845 | #define DAC_DOR1_DACC1DOR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5846 | #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 5847 | #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ |
| mbed_official | 19:112740acecfa | 5848 | |
| mbed_official | 19:112740acecfa | 5849 | /******************* Bit definition for DAC_DOR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 5850 | #define DAC_DOR2_DACC2DOR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5851 | #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 5852 | #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ |
| mbed_official | 19:112740acecfa | 5853 | |
| mbed_official | 19:112740acecfa | 5854 | /******************** Bit definition for DAC_SR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 5855 | #define DAC_SR_DMAUDR1_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 5856 | #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 5857 | #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ |
| AnnaBridge | 167:e84263d55307 | 5858 | #define DAC_SR_DMAUDR2_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 5859 | #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 5860 | #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ |
| mbed_official | 19:112740acecfa | 5861 | |
| mbed_official | 19:112740acecfa | 5862 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 5863 | /* */ |
| mbed_official | 19:112740acecfa | 5864 | /* DCMI */ |
| mbed_official | 19:112740acecfa | 5865 | /* */ |
| mbed_official | 19:112740acecfa | 5866 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 5867 | /******************** Bits definition for DCMI_CR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5868 | #define DCMI_CR_CAPTURE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5869 | #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5870 | #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk |
| AnnaBridge | 167:e84263d55307 | 5871 | #define DCMI_CR_CM_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5872 | #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5873 | #define DCMI_CR_CM DCMI_CR_CM_Msk |
| AnnaBridge | 167:e84263d55307 | 5874 | #define DCMI_CR_CROP_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5875 | #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5876 | #define DCMI_CR_CROP DCMI_CR_CROP_Msk |
| AnnaBridge | 167:e84263d55307 | 5877 | #define DCMI_CR_JPEG_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5878 | #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5879 | #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk |
| AnnaBridge | 167:e84263d55307 | 5880 | #define DCMI_CR_ESS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5881 | #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5882 | #define DCMI_CR_ESS DCMI_CR_ESS_Msk |
| AnnaBridge | 167:e84263d55307 | 5883 | #define DCMI_CR_PCKPOL_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 5884 | #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 5885 | #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk |
| AnnaBridge | 167:e84263d55307 | 5886 | #define DCMI_CR_HSPOL_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 5887 | #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 5888 | #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk |
| AnnaBridge | 167:e84263d55307 | 5889 | #define DCMI_CR_VSPOL_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 5890 | #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 5891 | #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk |
| AnnaBridge | 167:e84263d55307 | 5892 | #define DCMI_CR_FCRC_0 0x00000100U |
| AnnaBridge | 167:e84263d55307 | 5893 | #define DCMI_CR_FCRC_1 0x00000200U |
| AnnaBridge | 167:e84263d55307 | 5894 | #define DCMI_CR_EDM_0 0x00000400U |
| AnnaBridge | 167:e84263d55307 | 5895 | #define DCMI_CR_EDM_1 0x00000800U |
| AnnaBridge | 167:e84263d55307 | 5896 | #define DCMI_CR_OUTEN_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 5897 | #define DCMI_CR_OUTEN_Msk (0x1U << DCMI_CR_OUTEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 5898 | #define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk |
| AnnaBridge | 167:e84263d55307 | 5899 | #define DCMI_CR_ENABLE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 5900 | #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 5901 | #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk |
| AnnaBridge | 167:e84263d55307 | 5902 | #define DCMI_CR_BSM_0 0x00010000U |
| AnnaBridge | 167:e84263d55307 | 5903 | #define DCMI_CR_BSM_1 0x00020000U |
| AnnaBridge | 167:e84263d55307 | 5904 | #define DCMI_CR_OEBS_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 5905 | #define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 5906 | #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk |
| AnnaBridge | 167:e84263d55307 | 5907 | #define DCMI_CR_LSM_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 5908 | #define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 5909 | #define DCMI_CR_LSM DCMI_CR_LSM_Msk |
| AnnaBridge | 167:e84263d55307 | 5910 | #define DCMI_CR_OELS_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 5911 | #define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 5912 | #define DCMI_CR_OELS DCMI_CR_OELS_Msk |
| mbed_official | 19:112740acecfa | 5913 | |
| mbed_official | 19:112740acecfa | 5914 | /******************** Bits definition for DCMI_SR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 5915 | #define DCMI_SR_HSYNC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5916 | #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5917 | #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk |
| AnnaBridge | 167:e84263d55307 | 5918 | #define DCMI_SR_VSYNC_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5919 | #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5920 | #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk |
| AnnaBridge | 167:e84263d55307 | 5921 | #define DCMI_SR_FNE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5922 | #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5923 | #define DCMI_SR_FNE DCMI_SR_FNE_Msk |
| <> | 144:ef7eb2e8f9f7 | 5924 | |
| <> | 144:ef7eb2e8f9f7 | 5925 | /******************** Bits definition for DCMI_RIS register *****************/ |
| AnnaBridge | 167:e84263d55307 | 5926 | #define DCMI_RIS_FRAME_RIS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5927 | #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5928 | #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk |
| AnnaBridge | 167:e84263d55307 | 5929 | #define DCMI_RIS_OVR_RIS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5930 | #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5931 | #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk |
| AnnaBridge | 167:e84263d55307 | 5932 | #define DCMI_RIS_ERR_RIS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5933 | #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5934 | #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk |
| AnnaBridge | 167:e84263d55307 | 5935 | #define DCMI_RIS_VSYNC_RIS_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5936 | #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5937 | #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk |
| AnnaBridge | 167:e84263d55307 | 5938 | #define DCMI_RIS_LINE_RIS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5939 | #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5940 | #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk |
| <> | 144:ef7eb2e8f9f7 | 5941 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 5942 | #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS |
| <> | 144:ef7eb2e8f9f7 | 5943 | #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS |
| <> | 144:ef7eb2e8f9f7 | 5944 | #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS |
| <> | 144:ef7eb2e8f9f7 | 5945 | #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS |
| <> | 144:ef7eb2e8f9f7 | 5946 | #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS |
| <> | 144:ef7eb2e8f9f7 | 5947 | #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS |
| mbed_official | 19:112740acecfa | 5948 | |
| mbed_official | 19:112740acecfa | 5949 | /******************** Bits definition for DCMI_IER register *****************/ |
| AnnaBridge | 167:e84263d55307 | 5950 | #define DCMI_IER_FRAME_IE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5951 | #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5952 | #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk |
| AnnaBridge | 167:e84263d55307 | 5953 | #define DCMI_IER_OVR_IE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5954 | #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5955 | #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk |
| AnnaBridge | 167:e84263d55307 | 5956 | #define DCMI_IER_ERR_IE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5957 | #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5958 | #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk |
| AnnaBridge | 167:e84263d55307 | 5959 | #define DCMI_IER_VSYNC_IE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5960 | #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5961 | #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk |
| AnnaBridge | 167:e84263d55307 | 5962 | #define DCMI_IER_LINE_IE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5963 | #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5964 | #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk |
| <> | 144:ef7eb2e8f9f7 | 5965 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 5966 | #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE |
| AnnaBridge | 167:e84263d55307 | 5967 | |
| <> | 144:ef7eb2e8f9f7 | 5968 | /******************** Bits definition for DCMI_MIS register *****************/ |
| AnnaBridge | 167:e84263d55307 | 5969 | #define DCMI_MIS_FRAME_MIS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5970 | #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5971 | #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk |
| AnnaBridge | 167:e84263d55307 | 5972 | #define DCMI_MIS_OVR_MIS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5973 | #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5974 | #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk |
| AnnaBridge | 167:e84263d55307 | 5975 | #define DCMI_MIS_ERR_MIS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 5976 | #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 5977 | #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk |
| AnnaBridge | 167:e84263d55307 | 5978 | #define DCMI_MIS_VSYNC_MIS_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 5979 | #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 5980 | #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk |
| AnnaBridge | 167:e84263d55307 | 5981 | #define DCMI_MIS_LINE_MIS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 5982 | #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 5983 | #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk |
| <> | 144:ef7eb2e8f9f7 | 5984 | |
| <> | 144:ef7eb2e8f9f7 | 5985 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 5986 | #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS |
| <> | 144:ef7eb2e8f9f7 | 5987 | #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS |
| <> | 144:ef7eb2e8f9f7 | 5988 | #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS |
| <> | 144:ef7eb2e8f9f7 | 5989 | #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS |
| <> | 144:ef7eb2e8f9f7 | 5990 | #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS |
| mbed_official | 19:112740acecfa | 5991 | |
| mbed_official | 19:112740acecfa | 5992 | /******************** Bits definition for DCMI_ICR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 5993 | #define DCMI_ICR_FRAME_ISC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 5994 | #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 5995 | #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk |
| AnnaBridge | 167:e84263d55307 | 5996 | #define DCMI_ICR_OVR_ISC_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 5997 | #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 5998 | #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk |
| AnnaBridge | 167:e84263d55307 | 5999 | #define DCMI_ICR_ERR_ISC_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6000 | #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6001 | #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk |
| AnnaBridge | 167:e84263d55307 | 6002 | #define DCMI_ICR_VSYNC_ISC_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6003 | #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6004 | #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk |
| AnnaBridge | 167:e84263d55307 | 6005 | #define DCMI_ICR_LINE_ISC_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6006 | #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6007 | #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk |
| <> | 144:ef7eb2e8f9f7 | 6008 | |
| <> | 144:ef7eb2e8f9f7 | 6009 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 6010 | #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC |
| <> | 144:ef7eb2e8f9f7 | 6011 | |
| <> | 144:ef7eb2e8f9f7 | 6012 | /******************** Bits definition for DCMI_ESCR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 6013 | #define DCMI_ESCR_FSC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6014 | #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 6015 | #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk |
| AnnaBridge | 167:e84263d55307 | 6016 | #define DCMI_ESCR_LSC_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6017 | #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 6018 | #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk |
| AnnaBridge | 167:e84263d55307 | 6019 | #define DCMI_ESCR_LEC_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6020 | #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 6021 | #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk |
| AnnaBridge | 167:e84263d55307 | 6022 | #define DCMI_ESCR_FEC_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 6023 | #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 6024 | #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk |
| <> | 144:ef7eb2e8f9f7 | 6025 | |
| <> | 144:ef7eb2e8f9f7 | 6026 | /******************** Bits definition for DCMI_ESUR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 6027 | #define DCMI_ESUR_FSU_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6028 | #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 6029 | #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk |
| AnnaBridge | 167:e84263d55307 | 6030 | #define DCMI_ESUR_LSU_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6031 | #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 6032 | #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk |
| AnnaBridge | 167:e84263d55307 | 6033 | #define DCMI_ESUR_LEU_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6034 | #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 6035 | #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk |
| AnnaBridge | 167:e84263d55307 | 6036 | #define DCMI_ESUR_FEU_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 6037 | #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 6038 | #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk |
| <> | 144:ef7eb2e8f9f7 | 6039 | |
| <> | 144:ef7eb2e8f9f7 | 6040 | /******************** Bits definition for DCMI_CWSTRT register ******************/ |
| AnnaBridge | 167:e84263d55307 | 6041 | #define DCMI_CWSTRT_HOFFCNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6042 | #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 167:e84263d55307 | 6043 | #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk |
| AnnaBridge | 167:e84263d55307 | 6044 | #define DCMI_CWSTRT_VST_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6045 | #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 6046 | #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk |
| <> | 144:ef7eb2e8f9f7 | 6047 | |
| <> | 144:ef7eb2e8f9f7 | 6048 | /******************** Bits definition for DCMI_CWSIZE register ******************/ |
| AnnaBridge | 167:e84263d55307 | 6049 | #define DCMI_CWSIZE_CAPCNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6050 | #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 167:e84263d55307 | 6051 | #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk |
| AnnaBridge | 167:e84263d55307 | 6052 | #define DCMI_CWSIZE_VLINE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6053 | #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 6054 | #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk |
| AnnaBridge | 167:e84263d55307 | 6055 | |
| AnnaBridge | 167:e84263d55307 | 6056 | /******************** Bits definition for DCMI_DR register *********************/ |
| AnnaBridge | 167:e84263d55307 | 6057 | #define DCMI_DR_BYTE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6058 | #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 6059 | #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk |
| AnnaBridge | 167:e84263d55307 | 6060 | #define DCMI_DR_BYTE1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6061 | #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 6062 | #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk |
| AnnaBridge | 167:e84263d55307 | 6063 | #define DCMI_DR_BYTE2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6064 | #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 6065 | #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk |
| AnnaBridge | 167:e84263d55307 | 6066 | #define DCMI_DR_BYTE3_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 6067 | #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 6068 | #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk |
| mbed_official | 19:112740acecfa | 6069 | |
| mbed_official | 19:112740acecfa | 6070 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 6071 | /* */ |
| mbed_official | 19:112740acecfa | 6072 | /* DMA Controller */ |
| mbed_official | 19:112740acecfa | 6073 | /* */ |
| mbed_official | 19:112740acecfa | 6074 | /******************************************************************************/ |
| <> | 144:ef7eb2e8f9f7 | 6075 | /******************** Bits definition for DMA_SxCR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 6076 | #define DMA_SxCR_CHSEL_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 6077 | #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */ |
| AnnaBridge | 167:e84263d55307 | 6078 | #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 6079 | #define DMA_SxCR_CHSEL_0 0x02000000U |
| AnnaBridge | 167:e84263d55307 | 6080 | #define DMA_SxCR_CHSEL_1 0x04000000U |
| AnnaBridge | 167:e84263d55307 | 6081 | #define DMA_SxCR_CHSEL_2 0x08000000U |
| AnnaBridge | 167:e84263d55307 | 6082 | #define DMA_SxCR_MBURST_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 6083 | #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */ |
| AnnaBridge | 167:e84263d55307 | 6084 | #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk |
| AnnaBridge | 167:e84263d55307 | 6085 | #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 6086 | #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 6087 | #define DMA_SxCR_PBURST_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 6088 | #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 167:e84263d55307 | 6089 | #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk |
| AnnaBridge | 167:e84263d55307 | 6090 | #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 6091 | #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 6092 | #define DMA_SxCR_CT_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 6093 | #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 6094 | #define DMA_SxCR_CT DMA_SxCR_CT_Msk |
| AnnaBridge | 167:e84263d55307 | 6095 | #define DMA_SxCR_DBM_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 6096 | #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 6097 | #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk |
| AnnaBridge | 167:e84263d55307 | 6098 | #define DMA_SxCR_PL_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6099 | #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 6100 | #define DMA_SxCR_PL DMA_SxCR_PL_Msk |
| AnnaBridge | 167:e84263d55307 | 6101 | #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 6102 | #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 6103 | #define DMA_SxCR_PINCOS_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 6104 | #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 6105 | #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk |
| AnnaBridge | 167:e84263d55307 | 6106 | #define DMA_SxCR_MSIZE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 6107 | #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */ |
| AnnaBridge | 167:e84263d55307 | 6108 | #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk |
| AnnaBridge | 167:e84263d55307 | 6109 | #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 6110 | #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 6111 | #define DMA_SxCR_PSIZE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 6112 | #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */ |
| AnnaBridge | 167:e84263d55307 | 6113 | #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk |
| AnnaBridge | 167:e84263d55307 | 6114 | #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 6115 | #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 6116 | #define DMA_SxCR_MINC_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 6117 | #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 6118 | #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk |
| AnnaBridge | 167:e84263d55307 | 6119 | #define DMA_SxCR_PINC_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 6120 | #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 6121 | #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk |
| AnnaBridge | 167:e84263d55307 | 6122 | #define DMA_SxCR_CIRC_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6123 | #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 6124 | #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk |
| AnnaBridge | 167:e84263d55307 | 6125 | #define DMA_SxCR_DIR_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 6126 | #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 6127 | #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk |
| AnnaBridge | 167:e84263d55307 | 6128 | #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 6129 | #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 6130 | #define DMA_SxCR_PFCTRL_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6131 | #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6132 | #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk |
| AnnaBridge | 167:e84263d55307 | 6133 | #define DMA_SxCR_TCIE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6134 | #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6135 | #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk |
| AnnaBridge | 167:e84263d55307 | 6136 | #define DMA_SxCR_HTIE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6137 | #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6138 | #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk |
| AnnaBridge | 167:e84263d55307 | 6139 | #define DMA_SxCR_TEIE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6140 | #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6141 | #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk |
| AnnaBridge | 167:e84263d55307 | 6142 | #define DMA_SxCR_DMEIE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6143 | #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6144 | #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk |
| AnnaBridge | 167:e84263d55307 | 6145 | #define DMA_SxCR_EN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6146 | #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6147 | #define DMA_SxCR_EN DMA_SxCR_EN_Msk |
| <> | 144:ef7eb2e8f9f7 | 6148 | |
| <> | 144:ef7eb2e8f9f7 | 6149 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 6150 | #define DMA_SxCR_ACK_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 6151 | #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 6152 | #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk |
| mbed_official | 19:112740acecfa | 6153 | |
| mbed_official | 19:112740acecfa | 6154 | /******************** Bits definition for DMA_SxCNDTR register **************/ |
| AnnaBridge | 167:e84263d55307 | 6155 | #define DMA_SxNDT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6156 | #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 6157 | #define DMA_SxNDT DMA_SxNDT_Msk |
| AnnaBridge | 167:e84263d55307 | 6158 | #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6159 | #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6160 | #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6161 | #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6162 | #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6163 | #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6164 | #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 6165 | #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 6166 | #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 6167 | #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 6168 | #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 6169 | #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 6170 | #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 6171 | #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 6172 | #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 6173 | #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */ |
| mbed_official | 19:112740acecfa | 6174 | |
| mbed_official | 19:112740acecfa | 6175 | /******************** Bits definition for DMA_SxFCR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 6176 | #define DMA_SxFCR_FEIE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 6177 | #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 6178 | #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk |
| AnnaBridge | 167:e84263d55307 | 6179 | #define DMA_SxFCR_FS_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6180 | #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 167:e84263d55307 | 6181 | #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk |
| AnnaBridge | 167:e84263d55307 | 6182 | #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6183 | #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6184 | #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6185 | #define DMA_SxFCR_DMDIS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6186 | #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6187 | #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk |
| AnnaBridge | 167:e84263d55307 | 6188 | #define DMA_SxFCR_FTH_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6189 | #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 6190 | #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk |
| AnnaBridge | 167:e84263d55307 | 6191 | #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6192 | #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */ |
| mbed_official | 19:112740acecfa | 6193 | |
| mbed_official | 19:112740acecfa | 6194 | /******************** Bits definition for DMA_LISR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 6195 | #define DMA_LISR_TCIF3_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 6196 | #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 6197 | #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk |
| AnnaBridge | 167:e84263d55307 | 6198 | #define DMA_LISR_HTIF3_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 6199 | #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 6200 | #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk |
| AnnaBridge | 167:e84263d55307 | 6201 | #define DMA_LISR_TEIF3_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 6202 | #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 6203 | #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk |
| AnnaBridge | 167:e84263d55307 | 6204 | #define DMA_LISR_DMEIF3_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 6205 | #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 6206 | #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk |
| AnnaBridge | 167:e84263d55307 | 6207 | #define DMA_LISR_FEIF3_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 6208 | #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 6209 | #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk |
| AnnaBridge | 167:e84263d55307 | 6210 | #define DMA_LISR_TCIF2_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 6211 | #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 6212 | #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk |
| AnnaBridge | 167:e84263d55307 | 6213 | #define DMA_LISR_HTIF2_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 6214 | #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 6215 | #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk |
| AnnaBridge | 167:e84263d55307 | 6216 | #define DMA_LISR_TEIF2_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 6217 | #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 6218 | #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk |
| AnnaBridge | 167:e84263d55307 | 6219 | #define DMA_LISR_DMEIF2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 6220 | #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 6221 | #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk |
| AnnaBridge | 167:e84263d55307 | 6222 | #define DMA_LISR_FEIF2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6223 | #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 6224 | #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk |
| AnnaBridge | 167:e84263d55307 | 6225 | #define DMA_LISR_TCIF1_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 6226 | #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 6227 | #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk |
| AnnaBridge | 167:e84263d55307 | 6228 | #define DMA_LISR_HTIF1_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 6229 | #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 6230 | #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk |
| AnnaBridge | 167:e84263d55307 | 6231 | #define DMA_LISR_TEIF1_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 6232 | #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 6233 | #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk |
| AnnaBridge | 167:e84263d55307 | 6234 | #define DMA_LISR_DMEIF1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6235 | #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 6236 | #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk |
| AnnaBridge | 167:e84263d55307 | 6237 | #define DMA_LISR_FEIF1_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 6238 | #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 6239 | #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk |
| AnnaBridge | 167:e84263d55307 | 6240 | #define DMA_LISR_TCIF0_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6241 | #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6242 | #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk |
| AnnaBridge | 167:e84263d55307 | 6243 | #define DMA_LISR_HTIF0_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6244 | #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6245 | #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk |
| AnnaBridge | 167:e84263d55307 | 6246 | #define DMA_LISR_TEIF0_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6247 | #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6248 | #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk |
| AnnaBridge | 167:e84263d55307 | 6249 | #define DMA_LISR_DMEIF0_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6250 | #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6251 | #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk |
| AnnaBridge | 167:e84263d55307 | 6252 | #define DMA_LISR_FEIF0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6253 | #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6254 | #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk |
| mbed_official | 19:112740acecfa | 6255 | |
| mbed_official | 19:112740acecfa | 6256 | /******************** Bits definition for DMA_HISR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 6257 | #define DMA_HISR_TCIF7_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 6258 | #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 6259 | #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk |
| AnnaBridge | 167:e84263d55307 | 6260 | #define DMA_HISR_HTIF7_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 6261 | #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 6262 | #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk |
| AnnaBridge | 167:e84263d55307 | 6263 | #define DMA_HISR_TEIF7_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 6264 | #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 6265 | #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk |
| AnnaBridge | 167:e84263d55307 | 6266 | #define DMA_HISR_DMEIF7_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 6267 | #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 6268 | #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk |
| AnnaBridge | 167:e84263d55307 | 6269 | #define DMA_HISR_FEIF7_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 6270 | #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 6271 | #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk |
| AnnaBridge | 167:e84263d55307 | 6272 | #define DMA_HISR_TCIF6_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 6273 | #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 6274 | #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk |
| AnnaBridge | 167:e84263d55307 | 6275 | #define DMA_HISR_HTIF6_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 6276 | #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 6277 | #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk |
| AnnaBridge | 167:e84263d55307 | 6278 | #define DMA_HISR_TEIF6_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 6279 | #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 6280 | #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk |
| AnnaBridge | 167:e84263d55307 | 6281 | #define DMA_HISR_DMEIF6_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 6282 | #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 6283 | #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk |
| AnnaBridge | 167:e84263d55307 | 6284 | #define DMA_HISR_FEIF6_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6285 | #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 6286 | #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk |
| AnnaBridge | 167:e84263d55307 | 6287 | #define DMA_HISR_TCIF5_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 6288 | #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 6289 | #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk |
| AnnaBridge | 167:e84263d55307 | 6290 | #define DMA_HISR_HTIF5_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 6291 | #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 6292 | #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk |
| AnnaBridge | 167:e84263d55307 | 6293 | #define DMA_HISR_TEIF5_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 6294 | #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 6295 | #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk |
| AnnaBridge | 167:e84263d55307 | 6296 | #define DMA_HISR_DMEIF5_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6297 | #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 6298 | #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk |
| AnnaBridge | 167:e84263d55307 | 6299 | #define DMA_HISR_FEIF5_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 6300 | #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 6301 | #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk |
| AnnaBridge | 167:e84263d55307 | 6302 | #define DMA_HISR_TCIF4_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6303 | #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6304 | #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk |
| AnnaBridge | 167:e84263d55307 | 6305 | #define DMA_HISR_HTIF4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6306 | #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6307 | #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk |
| AnnaBridge | 167:e84263d55307 | 6308 | #define DMA_HISR_TEIF4_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6309 | #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6310 | #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk |
| AnnaBridge | 167:e84263d55307 | 6311 | #define DMA_HISR_DMEIF4_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6312 | #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6313 | #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk |
| AnnaBridge | 167:e84263d55307 | 6314 | #define DMA_HISR_FEIF4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6315 | #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6316 | #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk |
| mbed_official | 19:112740acecfa | 6317 | |
| mbed_official | 19:112740acecfa | 6318 | /******************** Bits definition for DMA_LIFCR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 6319 | #define DMA_LIFCR_CTCIF3_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 6320 | #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 6321 | #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk |
| AnnaBridge | 167:e84263d55307 | 6322 | #define DMA_LIFCR_CHTIF3_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 6323 | #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 6324 | #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk |
| AnnaBridge | 167:e84263d55307 | 6325 | #define DMA_LIFCR_CTEIF3_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 6326 | #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 6327 | #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk |
| AnnaBridge | 167:e84263d55307 | 6328 | #define DMA_LIFCR_CDMEIF3_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 6329 | #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 6330 | #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk |
| AnnaBridge | 167:e84263d55307 | 6331 | #define DMA_LIFCR_CFEIF3_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 6332 | #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 6333 | #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk |
| AnnaBridge | 167:e84263d55307 | 6334 | #define DMA_LIFCR_CTCIF2_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 6335 | #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 6336 | #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk |
| AnnaBridge | 167:e84263d55307 | 6337 | #define DMA_LIFCR_CHTIF2_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 6338 | #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 6339 | #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk |
| AnnaBridge | 167:e84263d55307 | 6340 | #define DMA_LIFCR_CTEIF2_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 6341 | #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 6342 | #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk |
| AnnaBridge | 167:e84263d55307 | 6343 | #define DMA_LIFCR_CDMEIF2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 6344 | #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 6345 | #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk |
| AnnaBridge | 167:e84263d55307 | 6346 | #define DMA_LIFCR_CFEIF2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6347 | #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 6348 | #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk |
| AnnaBridge | 167:e84263d55307 | 6349 | #define DMA_LIFCR_CTCIF1_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 6350 | #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 6351 | #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk |
| AnnaBridge | 167:e84263d55307 | 6352 | #define DMA_LIFCR_CHTIF1_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 6353 | #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 6354 | #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk |
| AnnaBridge | 167:e84263d55307 | 6355 | #define DMA_LIFCR_CTEIF1_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 6356 | #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 6357 | #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk |
| AnnaBridge | 167:e84263d55307 | 6358 | #define DMA_LIFCR_CDMEIF1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6359 | #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 6360 | #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk |
| AnnaBridge | 167:e84263d55307 | 6361 | #define DMA_LIFCR_CFEIF1_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 6362 | #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 6363 | #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk |
| AnnaBridge | 167:e84263d55307 | 6364 | #define DMA_LIFCR_CTCIF0_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6365 | #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6366 | #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk |
| AnnaBridge | 167:e84263d55307 | 6367 | #define DMA_LIFCR_CHTIF0_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6368 | #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6369 | #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk |
| AnnaBridge | 167:e84263d55307 | 6370 | #define DMA_LIFCR_CTEIF0_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6371 | #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6372 | #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk |
| AnnaBridge | 167:e84263d55307 | 6373 | #define DMA_LIFCR_CDMEIF0_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6374 | #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6375 | #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk |
| AnnaBridge | 167:e84263d55307 | 6376 | #define DMA_LIFCR_CFEIF0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6377 | #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6378 | #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk |
| mbed_official | 19:112740acecfa | 6379 | |
| mbed_official | 19:112740acecfa | 6380 | /******************** Bits definition for DMA_HIFCR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 6381 | #define DMA_HIFCR_CTCIF7_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 6382 | #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 6383 | #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk |
| AnnaBridge | 167:e84263d55307 | 6384 | #define DMA_HIFCR_CHTIF7_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 6385 | #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 6386 | #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk |
| AnnaBridge | 167:e84263d55307 | 6387 | #define DMA_HIFCR_CTEIF7_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 6388 | #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 6389 | #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk |
| AnnaBridge | 167:e84263d55307 | 6390 | #define DMA_HIFCR_CDMEIF7_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 6391 | #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 6392 | #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk |
| AnnaBridge | 167:e84263d55307 | 6393 | #define DMA_HIFCR_CFEIF7_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 6394 | #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 6395 | #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk |
| AnnaBridge | 167:e84263d55307 | 6396 | #define DMA_HIFCR_CTCIF6_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 6397 | #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 6398 | #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk |
| AnnaBridge | 167:e84263d55307 | 6399 | #define DMA_HIFCR_CHTIF6_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 6400 | #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 6401 | #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk |
| AnnaBridge | 167:e84263d55307 | 6402 | #define DMA_HIFCR_CTEIF6_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 6403 | #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 6404 | #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk |
| AnnaBridge | 167:e84263d55307 | 6405 | #define DMA_HIFCR_CDMEIF6_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 6406 | #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 6407 | #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk |
| AnnaBridge | 167:e84263d55307 | 6408 | #define DMA_HIFCR_CFEIF6_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6409 | #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 6410 | #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk |
| AnnaBridge | 167:e84263d55307 | 6411 | #define DMA_HIFCR_CTCIF5_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 6412 | #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 6413 | #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk |
| AnnaBridge | 167:e84263d55307 | 6414 | #define DMA_HIFCR_CHTIF5_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 6415 | #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 6416 | #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk |
| AnnaBridge | 167:e84263d55307 | 6417 | #define DMA_HIFCR_CTEIF5_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 6418 | #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 6419 | #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk |
| AnnaBridge | 167:e84263d55307 | 6420 | #define DMA_HIFCR_CDMEIF5_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6421 | #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 6422 | #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk |
| AnnaBridge | 167:e84263d55307 | 6423 | #define DMA_HIFCR_CFEIF5_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 6424 | #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 6425 | #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk |
| AnnaBridge | 167:e84263d55307 | 6426 | #define DMA_HIFCR_CTCIF4_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6427 | #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6428 | #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk |
| AnnaBridge | 167:e84263d55307 | 6429 | #define DMA_HIFCR_CHTIF4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6430 | #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6431 | #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk |
| AnnaBridge | 167:e84263d55307 | 6432 | #define DMA_HIFCR_CTEIF4_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6433 | #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6434 | #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk |
| AnnaBridge | 167:e84263d55307 | 6435 | #define DMA_HIFCR_CDMEIF4_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6436 | #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6437 | #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk |
| AnnaBridge | 167:e84263d55307 | 6438 | #define DMA_HIFCR_CFEIF4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6439 | #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6440 | #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk |
| AnnaBridge | 167:e84263d55307 | 6441 | |
| AnnaBridge | 167:e84263d55307 | 6442 | /****************** Bit definition for DMA_SxPAR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 6443 | #define DMA_SxPAR_PA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6444 | #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 6445 | #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */ |
| AnnaBridge | 167:e84263d55307 | 6446 | |
| AnnaBridge | 167:e84263d55307 | 6447 | /****************** Bit definition for DMA_SxM0AR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 6448 | #define DMA_SxM0AR_M0A_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6449 | #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 6450 | #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */ |
| AnnaBridge | 167:e84263d55307 | 6451 | |
| AnnaBridge | 167:e84263d55307 | 6452 | /****************** Bit definition for DMA_SxM1AR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 6453 | #define DMA_SxM1AR_M1A_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6454 | #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 6455 | #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */ |
| mbed_official | 19:112740acecfa | 6456 | |
| mbed_official | 19:112740acecfa | 6457 | |
| mbed_official | 19:112740acecfa | 6458 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 6459 | /* */ |
| mbed_official | 19:112740acecfa | 6460 | /* AHB Master DMA2D Controller (DMA2D) */ |
| mbed_official | 19:112740acecfa | 6461 | /* */ |
| mbed_official | 19:112740acecfa | 6462 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 6463 | |
| mbed_official | 19:112740acecfa | 6464 | /******************** Bit definition for DMA2D_CR register ******************/ |
| mbed_official | 19:112740acecfa | 6465 | |
| AnnaBridge | 167:e84263d55307 | 6466 | #define DMA2D_CR_START_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6467 | #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6468 | #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */ |
| AnnaBridge | 167:e84263d55307 | 6469 | #define DMA2D_CR_SUSP_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6470 | #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6471 | #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */ |
| AnnaBridge | 167:e84263d55307 | 6472 | #define DMA2D_CR_ABORT_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6473 | #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6474 | #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */ |
| AnnaBridge | 167:e84263d55307 | 6475 | #define DMA2D_CR_TEIE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6476 | #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 6477 | #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 6478 | #define DMA2D_CR_TCIE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 6479 | #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 6480 | #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 6481 | #define DMA2D_CR_TWIE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 6482 | #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 6483 | #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 6484 | #define DMA2D_CR_CAEIE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 6485 | #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 6486 | #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 6487 | #define DMA2D_CR_CTCIE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 6488 | #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 6489 | #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 6490 | #define DMA2D_CR_CEIE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 6491 | #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 6492 | #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 6493 | #define DMA2D_CR_MODE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6494 | #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 6495 | #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */ |
| AnnaBridge | 167:e84263d55307 | 6496 | #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 6497 | #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */ |
| mbed_official | 19:112740acecfa | 6498 | |
| mbed_official | 19:112740acecfa | 6499 | /******************** Bit definition for DMA2D_ISR register *****************/ |
| mbed_official | 19:112740acecfa | 6500 | |
| AnnaBridge | 167:e84263d55307 | 6501 | #define DMA2D_ISR_TEIF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6502 | #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6503 | #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 6504 | #define DMA2D_ISR_TCIF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6505 | #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6506 | #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 6507 | #define DMA2D_ISR_TWIF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6508 | #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6509 | #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 6510 | #define DMA2D_ISR_CAEIF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6511 | #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6512 | #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 6513 | #define DMA2D_ISR_CTCIF_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6514 | #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6515 | #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 6516 | #define DMA2D_ISR_CEIF_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6517 | #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6518 | #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */ |
| <> | 144:ef7eb2e8f9f7 | 6519 | |
| <> | 144:ef7eb2e8f9f7 | 6520 | /******************** Bit definition for DMA2D_IFCR register ****************/ |
| <> | 144:ef7eb2e8f9f7 | 6521 | |
| AnnaBridge | 167:e84263d55307 | 6522 | #define DMA2D_IFCR_CTEIF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6523 | #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6524 | #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 6525 | #define DMA2D_IFCR_CTCIF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6526 | #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6527 | #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 6528 | #define DMA2D_IFCR_CTWIF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6529 | #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6530 | #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 6531 | #define DMA2D_IFCR_CAECIF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6532 | #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6533 | #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 6534 | #define DMA2D_IFCR_CCTCIF_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6535 | #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6536 | #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 6537 | #define DMA2D_IFCR_CCEIF_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6538 | #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6539 | #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */ |
| <> | 144:ef7eb2e8f9f7 | 6540 | |
| <> | 144:ef7eb2e8f9f7 | 6541 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 6542 | #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */ |
| <> | 144:ef7eb2e8f9f7 | 6543 | #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */ |
| <> | 144:ef7eb2e8f9f7 | 6544 | #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */ |
| <> | 144:ef7eb2e8f9f7 | 6545 | #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */ |
| <> | 144:ef7eb2e8f9f7 | 6546 | #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */ |
| <> | 144:ef7eb2e8f9f7 | 6547 | #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */ |
| mbed_official | 19:112740acecfa | 6548 | |
| mbed_official | 19:112740acecfa | 6549 | /******************** Bit definition for DMA2D_FGMAR register ***************/ |
| mbed_official | 19:112740acecfa | 6550 | |
| AnnaBridge | 167:e84263d55307 | 6551 | #define DMA2D_FGMAR_MA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6552 | #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 6553 | #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */ |
| mbed_official | 19:112740acecfa | 6554 | |
| mbed_official | 19:112740acecfa | 6555 | /******************** Bit definition for DMA2D_FGOR register ****************/ |
| mbed_official | 19:112740acecfa | 6556 | |
| AnnaBridge | 167:e84263d55307 | 6557 | #define DMA2D_FGOR_LO_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6558 | #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 167:e84263d55307 | 6559 | #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */ |
| mbed_official | 19:112740acecfa | 6560 | |
| mbed_official | 19:112740acecfa | 6561 | /******************** Bit definition for DMA2D_BGMAR register ***************/ |
| mbed_official | 19:112740acecfa | 6562 | |
| AnnaBridge | 167:e84263d55307 | 6563 | #define DMA2D_BGMAR_MA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6564 | #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 6565 | #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */ |
| mbed_official | 19:112740acecfa | 6566 | |
| mbed_official | 19:112740acecfa | 6567 | /******************** Bit definition for DMA2D_BGOR register ****************/ |
| mbed_official | 19:112740acecfa | 6568 | |
| AnnaBridge | 167:e84263d55307 | 6569 | #define DMA2D_BGOR_LO_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6570 | #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 167:e84263d55307 | 6571 | #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */ |
| mbed_official | 19:112740acecfa | 6572 | |
| mbed_official | 19:112740acecfa | 6573 | /******************** Bit definition for DMA2D_FGPFCCR register *************/ |
| mbed_official | 19:112740acecfa | 6574 | |
| AnnaBridge | 167:e84263d55307 | 6575 | #define DMA2D_FGPFCCR_CM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6576 | #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 6577 | #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */ |
| AnnaBridge | 167:e84263d55307 | 6578 | #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6579 | #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6580 | #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6581 | #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6582 | #define DMA2D_FGPFCCR_CCM_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6583 | #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6584 | #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */ |
| AnnaBridge | 167:e84263d55307 | 6585 | #define DMA2D_FGPFCCR_START_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6586 | #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6587 | #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */ |
| AnnaBridge | 167:e84263d55307 | 6588 | #define DMA2D_FGPFCCR_CS_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6589 | #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 6590 | #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */ |
| AnnaBridge | 167:e84263d55307 | 6591 | #define DMA2D_FGPFCCR_AM_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6592 | #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 6593 | #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */ |
| AnnaBridge | 167:e84263d55307 | 6594 | #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 6595 | #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 6596 | #define DMA2D_FGPFCCR_ALPHA_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 6597 | #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 6598 | #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */ |
| mbed_official | 19:112740acecfa | 6599 | |
| mbed_official | 19:112740acecfa | 6600 | /******************** Bit definition for DMA2D_FGCOLR register **************/ |
| mbed_official | 19:112740acecfa | 6601 | |
| AnnaBridge | 167:e84263d55307 | 6602 | #define DMA2D_FGCOLR_BLUE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6603 | #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 6604 | #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */ |
| AnnaBridge | 167:e84263d55307 | 6605 | #define DMA2D_FGCOLR_GREEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6606 | #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 6607 | #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */ |
| AnnaBridge | 167:e84263d55307 | 6608 | #define DMA2D_FGCOLR_RED_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6609 | #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 6610 | #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */ |
| mbed_official | 19:112740acecfa | 6611 | |
| mbed_official | 19:112740acecfa | 6612 | /******************** Bit definition for DMA2D_BGPFCCR register *************/ |
| mbed_official | 19:112740acecfa | 6613 | |
| AnnaBridge | 167:e84263d55307 | 6614 | #define DMA2D_BGPFCCR_CM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6615 | #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 6616 | #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */ |
| AnnaBridge | 167:e84263d55307 | 6617 | #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6618 | #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6619 | #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6620 | #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 6621 | #define DMA2D_BGPFCCR_CCM_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6622 | #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6623 | #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */ |
| AnnaBridge | 167:e84263d55307 | 6624 | #define DMA2D_BGPFCCR_START_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6625 | #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6626 | #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */ |
| AnnaBridge | 167:e84263d55307 | 6627 | #define DMA2D_BGPFCCR_CS_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6628 | #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 6629 | #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */ |
| AnnaBridge | 167:e84263d55307 | 6630 | #define DMA2D_BGPFCCR_AM_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6631 | #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 6632 | #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */ |
| AnnaBridge | 167:e84263d55307 | 6633 | #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 6634 | #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 6635 | #define DMA2D_BGPFCCR_ALPHA_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 6636 | #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 6637 | #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */ |
| mbed_official | 19:112740acecfa | 6638 | |
| mbed_official | 19:112740acecfa | 6639 | /******************** Bit definition for DMA2D_BGCOLR register **************/ |
| mbed_official | 19:112740acecfa | 6640 | |
| AnnaBridge | 167:e84263d55307 | 6641 | #define DMA2D_BGCOLR_BLUE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6642 | #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 6643 | #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */ |
| AnnaBridge | 167:e84263d55307 | 6644 | #define DMA2D_BGCOLR_GREEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6645 | #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 6646 | #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */ |
| AnnaBridge | 167:e84263d55307 | 6647 | #define DMA2D_BGCOLR_RED_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6648 | #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 6649 | #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */ |
| mbed_official | 19:112740acecfa | 6650 | |
| mbed_official | 19:112740acecfa | 6651 | /******************** Bit definition for DMA2D_FGCMAR register **************/ |
| mbed_official | 19:112740acecfa | 6652 | |
| AnnaBridge | 167:e84263d55307 | 6653 | #define DMA2D_FGCMAR_MA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6654 | #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 6655 | #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */ |
| mbed_official | 19:112740acecfa | 6656 | |
| mbed_official | 19:112740acecfa | 6657 | /******************** Bit definition for DMA2D_BGCMAR register **************/ |
| mbed_official | 19:112740acecfa | 6658 | |
| AnnaBridge | 167:e84263d55307 | 6659 | #define DMA2D_BGCMAR_MA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6660 | #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 6661 | #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */ |
| mbed_official | 19:112740acecfa | 6662 | |
| mbed_official | 19:112740acecfa | 6663 | /******************** Bit definition for DMA2D_OPFCCR register **************/ |
| mbed_official | 19:112740acecfa | 6664 | |
| AnnaBridge | 167:e84263d55307 | 6665 | #define DMA2D_OPFCCR_CM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6666 | #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 6667 | #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */ |
| AnnaBridge | 167:e84263d55307 | 6668 | #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6669 | #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6670 | #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */ |
| mbed_official | 19:112740acecfa | 6671 | |
| mbed_official | 19:112740acecfa | 6672 | /******************** Bit definition for DMA2D_OCOLR register ***************/ |
| mbed_official | 19:112740acecfa | 6673 | |
| mbed_official | 19:112740acecfa | 6674 | /*!<Mode_ARGB8888/RGB888 */ |
| mbed_official | 19:112740acecfa | 6675 | |
| AnnaBridge | 167:e84263d55307 | 6676 | #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */ |
| AnnaBridge | 167:e84263d55307 | 6677 | #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */ |
| AnnaBridge | 167:e84263d55307 | 6678 | #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */ |
| AnnaBridge | 167:e84263d55307 | 6679 | #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */ |
| mbed_official | 19:112740acecfa | 6680 | |
| mbed_official | 19:112740acecfa | 6681 | /*!<Mode_RGB565 */ |
| AnnaBridge | 167:e84263d55307 | 6682 | #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */ |
| AnnaBridge | 167:e84263d55307 | 6683 | #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */ |
| AnnaBridge | 167:e84263d55307 | 6684 | #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */ |
| mbed_official | 19:112740acecfa | 6685 | |
| mbed_official | 19:112740acecfa | 6686 | /*!<Mode_ARGB1555 */ |
| AnnaBridge | 167:e84263d55307 | 6687 | #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */ |
| AnnaBridge | 167:e84263d55307 | 6688 | #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */ |
| AnnaBridge | 167:e84263d55307 | 6689 | #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */ |
| AnnaBridge | 167:e84263d55307 | 6690 | #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */ |
| mbed_official | 19:112740acecfa | 6691 | |
| mbed_official | 19:112740acecfa | 6692 | /*!<Mode_ARGB4444 */ |
| AnnaBridge | 167:e84263d55307 | 6693 | #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */ |
| AnnaBridge | 167:e84263d55307 | 6694 | #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */ |
| AnnaBridge | 167:e84263d55307 | 6695 | #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */ |
| AnnaBridge | 167:e84263d55307 | 6696 | #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */ |
| mbed_official | 19:112740acecfa | 6697 | |
| mbed_official | 19:112740acecfa | 6698 | /******************** Bit definition for DMA2D_OMAR register ****************/ |
| mbed_official | 19:112740acecfa | 6699 | |
| AnnaBridge | 167:e84263d55307 | 6700 | #define DMA2D_OMAR_MA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6701 | #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 6702 | #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */ |
| mbed_official | 19:112740acecfa | 6703 | |
| mbed_official | 19:112740acecfa | 6704 | /******************** Bit definition for DMA2D_OOR register *****************/ |
| mbed_official | 19:112740acecfa | 6705 | |
| AnnaBridge | 167:e84263d55307 | 6706 | #define DMA2D_OOR_LO_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6707 | #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 167:e84263d55307 | 6708 | #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */ |
| mbed_official | 19:112740acecfa | 6709 | |
| mbed_official | 19:112740acecfa | 6710 | /******************** Bit definition for DMA2D_NLR register *****************/ |
| mbed_official | 19:112740acecfa | 6711 | |
| AnnaBridge | 167:e84263d55307 | 6712 | #define DMA2D_NLR_NL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6713 | #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 6714 | #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */ |
| AnnaBridge | 167:e84263d55307 | 6715 | #define DMA2D_NLR_PL_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6716 | #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 6717 | #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */ |
| mbed_official | 19:112740acecfa | 6718 | |
| mbed_official | 19:112740acecfa | 6719 | /******************** Bit definition for DMA2D_LWR register *****************/ |
| mbed_official | 19:112740acecfa | 6720 | |
| AnnaBridge | 167:e84263d55307 | 6721 | #define DMA2D_LWR_LW_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6722 | #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 6723 | #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */ |
| mbed_official | 19:112740acecfa | 6724 | |
| mbed_official | 19:112740acecfa | 6725 | /******************** Bit definition for DMA2D_AMTCR register ***************/ |
| mbed_official | 19:112740acecfa | 6726 | |
| AnnaBridge | 167:e84263d55307 | 6727 | #define DMA2D_AMTCR_EN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6728 | #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6729 | #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ |
| AnnaBridge | 167:e84263d55307 | 6730 | #define DMA2D_AMTCR_DT_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6731 | #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 6732 | #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */ |
| mbed_official | 19:112740acecfa | 6733 | |
| mbed_official | 19:112740acecfa | 6734 | /******************** Bit definition for DMA2D_FGCLUT register **************/ |
| mbed_official | 19:112740acecfa | 6735 | |
| mbed_official | 19:112740acecfa | 6736 | /******************** Bit definition for DMA2D_BGCLUT register **************/ |
| mbed_official | 19:112740acecfa | 6737 | |
| mbed_official | 19:112740acecfa | 6738 | |
| mbed_official | 19:112740acecfa | 6739 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 6740 | /* */ |
| mbed_official | 19:112740acecfa | 6741 | /* Display Serial Interface (DSI) */ |
| mbed_official | 19:112740acecfa | 6742 | /* */ |
| mbed_official | 19:112740acecfa | 6743 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 6744 | /******************* Bit definition for DSI_VR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 6745 | #define DSI_VR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6746 | #define DSI_VR_Msk (0x18999815U << DSI_VR_Pos) /*!< 0x3133302A */ |
| AnnaBridge | 167:e84263d55307 | 6747 | #define DSI_VR DSI_VR_Msk /*!< DSI Host Version */ |
| mbed_official | 19:112740acecfa | 6748 | |
| mbed_official | 19:112740acecfa | 6749 | /******************* Bit definition for DSI_CR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 6750 | #define DSI_CR_EN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6751 | #define DSI_CR_EN_Msk (0x1U << DSI_CR_EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6752 | #define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */ |
| mbed_official | 19:112740acecfa | 6753 | |
| mbed_official | 19:112740acecfa | 6754 | /******************* Bit definition for DSI_CCR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 6755 | #define DSI_CCR_TXECKDIV_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6756 | #define DSI_CCR_TXECKDIV_Msk (0xFFU << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 6757 | #define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */ |
| AnnaBridge | 167:e84263d55307 | 6758 | #define DSI_CCR_TXECKDIV0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6759 | #define DSI_CCR_TXECKDIV0_Msk (0x1U << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6760 | #define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk |
| AnnaBridge | 167:e84263d55307 | 6761 | #define DSI_CCR_TXECKDIV1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6762 | #define DSI_CCR_TXECKDIV1_Msk (0x1U << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6763 | #define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk |
| AnnaBridge | 167:e84263d55307 | 6764 | #define DSI_CCR_TXECKDIV2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6765 | #define DSI_CCR_TXECKDIV2_Msk (0x1U << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6766 | #define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk |
| AnnaBridge | 167:e84263d55307 | 6767 | #define DSI_CCR_TXECKDIV3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6768 | #define DSI_CCR_TXECKDIV3_Msk (0x1U << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6769 | #define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk |
| AnnaBridge | 167:e84263d55307 | 6770 | #define DSI_CCR_TXECKDIV4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6771 | #define DSI_CCR_TXECKDIV4_Msk (0x1U << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6772 | #define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk |
| AnnaBridge | 167:e84263d55307 | 6773 | #define DSI_CCR_TXECKDIV5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6774 | #define DSI_CCR_TXECKDIV5_Msk (0x1U << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6775 | #define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk |
| AnnaBridge | 167:e84263d55307 | 6776 | #define DSI_CCR_TXECKDIV6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 6777 | #define DSI_CCR_TXECKDIV6_Msk (0x1U << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 6778 | #define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk |
| AnnaBridge | 167:e84263d55307 | 6779 | #define DSI_CCR_TXECKDIV7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 6780 | #define DSI_CCR_TXECKDIV7_Msk (0x1U << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 6781 | #define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk |
| AnnaBridge | 167:e84263d55307 | 6782 | |
| AnnaBridge | 167:e84263d55307 | 6783 | #define DSI_CCR_TOCKDIV_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6784 | #define DSI_CCR_TOCKDIV_Msk (0xFFU << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 6785 | #define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */ |
| AnnaBridge | 167:e84263d55307 | 6786 | #define DSI_CCR_TOCKDIV0_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6787 | #define DSI_CCR_TOCKDIV0_Msk (0x1U << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 6788 | #define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk |
| AnnaBridge | 167:e84263d55307 | 6789 | #define DSI_CCR_TOCKDIV1_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 6790 | #define DSI_CCR_TOCKDIV1_Msk (0x1U << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 6791 | #define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk |
| AnnaBridge | 167:e84263d55307 | 6792 | #define DSI_CCR_TOCKDIV2_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 6793 | #define DSI_CCR_TOCKDIV2_Msk (0x1U << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 6794 | #define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk |
| AnnaBridge | 167:e84263d55307 | 6795 | #define DSI_CCR_TOCKDIV3_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 6796 | #define DSI_CCR_TOCKDIV3_Msk (0x1U << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 6797 | #define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk |
| AnnaBridge | 167:e84263d55307 | 6798 | #define DSI_CCR_TOCKDIV4_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 6799 | #define DSI_CCR_TOCKDIV4_Msk (0x1U << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 6800 | #define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk |
| AnnaBridge | 167:e84263d55307 | 6801 | #define DSI_CCR_TOCKDIV5_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 6802 | #define DSI_CCR_TOCKDIV5_Msk (0x1U << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 6803 | #define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk |
| AnnaBridge | 167:e84263d55307 | 6804 | #define DSI_CCR_TOCKDIV6_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 6805 | #define DSI_CCR_TOCKDIV6_Msk (0x1U << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 6806 | #define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk |
| AnnaBridge | 167:e84263d55307 | 6807 | #define DSI_CCR_TOCKDIV7_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 6808 | #define DSI_CCR_TOCKDIV7_Msk (0x1U << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 6809 | #define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk |
| mbed_official | 19:112740acecfa | 6810 | |
| mbed_official | 19:112740acecfa | 6811 | /******************* Bit definition for DSI_LVCIDR register *************/ |
| AnnaBridge | 167:e84263d55307 | 6812 | #define DSI_LVCIDR_VCID_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6813 | #define DSI_LVCIDR_VCID_Msk (0x3U << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 6814 | #define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */ |
| AnnaBridge | 167:e84263d55307 | 6815 | #define DSI_LVCIDR_VCID0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6816 | #define DSI_LVCIDR_VCID0_Msk (0x1U << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6817 | #define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk |
| AnnaBridge | 167:e84263d55307 | 6818 | #define DSI_LVCIDR_VCID1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6819 | #define DSI_LVCIDR_VCID1_Msk (0x1U << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6820 | #define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk |
| mbed_official | 19:112740acecfa | 6821 | |
| mbed_official | 19:112740acecfa | 6822 | /******************* Bit definition for DSI_LCOLCR register *************/ |
| AnnaBridge | 167:e84263d55307 | 6823 | #define DSI_LCOLCR_COLC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6824 | #define DSI_LCOLCR_COLC_Msk (0xFU << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 6825 | #define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */ |
| AnnaBridge | 167:e84263d55307 | 6826 | #define DSI_LCOLCR_COLC0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6827 | #define DSI_LCOLCR_COLC0_Msk (0x1U << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6828 | #define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk |
| AnnaBridge | 167:e84263d55307 | 6829 | #define DSI_LCOLCR_COLC1_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6830 | #define DSI_LCOLCR_COLC1_Msk (0x1U << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6831 | #define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk |
| AnnaBridge | 167:e84263d55307 | 6832 | #define DSI_LCOLCR_COLC2_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 6833 | #define DSI_LCOLCR_COLC2_Msk (0x1U << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 6834 | #define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk |
| AnnaBridge | 167:e84263d55307 | 6835 | #define DSI_LCOLCR_COLC3_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 6836 | #define DSI_LCOLCR_COLC3_Msk (0x1U << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 6837 | #define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk |
| AnnaBridge | 167:e84263d55307 | 6838 | |
| AnnaBridge | 167:e84263d55307 | 6839 | #define DSI_LCOLCR_LPE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6840 | #define DSI_LCOLCR_LPE_Msk (0x1U << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 6841 | #define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */ |
| mbed_official | 19:112740acecfa | 6842 | |
| mbed_official | 19:112740acecfa | 6843 | /******************* Bit definition for DSI_LPCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 6844 | #define DSI_LPCR_DEP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6845 | #define DSI_LPCR_DEP_Msk (0x1U << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6846 | #define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */ |
| AnnaBridge | 167:e84263d55307 | 6847 | #define DSI_LPCR_VSP_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6848 | #define DSI_LPCR_VSP_Msk (0x1U << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6849 | #define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */ |
| AnnaBridge | 167:e84263d55307 | 6850 | #define DSI_LPCR_HSP_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6851 | #define DSI_LPCR_HSP_Msk (0x1U << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6852 | #define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */ |
| mbed_official | 19:112740acecfa | 6853 | |
| mbed_official | 19:112740acecfa | 6854 | /******************* Bit definition for DSI_LPMCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 6855 | #define DSI_LPMCR_VLPSIZE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6856 | #define DSI_LPMCR_VLPSIZE_Msk (0xFFU << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 6857 | #define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */ |
| AnnaBridge | 167:e84263d55307 | 6858 | #define DSI_LPMCR_VLPSIZE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6859 | #define DSI_LPMCR_VLPSIZE0_Msk (0x1U << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6860 | #define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk |
| AnnaBridge | 167:e84263d55307 | 6861 | #define DSI_LPMCR_VLPSIZE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6862 | #define DSI_LPMCR_VLPSIZE1_Msk (0x1U << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6863 | #define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk |
| AnnaBridge | 167:e84263d55307 | 6864 | #define DSI_LPMCR_VLPSIZE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6865 | #define DSI_LPMCR_VLPSIZE2_Msk (0x1U << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6866 | #define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk |
| AnnaBridge | 167:e84263d55307 | 6867 | #define DSI_LPMCR_VLPSIZE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6868 | #define DSI_LPMCR_VLPSIZE3_Msk (0x1U << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6869 | #define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk |
| AnnaBridge | 167:e84263d55307 | 6870 | #define DSI_LPMCR_VLPSIZE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6871 | #define DSI_LPMCR_VLPSIZE4_Msk (0x1U << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6872 | #define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk |
| AnnaBridge | 167:e84263d55307 | 6873 | #define DSI_LPMCR_VLPSIZE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 6874 | #define DSI_LPMCR_VLPSIZE5_Msk (0x1U << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 6875 | #define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk |
| AnnaBridge | 167:e84263d55307 | 6876 | #define DSI_LPMCR_VLPSIZE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 6877 | #define DSI_LPMCR_VLPSIZE6_Msk (0x1U << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 6878 | #define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk |
| AnnaBridge | 167:e84263d55307 | 6879 | #define DSI_LPMCR_VLPSIZE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 6880 | #define DSI_LPMCR_VLPSIZE7_Msk (0x1U << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 6881 | #define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk |
| AnnaBridge | 167:e84263d55307 | 6882 | |
| AnnaBridge | 167:e84263d55307 | 6883 | #define DSI_LPMCR_LPSIZE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6884 | #define DSI_LPMCR_LPSIZE_Msk (0xFFU << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 6885 | #define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */ |
| AnnaBridge | 167:e84263d55307 | 6886 | #define DSI_LPMCR_LPSIZE0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6887 | #define DSI_LPMCR_LPSIZE0_Msk (0x1U << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 6888 | #define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk |
| AnnaBridge | 167:e84263d55307 | 6889 | #define DSI_LPMCR_LPSIZE1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 6890 | #define DSI_LPMCR_LPSIZE1_Msk (0x1U << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 6891 | #define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk |
| AnnaBridge | 167:e84263d55307 | 6892 | #define DSI_LPMCR_LPSIZE2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 6893 | #define DSI_LPMCR_LPSIZE2_Msk (0x1U << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 6894 | #define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk |
| AnnaBridge | 167:e84263d55307 | 6895 | #define DSI_LPMCR_LPSIZE3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 6896 | #define DSI_LPMCR_LPSIZE3_Msk (0x1U << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 6897 | #define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk |
| AnnaBridge | 167:e84263d55307 | 6898 | #define DSI_LPMCR_LPSIZE4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 6899 | #define DSI_LPMCR_LPSIZE4_Msk (0x1U << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 6900 | #define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk |
| AnnaBridge | 167:e84263d55307 | 6901 | #define DSI_LPMCR_LPSIZE5_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 6902 | #define DSI_LPMCR_LPSIZE5_Msk (0x1U << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 6903 | #define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk |
| AnnaBridge | 167:e84263d55307 | 6904 | #define DSI_LPMCR_LPSIZE6_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 6905 | #define DSI_LPMCR_LPSIZE6_Msk (0x1U << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 6906 | #define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk |
| AnnaBridge | 167:e84263d55307 | 6907 | #define DSI_LPMCR_LPSIZE7_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 6908 | #define DSI_LPMCR_LPSIZE7_Msk (0x1U << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 6909 | #define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk |
| mbed_official | 19:112740acecfa | 6910 | |
| mbed_official | 19:112740acecfa | 6911 | /******************* Bit definition for DSI_PCR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 6912 | #define DSI_PCR_ETTXE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6913 | #define DSI_PCR_ETTXE_Msk (0x1U << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6914 | #define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */ |
| AnnaBridge | 167:e84263d55307 | 6915 | #define DSI_PCR_ETRXE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6916 | #define DSI_PCR_ETRXE_Msk (0x1U << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6917 | #define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */ |
| AnnaBridge | 167:e84263d55307 | 6918 | #define DSI_PCR_BTAE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 6919 | #define DSI_PCR_BTAE_Msk (0x1U << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 6920 | #define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */ |
| AnnaBridge | 167:e84263d55307 | 6921 | #define DSI_PCR_ECCRXE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 6922 | #define DSI_PCR_ECCRXE_Msk (0x1U << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 6923 | #define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */ |
| AnnaBridge | 167:e84263d55307 | 6924 | #define DSI_PCR_CRCRXE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 6925 | #define DSI_PCR_CRCRXE_Msk (0x1U << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 6926 | #define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */ |
| mbed_official | 19:112740acecfa | 6927 | |
| mbed_official | 19:112740acecfa | 6928 | /******************* Bit definition for DSI_GVCIDR register *************/ |
| AnnaBridge | 167:e84263d55307 | 6929 | #define DSI_GVCIDR_VCID_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6930 | #define DSI_GVCIDR_VCID_Msk (0x3U << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 6931 | #define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */ |
| AnnaBridge | 167:e84263d55307 | 6932 | #define DSI_GVCIDR_VCID0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6933 | #define DSI_GVCIDR_VCID0_Msk (0x1U << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6934 | #define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk |
| AnnaBridge | 167:e84263d55307 | 6935 | #define DSI_GVCIDR_VCID1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6936 | #define DSI_GVCIDR_VCID1_Msk (0x1U << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6937 | #define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk |
| mbed_official | 19:112740acecfa | 6938 | |
| mbed_official | 19:112740acecfa | 6939 | /******************* Bit definition for DSI_MCR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 6940 | #define DSI_MCR_CMDM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6941 | #define DSI_MCR_CMDM_Msk (0x1U << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6942 | #define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */ |
| mbed_official | 19:112740acecfa | 6943 | |
| mbed_official | 19:112740acecfa | 6944 | /******************* Bit definition for DSI_VMCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 6945 | #define DSI_VMCR_VMT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6946 | #define DSI_VMCR_VMT_Msk (0x3U << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 6947 | #define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */ |
| AnnaBridge | 167:e84263d55307 | 6948 | #define DSI_VMCR_VMT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6949 | #define DSI_VMCR_VMT0_Msk (0x1U << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6950 | #define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk |
| AnnaBridge | 167:e84263d55307 | 6951 | #define DSI_VMCR_VMT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6952 | #define DSI_VMCR_VMT1_Msk (0x1U << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6953 | #define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk |
| AnnaBridge | 167:e84263d55307 | 6954 | |
| AnnaBridge | 167:e84263d55307 | 6955 | #define DSI_VMCR_LPVSAE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 6956 | #define DSI_VMCR_LPVSAE_Msk (0x1U << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 6957 | #define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */ |
| AnnaBridge | 167:e84263d55307 | 6958 | #define DSI_VMCR_LPVBPE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 6959 | #define DSI_VMCR_LPVBPE_Msk (0x1U << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 6960 | #define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */ |
| AnnaBridge | 167:e84263d55307 | 6961 | #define DSI_VMCR_LPVFPE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 6962 | #define DSI_VMCR_LPVFPE_Msk (0x1U << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 6963 | #define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */ |
| AnnaBridge | 167:e84263d55307 | 6964 | #define DSI_VMCR_LPVAE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 6965 | #define DSI_VMCR_LPVAE_Msk (0x1U << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 6966 | #define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */ |
| AnnaBridge | 167:e84263d55307 | 6967 | #define DSI_VMCR_LPHBPE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 6968 | #define DSI_VMCR_LPHBPE_Msk (0x1U << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 6969 | #define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */ |
| AnnaBridge | 167:e84263d55307 | 6970 | #define DSI_VMCR_LPHFPE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 6971 | #define DSI_VMCR_LPHFPE_Msk (0x1U << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 6972 | #define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */ |
| AnnaBridge | 167:e84263d55307 | 6973 | #define DSI_VMCR_FBTAAE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 6974 | #define DSI_VMCR_FBTAAE_Msk (0x1U << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 6975 | #define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */ |
| AnnaBridge | 167:e84263d55307 | 6976 | #define DSI_VMCR_LPCE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 6977 | #define DSI_VMCR_LPCE_Msk (0x1U << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 6978 | #define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */ |
| AnnaBridge | 167:e84263d55307 | 6979 | #define DSI_VMCR_PGE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 6980 | #define DSI_VMCR_PGE_Msk (0x1U << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 6981 | #define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */ |
| AnnaBridge | 167:e84263d55307 | 6982 | #define DSI_VMCR_PGM_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 6983 | #define DSI_VMCR_PGM_Msk (0x1U << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 6984 | #define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */ |
| AnnaBridge | 167:e84263d55307 | 6985 | #define DSI_VMCR_PGO_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 6986 | #define DSI_VMCR_PGO_Msk (0x1U << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 6987 | #define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */ |
| mbed_official | 19:112740acecfa | 6988 | |
| mbed_official | 19:112740acecfa | 6989 | /******************* Bit definition for DSI_VPCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 6990 | #define DSI_VPCR_VPSIZE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6991 | #define DSI_VPCR_VPSIZE_Msk (0x3FFFU << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 167:e84263d55307 | 6992 | #define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */ |
| AnnaBridge | 167:e84263d55307 | 6993 | #define DSI_VPCR_VPSIZE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 6994 | #define DSI_VPCR_VPSIZE0_Msk (0x1U << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 6995 | #define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk |
| AnnaBridge | 167:e84263d55307 | 6996 | #define DSI_VPCR_VPSIZE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 6997 | #define DSI_VPCR_VPSIZE1_Msk (0x1U << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 6998 | #define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk |
| AnnaBridge | 167:e84263d55307 | 6999 | #define DSI_VPCR_VPSIZE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7000 | #define DSI_VPCR_VPSIZE2_Msk (0x1U << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7001 | #define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk |
| AnnaBridge | 167:e84263d55307 | 7002 | #define DSI_VPCR_VPSIZE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7003 | #define DSI_VPCR_VPSIZE3_Msk (0x1U << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7004 | #define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk |
| AnnaBridge | 167:e84263d55307 | 7005 | #define DSI_VPCR_VPSIZE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7006 | #define DSI_VPCR_VPSIZE4_Msk (0x1U << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7007 | #define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk |
| AnnaBridge | 167:e84263d55307 | 7008 | #define DSI_VPCR_VPSIZE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7009 | #define DSI_VPCR_VPSIZE5_Msk (0x1U << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7010 | #define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk |
| AnnaBridge | 167:e84263d55307 | 7011 | #define DSI_VPCR_VPSIZE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7012 | #define DSI_VPCR_VPSIZE6_Msk (0x1U << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7013 | #define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk |
| AnnaBridge | 167:e84263d55307 | 7014 | #define DSI_VPCR_VPSIZE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7015 | #define DSI_VPCR_VPSIZE7_Msk (0x1U << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7016 | #define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk |
| AnnaBridge | 167:e84263d55307 | 7017 | #define DSI_VPCR_VPSIZE8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7018 | #define DSI_VPCR_VPSIZE8_Msk (0x1U << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7019 | #define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk |
| AnnaBridge | 167:e84263d55307 | 7020 | #define DSI_VPCR_VPSIZE9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7021 | #define DSI_VPCR_VPSIZE9_Msk (0x1U << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7022 | #define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk |
| AnnaBridge | 167:e84263d55307 | 7023 | #define DSI_VPCR_VPSIZE10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7024 | #define DSI_VPCR_VPSIZE10_Msk (0x1U << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7025 | #define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk |
| AnnaBridge | 167:e84263d55307 | 7026 | #define DSI_VPCR_VPSIZE11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7027 | #define DSI_VPCR_VPSIZE11_Msk (0x1U << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7028 | #define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk |
| AnnaBridge | 167:e84263d55307 | 7029 | #define DSI_VPCR_VPSIZE12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7030 | #define DSI_VPCR_VPSIZE12_Msk (0x1U << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7031 | #define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk |
| AnnaBridge | 167:e84263d55307 | 7032 | #define DSI_VPCR_VPSIZE13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7033 | #define DSI_VPCR_VPSIZE13_Msk (0x1U << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7034 | #define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk |
| mbed_official | 19:112740acecfa | 7035 | |
| mbed_official | 19:112740acecfa | 7036 | /******************* Bit definition for DSI_VCCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 7037 | #define DSI_VCCR_NUMC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7038 | #define DSI_VCCR_NUMC_Msk (0x1FFFU << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */ |
| AnnaBridge | 167:e84263d55307 | 7039 | #define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */ |
| AnnaBridge | 167:e84263d55307 | 7040 | #define DSI_VCCR_NUMC0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7041 | #define DSI_VCCR_NUMC0_Msk (0x1U << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7042 | #define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk |
| AnnaBridge | 167:e84263d55307 | 7043 | #define DSI_VCCR_NUMC1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7044 | #define DSI_VCCR_NUMC1_Msk (0x1U << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7045 | #define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk |
| AnnaBridge | 167:e84263d55307 | 7046 | #define DSI_VCCR_NUMC2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7047 | #define DSI_VCCR_NUMC2_Msk (0x1U << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7048 | #define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk |
| AnnaBridge | 167:e84263d55307 | 7049 | #define DSI_VCCR_NUMC3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7050 | #define DSI_VCCR_NUMC3_Msk (0x1U << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7051 | #define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk |
| AnnaBridge | 167:e84263d55307 | 7052 | #define DSI_VCCR_NUMC4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7053 | #define DSI_VCCR_NUMC4_Msk (0x1U << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7054 | #define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk |
| AnnaBridge | 167:e84263d55307 | 7055 | #define DSI_VCCR_NUMC5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7056 | #define DSI_VCCR_NUMC5_Msk (0x1U << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7057 | #define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk |
| AnnaBridge | 167:e84263d55307 | 7058 | #define DSI_VCCR_NUMC6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7059 | #define DSI_VCCR_NUMC6_Msk (0x1U << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7060 | #define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk |
| AnnaBridge | 167:e84263d55307 | 7061 | #define DSI_VCCR_NUMC7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7062 | #define DSI_VCCR_NUMC7_Msk (0x1U << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7063 | #define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk |
| AnnaBridge | 167:e84263d55307 | 7064 | #define DSI_VCCR_NUMC8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7065 | #define DSI_VCCR_NUMC8_Msk (0x1U << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7066 | #define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk |
| AnnaBridge | 167:e84263d55307 | 7067 | #define DSI_VCCR_NUMC9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7068 | #define DSI_VCCR_NUMC9_Msk (0x1U << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7069 | #define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk |
| AnnaBridge | 167:e84263d55307 | 7070 | #define DSI_VCCR_NUMC10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7071 | #define DSI_VCCR_NUMC10_Msk (0x1U << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7072 | #define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk |
| AnnaBridge | 167:e84263d55307 | 7073 | #define DSI_VCCR_NUMC11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7074 | #define DSI_VCCR_NUMC11_Msk (0x1U << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7075 | #define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk |
| AnnaBridge | 167:e84263d55307 | 7076 | #define DSI_VCCR_NUMC12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7077 | #define DSI_VCCR_NUMC12_Msk (0x1U << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7078 | #define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk |
| mbed_official | 19:112740acecfa | 7079 | |
| mbed_official | 19:112740acecfa | 7080 | /******************* Bit definition for DSI_VNPCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 7081 | #define DSI_VNPCR_NPSIZE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7082 | #define DSI_VNPCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */ |
| AnnaBridge | 167:e84263d55307 | 7083 | #define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */ |
| AnnaBridge | 167:e84263d55307 | 7084 | #define DSI_VNPCR_NPSIZE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7085 | #define DSI_VNPCR_NPSIZE0_Msk (0x1U << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7086 | #define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk |
| AnnaBridge | 167:e84263d55307 | 7087 | #define DSI_VNPCR_NPSIZE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7088 | #define DSI_VNPCR_NPSIZE1_Msk (0x1U << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7089 | #define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk |
| AnnaBridge | 167:e84263d55307 | 7090 | #define DSI_VNPCR_NPSIZE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7091 | #define DSI_VNPCR_NPSIZE2_Msk (0x1U << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7092 | #define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk |
| AnnaBridge | 167:e84263d55307 | 7093 | #define DSI_VNPCR_NPSIZE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7094 | #define DSI_VNPCR_NPSIZE3_Msk (0x1U << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7095 | #define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk |
| AnnaBridge | 167:e84263d55307 | 7096 | #define DSI_VNPCR_NPSIZE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7097 | #define DSI_VNPCR_NPSIZE4_Msk (0x1U << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7098 | #define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk |
| AnnaBridge | 167:e84263d55307 | 7099 | #define DSI_VNPCR_NPSIZE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7100 | #define DSI_VNPCR_NPSIZE5_Msk (0x1U << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7101 | #define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk |
| AnnaBridge | 167:e84263d55307 | 7102 | #define DSI_VNPCR_NPSIZE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7103 | #define DSI_VNPCR_NPSIZE6_Msk (0x1U << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7104 | #define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk |
| AnnaBridge | 167:e84263d55307 | 7105 | #define DSI_VNPCR_NPSIZE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7106 | #define DSI_VNPCR_NPSIZE7_Msk (0x1U << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7107 | #define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk |
| AnnaBridge | 167:e84263d55307 | 7108 | #define DSI_VNPCR_NPSIZE8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7109 | #define DSI_VNPCR_NPSIZE8_Msk (0x1U << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7110 | #define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk |
| AnnaBridge | 167:e84263d55307 | 7111 | #define DSI_VNPCR_NPSIZE9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7112 | #define DSI_VNPCR_NPSIZE9_Msk (0x1U << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7113 | #define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk |
| AnnaBridge | 167:e84263d55307 | 7114 | #define DSI_VNPCR_NPSIZE10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7115 | #define DSI_VNPCR_NPSIZE10_Msk (0x1U << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7116 | #define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk |
| AnnaBridge | 167:e84263d55307 | 7117 | #define DSI_VNPCR_NPSIZE11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7118 | #define DSI_VNPCR_NPSIZE11_Msk (0x1U << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7119 | #define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk |
| AnnaBridge | 167:e84263d55307 | 7120 | #define DSI_VNPCR_NPSIZE12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7121 | #define DSI_VNPCR_NPSIZE12_Msk (0x1U << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7122 | #define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk |
| mbed_official | 19:112740acecfa | 7123 | |
| mbed_official | 19:112740acecfa | 7124 | /******************* Bit definition for DSI_VHSACR register *************/ |
| AnnaBridge | 167:e84263d55307 | 7125 | #define DSI_VHSACR_HSA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7126 | #define DSI_VHSACR_HSA_Msk (0xFFFU << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 7127 | #define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */ |
| AnnaBridge | 167:e84263d55307 | 7128 | #define DSI_VHSACR_HSA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7129 | #define DSI_VHSACR_HSA0_Msk (0x1U << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7130 | #define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk |
| AnnaBridge | 167:e84263d55307 | 7131 | #define DSI_VHSACR_HSA1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7132 | #define DSI_VHSACR_HSA1_Msk (0x1U << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7133 | #define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk |
| AnnaBridge | 167:e84263d55307 | 7134 | #define DSI_VHSACR_HSA2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7135 | #define DSI_VHSACR_HSA2_Msk (0x1U << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7136 | #define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk |
| AnnaBridge | 167:e84263d55307 | 7137 | #define DSI_VHSACR_HSA3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7138 | #define DSI_VHSACR_HSA3_Msk (0x1U << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7139 | #define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk |
| AnnaBridge | 167:e84263d55307 | 7140 | #define DSI_VHSACR_HSA4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7141 | #define DSI_VHSACR_HSA4_Msk (0x1U << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7142 | #define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk |
| AnnaBridge | 167:e84263d55307 | 7143 | #define DSI_VHSACR_HSA5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7144 | #define DSI_VHSACR_HSA5_Msk (0x1U << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7145 | #define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk |
| AnnaBridge | 167:e84263d55307 | 7146 | #define DSI_VHSACR_HSA6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7147 | #define DSI_VHSACR_HSA6_Msk (0x1U << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7148 | #define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk |
| AnnaBridge | 167:e84263d55307 | 7149 | #define DSI_VHSACR_HSA7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7150 | #define DSI_VHSACR_HSA7_Msk (0x1U << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7151 | #define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk |
| AnnaBridge | 167:e84263d55307 | 7152 | #define DSI_VHSACR_HSA8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7153 | #define DSI_VHSACR_HSA8_Msk (0x1U << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7154 | #define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk |
| AnnaBridge | 167:e84263d55307 | 7155 | #define DSI_VHSACR_HSA9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7156 | #define DSI_VHSACR_HSA9_Msk (0x1U << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7157 | #define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk |
| AnnaBridge | 167:e84263d55307 | 7158 | #define DSI_VHSACR_HSA10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7159 | #define DSI_VHSACR_HSA10_Msk (0x1U << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7160 | #define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk |
| AnnaBridge | 167:e84263d55307 | 7161 | #define DSI_VHSACR_HSA11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7162 | #define DSI_VHSACR_HSA11_Msk (0x1U << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7163 | #define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk |
| mbed_official | 19:112740acecfa | 7164 | |
| mbed_official | 19:112740acecfa | 7165 | /******************* Bit definition for DSI_VHBPCR register *************/ |
| AnnaBridge | 167:e84263d55307 | 7166 | #define DSI_VHBPCR_HBP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7167 | #define DSI_VHBPCR_HBP_Msk (0xFFFU << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 7168 | #define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */ |
| AnnaBridge | 167:e84263d55307 | 7169 | #define DSI_VHBPCR_HBP0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7170 | #define DSI_VHBPCR_HBP0_Msk (0x1U << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7171 | #define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk |
| AnnaBridge | 167:e84263d55307 | 7172 | #define DSI_VHBPCR_HBP1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7173 | #define DSI_VHBPCR_HBP1_Msk (0x1U << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7174 | #define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk |
| AnnaBridge | 167:e84263d55307 | 7175 | #define DSI_VHBPCR_HBP2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7176 | #define DSI_VHBPCR_HBP2_Msk (0x1U << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7177 | #define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk |
| AnnaBridge | 167:e84263d55307 | 7178 | #define DSI_VHBPCR_HBP3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7179 | #define DSI_VHBPCR_HBP3_Msk (0x1U << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7180 | #define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk |
| AnnaBridge | 167:e84263d55307 | 7181 | #define DSI_VHBPCR_HBP4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7182 | #define DSI_VHBPCR_HBP4_Msk (0x1U << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7183 | #define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk |
| AnnaBridge | 167:e84263d55307 | 7184 | #define DSI_VHBPCR_HBP5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7185 | #define DSI_VHBPCR_HBP5_Msk (0x1U << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7186 | #define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk |
| AnnaBridge | 167:e84263d55307 | 7187 | #define DSI_VHBPCR_HBP6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7188 | #define DSI_VHBPCR_HBP6_Msk (0x1U << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7189 | #define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk |
| AnnaBridge | 167:e84263d55307 | 7190 | #define DSI_VHBPCR_HBP7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7191 | #define DSI_VHBPCR_HBP7_Msk (0x1U << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7192 | #define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk |
| AnnaBridge | 167:e84263d55307 | 7193 | #define DSI_VHBPCR_HBP8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7194 | #define DSI_VHBPCR_HBP8_Msk (0x1U << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7195 | #define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk |
| AnnaBridge | 167:e84263d55307 | 7196 | #define DSI_VHBPCR_HBP9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7197 | #define DSI_VHBPCR_HBP9_Msk (0x1U << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7198 | #define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk |
| AnnaBridge | 167:e84263d55307 | 7199 | #define DSI_VHBPCR_HBP10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7200 | #define DSI_VHBPCR_HBP10_Msk (0x1U << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7201 | #define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk |
| AnnaBridge | 167:e84263d55307 | 7202 | #define DSI_VHBPCR_HBP11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7203 | #define DSI_VHBPCR_HBP11_Msk (0x1U << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7204 | #define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk |
| mbed_official | 19:112740acecfa | 7205 | |
| mbed_official | 19:112740acecfa | 7206 | /******************* Bit definition for DSI_VLCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 7207 | #define DSI_VLCR_HLINE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7208 | #define DSI_VLCR_HLINE_Msk (0x7FFFU << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 167:e84263d55307 | 7209 | #define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */ |
| AnnaBridge | 167:e84263d55307 | 7210 | #define DSI_VLCR_HLINE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7211 | #define DSI_VLCR_HLINE0_Msk (0x1U << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7212 | #define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk |
| AnnaBridge | 167:e84263d55307 | 7213 | #define DSI_VLCR_HLINE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7214 | #define DSI_VLCR_HLINE1_Msk (0x1U << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7215 | #define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk |
| AnnaBridge | 167:e84263d55307 | 7216 | #define DSI_VLCR_HLINE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7217 | #define DSI_VLCR_HLINE2_Msk (0x1U << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7218 | #define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk |
| AnnaBridge | 167:e84263d55307 | 7219 | #define DSI_VLCR_HLINE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7220 | #define DSI_VLCR_HLINE3_Msk (0x1U << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7221 | #define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk |
| AnnaBridge | 167:e84263d55307 | 7222 | #define DSI_VLCR_HLINE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7223 | #define DSI_VLCR_HLINE4_Msk (0x1U << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7224 | #define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk |
| AnnaBridge | 167:e84263d55307 | 7225 | #define DSI_VLCR_HLINE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7226 | #define DSI_VLCR_HLINE5_Msk (0x1U << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7227 | #define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk |
| AnnaBridge | 167:e84263d55307 | 7228 | #define DSI_VLCR_HLINE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7229 | #define DSI_VLCR_HLINE6_Msk (0x1U << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7230 | #define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk |
| AnnaBridge | 167:e84263d55307 | 7231 | #define DSI_VLCR_HLINE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7232 | #define DSI_VLCR_HLINE7_Msk (0x1U << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7233 | #define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk |
| AnnaBridge | 167:e84263d55307 | 7234 | #define DSI_VLCR_HLINE8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7235 | #define DSI_VLCR_HLINE8_Msk (0x1U << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7236 | #define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk |
| AnnaBridge | 167:e84263d55307 | 7237 | #define DSI_VLCR_HLINE9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7238 | #define DSI_VLCR_HLINE9_Msk (0x1U << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7239 | #define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk |
| AnnaBridge | 167:e84263d55307 | 7240 | #define DSI_VLCR_HLINE10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7241 | #define DSI_VLCR_HLINE10_Msk (0x1U << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7242 | #define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk |
| AnnaBridge | 167:e84263d55307 | 7243 | #define DSI_VLCR_HLINE11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7244 | #define DSI_VLCR_HLINE11_Msk (0x1U << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7245 | #define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk |
| AnnaBridge | 167:e84263d55307 | 7246 | #define DSI_VLCR_HLINE12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7247 | #define DSI_VLCR_HLINE12_Msk (0x1U << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7248 | #define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk |
| AnnaBridge | 167:e84263d55307 | 7249 | #define DSI_VLCR_HLINE13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7250 | #define DSI_VLCR_HLINE13_Msk (0x1U << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7251 | #define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk |
| AnnaBridge | 167:e84263d55307 | 7252 | #define DSI_VLCR_HLINE14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 7253 | #define DSI_VLCR_HLINE14_Msk (0x1U << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 7254 | #define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk |
| mbed_official | 19:112740acecfa | 7255 | |
| mbed_official | 19:112740acecfa | 7256 | /******************* Bit definition for DSI_VVSACR register *************/ |
| AnnaBridge | 167:e84263d55307 | 7257 | #define DSI_VVSACR_VSA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7258 | #define DSI_VVSACR_VSA_Msk (0x3FFU << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 167:e84263d55307 | 7259 | #define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */ |
| AnnaBridge | 167:e84263d55307 | 7260 | #define DSI_VVSACR_VSA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7261 | #define DSI_VVSACR_VSA0_Msk (0x1U << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7262 | #define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk |
| AnnaBridge | 167:e84263d55307 | 7263 | #define DSI_VVSACR_VSA1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7264 | #define DSI_VVSACR_VSA1_Msk (0x1U << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7265 | #define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk |
| AnnaBridge | 167:e84263d55307 | 7266 | #define DSI_VVSACR_VSA2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7267 | #define DSI_VVSACR_VSA2_Msk (0x1U << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7268 | #define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk |
| AnnaBridge | 167:e84263d55307 | 7269 | #define DSI_VVSACR_VSA3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7270 | #define DSI_VVSACR_VSA3_Msk (0x1U << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7271 | #define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk |
| AnnaBridge | 167:e84263d55307 | 7272 | #define DSI_VVSACR_VSA4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7273 | #define DSI_VVSACR_VSA4_Msk (0x1U << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7274 | #define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk |
| AnnaBridge | 167:e84263d55307 | 7275 | #define DSI_VVSACR_VSA5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7276 | #define DSI_VVSACR_VSA5_Msk (0x1U << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7277 | #define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk |
| AnnaBridge | 167:e84263d55307 | 7278 | #define DSI_VVSACR_VSA6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7279 | #define DSI_VVSACR_VSA6_Msk (0x1U << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7280 | #define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk |
| AnnaBridge | 167:e84263d55307 | 7281 | #define DSI_VVSACR_VSA7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7282 | #define DSI_VVSACR_VSA7_Msk (0x1U << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7283 | #define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk |
| AnnaBridge | 167:e84263d55307 | 7284 | #define DSI_VVSACR_VSA8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7285 | #define DSI_VVSACR_VSA8_Msk (0x1U << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7286 | #define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk |
| AnnaBridge | 167:e84263d55307 | 7287 | #define DSI_VVSACR_VSA9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7288 | #define DSI_VVSACR_VSA9_Msk (0x1U << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7289 | #define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk |
| mbed_official | 19:112740acecfa | 7290 | |
| mbed_official | 19:112740acecfa | 7291 | /******************* Bit definition for DSI_VVBPCR register *************/ |
| AnnaBridge | 167:e84263d55307 | 7292 | #define DSI_VVBPCR_VBP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7293 | #define DSI_VVBPCR_VBP_Msk (0x3FFU << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 167:e84263d55307 | 7294 | #define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */ |
| AnnaBridge | 167:e84263d55307 | 7295 | #define DSI_VVBPCR_VBP0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7296 | #define DSI_VVBPCR_VBP0_Msk (0x1U << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7297 | #define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk |
| AnnaBridge | 167:e84263d55307 | 7298 | #define DSI_VVBPCR_VBP1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7299 | #define DSI_VVBPCR_VBP1_Msk (0x1U << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7300 | #define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk |
| AnnaBridge | 167:e84263d55307 | 7301 | #define DSI_VVBPCR_VBP2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7302 | #define DSI_VVBPCR_VBP2_Msk (0x1U << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7303 | #define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk |
| AnnaBridge | 167:e84263d55307 | 7304 | #define DSI_VVBPCR_VBP3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7305 | #define DSI_VVBPCR_VBP3_Msk (0x1U << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7306 | #define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk |
| AnnaBridge | 167:e84263d55307 | 7307 | #define DSI_VVBPCR_VBP4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7308 | #define DSI_VVBPCR_VBP4_Msk (0x1U << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7309 | #define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk |
| AnnaBridge | 167:e84263d55307 | 7310 | #define DSI_VVBPCR_VBP5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7311 | #define DSI_VVBPCR_VBP5_Msk (0x1U << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7312 | #define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk |
| AnnaBridge | 167:e84263d55307 | 7313 | #define DSI_VVBPCR_VBP6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7314 | #define DSI_VVBPCR_VBP6_Msk (0x1U << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7315 | #define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk |
| AnnaBridge | 167:e84263d55307 | 7316 | #define DSI_VVBPCR_VBP7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7317 | #define DSI_VVBPCR_VBP7_Msk (0x1U << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7318 | #define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk |
| AnnaBridge | 167:e84263d55307 | 7319 | #define DSI_VVBPCR_VBP8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7320 | #define DSI_VVBPCR_VBP8_Msk (0x1U << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7321 | #define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk |
| AnnaBridge | 167:e84263d55307 | 7322 | #define DSI_VVBPCR_VBP9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7323 | #define DSI_VVBPCR_VBP9_Msk (0x1U << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7324 | #define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk |
| mbed_official | 19:112740acecfa | 7325 | |
| mbed_official | 19:112740acecfa | 7326 | /******************* Bit definition for DSI_VVFPCR register *************/ |
| AnnaBridge | 167:e84263d55307 | 7327 | #define DSI_VVFPCR_VFP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7328 | #define DSI_VVFPCR_VFP_Msk (0x3FFU << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 167:e84263d55307 | 7329 | #define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */ |
| AnnaBridge | 167:e84263d55307 | 7330 | #define DSI_VVFPCR_VFP0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7331 | #define DSI_VVFPCR_VFP0_Msk (0x1U << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7332 | #define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk |
| AnnaBridge | 167:e84263d55307 | 7333 | #define DSI_VVFPCR_VFP1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7334 | #define DSI_VVFPCR_VFP1_Msk (0x1U << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7335 | #define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk |
| AnnaBridge | 167:e84263d55307 | 7336 | #define DSI_VVFPCR_VFP2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7337 | #define DSI_VVFPCR_VFP2_Msk (0x1U << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7338 | #define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk |
| AnnaBridge | 167:e84263d55307 | 7339 | #define DSI_VVFPCR_VFP3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7340 | #define DSI_VVFPCR_VFP3_Msk (0x1U << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7341 | #define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk |
| AnnaBridge | 167:e84263d55307 | 7342 | #define DSI_VVFPCR_VFP4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7343 | #define DSI_VVFPCR_VFP4_Msk (0x1U << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7344 | #define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk |
| AnnaBridge | 167:e84263d55307 | 7345 | #define DSI_VVFPCR_VFP5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7346 | #define DSI_VVFPCR_VFP5_Msk (0x1U << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7347 | #define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk |
| AnnaBridge | 167:e84263d55307 | 7348 | #define DSI_VVFPCR_VFP6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7349 | #define DSI_VVFPCR_VFP6_Msk (0x1U << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7350 | #define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk |
| AnnaBridge | 167:e84263d55307 | 7351 | #define DSI_VVFPCR_VFP7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7352 | #define DSI_VVFPCR_VFP7_Msk (0x1U << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7353 | #define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk |
| AnnaBridge | 167:e84263d55307 | 7354 | #define DSI_VVFPCR_VFP8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7355 | #define DSI_VVFPCR_VFP8_Msk (0x1U << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7356 | #define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk |
| AnnaBridge | 167:e84263d55307 | 7357 | #define DSI_VVFPCR_VFP9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7358 | #define DSI_VVFPCR_VFP9_Msk (0x1U << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7359 | #define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk |
| mbed_official | 19:112740acecfa | 7360 | |
| mbed_official | 19:112740acecfa | 7361 | /******************* Bit definition for DSI_VVACR register **************/ |
| AnnaBridge | 167:e84263d55307 | 7362 | #define DSI_VVACR_VA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7363 | #define DSI_VVACR_VA_Msk (0x3FFFU << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 167:e84263d55307 | 7364 | #define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */ |
| AnnaBridge | 167:e84263d55307 | 7365 | #define DSI_VVACR_VA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7366 | #define DSI_VVACR_VA0_Msk (0x1U << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7367 | #define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk |
| AnnaBridge | 167:e84263d55307 | 7368 | #define DSI_VVACR_VA1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7369 | #define DSI_VVACR_VA1_Msk (0x1U << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7370 | #define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk |
| AnnaBridge | 167:e84263d55307 | 7371 | #define DSI_VVACR_VA2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7372 | #define DSI_VVACR_VA2_Msk (0x1U << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7373 | #define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk |
| AnnaBridge | 167:e84263d55307 | 7374 | #define DSI_VVACR_VA3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7375 | #define DSI_VVACR_VA3_Msk (0x1U << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7376 | #define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk |
| AnnaBridge | 167:e84263d55307 | 7377 | #define DSI_VVACR_VA4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7378 | #define DSI_VVACR_VA4_Msk (0x1U << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7379 | #define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk |
| AnnaBridge | 167:e84263d55307 | 7380 | #define DSI_VVACR_VA5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7381 | #define DSI_VVACR_VA5_Msk (0x1U << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7382 | #define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk |
| AnnaBridge | 167:e84263d55307 | 7383 | #define DSI_VVACR_VA6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7384 | #define DSI_VVACR_VA6_Msk (0x1U << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7385 | #define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk |
| AnnaBridge | 167:e84263d55307 | 7386 | #define DSI_VVACR_VA7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7387 | #define DSI_VVACR_VA7_Msk (0x1U << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7388 | #define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk |
| AnnaBridge | 167:e84263d55307 | 7389 | #define DSI_VVACR_VA8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7390 | #define DSI_VVACR_VA8_Msk (0x1U << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7391 | #define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk |
| AnnaBridge | 167:e84263d55307 | 7392 | #define DSI_VVACR_VA9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7393 | #define DSI_VVACR_VA9_Msk (0x1U << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7394 | #define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk |
| AnnaBridge | 167:e84263d55307 | 7395 | #define DSI_VVACR_VA10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7396 | #define DSI_VVACR_VA10_Msk (0x1U << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7397 | #define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk |
| AnnaBridge | 167:e84263d55307 | 7398 | #define DSI_VVACR_VA11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7399 | #define DSI_VVACR_VA11_Msk (0x1U << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7400 | #define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk |
| AnnaBridge | 167:e84263d55307 | 7401 | #define DSI_VVACR_VA12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7402 | #define DSI_VVACR_VA12_Msk (0x1U << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7403 | #define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk |
| AnnaBridge | 167:e84263d55307 | 7404 | #define DSI_VVACR_VA13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7405 | #define DSI_VVACR_VA13_Msk (0x1U << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7406 | #define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk |
| mbed_official | 19:112740acecfa | 7407 | |
| mbed_official | 19:112740acecfa | 7408 | /******************* Bit definition for DSI_LCCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 7409 | #define DSI_LCCR_CMDSIZE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7410 | #define DSI_LCCR_CMDSIZE_Msk (0xFFFFU << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 7411 | #define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */ |
| AnnaBridge | 167:e84263d55307 | 7412 | #define DSI_LCCR_CMDSIZE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7413 | #define DSI_LCCR_CMDSIZE0_Msk (0x1U << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7414 | #define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk |
| AnnaBridge | 167:e84263d55307 | 7415 | #define DSI_LCCR_CMDSIZE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7416 | #define DSI_LCCR_CMDSIZE1_Msk (0x1U << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7417 | #define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk |
| AnnaBridge | 167:e84263d55307 | 7418 | #define DSI_LCCR_CMDSIZE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7419 | #define DSI_LCCR_CMDSIZE2_Msk (0x1U << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7420 | #define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk |
| AnnaBridge | 167:e84263d55307 | 7421 | #define DSI_LCCR_CMDSIZE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7422 | #define DSI_LCCR_CMDSIZE3_Msk (0x1U << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7423 | #define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk |
| AnnaBridge | 167:e84263d55307 | 7424 | #define DSI_LCCR_CMDSIZE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7425 | #define DSI_LCCR_CMDSIZE4_Msk (0x1U << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7426 | #define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk |
| AnnaBridge | 167:e84263d55307 | 7427 | #define DSI_LCCR_CMDSIZE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7428 | #define DSI_LCCR_CMDSIZE5_Msk (0x1U << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7429 | #define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk |
| AnnaBridge | 167:e84263d55307 | 7430 | #define DSI_LCCR_CMDSIZE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7431 | #define DSI_LCCR_CMDSIZE6_Msk (0x1U << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7432 | #define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk |
| AnnaBridge | 167:e84263d55307 | 7433 | #define DSI_LCCR_CMDSIZE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7434 | #define DSI_LCCR_CMDSIZE7_Msk (0x1U << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7435 | #define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk |
| AnnaBridge | 167:e84263d55307 | 7436 | #define DSI_LCCR_CMDSIZE8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7437 | #define DSI_LCCR_CMDSIZE8_Msk (0x1U << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7438 | #define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk |
| AnnaBridge | 167:e84263d55307 | 7439 | #define DSI_LCCR_CMDSIZE9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7440 | #define DSI_LCCR_CMDSIZE9_Msk (0x1U << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7441 | #define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk |
| AnnaBridge | 167:e84263d55307 | 7442 | #define DSI_LCCR_CMDSIZE10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7443 | #define DSI_LCCR_CMDSIZE10_Msk (0x1U << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7444 | #define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk |
| AnnaBridge | 167:e84263d55307 | 7445 | #define DSI_LCCR_CMDSIZE11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7446 | #define DSI_LCCR_CMDSIZE11_Msk (0x1U << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7447 | #define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk |
| AnnaBridge | 167:e84263d55307 | 7448 | #define DSI_LCCR_CMDSIZE12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7449 | #define DSI_LCCR_CMDSIZE12_Msk (0x1U << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7450 | #define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk |
| AnnaBridge | 167:e84263d55307 | 7451 | #define DSI_LCCR_CMDSIZE13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7452 | #define DSI_LCCR_CMDSIZE13_Msk (0x1U << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7453 | #define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk |
| AnnaBridge | 167:e84263d55307 | 7454 | #define DSI_LCCR_CMDSIZE14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 7455 | #define DSI_LCCR_CMDSIZE14_Msk (0x1U << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 7456 | #define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk |
| AnnaBridge | 167:e84263d55307 | 7457 | #define DSI_LCCR_CMDSIZE15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 7458 | #define DSI_LCCR_CMDSIZE15_Msk (0x1U << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 7459 | #define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk |
| mbed_official | 19:112740acecfa | 7460 | |
| mbed_official | 19:112740acecfa | 7461 | /******************* Bit definition for DSI_CMCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 7462 | #define DSI_CMCR_TEARE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7463 | #define DSI_CMCR_TEARE_Msk (0x1U << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7464 | #define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */ |
| AnnaBridge | 167:e84263d55307 | 7465 | #define DSI_CMCR_ARE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7466 | #define DSI_CMCR_ARE_Msk (0x1U << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7467 | #define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */ |
| AnnaBridge | 167:e84263d55307 | 7468 | #define DSI_CMCR_GSW0TX_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7469 | #define DSI_CMCR_GSW0TX_Msk (0x1U << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7470 | #define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7471 | #define DSI_CMCR_GSW1TX_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7472 | #define DSI_CMCR_GSW1TX_Msk (0x1U << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7473 | #define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7474 | #define DSI_CMCR_GSW2TX_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7475 | #define DSI_CMCR_GSW2TX_Msk (0x1U << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7476 | #define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7477 | #define DSI_CMCR_GSR0TX_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7478 | #define DSI_CMCR_GSR0TX_Msk (0x1U << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7479 | #define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7480 | #define DSI_CMCR_GSR1TX_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7481 | #define DSI_CMCR_GSR1TX_Msk (0x1U << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7482 | #define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7483 | #define DSI_CMCR_GSR2TX_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7484 | #define DSI_CMCR_GSR2TX_Msk (0x1U << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7485 | #define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7486 | #define DSI_CMCR_GLWTX_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 7487 | #define DSI_CMCR_GLWTX_Msk (0x1U << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 7488 | #define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7489 | #define DSI_CMCR_DSW0TX_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 7490 | #define DSI_CMCR_DSW0TX_Msk (0x1U << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 7491 | #define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7492 | #define DSI_CMCR_DSW1TX_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 7493 | #define DSI_CMCR_DSW1TX_Msk (0x1U << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 7494 | #define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7495 | #define DSI_CMCR_DSR0TX_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 7496 | #define DSI_CMCR_DSR0TX_Msk (0x1U << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 7497 | #define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7498 | #define DSI_CMCR_DLWTX_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 7499 | #define DSI_CMCR_DLWTX_Msk (0x1U << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 7500 | #define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */ |
| AnnaBridge | 167:e84263d55307 | 7501 | #define DSI_CMCR_MRDPS_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 7502 | #define DSI_CMCR_MRDPS_Msk (0x1U << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 7503 | #define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */ |
| mbed_official | 19:112740acecfa | 7504 | |
| mbed_official | 19:112740acecfa | 7505 | /******************* Bit definition for DSI_GHCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 7506 | #define DSI_GHCR_DT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7507 | #define DSI_GHCR_DT_Msk (0x3FU << DSI_GHCR_DT_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 167:e84263d55307 | 7508 | #define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */ |
| AnnaBridge | 167:e84263d55307 | 7509 | #define DSI_GHCR_DT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7510 | #define DSI_GHCR_DT0_Msk (0x1U << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7511 | #define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk |
| AnnaBridge | 167:e84263d55307 | 7512 | #define DSI_GHCR_DT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7513 | #define DSI_GHCR_DT1_Msk (0x1U << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7514 | #define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk |
| AnnaBridge | 167:e84263d55307 | 7515 | #define DSI_GHCR_DT2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7516 | #define DSI_GHCR_DT2_Msk (0x1U << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7517 | #define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk |
| AnnaBridge | 167:e84263d55307 | 7518 | #define DSI_GHCR_DT3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7519 | #define DSI_GHCR_DT3_Msk (0x1U << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7520 | #define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk |
| AnnaBridge | 167:e84263d55307 | 7521 | #define DSI_GHCR_DT4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7522 | #define DSI_GHCR_DT4_Msk (0x1U << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7523 | #define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk |
| AnnaBridge | 167:e84263d55307 | 7524 | #define DSI_GHCR_DT5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7525 | #define DSI_GHCR_DT5_Msk (0x1U << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7526 | #define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk |
| AnnaBridge | 167:e84263d55307 | 7527 | |
| AnnaBridge | 167:e84263d55307 | 7528 | #define DSI_GHCR_VCID_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7529 | #define DSI_GHCR_VCID_Msk (0x3U << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 7530 | #define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */ |
| AnnaBridge | 167:e84263d55307 | 7531 | #define DSI_GHCR_VCID0_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7532 | #define DSI_GHCR_VCID0_Msk (0x1U << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7533 | #define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk |
| AnnaBridge | 167:e84263d55307 | 7534 | #define DSI_GHCR_VCID1_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7535 | #define DSI_GHCR_VCID1_Msk (0x1U << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7536 | #define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk |
| AnnaBridge | 167:e84263d55307 | 7537 | |
| AnnaBridge | 167:e84263d55307 | 7538 | #define DSI_GHCR_WCLSB_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7539 | #define DSI_GHCR_WCLSB_Msk (0xFFU << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 7540 | #define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */ |
| AnnaBridge | 167:e84263d55307 | 7541 | #define DSI_GHCR_WCLSB0_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7542 | #define DSI_GHCR_WCLSB0_Msk (0x1U << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7543 | #define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk |
| AnnaBridge | 167:e84263d55307 | 7544 | #define DSI_GHCR_WCLSB1_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7545 | #define DSI_GHCR_WCLSB1_Msk (0x1U << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7546 | #define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk |
| AnnaBridge | 167:e84263d55307 | 7547 | #define DSI_GHCR_WCLSB2_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7548 | #define DSI_GHCR_WCLSB2_Msk (0x1U << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7549 | #define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk |
| AnnaBridge | 167:e84263d55307 | 7550 | #define DSI_GHCR_WCLSB3_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7551 | #define DSI_GHCR_WCLSB3_Msk (0x1U << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7552 | #define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk |
| AnnaBridge | 167:e84263d55307 | 7553 | #define DSI_GHCR_WCLSB4_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7554 | #define DSI_GHCR_WCLSB4_Msk (0x1U << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7555 | #define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk |
| AnnaBridge | 167:e84263d55307 | 7556 | #define DSI_GHCR_WCLSB5_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7557 | #define DSI_GHCR_WCLSB5_Msk (0x1U << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7558 | #define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk |
| AnnaBridge | 167:e84263d55307 | 7559 | #define DSI_GHCR_WCLSB6_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 7560 | #define DSI_GHCR_WCLSB6_Msk (0x1U << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 7561 | #define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk |
| AnnaBridge | 167:e84263d55307 | 7562 | #define DSI_GHCR_WCLSB7_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 7563 | #define DSI_GHCR_WCLSB7_Msk (0x1U << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 7564 | #define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk |
| AnnaBridge | 167:e84263d55307 | 7565 | |
| AnnaBridge | 167:e84263d55307 | 7566 | #define DSI_GHCR_WCMSB_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 7567 | #define DSI_GHCR_WCMSB_Msk (0xFFU << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 7568 | #define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */ |
| AnnaBridge | 167:e84263d55307 | 7569 | #define DSI_GHCR_WCMSB0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 7570 | #define DSI_GHCR_WCMSB0_Msk (0x1U << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 7571 | #define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk |
| AnnaBridge | 167:e84263d55307 | 7572 | #define DSI_GHCR_WCMSB1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 7573 | #define DSI_GHCR_WCMSB1_Msk (0x1U << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 7574 | #define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk |
| AnnaBridge | 167:e84263d55307 | 7575 | #define DSI_GHCR_WCMSB2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 7576 | #define DSI_GHCR_WCMSB2_Msk (0x1U << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 7577 | #define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk |
| AnnaBridge | 167:e84263d55307 | 7578 | #define DSI_GHCR_WCMSB3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 7579 | #define DSI_GHCR_WCMSB3_Msk (0x1U << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 7580 | #define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk |
| AnnaBridge | 167:e84263d55307 | 7581 | #define DSI_GHCR_WCMSB4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 7582 | #define DSI_GHCR_WCMSB4_Msk (0x1U << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 7583 | #define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk |
| AnnaBridge | 167:e84263d55307 | 7584 | #define DSI_GHCR_WCMSB5_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 7585 | #define DSI_GHCR_WCMSB5_Msk (0x1U << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 7586 | #define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk |
| AnnaBridge | 167:e84263d55307 | 7587 | #define DSI_GHCR_WCMSB6_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 7588 | #define DSI_GHCR_WCMSB6_Msk (0x1U << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 7589 | #define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk |
| AnnaBridge | 167:e84263d55307 | 7590 | #define DSI_GHCR_WCMSB7_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 7591 | #define DSI_GHCR_WCMSB7_Msk (0x1U << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 7592 | #define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk |
| mbed_official | 19:112740acecfa | 7593 | |
| mbed_official | 19:112740acecfa | 7594 | /******************* Bit definition for DSI_GPDR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 7595 | #define DSI_GPDR_DATA1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7596 | #define DSI_GPDR_DATA1_Msk (0xFFU << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 7597 | #define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */ |
| AnnaBridge | 167:e84263d55307 | 7598 | #define DSI_GPDR_DATA1_0 (0x01U << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7599 | #define DSI_GPDR_DATA1_1 (0x02U << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7600 | #define DSI_GPDR_DATA1_2 (0x04U << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7601 | #define DSI_GPDR_DATA1_3 (0x08U << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7602 | #define DSI_GPDR_DATA1_4 (0x10U << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7603 | #define DSI_GPDR_DATA1_5 (0x20U << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7604 | #define DSI_GPDR_DATA1_6 (0x40U << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7605 | #define DSI_GPDR_DATA1_7 (0x80U << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7606 | |
| AnnaBridge | 167:e84263d55307 | 7607 | #define DSI_GPDR_DATA2_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7608 | #define DSI_GPDR_DATA2_Msk (0xFFU << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 7609 | #define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */ |
| AnnaBridge | 167:e84263d55307 | 7610 | #define DSI_GPDR_DATA2_0 (0x01U << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7611 | #define DSI_GPDR_DATA2_1 (0x02U << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7612 | #define DSI_GPDR_DATA2_2 (0x04U << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7613 | #define DSI_GPDR_DATA2_3 (0x08U << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7614 | #define DSI_GPDR_DATA2_4 (0x10U << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7615 | #define DSI_GPDR_DATA2_5 (0x20U << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7616 | #define DSI_GPDR_DATA2_6 (0x40U << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 7617 | #define DSI_GPDR_DATA2_7 (0x80U << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 7618 | |
| AnnaBridge | 167:e84263d55307 | 7619 | #define DSI_GPDR_DATA3_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 7620 | #define DSI_GPDR_DATA3_Msk (0xFFU << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 7621 | #define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */ |
| AnnaBridge | 167:e84263d55307 | 7622 | #define DSI_GPDR_DATA3_0 (0x01U << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 7623 | #define DSI_GPDR_DATA3_1 (0x02U << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 7624 | #define DSI_GPDR_DATA3_2 (0x04U << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 7625 | #define DSI_GPDR_DATA3_3 (0x08U << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 7626 | #define DSI_GPDR_DATA3_4 (0x10U << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 7627 | #define DSI_GPDR_DATA3_5 (0x20U << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 7628 | #define DSI_GPDR_DATA3_6 (0x40U << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 7629 | #define DSI_GPDR_DATA3_7 (0x80U << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 7630 | |
| AnnaBridge | 167:e84263d55307 | 7631 | #define DSI_GPDR_DATA4_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 7632 | #define DSI_GPDR_DATA4_Msk (0xFFU << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 7633 | #define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */ |
| AnnaBridge | 167:e84263d55307 | 7634 | #define DSI_GPDR_DATA4_0 (0x01U << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 7635 | #define DSI_GPDR_DATA4_1 (0x02U << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 7636 | #define DSI_GPDR_DATA4_2 (0x04U << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 7637 | #define DSI_GPDR_DATA4_3 (0x08U << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 7638 | #define DSI_GPDR_DATA4_4 (0x10U << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 7639 | #define DSI_GPDR_DATA4_5 (0x20U << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 7640 | #define DSI_GPDR_DATA4_6 (0x40U << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 7641 | #define DSI_GPDR_DATA4_7 (0x80U << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */ |
| mbed_official | 19:112740acecfa | 7642 | |
| mbed_official | 19:112740acecfa | 7643 | /******************* Bit definition for DSI_GPSR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 7644 | #define DSI_GPSR_CMDFE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7645 | #define DSI_GPSR_CMDFE_Msk (0x1U << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7646 | #define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */ |
| AnnaBridge | 167:e84263d55307 | 7647 | #define DSI_GPSR_CMDFF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7648 | #define DSI_GPSR_CMDFF_Msk (0x1U << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7649 | #define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */ |
| AnnaBridge | 167:e84263d55307 | 7650 | #define DSI_GPSR_PWRFE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7651 | #define DSI_GPSR_PWRFE_Msk (0x1U << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7652 | #define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */ |
| AnnaBridge | 167:e84263d55307 | 7653 | #define DSI_GPSR_PWRFF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7654 | #define DSI_GPSR_PWRFF_Msk (0x1U << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7655 | #define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */ |
| AnnaBridge | 167:e84263d55307 | 7656 | #define DSI_GPSR_PRDFE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7657 | #define DSI_GPSR_PRDFE_Msk (0x1U << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7658 | #define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */ |
| AnnaBridge | 167:e84263d55307 | 7659 | #define DSI_GPSR_PRDFF_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7660 | #define DSI_GPSR_PRDFF_Msk (0x1U << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7661 | #define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */ |
| AnnaBridge | 167:e84263d55307 | 7662 | #define DSI_GPSR_RCB_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7663 | #define DSI_GPSR_RCB_Msk (0x1U << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7664 | #define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */ |
| mbed_official | 19:112740acecfa | 7665 | |
| mbed_official | 19:112740acecfa | 7666 | /******************* Bit definition for DSI_TCCR0 register **************/ |
| AnnaBridge | 167:e84263d55307 | 7667 | #define DSI_TCCR0_LPRX_TOCNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7668 | #define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 7669 | #define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */ |
| AnnaBridge | 167:e84263d55307 | 7670 | #define DSI_TCCR0_LPRX_TOCNT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7671 | #define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7672 | #define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk |
| AnnaBridge | 167:e84263d55307 | 7673 | #define DSI_TCCR0_LPRX_TOCNT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7674 | #define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7675 | #define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk |
| AnnaBridge | 167:e84263d55307 | 7676 | #define DSI_TCCR0_LPRX_TOCNT2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7677 | #define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7678 | #define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk |
| AnnaBridge | 167:e84263d55307 | 7679 | #define DSI_TCCR0_LPRX_TOCNT3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7680 | #define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7681 | #define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk |
| AnnaBridge | 167:e84263d55307 | 7682 | #define DSI_TCCR0_LPRX_TOCNT4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7683 | #define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7684 | #define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk |
| AnnaBridge | 167:e84263d55307 | 7685 | #define DSI_TCCR0_LPRX_TOCNT5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7686 | #define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7687 | #define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk |
| AnnaBridge | 167:e84263d55307 | 7688 | #define DSI_TCCR0_LPRX_TOCNT6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7689 | #define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7690 | #define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk |
| AnnaBridge | 167:e84263d55307 | 7691 | #define DSI_TCCR0_LPRX_TOCNT7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7692 | #define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7693 | #define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk |
| AnnaBridge | 167:e84263d55307 | 7694 | #define DSI_TCCR0_LPRX_TOCNT8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7695 | #define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7696 | #define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk |
| AnnaBridge | 167:e84263d55307 | 7697 | #define DSI_TCCR0_LPRX_TOCNT9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7698 | #define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7699 | #define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk |
| AnnaBridge | 167:e84263d55307 | 7700 | #define DSI_TCCR0_LPRX_TOCNT10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7701 | #define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7702 | #define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk |
| AnnaBridge | 167:e84263d55307 | 7703 | #define DSI_TCCR0_LPRX_TOCNT11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7704 | #define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7705 | #define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk |
| AnnaBridge | 167:e84263d55307 | 7706 | #define DSI_TCCR0_LPRX_TOCNT12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7707 | #define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7708 | #define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk |
| AnnaBridge | 167:e84263d55307 | 7709 | #define DSI_TCCR0_LPRX_TOCNT13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7710 | #define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7711 | #define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk |
| AnnaBridge | 167:e84263d55307 | 7712 | #define DSI_TCCR0_LPRX_TOCNT14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 7713 | #define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 7714 | #define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk |
| AnnaBridge | 167:e84263d55307 | 7715 | #define DSI_TCCR0_LPRX_TOCNT15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 7716 | #define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 7717 | #define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk |
| AnnaBridge | 167:e84263d55307 | 7718 | |
| AnnaBridge | 167:e84263d55307 | 7719 | #define DSI_TCCR0_HSTX_TOCNT_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 7720 | #define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 7721 | #define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */ |
| AnnaBridge | 167:e84263d55307 | 7722 | #define DSI_TCCR0_HSTX_TOCNT0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 7723 | #define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 7724 | #define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk |
| AnnaBridge | 167:e84263d55307 | 7725 | #define DSI_TCCR0_HSTX_TOCNT1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 7726 | #define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 7727 | #define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk |
| AnnaBridge | 167:e84263d55307 | 7728 | #define DSI_TCCR0_HSTX_TOCNT2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 7729 | #define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 7730 | #define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk |
| AnnaBridge | 167:e84263d55307 | 7731 | #define DSI_TCCR0_HSTX_TOCNT3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 7732 | #define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 7733 | #define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk |
| AnnaBridge | 167:e84263d55307 | 7734 | #define DSI_TCCR0_HSTX_TOCNT4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 7735 | #define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 7736 | #define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk |
| AnnaBridge | 167:e84263d55307 | 7737 | #define DSI_TCCR0_HSTX_TOCNT5_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 7738 | #define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 7739 | #define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk |
| AnnaBridge | 167:e84263d55307 | 7740 | #define DSI_TCCR0_HSTX_TOCNT6_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 7741 | #define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 7742 | #define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk |
| AnnaBridge | 167:e84263d55307 | 7743 | #define DSI_TCCR0_HSTX_TOCNT7_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 7744 | #define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 7745 | #define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk |
| AnnaBridge | 167:e84263d55307 | 7746 | #define DSI_TCCR0_HSTX_TOCNT8_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 7747 | #define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 7748 | #define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk |
| AnnaBridge | 167:e84263d55307 | 7749 | #define DSI_TCCR0_HSTX_TOCNT9_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 7750 | #define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 7751 | #define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk |
| AnnaBridge | 167:e84263d55307 | 7752 | #define DSI_TCCR0_HSTX_TOCNT10_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 7753 | #define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 7754 | #define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk |
| AnnaBridge | 167:e84263d55307 | 7755 | #define DSI_TCCR0_HSTX_TOCNT11_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 7756 | #define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 7757 | #define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk |
| AnnaBridge | 167:e84263d55307 | 7758 | #define DSI_TCCR0_HSTX_TOCNT12_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 7759 | #define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 7760 | #define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk |
| AnnaBridge | 167:e84263d55307 | 7761 | #define DSI_TCCR0_HSTX_TOCNT13_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 7762 | #define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 7763 | #define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk |
| AnnaBridge | 167:e84263d55307 | 7764 | #define DSI_TCCR0_HSTX_TOCNT14_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 7765 | #define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 7766 | #define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk |
| AnnaBridge | 167:e84263d55307 | 7767 | #define DSI_TCCR0_HSTX_TOCNT15_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 7768 | #define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 7769 | #define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk |
| mbed_official | 19:112740acecfa | 7770 | |
| mbed_official | 19:112740acecfa | 7771 | /******************* Bit definition for DSI_TCCR1 register **************/ |
| AnnaBridge | 167:e84263d55307 | 7772 | #define DSI_TCCR1_HSRD_TOCNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7773 | #define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFU << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 7774 | #define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */ |
| AnnaBridge | 167:e84263d55307 | 7775 | #define DSI_TCCR1_HSRD_TOCNT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7776 | #define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7777 | #define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk |
| AnnaBridge | 167:e84263d55307 | 7778 | #define DSI_TCCR1_HSRD_TOCNT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7779 | #define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7780 | #define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk |
| AnnaBridge | 167:e84263d55307 | 7781 | #define DSI_TCCR1_HSRD_TOCNT2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7782 | #define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7783 | #define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk |
| AnnaBridge | 167:e84263d55307 | 7784 | #define DSI_TCCR1_HSRD_TOCNT3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7785 | #define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7786 | #define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk |
| AnnaBridge | 167:e84263d55307 | 7787 | #define DSI_TCCR1_HSRD_TOCNT4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7788 | #define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7789 | #define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk |
| AnnaBridge | 167:e84263d55307 | 7790 | #define DSI_TCCR1_HSRD_TOCNT5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7791 | #define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7792 | #define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk |
| AnnaBridge | 167:e84263d55307 | 7793 | #define DSI_TCCR1_HSRD_TOCNT6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7794 | #define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7795 | #define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk |
| AnnaBridge | 167:e84263d55307 | 7796 | #define DSI_TCCR1_HSRD_TOCNT7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7797 | #define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7798 | #define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk |
| AnnaBridge | 167:e84263d55307 | 7799 | #define DSI_TCCR1_HSRD_TOCNT8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7800 | #define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7801 | #define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk |
| AnnaBridge | 167:e84263d55307 | 7802 | #define DSI_TCCR1_HSRD_TOCNT9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7803 | #define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7804 | #define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk |
| AnnaBridge | 167:e84263d55307 | 7805 | #define DSI_TCCR1_HSRD_TOCNT10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7806 | #define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7807 | #define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk |
| AnnaBridge | 167:e84263d55307 | 7808 | #define DSI_TCCR1_HSRD_TOCNT11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7809 | #define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7810 | #define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk |
| AnnaBridge | 167:e84263d55307 | 7811 | #define DSI_TCCR1_HSRD_TOCNT12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7812 | #define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7813 | #define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk |
| AnnaBridge | 167:e84263d55307 | 7814 | #define DSI_TCCR1_HSRD_TOCNT13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7815 | #define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7816 | #define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk |
| AnnaBridge | 167:e84263d55307 | 7817 | #define DSI_TCCR1_HSRD_TOCNT14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 7818 | #define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 7819 | #define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk |
| AnnaBridge | 167:e84263d55307 | 7820 | #define DSI_TCCR1_HSRD_TOCNT15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 7821 | #define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 7822 | #define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk |
| mbed_official | 19:112740acecfa | 7823 | |
| mbed_official | 19:112740acecfa | 7824 | /******************* Bit definition for DSI_TCCR2 register **************/ |
| AnnaBridge | 167:e84263d55307 | 7825 | #define DSI_TCCR2_LPRD_TOCNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7826 | #define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFU << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 7827 | #define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */ |
| AnnaBridge | 167:e84263d55307 | 7828 | #define DSI_TCCR2_LPRD_TOCNT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7829 | #define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7830 | #define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk |
| AnnaBridge | 167:e84263d55307 | 7831 | #define DSI_TCCR2_LPRD_TOCNT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7832 | #define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7833 | #define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk |
| AnnaBridge | 167:e84263d55307 | 7834 | #define DSI_TCCR2_LPRD_TOCNT2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7835 | #define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7836 | #define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk |
| AnnaBridge | 167:e84263d55307 | 7837 | #define DSI_TCCR2_LPRD_TOCNT3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7838 | #define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7839 | #define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk |
| AnnaBridge | 167:e84263d55307 | 7840 | #define DSI_TCCR2_LPRD_TOCNT4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7841 | #define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7842 | #define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk |
| AnnaBridge | 167:e84263d55307 | 7843 | #define DSI_TCCR2_LPRD_TOCNT5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7844 | #define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7845 | #define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk |
| AnnaBridge | 167:e84263d55307 | 7846 | #define DSI_TCCR2_LPRD_TOCNT6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7847 | #define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7848 | #define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk |
| AnnaBridge | 167:e84263d55307 | 7849 | #define DSI_TCCR2_LPRD_TOCNT7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7850 | #define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7851 | #define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk |
| AnnaBridge | 167:e84263d55307 | 7852 | #define DSI_TCCR2_LPRD_TOCNT8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7853 | #define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7854 | #define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk |
| AnnaBridge | 167:e84263d55307 | 7855 | #define DSI_TCCR2_LPRD_TOCNT9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7856 | #define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7857 | #define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk |
| AnnaBridge | 167:e84263d55307 | 7858 | #define DSI_TCCR2_LPRD_TOCNT10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7859 | #define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7860 | #define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk |
| AnnaBridge | 167:e84263d55307 | 7861 | #define DSI_TCCR2_LPRD_TOCNT11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7862 | #define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7863 | #define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk |
| AnnaBridge | 167:e84263d55307 | 7864 | #define DSI_TCCR2_LPRD_TOCNT12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7865 | #define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7866 | #define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk |
| AnnaBridge | 167:e84263d55307 | 7867 | #define DSI_TCCR2_LPRD_TOCNT13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7868 | #define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7869 | #define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk |
| AnnaBridge | 167:e84263d55307 | 7870 | #define DSI_TCCR2_LPRD_TOCNT14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 7871 | #define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 7872 | #define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk |
| AnnaBridge | 167:e84263d55307 | 7873 | #define DSI_TCCR2_LPRD_TOCNT15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 7874 | #define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 7875 | #define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk |
| mbed_official | 19:112740acecfa | 7876 | |
| mbed_official | 19:112740acecfa | 7877 | /******************* Bit definition for DSI_TCCR3 register **************/ |
| AnnaBridge | 167:e84263d55307 | 7878 | #define DSI_TCCR3_HSWR_TOCNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7879 | #define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFU << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 7880 | #define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */ |
| AnnaBridge | 167:e84263d55307 | 7881 | #define DSI_TCCR3_HSWR_TOCNT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7882 | #define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7883 | #define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk |
| AnnaBridge | 167:e84263d55307 | 7884 | #define DSI_TCCR3_HSWR_TOCNT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7885 | #define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7886 | #define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk |
| AnnaBridge | 167:e84263d55307 | 7887 | #define DSI_TCCR3_HSWR_TOCNT2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7888 | #define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7889 | #define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk |
| AnnaBridge | 167:e84263d55307 | 7890 | #define DSI_TCCR3_HSWR_TOCNT3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7891 | #define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7892 | #define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk |
| AnnaBridge | 167:e84263d55307 | 7893 | #define DSI_TCCR3_HSWR_TOCNT4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7894 | #define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7895 | #define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk |
| AnnaBridge | 167:e84263d55307 | 7896 | #define DSI_TCCR3_HSWR_TOCNT5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7897 | #define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7898 | #define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk |
| AnnaBridge | 167:e84263d55307 | 7899 | #define DSI_TCCR3_HSWR_TOCNT6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7900 | #define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7901 | #define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk |
| AnnaBridge | 167:e84263d55307 | 7902 | #define DSI_TCCR3_HSWR_TOCNT7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7903 | #define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7904 | #define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk |
| AnnaBridge | 167:e84263d55307 | 7905 | #define DSI_TCCR3_HSWR_TOCNT8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7906 | #define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7907 | #define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk |
| AnnaBridge | 167:e84263d55307 | 7908 | #define DSI_TCCR3_HSWR_TOCNT9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7909 | #define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7910 | #define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk |
| AnnaBridge | 167:e84263d55307 | 7911 | #define DSI_TCCR3_HSWR_TOCNT10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7912 | #define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7913 | #define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk |
| AnnaBridge | 167:e84263d55307 | 7914 | #define DSI_TCCR3_HSWR_TOCNT11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7915 | #define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7916 | #define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk |
| AnnaBridge | 167:e84263d55307 | 7917 | #define DSI_TCCR3_HSWR_TOCNT12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7918 | #define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7919 | #define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk |
| AnnaBridge | 167:e84263d55307 | 7920 | #define DSI_TCCR3_HSWR_TOCNT13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7921 | #define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7922 | #define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk |
| AnnaBridge | 167:e84263d55307 | 7923 | #define DSI_TCCR3_HSWR_TOCNT14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 7924 | #define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 7925 | #define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk |
| AnnaBridge | 167:e84263d55307 | 7926 | #define DSI_TCCR3_HSWR_TOCNT15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 7927 | #define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 7928 | #define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk |
| AnnaBridge | 167:e84263d55307 | 7929 | |
| AnnaBridge | 167:e84263d55307 | 7930 | #define DSI_TCCR3_PM_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 7931 | #define DSI_TCCR3_PM_Msk (0x1U << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 7932 | #define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */ |
| mbed_official | 19:112740acecfa | 7933 | |
| mbed_official | 19:112740acecfa | 7934 | /******************* Bit definition for DSI_TCCR4 register **************/ |
| AnnaBridge | 167:e84263d55307 | 7935 | #define DSI_TCCR4_LPWR_TOCNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7936 | #define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFU << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 7937 | #define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */ |
| AnnaBridge | 167:e84263d55307 | 7938 | #define DSI_TCCR4_LPWR_TOCNT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7939 | #define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7940 | #define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk |
| AnnaBridge | 167:e84263d55307 | 7941 | #define DSI_TCCR4_LPWR_TOCNT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7942 | #define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7943 | #define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk |
| AnnaBridge | 167:e84263d55307 | 7944 | #define DSI_TCCR4_LPWR_TOCNT2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7945 | #define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7946 | #define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk |
| AnnaBridge | 167:e84263d55307 | 7947 | #define DSI_TCCR4_LPWR_TOCNT3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 7948 | #define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 7949 | #define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk |
| AnnaBridge | 167:e84263d55307 | 7950 | #define DSI_TCCR4_LPWR_TOCNT4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 7951 | #define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 7952 | #define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk |
| AnnaBridge | 167:e84263d55307 | 7953 | #define DSI_TCCR4_LPWR_TOCNT5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 7954 | #define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 7955 | #define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk |
| AnnaBridge | 167:e84263d55307 | 7956 | #define DSI_TCCR4_LPWR_TOCNT6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 7957 | #define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 7958 | #define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk |
| AnnaBridge | 167:e84263d55307 | 7959 | #define DSI_TCCR4_LPWR_TOCNT7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 7960 | #define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 7961 | #define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk |
| AnnaBridge | 167:e84263d55307 | 7962 | #define DSI_TCCR4_LPWR_TOCNT8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 7963 | #define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 7964 | #define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk |
| AnnaBridge | 167:e84263d55307 | 7965 | #define DSI_TCCR4_LPWR_TOCNT9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 7966 | #define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 7967 | #define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk |
| AnnaBridge | 167:e84263d55307 | 7968 | #define DSI_TCCR4_LPWR_TOCNT10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 7969 | #define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 7970 | #define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk |
| AnnaBridge | 167:e84263d55307 | 7971 | #define DSI_TCCR4_LPWR_TOCNT11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 7972 | #define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 7973 | #define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk |
| AnnaBridge | 167:e84263d55307 | 7974 | #define DSI_TCCR4_LPWR_TOCNT12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 7975 | #define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 7976 | #define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk |
| AnnaBridge | 167:e84263d55307 | 7977 | #define DSI_TCCR4_LPWR_TOCNT13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 7978 | #define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 7979 | #define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk |
| AnnaBridge | 167:e84263d55307 | 7980 | #define DSI_TCCR4_LPWR_TOCNT14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 7981 | #define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 7982 | #define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk |
| AnnaBridge | 167:e84263d55307 | 7983 | #define DSI_TCCR4_LPWR_TOCNT15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 7984 | #define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 7985 | #define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk |
| mbed_official | 19:112740acecfa | 7986 | |
| mbed_official | 19:112740acecfa | 7987 | /******************* Bit definition for DSI_TCCR5 register **************/ |
| AnnaBridge | 167:e84263d55307 | 7988 | #define DSI_TCCR5_BTA_TOCNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7989 | #define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFU << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 7990 | #define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */ |
| AnnaBridge | 167:e84263d55307 | 7991 | #define DSI_TCCR5_BTA_TOCNT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 7992 | #define DSI_TCCR5_BTA_TOCNT0_Msk (0x1U << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 7993 | #define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk |
| AnnaBridge | 167:e84263d55307 | 7994 | #define DSI_TCCR5_BTA_TOCNT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 7995 | #define DSI_TCCR5_BTA_TOCNT1_Msk (0x1U << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 7996 | #define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk |
| AnnaBridge | 167:e84263d55307 | 7997 | #define DSI_TCCR5_BTA_TOCNT2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 7998 | #define DSI_TCCR5_BTA_TOCNT2_Msk (0x1U << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 7999 | #define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk |
| AnnaBridge | 167:e84263d55307 | 8000 | #define DSI_TCCR5_BTA_TOCNT3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8001 | #define DSI_TCCR5_BTA_TOCNT3_Msk (0x1U << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8002 | #define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk |
| AnnaBridge | 167:e84263d55307 | 8003 | #define DSI_TCCR5_BTA_TOCNT4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8004 | #define DSI_TCCR5_BTA_TOCNT4_Msk (0x1U << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8005 | #define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk |
| AnnaBridge | 167:e84263d55307 | 8006 | #define DSI_TCCR5_BTA_TOCNT5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8007 | #define DSI_TCCR5_BTA_TOCNT5_Msk (0x1U << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8008 | #define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk |
| AnnaBridge | 167:e84263d55307 | 8009 | #define DSI_TCCR5_BTA_TOCNT6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8010 | #define DSI_TCCR5_BTA_TOCNT6_Msk (0x1U << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8011 | #define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk |
| AnnaBridge | 167:e84263d55307 | 8012 | #define DSI_TCCR5_BTA_TOCNT7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8013 | #define DSI_TCCR5_BTA_TOCNT7_Msk (0x1U << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8014 | #define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk |
| AnnaBridge | 167:e84263d55307 | 8015 | #define DSI_TCCR5_BTA_TOCNT8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8016 | #define DSI_TCCR5_BTA_TOCNT8_Msk (0x1U << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8017 | #define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk |
| AnnaBridge | 167:e84263d55307 | 8018 | #define DSI_TCCR5_BTA_TOCNT9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8019 | #define DSI_TCCR5_BTA_TOCNT9_Msk (0x1U << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8020 | #define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk |
| AnnaBridge | 167:e84263d55307 | 8021 | #define DSI_TCCR5_BTA_TOCNT10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8022 | #define DSI_TCCR5_BTA_TOCNT10_Msk (0x1U << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8023 | #define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk |
| AnnaBridge | 167:e84263d55307 | 8024 | #define DSI_TCCR5_BTA_TOCNT11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8025 | #define DSI_TCCR5_BTA_TOCNT11_Msk (0x1U << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8026 | #define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk |
| AnnaBridge | 167:e84263d55307 | 8027 | #define DSI_TCCR5_BTA_TOCNT12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8028 | #define DSI_TCCR5_BTA_TOCNT12_Msk (0x1U << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8029 | #define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk |
| AnnaBridge | 167:e84263d55307 | 8030 | #define DSI_TCCR5_BTA_TOCNT13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 8031 | #define DSI_TCCR5_BTA_TOCNT13_Msk (0x1U << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 8032 | #define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk |
| AnnaBridge | 167:e84263d55307 | 8033 | #define DSI_TCCR5_BTA_TOCNT14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 8034 | #define DSI_TCCR5_BTA_TOCNT14_Msk (0x1U << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 8035 | #define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk |
| AnnaBridge | 167:e84263d55307 | 8036 | #define DSI_TCCR5_BTA_TOCNT15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 8037 | #define DSI_TCCR5_BTA_TOCNT15_Msk (0x1U << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 8038 | #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk |
| mbed_official | 19:112740acecfa | 8039 | |
| mbed_official | 19:112740acecfa | 8040 | /******************* Bit definition for DSI_TDCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 8041 | #define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */ |
| AnnaBridge | 167:e84263d55307 | 8042 | #define DSI_TDCR_3DM0 0x00000001U |
| AnnaBridge | 167:e84263d55307 | 8043 | #define DSI_TDCR_3DM1 0x00000002U |
| AnnaBridge | 167:e84263d55307 | 8044 | |
| AnnaBridge | 167:e84263d55307 | 8045 | #define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */ |
| AnnaBridge | 167:e84263d55307 | 8046 | #define DSI_TDCR_3DF0 0x00000004U |
| AnnaBridge | 167:e84263d55307 | 8047 | #define DSI_TDCR_3DF1 0x00000008U |
| AnnaBridge | 167:e84263d55307 | 8048 | |
| AnnaBridge | 167:e84263d55307 | 8049 | #define DSI_TDCR_SVS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8050 | #define DSI_TDCR_SVS_Msk (0x1U << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8051 | #define DSI_TDCR_SVS DSI_TDCR_SVS_Msk /*!< Second VSYNC */ |
| AnnaBridge | 167:e84263d55307 | 8052 | #define DSI_TDCR_RF_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8053 | #define DSI_TDCR_RF_Msk (0x1U << DSI_TDCR_RF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8054 | #define DSI_TDCR_RF DSI_TDCR_RF_Msk /*!< Right First */ |
| AnnaBridge | 167:e84263d55307 | 8055 | #define DSI_TDCR_S3DC_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 8056 | #define DSI_TDCR_S3DC_Msk (0x1U << DSI_TDCR_S3DC_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 8057 | #define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk /*!< Send 3D Control */ |
| mbed_official | 19:112740acecfa | 8058 | |
| mbed_official | 19:112740acecfa | 8059 | /******************* Bit definition for DSI_CLCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 8060 | #define DSI_CLCR_DPCC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8061 | #define DSI_CLCR_DPCC_Msk (0x1U << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8062 | #define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */ |
| AnnaBridge | 167:e84263d55307 | 8063 | #define DSI_CLCR_ACR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8064 | #define DSI_CLCR_ACR_Msk (0x1U << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8065 | #define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */ |
| mbed_official | 19:112740acecfa | 8066 | |
| mbed_official | 19:112740acecfa | 8067 | /******************* Bit definition for DSI_CLTCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 8068 | #define DSI_CLTCR_LP2HS_TIME_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8069 | #define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFU << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 167:e84263d55307 | 8070 | #define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */ |
| AnnaBridge | 167:e84263d55307 | 8071 | #define DSI_CLTCR_LP2HS_TIME0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8072 | #define DSI_CLTCR_LP2HS_TIME0_Msk (0x1U << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8073 | #define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk |
| AnnaBridge | 167:e84263d55307 | 8074 | #define DSI_CLTCR_LP2HS_TIME1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8075 | #define DSI_CLTCR_LP2HS_TIME1_Msk (0x1U << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8076 | #define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk |
| AnnaBridge | 167:e84263d55307 | 8077 | #define DSI_CLTCR_LP2HS_TIME2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8078 | #define DSI_CLTCR_LP2HS_TIME2_Msk (0x1U << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8079 | #define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk |
| AnnaBridge | 167:e84263d55307 | 8080 | #define DSI_CLTCR_LP2HS_TIME3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8081 | #define DSI_CLTCR_LP2HS_TIME3_Msk (0x1U << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8082 | #define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk |
| AnnaBridge | 167:e84263d55307 | 8083 | #define DSI_CLTCR_LP2HS_TIME4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8084 | #define DSI_CLTCR_LP2HS_TIME4_Msk (0x1U << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8085 | #define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk |
| AnnaBridge | 167:e84263d55307 | 8086 | #define DSI_CLTCR_LP2HS_TIME5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8087 | #define DSI_CLTCR_LP2HS_TIME5_Msk (0x1U << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8088 | #define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk |
| AnnaBridge | 167:e84263d55307 | 8089 | #define DSI_CLTCR_LP2HS_TIME6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8090 | #define DSI_CLTCR_LP2HS_TIME6_Msk (0x1U << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8091 | #define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk |
| AnnaBridge | 167:e84263d55307 | 8092 | #define DSI_CLTCR_LP2HS_TIME7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8093 | #define DSI_CLTCR_LP2HS_TIME7_Msk (0x1U << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8094 | #define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk |
| AnnaBridge | 167:e84263d55307 | 8095 | #define DSI_CLTCR_LP2HS_TIME8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8096 | #define DSI_CLTCR_LP2HS_TIME8_Msk (0x1U << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8097 | #define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk |
| AnnaBridge | 167:e84263d55307 | 8098 | #define DSI_CLTCR_LP2HS_TIME9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8099 | #define DSI_CLTCR_LP2HS_TIME9_Msk (0x1U << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8100 | #define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk |
| AnnaBridge | 167:e84263d55307 | 8101 | |
| AnnaBridge | 167:e84263d55307 | 8102 | #define DSI_CLTCR_HS2LP_TIME_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 8103 | #define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFU << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 8104 | #define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */ |
| AnnaBridge | 167:e84263d55307 | 8105 | #define DSI_CLTCR_HS2LP_TIME0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 8106 | #define DSI_CLTCR_HS2LP_TIME0_Msk (0x1U << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 8107 | #define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk |
| AnnaBridge | 167:e84263d55307 | 8108 | #define DSI_CLTCR_HS2LP_TIME1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 8109 | #define DSI_CLTCR_HS2LP_TIME1_Msk (0x1U << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 8110 | #define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk |
| AnnaBridge | 167:e84263d55307 | 8111 | #define DSI_CLTCR_HS2LP_TIME2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 8112 | #define DSI_CLTCR_HS2LP_TIME2_Msk (0x1U << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 8113 | #define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk |
| AnnaBridge | 167:e84263d55307 | 8114 | #define DSI_CLTCR_HS2LP_TIME3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 8115 | #define DSI_CLTCR_HS2LP_TIME3_Msk (0x1U << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 8116 | #define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk |
| AnnaBridge | 167:e84263d55307 | 8117 | #define DSI_CLTCR_HS2LP_TIME4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 8118 | #define DSI_CLTCR_HS2LP_TIME4_Msk (0x1U << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 8119 | #define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk |
| AnnaBridge | 167:e84263d55307 | 8120 | #define DSI_CLTCR_HS2LP_TIME5_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 8121 | #define DSI_CLTCR_HS2LP_TIME5_Msk (0x1U << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 8122 | #define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk |
| AnnaBridge | 167:e84263d55307 | 8123 | #define DSI_CLTCR_HS2LP_TIME6_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 8124 | #define DSI_CLTCR_HS2LP_TIME6_Msk (0x1U << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 8125 | #define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk |
| AnnaBridge | 167:e84263d55307 | 8126 | #define DSI_CLTCR_HS2LP_TIME7_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 8127 | #define DSI_CLTCR_HS2LP_TIME7_Msk (0x1U << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 8128 | #define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk |
| AnnaBridge | 167:e84263d55307 | 8129 | #define DSI_CLTCR_HS2LP_TIME8_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 8130 | #define DSI_CLTCR_HS2LP_TIME8_Msk (0x1U << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 8131 | #define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk |
| AnnaBridge | 167:e84263d55307 | 8132 | #define DSI_CLTCR_HS2LP_TIME9_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 8133 | #define DSI_CLTCR_HS2LP_TIME9_Msk (0x1U << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 8134 | #define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk |
| mbed_official | 19:112740acecfa | 8135 | |
| mbed_official | 19:112740acecfa | 8136 | /******************* Bit definition for DSI_DLTCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 8137 | #define DSI_DLTCR_MRD_TIME_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8138 | #define DSI_DLTCR_MRD_TIME_Msk (0x7FFFU << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 167:e84263d55307 | 8139 | #define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */ |
| AnnaBridge | 167:e84263d55307 | 8140 | #define DSI_DLTCR_MRD_TIME0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8141 | #define DSI_DLTCR_MRD_TIME0_Msk (0x1U << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8142 | #define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk |
| AnnaBridge | 167:e84263d55307 | 8143 | #define DSI_DLTCR_MRD_TIME1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8144 | #define DSI_DLTCR_MRD_TIME1_Msk (0x1U << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8145 | #define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk |
| AnnaBridge | 167:e84263d55307 | 8146 | #define DSI_DLTCR_MRD_TIME2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8147 | #define DSI_DLTCR_MRD_TIME2_Msk (0x1U << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8148 | #define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk |
| AnnaBridge | 167:e84263d55307 | 8149 | #define DSI_DLTCR_MRD_TIME3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8150 | #define DSI_DLTCR_MRD_TIME3_Msk (0x1U << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8151 | #define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk |
| AnnaBridge | 167:e84263d55307 | 8152 | #define DSI_DLTCR_MRD_TIME4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8153 | #define DSI_DLTCR_MRD_TIME4_Msk (0x1U << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8154 | #define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk |
| AnnaBridge | 167:e84263d55307 | 8155 | #define DSI_DLTCR_MRD_TIME5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8156 | #define DSI_DLTCR_MRD_TIME5_Msk (0x1U << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8157 | #define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk |
| AnnaBridge | 167:e84263d55307 | 8158 | #define DSI_DLTCR_MRD_TIME6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8159 | #define DSI_DLTCR_MRD_TIME6_Msk (0x1U << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8160 | #define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk |
| AnnaBridge | 167:e84263d55307 | 8161 | #define DSI_DLTCR_MRD_TIME7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8162 | #define DSI_DLTCR_MRD_TIME7_Msk (0x1U << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8163 | #define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk |
| AnnaBridge | 167:e84263d55307 | 8164 | #define DSI_DLTCR_MRD_TIME8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8165 | #define DSI_DLTCR_MRD_TIME8_Msk (0x1U << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8166 | #define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk |
| AnnaBridge | 167:e84263d55307 | 8167 | #define DSI_DLTCR_MRD_TIME9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8168 | #define DSI_DLTCR_MRD_TIME9_Msk (0x1U << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8169 | #define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk |
| AnnaBridge | 167:e84263d55307 | 8170 | #define DSI_DLTCR_MRD_TIME10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8171 | #define DSI_DLTCR_MRD_TIME10_Msk (0x1U << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8172 | #define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk |
| AnnaBridge | 167:e84263d55307 | 8173 | #define DSI_DLTCR_MRD_TIME11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8174 | #define DSI_DLTCR_MRD_TIME11_Msk (0x1U << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8175 | #define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk |
| AnnaBridge | 167:e84263d55307 | 8176 | #define DSI_DLTCR_MRD_TIME12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8177 | #define DSI_DLTCR_MRD_TIME12_Msk (0x1U << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8178 | #define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk |
| AnnaBridge | 167:e84263d55307 | 8179 | #define DSI_DLTCR_MRD_TIME13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 8180 | #define DSI_DLTCR_MRD_TIME13_Msk (0x1U << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 8181 | #define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk |
| AnnaBridge | 167:e84263d55307 | 8182 | #define DSI_DLTCR_MRD_TIME14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 8183 | #define DSI_DLTCR_MRD_TIME14_Msk (0x1U << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 8184 | #define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk |
| AnnaBridge | 167:e84263d55307 | 8185 | |
| AnnaBridge | 167:e84263d55307 | 8186 | #define DSI_DLTCR_LP2HS_TIME_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 8187 | #define DSI_DLTCR_LP2HS_TIME_Msk (0xFFU << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 8188 | #define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */ |
| AnnaBridge | 167:e84263d55307 | 8189 | #define DSI_DLTCR_LP2HS_TIME0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 8190 | #define DSI_DLTCR_LP2HS_TIME0_Msk (0x1U << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 8191 | #define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk |
| AnnaBridge | 167:e84263d55307 | 8192 | #define DSI_DLTCR_LP2HS_TIME1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 8193 | #define DSI_DLTCR_LP2HS_TIME1_Msk (0x1U << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 8194 | #define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk |
| AnnaBridge | 167:e84263d55307 | 8195 | #define DSI_DLTCR_LP2HS_TIME2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 8196 | #define DSI_DLTCR_LP2HS_TIME2_Msk (0x1U << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 8197 | #define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk |
| AnnaBridge | 167:e84263d55307 | 8198 | #define DSI_DLTCR_LP2HS_TIME3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 8199 | #define DSI_DLTCR_LP2HS_TIME3_Msk (0x1U << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 8200 | #define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk |
| AnnaBridge | 167:e84263d55307 | 8201 | #define DSI_DLTCR_LP2HS_TIME4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 8202 | #define DSI_DLTCR_LP2HS_TIME4_Msk (0x1U << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 8203 | #define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk |
| AnnaBridge | 167:e84263d55307 | 8204 | #define DSI_DLTCR_LP2HS_TIME5_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 8205 | #define DSI_DLTCR_LP2HS_TIME5_Msk (0x1U << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 8206 | #define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk |
| AnnaBridge | 167:e84263d55307 | 8207 | #define DSI_DLTCR_LP2HS_TIME6_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 8208 | #define DSI_DLTCR_LP2HS_TIME6_Msk (0x1U << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 8209 | #define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk |
| AnnaBridge | 167:e84263d55307 | 8210 | #define DSI_DLTCR_LP2HS_TIME7_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 8211 | #define DSI_DLTCR_LP2HS_TIME7_Msk (0x1U << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 8212 | #define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk |
| AnnaBridge | 167:e84263d55307 | 8213 | |
| AnnaBridge | 167:e84263d55307 | 8214 | #define DSI_DLTCR_HS2LP_TIME_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 8215 | #define DSI_DLTCR_HS2LP_TIME_Msk (0xFFU << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 8216 | #define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */ |
| AnnaBridge | 167:e84263d55307 | 8217 | #define DSI_DLTCR_HS2LP_TIME0_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 8218 | #define DSI_DLTCR_HS2LP_TIME0_Msk (0x1U << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 8219 | #define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk |
| AnnaBridge | 167:e84263d55307 | 8220 | #define DSI_DLTCR_HS2LP_TIME1_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 8221 | #define DSI_DLTCR_HS2LP_TIME1_Msk (0x1U << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 8222 | #define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk |
| AnnaBridge | 167:e84263d55307 | 8223 | #define DSI_DLTCR_HS2LP_TIME2_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 8224 | #define DSI_DLTCR_HS2LP_TIME2_Msk (0x1U << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 8225 | #define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk |
| AnnaBridge | 167:e84263d55307 | 8226 | #define DSI_DLTCR_HS2LP_TIME3_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 8227 | #define DSI_DLTCR_HS2LP_TIME3_Msk (0x1U << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 8228 | #define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk |
| AnnaBridge | 167:e84263d55307 | 8229 | #define DSI_DLTCR_HS2LP_TIME4_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 8230 | #define DSI_DLTCR_HS2LP_TIME4_Msk (0x1U << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 8231 | #define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk |
| AnnaBridge | 167:e84263d55307 | 8232 | #define DSI_DLTCR_HS2LP_TIME5_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 8233 | #define DSI_DLTCR_HS2LP_TIME5_Msk (0x1U << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 8234 | #define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk |
| AnnaBridge | 167:e84263d55307 | 8235 | #define DSI_DLTCR_HS2LP_TIME6_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 8236 | #define DSI_DLTCR_HS2LP_TIME6_Msk (0x1U << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 8237 | #define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk |
| AnnaBridge | 167:e84263d55307 | 8238 | #define DSI_DLTCR_HS2LP_TIME7_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 8239 | #define DSI_DLTCR_HS2LP_TIME7_Msk (0x1U << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 8240 | #define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk |
| mbed_official | 19:112740acecfa | 8241 | |
| mbed_official | 19:112740acecfa | 8242 | /******************* Bit definition for DSI_PCTLR register **************/ |
| AnnaBridge | 167:e84263d55307 | 8243 | #define DSI_PCTLR_DEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8244 | #define DSI_PCTLR_DEN_Msk (0x1U << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8245 | #define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */ |
| AnnaBridge | 167:e84263d55307 | 8246 | #define DSI_PCTLR_CKE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8247 | #define DSI_PCTLR_CKE_Msk (0x1U << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8248 | #define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */ |
| mbed_official | 19:112740acecfa | 8249 | |
| mbed_official | 19:112740acecfa | 8250 | /******************* Bit definition for DSI_PCONFR register *************/ |
| AnnaBridge | 167:e84263d55307 | 8251 | #define DSI_PCONFR_NL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8252 | #define DSI_PCONFR_NL_Msk (0x3U << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 8253 | #define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */ |
| AnnaBridge | 167:e84263d55307 | 8254 | #define DSI_PCONFR_NL0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8255 | #define DSI_PCONFR_NL0_Msk (0x1U << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8256 | #define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk |
| AnnaBridge | 167:e84263d55307 | 8257 | #define DSI_PCONFR_NL1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8258 | #define DSI_PCONFR_NL1_Msk (0x1U << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8259 | #define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk |
| AnnaBridge | 167:e84263d55307 | 8260 | |
| AnnaBridge | 167:e84263d55307 | 8261 | #define DSI_PCONFR_SW_TIME_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8262 | #define DSI_PCONFR_SW_TIME_Msk (0xFFU << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 8263 | #define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */ |
| AnnaBridge | 167:e84263d55307 | 8264 | #define DSI_PCONFR_SW_TIME0_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8265 | #define DSI_PCONFR_SW_TIME0_Msk (0x1U << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8266 | #define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk |
| AnnaBridge | 167:e84263d55307 | 8267 | #define DSI_PCONFR_SW_TIME1_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8268 | #define DSI_PCONFR_SW_TIME1_Msk (0x1U << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8269 | #define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk |
| AnnaBridge | 167:e84263d55307 | 8270 | #define DSI_PCONFR_SW_TIME2_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8271 | #define DSI_PCONFR_SW_TIME2_Msk (0x1U << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8272 | #define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk |
| AnnaBridge | 167:e84263d55307 | 8273 | #define DSI_PCONFR_SW_TIME3_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8274 | #define DSI_PCONFR_SW_TIME3_Msk (0x1U << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8275 | #define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk |
| AnnaBridge | 167:e84263d55307 | 8276 | #define DSI_PCONFR_SW_TIME4_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8277 | #define DSI_PCONFR_SW_TIME4_Msk (0x1U << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8278 | #define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk |
| AnnaBridge | 167:e84263d55307 | 8279 | #define DSI_PCONFR_SW_TIME5_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 8280 | #define DSI_PCONFR_SW_TIME5_Msk (0x1U << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 8281 | #define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk |
| AnnaBridge | 167:e84263d55307 | 8282 | #define DSI_PCONFR_SW_TIME6_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 8283 | #define DSI_PCONFR_SW_TIME6_Msk (0x1U << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 8284 | #define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk |
| AnnaBridge | 167:e84263d55307 | 8285 | #define DSI_PCONFR_SW_TIME7_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 8286 | #define DSI_PCONFR_SW_TIME7_Msk (0x1U << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 8287 | #define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk |
| mbed_official | 19:112740acecfa | 8288 | |
| mbed_official | 19:112740acecfa | 8289 | /******************* Bit definition for DSI_PUCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 8290 | #define DSI_PUCR_URCL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8291 | #define DSI_PUCR_URCL_Msk (0x1U << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8292 | #define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */ |
| AnnaBridge | 167:e84263d55307 | 8293 | #define DSI_PUCR_UECL_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8294 | #define DSI_PUCR_UECL_Msk (0x1U << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8295 | #define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */ |
| AnnaBridge | 167:e84263d55307 | 8296 | #define DSI_PUCR_URDL_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8297 | #define DSI_PUCR_URDL_Msk (0x1U << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8298 | #define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */ |
| AnnaBridge | 167:e84263d55307 | 8299 | #define DSI_PUCR_UEDL_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8300 | #define DSI_PUCR_UEDL_Msk (0x1U << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8301 | #define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */ |
| mbed_official | 19:112740acecfa | 8302 | |
| mbed_official | 19:112740acecfa | 8303 | /******************* Bit definition for DSI_PTTCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 8304 | #define DSI_PTTCR_TX_TRIG_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8305 | #define DSI_PTTCR_TX_TRIG_Msk (0xFU << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 8306 | #define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */ |
| AnnaBridge | 167:e84263d55307 | 8307 | #define DSI_PTTCR_TX_TRIG0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8308 | #define DSI_PTTCR_TX_TRIG0_Msk (0x1U << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8309 | #define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk |
| AnnaBridge | 167:e84263d55307 | 8310 | #define DSI_PTTCR_TX_TRIG1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8311 | #define DSI_PTTCR_TX_TRIG1_Msk (0x1U << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8312 | #define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk |
| AnnaBridge | 167:e84263d55307 | 8313 | #define DSI_PTTCR_TX_TRIG2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8314 | #define DSI_PTTCR_TX_TRIG2_Msk (0x1U << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8315 | #define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk |
| AnnaBridge | 167:e84263d55307 | 8316 | #define DSI_PTTCR_TX_TRIG3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8317 | #define DSI_PTTCR_TX_TRIG3_Msk (0x1U << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8318 | #define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk |
| mbed_official | 19:112740acecfa | 8319 | |
| mbed_official | 19:112740acecfa | 8320 | /******************* Bit definition for DSI_PSR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 8321 | #define DSI_PSR_PD_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8322 | #define DSI_PSR_PD_Msk (0x1U << DSI_PSR_PD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8323 | #define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */ |
| AnnaBridge | 167:e84263d55307 | 8324 | #define DSI_PSR_PSSC_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8325 | #define DSI_PSR_PSSC_Msk (0x1U << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8326 | #define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */ |
| AnnaBridge | 167:e84263d55307 | 8327 | #define DSI_PSR_UANC_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8328 | #define DSI_PSR_UANC_Msk (0x1U << DSI_PSR_UANC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8329 | #define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */ |
| AnnaBridge | 167:e84263d55307 | 8330 | #define DSI_PSR_PSS0_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8331 | #define DSI_PSR_PSS0_Msk (0x1U << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8332 | #define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */ |
| AnnaBridge | 167:e84263d55307 | 8333 | #define DSI_PSR_UAN0_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8334 | #define DSI_PSR_UAN0_Msk (0x1U << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8335 | #define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */ |
| AnnaBridge | 167:e84263d55307 | 8336 | #define DSI_PSR_RUE0_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8337 | #define DSI_PSR_RUE0_Msk (0x1U << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8338 | #define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */ |
| AnnaBridge | 167:e84263d55307 | 8339 | #define DSI_PSR_PSS1_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8340 | #define DSI_PSR_PSS1_Msk (0x1U << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8341 | #define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */ |
| AnnaBridge | 167:e84263d55307 | 8342 | #define DSI_PSR_UAN1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8343 | #define DSI_PSR_UAN1_Msk (0x1U << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8344 | #define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */ |
| mbed_official | 19:112740acecfa | 8345 | |
| mbed_official | 19:112740acecfa | 8346 | /******************* Bit definition for DSI_ISR0 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 8347 | #define DSI_ISR0_AE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8348 | #define DSI_ISR0_AE0_Msk (0x1U << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8349 | #define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */ |
| AnnaBridge | 167:e84263d55307 | 8350 | #define DSI_ISR0_AE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8351 | #define DSI_ISR0_AE1_Msk (0x1U << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8352 | #define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */ |
| AnnaBridge | 167:e84263d55307 | 8353 | #define DSI_ISR0_AE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8354 | #define DSI_ISR0_AE2_Msk (0x1U << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8355 | #define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */ |
| AnnaBridge | 167:e84263d55307 | 8356 | #define DSI_ISR0_AE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8357 | #define DSI_ISR0_AE3_Msk (0x1U << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8358 | #define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */ |
| AnnaBridge | 167:e84263d55307 | 8359 | #define DSI_ISR0_AE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8360 | #define DSI_ISR0_AE4_Msk (0x1U << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8361 | #define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */ |
| AnnaBridge | 167:e84263d55307 | 8362 | #define DSI_ISR0_AE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8363 | #define DSI_ISR0_AE5_Msk (0x1U << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8364 | #define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */ |
| AnnaBridge | 167:e84263d55307 | 8365 | #define DSI_ISR0_AE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8366 | #define DSI_ISR0_AE6_Msk (0x1U << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8367 | #define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */ |
| AnnaBridge | 167:e84263d55307 | 8368 | #define DSI_ISR0_AE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8369 | #define DSI_ISR0_AE7_Msk (0x1U << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8370 | #define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */ |
| AnnaBridge | 167:e84263d55307 | 8371 | #define DSI_ISR0_AE8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8372 | #define DSI_ISR0_AE8_Msk (0x1U << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8373 | #define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */ |
| AnnaBridge | 167:e84263d55307 | 8374 | #define DSI_ISR0_AE9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8375 | #define DSI_ISR0_AE9_Msk (0x1U << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8376 | #define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */ |
| AnnaBridge | 167:e84263d55307 | 8377 | #define DSI_ISR0_AE10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8378 | #define DSI_ISR0_AE10_Msk (0x1U << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8379 | #define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */ |
| AnnaBridge | 167:e84263d55307 | 8380 | #define DSI_ISR0_AE11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8381 | #define DSI_ISR0_AE11_Msk (0x1U << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8382 | #define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */ |
| AnnaBridge | 167:e84263d55307 | 8383 | #define DSI_ISR0_AE12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8384 | #define DSI_ISR0_AE12_Msk (0x1U << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8385 | #define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */ |
| AnnaBridge | 167:e84263d55307 | 8386 | #define DSI_ISR0_AE13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 8387 | #define DSI_ISR0_AE13_Msk (0x1U << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 8388 | #define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */ |
| AnnaBridge | 167:e84263d55307 | 8389 | #define DSI_ISR0_AE14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 8390 | #define DSI_ISR0_AE14_Msk (0x1U << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 8391 | #define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */ |
| AnnaBridge | 167:e84263d55307 | 8392 | #define DSI_ISR0_AE15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 8393 | #define DSI_ISR0_AE15_Msk (0x1U << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 8394 | #define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */ |
| AnnaBridge | 167:e84263d55307 | 8395 | #define DSI_ISR0_PE0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 8396 | #define DSI_ISR0_PE0_Msk (0x1U << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 8397 | #define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */ |
| AnnaBridge | 167:e84263d55307 | 8398 | #define DSI_ISR0_PE1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 8399 | #define DSI_ISR0_PE1_Msk (0x1U << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 8400 | #define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */ |
| AnnaBridge | 167:e84263d55307 | 8401 | #define DSI_ISR0_PE2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 8402 | #define DSI_ISR0_PE2_Msk (0x1U << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 8403 | #define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */ |
| AnnaBridge | 167:e84263d55307 | 8404 | #define DSI_ISR0_PE3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 8405 | #define DSI_ISR0_PE3_Msk (0x1U << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 8406 | #define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */ |
| AnnaBridge | 167:e84263d55307 | 8407 | #define DSI_ISR0_PE4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 8408 | #define DSI_ISR0_PE4_Msk (0x1U << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 8409 | #define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */ |
| mbed_official | 19:112740acecfa | 8410 | |
| mbed_official | 19:112740acecfa | 8411 | /******************* Bit definition for DSI_ISR1 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 8412 | #define DSI_ISR1_TOHSTX_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8413 | #define DSI_ISR1_TOHSTX_Msk (0x1U << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8414 | #define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */ |
| AnnaBridge | 167:e84263d55307 | 8415 | #define DSI_ISR1_TOLPRX_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8416 | #define DSI_ISR1_TOLPRX_Msk (0x1U << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8417 | #define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */ |
| AnnaBridge | 167:e84263d55307 | 8418 | #define DSI_ISR1_ECCSE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8419 | #define DSI_ISR1_ECCSE_Msk (0x1U << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8420 | #define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */ |
| AnnaBridge | 167:e84263d55307 | 8421 | #define DSI_ISR1_ECCME_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8422 | #define DSI_ISR1_ECCME_Msk (0x1U << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8423 | #define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */ |
| AnnaBridge | 167:e84263d55307 | 8424 | #define DSI_ISR1_CRCE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8425 | #define DSI_ISR1_CRCE_Msk (0x1U << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8426 | #define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */ |
| AnnaBridge | 167:e84263d55307 | 8427 | #define DSI_ISR1_PSE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8428 | #define DSI_ISR1_PSE_Msk (0x1U << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8429 | #define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */ |
| AnnaBridge | 167:e84263d55307 | 8430 | #define DSI_ISR1_EOTPE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8431 | #define DSI_ISR1_EOTPE_Msk (0x1U << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8432 | #define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */ |
| AnnaBridge | 167:e84263d55307 | 8433 | #define DSI_ISR1_LPWRE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8434 | #define DSI_ISR1_LPWRE_Msk (0x1U << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8435 | #define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */ |
| AnnaBridge | 167:e84263d55307 | 8436 | #define DSI_ISR1_GCWRE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8437 | #define DSI_ISR1_GCWRE_Msk (0x1U << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8438 | #define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */ |
| AnnaBridge | 167:e84263d55307 | 8439 | #define DSI_ISR1_GPWRE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8440 | #define DSI_ISR1_GPWRE_Msk (0x1U << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8441 | #define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */ |
| AnnaBridge | 167:e84263d55307 | 8442 | #define DSI_ISR1_GPTXE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8443 | #define DSI_ISR1_GPTXE_Msk (0x1U << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8444 | #define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */ |
| AnnaBridge | 167:e84263d55307 | 8445 | #define DSI_ISR1_GPRDE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8446 | #define DSI_ISR1_GPRDE_Msk (0x1U << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8447 | #define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */ |
| AnnaBridge | 167:e84263d55307 | 8448 | #define DSI_ISR1_GPRXE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8449 | #define DSI_ISR1_GPRXE_Msk (0x1U << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8450 | #define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */ |
| mbed_official | 19:112740acecfa | 8451 | |
| mbed_official | 19:112740acecfa | 8452 | /******************* Bit definition for DSI_IER0 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 8453 | #define DSI_IER0_AE0IE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8454 | #define DSI_IER0_AE0IE_Msk (0x1U << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8455 | #define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8456 | #define DSI_IER0_AE1IE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8457 | #define DSI_IER0_AE1IE_Msk (0x1U << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8458 | #define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8459 | #define DSI_IER0_AE2IE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8460 | #define DSI_IER0_AE2IE_Msk (0x1U << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8461 | #define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8462 | #define DSI_IER0_AE3IE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8463 | #define DSI_IER0_AE3IE_Msk (0x1U << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8464 | #define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8465 | #define DSI_IER0_AE4IE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8466 | #define DSI_IER0_AE4IE_Msk (0x1U << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8467 | #define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8468 | #define DSI_IER0_AE5IE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8469 | #define DSI_IER0_AE5IE_Msk (0x1U << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8470 | #define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8471 | #define DSI_IER0_AE6IE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8472 | #define DSI_IER0_AE6IE_Msk (0x1U << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8473 | #define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8474 | #define DSI_IER0_AE7IE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8475 | #define DSI_IER0_AE7IE_Msk (0x1U << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8476 | #define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8477 | #define DSI_IER0_AE8IE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8478 | #define DSI_IER0_AE8IE_Msk (0x1U << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8479 | #define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8480 | #define DSI_IER0_AE9IE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8481 | #define DSI_IER0_AE9IE_Msk (0x1U << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8482 | #define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8483 | #define DSI_IER0_AE10IE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8484 | #define DSI_IER0_AE10IE_Msk (0x1U << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8485 | #define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8486 | #define DSI_IER0_AE11IE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8487 | #define DSI_IER0_AE11IE_Msk (0x1U << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8488 | #define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8489 | #define DSI_IER0_AE12IE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8490 | #define DSI_IER0_AE12IE_Msk (0x1U << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8491 | #define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8492 | #define DSI_IER0_AE13IE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 8493 | #define DSI_IER0_AE13IE_Msk (0x1U << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 8494 | #define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8495 | #define DSI_IER0_AE14IE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 8496 | #define DSI_IER0_AE14IE_Msk (0x1U << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 8497 | #define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8498 | #define DSI_IER0_AE15IE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 8499 | #define DSI_IER0_AE15IE_Msk (0x1U << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 8500 | #define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8501 | #define DSI_IER0_PE0IE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 8502 | #define DSI_IER0_PE0IE_Msk (0x1U << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 8503 | #define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8504 | #define DSI_IER0_PE1IE_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 8505 | #define DSI_IER0_PE1IE_Msk (0x1U << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 8506 | #define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8507 | #define DSI_IER0_PE2IE_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 8508 | #define DSI_IER0_PE2IE_Msk (0x1U << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 8509 | #define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8510 | #define DSI_IER0_PE3IE_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 8511 | #define DSI_IER0_PE3IE_Msk (0x1U << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 8512 | #define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8513 | #define DSI_IER0_PE4IE_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 8514 | #define DSI_IER0_PE4IE_Msk (0x1U << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 8515 | #define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */ |
| mbed_official | 19:112740acecfa | 8516 | |
| mbed_official | 19:112740acecfa | 8517 | /******************* Bit definition for DSI_IER1 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 8518 | #define DSI_IER1_TOHSTXIE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8519 | #define DSI_IER1_TOHSTXIE_Msk (0x1U << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8520 | #define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8521 | #define DSI_IER1_TOLPRXIE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8522 | #define DSI_IER1_TOLPRXIE_Msk (0x1U << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8523 | #define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8524 | #define DSI_IER1_ECCSEIE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8525 | #define DSI_IER1_ECCSEIE_Msk (0x1U << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8526 | #define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8527 | #define DSI_IER1_ECCMEIE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8528 | #define DSI_IER1_ECCMEIE_Msk (0x1U << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8529 | #define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8530 | #define DSI_IER1_CRCEIE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8531 | #define DSI_IER1_CRCEIE_Msk (0x1U << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8532 | #define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8533 | #define DSI_IER1_PSEIE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8534 | #define DSI_IER1_PSEIE_Msk (0x1U << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8535 | #define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8536 | #define DSI_IER1_EOTPEIE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8537 | #define DSI_IER1_EOTPEIE_Msk (0x1U << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8538 | #define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8539 | #define DSI_IER1_LPWREIE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8540 | #define DSI_IER1_LPWREIE_Msk (0x1U << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8541 | #define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8542 | #define DSI_IER1_GCWREIE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8543 | #define DSI_IER1_GCWREIE_Msk (0x1U << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8544 | #define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8545 | #define DSI_IER1_GPWREIE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8546 | #define DSI_IER1_GPWREIE_Msk (0x1U << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8547 | #define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8548 | #define DSI_IER1_GPTXEIE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8549 | #define DSI_IER1_GPTXEIE_Msk (0x1U << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8550 | #define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8551 | #define DSI_IER1_GPRDEIE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8552 | #define DSI_IER1_GPRDEIE_Msk (0x1U << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8553 | #define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 8554 | #define DSI_IER1_GPRXEIE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8555 | #define DSI_IER1_GPRXEIE_Msk (0x1U << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8556 | #define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */ |
| mbed_official | 19:112740acecfa | 8557 | |
| mbed_official | 19:112740acecfa | 8558 | /******************* Bit definition for DSI_FIR0 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 8559 | #define DSI_FIR0_FAE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8560 | #define DSI_FIR0_FAE0_Msk (0x1U << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8561 | #define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */ |
| AnnaBridge | 167:e84263d55307 | 8562 | #define DSI_FIR0_FAE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8563 | #define DSI_FIR0_FAE1_Msk (0x1U << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8564 | #define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */ |
| AnnaBridge | 167:e84263d55307 | 8565 | #define DSI_FIR0_FAE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8566 | #define DSI_FIR0_FAE2_Msk (0x1U << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8567 | #define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */ |
| AnnaBridge | 167:e84263d55307 | 8568 | #define DSI_FIR0_FAE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8569 | #define DSI_FIR0_FAE3_Msk (0x1U << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8570 | #define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */ |
| AnnaBridge | 167:e84263d55307 | 8571 | #define DSI_FIR0_FAE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8572 | #define DSI_FIR0_FAE4_Msk (0x1U << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8573 | #define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */ |
| AnnaBridge | 167:e84263d55307 | 8574 | #define DSI_FIR0_FAE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8575 | #define DSI_FIR0_FAE5_Msk (0x1U << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8576 | #define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */ |
| AnnaBridge | 167:e84263d55307 | 8577 | #define DSI_FIR0_FAE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8578 | #define DSI_FIR0_FAE6_Msk (0x1U << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8579 | #define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */ |
| AnnaBridge | 167:e84263d55307 | 8580 | #define DSI_FIR0_FAE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8581 | #define DSI_FIR0_FAE7_Msk (0x1U << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8582 | #define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */ |
| AnnaBridge | 167:e84263d55307 | 8583 | #define DSI_FIR0_FAE8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8584 | #define DSI_FIR0_FAE8_Msk (0x1U << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8585 | #define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */ |
| AnnaBridge | 167:e84263d55307 | 8586 | #define DSI_FIR0_FAE9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8587 | #define DSI_FIR0_FAE9_Msk (0x1U << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8588 | #define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */ |
| AnnaBridge | 167:e84263d55307 | 8589 | #define DSI_FIR0_FAE10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8590 | #define DSI_FIR0_FAE10_Msk (0x1U << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8591 | #define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */ |
| AnnaBridge | 167:e84263d55307 | 8592 | #define DSI_FIR0_FAE11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8593 | #define DSI_FIR0_FAE11_Msk (0x1U << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8594 | #define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */ |
| AnnaBridge | 167:e84263d55307 | 8595 | #define DSI_FIR0_FAE12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8596 | #define DSI_FIR0_FAE12_Msk (0x1U << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8597 | #define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */ |
| AnnaBridge | 167:e84263d55307 | 8598 | #define DSI_FIR0_FAE13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 8599 | #define DSI_FIR0_FAE13_Msk (0x1U << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 8600 | #define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */ |
| AnnaBridge | 167:e84263d55307 | 8601 | #define DSI_FIR0_FAE14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 8602 | #define DSI_FIR0_FAE14_Msk (0x1U << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 8603 | #define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */ |
| AnnaBridge | 167:e84263d55307 | 8604 | #define DSI_FIR0_FAE15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 8605 | #define DSI_FIR0_FAE15_Msk (0x1U << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 8606 | #define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */ |
| AnnaBridge | 167:e84263d55307 | 8607 | #define DSI_FIR0_FPE0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 8608 | #define DSI_FIR0_FPE0_Msk (0x1U << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 8609 | #define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */ |
| AnnaBridge | 167:e84263d55307 | 8610 | #define DSI_FIR0_FPE1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 8611 | #define DSI_FIR0_FPE1_Msk (0x1U << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 8612 | #define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */ |
| AnnaBridge | 167:e84263d55307 | 8613 | #define DSI_FIR0_FPE2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 8614 | #define DSI_FIR0_FPE2_Msk (0x1U << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 8615 | #define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */ |
| AnnaBridge | 167:e84263d55307 | 8616 | #define DSI_FIR0_FPE3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 8617 | #define DSI_FIR0_FPE3_Msk (0x1U << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 8618 | #define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */ |
| AnnaBridge | 167:e84263d55307 | 8619 | #define DSI_FIR0_FPE4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 8620 | #define DSI_FIR0_FPE4_Msk (0x1U << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 8621 | #define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */ |
| mbed_official | 19:112740acecfa | 8622 | |
| mbed_official | 19:112740acecfa | 8623 | /******************* Bit definition for DSI_FIR1 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 8624 | #define DSI_FIR1_FTOHSTX_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8625 | #define DSI_FIR1_FTOHSTX_Msk (0x1U << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8626 | #define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */ |
| AnnaBridge | 167:e84263d55307 | 8627 | #define DSI_FIR1_FTOLPRX_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8628 | #define DSI_FIR1_FTOLPRX_Msk (0x1U << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8629 | #define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */ |
| AnnaBridge | 167:e84263d55307 | 8630 | #define DSI_FIR1_FECCSE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8631 | #define DSI_FIR1_FECCSE_Msk (0x1U << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8632 | #define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */ |
| AnnaBridge | 167:e84263d55307 | 8633 | #define DSI_FIR1_FECCME_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8634 | #define DSI_FIR1_FECCME_Msk (0x1U << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8635 | #define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */ |
| AnnaBridge | 167:e84263d55307 | 8636 | #define DSI_FIR1_FCRCE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8637 | #define DSI_FIR1_FCRCE_Msk (0x1U << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8638 | #define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */ |
| AnnaBridge | 167:e84263d55307 | 8639 | #define DSI_FIR1_FPSE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8640 | #define DSI_FIR1_FPSE_Msk (0x1U << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8641 | #define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */ |
| AnnaBridge | 167:e84263d55307 | 8642 | #define DSI_FIR1_FEOTPE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8643 | #define DSI_FIR1_FEOTPE_Msk (0x1U << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8644 | #define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */ |
| AnnaBridge | 167:e84263d55307 | 8645 | #define DSI_FIR1_FLPWRE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8646 | #define DSI_FIR1_FLPWRE_Msk (0x1U << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8647 | #define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */ |
| AnnaBridge | 167:e84263d55307 | 8648 | #define DSI_FIR1_FGCWRE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8649 | #define DSI_FIR1_FGCWRE_Msk (0x1U << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8650 | #define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */ |
| AnnaBridge | 167:e84263d55307 | 8651 | #define DSI_FIR1_FGPWRE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8652 | #define DSI_FIR1_FGPWRE_Msk (0x1U << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8653 | #define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */ |
| AnnaBridge | 167:e84263d55307 | 8654 | #define DSI_FIR1_FGPTXE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8655 | #define DSI_FIR1_FGPTXE_Msk (0x1U << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8656 | #define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */ |
| AnnaBridge | 167:e84263d55307 | 8657 | #define DSI_FIR1_FGPRDE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8658 | #define DSI_FIR1_FGPRDE_Msk (0x1U << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8659 | #define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */ |
| AnnaBridge | 167:e84263d55307 | 8660 | #define DSI_FIR1_FGPRXE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8661 | #define DSI_FIR1_FGPRXE_Msk (0x1U << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8662 | #define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */ |
| mbed_official | 19:112740acecfa | 8663 | |
| mbed_official | 19:112740acecfa | 8664 | /******************* Bit definition for DSI_VSCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 8665 | #define DSI_VSCR_EN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8666 | #define DSI_VSCR_EN_Msk (0x1U << DSI_VSCR_EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8667 | #define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */ |
| AnnaBridge | 167:e84263d55307 | 8668 | #define DSI_VSCR_UR_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8669 | #define DSI_VSCR_UR_Msk (0x1U << DSI_VSCR_UR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8670 | #define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */ |
| mbed_official | 19:112740acecfa | 8671 | |
| mbed_official | 19:112740acecfa | 8672 | /******************* Bit definition for DSI_LCVCIDR register ************/ |
| AnnaBridge | 167:e84263d55307 | 8673 | #define DSI_LCVCIDR_VCID_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8674 | #define DSI_LCVCIDR_VCID_Msk (0x3U << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 8675 | #define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */ |
| AnnaBridge | 167:e84263d55307 | 8676 | #define DSI_LCVCIDR_VCID0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8677 | #define DSI_LCVCIDR_VCID0_Msk (0x1U << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8678 | #define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk |
| AnnaBridge | 167:e84263d55307 | 8679 | #define DSI_LCVCIDR_VCID1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8680 | #define DSI_LCVCIDR_VCID1_Msk (0x1U << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8681 | #define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk |
| mbed_official | 19:112740acecfa | 8682 | |
| mbed_official | 19:112740acecfa | 8683 | /******************* Bit definition for DSI_LCCCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 8684 | #define DSI_LCCCR_COLC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8685 | #define DSI_LCCCR_COLC_Msk (0xFU << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 8686 | #define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */ |
| AnnaBridge | 167:e84263d55307 | 8687 | #define DSI_LCCCR_COLC0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8688 | #define DSI_LCCCR_COLC0_Msk (0x1U << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8689 | #define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk |
| AnnaBridge | 167:e84263d55307 | 8690 | #define DSI_LCCCR_COLC1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8691 | #define DSI_LCCCR_COLC1_Msk (0x1U << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8692 | #define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk |
| AnnaBridge | 167:e84263d55307 | 8693 | #define DSI_LCCCR_COLC2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8694 | #define DSI_LCCCR_COLC2_Msk (0x1U << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8695 | #define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk |
| AnnaBridge | 167:e84263d55307 | 8696 | #define DSI_LCCCR_COLC3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8697 | #define DSI_LCCCR_COLC3_Msk (0x1U << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8698 | #define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk |
| AnnaBridge | 167:e84263d55307 | 8699 | |
| AnnaBridge | 167:e84263d55307 | 8700 | #define DSI_LCCCR_LPE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8701 | #define DSI_LCCCR_LPE_Msk (0x1U << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8702 | #define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */ |
| mbed_official | 19:112740acecfa | 8703 | |
| mbed_official | 19:112740acecfa | 8704 | /******************* Bit definition for DSI_LPMCCR register *************/ |
| AnnaBridge | 167:e84263d55307 | 8705 | #define DSI_LPMCCR_VLPSIZE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8706 | #define DSI_LPMCCR_VLPSIZE_Msk (0xFFU << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 8707 | #define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */ |
| AnnaBridge | 167:e84263d55307 | 8708 | #define DSI_LPMCCR_VLPSIZE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8709 | #define DSI_LPMCCR_VLPSIZE0_Msk (0x1U << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8710 | #define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk |
| AnnaBridge | 167:e84263d55307 | 8711 | #define DSI_LPMCCR_VLPSIZE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8712 | #define DSI_LPMCCR_VLPSIZE1_Msk (0x1U << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8713 | #define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk |
| AnnaBridge | 167:e84263d55307 | 8714 | #define DSI_LPMCCR_VLPSIZE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8715 | #define DSI_LPMCCR_VLPSIZE2_Msk (0x1U << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8716 | #define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk |
| AnnaBridge | 167:e84263d55307 | 8717 | #define DSI_LPMCCR_VLPSIZE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8718 | #define DSI_LPMCCR_VLPSIZE3_Msk (0x1U << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8719 | #define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk |
| AnnaBridge | 167:e84263d55307 | 8720 | #define DSI_LPMCCR_VLPSIZE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8721 | #define DSI_LPMCCR_VLPSIZE4_Msk (0x1U << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8722 | #define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk |
| AnnaBridge | 167:e84263d55307 | 8723 | #define DSI_LPMCCR_VLPSIZE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8724 | #define DSI_LPMCCR_VLPSIZE5_Msk (0x1U << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8725 | #define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk |
| AnnaBridge | 167:e84263d55307 | 8726 | #define DSI_LPMCCR_VLPSIZE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8727 | #define DSI_LPMCCR_VLPSIZE6_Msk (0x1U << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8728 | #define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk |
| AnnaBridge | 167:e84263d55307 | 8729 | #define DSI_LPMCCR_VLPSIZE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8730 | #define DSI_LPMCCR_VLPSIZE7_Msk (0x1U << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8731 | #define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk |
| AnnaBridge | 167:e84263d55307 | 8732 | |
| AnnaBridge | 167:e84263d55307 | 8733 | #define DSI_LPMCCR_LPSIZE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 8734 | #define DSI_LPMCCR_LPSIZE_Msk (0xFFU << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 8735 | #define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */ |
| AnnaBridge | 167:e84263d55307 | 8736 | #define DSI_LPMCCR_LPSIZE0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 8737 | #define DSI_LPMCCR_LPSIZE0_Msk (0x1U << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 8738 | #define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk |
| AnnaBridge | 167:e84263d55307 | 8739 | #define DSI_LPMCCR_LPSIZE1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 8740 | #define DSI_LPMCCR_LPSIZE1_Msk (0x1U << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 8741 | #define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk |
| AnnaBridge | 167:e84263d55307 | 8742 | #define DSI_LPMCCR_LPSIZE2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 8743 | #define DSI_LPMCCR_LPSIZE2_Msk (0x1U << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 8744 | #define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk |
| AnnaBridge | 167:e84263d55307 | 8745 | #define DSI_LPMCCR_LPSIZE3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 8746 | #define DSI_LPMCCR_LPSIZE3_Msk (0x1U << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 8747 | #define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk |
| AnnaBridge | 167:e84263d55307 | 8748 | #define DSI_LPMCCR_LPSIZE4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 8749 | #define DSI_LPMCCR_LPSIZE4_Msk (0x1U << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 8750 | #define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk |
| AnnaBridge | 167:e84263d55307 | 8751 | #define DSI_LPMCCR_LPSIZE5_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 8752 | #define DSI_LPMCCR_LPSIZE5_Msk (0x1U << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 8753 | #define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk |
| AnnaBridge | 167:e84263d55307 | 8754 | #define DSI_LPMCCR_LPSIZE6_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 8755 | #define DSI_LPMCCR_LPSIZE6_Msk (0x1U << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 8756 | #define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk |
| AnnaBridge | 167:e84263d55307 | 8757 | #define DSI_LPMCCR_LPSIZE7_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 8758 | #define DSI_LPMCCR_LPSIZE7_Msk (0x1U << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 8759 | #define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk |
| mbed_official | 19:112740acecfa | 8760 | |
| mbed_official | 19:112740acecfa | 8761 | /******************* Bit definition for DSI_VMCCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 8762 | #define DSI_VMCCR_VMT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8763 | #define DSI_VMCCR_VMT_Msk (0x3U << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 8764 | #define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */ |
| AnnaBridge | 167:e84263d55307 | 8765 | #define DSI_VMCCR_VMT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8766 | #define DSI_VMCCR_VMT0_Msk (0x1U << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8767 | #define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk |
| AnnaBridge | 167:e84263d55307 | 8768 | #define DSI_VMCCR_VMT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8769 | #define DSI_VMCCR_VMT1_Msk (0x1U << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8770 | #define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk |
| AnnaBridge | 167:e84263d55307 | 8771 | |
| AnnaBridge | 167:e84263d55307 | 8772 | #define DSI_VMCCR_LPVSAE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8773 | #define DSI_VMCCR_LPVSAE_Msk (0x1U << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8774 | #define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */ |
| AnnaBridge | 167:e84263d55307 | 8775 | #define DSI_VMCCR_LPVBPE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8776 | #define DSI_VMCCR_LPVBPE_Msk (0x1U << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8777 | #define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */ |
| AnnaBridge | 167:e84263d55307 | 8778 | #define DSI_VMCCR_LPVFPE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8779 | #define DSI_VMCCR_LPVFPE_Msk (0x1U << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8780 | #define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */ |
| AnnaBridge | 167:e84263d55307 | 8781 | #define DSI_VMCCR_LPVAE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8782 | #define DSI_VMCCR_LPVAE_Msk (0x1U << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8783 | #define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */ |
| AnnaBridge | 167:e84263d55307 | 8784 | #define DSI_VMCCR_LPHBPE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8785 | #define DSI_VMCCR_LPHBPE_Msk (0x1U << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8786 | #define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */ |
| AnnaBridge | 167:e84263d55307 | 8787 | #define DSI_VMCCR_LPHFE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 8788 | #define DSI_VMCCR_LPHFE_Msk (0x1U << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 8789 | #define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */ |
| AnnaBridge | 167:e84263d55307 | 8790 | #define DSI_VMCCR_FBTAAE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 8791 | #define DSI_VMCCR_FBTAAE_Msk (0x1U << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 8792 | #define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */ |
| AnnaBridge | 167:e84263d55307 | 8793 | #define DSI_VMCCR_LPCE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 8794 | #define DSI_VMCCR_LPCE_Msk (0x1U << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 8795 | #define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */ |
| mbed_official | 19:112740acecfa | 8796 | |
| mbed_official | 19:112740acecfa | 8797 | /******************* Bit definition for DSI_VPCCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 8798 | #define DSI_VPCCR_VPSIZE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8799 | #define DSI_VPCCR_VPSIZE_Msk (0x3FFFU << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 167:e84263d55307 | 8800 | #define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */ |
| AnnaBridge | 167:e84263d55307 | 8801 | #define DSI_VPCCR_VPSIZE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8802 | #define DSI_VPCCR_VPSIZE0_Msk (0x1U << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8803 | #define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk |
| AnnaBridge | 167:e84263d55307 | 8804 | #define DSI_VPCCR_VPSIZE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8805 | #define DSI_VPCCR_VPSIZE1_Msk (0x1U << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8806 | #define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk |
| AnnaBridge | 167:e84263d55307 | 8807 | #define DSI_VPCCR_VPSIZE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8808 | #define DSI_VPCCR_VPSIZE2_Msk (0x1U << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8809 | #define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk |
| AnnaBridge | 167:e84263d55307 | 8810 | #define DSI_VPCCR_VPSIZE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8811 | #define DSI_VPCCR_VPSIZE3_Msk (0x1U << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8812 | #define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk |
| AnnaBridge | 167:e84263d55307 | 8813 | #define DSI_VPCCR_VPSIZE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8814 | #define DSI_VPCCR_VPSIZE4_Msk (0x1U << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8815 | #define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk |
| AnnaBridge | 167:e84263d55307 | 8816 | #define DSI_VPCCR_VPSIZE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8817 | #define DSI_VPCCR_VPSIZE5_Msk (0x1U << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8818 | #define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk |
| AnnaBridge | 167:e84263d55307 | 8819 | #define DSI_VPCCR_VPSIZE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8820 | #define DSI_VPCCR_VPSIZE6_Msk (0x1U << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8821 | #define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk |
| AnnaBridge | 167:e84263d55307 | 8822 | #define DSI_VPCCR_VPSIZE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8823 | #define DSI_VPCCR_VPSIZE7_Msk (0x1U << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8824 | #define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk |
| AnnaBridge | 167:e84263d55307 | 8825 | #define DSI_VPCCR_VPSIZE8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8826 | #define DSI_VPCCR_VPSIZE8_Msk (0x1U << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8827 | #define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk |
| AnnaBridge | 167:e84263d55307 | 8828 | #define DSI_VPCCR_VPSIZE9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8829 | #define DSI_VPCCR_VPSIZE9_Msk (0x1U << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8830 | #define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk |
| AnnaBridge | 167:e84263d55307 | 8831 | #define DSI_VPCCR_VPSIZE10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8832 | #define DSI_VPCCR_VPSIZE10_Msk (0x1U << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8833 | #define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk |
| AnnaBridge | 167:e84263d55307 | 8834 | #define DSI_VPCCR_VPSIZE11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8835 | #define DSI_VPCCR_VPSIZE11_Msk (0x1U << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8836 | #define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk |
| AnnaBridge | 167:e84263d55307 | 8837 | #define DSI_VPCCR_VPSIZE12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8838 | #define DSI_VPCCR_VPSIZE12_Msk (0x1U << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8839 | #define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk |
| AnnaBridge | 167:e84263d55307 | 8840 | #define DSI_VPCCR_VPSIZE13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 8841 | #define DSI_VPCCR_VPSIZE13_Msk (0x1U << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 8842 | #define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk |
| mbed_official | 19:112740acecfa | 8843 | |
| mbed_official | 19:112740acecfa | 8844 | /******************* Bit definition for DSI_VCCCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 8845 | #define DSI_VCCCR_NUMC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8846 | #define DSI_VCCCR_NUMC_Msk (0x1FFFU << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */ |
| AnnaBridge | 167:e84263d55307 | 8847 | #define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */ |
| AnnaBridge | 167:e84263d55307 | 8848 | #define DSI_VCCCR_NUMC0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8849 | #define DSI_VCCCR_NUMC0_Msk (0x1U << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8850 | #define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk |
| AnnaBridge | 167:e84263d55307 | 8851 | #define DSI_VCCCR_NUMC1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8852 | #define DSI_VCCCR_NUMC1_Msk (0x1U << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8853 | #define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk |
| AnnaBridge | 167:e84263d55307 | 8854 | #define DSI_VCCCR_NUMC2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8855 | #define DSI_VCCCR_NUMC2_Msk (0x1U << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8856 | #define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk |
| AnnaBridge | 167:e84263d55307 | 8857 | #define DSI_VCCCR_NUMC3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8858 | #define DSI_VCCCR_NUMC3_Msk (0x1U << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8859 | #define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk |
| AnnaBridge | 167:e84263d55307 | 8860 | #define DSI_VCCCR_NUMC4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8861 | #define DSI_VCCCR_NUMC4_Msk (0x1U << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8862 | #define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk |
| AnnaBridge | 167:e84263d55307 | 8863 | #define DSI_VCCCR_NUMC5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8864 | #define DSI_VCCCR_NUMC5_Msk (0x1U << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8865 | #define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk |
| AnnaBridge | 167:e84263d55307 | 8866 | #define DSI_VCCCR_NUMC6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8867 | #define DSI_VCCCR_NUMC6_Msk (0x1U << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8868 | #define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk |
| AnnaBridge | 167:e84263d55307 | 8869 | #define DSI_VCCCR_NUMC7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8870 | #define DSI_VCCCR_NUMC7_Msk (0x1U << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8871 | #define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk |
| AnnaBridge | 167:e84263d55307 | 8872 | #define DSI_VCCCR_NUMC8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8873 | #define DSI_VCCCR_NUMC8_Msk (0x1U << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8874 | #define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk |
| AnnaBridge | 167:e84263d55307 | 8875 | #define DSI_VCCCR_NUMC9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8876 | #define DSI_VCCCR_NUMC9_Msk (0x1U << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8877 | #define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk |
| AnnaBridge | 167:e84263d55307 | 8878 | #define DSI_VCCCR_NUMC10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8879 | #define DSI_VCCCR_NUMC10_Msk (0x1U << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8880 | #define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk |
| AnnaBridge | 167:e84263d55307 | 8881 | #define DSI_VCCCR_NUMC11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8882 | #define DSI_VCCCR_NUMC11_Msk (0x1U << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8883 | #define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk |
| AnnaBridge | 167:e84263d55307 | 8884 | #define DSI_VCCCR_NUMC12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8885 | #define DSI_VCCCR_NUMC12_Msk (0x1U << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8886 | #define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk |
| mbed_official | 19:112740acecfa | 8887 | |
| mbed_official | 19:112740acecfa | 8888 | /******************* Bit definition for DSI_VNPCCR register *************/ |
| AnnaBridge | 167:e84263d55307 | 8889 | #define DSI_VNPCCR_NPSIZE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8890 | #define DSI_VNPCCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */ |
| AnnaBridge | 167:e84263d55307 | 8891 | #define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */ |
| AnnaBridge | 167:e84263d55307 | 8892 | #define DSI_VNPCCR_NPSIZE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8893 | #define DSI_VNPCCR_NPSIZE0_Msk (0x1U << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8894 | #define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk |
| AnnaBridge | 167:e84263d55307 | 8895 | #define DSI_VNPCCR_NPSIZE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8896 | #define DSI_VNPCCR_NPSIZE1_Msk (0x1U << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8897 | #define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk |
| AnnaBridge | 167:e84263d55307 | 8898 | #define DSI_VNPCCR_NPSIZE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8899 | #define DSI_VNPCCR_NPSIZE2_Msk (0x1U << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8900 | #define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk |
| AnnaBridge | 167:e84263d55307 | 8901 | #define DSI_VNPCCR_NPSIZE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8902 | #define DSI_VNPCCR_NPSIZE3_Msk (0x1U << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8903 | #define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk |
| AnnaBridge | 167:e84263d55307 | 8904 | #define DSI_VNPCCR_NPSIZE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8905 | #define DSI_VNPCCR_NPSIZE4_Msk (0x1U << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8906 | #define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk |
| AnnaBridge | 167:e84263d55307 | 8907 | #define DSI_VNPCCR_NPSIZE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8908 | #define DSI_VNPCCR_NPSIZE5_Msk (0x1U << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8909 | #define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk |
| AnnaBridge | 167:e84263d55307 | 8910 | #define DSI_VNPCCR_NPSIZE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8911 | #define DSI_VNPCCR_NPSIZE6_Msk (0x1U << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8912 | #define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk |
| AnnaBridge | 167:e84263d55307 | 8913 | #define DSI_VNPCCR_NPSIZE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8914 | #define DSI_VNPCCR_NPSIZE7_Msk (0x1U << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8915 | #define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk |
| AnnaBridge | 167:e84263d55307 | 8916 | #define DSI_VNPCCR_NPSIZE8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8917 | #define DSI_VNPCCR_NPSIZE8_Msk (0x1U << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8918 | #define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk |
| AnnaBridge | 167:e84263d55307 | 8919 | #define DSI_VNPCCR_NPSIZE9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8920 | #define DSI_VNPCCR_NPSIZE9_Msk (0x1U << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8921 | #define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk |
| AnnaBridge | 167:e84263d55307 | 8922 | #define DSI_VNPCCR_NPSIZE10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8923 | #define DSI_VNPCCR_NPSIZE10_Msk (0x1U << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8924 | #define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk |
| AnnaBridge | 167:e84263d55307 | 8925 | #define DSI_VNPCCR_NPSIZE11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8926 | #define DSI_VNPCCR_NPSIZE11_Msk (0x1U << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8927 | #define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk |
| AnnaBridge | 167:e84263d55307 | 8928 | #define DSI_VNPCCR_NPSIZE12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 8929 | #define DSI_VNPCCR_NPSIZE12_Msk (0x1U << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 8930 | #define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk |
| mbed_official | 19:112740acecfa | 8931 | |
| mbed_official | 19:112740acecfa | 8932 | /******************* Bit definition for DSI_VHSACCR register ************/ |
| AnnaBridge | 167:e84263d55307 | 8933 | #define DSI_VHSACCR_HSA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8934 | #define DSI_VHSACCR_HSA_Msk (0xFFFU << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 8935 | #define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */ |
| AnnaBridge | 167:e84263d55307 | 8936 | #define DSI_VHSACCR_HSA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8937 | #define DSI_VHSACCR_HSA0_Msk (0x1U << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8938 | #define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk |
| AnnaBridge | 167:e84263d55307 | 8939 | #define DSI_VHSACCR_HSA1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8940 | #define DSI_VHSACCR_HSA1_Msk (0x1U << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8941 | #define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk |
| AnnaBridge | 167:e84263d55307 | 8942 | #define DSI_VHSACCR_HSA2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8943 | #define DSI_VHSACCR_HSA2_Msk (0x1U << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8944 | #define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk |
| AnnaBridge | 167:e84263d55307 | 8945 | #define DSI_VHSACCR_HSA3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8946 | #define DSI_VHSACCR_HSA3_Msk (0x1U << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8947 | #define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk |
| AnnaBridge | 167:e84263d55307 | 8948 | #define DSI_VHSACCR_HSA4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8949 | #define DSI_VHSACCR_HSA4_Msk (0x1U << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8950 | #define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk |
| AnnaBridge | 167:e84263d55307 | 8951 | #define DSI_VHSACCR_HSA5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8952 | #define DSI_VHSACCR_HSA5_Msk (0x1U << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8953 | #define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk |
| AnnaBridge | 167:e84263d55307 | 8954 | #define DSI_VHSACCR_HSA6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8955 | #define DSI_VHSACCR_HSA6_Msk (0x1U << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8956 | #define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk |
| AnnaBridge | 167:e84263d55307 | 8957 | #define DSI_VHSACCR_HSA7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8958 | #define DSI_VHSACCR_HSA7_Msk (0x1U << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 8959 | #define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk |
| AnnaBridge | 167:e84263d55307 | 8960 | #define DSI_VHSACCR_HSA8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 8961 | #define DSI_VHSACCR_HSA8_Msk (0x1U << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 8962 | #define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk |
| AnnaBridge | 167:e84263d55307 | 8963 | #define DSI_VHSACCR_HSA9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 8964 | #define DSI_VHSACCR_HSA9_Msk (0x1U << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 8965 | #define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk |
| AnnaBridge | 167:e84263d55307 | 8966 | #define DSI_VHSACCR_HSA10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 8967 | #define DSI_VHSACCR_HSA10_Msk (0x1U << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 8968 | #define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk |
| AnnaBridge | 167:e84263d55307 | 8969 | #define DSI_VHSACCR_HSA11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 8970 | #define DSI_VHSACCR_HSA11_Msk (0x1U << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 8971 | #define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk |
| mbed_official | 19:112740acecfa | 8972 | |
| mbed_official | 19:112740acecfa | 8973 | /******************* Bit definition for DSI_VHBPCCR register ************/ |
| AnnaBridge | 167:e84263d55307 | 8974 | #define DSI_VHBPCCR_HBP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8975 | #define DSI_VHBPCCR_HBP_Msk (0xFFFU << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 8976 | #define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */ |
| AnnaBridge | 167:e84263d55307 | 8977 | #define DSI_VHBPCCR_HBP0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 8978 | #define DSI_VHBPCCR_HBP0_Msk (0x1U << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 8979 | #define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk |
| AnnaBridge | 167:e84263d55307 | 8980 | #define DSI_VHBPCCR_HBP1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 8981 | #define DSI_VHBPCCR_HBP1_Msk (0x1U << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 8982 | #define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk |
| AnnaBridge | 167:e84263d55307 | 8983 | #define DSI_VHBPCCR_HBP2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 8984 | #define DSI_VHBPCCR_HBP2_Msk (0x1U << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 8985 | #define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk |
| AnnaBridge | 167:e84263d55307 | 8986 | #define DSI_VHBPCCR_HBP3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 8987 | #define DSI_VHBPCCR_HBP3_Msk (0x1U << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 8988 | #define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk |
| AnnaBridge | 167:e84263d55307 | 8989 | #define DSI_VHBPCCR_HBP4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 8990 | #define DSI_VHBPCCR_HBP4_Msk (0x1U << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 8991 | #define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk |
| AnnaBridge | 167:e84263d55307 | 8992 | #define DSI_VHBPCCR_HBP5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 8993 | #define DSI_VHBPCCR_HBP5_Msk (0x1U << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 8994 | #define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk |
| AnnaBridge | 167:e84263d55307 | 8995 | #define DSI_VHBPCCR_HBP6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 8996 | #define DSI_VHBPCCR_HBP6_Msk (0x1U << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 8997 | #define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk |
| AnnaBridge | 167:e84263d55307 | 8998 | #define DSI_VHBPCCR_HBP7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 8999 | #define DSI_VHBPCCR_HBP7_Msk (0x1U << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9000 | #define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk |
| AnnaBridge | 167:e84263d55307 | 9001 | #define DSI_VHBPCCR_HBP8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9002 | #define DSI_VHBPCCR_HBP8_Msk (0x1U << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9003 | #define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk |
| AnnaBridge | 167:e84263d55307 | 9004 | #define DSI_VHBPCCR_HBP9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9005 | #define DSI_VHBPCCR_HBP9_Msk (0x1U << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9006 | #define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk |
| AnnaBridge | 167:e84263d55307 | 9007 | #define DSI_VHBPCCR_HBP10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9008 | #define DSI_VHBPCCR_HBP10_Msk (0x1U << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9009 | #define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk |
| AnnaBridge | 167:e84263d55307 | 9010 | #define DSI_VHBPCCR_HBP11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 9011 | #define DSI_VHBPCCR_HBP11_Msk (0x1U << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 9012 | #define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk |
| mbed_official | 19:112740acecfa | 9013 | |
| mbed_official | 19:112740acecfa | 9014 | /******************* Bit definition for DSI_VLCCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 9015 | #define DSI_VLCCR_HLINE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9016 | #define DSI_VLCCR_HLINE_Msk (0x7FFFU << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 167:e84263d55307 | 9017 | #define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */ |
| AnnaBridge | 167:e84263d55307 | 9018 | #define DSI_VLCCR_HLINE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9019 | #define DSI_VLCCR_HLINE0_Msk (0x1U << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9020 | #define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk |
| AnnaBridge | 167:e84263d55307 | 9021 | #define DSI_VLCCR_HLINE1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9022 | #define DSI_VLCCR_HLINE1_Msk (0x1U << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9023 | #define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk |
| AnnaBridge | 167:e84263d55307 | 9024 | #define DSI_VLCCR_HLINE2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9025 | #define DSI_VLCCR_HLINE2_Msk (0x1U << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9026 | #define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk |
| AnnaBridge | 167:e84263d55307 | 9027 | #define DSI_VLCCR_HLINE3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9028 | #define DSI_VLCCR_HLINE3_Msk (0x1U << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9029 | #define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk |
| AnnaBridge | 167:e84263d55307 | 9030 | #define DSI_VLCCR_HLINE4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9031 | #define DSI_VLCCR_HLINE4_Msk (0x1U << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9032 | #define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk |
| AnnaBridge | 167:e84263d55307 | 9033 | #define DSI_VLCCR_HLINE5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9034 | #define DSI_VLCCR_HLINE5_Msk (0x1U << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9035 | #define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk |
| AnnaBridge | 167:e84263d55307 | 9036 | #define DSI_VLCCR_HLINE6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9037 | #define DSI_VLCCR_HLINE6_Msk (0x1U << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9038 | #define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk |
| AnnaBridge | 167:e84263d55307 | 9039 | #define DSI_VLCCR_HLINE7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9040 | #define DSI_VLCCR_HLINE7_Msk (0x1U << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9041 | #define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk |
| AnnaBridge | 167:e84263d55307 | 9042 | #define DSI_VLCCR_HLINE8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9043 | #define DSI_VLCCR_HLINE8_Msk (0x1U << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9044 | #define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk |
| AnnaBridge | 167:e84263d55307 | 9045 | #define DSI_VLCCR_HLINE9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9046 | #define DSI_VLCCR_HLINE9_Msk (0x1U << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9047 | #define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk |
| AnnaBridge | 167:e84263d55307 | 9048 | #define DSI_VLCCR_HLINE10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9049 | #define DSI_VLCCR_HLINE10_Msk (0x1U << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9050 | #define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk |
| AnnaBridge | 167:e84263d55307 | 9051 | #define DSI_VLCCR_HLINE11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 9052 | #define DSI_VLCCR_HLINE11_Msk (0x1U << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 9053 | #define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk |
| AnnaBridge | 167:e84263d55307 | 9054 | #define DSI_VLCCR_HLINE12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 9055 | #define DSI_VLCCR_HLINE12_Msk (0x1U << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 9056 | #define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk |
| AnnaBridge | 167:e84263d55307 | 9057 | #define DSI_VLCCR_HLINE13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9058 | #define DSI_VLCCR_HLINE13_Msk (0x1U << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9059 | #define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk |
| AnnaBridge | 167:e84263d55307 | 9060 | #define DSI_VLCCR_HLINE14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 9061 | #define DSI_VLCCR_HLINE14_Msk (0x1U << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 9062 | #define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk |
| mbed_official | 19:112740acecfa | 9063 | |
| mbed_official | 19:112740acecfa | 9064 | /******************* Bit definition for DSI_VVSACCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 9065 | #define DSI_VVSACCR_VSA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9066 | #define DSI_VVSACCR_VSA_Msk (0x3FFU << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 167:e84263d55307 | 9067 | #define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */ |
| AnnaBridge | 167:e84263d55307 | 9068 | #define DSI_VVSACCR_VSA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9069 | #define DSI_VVSACCR_VSA0_Msk (0x1U << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9070 | #define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk |
| AnnaBridge | 167:e84263d55307 | 9071 | #define DSI_VVSACCR_VSA1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9072 | #define DSI_VVSACCR_VSA1_Msk (0x1U << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9073 | #define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk |
| AnnaBridge | 167:e84263d55307 | 9074 | #define DSI_VVSACCR_VSA2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9075 | #define DSI_VVSACCR_VSA2_Msk (0x1U << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9076 | #define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk |
| AnnaBridge | 167:e84263d55307 | 9077 | #define DSI_VVSACCR_VSA3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9078 | #define DSI_VVSACCR_VSA3_Msk (0x1U << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9079 | #define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk |
| AnnaBridge | 167:e84263d55307 | 9080 | #define DSI_VVSACCR_VSA4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9081 | #define DSI_VVSACCR_VSA4_Msk (0x1U << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9082 | #define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk |
| AnnaBridge | 167:e84263d55307 | 9083 | #define DSI_VVSACCR_VSA5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9084 | #define DSI_VVSACCR_VSA5_Msk (0x1U << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9085 | #define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk |
| AnnaBridge | 167:e84263d55307 | 9086 | #define DSI_VVSACCR_VSA6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9087 | #define DSI_VVSACCR_VSA6_Msk (0x1U << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9088 | #define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk |
| AnnaBridge | 167:e84263d55307 | 9089 | #define DSI_VVSACCR_VSA7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9090 | #define DSI_VVSACCR_VSA7_Msk (0x1U << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9091 | #define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk |
| AnnaBridge | 167:e84263d55307 | 9092 | #define DSI_VVSACCR_VSA8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9093 | #define DSI_VVSACCR_VSA8_Msk (0x1U << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9094 | #define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk |
| AnnaBridge | 167:e84263d55307 | 9095 | #define DSI_VVSACCR_VSA9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9096 | #define DSI_VVSACCR_VSA9_Msk (0x1U << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9097 | #define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk |
| mbed_official | 19:112740acecfa | 9098 | |
| mbed_official | 19:112740acecfa | 9099 | /******************* Bit definition for DSI_VVBPCCR register ************/ |
| AnnaBridge | 167:e84263d55307 | 9100 | #define DSI_VVBPCCR_VBP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9101 | #define DSI_VVBPCCR_VBP_Msk (0x3FFU << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 167:e84263d55307 | 9102 | #define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */ |
| AnnaBridge | 167:e84263d55307 | 9103 | #define DSI_VVBPCCR_VBP0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9104 | #define DSI_VVBPCCR_VBP0_Msk (0x1U << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9105 | #define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk |
| AnnaBridge | 167:e84263d55307 | 9106 | #define DSI_VVBPCCR_VBP1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9107 | #define DSI_VVBPCCR_VBP1_Msk (0x1U << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9108 | #define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk |
| AnnaBridge | 167:e84263d55307 | 9109 | #define DSI_VVBPCCR_VBP2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9110 | #define DSI_VVBPCCR_VBP2_Msk (0x1U << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9111 | #define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk |
| AnnaBridge | 167:e84263d55307 | 9112 | #define DSI_VVBPCCR_VBP3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9113 | #define DSI_VVBPCCR_VBP3_Msk (0x1U << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9114 | #define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk |
| AnnaBridge | 167:e84263d55307 | 9115 | #define DSI_VVBPCCR_VBP4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9116 | #define DSI_VVBPCCR_VBP4_Msk (0x1U << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9117 | #define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk |
| AnnaBridge | 167:e84263d55307 | 9118 | #define DSI_VVBPCCR_VBP5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9119 | #define DSI_VVBPCCR_VBP5_Msk (0x1U << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9120 | #define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk |
| AnnaBridge | 167:e84263d55307 | 9121 | #define DSI_VVBPCCR_VBP6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9122 | #define DSI_VVBPCCR_VBP6_Msk (0x1U << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9123 | #define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk |
| AnnaBridge | 167:e84263d55307 | 9124 | #define DSI_VVBPCCR_VBP7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9125 | #define DSI_VVBPCCR_VBP7_Msk (0x1U << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9126 | #define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk |
| AnnaBridge | 167:e84263d55307 | 9127 | #define DSI_VVBPCCR_VBP8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9128 | #define DSI_VVBPCCR_VBP8_Msk (0x1U << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9129 | #define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk |
| AnnaBridge | 167:e84263d55307 | 9130 | #define DSI_VVBPCCR_VBP9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9131 | #define DSI_VVBPCCR_VBP9_Msk (0x1U << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9132 | #define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk |
| mbed_official | 19:112740acecfa | 9133 | |
| mbed_official | 19:112740acecfa | 9134 | /******************* Bit definition for DSI_VVFPCCR register ************/ |
| AnnaBridge | 167:e84263d55307 | 9135 | #define DSI_VVFPCCR_VFP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9136 | #define DSI_VVFPCCR_VFP_Msk (0x3FFU << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 167:e84263d55307 | 9137 | #define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */ |
| AnnaBridge | 167:e84263d55307 | 9138 | #define DSI_VVFPCCR_VFP0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9139 | #define DSI_VVFPCCR_VFP0_Msk (0x1U << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9140 | #define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk |
| AnnaBridge | 167:e84263d55307 | 9141 | #define DSI_VVFPCCR_VFP1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9142 | #define DSI_VVFPCCR_VFP1_Msk (0x1U << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9143 | #define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk |
| AnnaBridge | 167:e84263d55307 | 9144 | #define DSI_VVFPCCR_VFP2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9145 | #define DSI_VVFPCCR_VFP2_Msk (0x1U << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9146 | #define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk |
| AnnaBridge | 167:e84263d55307 | 9147 | #define DSI_VVFPCCR_VFP3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9148 | #define DSI_VVFPCCR_VFP3_Msk (0x1U << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9149 | #define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk |
| AnnaBridge | 167:e84263d55307 | 9150 | #define DSI_VVFPCCR_VFP4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9151 | #define DSI_VVFPCCR_VFP4_Msk (0x1U << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9152 | #define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk |
| AnnaBridge | 167:e84263d55307 | 9153 | #define DSI_VVFPCCR_VFP5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9154 | #define DSI_VVFPCCR_VFP5_Msk (0x1U << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9155 | #define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk |
| AnnaBridge | 167:e84263d55307 | 9156 | #define DSI_VVFPCCR_VFP6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9157 | #define DSI_VVFPCCR_VFP6_Msk (0x1U << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9158 | #define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk |
| AnnaBridge | 167:e84263d55307 | 9159 | #define DSI_VVFPCCR_VFP7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9160 | #define DSI_VVFPCCR_VFP7_Msk (0x1U << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9161 | #define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk |
| AnnaBridge | 167:e84263d55307 | 9162 | #define DSI_VVFPCCR_VFP8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9163 | #define DSI_VVFPCCR_VFP8_Msk (0x1U << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9164 | #define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk |
| AnnaBridge | 167:e84263d55307 | 9165 | #define DSI_VVFPCCR_VFP9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9166 | #define DSI_VVFPCCR_VFP9_Msk (0x1U << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9167 | #define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk |
| mbed_official | 19:112740acecfa | 9168 | |
| mbed_official | 19:112740acecfa | 9169 | /******************* Bit definition for DSI_VVACCR register *************/ |
| AnnaBridge | 167:e84263d55307 | 9170 | #define DSI_VVACCR_VA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9171 | #define DSI_VVACCR_VA_Msk (0x3FFFU << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 167:e84263d55307 | 9172 | #define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */ |
| AnnaBridge | 167:e84263d55307 | 9173 | #define DSI_VVACCR_VA0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9174 | #define DSI_VVACCR_VA0_Msk (0x1U << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9175 | #define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk |
| AnnaBridge | 167:e84263d55307 | 9176 | #define DSI_VVACCR_VA1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9177 | #define DSI_VVACCR_VA1_Msk (0x1U << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9178 | #define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk |
| AnnaBridge | 167:e84263d55307 | 9179 | #define DSI_VVACCR_VA2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9180 | #define DSI_VVACCR_VA2_Msk (0x1U << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9181 | #define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk |
| AnnaBridge | 167:e84263d55307 | 9182 | #define DSI_VVACCR_VA3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9183 | #define DSI_VVACCR_VA3_Msk (0x1U << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9184 | #define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk |
| AnnaBridge | 167:e84263d55307 | 9185 | #define DSI_VVACCR_VA4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9186 | #define DSI_VVACCR_VA4_Msk (0x1U << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9187 | #define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk |
| AnnaBridge | 167:e84263d55307 | 9188 | #define DSI_VVACCR_VA5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9189 | #define DSI_VVACCR_VA5_Msk (0x1U << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9190 | #define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk |
| AnnaBridge | 167:e84263d55307 | 9191 | #define DSI_VVACCR_VA6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9192 | #define DSI_VVACCR_VA6_Msk (0x1U << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9193 | #define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk |
| AnnaBridge | 167:e84263d55307 | 9194 | #define DSI_VVACCR_VA7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9195 | #define DSI_VVACCR_VA7_Msk (0x1U << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9196 | #define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk |
| AnnaBridge | 167:e84263d55307 | 9197 | #define DSI_VVACCR_VA8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9198 | #define DSI_VVACCR_VA8_Msk (0x1U << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9199 | #define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk |
| AnnaBridge | 167:e84263d55307 | 9200 | #define DSI_VVACCR_VA9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9201 | #define DSI_VVACCR_VA9_Msk (0x1U << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9202 | #define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk |
| AnnaBridge | 167:e84263d55307 | 9203 | #define DSI_VVACCR_VA10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9204 | #define DSI_VVACCR_VA10_Msk (0x1U << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9205 | #define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk |
| AnnaBridge | 167:e84263d55307 | 9206 | #define DSI_VVACCR_VA11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 9207 | #define DSI_VVACCR_VA11_Msk (0x1U << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 9208 | #define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk |
| AnnaBridge | 167:e84263d55307 | 9209 | #define DSI_VVACCR_VA12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 9210 | #define DSI_VVACCR_VA12_Msk (0x1U << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 9211 | #define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk |
| AnnaBridge | 167:e84263d55307 | 9212 | #define DSI_VVACCR_VA13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9213 | #define DSI_VVACCR_VA13_Msk (0x1U << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9214 | #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk |
| mbed_official | 19:112740acecfa | 9215 | |
| mbed_official | 19:112740acecfa | 9216 | /******************* Bit definition for DSI_TDCCR register **************/ |
| AnnaBridge | 167:e84263d55307 | 9217 | #define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */ |
| AnnaBridge | 167:e84263d55307 | 9218 | #define DSI_TDCCR_3DM0 0x00000001U |
| AnnaBridge | 167:e84263d55307 | 9219 | #define DSI_TDCCR_3DM1 0x00000002U |
| AnnaBridge | 167:e84263d55307 | 9220 | |
| AnnaBridge | 167:e84263d55307 | 9221 | #define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */ |
| AnnaBridge | 167:e84263d55307 | 9222 | #define DSI_TDCCR_3DF0 0x00000004U |
| AnnaBridge | 167:e84263d55307 | 9223 | #define DSI_TDCCR_3DF1 0x00000008U |
| AnnaBridge | 167:e84263d55307 | 9224 | |
| AnnaBridge | 167:e84263d55307 | 9225 | #define DSI_TDCCR_SVS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9226 | #define DSI_TDCCR_SVS_Msk (0x1U << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9227 | #define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk /*!< Second VSYNC */ |
| AnnaBridge | 167:e84263d55307 | 9228 | #define DSI_TDCCR_RF_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9229 | #define DSI_TDCCR_RF_Msk (0x1U << DSI_TDCCR_RF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9230 | #define DSI_TDCCR_RF DSI_TDCCR_RF_Msk /*!< Right First */ |
| AnnaBridge | 167:e84263d55307 | 9231 | #define DSI_TDCCR_S3DC_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9232 | #define DSI_TDCCR_S3DC_Msk (0x1U << DSI_TDCCR_S3DC_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 9233 | #define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk /*!< Send 3D Control */ |
| mbed_official | 19:112740acecfa | 9234 | |
| mbed_official | 19:112740acecfa | 9235 | /******************* Bit definition for DSI_WCFGR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 9236 | #define DSI_WCFGR_DSIM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9237 | #define DSI_WCFGR_DSIM_Msk (0x1U << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9238 | #define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */ |
| AnnaBridge | 167:e84263d55307 | 9239 | #define DSI_WCFGR_COLMUX_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9240 | #define DSI_WCFGR_COLMUX_Msk (0x7U << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */ |
| AnnaBridge | 167:e84263d55307 | 9241 | #define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */ |
| AnnaBridge | 167:e84263d55307 | 9242 | #define DSI_WCFGR_COLMUX0_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9243 | #define DSI_WCFGR_COLMUX0_Msk (0x1U << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9244 | #define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk |
| AnnaBridge | 167:e84263d55307 | 9245 | #define DSI_WCFGR_COLMUX1_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9246 | #define DSI_WCFGR_COLMUX1_Msk (0x1U << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9247 | #define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk |
| AnnaBridge | 167:e84263d55307 | 9248 | #define DSI_WCFGR_COLMUX2_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9249 | #define DSI_WCFGR_COLMUX2_Msk (0x1U << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9250 | #define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk |
| AnnaBridge | 167:e84263d55307 | 9251 | |
| AnnaBridge | 167:e84263d55307 | 9252 | #define DSI_WCFGR_TESRC_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9253 | #define DSI_WCFGR_TESRC_Msk (0x1U << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9254 | #define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */ |
| AnnaBridge | 167:e84263d55307 | 9255 | #define DSI_WCFGR_TEPOL_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9256 | #define DSI_WCFGR_TEPOL_Msk (0x1U << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9257 | #define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */ |
| AnnaBridge | 167:e84263d55307 | 9258 | #define DSI_WCFGR_AR_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9259 | #define DSI_WCFGR_AR_Msk (0x1U << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9260 | #define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */ |
| AnnaBridge | 167:e84263d55307 | 9261 | #define DSI_WCFGR_VSPOL_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9262 | #define DSI_WCFGR_VSPOL_Msk (0x1U << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9263 | #define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */ |
| mbed_official | 19:112740acecfa | 9264 | |
| mbed_official | 19:112740acecfa | 9265 | /******************* Bit definition for DSI_WCR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 9266 | #define DSI_WCR_COLM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9267 | #define DSI_WCR_COLM_Msk (0x1U << DSI_WCR_COLM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9268 | #define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */ |
| AnnaBridge | 167:e84263d55307 | 9269 | #define DSI_WCR_SHTDN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9270 | #define DSI_WCR_SHTDN_Msk (0x1U << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9271 | #define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */ |
| AnnaBridge | 167:e84263d55307 | 9272 | #define DSI_WCR_LTDCEN_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9273 | #define DSI_WCR_LTDCEN_Msk (0x1U << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9274 | #define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */ |
| AnnaBridge | 167:e84263d55307 | 9275 | #define DSI_WCR_DSIEN_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9276 | #define DSI_WCR_DSIEN_Msk (0x1U << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9277 | #define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */ |
| mbed_official | 19:112740acecfa | 9278 | |
| mbed_official | 19:112740acecfa | 9279 | /******************* Bit definition for DSI_WIER register ****************/ |
| AnnaBridge | 167:e84263d55307 | 9280 | #define DSI_WIER_TEIE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9281 | #define DSI_WIER_TEIE_Msk (0x1U << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9282 | #define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 9283 | #define DSI_WIER_ERIE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9284 | #define DSI_WIER_ERIE_Msk (0x1U << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9285 | #define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 9286 | #define DSI_WIER_PLLLIE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9287 | #define DSI_WIER_PLLLIE_Msk (0x1U << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9288 | #define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 9289 | #define DSI_WIER_PLLUIE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9290 | #define DSI_WIER_PLLUIE_Msk (0x1U << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9291 | #define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 9292 | #define DSI_WIER_RRIE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9293 | #define DSI_WIER_RRIE_Msk (0x1U << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9294 | #define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */ |
| mbed_official | 19:112740acecfa | 9295 | |
| mbed_official | 19:112740acecfa | 9296 | /******************* Bit definition for DSI_WISR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 9297 | #define DSI_WISR_TEIF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9298 | #define DSI_WISR_TEIF_Msk (0x1U << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9299 | #define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 9300 | #define DSI_WISR_ERIF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9301 | #define DSI_WISR_ERIF_Msk (0x1U << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9302 | #define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 9303 | #define DSI_WISR_BUSY_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9304 | #define DSI_WISR_BUSY_Msk (0x1U << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9305 | #define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */ |
| AnnaBridge | 167:e84263d55307 | 9306 | #define DSI_WISR_PLLLS_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9307 | #define DSI_WISR_PLLLS_Msk (0x1U << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9308 | #define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */ |
| AnnaBridge | 167:e84263d55307 | 9309 | #define DSI_WISR_PLLLIF_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9310 | #define DSI_WISR_PLLLIF_Msk (0x1U << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9311 | #define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 9312 | #define DSI_WISR_PLLUIF_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9313 | #define DSI_WISR_PLLUIF_Msk (0x1U << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9314 | #define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 9315 | #define DSI_WISR_RRS_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 9316 | #define DSI_WISR_RRS_Msk (0x1U << DSI_WISR_RRS_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 9317 | #define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */ |
| AnnaBridge | 167:e84263d55307 | 9318 | #define DSI_WISR_RRIF_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9319 | #define DSI_WISR_RRIF_Msk (0x1U << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9320 | #define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */ |
| mbed_official | 19:112740acecfa | 9321 | |
| mbed_official | 19:112740acecfa | 9322 | /******************* Bit definition for DSI_WIFCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 9323 | #define DSI_WIFCR_CTEIF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9324 | #define DSI_WIFCR_CTEIF_Msk (0x1U << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9325 | #define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 9326 | #define DSI_WIFCR_CERIF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9327 | #define DSI_WIFCR_CERIF_Msk (0x1U << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9328 | #define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 9329 | #define DSI_WIFCR_CPLLLIF_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9330 | #define DSI_WIFCR_CPLLLIF_Msk (0x1U << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9331 | #define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 9332 | #define DSI_WIFCR_CPLLUIF_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9333 | #define DSI_WIFCR_CPLLUIF_Msk (0x1U << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9334 | #define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 9335 | #define DSI_WIFCR_CRRIF_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9336 | #define DSI_WIFCR_CRRIF_Msk (0x1U << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9337 | #define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */ |
| mbed_official | 19:112740acecfa | 9338 | |
| mbed_official | 19:112740acecfa | 9339 | /******************* Bit definition for DSI_WPCR0 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 9340 | #define DSI_WPCR0_UIX4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9341 | #define DSI_WPCR0_UIX4_Msk (0x3FU << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 167:e84263d55307 | 9342 | #define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */ |
| AnnaBridge | 167:e84263d55307 | 9343 | #define DSI_WPCR0_UIX4_0 (0x01U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9344 | #define DSI_WPCR0_UIX4_1 (0x02U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9345 | #define DSI_WPCR0_UIX4_2 (0x04U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9346 | #define DSI_WPCR0_UIX4_3 (0x08U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9347 | #define DSI_WPCR0_UIX4_4 (0x10U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9348 | #define DSI_WPCR0_UIX4_5 (0x20U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9349 | |
| AnnaBridge | 167:e84263d55307 | 9350 | #define DSI_WPCR0_SWCL_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9351 | #define DSI_WPCR0_SWCL_Msk (0x1U << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9352 | #define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */ |
| AnnaBridge | 167:e84263d55307 | 9353 | #define DSI_WPCR0_SWDL0_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9354 | #define DSI_WPCR0_SWDL0_Msk (0x1U << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9355 | #define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */ |
| AnnaBridge | 167:e84263d55307 | 9356 | #define DSI_WPCR0_SWDL1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9357 | #define DSI_WPCR0_SWDL1_Msk (0x1U << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9358 | #define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */ |
| AnnaBridge | 167:e84263d55307 | 9359 | #define DSI_WPCR0_HSICL_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9360 | #define DSI_WPCR0_HSICL_Msk (0x1U << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9361 | #define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */ |
| AnnaBridge | 167:e84263d55307 | 9362 | #define DSI_WPCR0_HSIDL0_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9363 | #define DSI_WPCR0_HSIDL0_Msk (0x1U << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9364 | #define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */ |
| AnnaBridge | 167:e84263d55307 | 9365 | #define DSI_WPCR0_HSIDL1_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 9366 | #define DSI_WPCR0_HSIDL1_Msk (0x1U << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 9367 | #define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */ |
| AnnaBridge | 167:e84263d55307 | 9368 | #define DSI_WPCR0_FTXSMCL_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 9369 | #define DSI_WPCR0_FTXSMCL_Msk (0x1U << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 9370 | #define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */ |
| AnnaBridge | 167:e84263d55307 | 9371 | #define DSI_WPCR0_FTXSMDL_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9372 | #define DSI_WPCR0_FTXSMDL_Msk (0x1U << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9373 | #define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */ |
| AnnaBridge | 167:e84263d55307 | 9374 | #define DSI_WPCR0_CDOFFDL_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 9375 | #define DSI_WPCR0_CDOFFDL_Msk (0x1U << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 9376 | #define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */ |
| AnnaBridge | 167:e84263d55307 | 9377 | #define DSI_WPCR0_TDDL_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9378 | #define DSI_WPCR0_TDDL_Msk (0x1U << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 9379 | #define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */ |
| AnnaBridge | 167:e84263d55307 | 9380 | #define DSI_WPCR0_PDEN_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 9381 | #define DSI_WPCR0_PDEN_Msk (0x1U << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 9382 | #define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */ |
| AnnaBridge | 167:e84263d55307 | 9383 | #define DSI_WPCR0_TCLKPREPEN_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 9384 | #define DSI_WPCR0_TCLKPREPEN_Msk (0x1U << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 9385 | #define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */ |
| AnnaBridge | 167:e84263d55307 | 9386 | #define DSI_WPCR0_TCLKZEROEN_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 9387 | #define DSI_WPCR0_TCLKZEROEN_Msk (0x1U << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 9388 | #define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */ |
| AnnaBridge | 167:e84263d55307 | 9389 | #define DSI_WPCR0_THSPREPEN_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 9390 | #define DSI_WPCR0_THSPREPEN_Msk (0x1U << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 9391 | #define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */ |
| AnnaBridge | 167:e84263d55307 | 9392 | #define DSI_WPCR0_THSTRAILEN_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 9393 | #define DSI_WPCR0_THSTRAILEN_Msk (0x1U << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 9394 | #define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */ |
| AnnaBridge | 167:e84263d55307 | 9395 | #define DSI_WPCR0_THSZEROEN_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 9396 | #define DSI_WPCR0_THSZEROEN_Msk (0x1U << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 9397 | #define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */ |
| AnnaBridge | 167:e84263d55307 | 9398 | #define DSI_WPCR0_TLPXDEN_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 9399 | #define DSI_WPCR0_TLPXDEN_Msk (0x1U << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 9400 | #define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */ |
| AnnaBridge | 167:e84263d55307 | 9401 | #define DSI_WPCR0_THSEXITEN_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 9402 | #define DSI_WPCR0_THSEXITEN_Msk (0x1U << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 9403 | #define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */ |
| AnnaBridge | 167:e84263d55307 | 9404 | #define DSI_WPCR0_TLPXCEN_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 9405 | #define DSI_WPCR0_TLPXCEN_Msk (0x1U << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 9406 | #define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */ |
| AnnaBridge | 167:e84263d55307 | 9407 | #define DSI_WPCR0_TCLKPOSTEN_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 9408 | #define DSI_WPCR0_TCLKPOSTEN_Msk (0x1U << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 9409 | #define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */ |
| mbed_official | 19:112740acecfa | 9410 | |
| mbed_official | 19:112740acecfa | 9411 | /******************* Bit definition for DSI_WPCR1 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 9412 | #define DSI_WPCR1_HSTXDCL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9413 | #define DSI_WPCR1_HSTXDCL_Msk (0x3U << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 9414 | #define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */ |
| AnnaBridge | 167:e84263d55307 | 9415 | #define DSI_WPCR1_HSTXDCL0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9416 | #define DSI_WPCR1_HSTXDCL0_Msk (0x1U << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9417 | #define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk |
| AnnaBridge | 167:e84263d55307 | 9418 | #define DSI_WPCR1_HSTXDCL1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9419 | #define DSI_WPCR1_HSTXDCL1_Msk (0x1U << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9420 | #define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk |
| AnnaBridge | 167:e84263d55307 | 9421 | |
| AnnaBridge | 167:e84263d55307 | 9422 | #define DSI_WPCR1_HSTXDDL_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9423 | #define DSI_WPCR1_HSTXDDL_Msk (0x3U << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 9424 | #define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */ |
| AnnaBridge | 167:e84263d55307 | 9425 | #define DSI_WPCR1_HSTXDDL0_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9426 | #define DSI_WPCR1_HSTXDDL0_Msk (0x1U << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9427 | #define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk |
| AnnaBridge | 167:e84263d55307 | 9428 | #define DSI_WPCR1_HSTXDDL1_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9429 | #define DSI_WPCR1_HSTXDDL1_Msk (0x1U << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9430 | #define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk |
| AnnaBridge | 167:e84263d55307 | 9431 | |
| AnnaBridge | 167:e84263d55307 | 9432 | #define DSI_WPCR1_LPSRCCL_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9433 | #define DSI_WPCR1_LPSRCCL_Msk (0x3U << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 9434 | #define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */ |
| AnnaBridge | 167:e84263d55307 | 9435 | #define DSI_WPCR1_LPSRCCL0_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9436 | #define DSI_WPCR1_LPSRCCL0_Msk (0x1U << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9437 | #define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk |
| AnnaBridge | 167:e84263d55307 | 9438 | #define DSI_WPCR1_LPSRCCL1_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9439 | #define DSI_WPCR1_LPSRCCL1_Msk (0x1U << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9440 | #define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk |
| AnnaBridge | 167:e84263d55307 | 9441 | |
| AnnaBridge | 167:e84263d55307 | 9442 | #define DSI_WPCR1_LPSRCDL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9443 | #define DSI_WPCR1_LPSRCDL_Msk (0x3U << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 9444 | #define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */ |
| AnnaBridge | 167:e84263d55307 | 9445 | #define DSI_WPCR1_LPSRCDL0_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9446 | #define DSI_WPCR1_LPSRCDL0_Msk (0x1U << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9447 | #define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk |
| AnnaBridge | 167:e84263d55307 | 9448 | #define DSI_WPCR1_LPSRCDL1_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9449 | #define DSI_WPCR1_LPSRCDL1_Msk (0x1U << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9450 | #define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk |
| AnnaBridge | 167:e84263d55307 | 9451 | |
| AnnaBridge | 167:e84263d55307 | 9452 | #define DSI_WPCR1_SDDC_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 9453 | #define DSI_WPCR1_SDDC_Msk (0x1U << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 9454 | #define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */ |
| AnnaBridge | 167:e84263d55307 | 9455 | |
| AnnaBridge | 167:e84263d55307 | 9456 | #define DSI_WPCR1_LPRXVCDL_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 9457 | #define DSI_WPCR1_LPRXVCDL_Msk (0x3U << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 9458 | #define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */ |
| AnnaBridge | 167:e84263d55307 | 9459 | #define DSI_WPCR1_LPRXVCDL0_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 9460 | #define DSI_WPCR1_LPRXVCDL0_Msk (0x1U << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 9461 | #define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk |
| AnnaBridge | 167:e84263d55307 | 9462 | #define DSI_WPCR1_LPRXVCDL1_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 9463 | #define DSI_WPCR1_LPRXVCDL1_Msk (0x1U << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 9464 | #define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk |
| AnnaBridge | 167:e84263d55307 | 9465 | |
| AnnaBridge | 167:e84263d55307 | 9466 | #define DSI_WPCR1_HSTXSRCCL_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9467 | #define DSI_WPCR1_HSTXSRCCL_Msk (0x3U << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 9468 | #define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */ |
| AnnaBridge | 167:e84263d55307 | 9469 | #define DSI_WPCR1_HSTXSRCCL0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9470 | #define DSI_WPCR1_HSTXSRCCL0_Msk (0x1U << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 9471 | #define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk |
| AnnaBridge | 167:e84263d55307 | 9472 | #define DSI_WPCR1_HSTXSRCCL1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 9473 | #define DSI_WPCR1_HSTXSRCCL1_Msk (0x1U << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 9474 | #define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk |
| AnnaBridge | 167:e84263d55307 | 9475 | |
| AnnaBridge | 167:e84263d55307 | 9476 | #define DSI_WPCR1_HSTXSRCDL_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 9477 | #define DSI_WPCR1_HSTXSRCDL_Msk (0x3U << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 167:e84263d55307 | 9478 | #define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */ |
| AnnaBridge | 167:e84263d55307 | 9479 | #define DSI_WPCR1_HSTXSRCDL0_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 9480 | #define DSI_WPCR1_HSTXSRCDL0_Msk (0x1U << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 9481 | #define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk |
| AnnaBridge | 167:e84263d55307 | 9482 | #define DSI_WPCR1_HSTXSRCDL1_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 9483 | #define DSI_WPCR1_HSTXSRCDL1_Msk (0x1U << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 9484 | #define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk |
| AnnaBridge | 167:e84263d55307 | 9485 | |
| AnnaBridge | 167:e84263d55307 | 9486 | #define DSI_WPCR1_FLPRXLPM_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 9487 | #define DSI_WPCR1_FLPRXLPM_Msk (0x1U << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 9488 | #define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */ |
| AnnaBridge | 167:e84263d55307 | 9489 | |
| AnnaBridge | 167:e84263d55307 | 9490 | #define DSI_WPCR1_LPRXFT_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 9491 | #define DSI_WPCR1_LPRXFT_Msk (0x3U << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */ |
| AnnaBridge | 167:e84263d55307 | 9492 | #define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */ |
| AnnaBridge | 167:e84263d55307 | 9493 | #define DSI_WPCR1_LPRXFT0_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 9494 | #define DSI_WPCR1_LPRXFT0_Msk (0x1U << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 9495 | #define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk |
| AnnaBridge | 167:e84263d55307 | 9496 | #define DSI_WPCR1_LPRXFT1_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 9497 | #define DSI_WPCR1_LPRXFT1_Msk (0x1U << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 9498 | #define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk |
| mbed_official | 19:112740acecfa | 9499 | |
| mbed_official | 19:112740acecfa | 9500 | /******************* Bit definition for DSI_WPCR2 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 9501 | #define DSI_WPCR2_TCLKPREP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9502 | #define DSI_WPCR2_TCLKPREP_Msk (0xFFU << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 9503 | #define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */ |
| AnnaBridge | 167:e84263d55307 | 9504 | #define DSI_WPCR2_TCLKPREP0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9505 | #define DSI_WPCR2_TCLKPREP0_Msk (0x1U << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9506 | #define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk |
| AnnaBridge | 167:e84263d55307 | 9507 | #define DSI_WPCR2_TCLKPREP1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9508 | #define DSI_WPCR2_TCLKPREP1_Msk (0x1U << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9509 | #define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk |
| AnnaBridge | 167:e84263d55307 | 9510 | #define DSI_WPCR2_TCLKPREP2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9511 | #define DSI_WPCR2_TCLKPREP2_Msk (0x1U << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9512 | #define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk |
| AnnaBridge | 167:e84263d55307 | 9513 | #define DSI_WPCR2_TCLKPREP3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9514 | #define DSI_WPCR2_TCLKPREP3_Msk (0x1U << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9515 | #define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk |
| AnnaBridge | 167:e84263d55307 | 9516 | #define DSI_WPCR2_TCLKPREP4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9517 | #define DSI_WPCR2_TCLKPREP4_Msk (0x1U << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9518 | #define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk |
| AnnaBridge | 167:e84263d55307 | 9519 | #define DSI_WPCR2_TCLKPREP5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9520 | #define DSI_WPCR2_TCLKPREP5_Msk (0x1U << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9521 | #define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk |
| AnnaBridge | 167:e84263d55307 | 9522 | #define DSI_WPCR2_TCLKPREP6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9523 | #define DSI_WPCR2_TCLKPREP6_Msk (0x1U << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9524 | #define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk |
| AnnaBridge | 167:e84263d55307 | 9525 | #define DSI_WPCR2_TCLKPREP7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9526 | #define DSI_WPCR2_TCLKPREP7_Msk (0x1U << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9527 | #define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk |
| AnnaBridge | 167:e84263d55307 | 9528 | |
| AnnaBridge | 167:e84263d55307 | 9529 | #define DSI_WPCR2_TCLKZERO_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9530 | #define DSI_WPCR2_TCLKZERO_Msk (0xFFU << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 9531 | #define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */ |
| AnnaBridge | 167:e84263d55307 | 9532 | #define DSI_WPCR2_TCLKZERO0_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9533 | #define DSI_WPCR2_TCLKZERO0_Msk (0x1U << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9534 | #define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk |
| AnnaBridge | 167:e84263d55307 | 9535 | #define DSI_WPCR2_TCLKZERO1_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9536 | #define DSI_WPCR2_TCLKZERO1_Msk (0x1U << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9537 | #define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk |
| AnnaBridge | 167:e84263d55307 | 9538 | #define DSI_WPCR2_TCLKZERO2_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9539 | #define DSI_WPCR2_TCLKZERO2_Msk (0x1U << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9540 | #define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk |
| AnnaBridge | 167:e84263d55307 | 9541 | #define DSI_WPCR2_TCLKZERO3_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 9542 | #define DSI_WPCR2_TCLKZERO3_Msk (0x1U << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 9543 | #define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk |
| AnnaBridge | 167:e84263d55307 | 9544 | #define DSI_WPCR2_TCLKZERO4_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 9545 | #define DSI_WPCR2_TCLKZERO4_Msk (0x1U << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 9546 | #define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk |
| AnnaBridge | 167:e84263d55307 | 9547 | #define DSI_WPCR2_TCLKZERO5_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9548 | #define DSI_WPCR2_TCLKZERO5_Msk (0x1U << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9549 | #define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk |
| AnnaBridge | 167:e84263d55307 | 9550 | #define DSI_WPCR2_TCLKZERO6_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 9551 | #define DSI_WPCR2_TCLKZERO6_Msk (0x1U << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 9552 | #define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk |
| AnnaBridge | 167:e84263d55307 | 9553 | #define DSI_WPCR2_TCLKZERO7_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 9554 | #define DSI_WPCR2_TCLKZERO7_Msk (0x1U << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 9555 | #define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk |
| AnnaBridge | 167:e84263d55307 | 9556 | |
| AnnaBridge | 167:e84263d55307 | 9557 | #define DSI_WPCR2_THSPREP_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9558 | #define DSI_WPCR2_THSPREP_Msk (0xFFU << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 9559 | #define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */ |
| AnnaBridge | 167:e84263d55307 | 9560 | #define DSI_WPCR2_THSPREP0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9561 | #define DSI_WPCR2_THSPREP0_Msk (0x1U << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 9562 | #define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk |
| AnnaBridge | 167:e84263d55307 | 9563 | #define DSI_WPCR2_THSPREP1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 9564 | #define DSI_WPCR2_THSPREP1_Msk (0x1U << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 9565 | #define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk |
| AnnaBridge | 167:e84263d55307 | 9566 | #define DSI_WPCR2_THSPREP2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 9567 | #define DSI_WPCR2_THSPREP2_Msk (0x1U << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 9568 | #define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk |
| AnnaBridge | 167:e84263d55307 | 9569 | #define DSI_WPCR2_THSPREP3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 9570 | #define DSI_WPCR2_THSPREP3_Msk (0x1U << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 9571 | #define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk |
| AnnaBridge | 167:e84263d55307 | 9572 | #define DSI_WPCR2_THSPREP4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 9573 | #define DSI_WPCR2_THSPREP4_Msk (0x1U << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 9574 | #define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk |
| AnnaBridge | 167:e84263d55307 | 9575 | #define DSI_WPCR2_THSPREP5_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 9576 | #define DSI_WPCR2_THSPREP5_Msk (0x1U << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 9577 | #define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk |
| AnnaBridge | 167:e84263d55307 | 9578 | #define DSI_WPCR2_THSPREP6_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 9579 | #define DSI_WPCR2_THSPREP6_Msk (0x1U << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 9580 | #define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk |
| AnnaBridge | 167:e84263d55307 | 9581 | #define DSI_WPCR2_THSPREP7_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 9582 | #define DSI_WPCR2_THSPREP7_Msk (0x1U << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 9583 | #define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk |
| AnnaBridge | 167:e84263d55307 | 9584 | |
| AnnaBridge | 167:e84263d55307 | 9585 | #define DSI_WPCR2_THSTRAIL_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 9586 | #define DSI_WPCR2_THSTRAIL_Msk (0xFFU << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 9587 | #define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */ |
| AnnaBridge | 167:e84263d55307 | 9588 | #define DSI_WPCR2_THSTRAIL0_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 9589 | #define DSI_WPCR2_THSTRAIL0_Msk (0x1U << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 9590 | #define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk |
| AnnaBridge | 167:e84263d55307 | 9591 | #define DSI_WPCR2_THSTRAIL1_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 9592 | #define DSI_WPCR2_THSTRAIL1_Msk (0x1U << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 9593 | #define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk |
| AnnaBridge | 167:e84263d55307 | 9594 | #define DSI_WPCR2_THSTRAIL2_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 9595 | #define DSI_WPCR2_THSTRAIL2_Msk (0x1U << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 9596 | #define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk |
| AnnaBridge | 167:e84263d55307 | 9597 | #define DSI_WPCR2_THSTRAIL3_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 9598 | #define DSI_WPCR2_THSTRAIL3_Msk (0x1U << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 9599 | #define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk |
| AnnaBridge | 167:e84263d55307 | 9600 | #define DSI_WPCR2_THSTRAIL4_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 9601 | #define DSI_WPCR2_THSTRAIL4_Msk (0x1U << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 9602 | #define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk |
| AnnaBridge | 167:e84263d55307 | 9603 | #define DSI_WPCR2_THSTRAIL5_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 9604 | #define DSI_WPCR2_THSTRAIL5_Msk (0x1U << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 9605 | #define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk |
| AnnaBridge | 167:e84263d55307 | 9606 | #define DSI_WPCR2_THSTRAIL6_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 9607 | #define DSI_WPCR2_THSTRAIL6_Msk (0x1U << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 9608 | #define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk |
| AnnaBridge | 167:e84263d55307 | 9609 | #define DSI_WPCR2_THSTRAIL7_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 9610 | #define DSI_WPCR2_THSTRAIL7_Msk (0x1U << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 9611 | #define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk |
| mbed_official | 19:112740acecfa | 9612 | |
| mbed_official | 19:112740acecfa | 9613 | /******************* Bit definition for DSI_WPCR3 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 9614 | #define DSI_WPCR3_THSZERO_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9615 | #define DSI_WPCR3_THSZERO_Msk (0xFFU << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 9616 | #define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */ |
| AnnaBridge | 167:e84263d55307 | 9617 | #define DSI_WPCR3_THSZERO0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9618 | #define DSI_WPCR3_THSZERO0_Msk (0x1U << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9619 | #define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk |
| AnnaBridge | 167:e84263d55307 | 9620 | #define DSI_WPCR3_THSZERO1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9621 | #define DSI_WPCR3_THSZERO1_Msk (0x1U << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9622 | #define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk |
| AnnaBridge | 167:e84263d55307 | 9623 | #define DSI_WPCR3_THSZERO2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9624 | #define DSI_WPCR3_THSZERO2_Msk (0x1U << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9625 | #define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk |
| AnnaBridge | 167:e84263d55307 | 9626 | #define DSI_WPCR3_THSZERO3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9627 | #define DSI_WPCR3_THSZERO3_Msk (0x1U << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9628 | #define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk |
| AnnaBridge | 167:e84263d55307 | 9629 | #define DSI_WPCR3_THSZERO4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9630 | #define DSI_WPCR3_THSZERO4_Msk (0x1U << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9631 | #define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk |
| AnnaBridge | 167:e84263d55307 | 9632 | #define DSI_WPCR3_THSZERO5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9633 | #define DSI_WPCR3_THSZERO5_Msk (0x1U << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9634 | #define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk |
| AnnaBridge | 167:e84263d55307 | 9635 | #define DSI_WPCR3_THSZERO6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9636 | #define DSI_WPCR3_THSZERO6_Msk (0x1U << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9637 | #define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk |
| AnnaBridge | 167:e84263d55307 | 9638 | #define DSI_WPCR3_THSZERO7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9639 | #define DSI_WPCR3_THSZERO7_Msk (0x1U << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9640 | #define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk |
| AnnaBridge | 167:e84263d55307 | 9641 | |
| AnnaBridge | 167:e84263d55307 | 9642 | #define DSI_WPCR3_TLPXD_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9643 | #define DSI_WPCR3_TLPXD_Msk (0xFFU << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 9644 | #define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */ |
| AnnaBridge | 167:e84263d55307 | 9645 | #define DSI_WPCR3_TLPXD0_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9646 | #define DSI_WPCR3_TLPXD0_Msk (0x1U << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9647 | #define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk |
| AnnaBridge | 167:e84263d55307 | 9648 | #define DSI_WPCR3_TLPXD1_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9649 | #define DSI_WPCR3_TLPXD1_Msk (0x1U << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9650 | #define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk |
| AnnaBridge | 167:e84263d55307 | 9651 | #define DSI_WPCR3_TLPXD2_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9652 | #define DSI_WPCR3_TLPXD2_Msk (0x1U << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9653 | #define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk |
| AnnaBridge | 167:e84263d55307 | 9654 | #define DSI_WPCR3_TLPXD3_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 9655 | #define DSI_WPCR3_TLPXD3_Msk (0x1U << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 9656 | #define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk |
| AnnaBridge | 167:e84263d55307 | 9657 | #define DSI_WPCR3_TLPXD4_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 9658 | #define DSI_WPCR3_TLPXD4_Msk (0x1U << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 9659 | #define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk |
| AnnaBridge | 167:e84263d55307 | 9660 | #define DSI_WPCR3_TLPXD5_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9661 | #define DSI_WPCR3_TLPXD5_Msk (0x1U << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9662 | #define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk |
| AnnaBridge | 167:e84263d55307 | 9663 | #define DSI_WPCR3_TLPXD6_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 9664 | #define DSI_WPCR3_TLPXD6_Msk (0x1U << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 9665 | #define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk |
| AnnaBridge | 167:e84263d55307 | 9666 | #define DSI_WPCR3_TLPXD7_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 9667 | #define DSI_WPCR3_TLPXD7_Msk (0x1U << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 9668 | #define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk |
| AnnaBridge | 167:e84263d55307 | 9669 | |
| AnnaBridge | 167:e84263d55307 | 9670 | #define DSI_WPCR3_THSEXIT_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9671 | #define DSI_WPCR3_THSEXIT_Msk (0xFFU << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 9672 | #define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */ |
| AnnaBridge | 167:e84263d55307 | 9673 | #define DSI_WPCR3_THSEXIT0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9674 | #define DSI_WPCR3_THSEXIT0_Msk (0x1U << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 9675 | #define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk |
| AnnaBridge | 167:e84263d55307 | 9676 | #define DSI_WPCR3_THSEXIT1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 9677 | #define DSI_WPCR3_THSEXIT1_Msk (0x1U << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 9678 | #define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk |
| AnnaBridge | 167:e84263d55307 | 9679 | #define DSI_WPCR3_THSEXIT2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 9680 | #define DSI_WPCR3_THSEXIT2_Msk (0x1U << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 9681 | #define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk |
| AnnaBridge | 167:e84263d55307 | 9682 | #define DSI_WPCR3_THSEXIT3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 9683 | #define DSI_WPCR3_THSEXIT3_Msk (0x1U << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 9684 | #define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk |
| AnnaBridge | 167:e84263d55307 | 9685 | #define DSI_WPCR3_THSEXIT4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 9686 | #define DSI_WPCR3_THSEXIT4_Msk (0x1U << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 9687 | #define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk |
| AnnaBridge | 167:e84263d55307 | 9688 | #define DSI_WPCR3_THSEXIT5_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 9689 | #define DSI_WPCR3_THSEXIT5_Msk (0x1U << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 9690 | #define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk |
| AnnaBridge | 167:e84263d55307 | 9691 | #define DSI_WPCR3_THSEXIT6_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 9692 | #define DSI_WPCR3_THSEXIT6_Msk (0x1U << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 9693 | #define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk |
| AnnaBridge | 167:e84263d55307 | 9694 | #define DSI_WPCR3_THSEXIT7_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 9695 | #define DSI_WPCR3_THSEXIT7_Msk (0x1U << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 9696 | #define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk |
| AnnaBridge | 167:e84263d55307 | 9697 | |
| AnnaBridge | 167:e84263d55307 | 9698 | #define DSI_WPCR3_TLPXC_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 9699 | #define DSI_WPCR3_TLPXC_Msk (0xFFU << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 9700 | #define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */ |
| AnnaBridge | 167:e84263d55307 | 9701 | #define DSI_WPCR3_TLPXC0_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 9702 | #define DSI_WPCR3_TLPXC0_Msk (0x1U << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 9703 | #define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk |
| AnnaBridge | 167:e84263d55307 | 9704 | #define DSI_WPCR3_TLPXC1_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 9705 | #define DSI_WPCR3_TLPXC1_Msk (0x1U << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 9706 | #define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk |
| AnnaBridge | 167:e84263d55307 | 9707 | #define DSI_WPCR3_TLPXC2_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 9708 | #define DSI_WPCR3_TLPXC2_Msk (0x1U << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 9709 | #define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk |
| AnnaBridge | 167:e84263d55307 | 9710 | #define DSI_WPCR3_TLPXC3_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 9711 | #define DSI_WPCR3_TLPXC3_Msk (0x1U << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 9712 | #define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk |
| AnnaBridge | 167:e84263d55307 | 9713 | #define DSI_WPCR3_TLPXC4_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 9714 | #define DSI_WPCR3_TLPXC4_Msk (0x1U << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 9715 | #define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk |
| AnnaBridge | 167:e84263d55307 | 9716 | #define DSI_WPCR3_TLPXC5_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 9717 | #define DSI_WPCR3_TLPXC5_Msk (0x1U << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 9718 | #define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk |
| AnnaBridge | 167:e84263d55307 | 9719 | #define DSI_WPCR3_TLPXC6_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 9720 | #define DSI_WPCR3_TLPXC6_Msk (0x1U << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 9721 | #define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk |
| AnnaBridge | 167:e84263d55307 | 9722 | #define DSI_WPCR3_TLPXC7_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 9723 | #define DSI_WPCR3_TLPXC7_Msk (0x1U << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 9724 | #define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk |
| mbed_official | 19:112740acecfa | 9725 | |
| mbed_official | 19:112740acecfa | 9726 | /******************* Bit definition for DSI_WPCR4 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 9727 | #define DSI_WPCR4_TCLKPOST_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9728 | #define DSI_WPCR4_TCLKPOST_Msk (0xFFU << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 9729 | #define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */ |
| AnnaBridge | 167:e84263d55307 | 9730 | #define DSI_WPCR4_TCLKPOST0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9731 | #define DSI_WPCR4_TCLKPOST0_Msk (0x1U << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9732 | #define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk |
| AnnaBridge | 167:e84263d55307 | 9733 | #define DSI_WPCR4_TCLKPOST1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9734 | #define DSI_WPCR4_TCLKPOST1_Msk (0x1U << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9735 | #define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk |
| AnnaBridge | 167:e84263d55307 | 9736 | #define DSI_WPCR4_TCLKPOST2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9737 | #define DSI_WPCR4_TCLKPOST2_Msk (0x1U << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9738 | #define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk |
| AnnaBridge | 167:e84263d55307 | 9739 | #define DSI_WPCR4_TCLKPOST3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9740 | #define DSI_WPCR4_TCLKPOST3_Msk (0x1U << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9741 | #define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk |
| AnnaBridge | 167:e84263d55307 | 9742 | #define DSI_WPCR4_TCLKPOST4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9743 | #define DSI_WPCR4_TCLKPOST4_Msk (0x1U << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9744 | #define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk |
| AnnaBridge | 167:e84263d55307 | 9745 | #define DSI_WPCR4_TCLKPOST5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9746 | #define DSI_WPCR4_TCLKPOST5_Msk (0x1U << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9747 | #define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk |
| AnnaBridge | 167:e84263d55307 | 9748 | #define DSI_WPCR4_TCLKPOST6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9749 | #define DSI_WPCR4_TCLKPOST6_Msk (0x1U << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9750 | #define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk |
| AnnaBridge | 167:e84263d55307 | 9751 | #define DSI_WPCR4_TCLKPOST7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9752 | #define DSI_WPCR4_TCLKPOST7_Msk (0x1U << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9753 | #define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk |
| mbed_official | 19:112740acecfa | 9754 | |
| mbed_official | 19:112740acecfa | 9755 | /******************* Bit definition for DSI_WRPCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 9756 | #define DSI_WRPCR_PLLEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9757 | #define DSI_WRPCR_PLLEN_Msk (0x1U << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9758 | #define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */ |
| AnnaBridge | 167:e84263d55307 | 9759 | #define DSI_WRPCR_PLL_NDIV_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9760 | #define DSI_WRPCR_PLL_NDIV_Msk (0x7FU << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */ |
| AnnaBridge | 167:e84263d55307 | 9761 | #define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */ |
| AnnaBridge | 167:e84263d55307 | 9762 | #define DSI_WRPCR_PLL_NDIV0_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9763 | #define DSI_WRPCR_PLL_NDIV0_Msk (0x1U << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9764 | #define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk |
| AnnaBridge | 167:e84263d55307 | 9765 | #define DSI_WRPCR_PLL_NDIV1_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9766 | #define DSI_WRPCR_PLL_NDIV1_Msk (0x1U << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9767 | #define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk |
| AnnaBridge | 167:e84263d55307 | 9768 | #define DSI_WRPCR_PLL_NDIV2_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9769 | #define DSI_WRPCR_PLL_NDIV2_Msk (0x1U << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9770 | #define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk |
| AnnaBridge | 167:e84263d55307 | 9771 | #define DSI_WRPCR_PLL_NDIV3_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9772 | #define DSI_WRPCR_PLL_NDIV3_Msk (0x1U << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9773 | #define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk |
| AnnaBridge | 167:e84263d55307 | 9774 | #define DSI_WRPCR_PLL_NDIV4_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9775 | #define DSI_WRPCR_PLL_NDIV4_Msk (0x1U << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9776 | #define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk |
| AnnaBridge | 167:e84263d55307 | 9777 | #define DSI_WRPCR_PLL_NDIV5_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9778 | #define DSI_WRPCR_PLL_NDIV5_Msk (0x1U << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9779 | #define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk |
| AnnaBridge | 167:e84263d55307 | 9780 | #define DSI_WRPCR_PLL_NDIV6_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9781 | #define DSI_WRPCR_PLL_NDIV6_Msk (0x1U << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9782 | #define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk |
| AnnaBridge | 167:e84263d55307 | 9783 | |
| AnnaBridge | 167:e84263d55307 | 9784 | #define DSI_WRPCR_PLL_IDF_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 9785 | #define DSI_WRPCR_PLL_IDF_Msk (0xFU << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */ |
| AnnaBridge | 167:e84263d55307 | 9786 | #define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */ |
| AnnaBridge | 167:e84263d55307 | 9787 | #define DSI_WRPCR_PLL_IDF0_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 9788 | #define DSI_WRPCR_PLL_IDF0_Msk (0x1U << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 9789 | #define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk |
| AnnaBridge | 167:e84263d55307 | 9790 | #define DSI_WRPCR_PLL_IDF1_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 9791 | #define DSI_WRPCR_PLL_IDF1_Msk (0x1U << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 9792 | #define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk |
| AnnaBridge | 167:e84263d55307 | 9793 | #define DSI_WRPCR_PLL_IDF2_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9794 | #define DSI_WRPCR_PLL_IDF2_Msk (0x1U << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9795 | #define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk |
| AnnaBridge | 167:e84263d55307 | 9796 | #define DSI_WRPCR_PLL_IDF3_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 9797 | #define DSI_WRPCR_PLL_IDF3_Msk (0x1U << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 9798 | #define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk |
| AnnaBridge | 167:e84263d55307 | 9799 | |
| AnnaBridge | 167:e84263d55307 | 9800 | #define DSI_WRPCR_PLL_ODF_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9801 | #define DSI_WRPCR_PLL_ODF_Msk (0x3U << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 9802 | #define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */ |
| AnnaBridge | 167:e84263d55307 | 9803 | #define DSI_WRPCR_PLL_ODF0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9804 | #define DSI_WRPCR_PLL_ODF0_Msk (0x1U << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 9805 | #define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk |
| AnnaBridge | 167:e84263d55307 | 9806 | #define DSI_WRPCR_PLL_ODF1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 9807 | #define DSI_WRPCR_PLL_ODF1_Msk (0x1U << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 9808 | #define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk |
| AnnaBridge | 167:e84263d55307 | 9809 | |
| AnnaBridge | 167:e84263d55307 | 9810 | #define DSI_WRPCR_REGEN_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 9811 | #define DSI_WRPCR_REGEN_Msk (0x1U << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 9812 | #define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */ |
| mbed_official | 19:112740acecfa | 9813 | |
| mbed_official | 19:112740acecfa | 9814 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 9815 | /* */ |
| mbed_official | 19:112740acecfa | 9816 | /* External Interrupt/Event Controller */ |
| mbed_official | 19:112740acecfa | 9817 | /* */ |
| mbed_official | 19:112740acecfa | 9818 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 9819 | /******************* Bit definition for EXTI_IMR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 9820 | #define EXTI_IMR_MR0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9821 | #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9822 | #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ |
| AnnaBridge | 167:e84263d55307 | 9823 | #define EXTI_IMR_MR1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9824 | #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9825 | #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ |
| AnnaBridge | 167:e84263d55307 | 9826 | #define EXTI_IMR_MR2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9827 | #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9828 | #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ |
| AnnaBridge | 167:e84263d55307 | 9829 | #define EXTI_IMR_MR3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9830 | #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9831 | #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ |
| AnnaBridge | 167:e84263d55307 | 9832 | #define EXTI_IMR_MR4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9833 | #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9834 | #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ |
| AnnaBridge | 167:e84263d55307 | 9835 | #define EXTI_IMR_MR5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9836 | #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9837 | #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ |
| AnnaBridge | 167:e84263d55307 | 9838 | #define EXTI_IMR_MR6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9839 | #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9840 | #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ |
| AnnaBridge | 167:e84263d55307 | 9841 | #define EXTI_IMR_MR7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9842 | #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9843 | #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ |
| AnnaBridge | 167:e84263d55307 | 9844 | #define EXTI_IMR_MR8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9845 | #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9846 | #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ |
| AnnaBridge | 167:e84263d55307 | 9847 | #define EXTI_IMR_MR9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9848 | #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9849 | #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ |
| AnnaBridge | 167:e84263d55307 | 9850 | #define EXTI_IMR_MR10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9851 | #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9852 | #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ |
| AnnaBridge | 167:e84263d55307 | 9853 | #define EXTI_IMR_MR11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 9854 | #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 9855 | #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ |
| AnnaBridge | 167:e84263d55307 | 9856 | #define EXTI_IMR_MR12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 9857 | #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 9858 | #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ |
| AnnaBridge | 167:e84263d55307 | 9859 | #define EXTI_IMR_MR13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9860 | #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9861 | #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ |
| AnnaBridge | 167:e84263d55307 | 9862 | #define EXTI_IMR_MR14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 9863 | #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 9864 | #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ |
| AnnaBridge | 167:e84263d55307 | 9865 | #define EXTI_IMR_MR15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 9866 | #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 9867 | #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ |
| AnnaBridge | 167:e84263d55307 | 9868 | #define EXTI_IMR_MR16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9869 | #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 9870 | #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ |
| AnnaBridge | 167:e84263d55307 | 9871 | #define EXTI_IMR_MR17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 9872 | #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 9873 | #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ |
| AnnaBridge | 167:e84263d55307 | 9874 | #define EXTI_IMR_MR18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 9875 | #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 9876 | #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ |
| AnnaBridge | 167:e84263d55307 | 9877 | #define EXTI_IMR_MR19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 9878 | #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 9879 | #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ |
| AnnaBridge | 167:e84263d55307 | 9880 | #define EXTI_IMR_MR20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 9881 | #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 9882 | #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ |
| AnnaBridge | 167:e84263d55307 | 9883 | #define EXTI_IMR_MR21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 9884 | #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 9885 | #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ |
| AnnaBridge | 167:e84263d55307 | 9886 | #define EXTI_IMR_MR22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 9887 | #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 9888 | #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ |
| AnnaBridge | 167:e84263d55307 | 9889 | |
| AnnaBridge | 167:e84263d55307 | 9890 | /* Reference Defines */ |
| AnnaBridge | 167:e84263d55307 | 9891 | #define EXTI_IMR_IM0 EXTI_IMR_MR0 |
| AnnaBridge | 167:e84263d55307 | 9892 | #define EXTI_IMR_IM1 EXTI_IMR_MR1 |
| AnnaBridge | 167:e84263d55307 | 9893 | #define EXTI_IMR_IM2 EXTI_IMR_MR2 |
| AnnaBridge | 167:e84263d55307 | 9894 | #define EXTI_IMR_IM3 EXTI_IMR_MR3 |
| AnnaBridge | 167:e84263d55307 | 9895 | #define EXTI_IMR_IM4 EXTI_IMR_MR4 |
| AnnaBridge | 167:e84263d55307 | 9896 | #define EXTI_IMR_IM5 EXTI_IMR_MR5 |
| AnnaBridge | 167:e84263d55307 | 9897 | #define EXTI_IMR_IM6 EXTI_IMR_MR6 |
| AnnaBridge | 167:e84263d55307 | 9898 | #define EXTI_IMR_IM7 EXTI_IMR_MR7 |
| AnnaBridge | 167:e84263d55307 | 9899 | #define EXTI_IMR_IM8 EXTI_IMR_MR8 |
| AnnaBridge | 167:e84263d55307 | 9900 | #define EXTI_IMR_IM9 EXTI_IMR_MR9 |
| AnnaBridge | 167:e84263d55307 | 9901 | #define EXTI_IMR_IM10 EXTI_IMR_MR10 |
| AnnaBridge | 167:e84263d55307 | 9902 | #define EXTI_IMR_IM11 EXTI_IMR_MR11 |
| AnnaBridge | 167:e84263d55307 | 9903 | #define EXTI_IMR_IM12 EXTI_IMR_MR12 |
| AnnaBridge | 167:e84263d55307 | 9904 | #define EXTI_IMR_IM13 EXTI_IMR_MR13 |
| AnnaBridge | 167:e84263d55307 | 9905 | #define EXTI_IMR_IM14 EXTI_IMR_MR14 |
| AnnaBridge | 167:e84263d55307 | 9906 | #define EXTI_IMR_IM15 EXTI_IMR_MR15 |
| AnnaBridge | 167:e84263d55307 | 9907 | #define EXTI_IMR_IM16 EXTI_IMR_MR16 |
| AnnaBridge | 167:e84263d55307 | 9908 | #define EXTI_IMR_IM17 EXTI_IMR_MR17 |
| AnnaBridge | 167:e84263d55307 | 9909 | #define EXTI_IMR_IM18 EXTI_IMR_MR18 |
| AnnaBridge | 167:e84263d55307 | 9910 | #define EXTI_IMR_IM19 EXTI_IMR_MR19 |
| AnnaBridge | 167:e84263d55307 | 9911 | #define EXTI_IMR_IM20 EXTI_IMR_MR20 |
| AnnaBridge | 167:e84263d55307 | 9912 | #define EXTI_IMR_IM21 EXTI_IMR_MR21 |
| AnnaBridge | 167:e84263d55307 | 9913 | #define EXTI_IMR_IM22 EXTI_IMR_MR22 |
| AnnaBridge | 167:e84263d55307 | 9914 | #define EXTI_IMR_IM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9915 | #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */ |
| AnnaBridge | 167:e84263d55307 | 9916 | #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ |
| mbed_official | 19:112740acecfa | 9917 | |
| mbed_official | 19:112740acecfa | 9918 | /******************* Bit definition for EXTI_EMR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 9919 | #define EXTI_EMR_MR0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 9920 | #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 9921 | #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ |
| AnnaBridge | 167:e84263d55307 | 9922 | #define EXTI_EMR_MR1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 9923 | #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 9924 | #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ |
| AnnaBridge | 167:e84263d55307 | 9925 | #define EXTI_EMR_MR2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 9926 | #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 9927 | #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ |
| AnnaBridge | 167:e84263d55307 | 9928 | #define EXTI_EMR_MR3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 9929 | #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 9930 | #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ |
| AnnaBridge | 167:e84263d55307 | 9931 | #define EXTI_EMR_MR4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 9932 | #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 9933 | #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ |
| AnnaBridge | 167:e84263d55307 | 9934 | #define EXTI_EMR_MR5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 9935 | #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 9936 | #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ |
| AnnaBridge | 167:e84263d55307 | 9937 | #define EXTI_EMR_MR6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 9938 | #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 9939 | #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ |
| AnnaBridge | 167:e84263d55307 | 9940 | #define EXTI_EMR_MR7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 9941 | #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 9942 | #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ |
| AnnaBridge | 167:e84263d55307 | 9943 | #define EXTI_EMR_MR8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 9944 | #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 9945 | #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ |
| AnnaBridge | 167:e84263d55307 | 9946 | #define EXTI_EMR_MR9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 9947 | #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 9948 | #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ |
| AnnaBridge | 167:e84263d55307 | 9949 | #define EXTI_EMR_MR10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 9950 | #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 9951 | #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ |
| AnnaBridge | 167:e84263d55307 | 9952 | #define EXTI_EMR_MR11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 9953 | #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 9954 | #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ |
| AnnaBridge | 167:e84263d55307 | 9955 | #define EXTI_EMR_MR12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 9956 | #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 9957 | #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ |
| AnnaBridge | 167:e84263d55307 | 9958 | #define EXTI_EMR_MR13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 9959 | #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 9960 | #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ |
| AnnaBridge | 167:e84263d55307 | 9961 | #define EXTI_EMR_MR14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 9962 | #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 9963 | #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ |
| AnnaBridge | 167:e84263d55307 | 9964 | #define EXTI_EMR_MR15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 9965 | #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 9966 | #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ |
| AnnaBridge | 167:e84263d55307 | 9967 | #define EXTI_EMR_MR16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 9968 | #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 9969 | #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ |
| AnnaBridge | 167:e84263d55307 | 9970 | #define EXTI_EMR_MR17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 9971 | #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 9972 | #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ |
| AnnaBridge | 167:e84263d55307 | 9973 | #define EXTI_EMR_MR18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 9974 | #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 9975 | #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ |
| AnnaBridge | 167:e84263d55307 | 9976 | #define EXTI_EMR_MR19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 9977 | #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 9978 | #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ |
| AnnaBridge | 167:e84263d55307 | 9979 | #define EXTI_EMR_MR20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 9980 | #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 9981 | #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ |
| AnnaBridge | 167:e84263d55307 | 9982 | #define EXTI_EMR_MR21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 9983 | #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 9984 | #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ |
| AnnaBridge | 167:e84263d55307 | 9985 | #define EXTI_EMR_MR22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 9986 | #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 9987 | #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ |
| AnnaBridge | 167:e84263d55307 | 9988 | |
| AnnaBridge | 167:e84263d55307 | 9989 | /* Reference Defines */ |
| AnnaBridge | 167:e84263d55307 | 9990 | #define EXTI_EMR_EM0 EXTI_EMR_MR0 |
| AnnaBridge | 167:e84263d55307 | 9991 | #define EXTI_EMR_EM1 EXTI_EMR_MR1 |
| AnnaBridge | 167:e84263d55307 | 9992 | #define EXTI_EMR_EM2 EXTI_EMR_MR2 |
| AnnaBridge | 167:e84263d55307 | 9993 | #define EXTI_EMR_EM3 EXTI_EMR_MR3 |
| AnnaBridge | 167:e84263d55307 | 9994 | #define EXTI_EMR_EM4 EXTI_EMR_MR4 |
| AnnaBridge | 167:e84263d55307 | 9995 | #define EXTI_EMR_EM5 EXTI_EMR_MR5 |
| AnnaBridge | 167:e84263d55307 | 9996 | #define EXTI_EMR_EM6 EXTI_EMR_MR6 |
| AnnaBridge | 167:e84263d55307 | 9997 | #define EXTI_EMR_EM7 EXTI_EMR_MR7 |
| AnnaBridge | 167:e84263d55307 | 9998 | #define EXTI_EMR_EM8 EXTI_EMR_MR8 |
| AnnaBridge | 167:e84263d55307 | 9999 | #define EXTI_EMR_EM9 EXTI_EMR_MR9 |
| AnnaBridge | 167:e84263d55307 | 10000 | #define EXTI_EMR_EM10 EXTI_EMR_MR10 |
| AnnaBridge | 167:e84263d55307 | 10001 | #define EXTI_EMR_EM11 EXTI_EMR_MR11 |
| AnnaBridge | 167:e84263d55307 | 10002 | #define EXTI_EMR_EM12 EXTI_EMR_MR12 |
| AnnaBridge | 167:e84263d55307 | 10003 | #define EXTI_EMR_EM13 EXTI_EMR_MR13 |
| AnnaBridge | 167:e84263d55307 | 10004 | #define EXTI_EMR_EM14 EXTI_EMR_MR14 |
| AnnaBridge | 167:e84263d55307 | 10005 | #define EXTI_EMR_EM15 EXTI_EMR_MR15 |
| AnnaBridge | 167:e84263d55307 | 10006 | #define EXTI_EMR_EM16 EXTI_EMR_MR16 |
| AnnaBridge | 167:e84263d55307 | 10007 | #define EXTI_EMR_EM17 EXTI_EMR_MR17 |
| AnnaBridge | 167:e84263d55307 | 10008 | #define EXTI_EMR_EM18 EXTI_EMR_MR18 |
| AnnaBridge | 167:e84263d55307 | 10009 | #define EXTI_EMR_EM19 EXTI_EMR_MR19 |
| AnnaBridge | 167:e84263d55307 | 10010 | #define EXTI_EMR_EM20 EXTI_EMR_MR20 |
| AnnaBridge | 167:e84263d55307 | 10011 | #define EXTI_EMR_EM21 EXTI_EMR_MR21 |
| AnnaBridge | 167:e84263d55307 | 10012 | #define EXTI_EMR_EM22 EXTI_EMR_MR22 |
| mbed_official | 19:112740acecfa | 10013 | |
| mbed_official | 19:112740acecfa | 10014 | /****************** Bit definition for EXTI_RTSR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 10015 | #define EXTI_RTSR_TR0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10016 | #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10017 | #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
| AnnaBridge | 167:e84263d55307 | 10018 | #define EXTI_RTSR_TR1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10019 | #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10020 | #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
| AnnaBridge | 167:e84263d55307 | 10021 | #define EXTI_RTSR_TR2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 10022 | #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10023 | #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
| AnnaBridge | 167:e84263d55307 | 10024 | #define EXTI_RTSR_TR3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 10025 | #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10026 | #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
| AnnaBridge | 167:e84263d55307 | 10027 | #define EXTI_RTSR_TR4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10028 | #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10029 | #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
| AnnaBridge | 167:e84263d55307 | 10030 | #define EXTI_RTSR_TR5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 10031 | #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10032 | #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
| AnnaBridge | 167:e84263d55307 | 10033 | #define EXTI_RTSR_TR6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 10034 | #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10035 | #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
| AnnaBridge | 167:e84263d55307 | 10036 | #define EXTI_RTSR_TR7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 10037 | #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10038 | #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
| AnnaBridge | 167:e84263d55307 | 10039 | #define EXTI_RTSR_TR8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10040 | #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10041 | #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
| AnnaBridge | 167:e84263d55307 | 10042 | #define EXTI_RTSR_TR9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 10043 | #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10044 | #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
| AnnaBridge | 167:e84263d55307 | 10045 | #define EXTI_RTSR_TR10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 10046 | #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10047 | #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
| AnnaBridge | 167:e84263d55307 | 10048 | #define EXTI_RTSR_TR11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 10049 | #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10050 | #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
| AnnaBridge | 167:e84263d55307 | 10051 | #define EXTI_RTSR_TR12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 10052 | #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10053 | #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
| AnnaBridge | 167:e84263d55307 | 10054 | #define EXTI_RTSR_TR13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 10055 | #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10056 | #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
| AnnaBridge | 167:e84263d55307 | 10057 | #define EXTI_RTSR_TR14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 10058 | #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10059 | #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
| AnnaBridge | 167:e84263d55307 | 10060 | #define EXTI_RTSR_TR15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 10061 | #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10062 | #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
| AnnaBridge | 167:e84263d55307 | 10063 | #define EXTI_RTSR_TR16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10064 | #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10065 | #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
| AnnaBridge | 167:e84263d55307 | 10066 | #define EXTI_RTSR_TR17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 10067 | #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10068 | #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ |
| AnnaBridge | 167:e84263d55307 | 10069 | #define EXTI_RTSR_TR18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 10070 | #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10071 | #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ |
| AnnaBridge | 167:e84263d55307 | 10072 | #define EXTI_RTSR_TR19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 10073 | #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10074 | #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ |
| AnnaBridge | 167:e84263d55307 | 10075 | #define EXTI_RTSR_TR20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 10076 | #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 10077 | #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ |
| AnnaBridge | 167:e84263d55307 | 10078 | #define EXTI_RTSR_TR21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 10079 | #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 10080 | #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ |
| AnnaBridge | 167:e84263d55307 | 10081 | #define EXTI_RTSR_TR22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 10082 | #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 10083 | #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ |
| mbed_official | 19:112740acecfa | 10084 | |
| mbed_official | 19:112740acecfa | 10085 | /****************** Bit definition for EXTI_FTSR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 10086 | #define EXTI_FTSR_TR0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10087 | #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10088 | #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
| AnnaBridge | 167:e84263d55307 | 10089 | #define EXTI_FTSR_TR1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10090 | #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10091 | #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
| AnnaBridge | 167:e84263d55307 | 10092 | #define EXTI_FTSR_TR2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 10093 | #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10094 | #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
| AnnaBridge | 167:e84263d55307 | 10095 | #define EXTI_FTSR_TR3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 10096 | #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10097 | #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
| AnnaBridge | 167:e84263d55307 | 10098 | #define EXTI_FTSR_TR4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10099 | #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10100 | #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
| AnnaBridge | 167:e84263d55307 | 10101 | #define EXTI_FTSR_TR5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 10102 | #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10103 | #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
| AnnaBridge | 167:e84263d55307 | 10104 | #define EXTI_FTSR_TR6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 10105 | #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10106 | #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
| AnnaBridge | 167:e84263d55307 | 10107 | #define EXTI_FTSR_TR7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 10108 | #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10109 | #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
| AnnaBridge | 167:e84263d55307 | 10110 | #define EXTI_FTSR_TR8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10111 | #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10112 | #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
| AnnaBridge | 167:e84263d55307 | 10113 | #define EXTI_FTSR_TR9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 10114 | #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10115 | #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
| AnnaBridge | 167:e84263d55307 | 10116 | #define EXTI_FTSR_TR10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 10117 | #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10118 | #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
| AnnaBridge | 167:e84263d55307 | 10119 | #define EXTI_FTSR_TR11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 10120 | #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10121 | #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
| AnnaBridge | 167:e84263d55307 | 10122 | #define EXTI_FTSR_TR12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 10123 | #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10124 | #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
| AnnaBridge | 167:e84263d55307 | 10125 | #define EXTI_FTSR_TR13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 10126 | #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10127 | #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
| AnnaBridge | 167:e84263d55307 | 10128 | #define EXTI_FTSR_TR14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 10129 | #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10130 | #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
| AnnaBridge | 167:e84263d55307 | 10131 | #define EXTI_FTSR_TR15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 10132 | #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10133 | #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
| AnnaBridge | 167:e84263d55307 | 10134 | #define EXTI_FTSR_TR16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10135 | #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10136 | #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
| AnnaBridge | 167:e84263d55307 | 10137 | #define EXTI_FTSR_TR17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 10138 | #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10139 | #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ |
| AnnaBridge | 167:e84263d55307 | 10140 | #define EXTI_FTSR_TR18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 10141 | #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10142 | #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ |
| AnnaBridge | 167:e84263d55307 | 10143 | #define EXTI_FTSR_TR19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 10144 | #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10145 | #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ |
| AnnaBridge | 167:e84263d55307 | 10146 | #define EXTI_FTSR_TR20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 10147 | #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 10148 | #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ |
| AnnaBridge | 167:e84263d55307 | 10149 | #define EXTI_FTSR_TR21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 10150 | #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 10151 | #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ |
| AnnaBridge | 167:e84263d55307 | 10152 | #define EXTI_FTSR_TR22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 10153 | #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 10154 | #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ |
| mbed_official | 19:112740acecfa | 10155 | |
| mbed_official | 19:112740acecfa | 10156 | /****************** Bit definition for EXTI_SWIER register ******************/ |
| AnnaBridge | 167:e84263d55307 | 10157 | #define EXTI_SWIER_SWIER0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10158 | #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10159 | #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ |
| AnnaBridge | 167:e84263d55307 | 10160 | #define EXTI_SWIER_SWIER1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10161 | #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10162 | #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ |
| AnnaBridge | 167:e84263d55307 | 10163 | #define EXTI_SWIER_SWIER2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 10164 | #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10165 | #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ |
| AnnaBridge | 167:e84263d55307 | 10166 | #define EXTI_SWIER_SWIER3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 10167 | #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10168 | #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ |
| AnnaBridge | 167:e84263d55307 | 10169 | #define EXTI_SWIER_SWIER4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10170 | #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10171 | #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ |
| AnnaBridge | 167:e84263d55307 | 10172 | #define EXTI_SWIER_SWIER5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 10173 | #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10174 | #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ |
| AnnaBridge | 167:e84263d55307 | 10175 | #define EXTI_SWIER_SWIER6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 10176 | #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10177 | #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ |
| AnnaBridge | 167:e84263d55307 | 10178 | #define EXTI_SWIER_SWIER7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 10179 | #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10180 | #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ |
| AnnaBridge | 167:e84263d55307 | 10181 | #define EXTI_SWIER_SWIER8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10182 | #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10183 | #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ |
| AnnaBridge | 167:e84263d55307 | 10184 | #define EXTI_SWIER_SWIER9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 10185 | #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10186 | #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ |
| AnnaBridge | 167:e84263d55307 | 10187 | #define EXTI_SWIER_SWIER10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 10188 | #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10189 | #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ |
| AnnaBridge | 167:e84263d55307 | 10190 | #define EXTI_SWIER_SWIER11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 10191 | #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10192 | #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ |
| AnnaBridge | 167:e84263d55307 | 10193 | #define EXTI_SWIER_SWIER12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 10194 | #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10195 | #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ |
| AnnaBridge | 167:e84263d55307 | 10196 | #define EXTI_SWIER_SWIER13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 10197 | #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10198 | #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ |
| AnnaBridge | 167:e84263d55307 | 10199 | #define EXTI_SWIER_SWIER14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 10200 | #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10201 | #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ |
| AnnaBridge | 167:e84263d55307 | 10202 | #define EXTI_SWIER_SWIER15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 10203 | #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10204 | #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ |
| AnnaBridge | 167:e84263d55307 | 10205 | #define EXTI_SWIER_SWIER16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10206 | #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10207 | #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ |
| AnnaBridge | 167:e84263d55307 | 10208 | #define EXTI_SWIER_SWIER17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 10209 | #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10210 | #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ |
| AnnaBridge | 167:e84263d55307 | 10211 | #define EXTI_SWIER_SWIER18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 10212 | #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10213 | #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ |
| AnnaBridge | 167:e84263d55307 | 10214 | #define EXTI_SWIER_SWIER19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 10215 | #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10216 | #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ |
| AnnaBridge | 167:e84263d55307 | 10217 | #define EXTI_SWIER_SWIER20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 10218 | #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 10219 | #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ |
| AnnaBridge | 167:e84263d55307 | 10220 | #define EXTI_SWIER_SWIER21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 10221 | #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 10222 | #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ |
| AnnaBridge | 167:e84263d55307 | 10223 | #define EXTI_SWIER_SWIER22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 10224 | #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 10225 | #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ |
| mbed_official | 19:112740acecfa | 10226 | |
| mbed_official | 19:112740acecfa | 10227 | /******************* Bit definition for EXTI_PR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 10228 | #define EXTI_PR_PR0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10229 | #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10230 | #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ |
| AnnaBridge | 167:e84263d55307 | 10231 | #define EXTI_PR_PR1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10232 | #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10233 | #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ |
| AnnaBridge | 167:e84263d55307 | 10234 | #define EXTI_PR_PR2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 10235 | #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10236 | #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ |
| AnnaBridge | 167:e84263d55307 | 10237 | #define EXTI_PR_PR3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 10238 | #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10239 | #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ |
| AnnaBridge | 167:e84263d55307 | 10240 | #define EXTI_PR_PR4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10241 | #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10242 | #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ |
| AnnaBridge | 167:e84263d55307 | 10243 | #define EXTI_PR_PR5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 10244 | #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10245 | #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ |
| AnnaBridge | 167:e84263d55307 | 10246 | #define EXTI_PR_PR6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 10247 | #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10248 | #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ |
| AnnaBridge | 167:e84263d55307 | 10249 | #define EXTI_PR_PR7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 10250 | #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10251 | #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ |
| AnnaBridge | 167:e84263d55307 | 10252 | #define EXTI_PR_PR8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10253 | #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10254 | #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ |
| AnnaBridge | 167:e84263d55307 | 10255 | #define EXTI_PR_PR9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 10256 | #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10257 | #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ |
| AnnaBridge | 167:e84263d55307 | 10258 | #define EXTI_PR_PR10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 10259 | #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10260 | #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ |
| AnnaBridge | 167:e84263d55307 | 10261 | #define EXTI_PR_PR11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 10262 | #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10263 | #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ |
| AnnaBridge | 167:e84263d55307 | 10264 | #define EXTI_PR_PR12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 10265 | #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10266 | #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ |
| AnnaBridge | 167:e84263d55307 | 10267 | #define EXTI_PR_PR13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 10268 | #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10269 | #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ |
| AnnaBridge | 167:e84263d55307 | 10270 | #define EXTI_PR_PR14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 10271 | #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10272 | #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ |
| AnnaBridge | 167:e84263d55307 | 10273 | #define EXTI_PR_PR15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 10274 | #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10275 | #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ |
| AnnaBridge | 167:e84263d55307 | 10276 | #define EXTI_PR_PR16_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10277 | #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10278 | #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ |
| AnnaBridge | 167:e84263d55307 | 10279 | #define EXTI_PR_PR17_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 10280 | #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10281 | #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ |
| AnnaBridge | 167:e84263d55307 | 10282 | #define EXTI_PR_PR18_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 10283 | #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10284 | #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ |
| AnnaBridge | 167:e84263d55307 | 10285 | #define EXTI_PR_PR19_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 10286 | #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10287 | #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ |
| AnnaBridge | 167:e84263d55307 | 10288 | #define EXTI_PR_PR20_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 10289 | #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 10290 | #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ |
| AnnaBridge | 167:e84263d55307 | 10291 | #define EXTI_PR_PR21_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 10292 | #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 10293 | #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ |
| AnnaBridge | 167:e84263d55307 | 10294 | #define EXTI_PR_PR22_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 10295 | #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 10296 | #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ |
| mbed_official | 19:112740acecfa | 10297 | |
| mbed_official | 19:112740acecfa | 10298 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 10299 | /* */ |
| mbed_official | 19:112740acecfa | 10300 | /* FLASH */ |
| mbed_official | 19:112740acecfa | 10301 | /* */ |
| mbed_official | 19:112740acecfa | 10302 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 10303 | /******************* Bits definition for FLASH_ACR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 10304 | #define FLASH_ACR_LATENCY_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10305 | #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 10306 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk |
| AnnaBridge | 167:e84263d55307 | 10307 | #define FLASH_ACR_LATENCY_0WS 0x00000000U |
| AnnaBridge | 167:e84263d55307 | 10308 | #define FLASH_ACR_LATENCY_1WS 0x00000001U |
| AnnaBridge | 167:e84263d55307 | 10309 | #define FLASH_ACR_LATENCY_2WS 0x00000002U |
| AnnaBridge | 167:e84263d55307 | 10310 | #define FLASH_ACR_LATENCY_3WS 0x00000003U |
| AnnaBridge | 167:e84263d55307 | 10311 | #define FLASH_ACR_LATENCY_4WS 0x00000004U |
| AnnaBridge | 167:e84263d55307 | 10312 | #define FLASH_ACR_LATENCY_5WS 0x00000005U |
| AnnaBridge | 167:e84263d55307 | 10313 | #define FLASH_ACR_LATENCY_6WS 0x00000006U |
| AnnaBridge | 167:e84263d55307 | 10314 | #define FLASH_ACR_LATENCY_7WS 0x00000007U |
| AnnaBridge | 167:e84263d55307 | 10315 | |
| AnnaBridge | 167:e84263d55307 | 10316 | #define FLASH_ACR_LATENCY_8WS 0x00000008U |
| AnnaBridge | 167:e84263d55307 | 10317 | #define FLASH_ACR_LATENCY_9WS 0x00000009U |
| AnnaBridge | 167:e84263d55307 | 10318 | #define FLASH_ACR_LATENCY_10WS 0x0000000AU |
| AnnaBridge | 167:e84263d55307 | 10319 | #define FLASH_ACR_LATENCY_11WS 0x0000000BU |
| AnnaBridge | 167:e84263d55307 | 10320 | #define FLASH_ACR_LATENCY_12WS 0x0000000CU |
| AnnaBridge | 167:e84263d55307 | 10321 | #define FLASH_ACR_LATENCY_13WS 0x0000000DU |
| AnnaBridge | 167:e84263d55307 | 10322 | #define FLASH_ACR_LATENCY_14WS 0x0000000EU |
| AnnaBridge | 167:e84263d55307 | 10323 | #define FLASH_ACR_LATENCY_15WS 0x0000000FU |
| AnnaBridge | 167:e84263d55307 | 10324 | #define FLASH_ACR_PRFTEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10325 | #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10326 | #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk |
| AnnaBridge | 167:e84263d55307 | 10327 | #define FLASH_ACR_ICEN_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 10328 | #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10329 | #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk |
| AnnaBridge | 167:e84263d55307 | 10330 | #define FLASH_ACR_DCEN_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 10331 | #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10332 | #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk |
| AnnaBridge | 167:e84263d55307 | 10333 | #define FLASH_ACR_ICRST_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 10334 | #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10335 | #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk |
| AnnaBridge | 167:e84263d55307 | 10336 | #define FLASH_ACR_DCRST_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 10337 | #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10338 | #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk |
| AnnaBridge | 167:e84263d55307 | 10339 | #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 10340 | #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */ |
| AnnaBridge | 167:e84263d55307 | 10341 | #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk |
| AnnaBridge | 167:e84263d55307 | 10342 | #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10343 | #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */ |
| AnnaBridge | 167:e84263d55307 | 10344 | #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk |
| mbed_official | 19:112740acecfa | 10345 | |
| mbed_official | 19:112740acecfa | 10346 | /******************* Bits definition for FLASH_SR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 10347 | #define FLASH_SR_EOP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10348 | #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10349 | #define FLASH_SR_EOP FLASH_SR_EOP_Msk |
| AnnaBridge | 167:e84263d55307 | 10350 | #define FLASH_SR_SOP_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10351 | #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10352 | #define FLASH_SR_SOP FLASH_SR_SOP_Msk |
| AnnaBridge | 167:e84263d55307 | 10353 | #define FLASH_SR_WRPERR_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10354 | #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10355 | #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk |
| AnnaBridge | 167:e84263d55307 | 10356 | #define FLASH_SR_PGAERR_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 10357 | #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10358 | #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk |
| AnnaBridge | 167:e84263d55307 | 10359 | #define FLASH_SR_PGPERR_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 10360 | #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10361 | #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk |
| AnnaBridge | 167:e84263d55307 | 10362 | #define FLASH_SR_PGSERR_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 10363 | #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10364 | #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk |
| AnnaBridge | 167:e84263d55307 | 10365 | #define FLASH_SR_RDERR_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10366 | #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10367 | #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk |
| AnnaBridge | 167:e84263d55307 | 10368 | #define FLASH_SR_BSY_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10369 | #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10370 | #define FLASH_SR_BSY FLASH_SR_BSY_Msk |
| mbed_official | 19:112740acecfa | 10371 | |
| mbed_official | 19:112740acecfa | 10372 | /******************* Bits definition for FLASH_CR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 10373 | #define FLASH_CR_PG_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10374 | #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10375 | #define FLASH_CR_PG FLASH_CR_PG_Msk |
| AnnaBridge | 167:e84263d55307 | 10376 | #define FLASH_CR_SER_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10377 | #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10378 | #define FLASH_CR_SER FLASH_CR_SER_Msk |
| AnnaBridge | 167:e84263d55307 | 10379 | #define FLASH_CR_MER_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 10380 | #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10381 | #define FLASH_CR_MER FLASH_CR_MER_Msk |
| mbed_official | 19:112740acecfa | 10382 | #define FLASH_CR_MER1 FLASH_CR_MER |
| AnnaBridge | 167:e84263d55307 | 10383 | #define FLASH_CR_SNB_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 10384 | #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */ |
| AnnaBridge | 167:e84263d55307 | 10385 | #define FLASH_CR_SNB FLASH_CR_SNB_Msk |
| AnnaBridge | 167:e84263d55307 | 10386 | #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10387 | #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10388 | #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10389 | #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10390 | #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10391 | #define FLASH_CR_PSIZE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10392 | #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 10393 | #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk |
| AnnaBridge | 167:e84263d55307 | 10394 | #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10395 | #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10396 | #define FLASH_CR_MER2_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 10397 | #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10398 | #define FLASH_CR_MER2 FLASH_CR_MER2_Msk |
| AnnaBridge | 167:e84263d55307 | 10399 | #define FLASH_CR_STRT_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10400 | #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10401 | #define FLASH_CR_STRT FLASH_CR_STRT_Msk |
| AnnaBridge | 167:e84263d55307 | 10402 | #define FLASH_CR_EOPIE_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 10403 | #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 10404 | #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk |
| AnnaBridge | 167:e84263d55307 | 10405 | #define FLASH_CR_LOCK_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 10406 | #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 10407 | #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk |
| mbed_official | 19:112740acecfa | 10408 | |
| mbed_official | 19:112740acecfa | 10409 | /******************* Bits definition for FLASH_OPTCR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 10410 | #define FLASH_OPTCR_OPTLOCK_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10411 | #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10412 | #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk |
| AnnaBridge | 167:e84263d55307 | 10413 | #define FLASH_OPTCR_OPTSTRT_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10414 | #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10415 | #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk |
| AnnaBridge | 167:e84263d55307 | 10416 | |
| AnnaBridge | 167:e84263d55307 | 10417 | #define FLASH_OPTCR_BOR_LEV_0 0x00000004U |
| AnnaBridge | 167:e84263d55307 | 10418 | #define FLASH_OPTCR_BOR_LEV_1 0x00000008U |
| AnnaBridge | 167:e84263d55307 | 10419 | #define FLASH_OPTCR_BOR_LEV_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 10420 | #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 10421 | #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk |
| AnnaBridge | 167:e84263d55307 | 10422 | #define FLASH_OPTCR_BFB2_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10423 | #define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10424 | #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk |
| AnnaBridge | 167:e84263d55307 | 10425 | #define FLASH_OPTCR_WDG_SW_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 10426 | #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10427 | #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk |
| AnnaBridge | 167:e84263d55307 | 10428 | #define FLASH_OPTCR_nRST_STOP_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 10429 | #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10430 | #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 10431 | #define FLASH_OPTCR_nRST_STDBY_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 10432 | #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10433 | #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk |
| AnnaBridge | 167:e84263d55307 | 10434 | #define FLASH_OPTCR_RDP_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10435 | #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 10436 | #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk |
| AnnaBridge | 167:e84263d55307 | 10437 | #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10438 | #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10439 | #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10440 | #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10441 | #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10442 | #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10443 | #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10444 | #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10445 | #define FLASH_OPTCR_nWRP_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10446 | #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 10447 | #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk |
| AnnaBridge | 167:e84263d55307 | 10448 | #define FLASH_OPTCR_nWRP_0 0x00010000U |
| AnnaBridge | 167:e84263d55307 | 10449 | #define FLASH_OPTCR_nWRP_1 0x00020000U |
| AnnaBridge | 167:e84263d55307 | 10450 | #define FLASH_OPTCR_nWRP_2 0x00040000U |
| AnnaBridge | 167:e84263d55307 | 10451 | #define FLASH_OPTCR_nWRP_3 0x00080000U |
| AnnaBridge | 167:e84263d55307 | 10452 | #define FLASH_OPTCR_nWRP_4 0x00100000U |
| AnnaBridge | 167:e84263d55307 | 10453 | #define FLASH_OPTCR_nWRP_5 0x00200000U |
| AnnaBridge | 167:e84263d55307 | 10454 | #define FLASH_OPTCR_nWRP_6 0x00400000U |
| AnnaBridge | 167:e84263d55307 | 10455 | #define FLASH_OPTCR_nWRP_7 0x00800000U |
| AnnaBridge | 167:e84263d55307 | 10456 | #define FLASH_OPTCR_nWRP_8 0x01000000U |
| AnnaBridge | 167:e84263d55307 | 10457 | #define FLASH_OPTCR_nWRP_9 0x02000000U |
| AnnaBridge | 167:e84263d55307 | 10458 | #define FLASH_OPTCR_nWRP_10 0x04000000U |
| AnnaBridge | 167:e84263d55307 | 10459 | #define FLASH_OPTCR_nWRP_11 0x08000000U |
| AnnaBridge | 167:e84263d55307 | 10460 | #define FLASH_OPTCR_DB1M_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 10461 | #define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 10462 | #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk |
| AnnaBridge | 167:e84263d55307 | 10463 | #define FLASH_OPTCR_SPRMOD_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 10464 | #define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 10465 | #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk |
| mbed_official | 19:112740acecfa | 10466 | |
| mbed_official | 19:112740acecfa | 10467 | /****************** Bits definition for FLASH_OPTCR1 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 10468 | #define FLASH_OPTCR1_nWRP_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10469 | #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 10470 | #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk |
| AnnaBridge | 167:e84263d55307 | 10471 | #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10472 | #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10473 | #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10474 | #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10475 | #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 10476 | #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 10477 | #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 10478 | #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 10479 | #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 10480 | #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 10481 | #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 10482 | #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */ |
| mbed_official | 19:112740acecfa | 10483 | |
| mbed_official | 19:112740acecfa | 10484 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 10485 | /* */ |
| mbed_official | 19:112740acecfa | 10486 | /* Flexible Memory Controller */ |
| mbed_official | 19:112740acecfa | 10487 | /* */ |
| mbed_official | 19:112740acecfa | 10488 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 10489 | /****************** Bit definition for FMC_BCR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 10490 | #define FMC_BCR1_MBKEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10491 | #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10492 | #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10493 | #define FMC_BCR1_MUXEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10494 | #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10495 | #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10496 | |
| AnnaBridge | 167:e84263d55307 | 10497 | #define FMC_BCR1_MTYP_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 10498 | #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 10499 | #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ |
| AnnaBridge | 167:e84263d55307 | 10500 | #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10501 | #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10502 | |
| AnnaBridge | 167:e84263d55307 | 10503 | #define FMC_BCR1_MWID_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10504 | #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 10505 | #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ |
| AnnaBridge | 167:e84263d55307 | 10506 | #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10507 | #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10508 | |
| AnnaBridge | 167:e84263d55307 | 10509 | #define FMC_BCR1_FACCEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 10510 | #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10511 | #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */ |
| AnnaBridge | 167:e84263d55307 | 10512 | #define FMC_BCR1_BURSTEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10513 | #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10514 | #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10515 | #define FMC_BCR1_WAITPOL_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 10516 | #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10517 | #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */ |
| AnnaBridge | 167:e84263d55307 | 10518 | #define FMC_BCR1_WAITCFG_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 10519 | #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10520 | #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */ |
| AnnaBridge | 167:e84263d55307 | 10521 | #define FMC_BCR1_WREN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 10522 | #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10523 | #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10524 | #define FMC_BCR1_WAITEN_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 10525 | #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10526 | #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10527 | #define FMC_BCR1_EXTMOD_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 10528 | #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10529 | #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */ |
| AnnaBridge | 167:e84263d55307 | 10530 | #define FMC_BCR1_ASYNCWAIT_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 10531 | #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10532 | #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */ |
| AnnaBridge | 167:e84263d55307 | 10533 | #define FMC_BCR1_CPSIZE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10534 | #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 167:e84263d55307 | 10535 | #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */ |
| AnnaBridge | 167:e84263d55307 | 10536 | #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10537 | #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10538 | #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10539 | #define FMC_BCR1_CBURSTRW_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 10540 | #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10541 | #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */ |
| AnnaBridge | 167:e84263d55307 | 10542 | #define FMC_BCR1_CCLKEN_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 10543 | #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 10544 | #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */ |
| AnnaBridge | 167:e84263d55307 | 10545 | #define FMC_BCR1_WFDIS_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 10546 | #define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 10547 | #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */ |
| mbed_official | 19:112740acecfa | 10548 | |
| mbed_official | 19:112740acecfa | 10549 | /****************** Bit definition for FMC_BCR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 10550 | #define FMC_BCR2_MBKEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10551 | #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10552 | #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10553 | #define FMC_BCR2_MUXEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10554 | #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10555 | #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10556 | |
| AnnaBridge | 167:e84263d55307 | 10557 | #define FMC_BCR2_MTYP_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 10558 | #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 10559 | #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ |
| AnnaBridge | 167:e84263d55307 | 10560 | #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10561 | #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10562 | |
| AnnaBridge | 167:e84263d55307 | 10563 | #define FMC_BCR2_MWID_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10564 | #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 10565 | #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ |
| AnnaBridge | 167:e84263d55307 | 10566 | #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10567 | #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10568 | |
| AnnaBridge | 167:e84263d55307 | 10569 | #define FMC_BCR2_FACCEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 10570 | #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10571 | #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */ |
| AnnaBridge | 167:e84263d55307 | 10572 | #define FMC_BCR2_BURSTEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10573 | #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10574 | #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10575 | #define FMC_BCR2_WAITPOL_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 10576 | #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10577 | #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */ |
| AnnaBridge | 167:e84263d55307 | 10578 | #define FMC_BCR2_WAITCFG_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 10579 | #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10580 | #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */ |
| AnnaBridge | 167:e84263d55307 | 10581 | #define FMC_BCR2_WREN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 10582 | #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10583 | #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10584 | #define FMC_BCR2_WAITEN_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 10585 | #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10586 | #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10587 | #define FMC_BCR2_EXTMOD_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 10588 | #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10589 | #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */ |
| AnnaBridge | 167:e84263d55307 | 10590 | #define FMC_BCR2_ASYNCWAIT_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 10591 | #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10592 | #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */ |
| AnnaBridge | 167:e84263d55307 | 10593 | #define FMC_BCR2_CBURSTRW_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 10594 | #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10595 | #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */ |
| mbed_official | 19:112740acecfa | 10596 | |
| mbed_official | 19:112740acecfa | 10597 | /****************** Bit definition for FMC_BCR3 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 10598 | #define FMC_BCR3_MBKEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10599 | #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10600 | #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10601 | #define FMC_BCR3_MUXEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10602 | #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10603 | #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10604 | |
| AnnaBridge | 167:e84263d55307 | 10605 | #define FMC_BCR3_MTYP_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 10606 | #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 10607 | #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ |
| AnnaBridge | 167:e84263d55307 | 10608 | #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10609 | #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10610 | |
| AnnaBridge | 167:e84263d55307 | 10611 | #define FMC_BCR3_MWID_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10612 | #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 10613 | #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ |
| AnnaBridge | 167:e84263d55307 | 10614 | #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10615 | #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10616 | |
| AnnaBridge | 167:e84263d55307 | 10617 | #define FMC_BCR3_FACCEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 10618 | #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10619 | #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */ |
| AnnaBridge | 167:e84263d55307 | 10620 | #define FMC_BCR3_BURSTEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10621 | #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10622 | #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10623 | #define FMC_BCR3_WAITPOL_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 10624 | #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10625 | #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */ |
| AnnaBridge | 167:e84263d55307 | 10626 | #define FMC_BCR3_WAITCFG_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 10627 | #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10628 | #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */ |
| AnnaBridge | 167:e84263d55307 | 10629 | #define FMC_BCR3_WREN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 10630 | #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10631 | #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10632 | #define FMC_BCR3_WAITEN_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 10633 | #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10634 | #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10635 | #define FMC_BCR3_EXTMOD_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 10636 | #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10637 | #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */ |
| AnnaBridge | 167:e84263d55307 | 10638 | #define FMC_BCR3_ASYNCWAIT_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 10639 | #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10640 | #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */ |
| AnnaBridge | 167:e84263d55307 | 10641 | #define FMC_BCR3_CBURSTRW_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 10642 | #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10643 | #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */ |
| mbed_official | 19:112740acecfa | 10644 | |
| mbed_official | 19:112740acecfa | 10645 | /****************** Bit definition for FMC_BCR4 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 10646 | #define FMC_BCR4_MBKEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10647 | #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10648 | #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10649 | #define FMC_BCR4_MUXEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 10650 | #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10651 | #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10652 | |
| AnnaBridge | 167:e84263d55307 | 10653 | #define FMC_BCR4_MTYP_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 10654 | #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 10655 | #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ |
| AnnaBridge | 167:e84263d55307 | 10656 | #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10657 | #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10658 | |
| AnnaBridge | 167:e84263d55307 | 10659 | #define FMC_BCR4_MWID_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10660 | #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 10661 | #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ |
| AnnaBridge | 167:e84263d55307 | 10662 | #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10663 | #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10664 | |
| AnnaBridge | 167:e84263d55307 | 10665 | #define FMC_BCR4_FACCEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 10666 | #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10667 | #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */ |
| AnnaBridge | 167:e84263d55307 | 10668 | #define FMC_BCR4_BURSTEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10669 | #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10670 | #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10671 | #define FMC_BCR4_WAITPOL_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 10672 | #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10673 | #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */ |
| AnnaBridge | 167:e84263d55307 | 10674 | #define FMC_BCR4_WAITCFG_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 10675 | #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10676 | #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */ |
| AnnaBridge | 167:e84263d55307 | 10677 | #define FMC_BCR4_WREN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 10678 | #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10679 | #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10680 | #define FMC_BCR4_WAITEN_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 10681 | #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10682 | #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */ |
| AnnaBridge | 167:e84263d55307 | 10683 | #define FMC_BCR4_EXTMOD_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 10684 | #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10685 | #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */ |
| AnnaBridge | 167:e84263d55307 | 10686 | #define FMC_BCR4_ASYNCWAIT_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 10687 | #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10688 | #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */ |
| AnnaBridge | 167:e84263d55307 | 10689 | #define FMC_BCR4_CBURSTRW_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 10690 | #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10691 | #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */ |
| mbed_official | 19:112740acecfa | 10692 | |
| mbed_official | 19:112740acecfa | 10693 | /****************** Bit definition for FMC_BTR1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 10694 | #define FMC_BTR1_ADDSET_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10695 | #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 10696 | #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10697 | #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10698 | #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10699 | #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10700 | #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10701 | |
| AnnaBridge | 167:e84263d55307 | 10702 | #define FMC_BTR1_ADDHLD_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10703 | #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 10704 | #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10705 | #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10706 | #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10707 | #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10708 | #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10709 | |
| AnnaBridge | 167:e84263d55307 | 10710 | #define FMC_BTR1_DATAST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10711 | #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 10712 | #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10713 | #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10714 | #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10715 | #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10716 | #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10717 | #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10718 | #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10719 | #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10720 | #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10721 | |
| AnnaBridge | 167:e84263d55307 | 10722 | #define FMC_BTR1_BUSTURN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10723 | #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 10724 | #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10725 | #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10726 | #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10727 | #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10728 | #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10729 | |
| AnnaBridge | 167:e84263d55307 | 10730 | #define FMC_BTR1_CLKDIV_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 10731 | #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 10732 | #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| AnnaBridge | 167:e84263d55307 | 10733 | #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 10734 | #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 10735 | #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 10736 | #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 10737 | |
| AnnaBridge | 167:e84263d55307 | 10738 | #define FMC_BTR1_DATLAT_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 10739 | #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 10740 | #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ |
| AnnaBridge | 167:e84263d55307 | 10741 | #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 10742 | #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 10743 | #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 10744 | #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 10745 | |
| AnnaBridge | 167:e84263d55307 | 10746 | #define FMC_BTR1_ACCMOD_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 10747 | #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 10748 | #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ |
| AnnaBridge | 167:e84263d55307 | 10749 | #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 10750 | #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 10751 | |
| mbed_official | 19:112740acecfa | 10752 | /****************** Bit definition for FMC_BTR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 10753 | #define FMC_BTR2_ADDSET_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10754 | #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 10755 | #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10756 | #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10757 | #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10758 | #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10759 | #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10760 | |
| AnnaBridge | 167:e84263d55307 | 10761 | #define FMC_BTR2_ADDHLD_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10762 | #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 10763 | #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10764 | #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10765 | #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10766 | #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10767 | #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10768 | |
| AnnaBridge | 167:e84263d55307 | 10769 | #define FMC_BTR2_DATAST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10770 | #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 10771 | #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10772 | #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10773 | #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10774 | #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10775 | #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10776 | #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10777 | #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10778 | #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10779 | #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10780 | |
| AnnaBridge | 167:e84263d55307 | 10781 | #define FMC_BTR2_BUSTURN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10782 | #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 10783 | #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10784 | #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10785 | #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10786 | #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10787 | #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10788 | |
| AnnaBridge | 167:e84263d55307 | 10789 | #define FMC_BTR2_CLKDIV_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 10790 | #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 10791 | #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| AnnaBridge | 167:e84263d55307 | 10792 | #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 10793 | #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 10794 | #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 10795 | #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 10796 | |
| AnnaBridge | 167:e84263d55307 | 10797 | #define FMC_BTR2_DATLAT_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 10798 | #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 10799 | #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ |
| AnnaBridge | 167:e84263d55307 | 10800 | #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 10801 | #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 10802 | #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 10803 | #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 10804 | |
| AnnaBridge | 167:e84263d55307 | 10805 | #define FMC_BTR2_ACCMOD_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 10806 | #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 10807 | #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ |
| AnnaBridge | 167:e84263d55307 | 10808 | #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 10809 | #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 10810 | |
| mbed_official | 19:112740acecfa | 10811 | /******************* Bit definition for FMC_BTR3 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 10812 | #define FMC_BTR3_ADDSET_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10813 | #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 10814 | #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10815 | #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10816 | #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10817 | #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10818 | #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10819 | |
| AnnaBridge | 167:e84263d55307 | 10820 | #define FMC_BTR3_ADDHLD_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10821 | #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 10822 | #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10823 | #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10824 | #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10825 | #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10826 | #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10827 | |
| AnnaBridge | 167:e84263d55307 | 10828 | #define FMC_BTR3_DATAST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10829 | #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 10830 | #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10831 | #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10832 | #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10833 | #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10834 | #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10835 | #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10836 | #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10837 | #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10838 | #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10839 | |
| AnnaBridge | 167:e84263d55307 | 10840 | #define FMC_BTR3_BUSTURN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10841 | #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 10842 | #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10843 | #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10844 | #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10845 | #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10846 | #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10847 | |
| AnnaBridge | 167:e84263d55307 | 10848 | #define FMC_BTR3_CLKDIV_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 10849 | #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 10850 | #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| AnnaBridge | 167:e84263d55307 | 10851 | #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 10852 | #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 10853 | #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 10854 | #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 10855 | |
| AnnaBridge | 167:e84263d55307 | 10856 | #define FMC_BTR3_DATLAT_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 10857 | #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 10858 | #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ |
| AnnaBridge | 167:e84263d55307 | 10859 | #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 10860 | #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 10861 | #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 10862 | #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 10863 | |
| AnnaBridge | 167:e84263d55307 | 10864 | #define FMC_BTR3_ACCMOD_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 10865 | #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 10866 | #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ |
| AnnaBridge | 167:e84263d55307 | 10867 | #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 10868 | #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 10869 | |
| mbed_official | 19:112740acecfa | 10870 | /****************** Bit definition for FMC_BTR4 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 10871 | #define FMC_BTR4_ADDSET_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10872 | #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 10873 | #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10874 | #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10875 | #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10876 | #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10877 | #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10878 | |
| AnnaBridge | 167:e84263d55307 | 10879 | #define FMC_BTR4_ADDHLD_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10880 | #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 10881 | #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10882 | #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10883 | #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10884 | #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10885 | #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10886 | |
| AnnaBridge | 167:e84263d55307 | 10887 | #define FMC_BTR4_DATAST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10888 | #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 10889 | #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10890 | #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10891 | #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10892 | #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10893 | #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10894 | #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10895 | #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10896 | #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10897 | #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10898 | |
| AnnaBridge | 167:e84263d55307 | 10899 | #define FMC_BTR4_BUSTURN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10900 | #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 10901 | #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10902 | #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10903 | #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10904 | #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10905 | #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10906 | |
| AnnaBridge | 167:e84263d55307 | 10907 | #define FMC_BTR4_CLKDIV_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 10908 | #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 10909 | #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| AnnaBridge | 167:e84263d55307 | 10910 | #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 10911 | #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 10912 | #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 10913 | #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 10914 | |
| AnnaBridge | 167:e84263d55307 | 10915 | #define FMC_BTR4_DATLAT_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 10916 | #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 10917 | #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ |
| AnnaBridge | 167:e84263d55307 | 10918 | #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 10919 | #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 10920 | #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 10921 | #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 10922 | |
| AnnaBridge | 167:e84263d55307 | 10923 | #define FMC_BTR4_ACCMOD_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 10924 | #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 10925 | #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ |
| AnnaBridge | 167:e84263d55307 | 10926 | #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 10927 | #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 10928 | |
| mbed_official | 19:112740acecfa | 10929 | /****************** Bit definition for FMC_BWTR1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 10930 | #define FMC_BWTR1_ADDSET_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10931 | #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 10932 | #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10933 | #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10934 | #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10935 | #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10936 | #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10937 | |
| AnnaBridge | 167:e84263d55307 | 10938 | #define FMC_BWTR1_ADDHLD_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10939 | #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 10940 | #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10941 | #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10942 | #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10943 | #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10944 | #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10945 | |
| AnnaBridge | 167:e84263d55307 | 10946 | #define FMC_BWTR1_DATAST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10947 | #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 10948 | #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10949 | #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10950 | #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10951 | #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10952 | #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10953 | #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10954 | #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10955 | #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10956 | #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 10957 | |
| AnnaBridge | 167:e84263d55307 | 10958 | #define FMC_BWTR1_BUSTURN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 10959 | #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 10960 | #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ |
| AnnaBridge | 167:e84263d55307 | 10961 | #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 10962 | #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 10963 | #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 10964 | #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 10965 | |
| AnnaBridge | 167:e84263d55307 | 10966 | #define FMC_BWTR1_ACCMOD_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 10967 | #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 10968 | #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ |
| AnnaBridge | 167:e84263d55307 | 10969 | #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 10970 | #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 10971 | |
| mbed_official | 19:112740acecfa | 10972 | /****************** Bit definition for FMC_BWTR2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 10973 | #define FMC_BWTR2_ADDSET_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 10974 | #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 10975 | #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10976 | #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 10977 | #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 10978 | #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 10979 | #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 10980 | |
| AnnaBridge | 167:e84263d55307 | 10981 | #define FMC_BWTR2_ADDHLD_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 10982 | #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 10983 | #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10984 | #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 10985 | #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 10986 | #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 10987 | #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 10988 | |
| AnnaBridge | 167:e84263d55307 | 10989 | #define FMC_BWTR2_DATAST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 10990 | #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 10991 | #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 10992 | #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 10993 | #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 10994 | #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 10995 | #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 10996 | #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 10997 | #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 10998 | #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 10999 | #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11000 | |
| AnnaBridge | 167:e84263d55307 | 11001 | #define FMC_BWTR2_BUSTURN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11002 | #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 11003 | #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ |
| AnnaBridge | 167:e84263d55307 | 11004 | #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11005 | #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11006 | #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11007 | #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 11008 | |
| AnnaBridge | 167:e84263d55307 | 11009 | #define FMC_BWTR2_ACCMOD_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 11010 | #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 11011 | #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ |
| AnnaBridge | 167:e84263d55307 | 11012 | #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 11013 | #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 11014 | |
| mbed_official | 19:112740acecfa | 11015 | /****************** Bit definition for FMC_BWTR3 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11016 | #define FMC_BWTR3_ADDSET_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11017 | #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 11018 | #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 11019 | #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11020 | #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11021 | #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11022 | #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11023 | |
| AnnaBridge | 167:e84263d55307 | 11024 | #define FMC_BWTR3_ADDHLD_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11025 | #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 11026 | #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 11027 | #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11028 | #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11029 | #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11030 | #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11031 | |
| AnnaBridge | 167:e84263d55307 | 11032 | #define FMC_BWTR3_DATAST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11033 | #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 11034 | #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 11035 | #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11036 | #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11037 | #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11038 | #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11039 | #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11040 | #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11041 | #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11042 | #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11043 | |
| AnnaBridge | 167:e84263d55307 | 11044 | #define FMC_BWTR3_BUSTURN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11045 | #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 11046 | #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ |
| AnnaBridge | 167:e84263d55307 | 11047 | #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11048 | #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11049 | #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11050 | #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 11051 | |
| AnnaBridge | 167:e84263d55307 | 11052 | #define FMC_BWTR3_ACCMOD_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 11053 | #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 11054 | #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ |
| AnnaBridge | 167:e84263d55307 | 11055 | #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 11056 | #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 11057 | |
| mbed_official | 19:112740acecfa | 11058 | /****************** Bit definition for FMC_BWTR4 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11059 | #define FMC_BWTR4_ADDSET_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11060 | #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 11061 | #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 11062 | #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11063 | #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11064 | #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11065 | #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11066 | |
| AnnaBridge | 167:e84263d55307 | 11067 | #define FMC_BWTR4_ADDHLD_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11068 | #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 11069 | #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 11070 | #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11071 | #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11072 | #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11073 | #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11074 | |
| AnnaBridge | 167:e84263d55307 | 11075 | #define FMC_BWTR4_DATAST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11076 | #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 11077 | #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ |
| AnnaBridge | 167:e84263d55307 | 11078 | #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11079 | #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11080 | #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11081 | #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11082 | #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11083 | #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11084 | #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11085 | #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11086 | |
| AnnaBridge | 167:e84263d55307 | 11087 | #define FMC_BWTR4_BUSTURN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11088 | #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 11089 | #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ |
| AnnaBridge | 167:e84263d55307 | 11090 | #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11091 | #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11092 | #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11093 | #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 11094 | |
| AnnaBridge | 167:e84263d55307 | 11095 | #define FMC_BWTR4_ACCMOD_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 11096 | #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 11097 | #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ |
| AnnaBridge | 167:e84263d55307 | 11098 | #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 11099 | #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */ |
| mbed_official | 19:112740acecfa | 11100 | |
| mbed_official | 19:112740acecfa | 11101 | /****************** Bit definition for FMC_PCR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 11102 | #define FMC_PCR_PWAITEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 11103 | #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11104 | #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */ |
| AnnaBridge | 167:e84263d55307 | 11105 | #define FMC_PCR_PBKEN_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 11106 | #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11107 | #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */ |
| AnnaBridge | 167:e84263d55307 | 11108 | #define FMC_PCR_PTYP_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 11109 | #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11110 | #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */ |
| AnnaBridge | 167:e84263d55307 | 11111 | |
| AnnaBridge | 167:e84263d55307 | 11112 | #define FMC_PCR_PWID_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11113 | #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 11114 | #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */ |
| AnnaBridge | 167:e84263d55307 | 11115 | #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11116 | #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11117 | |
| AnnaBridge | 167:e84263d55307 | 11118 | #define FMC_PCR_ECCEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 11119 | #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11120 | #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */ |
| AnnaBridge | 167:e84263d55307 | 11121 | |
| AnnaBridge | 167:e84263d55307 | 11122 | #define FMC_PCR_TCLR_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 11123 | #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */ |
| AnnaBridge | 167:e84263d55307 | 11124 | #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */ |
| AnnaBridge | 167:e84263d55307 | 11125 | #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11126 | #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11127 | #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11128 | #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11129 | |
| AnnaBridge | 167:e84263d55307 | 11130 | #define FMC_PCR_TAR_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 11131 | #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */ |
| AnnaBridge | 167:e84263d55307 | 11132 | #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */ |
| AnnaBridge | 167:e84263d55307 | 11133 | #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11134 | #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11135 | #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11136 | #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11137 | |
| AnnaBridge | 167:e84263d55307 | 11138 | #define FMC_PCR_ECCPS_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 11139 | #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */ |
| AnnaBridge | 167:e84263d55307 | 11140 | #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */ |
| AnnaBridge | 167:e84263d55307 | 11141 | #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11142 | #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11143 | #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */ |
| mbed_official | 19:112740acecfa | 11144 | |
| mbed_official | 19:112740acecfa | 11145 | /******************* Bit definition for FMC_SR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 11146 | #define FMC_SR_IRS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11147 | #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11148 | #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */ |
| AnnaBridge | 167:e84263d55307 | 11149 | #define FMC_SR_ILS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 11150 | #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11151 | #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */ |
| AnnaBridge | 167:e84263d55307 | 11152 | #define FMC_SR_IFS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 11153 | #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11154 | #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */ |
| AnnaBridge | 167:e84263d55307 | 11155 | #define FMC_SR_IREN_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 11156 | #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11157 | #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */ |
| AnnaBridge | 167:e84263d55307 | 11158 | #define FMC_SR_ILEN_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11159 | #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11160 | #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */ |
| AnnaBridge | 167:e84263d55307 | 11161 | #define FMC_SR_IFEN_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 11162 | #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11163 | #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */ |
| AnnaBridge | 167:e84263d55307 | 11164 | #define FMC_SR_FEMPT_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 11165 | #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11166 | #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */ |
| mbed_official | 19:112740acecfa | 11167 | |
| mbed_official | 19:112740acecfa | 11168 | /****************** Bit definition for FMC_PMEM register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11169 | #define FMC_PMEM_MEMSET2_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11170 | #define FMC_PMEM_MEMSET2_Msk (0xFFU << FMC_PMEM_MEMSET2_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 11171 | #define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */ |
| AnnaBridge | 167:e84263d55307 | 11172 | #define FMC_PMEM_MEMSET2_0 (0x01U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11173 | #define FMC_PMEM_MEMSET2_1 (0x02U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11174 | #define FMC_PMEM_MEMSET2_2 (0x04U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11175 | #define FMC_PMEM_MEMSET2_3 (0x08U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11176 | #define FMC_PMEM_MEMSET2_4 (0x10U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11177 | #define FMC_PMEM_MEMSET2_5 (0x20U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11178 | #define FMC_PMEM_MEMSET2_6 (0x40U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11179 | #define FMC_PMEM_MEMSET2_7 (0x80U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11180 | |
| AnnaBridge | 167:e84263d55307 | 11181 | #define FMC_PMEM_MEMWAIT2_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11182 | #define FMC_PMEM_MEMWAIT2_Msk (0xFFU << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 11183 | #define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */ |
| AnnaBridge | 167:e84263d55307 | 11184 | #define FMC_PMEM_MEMWAIT2_0 (0x01U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11185 | #define FMC_PMEM_MEMWAIT2_1 (0x02U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11186 | #define FMC_PMEM_MEMWAIT2_2 (0x04U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11187 | #define FMC_PMEM_MEMWAIT2_3 (0x08U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11188 | #define FMC_PMEM_MEMWAIT2_4 (0x10U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11189 | #define FMC_PMEM_MEMWAIT2_5 (0x20U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11190 | #define FMC_PMEM_MEMWAIT2_6 (0x40U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11191 | #define FMC_PMEM_MEMWAIT2_7 (0x80U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11192 | |
| AnnaBridge | 167:e84263d55307 | 11193 | #define FMC_PMEM_MEMHOLD2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11194 | #define FMC_PMEM_MEMHOLD2_Msk (0xFFU << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 11195 | #define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */ |
| AnnaBridge | 167:e84263d55307 | 11196 | #define FMC_PMEM_MEMHOLD2_0 (0x01U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11197 | #define FMC_PMEM_MEMHOLD2_1 (0x02U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11198 | #define FMC_PMEM_MEMHOLD2_2 (0x04U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11199 | #define FMC_PMEM_MEMHOLD2_3 (0x08U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 11200 | #define FMC_PMEM_MEMHOLD2_4 (0x10U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 11201 | #define FMC_PMEM_MEMHOLD2_5 (0x20U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 11202 | #define FMC_PMEM_MEMHOLD2_6 (0x40U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 11203 | #define FMC_PMEM_MEMHOLD2_7 (0x80U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 11204 | |
| AnnaBridge | 167:e84263d55307 | 11205 | #define FMC_PMEM_MEMHIZ2_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 11206 | #define FMC_PMEM_MEMHIZ2_Msk (0xFFU << FMC_PMEM_MEMHIZ2_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 11207 | #define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ |
| AnnaBridge | 167:e84263d55307 | 11208 | #define FMC_PMEM_MEMHIZ2_0 (0x01U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 11209 | #define FMC_PMEM_MEMHIZ2_1 (0x02U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 11210 | #define FMC_PMEM_MEMHIZ2_2 (0x04U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 11211 | #define FMC_PMEM_MEMHIZ2_3 (0x08U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 11212 | #define FMC_PMEM_MEMHIZ2_4 (0x10U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 11213 | #define FMC_PMEM_MEMHIZ2_5 (0x20U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 11214 | #define FMC_PMEM_MEMHIZ2_6 (0x40U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 11215 | #define FMC_PMEM_MEMHIZ2_7 (0x80U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x80000000 */ |
| mbed_official | 19:112740acecfa | 11216 | |
| mbed_official | 19:112740acecfa | 11217 | /****************** Bit definition for FMC_PATT register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11218 | #define FMC_PATT_ATTSET2_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11219 | #define FMC_PATT_ATTSET2_Msk (0xFFU << FMC_PATT_ATTSET2_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 11220 | #define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */ |
| AnnaBridge | 167:e84263d55307 | 11221 | #define FMC_PATT_ATTSET2_0 (0x01U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11222 | #define FMC_PATT_ATTSET2_1 (0x02U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11223 | #define FMC_PATT_ATTSET2_2 (0x04U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11224 | #define FMC_PATT_ATTSET2_3 (0x08U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11225 | #define FMC_PATT_ATTSET2_4 (0x10U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11226 | #define FMC_PATT_ATTSET2_5 (0x20U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11227 | #define FMC_PATT_ATTSET2_6 (0x40U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11228 | #define FMC_PATT_ATTSET2_7 (0x80U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11229 | |
| AnnaBridge | 167:e84263d55307 | 11230 | #define FMC_PATT_ATTWAIT2_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11231 | #define FMC_PATT_ATTWAIT2_Msk (0xFFU << FMC_PATT_ATTWAIT2_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 11232 | #define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ |
| AnnaBridge | 167:e84263d55307 | 11233 | #define FMC_PATT_ATTWAIT2_0 (0x01U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11234 | #define FMC_PATT_ATTWAIT2_1 (0x02U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11235 | #define FMC_PATT_ATTWAIT2_2 (0x04U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11236 | #define FMC_PATT_ATTWAIT2_3 (0x08U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11237 | #define FMC_PATT_ATTWAIT2_4 (0x10U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11238 | #define FMC_PATT_ATTWAIT2_5 (0x20U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11239 | #define FMC_PATT_ATTWAIT2_6 (0x40U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11240 | #define FMC_PATT_ATTWAIT2_7 (0x80U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11241 | |
| AnnaBridge | 167:e84263d55307 | 11242 | #define FMC_PATT_ATTHOLD2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11243 | #define FMC_PATT_ATTHOLD2_Msk (0xFFU << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 11244 | #define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ |
| AnnaBridge | 167:e84263d55307 | 11245 | #define FMC_PATT_ATTHOLD2_0 (0x01U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11246 | #define FMC_PATT_ATTHOLD2_1 (0x02U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11247 | #define FMC_PATT_ATTHOLD2_2 (0x04U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11248 | #define FMC_PATT_ATTHOLD2_3 (0x08U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 11249 | #define FMC_PATT_ATTHOLD2_4 (0x10U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 11250 | #define FMC_PATT_ATTHOLD2_5 (0x20U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 11251 | #define FMC_PATT_ATTHOLD2_6 (0x40U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 11252 | #define FMC_PATT_ATTHOLD2_7 (0x80U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 11253 | |
| AnnaBridge | 167:e84263d55307 | 11254 | #define FMC_PATT_ATTHIZ2_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 11255 | #define FMC_PATT_ATTHIZ2_Msk (0xFFU << FMC_PATT_ATTHIZ2_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 11256 | #define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ |
| AnnaBridge | 167:e84263d55307 | 11257 | #define FMC_PATT_ATTHIZ2_0 (0x01U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 11258 | #define FMC_PATT_ATTHIZ2_1 (0x02U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 11259 | #define FMC_PATT_ATTHIZ2_2 (0x04U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 11260 | #define FMC_PATT_ATTHIZ2_3 (0x08U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 11261 | #define FMC_PATT_ATTHIZ2_4 (0x10U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 11262 | #define FMC_PATT_ATTHIZ2_5 (0x20U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 11263 | #define FMC_PATT_ATTHIZ2_6 (0x40U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 11264 | #define FMC_PATT_ATTHIZ2_7 (0x80U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x80000000 */ |
| mbed_official | 19:112740acecfa | 11265 | |
| mbed_official | 19:112740acecfa | 11266 | /****************** Bit definition for FMC_ECCR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11267 | #define FMC_ECCR_ECC2_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11268 | #define FMC_ECCR_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR_ECC2_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 11269 | #define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk /*!<ECC result */ |
| mbed_official | 19:112740acecfa | 11270 | |
| mbed_official | 19:112740acecfa | 11271 | /****************** Bit definition for FMC_SDCR1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11272 | #define FMC_SDCR1_NC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11273 | #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 11274 | #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */ |
| AnnaBridge | 167:e84263d55307 | 11275 | #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11276 | #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11277 | |
| AnnaBridge | 167:e84263d55307 | 11278 | #define FMC_SDCR1_NR_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 11279 | #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 11280 | #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */ |
| AnnaBridge | 167:e84263d55307 | 11281 | #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11282 | #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11283 | |
| AnnaBridge | 167:e84263d55307 | 11284 | #define FMC_SDCR1_MWID_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11285 | #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 11286 | #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */ |
| AnnaBridge | 167:e84263d55307 | 11287 | #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11288 | #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11289 | |
| AnnaBridge | 167:e84263d55307 | 11290 | #define FMC_SDCR1_NB_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 11291 | #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11292 | #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */ |
| AnnaBridge | 167:e84263d55307 | 11293 | |
| AnnaBridge | 167:e84263d55307 | 11294 | #define FMC_SDCR1_CAS_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 11295 | #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */ |
| AnnaBridge | 167:e84263d55307 | 11296 | #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */ |
| AnnaBridge | 167:e84263d55307 | 11297 | #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11298 | #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11299 | |
| AnnaBridge | 167:e84263d55307 | 11300 | #define FMC_SDCR1_WP_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 11301 | #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11302 | #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */ |
| AnnaBridge | 167:e84263d55307 | 11303 | |
| AnnaBridge | 167:e84263d55307 | 11304 | #define FMC_SDCR1_SDCLK_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 11305 | #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 11306 | #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */ |
| AnnaBridge | 167:e84263d55307 | 11307 | #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11308 | #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11309 | |
| AnnaBridge | 167:e84263d55307 | 11310 | #define FMC_SDCR1_RBURST_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 11311 | #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11312 | #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */ |
| AnnaBridge | 167:e84263d55307 | 11313 | |
| AnnaBridge | 167:e84263d55307 | 11314 | #define FMC_SDCR1_RPIPE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 11315 | #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */ |
| AnnaBridge | 167:e84263d55307 | 11316 | #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */ |
| AnnaBridge | 167:e84263d55307 | 11317 | #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11318 | #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */ |
| mbed_official | 19:112740acecfa | 11319 | |
| mbed_official | 19:112740acecfa | 11320 | /****************** Bit definition for FMC_SDCR2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11321 | #define FMC_SDCR2_NC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11322 | #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 11323 | #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */ |
| AnnaBridge | 167:e84263d55307 | 11324 | #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11325 | #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11326 | |
| AnnaBridge | 167:e84263d55307 | 11327 | #define FMC_SDCR2_NR_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 11328 | #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 11329 | #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */ |
| AnnaBridge | 167:e84263d55307 | 11330 | #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11331 | #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11332 | |
| AnnaBridge | 167:e84263d55307 | 11333 | #define FMC_SDCR2_MWID_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11334 | #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 11335 | #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */ |
| AnnaBridge | 167:e84263d55307 | 11336 | #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11337 | #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11338 | |
| AnnaBridge | 167:e84263d55307 | 11339 | #define FMC_SDCR2_NB_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 11340 | #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11341 | #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */ |
| AnnaBridge | 167:e84263d55307 | 11342 | |
| AnnaBridge | 167:e84263d55307 | 11343 | #define FMC_SDCR2_CAS_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 11344 | #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */ |
| AnnaBridge | 167:e84263d55307 | 11345 | #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */ |
| AnnaBridge | 167:e84263d55307 | 11346 | #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11347 | #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11348 | |
| AnnaBridge | 167:e84263d55307 | 11349 | #define FMC_SDCR2_WP_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 11350 | #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11351 | #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */ |
| AnnaBridge | 167:e84263d55307 | 11352 | |
| AnnaBridge | 167:e84263d55307 | 11353 | #define FMC_SDCR2_SDCLK_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 11354 | #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 11355 | #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */ |
| AnnaBridge | 167:e84263d55307 | 11356 | #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11357 | #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11358 | |
| AnnaBridge | 167:e84263d55307 | 11359 | #define FMC_SDCR2_RBURST_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 11360 | #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11361 | #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */ |
| AnnaBridge | 167:e84263d55307 | 11362 | |
| AnnaBridge | 167:e84263d55307 | 11363 | #define FMC_SDCR2_RPIPE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 11364 | #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */ |
| AnnaBridge | 167:e84263d55307 | 11365 | #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */ |
| AnnaBridge | 167:e84263d55307 | 11366 | #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11367 | #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */ |
| mbed_official | 19:112740acecfa | 11368 | |
| mbed_official | 19:112740acecfa | 11369 | /****************** Bit definition for FMC_SDTR1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11370 | #define FMC_SDTR1_TMRD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11371 | #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 11372 | #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */ |
| AnnaBridge | 167:e84263d55307 | 11373 | #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11374 | #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11375 | #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11376 | #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */ |
| mbed_official | 19:112740acecfa | 11377 | |
| AnnaBridge | 167:e84263d55307 | 11378 | #define FMC_SDTR1_TXSR_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11379 | #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 11380 | #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */ |
| AnnaBridge | 167:e84263d55307 | 11381 | #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11382 | #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11383 | #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11384 | #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11385 | |
| AnnaBridge | 167:e84263d55307 | 11386 | #define FMC_SDTR1_TRAS_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11387 | #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 11388 | #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */ |
| AnnaBridge | 167:e84263d55307 | 11389 | #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11390 | #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11391 | #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11392 | #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11393 | |
| AnnaBridge | 167:e84263d55307 | 11394 | #define FMC_SDTR1_TRC_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 11395 | #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 167:e84263d55307 | 11396 | #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */ |
| AnnaBridge | 167:e84263d55307 | 11397 | #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11398 | #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11399 | #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11400 | |
| AnnaBridge | 167:e84263d55307 | 11401 | #define FMC_SDTR1_TWR_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11402 | #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 11403 | #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */ |
| AnnaBridge | 167:e84263d55307 | 11404 | #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11405 | #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11406 | #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11407 | |
| AnnaBridge | 167:e84263d55307 | 11408 | #define FMC_SDTR1_TRP_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 11409 | #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 11410 | #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */ |
| AnnaBridge | 167:e84263d55307 | 11411 | #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 11412 | #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 11413 | #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 11414 | |
| AnnaBridge | 167:e84263d55307 | 11415 | #define FMC_SDTR1_TRCD_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 11416 | #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 11417 | #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */ |
| AnnaBridge | 167:e84263d55307 | 11418 | #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 11419 | #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 11420 | #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */ |
| mbed_official | 19:112740acecfa | 11421 | |
| mbed_official | 19:112740acecfa | 11422 | /****************** Bit definition for FMC_SDTR2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11423 | #define FMC_SDTR2_TMRD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11424 | #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 11425 | #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */ |
| AnnaBridge | 167:e84263d55307 | 11426 | #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11427 | #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11428 | #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11429 | #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */ |
| mbed_official | 19:112740acecfa | 11430 | |
| AnnaBridge | 167:e84263d55307 | 11431 | #define FMC_SDTR2_TXSR_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11432 | #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 11433 | #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */ |
| AnnaBridge | 167:e84263d55307 | 11434 | #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11435 | #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11436 | #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11437 | #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11438 | |
| AnnaBridge | 167:e84263d55307 | 11439 | #define FMC_SDTR2_TRAS_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11440 | #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 11441 | #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */ |
| AnnaBridge | 167:e84263d55307 | 11442 | #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11443 | #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11444 | #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11445 | #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11446 | |
| AnnaBridge | 167:e84263d55307 | 11447 | #define FMC_SDTR2_TRC_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 11448 | #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 167:e84263d55307 | 11449 | #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */ |
| AnnaBridge | 167:e84263d55307 | 11450 | #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11451 | #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11452 | #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11453 | |
| AnnaBridge | 167:e84263d55307 | 11454 | #define FMC_SDTR2_TWR_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11455 | #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 11456 | #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */ |
| AnnaBridge | 167:e84263d55307 | 11457 | #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11458 | #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11459 | #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11460 | |
| AnnaBridge | 167:e84263d55307 | 11461 | #define FMC_SDTR2_TRP_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 11462 | #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 11463 | #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */ |
| AnnaBridge | 167:e84263d55307 | 11464 | #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 11465 | #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 11466 | #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 11467 | |
| AnnaBridge | 167:e84263d55307 | 11468 | #define FMC_SDTR2_TRCD_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 11469 | #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 11470 | #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */ |
| AnnaBridge | 167:e84263d55307 | 11471 | #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 11472 | #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 11473 | #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */ |
| mbed_official | 19:112740acecfa | 11474 | |
| mbed_official | 19:112740acecfa | 11475 | /****************** Bit definition for FMC_SDCMR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11476 | #define FMC_SDCMR_MODE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11477 | #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 11478 | #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ |
| AnnaBridge | 167:e84263d55307 | 11479 | #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11480 | #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11481 | #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ |
| mbed_official | 19:112740acecfa | 11482 | |
| AnnaBridge | 167:e84263d55307 | 11483 | #define FMC_SDCMR_CTB2_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 11484 | #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11485 | #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */ |
| AnnaBridge | 167:e84263d55307 | 11486 | |
| AnnaBridge | 167:e84263d55307 | 11487 | #define FMC_SDCMR_CTB1_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11488 | #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11489 | #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */ |
| AnnaBridge | 167:e84263d55307 | 11490 | |
| AnnaBridge | 167:e84263d55307 | 11491 | #define FMC_SDCMR_NRFS_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 11492 | #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */ |
| AnnaBridge | 167:e84263d55307 | 11493 | #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */ |
| AnnaBridge | 167:e84263d55307 | 11494 | #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11495 | #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11496 | #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11497 | #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11498 | |
| AnnaBridge | 167:e84263d55307 | 11499 | #define FMC_SDCMR_MRD_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 11500 | #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */ |
| AnnaBridge | 167:e84263d55307 | 11501 | #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */ |
| mbed_official | 19:112740acecfa | 11502 | |
| mbed_official | 19:112740acecfa | 11503 | /****************** Bit definition for FMC_SDRTR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11504 | #define FMC_SDRTR_CRE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11505 | #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11506 | #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */ |
| AnnaBridge | 167:e84263d55307 | 11507 | |
| AnnaBridge | 167:e84263d55307 | 11508 | #define FMC_SDRTR_COUNT_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 11509 | #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */ |
| AnnaBridge | 167:e84263d55307 | 11510 | #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */ |
| AnnaBridge | 167:e84263d55307 | 11511 | |
| AnnaBridge | 167:e84263d55307 | 11512 | #define FMC_SDRTR_REIE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 11513 | #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11514 | #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */ |
| mbed_official | 19:112740acecfa | 11515 | |
| mbed_official | 19:112740acecfa | 11516 | /****************** Bit definition for FMC_SDSR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 11517 | #define FMC_SDSR_RE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11518 | #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11519 | #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */ |
| AnnaBridge | 167:e84263d55307 | 11520 | |
| AnnaBridge | 167:e84263d55307 | 11521 | #define FMC_SDSR_MODES1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 11522 | #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 167:e84263d55307 | 11523 | #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */ |
| AnnaBridge | 167:e84263d55307 | 11524 | #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11525 | #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11526 | |
| AnnaBridge | 167:e84263d55307 | 11527 | #define FMC_SDSR_MODES2_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 11528 | #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */ |
| AnnaBridge | 167:e84263d55307 | 11529 | #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */ |
| AnnaBridge | 167:e84263d55307 | 11530 | #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11531 | #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11532 | #define FMC_SDSR_BUSY_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 11533 | #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11534 | #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */ |
| mbed_official | 19:112740acecfa | 11535 | |
| mbed_official | 19:112740acecfa | 11536 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 11537 | /* */ |
| mbed_official | 19:112740acecfa | 11538 | /* General Purpose I/O */ |
| mbed_official | 19:112740acecfa | 11539 | /* */ |
| mbed_official | 19:112740acecfa | 11540 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 11541 | /****************** Bits definition for GPIO_MODER register *****************/ |
| AnnaBridge | 167:e84263d55307 | 11542 | #define GPIO_MODER_MODE0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11543 | #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 11544 | #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk |
| AnnaBridge | 167:e84263d55307 | 11545 | #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11546 | #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11547 | #define GPIO_MODER_MODE1_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 11548 | #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 11549 | #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk |
| AnnaBridge | 167:e84263d55307 | 11550 | #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11551 | #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11552 | #define GPIO_MODER_MODE2_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11553 | #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 11554 | #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk |
| AnnaBridge | 167:e84263d55307 | 11555 | #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11556 | #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11557 | #define GPIO_MODER_MODE3_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 11558 | #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 11559 | #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk |
| AnnaBridge | 167:e84263d55307 | 11560 | #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11561 | #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11562 | #define GPIO_MODER_MODE4_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11563 | #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 11564 | #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk |
| AnnaBridge | 167:e84263d55307 | 11565 | #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11566 | #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11567 | #define GPIO_MODER_MODE5_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 11568 | #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 11569 | #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk |
| AnnaBridge | 167:e84263d55307 | 11570 | #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11571 | #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11572 | #define GPIO_MODER_MODE6_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 11573 | #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 167:e84263d55307 | 11574 | #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk |
| AnnaBridge | 167:e84263d55307 | 11575 | #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11576 | #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11577 | #define GPIO_MODER_MODE7_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 11578 | #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 11579 | #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk |
| AnnaBridge | 167:e84263d55307 | 11580 | #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11581 | #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11582 | #define GPIO_MODER_MODE8_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11583 | #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 11584 | #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk |
| AnnaBridge | 167:e84263d55307 | 11585 | #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11586 | #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11587 | #define GPIO_MODER_MODE9_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 11588 | #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 167:e84263d55307 | 11589 | #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk |
| AnnaBridge | 167:e84263d55307 | 11590 | #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11591 | #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 11592 | #define GPIO_MODER_MODE10_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 11593 | #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 11594 | #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk |
| AnnaBridge | 167:e84263d55307 | 11595 | #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 11596 | #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 11597 | #define GPIO_MODER_MODE11_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 11598 | #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 167:e84263d55307 | 11599 | #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk |
| AnnaBridge | 167:e84263d55307 | 11600 | #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 11601 | #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 11602 | #define GPIO_MODER_MODE12_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 11603 | #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 167:e84263d55307 | 11604 | #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk |
| AnnaBridge | 167:e84263d55307 | 11605 | #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 11606 | #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 11607 | #define GPIO_MODER_MODE13_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 11608 | #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 167:e84263d55307 | 11609 | #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk |
| AnnaBridge | 167:e84263d55307 | 11610 | #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 11611 | #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 11612 | #define GPIO_MODER_MODE14_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 11613 | #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 11614 | #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk |
| AnnaBridge | 167:e84263d55307 | 11615 | #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 11616 | #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 11617 | #define GPIO_MODER_MODE15_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 11618 | #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 167:e84263d55307 | 11619 | #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk |
| AnnaBridge | 167:e84263d55307 | 11620 | #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 11621 | #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 11622 | |
| AnnaBridge | 167:e84263d55307 | 11623 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 11624 | #define GPIO_MODER_MODER0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11625 | #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 11626 | #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk |
| AnnaBridge | 167:e84263d55307 | 11627 | #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11628 | #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11629 | #define GPIO_MODER_MODER1_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 11630 | #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 11631 | #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk |
| AnnaBridge | 167:e84263d55307 | 11632 | #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11633 | #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11634 | #define GPIO_MODER_MODER2_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11635 | #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 11636 | #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk |
| AnnaBridge | 167:e84263d55307 | 11637 | #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11638 | #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11639 | #define GPIO_MODER_MODER3_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 11640 | #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 11641 | #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk |
| AnnaBridge | 167:e84263d55307 | 11642 | #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11643 | #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11644 | #define GPIO_MODER_MODER4_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11645 | #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 11646 | #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk |
| AnnaBridge | 167:e84263d55307 | 11647 | #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11648 | #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11649 | #define GPIO_MODER_MODER5_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 11650 | #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 11651 | #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk |
| AnnaBridge | 167:e84263d55307 | 11652 | #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11653 | #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11654 | #define GPIO_MODER_MODER6_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 11655 | #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 167:e84263d55307 | 11656 | #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk |
| AnnaBridge | 167:e84263d55307 | 11657 | #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11658 | #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11659 | #define GPIO_MODER_MODER7_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 11660 | #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 11661 | #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk |
| AnnaBridge | 167:e84263d55307 | 11662 | #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11663 | #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11664 | #define GPIO_MODER_MODER8_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11665 | #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 11666 | #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk |
| AnnaBridge | 167:e84263d55307 | 11667 | #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11668 | #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11669 | #define GPIO_MODER_MODER9_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 11670 | #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 167:e84263d55307 | 11671 | #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk |
| AnnaBridge | 167:e84263d55307 | 11672 | #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11673 | #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 11674 | #define GPIO_MODER_MODER10_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 11675 | #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 11676 | #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk |
| AnnaBridge | 167:e84263d55307 | 11677 | #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 11678 | #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 11679 | #define GPIO_MODER_MODER11_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 11680 | #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 167:e84263d55307 | 11681 | #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk |
| AnnaBridge | 167:e84263d55307 | 11682 | #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 11683 | #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 11684 | #define GPIO_MODER_MODER12_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 11685 | #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 167:e84263d55307 | 11686 | #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk |
| AnnaBridge | 167:e84263d55307 | 11687 | #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 11688 | #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 11689 | #define GPIO_MODER_MODER13_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 11690 | #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 167:e84263d55307 | 11691 | #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk |
| AnnaBridge | 167:e84263d55307 | 11692 | #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 11693 | #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 11694 | #define GPIO_MODER_MODER14_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 11695 | #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 11696 | #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk |
| AnnaBridge | 167:e84263d55307 | 11697 | #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 11698 | #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 11699 | #define GPIO_MODER_MODER15_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 11700 | #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 167:e84263d55307 | 11701 | #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk |
| AnnaBridge | 167:e84263d55307 | 11702 | #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 11703 | #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ |
| mbed_official | 19:112740acecfa | 11704 | |
| mbed_official | 19:112740acecfa | 11705 | /****************** Bits definition for GPIO_OTYPER register ****************/ |
| AnnaBridge | 167:e84263d55307 | 11706 | #define GPIO_OTYPER_OT0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11707 | #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11708 | #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk |
| AnnaBridge | 167:e84263d55307 | 11709 | #define GPIO_OTYPER_OT1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 11710 | #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11711 | #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk |
| AnnaBridge | 167:e84263d55307 | 11712 | #define GPIO_OTYPER_OT2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 11713 | #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11714 | #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk |
| AnnaBridge | 167:e84263d55307 | 11715 | #define GPIO_OTYPER_OT3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 11716 | #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11717 | #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk |
| AnnaBridge | 167:e84263d55307 | 11718 | #define GPIO_OTYPER_OT4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11719 | #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11720 | #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk |
| AnnaBridge | 167:e84263d55307 | 11721 | #define GPIO_OTYPER_OT5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 11722 | #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11723 | #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk |
| AnnaBridge | 167:e84263d55307 | 11724 | #define GPIO_OTYPER_OT6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 11725 | #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11726 | #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk |
| AnnaBridge | 167:e84263d55307 | 11727 | #define GPIO_OTYPER_OT7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 11728 | #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11729 | #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk |
| AnnaBridge | 167:e84263d55307 | 11730 | #define GPIO_OTYPER_OT8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11731 | #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11732 | #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk |
| AnnaBridge | 167:e84263d55307 | 11733 | #define GPIO_OTYPER_OT9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 11734 | #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11735 | #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk |
| AnnaBridge | 167:e84263d55307 | 11736 | #define GPIO_OTYPER_OT10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 11737 | #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11738 | #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk |
| AnnaBridge | 167:e84263d55307 | 11739 | #define GPIO_OTYPER_OT11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 11740 | #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11741 | #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk |
| AnnaBridge | 167:e84263d55307 | 11742 | #define GPIO_OTYPER_OT12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 11743 | #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11744 | #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk |
| AnnaBridge | 167:e84263d55307 | 11745 | #define GPIO_OTYPER_OT13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 11746 | #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11747 | #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk |
| AnnaBridge | 167:e84263d55307 | 11748 | #define GPIO_OTYPER_OT14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 11749 | #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11750 | #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk |
| AnnaBridge | 167:e84263d55307 | 11751 | #define GPIO_OTYPER_OT15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 11752 | #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11753 | #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk |
| AnnaBridge | 167:e84263d55307 | 11754 | |
| AnnaBridge | 167:e84263d55307 | 11755 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 11756 | #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0 |
| AnnaBridge | 167:e84263d55307 | 11757 | #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1 |
| AnnaBridge | 167:e84263d55307 | 11758 | #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2 |
| AnnaBridge | 167:e84263d55307 | 11759 | #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3 |
| AnnaBridge | 167:e84263d55307 | 11760 | #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4 |
| AnnaBridge | 167:e84263d55307 | 11761 | #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5 |
| AnnaBridge | 167:e84263d55307 | 11762 | #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6 |
| AnnaBridge | 167:e84263d55307 | 11763 | #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7 |
| AnnaBridge | 167:e84263d55307 | 11764 | #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8 |
| AnnaBridge | 167:e84263d55307 | 11765 | #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9 |
| AnnaBridge | 167:e84263d55307 | 11766 | #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10 |
| AnnaBridge | 167:e84263d55307 | 11767 | #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11 |
| AnnaBridge | 167:e84263d55307 | 11768 | #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12 |
| AnnaBridge | 167:e84263d55307 | 11769 | #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13 |
| AnnaBridge | 167:e84263d55307 | 11770 | #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14 |
| AnnaBridge | 167:e84263d55307 | 11771 | #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15 |
| mbed_official | 19:112740acecfa | 11772 | |
| mbed_official | 19:112740acecfa | 11773 | /****************** Bits definition for GPIO_OSPEEDR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 11774 | #define GPIO_OSPEEDR_OSPEED0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11775 | #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 11776 | #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk |
| AnnaBridge | 167:e84263d55307 | 11777 | #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11778 | #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11779 | #define GPIO_OSPEEDR_OSPEED1_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 11780 | #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 11781 | #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk |
| AnnaBridge | 167:e84263d55307 | 11782 | #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11783 | #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11784 | #define GPIO_OSPEEDR_OSPEED2_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11785 | #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 11786 | #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk |
| AnnaBridge | 167:e84263d55307 | 11787 | #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11788 | #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11789 | #define GPIO_OSPEEDR_OSPEED3_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 11790 | #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 11791 | #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk |
| AnnaBridge | 167:e84263d55307 | 11792 | #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11793 | #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11794 | #define GPIO_OSPEEDR_OSPEED4_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11795 | #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 11796 | #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk |
| AnnaBridge | 167:e84263d55307 | 11797 | #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11798 | #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11799 | #define GPIO_OSPEEDR_OSPEED5_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 11800 | #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 11801 | #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk |
| AnnaBridge | 167:e84263d55307 | 11802 | #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11803 | #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11804 | #define GPIO_OSPEEDR_OSPEED6_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 11805 | #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 167:e84263d55307 | 11806 | #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk |
| AnnaBridge | 167:e84263d55307 | 11807 | #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11808 | #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11809 | #define GPIO_OSPEEDR_OSPEED7_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 11810 | #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 11811 | #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk |
| AnnaBridge | 167:e84263d55307 | 11812 | #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11813 | #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11814 | #define GPIO_OSPEEDR_OSPEED8_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11815 | #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 11816 | #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk |
| AnnaBridge | 167:e84263d55307 | 11817 | #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11818 | #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11819 | #define GPIO_OSPEEDR_OSPEED9_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 11820 | #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 167:e84263d55307 | 11821 | #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk |
| AnnaBridge | 167:e84263d55307 | 11822 | #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11823 | #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 11824 | #define GPIO_OSPEEDR_OSPEED10_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 11825 | #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 11826 | #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk |
| AnnaBridge | 167:e84263d55307 | 11827 | #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 11828 | #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 11829 | #define GPIO_OSPEEDR_OSPEED11_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 11830 | #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 167:e84263d55307 | 11831 | #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk |
| AnnaBridge | 167:e84263d55307 | 11832 | #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 11833 | #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 11834 | #define GPIO_OSPEEDR_OSPEED12_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 11835 | #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 167:e84263d55307 | 11836 | #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk |
| AnnaBridge | 167:e84263d55307 | 11837 | #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 11838 | #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 11839 | #define GPIO_OSPEEDR_OSPEED13_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 11840 | #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 167:e84263d55307 | 11841 | #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk |
| AnnaBridge | 167:e84263d55307 | 11842 | #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 11843 | #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 11844 | #define GPIO_OSPEEDR_OSPEED14_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 11845 | #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 11846 | #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk |
| AnnaBridge | 167:e84263d55307 | 11847 | #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 11848 | #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 11849 | #define GPIO_OSPEEDR_OSPEED15_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 11850 | #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 167:e84263d55307 | 11851 | #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk |
| AnnaBridge | 167:e84263d55307 | 11852 | #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 11853 | #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 11854 | |
| AnnaBridge | 167:e84263d55307 | 11855 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 11856 | #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0 |
| AnnaBridge | 167:e84263d55307 | 11857 | #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0 |
| AnnaBridge | 167:e84263d55307 | 11858 | #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1 |
| AnnaBridge | 167:e84263d55307 | 11859 | #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1 |
| AnnaBridge | 167:e84263d55307 | 11860 | #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0 |
| AnnaBridge | 167:e84263d55307 | 11861 | #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1 |
| AnnaBridge | 167:e84263d55307 | 11862 | #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2 |
| AnnaBridge | 167:e84263d55307 | 11863 | #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0 |
| AnnaBridge | 167:e84263d55307 | 11864 | #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1 |
| AnnaBridge | 167:e84263d55307 | 11865 | #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3 |
| AnnaBridge | 167:e84263d55307 | 11866 | #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0 |
| AnnaBridge | 167:e84263d55307 | 11867 | #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1 |
| AnnaBridge | 167:e84263d55307 | 11868 | #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4 |
| AnnaBridge | 167:e84263d55307 | 11869 | #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0 |
| AnnaBridge | 167:e84263d55307 | 11870 | #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1 |
| AnnaBridge | 167:e84263d55307 | 11871 | #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5 |
| AnnaBridge | 167:e84263d55307 | 11872 | #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0 |
| AnnaBridge | 167:e84263d55307 | 11873 | #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1 |
| AnnaBridge | 167:e84263d55307 | 11874 | #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6 |
| AnnaBridge | 167:e84263d55307 | 11875 | #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0 |
| AnnaBridge | 167:e84263d55307 | 11876 | #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1 |
| AnnaBridge | 167:e84263d55307 | 11877 | #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7 |
| AnnaBridge | 167:e84263d55307 | 11878 | #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0 |
| AnnaBridge | 167:e84263d55307 | 11879 | #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1 |
| AnnaBridge | 167:e84263d55307 | 11880 | #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8 |
| AnnaBridge | 167:e84263d55307 | 11881 | #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0 |
| AnnaBridge | 167:e84263d55307 | 11882 | #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1 |
| AnnaBridge | 167:e84263d55307 | 11883 | #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9 |
| AnnaBridge | 167:e84263d55307 | 11884 | #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0 |
| AnnaBridge | 167:e84263d55307 | 11885 | #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1 |
| AnnaBridge | 167:e84263d55307 | 11886 | #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10 |
| AnnaBridge | 167:e84263d55307 | 11887 | #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0 |
| AnnaBridge | 167:e84263d55307 | 11888 | #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1 |
| AnnaBridge | 167:e84263d55307 | 11889 | #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11 |
| AnnaBridge | 167:e84263d55307 | 11890 | #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0 |
| AnnaBridge | 167:e84263d55307 | 11891 | #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1 |
| AnnaBridge | 167:e84263d55307 | 11892 | #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12 |
| AnnaBridge | 167:e84263d55307 | 11893 | #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0 |
| AnnaBridge | 167:e84263d55307 | 11894 | #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1 |
| AnnaBridge | 167:e84263d55307 | 11895 | #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13 |
| AnnaBridge | 167:e84263d55307 | 11896 | #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0 |
| AnnaBridge | 167:e84263d55307 | 11897 | #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1 |
| AnnaBridge | 167:e84263d55307 | 11898 | #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14 |
| AnnaBridge | 167:e84263d55307 | 11899 | #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0 |
| AnnaBridge | 167:e84263d55307 | 11900 | #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1 |
| AnnaBridge | 167:e84263d55307 | 11901 | #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15 |
| AnnaBridge | 167:e84263d55307 | 11902 | #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0 |
| AnnaBridge | 167:e84263d55307 | 11903 | #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1 |
| mbed_official | 19:112740acecfa | 11904 | |
| mbed_official | 19:112740acecfa | 11905 | /****************** Bits definition for GPIO_PUPDR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 11906 | #define GPIO_PUPDR_PUPD0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 11907 | #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 11908 | #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk |
| AnnaBridge | 167:e84263d55307 | 11909 | #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 11910 | #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 11911 | #define GPIO_PUPDR_PUPD1_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 11912 | #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 11913 | #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk |
| AnnaBridge | 167:e84263d55307 | 11914 | #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 11915 | #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 11916 | #define GPIO_PUPDR_PUPD2_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 11917 | #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 11918 | #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk |
| AnnaBridge | 167:e84263d55307 | 11919 | #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 11920 | #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 11921 | #define GPIO_PUPDR_PUPD3_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 11922 | #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 11923 | #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk |
| AnnaBridge | 167:e84263d55307 | 11924 | #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 11925 | #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 11926 | #define GPIO_PUPDR_PUPD4_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 11927 | #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 11928 | #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk |
| AnnaBridge | 167:e84263d55307 | 11929 | #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 11930 | #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 11931 | #define GPIO_PUPDR_PUPD5_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 11932 | #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 11933 | #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk |
| AnnaBridge | 167:e84263d55307 | 11934 | #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 11935 | #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 11936 | #define GPIO_PUPDR_PUPD6_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 11937 | #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 167:e84263d55307 | 11938 | #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk |
| AnnaBridge | 167:e84263d55307 | 11939 | #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 11940 | #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 11941 | #define GPIO_PUPDR_PUPD7_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 11942 | #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 11943 | #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk |
| AnnaBridge | 167:e84263d55307 | 11944 | #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 11945 | #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 11946 | #define GPIO_PUPDR_PUPD8_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 11947 | #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 11948 | #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk |
| AnnaBridge | 167:e84263d55307 | 11949 | #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 11950 | #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 11951 | #define GPIO_PUPDR_PUPD9_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 11952 | #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 167:e84263d55307 | 11953 | #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk |
| AnnaBridge | 167:e84263d55307 | 11954 | #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 11955 | #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 11956 | #define GPIO_PUPDR_PUPD10_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 11957 | #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 11958 | #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk |
| AnnaBridge | 167:e84263d55307 | 11959 | #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 11960 | #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 11961 | #define GPIO_PUPDR_PUPD11_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 11962 | #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 167:e84263d55307 | 11963 | #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk |
| AnnaBridge | 167:e84263d55307 | 11964 | #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 11965 | #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 11966 | #define GPIO_PUPDR_PUPD12_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 11967 | #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 167:e84263d55307 | 11968 | #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk |
| AnnaBridge | 167:e84263d55307 | 11969 | #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 11970 | #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 11971 | #define GPIO_PUPDR_PUPD13_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 11972 | #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 167:e84263d55307 | 11973 | #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk |
| AnnaBridge | 167:e84263d55307 | 11974 | #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 11975 | #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 11976 | #define GPIO_PUPDR_PUPD14_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 11977 | #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 11978 | #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk |
| AnnaBridge | 167:e84263d55307 | 11979 | #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 11980 | #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 11981 | #define GPIO_PUPDR_PUPD15_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 11982 | #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 167:e84263d55307 | 11983 | #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk |
| AnnaBridge | 167:e84263d55307 | 11984 | #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 11985 | #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 11986 | |
| AnnaBridge | 167:e84263d55307 | 11987 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 11988 | #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0 |
| AnnaBridge | 167:e84263d55307 | 11989 | #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0 |
| AnnaBridge | 167:e84263d55307 | 11990 | #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1 |
| AnnaBridge | 167:e84263d55307 | 11991 | #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1 |
| AnnaBridge | 167:e84263d55307 | 11992 | #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0 |
| AnnaBridge | 167:e84263d55307 | 11993 | #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1 |
| AnnaBridge | 167:e84263d55307 | 11994 | #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2 |
| AnnaBridge | 167:e84263d55307 | 11995 | #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0 |
| AnnaBridge | 167:e84263d55307 | 11996 | #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1 |
| AnnaBridge | 167:e84263d55307 | 11997 | #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3 |
| AnnaBridge | 167:e84263d55307 | 11998 | #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0 |
| AnnaBridge | 167:e84263d55307 | 11999 | #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1 |
| AnnaBridge | 167:e84263d55307 | 12000 | #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4 |
| AnnaBridge | 167:e84263d55307 | 12001 | #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0 |
| AnnaBridge | 167:e84263d55307 | 12002 | #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1 |
| AnnaBridge | 167:e84263d55307 | 12003 | #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5 |
| AnnaBridge | 167:e84263d55307 | 12004 | #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0 |
| AnnaBridge | 167:e84263d55307 | 12005 | #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1 |
| AnnaBridge | 167:e84263d55307 | 12006 | #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6 |
| AnnaBridge | 167:e84263d55307 | 12007 | #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0 |
| AnnaBridge | 167:e84263d55307 | 12008 | #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1 |
| AnnaBridge | 167:e84263d55307 | 12009 | #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7 |
| AnnaBridge | 167:e84263d55307 | 12010 | #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0 |
| AnnaBridge | 167:e84263d55307 | 12011 | #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1 |
| AnnaBridge | 167:e84263d55307 | 12012 | #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8 |
| AnnaBridge | 167:e84263d55307 | 12013 | #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0 |
| AnnaBridge | 167:e84263d55307 | 12014 | #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1 |
| AnnaBridge | 167:e84263d55307 | 12015 | #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9 |
| AnnaBridge | 167:e84263d55307 | 12016 | #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0 |
| AnnaBridge | 167:e84263d55307 | 12017 | #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1 |
| AnnaBridge | 167:e84263d55307 | 12018 | #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10 |
| AnnaBridge | 167:e84263d55307 | 12019 | #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0 |
| AnnaBridge | 167:e84263d55307 | 12020 | #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1 |
| AnnaBridge | 167:e84263d55307 | 12021 | #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11 |
| AnnaBridge | 167:e84263d55307 | 12022 | #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0 |
| AnnaBridge | 167:e84263d55307 | 12023 | #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1 |
| AnnaBridge | 167:e84263d55307 | 12024 | #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12 |
| AnnaBridge | 167:e84263d55307 | 12025 | #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0 |
| AnnaBridge | 167:e84263d55307 | 12026 | #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1 |
| AnnaBridge | 167:e84263d55307 | 12027 | #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13 |
| AnnaBridge | 167:e84263d55307 | 12028 | #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0 |
| AnnaBridge | 167:e84263d55307 | 12029 | #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1 |
| AnnaBridge | 167:e84263d55307 | 12030 | #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14 |
| AnnaBridge | 167:e84263d55307 | 12031 | #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0 |
| AnnaBridge | 167:e84263d55307 | 12032 | #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1 |
| AnnaBridge | 167:e84263d55307 | 12033 | #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15 |
| AnnaBridge | 167:e84263d55307 | 12034 | #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0 |
| AnnaBridge | 167:e84263d55307 | 12035 | #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1 |
| mbed_official | 19:112740acecfa | 12036 | |
| mbed_official | 19:112740acecfa | 12037 | /****************** Bits definition for GPIO_IDR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 12038 | #define GPIO_IDR_ID0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12039 | #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12040 | #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk |
| AnnaBridge | 167:e84263d55307 | 12041 | #define GPIO_IDR_ID1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12042 | #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12043 | #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk |
| AnnaBridge | 167:e84263d55307 | 12044 | #define GPIO_IDR_ID2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12045 | #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12046 | #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk |
| AnnaBridge | 167:e84263d55307 | 12047 | #define GPIO_IDR_ID3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12048 | #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12049 | #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk |
| AnnaBridge | 167:e84263d55307 | 12050 | #define GPIO_IDR_ID4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12051 | #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12052 | #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk |
| AnnaBridge | 167:e84263d55307 | 12053 | #define GPIO_IDR_ID5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 12054 | #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12055 | #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk |
| AnnaBridge | 167:e84263d55307 | 12056 | #define GPIO_IDR_ID6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 12057 | #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12058 | #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk |
| AnnaBridge | 167:e84263d55307 | 12059 | #define GPIO_IDR_ID7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 12060 | #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12061 | #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk |
| AnnaBridge | 167:e84263d55307 | 12062 | #define GPIO_IDR_ID8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12063 | #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12064 | #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk |
| AnnaBridge | 167:e84263d55307 | 12065 | #define GPIO_IDR_ID9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 12066 | #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12067 | #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk |
| AnnaBridge | 167:e84263d55307 | 12068 | #define GPIO_IDR_ID10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 12069 | #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 12070 | #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk |
| AnnaBridge | 167:e84263d55307 | 12071 | #define GPIO_IDR_ID11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 12072 | #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 12073 | #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk |
| AnnaBridge | 167:e84263d55307 | 12074 | #define GPIO_IDR_ID12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12075 | #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 12076 | #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk |
| AnnaBridge | 167:e84263d55307 | 12077 | #define GPIO_IDR_ID13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 12078 | #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 12079 | #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk |
| AnnaBridge | 167:e84263d55307 | 12080 | #define GPIO_IDR_ID14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 12081 | #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 12082 | #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk |
| AnnaBridge | 167:e84263d55307 | 12083 | #define GPIO_IDR_ID15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 12084 | #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12085 | #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk |
| AnnaBridge | 167:e84263d55307 | 12086 | |
| AnnaBridge | 167:e84263d55307 | 12087 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 12088 | #define GPIO_IDR_IDR_0 GPIO_IDR_ID0 |
| AnnaBridge | 167:e84263d55307 | 12089 | #define GPIO_IDR_IDR_1 GPIO_IDR_ID1 |
| AnnaBridge | 167:e84263d55307 | 12090 | #define GPIO_IDR_IDR_2 GPIO_IDR_ID2 |
| AnnaBridge | 167:e84263d55307 | 12091 | #define GPIO_IDR_IDR_3 GPIO_IDR_ID3 |
| AnnaBridge | 167:e84263d55307 | 12092 | #define GPIO_IDR_IDR_4 GPIO_IDR_ID4 |
| AnnaBridge | 167:e84263d55307 | 12093 | #define GPIO_IDR_IDR_5 GPIO_IDR_ID5 |
| AnnaBridge | 167:e84263d55307 | 12094 | #define GPIO_IDR_IDR_6 GPIO_IDR_ID6 |
| AnnaBridge | 167:e84263d55307 | 12095 | #define GPIO_IDR_IDR_7 GPIO_IDR_ID7 |
| AnnaBridge | 167:e84263d55307 | 12096 | #define GPIO_IDR_IDR_8 GPIO_IDR_ID8 |
| AnnaBridge | 167:e84263d55307 | 12097 | #define GPIO_IDR_IDR_9 GPIO_IDR_ID9 |
| AnnaBridge | 167:e84263d55307 | 12098 | #define GPIO_IDR_IDR_10 GPIO_IDR_ID10 |
| AnnaBridge | 167:e84263d55307 | 12099 | #define GPIO_IDR_IDR_11 GPIO_IDR_ID11 |
| AnnaBridge | 167:e84263d55307 | 12100 | #define GPIO_IDR_IDR_12 GPIO_IDR_ID12 |
| AnnaBridge | 167:e84263d55307 | 12101 | #define GPIO_IDR_IDR_13 GPIO_IDR_ID13 |
| AnnaBridge | 167:e84263d55307 | 12102 | #define GPIO_IDR_IDR_14 GPIO_IDR_ID14 |
| AnnaBridge | 167:e84263d55307 | 12103 | #define GPIO_IDR_IDR_15 GPIO_IDR_ID15 |
| mbed_official | 19:112740acecfa | 12104 | |
| mbed_official | 19:112740acecfa | 12105 | /****************** Bits definition for GPIO_ODR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 12106 | #define GPIO_ODR_OD0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12107 | #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12108 | #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk |
| AnnaBridge | 167:e84263d55307 | 12109 | #define GPIO_ODR_OD1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12110 | #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12111 | #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk |
| AnnaBridge | 167:e84263d55307 | 12112 | #define GPIO_ODR_OD2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12113 | #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12114 | #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk |
| AnnaBridge | 167:e84263d55307 | 12115 | #define GPIO_ODR_OD3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12116 | #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12117 | #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk |
| AnnaBridge | 167:e84263d55307 | 12118 | #define GPIO_ODR_OD4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12119 | #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12120 | #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk |
| AnnaBridge | 167:e84263d55307 | 12121 | #define GPIO_ODR_OD5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 12122 | #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12123 | #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk |
| AnnaBridge | 167:e84263d55307 | 12124 | #define GPIO_ODR_OD6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 12125 | #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12126 | #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk |
| AnnaBridge | 167:e84263d55307 | 12127 | #define GPIO_ODR_OD7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 12128 | #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12129 | #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk |
| AnnaBridge | 167:e84263d55307 | 12130 | #define GPIO_ODR_OD8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12131 | #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12132 | #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk |
| AnnaBridge | 167:e84263d55307 | 12133 | #define GPIO_ODR_OD9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 12134 | #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12135 | #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk |
| AnnaBridge | 167:e84263d55307 | 12136 | #define GPIO_ODR_OD10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 12137 | #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 12138 | #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk |
| AnnaBridge | 167:e84263d55307 | 12139 | #define GPIO_ODR_OD11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 12140 | #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 12141 | #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk |
| AnnaBridge | 167:e84263d55307 | 12142 | #define GPIO_ODR_OD12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12143 | #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 12144 | #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk |
| AnnaBridge | 167:e84263d55307 | 12145 | #define GPIO_ODR_OD13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 12146 | #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 12147 | #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk |
| AnnaBridge | 167:e84263d55307 | 12148 | #define GPIO_ODR_OD14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 12149 | #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 12150 | #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk |
| AnnaBridge | 167:e84263d55307 | 12151 | #define GPIO_ODR_OD15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 12152 | #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12153 | #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk |
| AnnaBridge | 167:e84263d55307 | 12154 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 12155 | #define GPIO_ODR_ODR_0 GPIO_ODR_OD0 |
| AnnaBridge | 167:e84263d55307 | 12156 | #define GPIO_ODR_ODR_1 GPIO_ODR_OD1 |
| AnnaBridge | 167:e84263d55307 | 12157 | #define GPIO_ODR_ODR_2 GPIO_ODR_OD2 |
| AnnaBridge | 167:e84263d55307 | 12158 | #define GPIO_ODR_ODR_3 GPIO_ODR_OD3 |
| AnnaBridge | 167:e84263d55307 | 12159 | #define GPIO_ODR_ODR_4 GPIO_ODR_OD4 |
| AnnaBridge | 167:e84263d55307 | 12160 | #define GPIO_ODR_ODR_5 GPIO_ODR_OD5 |
| AnnaBridge | 167:e84263d55307 | 12161 | #define GPIO_ODR_ODR_6 GPIO_ODR_OD6 |
| AnnaBridge | 167:e84263d55307 | 12162 | #define GPIO_ODR_ODR_7 GPIO_ODR_OD7 |
| AnnaBridge | 167:e84263d55307 | 12163 | #define GPIO_ODR_ODR_8 GPIO_ODR_OD8 |
| AnnaBridge | 167:e84263d55307 | 12164 | #define GPIO_ODR_ODR_9 GPIO_ODR_OD9 |
| AnnaBridge | 167:e84263d55307 | 12165 | #define GPIO_ODR_ODR_10 GPIO_ODR_OD10 |
| AnnaBridge | 167:e84263d55307 | 12166 | #define GPIO_ODR_ODR_11 GPIO_ODR_OD11 |
| AnnaBridge | 167:e84263d55307 | 12167 | #define GPIO_ODR_ODR_12 GPIO_ODR_OD12 |
| AnnaBridge | 167:e84263d55307 | 12168 | #define GPIO_ODR_ODR_13 GPIO_ODR_OD13 |
| AnnaBridge | 167:e84263d55307 | 12169 | #define GPIO_ODR_ODR_14 GPIO_ODR_OD14 |
| AnnaBridge | 167:e84263d55307 | 12170 | #define GPIO_ODR_ODR_15 GPIO_ODR_OD15 |
| mbed_official | 19:112740acecfa | 12171 | |
| mbed_official | 19:112740acecfa | 12172 | /****************** Bits definition for GPIO_BSRR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 12173 | #define GPIO_BSRR_BS0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12174 | #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12175 | #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk |
| AnnaBridge | 167:e84263d55307 | 12176 | #define GPIO_BSRR_BS1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12177 | #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12178 | #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk |
| AnnaBridge | 167:e84263d55307 | 12179 | #define GPIO_BSRR_BS2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12180 | #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12181 | #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk |
| AnnaBridge | 167:e84263d55307 | 12182 | #define GPIO_BSRR_BS3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12183 | #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12184 | #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk |
| AnnaBridge | 167:e84263d55307 | 12185 | #define GPIO_BSRR_BS4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12186 | #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12187 | #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk |
| AnnaBridge | 167:e84263d55307 | 12188 | #define GPIO_BSRR_BS5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 12189 | #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12190 | #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk |
| AnnaBridge | 167:e84263d55307 | 12191 | #define GPIO_BSRR_BS6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 12192 | #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12193 | #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk |
| AnnaBridge | 167:e84263d55307 | 12194 | #define GPIO_BSRR_BS7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 12195 | #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12196 | #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk |
| AnnaBridge | 167:e84263d55307 | 12197 | #define GPIO_BSRR_BS8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12198 | #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12199 | #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk |
| AnnaBridge | 167:e84263d55307 | 12200 | #define GPIO_BSRR_BS9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 12201 | #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12202 | #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk |
| AnnaBridge | 167:e84263d55307 | 12203 | #define GPIO_BSRR_BS10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 12204 | #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 12205 | #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk |
| AnnaBridge | 167:e84263d55307 | 12206 | #define GPIO_BSRR_BS11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 12207 | #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 12208 | #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk |
| AnnaBridge | 167:e84263d55307 | 12209 | #define GPIO_BSRR_BS12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12210 | #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 12211 | #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk |
| AnnaBridge | 167:e84263d55307 | 12212 | #define GPIO_BSRR_BS13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 12213 | #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 12214 | #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk |
| AnnaBridge | 167:e84263d55307 | 12215 | #define GPIO_BSRR_BS14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 12216 | #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 12217 | #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk |
| AnnaBridge | 167:e84263d55307 | 12218 | #define GPIO_BSRR_BS15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 12219 | #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12220 | #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk |
| AnnaBridge | 167:e84263d55307 | 12221 | #define GPIO_BSRR_BR0_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 12222 | #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 12223 | #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk |
| AnnaBridge | 167:e84263d55307 | 12224 | #define GPIO_BSRR_BR1_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 12225 | #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 12226 | #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk |
| AnnaBridge | 167:e84263d55307 | 12227 | #define GPIO_BSRR_BR2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 12228 | #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 12229 | #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk |
| AnnaBridge | 167:e84263d55307 | 12230 | #define GPIO_BSRR_BR3_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 12231 | #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 12232 | #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk |
| AnnaBridge | 167:e84263d55307 | 12233 | #define GPIO_BSRR_BR4_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 12234 | #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 12235 | #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk |
| AnnaBridge | 167:e84263d55307 | 12236 | #define GPIO_BSRR_BR5_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 12237 | #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 12238 | #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk |
| AnnaBridge | 167:e84263d55307 | 12239 | #define GPIO_BSRR_BR6_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 12240 | #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 12241 | #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk |
| AnnaBridge | 167:e84263d55307 | 12242 | #define GPIO_BSRR_BR7_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 12243 | #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 12244 | #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk |
| AnnaBridge | 167:e84263d55307 | 12245 | #define GPIO_BSRR_BR8_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 12246 | #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 12247 | #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk |
| AnnaBridge | 167:e84263d55307 | 12248 | #define GPIO_BSRR_BR9_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 12249 | #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 12250 | #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk |
| AnnaBridge | 167:e84263d55307 | 12251 | #define GPIO_BSRR_BR10_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 12252 | #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 12253 | #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk |
| AnnaBridge | 167:e84263d55307 | 12254 | #define GPIO_BSRR_BR11_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 12255 | #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 12256 | #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk |
| AnnaBridge | 167:e84263d55307 | 12257 | #define GPIO_BSRR_BR12_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 12258 | #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 12259 | #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk |
| AnnaBridge | 167:e84263d55307 | 12260 | #define GPIO_BSRR_BR13_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 12261 | #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 12262 | #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk |
| AnnaBridge | 167:e84263d55307 | 12263 | #define GPIO_BSRR_BR14_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 12264 | #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 12265 | #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk |
| AnnaBridge | 167:e84263d55307 | 12266 | #define GPIO_BSRR_BR15_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 12267 | #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 12268 | #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk |
| AnnaBridge | 167:e84263d55307 | 12269 | |
| AnnaBridge | 167:e84263d55307 | 12270 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 12271 | #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0 |
| AnnaBridge | 167:e84263d55307 | 12272 | #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1 |
| AnnaBridge | 167:e84263d55307 | 12273 | #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2 |
| AnnaBridge | 167:e84263d55307 | 12274 | #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3 |
| AnnaBridge | 167:e84263d55307 | 12275 | #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4 |
| AnnaBridge | 167:e84263d55307 | 12276 | #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5 |
| AnnaBridge | 167:e84263d55307 | 12277 | #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6 |
| AnnaBridge | 167:e84263d55307 | 12278 | #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7 |
| AnnaBridge | 167:e84263d55307 | 12279 | #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8 |
| AnnaBridge | 167:e84263d55307 | 12280 | #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9 |
| AnnaBridge | 167:e84263d55307 | 12281 | #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10 |
| AnnaBridge | 167:e84263d55307 | 12282 | #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11 |
| AnnaBridge | 167:e84263d55307 | 12283 | #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12 |
| AnnaBridge | 167:e84263d55307 | 12284 | #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13 |
| AnnaBridge | 167:e84263d55307 | 12285 | #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14 |
| AnnaBridge | 167:e84263d55307 | 12286 | #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15 |
| AnnaBridge | 167:e84263d55307 | 12287 | #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0 |
| AnnaBridge | 167:e84263d55307 | 12288 | #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1 |
| AnnaBridge | 167:e84263d55307 | 12289 | #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2 |
| AnnaBridge | 167:e84263d55307 | 12290 | #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3 |
| AnnaBridge | 167:e84263d55307 | 12291 | #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4 |
| AnnaBridge | 167:e84263d55307 | 12292 | #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5 |
| AnnaBridge | 167:e84263d55307 | 12293 | #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6 |
| AnnaBridge | 167:e84263d55307 | 12294 | #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7 |
| AnnaBridge | 167:e84263d55307 | 12295 | #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8 |
| AnnaBridge | 167:e84263d55307 | 12296 | #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9 |
| AnnaBridge | 167:e84263d55307 | 12297 | #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10 |
| AnnaBridge | 167:e84263d55307 | 12298 | #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11 |
| AnnaBridge | 167:e84263d55307 | 12299 | #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12 |
| AnnaBridge | 167:e84263d55307 | 12300 | #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13 |
| AnnaBridge | 167:e84263d55307 | 12301 | #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14 |
| AnnaBridge | 167:e84263d55307 | 12302 | #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15 |
| mbed_official | 19:112740acecfa | 12303 | /****************** Bit definition for GPIO_LCKR register *********************/ |
| AnnaBridge | 167:e84263d55307 | 12304 | #define GPIO_LCKR_LCK0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12305 | #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12306 | #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk |
| AnnaBridge | 167:e84263d55307 | 12307 | #define GPIO_LCKR_LCK1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12308 | #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12309 | #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk |
| AnnaBridge | 167:e84263d55307 | 12310 | #define GPIO_LCKR_LCK2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12311 | #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12312 | #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk |
| AnnaBridge | 167:e84263d55307 | 12313 | #define GPIO_LCKR_LCK3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12314 | #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12315 | #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk |
| AnnaBridge | 167:e84263d55307 | 12316 | #define GPIO_LCKR_LCK4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12317 | #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12318 | #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk |
| AnnaBridge | 167:e84263d55307 | 12319 | #define GPIO_LCKR_LCK5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 12320 | #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12321 | #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk |
| AnnaBridge | 167:e84263d55307 | 12322 | #define GPIO_LCKR_LCK6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 12323 | #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12324 | #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk |
| AnnaBridge | 167:e84263d55307 | 12325 | #define GPIO_LCKR_LCK7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 12326 | #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12327 | #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk |
| AnnaBridge | 167:e84263d55307 | 12328 | #define GPIO_LCKR_LCK8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12329 | #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12330 | #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk |
| AnnaBridge | 167:e84263d55307 | 12331 | #define GPIO_LCKR_LCK9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 12332 | #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12333 | #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk |
| AnnaBridge | 167:e84263d55307 | 12334 | #define GPIO_LCKR_LCK10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 12335 | #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 12336 | #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk |
| AnnaBridge | 167:e84263d55307 | 12337 | #define GPIO_LCKR_LCK11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 12338 | #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 12339 | #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk |
| AnnaBridge | 167:e84263d55307 | 12340 | #define GPIO_LCKR_LCK12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12341 | #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 12342 | #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk |
| AnnaBridge | 167:e84263d55307 | 12343 | #define GPIO_LCKR_LCK13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 12344 | #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 12345 | #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk |
| AnnaBridge | 167:e84263d55307 | 12346 | #define GPIO_LCKR_LCK14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 12347 | #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 12348 | #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk |
| AnnaBridge | 167:e84263d55307 | 12349 | #define GPIO_LCKR_LCK15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 12350 | #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12351 | #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk |
| AnnaBridge | 167:e84263d55307 | 12352 | #define GPIO_LCKR_LCKK_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 12353 | #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 12354 | #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk |
| AnnaBridge | 167:e84263d55307 | 12355 | /****************** Bit definition for GPIO_AFRL register *********************/ |
| AnnaBridge | 167:e84263d55307 | 12356 | #define GPIO_AFRL_AFSEL0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12357 | #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 12358 | #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk |
| AnnaBridge | 167:e84263d55307 | 12359 | #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12360 | #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12361 | #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12362 | #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12363 | #define GPIO_AFRL_AFSEL1_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12364 | #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 12365 | #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk |
| AnnaBridge | 167:e84263d55307 | 12366 | #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12367 | #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12368 | #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12369 | #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12370 | #define GPIO_AFRL_AFSEL2_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12371 | #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 12372 | #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk |
| AnnaBridge | 167:e84263d55307 | 12373 | #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12374 | #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12375 | #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 12376 | #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 12377 | #define GPIO_AFRL_AFSEL3_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12378 | #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 167:e84263d55307 | 12379 | #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk |
| AnnaBridge | 167:e84263d55307 | 12380 | #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 12381 | #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 12382 | #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 12383 | #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12384 | #define GPIO_AFRL_AFSEL4_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 12385 | #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 12386 | #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk |
| AnnaBridge | 167:e84263d55307 | 12387 | #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 12388 | #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 12389 | #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 12390 | #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 12391 | #define GPIO_AFRL_AFSEL5_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 12392 | #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 12393 | #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk |
| AnnaBridge | 167:e84263d55307 | 12394 | #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 12395 | #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 12396 | #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 12397 | #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 12398 | #define GPIO_AFRL_AFSEL6_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 12399 | #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 12400 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
| AnnaBridge | 167:e84263d55307 | 12401 | #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 12402 | #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 12403 | #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 12404 | #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 12405 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 12406 | #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
| AnnaBridge | 167:e84263d55307 | 12407 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
| AnnaBridge | 167:e84263d55307 | 12408 | #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 12409 | #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 12410 | #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 12411 | #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 12412 | |
| AnnaBridge | 167:e84263d55307 | 12413 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 12414 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
| AnnaBridge | 167:e84263d55307 | 12415 | #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0 |
| AnnaBridge | 167:e84263d55307 | 12416 | #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1 |
| AnnaBridge | 167:e84263d55307 | 12417 | #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2 |
| AnnaBridge | 167:e84263d55307 | 12418 | #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3 |
| AnnaBridge | 167:e84263d55307 | 12419 | #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 |
| AnnaBridge | 167:e84263d55307 | 12420 | #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0 |
| AnnaBridge | 167:e84263d55307 | 12421 | #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1 |
| AnnaBridge | 167:e84263d55307 | 12422 | #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2 |
| AnnaBridge | 167:e84263d55307 | 12423 | #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3 |
| AnnaBridge | 167:e84263d55307 | 12424 | #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 |
| AnnaBridge | 167:e84263d55307 | 12425 | #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0 |
| AnnaBridge | 167:e84263d55307 | 12426 | #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1 |
| AnnaBridge | 167:e84263d55307 | 12427 | #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2 |
| AnnaBridge | 167:e84263d55307 | 12428 | #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3 |
| AnnaBridge | 167:e84263d55307 | 12429 | #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 |
| AnnaBridge | 167:e84263d55307 | 12430 | #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0 |
| AnnaBridge | 167:e84263d55307 | 12431 | #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1 |
| AnnaBridge | 167:e84263d55307 | 12432 | #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2 |
| AnnaBridge | 167:e84263d55307 | 12433 | #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3 |
| AnnaBridge | 167:e84263d55307 | 12434 | #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 |
| AnnaBridge | 167:e84263d55307 | 12435 | #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0 |
| AnnaBridge | 167:e84263d55307 | 12436 | #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1 |
| AnnaBridge | 167:e84263d55307 | 12437 | #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2 |
| AnnaBridge | 167:e84263d55307 | 12438 | #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3 |
| AnnaBridge | 167:e84263d55307 | 12439 | #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 |
| AnnaBridge | 167:e84263d55307 | 12440 | #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0 |
| AnnaBridge | 167:e84263d55307 | 12441 | #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1 |
| AnnaBridge | 167:e84263d55307 | 12442 | #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2 |
| AnnaBridge | 167:e84263d55307 | 12443 | #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3 |
| AnnaBridge | 167:e84263d55307 | 12444 | #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 |
| AnnaBridge | 167:e84263d55307 | 12445 | #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0 |
| AnnaBridge | 167:e84263d55307 | 12446 | #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1 |
| AnnaBridge | 167:e84263d55307 | 12447 | #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2 |
| AnnaBridge | 167:e84263d55307 | 12448 | #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3 |
| AnnaBridge | 167:e84263d55307 | 12449 | #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 |
| AnnaBridge | 167:e84263d55307 | 12450 | #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0 |
| AnnaBridge | 167:e84263d55307 | 12451 | #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1 |
| AnnaBridge | 167:e84263d55307 | 12452 | #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2 |
| AnnaBridge | 167:e84263d55307 | 12453 | #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3 |
| AnnaBridge | 167:e84263d55307 | 12454 | |
| AnnaBridge | 167:e84263d55307 | 12455 | /****************** Bit definition for GPIO_AFRH register *********************/ |
| AnnaBridge | 167:e84263d55307 | 12456 | #define GPIO_AFRH_AFSEL8_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12457 | #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 12458 | #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk |
| AnnaBridge | 167:e84263d55307 | 12459 | #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12460 | #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12461 | #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12462 | #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12463 | #define GPIO_AFRH_AFSEL9_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12464 | #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 12465 | #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk |
| AnnaBridge | 167:e84263d55307 | 12466 | #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12467 | #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12468 | #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12469 | #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12470 | #define GPIO_AFRH_AFSEL10_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12471 | #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 12472 | #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk |
| AnnaBridge | 167:e84263d55307 | 12473 | #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12474 | #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12475 | #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 12476 | #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 12477 | #define GPIO_AFRH_AFSEL11_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12478 | #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 167:e84263d55307 | 12479 | #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk |
| AnnaBridge | 167:e84263d55307 | 12480 | #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 12481 | #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 12482 | #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 12483 | #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12484 | #define GPIO_AFRH_AFSEL12_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 12485 | #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 12486 | #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk |
| AnnaBridge | 167:e84263d55307 | 12487 | #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 12488 | #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 12489 | #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 12490 | #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 12491 | #define GPIO_AFRH_AFSEL13_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 12492 | #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 12493 | #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk |
| AnnaBridge | 167:e84263d55307 | 12494 | #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 12495 | #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 12496 | #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 12497 | #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 12498 | #define GPIO_AFRH_AFSEL14_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 12499 | #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 12500 | #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk |
| AnnaBridge | 167:e84263d55307 | 12501 | #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 12502 | #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 12503 | #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 12504 | #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 12505 | #define GPIO_AFRH_AFSEL15_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 12506 | #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ |
| AnnaBridge | 167:e84263d55307 | 12507 | #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk |
| AnnaBridge | 167:e84263d55307 | 12508 | #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 12509 | #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 12510 | #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 12511 | #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 12512 | |
| AnnaBridge | 167:e84263d55307 | 12513 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 12514 | #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 |
| AnnaBridge | 167:e84263d55307 | 12515 | #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0 |
| AnnaBridge | 167:e84263d55307 | 12516 | #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1 |
| AnnaBridge | 167:e84263d55307 | 12517 | #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2 |
| AnnaBridge | 167:e84263d55307 | 12518 | #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3 |
| AnnaBridge | 167:e84263d55307 | 12519 | #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 |
| AnnaBridge | 167:e84263d55307 | 12520 | #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0 |
| AnnaBridge | 167:e84263d55307 | 12521 | #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1 |
| AnnaBridge | 167:e84263d55307 | 12522 | #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2 |
| AnnaBridge | 167:e84263d55307 | 12523 | #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3 |
| AnnaBridge | 167:e84263d55307 | 12524 | #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 |
| AnnaBridge | 167:e84263d55307 | 12525 | #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0 |
| AnnaBridge | 167:e84263d55307 | 12526 | #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1 |
| AnnaBridge | 167:e84263d55307 | 12527 | #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2 |
| AnnaBridge | 167:e84263d55307 | 12528 | #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3 |
| AnnaBridge | 167:e84263d55307 | 12529 | #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 |
| AnnaBridge | 167:e84263d55307 | 12530 | #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0 |
| AnnaBridge | 167:e84263d55307 | 12531 | #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1 |
| AnnaBridge | 167:e84263d55307 | 12532 | #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2 |
| AnnaBridge | 167:e84263d55307 | 12533 | #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3 |
| AnnaBridge | 167:e84263d55307 | 12534 | #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 |
| AnnaBridge | 167:e84263d55307 | 12535 | #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0 |
| AnnaBridge | 167:e84263d55307 | 12536 | #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1 |
| AnnaBridge | 167:e84263d55307 | 12537 | #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2 |
| AnnaBridge | 167:e84263d55307 | 12538 | #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3 |
| AnnaBridge | 167:e84263d55307 | 12539 | #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 |
| AnnaBridge | 167:e84263d55307 | 12540 | #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0 |
| AnnaBridge | 167:e84263d55307 | 12541 | #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1 |
| AnnaBridge | 167:e84263d55307 | 12542 | #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2 |
| AnnaBridge | 167:e84263d55307 | 12543 | #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3 |
| AnnaBridge | 167:e84263d55307 | 12544 | #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 |
| AnnaBridge | 167:e84263d55307 | 12545 | #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0 |
| AnnaBridge | 167:e84263d55307 | 12546 | #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1 |
| AnnaBridge | 167:e84263d55307 | 12547 | #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2 |
| AnnaBridge | 167:e84263d55307 | 12548 | #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3 |
| AnnaBridge | 167:e84263d55307 | 12549 | #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 |
| AnnaBridge | 167:e84263d55307 | 12550 | #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0 |
| AnnaBridge | 167:e84263d55307 | 12551 | #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1 |
| AnnaBridge | 167:e84263d55307 | 12552 | #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2 |
| AnnaBridge | 167:e84263d55307 | 12553 | #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3 |
| AnnaBridge | 167:e84263d55307 | 12554 | |
| AnnaBridge | 167:e84263d55307 | 12555 | /****************** Bits definition for GPIO_BRR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 12556 | #define GPIO_BRR_BR0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12557 | #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12558 | #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk |
| AnnaBridge | 167:e84263d55307 | 12559 | #define GPIO_BRR_BR1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12560 | #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12561 | #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk |
| AnnaBridge | 167:e84263d55307 | 12562 | #define GPIO_BRR_BR2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12563 | #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12564 | #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk |
| AnnaBridge | 167:e84263d55307 | 12565 | #define GPIO_BRR_BR3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12566 | #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12567 | #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk |
| AnnaBridge | 167:e84263d55307 | 12568 | #define GPIO_BRR_BR4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12569 | #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12570 | #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk |
| AnnaBridge | 167:e84263d55307 | 12571 | #define GPIO_BRR_BR5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 12572 | #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12573 | #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk |
| AnnaBridge | 167:e84263d55307 | 12574 | #define GPIO_BRR_BR6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 12575 | #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12576 | #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk |
| AnnaBridge | 167:e84263d55307 | 12577 | #define GPIO_BRR_BR7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 12578 | #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12579 | #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk |
| AnnaBridge | 167:e84263d55307 | 12580 | #define GPIO_BRR_BR8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12581 | #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12582 | #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk |
| AnnaBridge | 167:e84263d55307 | 12583 | #define GPIO_BRR_BR9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 12584 | #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12585 | #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk |
| AnnaBridge | 167:e84263d55307 | 12586 | #define GPIO_BRR_BR10_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 12587 | #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 12588 | #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk |
| AnnaBridge | 167:e84263d55307 | 12589 | #define GPIO_BRR_BR11_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 12590 | #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 12591 | #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk |
| AnnaBridge | 167:e84263d55307 | 12592 | #define GPIO_BRR_BR12_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12593 | #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 12594 | #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk |
| AnnaBridge | 167:e84263d55307 | 12595 | #define GPIO_BRR_BR13_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 12596 | #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 12597 | #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk |
| AnnaBridge | 167:e84263d55307 | 12598 | #define GPIO_BRR_BR14_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 12599 | #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 12600 | #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk |
| AnnaBridge | 167:e84263d55307 | 12601 | #define GPIO_BRR_BR15_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 12602 | #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12603 | #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk |
| AnnaBridge | 167:e84263d55307 | 12604 | |
| mbed_official | 19:112740acecfa | 12605 | |
| mbed_official | 19:112740acecfa | 12606 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 12607 | /* */ |
| mbed_official | 19:112740acecfa | 12608 | /* Inter-integrated Circuit Interface */ |
| mbed_official | 19:112740acecfa | 12609 | /* */ |
| mbed_official | 19:112740acecfa | 12610 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 12611 | /******************* Bit definition for I2C_CR1 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 12612 | #define I2C_CR1_PE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12613 | #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12614 | #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */ |
| AnnaBridge | 167:e84263d55307 | 12615 | #define I2C_CR1_SMBUS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12616 | #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12617 | #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */ |
| AnnaBridge | 167:e84263d55307 | 12618 | #define I2C_CR1_SMBTYPE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12619 | #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12620 | #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */ |
| AnnaBridge | 167:e84263d55307 | 12621 | #define I2C_CR1_ENARP_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12622 | #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12623 | #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */ |
| AnnaBridge | 167:e84263d55307 | 12624 | #define I2C_CR1_ENPEC_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 12625 | #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12626 | #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */ |
| AnnaBridge | 167:e84263d55307 | 12627 | #define I2C_CR1_ENGC_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 12628 | #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12629 | #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */ |
| AnnaBridge | 167:e84263d55307 | 12630 | #define I2C_CR1_NOSTRETCH_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 12631 | #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12632 | #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */ |
| AnnaBridge | 167:e84263d55307 | 12633 | #define I2C_CR1_START_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12634 | #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12635 | #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */ |
| AnnaBridge | 167:e84263d55307 | 12636 | #define I2C_CR1_STOP_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 12637 | #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12638 | #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */ |
| AnnaBridge | 167:e84263d55307 | 12639 | #define I2C_CR1_ACK_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 12640 | #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 12641 | #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */ |
| AnnaBridge | 167:e84263d55307 | 12642 | #define I2C_CR1_POS_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 12643 | #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 12644 | #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */ |
| AnnaBridge | 167:e84263d55307 | 12645 | #define I2C_CR1_PEC_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12646 | #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 12647 | #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */ |
| AnnaBridge | 167:e84263d55307 | 12648 | #define I2C_CR1_ALERT_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 12649 | #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 12650 | #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */ |
| AnnaBridge | 167:e84263d55307 | 12651 | #define I2C_CR1_SWRST_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 12652 | #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12653 | #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */ |
| mbed_official | 19:112740acecfa | 12654 | |
| mbed_official | 19:112740acecfa | 12655 | /******************* Bit definition for I2C_CR2 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 12656 | #define I2C_CR2_FREQ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12657 | #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 167:e84263d55307 | 12658 | #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ |
| AnnaBridge | 167:e84263d55307 | 12659 | #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12660 | #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12661 | #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12662 | #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12663 | #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12664 | #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12665 | |
| AnnaBridge | 167:e84263d55307 | 12666 | #define I2C_CR2_ITERREN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12667 | #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12668 | #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 12669 | #define I2C_CR2_ITEVTEN_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 12670 | #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12671 | #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 12672 | #define I2C_CR2_ITBUFEN_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 12673 | #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 12674 | #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 12675 | #define I2C_CR2_DMAEN_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 12676 | #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 12677 | #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */ |
| AnnaBridge | 167:e84263d55307 | 12678 | #define I2C_CR2_LAST_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12679 | #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 12680 | #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */ |
| mbed_official | 19:112740acecfa | 12681 | |
| mbed_official | 19:112740acecfa | 12682 | /******************* Bit definition for I2C_OAR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 12683 | #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */ |
| AnnaBridge | 167:e84263d55307 | 12684 | #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */ |
| AnnaBridge | 167:e84263d55307 | 12685 | |
| AnnaBridge | 167:e84263d55307 | 12686 | #define I2C_OAR1_ADD0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12687 | #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12688 | #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 12689 | #define I2C_OAR1_ADD1_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12690 | #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12691 | #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 12692 | #define I2C_OAR1_ADD2_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12693 | #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12694 | #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */ |
| AnnaBridge | 167:e84263d55307 | 12695 | #define I2C_OAR1_ADD3_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12696 | #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12697 | #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */ |
| AnnaBridge | 167:e84263d55307 | 12698 | #define I2C_OAR1_ADD4_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12699 | #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12700 | #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */ |
| AnnaBridge | 167:e84263d55307 | 12701 | #define I2C_OAR1_ADD5_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 12702 | #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12703 | #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */ |
| AnnaBridge | 167:e84263d55307 | 12704 | #define I2C_OAR1_ADD6_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 12705 | #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12706 | #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */ |
| AnnaBridge | 167:e84263d55307 | 12707 | #define I2C_OAR1_ADD7_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 12708 | #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12709 | #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */ |
| AnnaBridge | 167:e84263d55307 | 12710 | #define I2C_OAR1_ADD8_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12711 | #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12712 | #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */ |
| AnnaBridge | 167:e84263d55307 | 12713 | #define I2C_OAR1_ADD9_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 12714 | #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12715 | #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */ |
| AnnaBridge | 167:e84263d55307 | 12716 | |
| AnnaBridge | 167:e84263d55307 | 12717 | #define I2C_OAR1_ADDMODE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 12718 | #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12719 | #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */ |
| mbed_official | 19:112740acecfa | 12720 | |
| mbed_official | 19:112740acecfa | 12721 | /******************* Bit definition for I2C_OAR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 12722 | #define I2C_OAR2_ENDUAL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12723 | #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12724 | #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */ |
| AnnaBridge | 167:e84263d55307 | 12725 | #define I2C_OAR2_ADD2_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12726 | #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ |
| AnnaBridge | 167:e84263d55307 | 12727 | #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */ |
| mbed_official | 19:112740acecfa | 12728 | |
| mbed_official | 19:112740acecfa | 12729 | /******************** Bit definition for I2C_DR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 12730 | #define I2C_DR_DR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12731 | #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 12732 | #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */ |
| mbed_official | 19:112740acecfa | 12733 | |
| mbed_official | 19:112740acecfa | 12734 | /******************* Bit definition for I2C_SR1 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 12735 | #define I2C_SR1_SB_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12736 | #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12737 | #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */ |
| AnnaBridge | 167:e84263d55307 | 12738 | #define I2C_SR1_ADDR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12739 | #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12740 | #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */ |
| AnnaBridge | 167:e84263d55307 | 12741 | #define I2C_SR1_BTF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12742 | #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12743 | #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */ |
| AnnaBridge | 167:e84263d55307 | 12744 | #define I2C_SR1_ADD10_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12745 | #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12746 | #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */ |
| AnnaBridge | 167:e84263d55307 | 12747 | #define I2C_SR1_STOPF_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12748 | #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12749 | #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */ |
| AnnaBridge | 167:e84263d55307 | 12750 | #define I2C_SR1_RXNE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 12751 | #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12752 | #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */ |
| AnnaBridge | 167:e84263d55307 | 12753 | #define I2C_SR1_TXE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 12754 | #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12755 | #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */ |
| AnnaBridge | 167:e84263d55307 | 12756 | #define I2C_SR1_BERR_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12757 | #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 12758 | #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */ |
| AnnaBridge | 167:e84263d55307 | 12759 | #define I2C_SR1_ARLO_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 12760 | #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 12761 | #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */ |
| AnnaBridge | 167:e84263d55307 | 12762 | #define I2C_SR1_AF_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 12763 | #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 12764 | #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */ |
| AnnaBridge | 167:e84263d55307 | 12765 | #define I2C_SR1_OVR_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 12766 | #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 12767 | #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */ |
| AnnaBridge | 167:e84263d55307 | 12768 | #define I2C_SR1_PECERR_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12769 | #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 12770 | #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */ |
| AnnaBridge | 167:e84263d55307 | 12771 | #define I2C_SR1_TIMEOUT_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 12772 | #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 12773 | #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */ |
| AnnaBridge | 167:e84263d55307 | 12774 | #define I2C_SR1_SMBALERT_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 12775 | #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12776 | #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */ |
| mbed_official | 19:112740acecfa | 12777 | |
| mbed_official | 19:112740acecfa | 12778 | /******************* Bit definition for I2C_SR2 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 12779 | #define I2C_SR2_MSL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12780 | #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12781 | #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */ |
| AnnaBridge | 167:e84263d55307 | 12782 | #define I2C_SR2_BUSY_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12783 | #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12784 | #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */ |
| AnnaBridge | 167:e84263d55307 | 12785 | #define I2C_SR2_TRA_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12786 | #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12787 | #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */ |
| AnnaBridge | 167:e84263d55307 | 12788 | #define I2C_SR2_GENCALL_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12789 | #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12790 | #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */ |
| AnnaBridge | 167:e84263d55307 | 12791 | #define I2C_SR2_SMBDEFAULT_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 12792 | #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 12793 | #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */ |
| AnnaBridge | 167:e84263d55307 | 12794 | #define I2C_SR2_SMBHOST_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 12795 | #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 12796 | #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */ |
| AnnaBridge | 167:e84263d55307 | 12797 | #define I2C_SR2_DUALF_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 12798 | #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 12799 | #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */ |
| AnnaBridge | 167:e84263d55307 | 12800 | #define I2C_SR2_PEC_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12801 | #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 12802 | #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */ |
| mbed_official | 19:112740acecfa | 12803 | |
| mbed_official | 19:112740acecfa | 12804 | /******************* Bit definition for I2C_CCR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 12805 | #define I2C_CCR_CCR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12806 | #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 12807 | #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */ |
| AnnaBridge | 167:e84263d55307 | 12808 | #define I2C_CCR_DUTY_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 12809 | #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 12810 | #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */ |
| AnnaBridge | 167:e84263d55307 | 12811 | #define I2C_CCR_FS_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 12812 | #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 12813 | #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */ |
| mbed_official | 19:112740acecfa | 12814 | |
| mbed_official | 19:112740acecfa | 12815 | /****************** Bit definition for I2C_TRISE register *******************/ |
| AnnaBridge | 167:e84263d55307 | 12816 | #define I2C_TRISE_TRISE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12817 | #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 167:e84263d55307 | 12818 | #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ |
| mbed_official | 19:112740acecfa | 12819 | |
| mbed_official | 19:112740acecfa | 12820 | /****************** Bit definition for I2C_FLTR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 12821 | #define I2C_FLTR_DNF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12822 | #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 12823 | #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */ |
| AnnaBridge | 167:e84263d55307 | 12824 | #define I2C_FLTR_ANOFF_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12825 | #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 12826 | #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */ |
| mbed_official | 19:112740acecfa | 12827 | |
| mbed_official | 19:112740acecfa | 12828 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 12829 | /* */ |
| mbed_official | 19:112740acecfa | 12830 | /* Independent WATCHDOG */ |
| mbed_official | 19:112740acecfa | 12831 | /* */ |
| mbed_official | 19:112740acecfa | 12832 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 12833 | /******************* Bit definition for IWDG_KR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 12834 | #define IWDG_KR_KEY_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12835 | #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 12836 | #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ |
| mbed_official | 19:112740acecfa | 12837 | |
| mbed_official | 19:112740acecfa | 12838 | /******************* Bit definition for IWDG_PR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 12839 | #define IWDG_PR_PR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12840 | #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 12841 | #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ |
| AnnaBridge | 167:e84263d55307 | 12842 | #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */ |
| AnnaBridge | 167:e84263d55307 | 12843 | #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */ |
| AnnaBridge | 167:e84263d55307 | 12844 | #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */ |
| mbed_official | 19:112740acecfa | 12845 | |
| mbed_official | 19:112740acecfa | 12846 | /******************* Bit definition for IWDG_RLR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 12847 | #define IWDG_RLR_RL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12848 | #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 12849 | #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ |
| mbed_official | 19:112740acecfa | 12850 | |
| mbed_official | 19:112740acecfa | 12851 | /******************* Bit definition for IWDG_SR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 12852 | #define IWDG_SR_PVU_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12853 | #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12854 | #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */ |
| AnnaBridge | 167:e84263d55307 | 12855 | #define IWDG_SR_RVU_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12856 | #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12857 | #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */ |
| mbed_official | 19:112740acecfa | 12858 | |
| mbed_official | 19:112740acecfa | 12859 | |
| mbed_official | 19:112740acecfa | 12860 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 12861 | /* */ |
| mbed_official | 19:112740acecfa | 12862 | /* LCD-TFT Display Controller (LTDC) */ |
| mbed_official | 19:112740acecfa | 12863 | /* */ |
| mbed_official | 19:112740acecfa | 12864 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 12865 | |
| mbed_official | 19:112740acecfa | 12866 | /******************** Bit definition for LTDC_SSCR register *****************/ |
| mbed_official | 19:112740acecfa | 12867 | |
| AnnaBridge | 167:e84263d55307 | 12868 | #define LTDC_SSCR_VSH_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12869 | #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 167:e84263d55307 | 12870 | #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */ |
| AnnaBridge | 167:e84263d55307 | 12871 | #define LTDC_SSCR_HSW_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 12872 | #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 12873 | #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */ |
| mbed_official | 19:112740acecfa | 12874 | |
| mbed_official | 19:112740acecfa | 12875 | /******************** Bit definition for LTDC_BPCR register *****************/ |
| mbed_official | 19:112740acecfa | 12876 | |
| AnnaBridge | 167:e84263d55307 | 12877 | #define LTDC_BPCR_AVBP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12878 | #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 167:e84263d55307 | 12879 | #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */ |
| AnnaBridge | 167:e84263d55307 | 12880 | #define LTDC_BPCR_AHBP_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 12881 | #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 12882 | #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */ |
| mbed_official | 19:112740acecfa | 12883 | |
| mbed_official | 19:112740acecfa | 12884 | /******************** Bit definition for LTDC_AWCR register *****************/ |
| mbed_official | 19:112740acecfa | 12885 | |
| AnnaBridge | 167:e84263d55307 | 12886 | #define LTDC_AWCR_AAH_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12887 | #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 167:e84263d55307 | 12888 | #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */ |
| AnnaBridge | 167:e84263d55307 | 12889 | #define LTDC_AWCR_AAW_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 12890 | #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 12891 | #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */ |
| mbed_official | 19:112740acecfa | 12892 | |
| mbed_official | 19:112740acecfa | 12893 | /******************** Bit definition for LTDC_TWCR register *****************/ |
| mbed_official | 19:112740acecfa | 12894 | |
| AnnaBridge | 167:e84263d55307 | 12895 | #define LTDC_TWCR_TOTALH_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12896 | #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 167:e84263d55307 | 12897 | #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */ |
| AnnaBridge | 167:e84263d55307 | 12898 | #define LTDC_TWCR_TOTALW_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 12899 | #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 12900 | #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */ |
| mbed_official | 19:112740acecfa | 12901 | |
| mbed_official | 19:112740acecfa | 12902 | /******************** Bit definition for LTDC_GCR register ******************/ |
| mbed_official | 19:112740acecfa | 12903 | |
| AnnaBridge | 167:e84263d55307 | 12904 | #define LTDC_GCR_LTDCEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12905 | #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12906 | #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */ |
| AnnaBridge | 167:e84263d55307 | 12907 | #define LTDC_GCR_DBW_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 12908 | #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 12909 | #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */ |
| AnnaBridge | 167:e84263d55307 | 12910 | #define LTDC_GCR_DGW_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12911 | #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 167:e84263d55307 | 12912 | #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */ |
| AnnaBridge | 167:e84263d55307 | 12913 | #define LTDC_GCR_DRW_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 12914 | #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 167:e84263d55307 | 12915 | #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */ |
| AnnaBridge | 167:e84263d55307 | 12916 | #define LTDC_GCR_DEN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 12917 | #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 12918 | #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */ |
| AnnaBridge | 167:e84263d55307 | 12919 | #define LTDC_GCR_PCPOL_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 12920 | #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 12921 | #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */ |
| AnnaBridge | 167:e84263d55307 | 12922 | #define LTDC_GCR_DEPOL_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 12923 | #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 12924 | #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */ |
| AnnaBridge | 167:e84263d55307 | 12925 | #define LTDC_GCR_VSPOL_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 12926 | #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 12927 | #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */ |
| AnnaBridge | 167:e84263d55307 | 12928 | #define LTDC_GCR_HSPOL_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 12929 | #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 12930 | #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */ |
| <> | 144:ef7eb2e8f9f7 | 12931 | |
| <> | 144:ef7eb2e8f9f7 | 12932 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 12933 | #define LTDC_GCR_DTEN LTDC_GCR_DEN |
| mbed_official | 19:112740acecfa | 12934 | |
| mbed_official | 19:112740acecfa | 12935 | /******************** Bit definition for LTDC_SRCR register *****************/ |
| mbed_official | 19:112740acecfa | 12936 | |
| AnnaBridge | 167:e84263d55307 | 12937 | #define LTDC_SRCR_IMR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12938 | #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12939 | #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */ |
| AnnaBridge | 167:e84263d55307 | 12940 | #define LTDC_SRCR_VBR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12941 | #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12942 | #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */ |
| mbed_official | 19:112740acecfa | 12943 | |
| mbed_official | 19:112740acecfa | 12944 | /******************** Bit definition for LTDC_BCCR register *****************/ |
| mbed_official | 19:112740acecfa | 12945 | |
| AnnaBridge | 167:e84263d55307 | 12946 | #define LTDC_BCCR_BCBLUE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12947 | #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 12948 | #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */ |
| AnnaBridge | 167:e84263d55307 | 12949 | #define LTDC_BCCR_BCGREEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 12950 | #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 12951 | #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */ |
| AnnaBridge | 167:e84263d55307 | 12952 | #define LTDC_BCCR_BCRED_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 12953 | #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 12954 | #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */ |
| mbed_official | 19:112740acecfa | 12955 | |
| mbed_official | 19:112740acecfa | 12956 | /******************** Bit definition for LTDC_IER register ******************/ |
| mbed_official | 19:112740acecfa | 12957 | |
| AnnaBridge | 167:e84263d55307 | 12958 | #define LTDC_IER_LIE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12959 | #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12960 | #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 12961 | #define LTDC_IER_FUIE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12962 | #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12963 | #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 12964 | #define LTDC_IER_TERRIE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12965 | #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12966 | #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 12967 | #define LTDC_IER_RRIE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12968 | #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12969 | #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */ |
| mbed_official | 19:112740acecfa | 12970 | |
| mbed_official | 19:112740acecfa | 12971 | /******************** Bit definition for LTDC_ISR register ******************/ |
| mbed_official | 19:112740acecfa | 12972 | |
| AnnaBridge | 167:e84263d55307 | 12973 | #define LTDC_ISR_LIF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12974 | #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12975 | #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 12976 | #define LTDC_ISR_FUIF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12977 | #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12978 | #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 12979 | #define LTDC_ISR_TERRIF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12980 | #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12981 | #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 12982 | #define LTDC_ISR_RRIF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12983 | #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12984 | #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */ |
| mbed_official | 19:112740acecfa | 12985 | |
| mbed_official | 19:112740acecfa | 12986 | /******************** Bit definition for LTDC_ICR register ******************/ |
| mbed_official | 19:112740acecfa | 12987 | |
| AnnaBridge | 167:e84263d55307 | 12988 | #define LTDC_ICR_CLIF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 12989 | #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 12990 | #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 12991 | #define LTDC_ICR_CFUIF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 12992 | #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 12993 | #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 12994 | #define LTDC_ICR_CTERRIF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 12995 | #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 12996 | #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 12997 | #define LTDC_ICR_CRRIF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 12998 | #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 12999 | #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */ |
| mbed_official | 19:112740acecfa | 13000 | |
| mbed_official | 19:112740acecfa | 13001 | /******************** Bit definition for LTDC_LIPCR register ****************/ |
| mbed_official | 19:112740acecfa | 13002 | |
| AnnaBridge | 167:e84263d55307 | 13003 | #define LTDC_LIPCR_LIPOS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13004 | #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 167:e84263d55307 | 13005 | #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */ |
| mbed_official | 19:112740acecfa | 13006 | |
| mbed_official | 19:112740acecfa | 13007 | /******************** Bit definition for LTDC_CPSR register *****************/ |
| mbed_official | 19:112740acecfa | 13008 | |
| AnnaBridge | 167:e84263d55307 | 13009 | #define LTDC_CPSR_CYPOS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13010 | #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 13011 | #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */ |
| AnnaBridge | 167:e84263d55307 | 13012 | #define LTDC_CPSR_CXPOS_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13013 | #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 13014 | #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */ |
| mbed_official | 19:112740acecfa | 13015 | |
| mbed_official | 19:112740acecfa | 13016 | /******************** Bit definition for LTDC_CDSR register *****************/ |
| mbed_official | 19:112740acecfa | 13017 | |
| AnnaBridge | 167:e84263d55307 | 13018 | #define LTDC_CDSR_VDES_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13019 | #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13020 | #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */ |
| AnnaBridge | 167:e84263d55307 | 13021 | #define LTDC_CDSR_HDES_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13022 | #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13023 | #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */ |
| AnnaBridge | 167:e84263d55307 | 13024 | #define LTDC_CDSR_VSYNCS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 13025 | #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13026 | #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */ |
| AnnaBridge | 167:e84263d55307 | 13027 | #define LTDC_CDSR_HSYNCS_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 13028 | #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13029 | #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */ |
| mbed_official | 19:112740acecfa | 13030 | |
| mbed_official | 19:112740acecfa | 13031 | /******************** Bit definition for LTDC_LxCR register *****************/ |
| mbed_official | 19:112740acecfa | 13032 | |
| AnnaBridge | 167:e84263d55307 | 13033 | #define LTDC_LxCR_LEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13034 | #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13035 | #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */ |
| AnnaBridge | 167:e84263d55307 | 13036 | #define LTDC_LxCR_COLKEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13037 | #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13038 | #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */ |
| AnnaBridge | 167:e84263d55307 | 13039 | #define LTDC_LxCR_CLUTEN_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 13040 | #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13041 | #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */ |
| mbed_official | 19:112740acecfa | 13042 | |
| mbed_official | 19:112740acecfa | 13043 | /******************** Bit definition for LTDC_LxWHPCR register **************/ |
| mbed_official | 19:112740acecfa | 13044 | |
| AnnaBridge | 167:e84263d55307 | 13045 | #define LTDC_LxWHPCR_WHSTPOS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13046 | #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 13047 | #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */ |
| AnnaBridge | 167:e84263d55307 | 13048 | #define LTDC_LxWHPCR_WHSPPOS_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13049 | #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 13050 | #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */ |
| mbed_official | 19:112740acecfa | 13051 | |
| mbed_official | 19:112740acecfa | 13052 | /******************** Bit definition for LTDC_LxWVPCR register **************/ |
| mbed_official | 19:112740acecfa | 13053 | |
| AnnaBridge | 167:e84263d55307 | 13054 | #define LTDC_LxWVPCR_WVSTPOS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13055 | #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 13056 | #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */ |
| AnnaBridge | 167:e84263d55307 | 13057 | #define LTDC_LxWVPCR_WVSPPOS_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13058 | #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 13059 | #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */ |
| mbed_official | 19:112740acecfa | 13060 | |
| mbed_official | 19:112740acecfa | 13061 | /******************** Bit definition for LTDC_LxCKCR register ***************/ |
| mbed_official | 19:112740acecfa | 13062 | |
| AnnaBridge | 167:e84263d55307 | 13063 | #define LTDC_LxCKCR_CKBLUE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13064 | #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 13065 | #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */ |
| AnnaBridge | 167:e84263d55307 | 13066 | #define LTDC_LxCKCR_CKGREEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13067 | #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 13068 | #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */ |
| AnnaBridge | 167:e84263d55307 | 13069 | #define LTDC_LxCKCR_CKRED_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13070 | #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 13071 | #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */ |
| mbed_official | 19:112740acecfa | 13072 | |
| mbed_official | 19:112740acecfa | 13073 | /******************** Bit definition for LTDC_LxPFCR register ***************/ |
| mbed_official | 19:112740acecfa | 13074 | |
| AnnaBridge | 167:e84263d55307 | 13075 | #define LTDC_LxPFCR_PF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13076 | #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 13077 | #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */ |
| mbed_official | 19:112740acecfa | 13078 | |
| mbed_official | 19:112740acecfa | 13079 | /******************** Bit definition for LTDC_LxCACR register ***************/ |
| mbed_official | 19:112740acecfa | 13080 | |
| AnnaBridge | 167:e84263d55307 | 13081 | #define LTDC_LxCACR_CONSTA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13082 | #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 13083 | #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */ |
| mbed_official | 19:112740acecfa | 13084 | |
| mbed_official | 19:112740acecfa | 13085 | /******************** Bit definition for LTDC_LxDCCR register ***************/ |
| mbed_official | 19:112740acecfa | 13086 | |
| AnnaBridge | 167:e84263d55307 | 13087 | #define LTDC_LxDCCR_DCBLUE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13088 | #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 13089 | #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */ |
| AnnaBridge | 167:e84263d55307 | 13090 | #define LTDC_LxDCCR_DCGREEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13091 | #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 13092 | #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */ |
| AnnaBridge | 167:e84263d55307 | 13093 | #define LTDC_LxDCCR_DCRED_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13094 | #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 13095 | #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */ |
| AnnaBridge | 167:e84263d55307 | 13096 | #define LTDC_LxDCCR_DCALPHA_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 13097 | #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 13098 | #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */ |
| mbed_official | 19:112740acecfa | 13099 | |
| mbed_official | 19:112740acecfa | 13100 | /******************** Bit definition for LTDC_LxBFCR register ***************/ |
| mbed_official | 19:112740acecfa | 13101 | |
| AnnaBridge | 167:e84263d55307 | 13102 | #define LTDC_LxBFCR_BF2_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13103 | #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 13104 | #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */ |
| AnnaBridge | 167:e84263d55307 | 13105 | #define LTDC_LxBFCR_BF1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13106 | #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 167:e84263d55307 | 13107 | #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */ |
| mbed_official | 19:112740acecfa | 13108 | |
| mbed_official | 19:112740acecfa | 13109 | /******************** Bit definition for LTDC_LxCFBAR register **************/ |
| mbed_official | 19:112740acecfa | 13110 | |
| AnnaBridge | 167:e84263d55307 | 13111 | #define LTDC_LxCFBAR_CFBADD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13112 | #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 13113 | #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */ |
| mbed_official | 19:112740acecfa | 13114 | |
| mbed_official | 19:112740acecfa | 13115 | /******************** Bit definition for LTDC_LxCFBLR register **************/ |
| mbed_official | 19:112740acecfa | 13116 | |
| AnnaBridge | 167:e84263d55307 | 13117 | #define LTDC_LxCFBLR_CFBLL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13118 | #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */ |
| AnnaBridge | 167:e84263d55307 | 13119 | #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */ |
| AnnaBridge | 167:e84263d55307 | 13120 | #define LTDC_LxCFBLR_CFBP_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13121 | #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 13122 | #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */ |
| mbed_official | 19:112740acecfa | 13123 | |
| mbed_official | 19:112740acecfa | 13124 | /******************** Bit definition for LTDC_LxCFBLNR register *************/ |
| mbed_official | 19:112740acecfa | 13125 | |
| AnnaBridge | 167:e84263d55307 | 13126 | #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13127 | #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 167:e84263d55307 | 13128 | #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */ |
| mbed_official | 19:112740acecfa | 13129 | |
| mbed_official | 19:112740acecfa | 13130 | /******************** Bit definition for LTDC_LxCLUTWR register *************/ |
| mbed_official | 19:112740acecfa | 13131 | |
| AnnaBridge | 167:e84263d55307 | 13132 | #define LTDC_LxCLUTWR_BLUE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13133 | #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 13134 | #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */ |
| AnnaBridge | 167:e84263d55307 | 13135 | #define LTDC_LxCLUTWR_GREEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13136 | #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 13137 | #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */ |
| AnnaBridge | 167:e84263d55307 | 13138 | #define LTDC_LxCLUTWR_RED_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13139 | #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 13140 | #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */ |
| AnnaBridge | 167:e84263d55307 | 13141 | #define LTDC_LxCLUTWR_CLUTADD_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 13142 | #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 13143 | #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ |
| mbed_official | 19:112740acecfa | 13144 | |
| mbed_official | 19:112740acecfa | 13145 | |
| mbed_official | 19:112740acecfa | 13146 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 13147 | /* */ |
| mbed_official | 19:112740acecfa | 13148 | /* Power Control */ |
| mbed_official | 19:112740acecfa | 13149 | /* */ |
| mbed_official | 19:112740acecfa | 13150 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 13151 | /******************** Bit definition for PWR_CR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 13152 | #define PWR_CR_LPDS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13153 | #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13154 | #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ |
| AnnaBridge | 167:e84263d55307 | 13155 | #define PWR_CR_PDDS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13156 | #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13157 | #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ |
| AnnaBridge | 167:e84263d55307 | 13158 | #define PWR_CR_CWUF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 13159 | #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13160 | #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ |
| AnnaBridge | 167:e84263d55307 | 13161 | #define PWR_CR_CSBF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 13162 | #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13163 | #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ |
| AnnaBridge | 167:e84263d55307 | 13164 | #define PWR_CR_PVDE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 13165 | #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13166 | #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ |
| AnnaBridge | 167:e84263d55307 | 13167 | |
| AnnaBridge | 167:e84263d55307 | 13168 | #define PWR_CR_PLS_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 13169 | #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ |
| AnnaBridge | 167:e84263d55307 | 13170 | #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ |
| AnnaBridge | 167:e84263d55307 | 13171 | #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 13172 | #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 13173 | #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ |
| mbed_official | 19:112740acecfa | 13174 | |
| mbed_official | 19:112740acecfa | 13175 | /*!< PVD level configuration */ |
| AnnaBridge | 167:e84263d55307 | 13176 | #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */ |
| AnnaBridge | 167:e84263d55307 | 13177 | #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */ |
| AnnaBridge | 167:e84263d55307 | 13178 | #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */ |
| AnnaBridge | 167:e84263d55307 | 13179 | #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */ |
| AnnaBridge | 167:e84263d55307 | 13180 | #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */ |
| AnnaBridge | 167:e84263d55307 | 13181 | #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */ |
| AnnaBridge | 167:e84263d55307 | 13182 | #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */ |
| AnnaBridge | 167:e84263d55307 | 13183 | #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */ |
| AnnaBridge | 167:e84263d55307 | 13184 | #define PWR_CR_DBP_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13185 | #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13186 | #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ |
| AnnaBridge | 167:e84263d55307 | 13187 | #define PWR_CR_FPDS_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 13188 | #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 13189 | #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */ |
| AnnaBridge | 167:e84263d55307 | 13190 | #define PWR_CR_LPLVDS_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 13191 | #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 13192 | #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */ |
| AnnaBridge | 167:e84263d55307 | 13193 | #define PWR_CR_MRLVDS_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 13194 | #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 13195 | #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */ |
| AnnaBridge | 167:e84263d55307 | 13196 | #define PWR_CR_ADCDC1_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 13197 | #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 13198 | #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */ |
| AnnaBridge | 167:e84263d55307 | 13199 | #define PWR_CR_VOS_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 13200 | #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 13201 | #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ |
| AnnaBridge | 167:e84263d55307 | 13202 | #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 13203 | #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 13204 | #define PWR_CR_ODEN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13205 | #define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 13206 | #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */ |
| AnnaBridge | 167:e84263d55307 | 13207 | #define PWR_CR_ODSWEN_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 13208 | #define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13209 | #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */ |
| AnnaBridge | 167:e84263d55307 | 13210 | #define PWR_CR_UDEN_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 13211 | #define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 167:e84263d55307 | 13212 | #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */ |
| AnnaBridge | 167:e84263d55307 | 13213 | #define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 13214 | #define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */ |
| mbed_official | 19:112740acecfa | 13215 | |
| mbed_official | 19:112740acecfa | 13216 | /* Legacy define */ |
| mbed_official | 19:112740acecfa | 13217 | #define PWR_CR_PMODE PWR_CR_VOS |
| mbed_official | 19:112740acecfa | 13218 | #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */ |
| mbed_official | 19:112740acecfa | 13219 | #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */ |
| mbed_official | 19:112740acecfa | 13220 | |
| mbed_official | 19:112740acecfa | 13221 | /******************* Bit definition for PWR_CSR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 13222 | #define PWR_CSR_WUF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13223 | #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13224 | #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ |
| AnnaBridge | 167:e84263d55307 | 13225 | #define PWR_CSR_SBF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13226 | #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13227 | #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ |
| AnnaBridge | 167:e84263d55307 | 13228 | #define PWR_CSR_PVDO_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 13229 | #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13230 | #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ |
| AnnaBridge | 167:e84263d55307 | 13231 | #define PWR_CSR_BRR_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 13232 | #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13233 | #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */ |
| AnnaBridge | 167:e84263d55307 | 13234 | #define PWR_CSR_WUPP_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 13235 | #define PWR_CSR_WUPP_Msk (0x1U << PWR_CSR_WUPP_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 13236 | #define PWR_CSR_WUPP PWR_CSR_WUPP_Msk /*!< WKUP pin Polarity */ |
| AnnaBridge | 167:e84263d55307 | 13237 | #define PWR_CSR_EWUP_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13238 | #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13239 | #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ |
| AnnaBridge | 167:e84263d55307 | 13240 | #define PWR_CSR_BRE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 13241 | #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 13242 | #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */ |
| AnnaBridge | 167:e84263d55307 | 13243 | #define PWR_CSR_VOSRDY_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 13244 | #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 13245 | #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */ |
| AnnaBridge | 167:e84263d55307 | 13246 | #define PWR_CSR_ODRDY_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13247 | #define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 13248 | #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */ |
| AnnaBridge | 167:e84263d55307 | 13249 | #define PWR_CSR_ODSWRDY_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 13250 | #define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13251 | #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */ |
| AnnaBridge | 167:e84263d55307 | 13252 | #define PWR_CSR_UDRDY_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 13253 | #define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 167:e84263d55307 | 13254 | #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */ |
| AnnaBridge | 167:e84263d55307 | 13255 | /* Legacy define */ |
| AnnaBridge | 167:e84263d55307 | 13256 | #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY |
| mbed_official | 19:112740acecfa | 13257 | |
| mbed_official | 19:112740acecfa | 13258 | /* Legacy define */ |
| mbed_official | 19:112740acecfa | 13259 | #define PWR_CSR_REGRDY PWR_CSR_VOSRDY |
| mbed_official | 19:112740acecfa | 13260 | |
| mbed_official | 19:112740acecfa | 13261 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 13262 | /* */ |
| mbed_official | 19:112740acecfa | 13263 | /* QUADSPI */ |
| mbed_official | 19:112740acecfa | 13264 | /* */ |
| mbed_official | 19:112740acecfa | 13265 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 13266 | /***************** Bit definition for QUADSPI_CR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 13267 | #define QUADSPI_CR_EN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13268 | #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13269 | #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */ |
| AnnaBridge | 167:e84263d55307 | 13270 | #define QUADSPI_CR_ABORT_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13271 | #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13272 | #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */ |
| AnnaBridge | 167:e84263d55307 | 13273 | #define QUADSPI_CR_DMAEN_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 13274 | #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13275 | #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */ |
| AnnaBridge | 167:e84263d55307 | 13276 | #define QUADSPI_CR_TCEN_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 13277 | #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13278 | #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */ |
| AnnaBridge | 167:e84263d55307 | 13279 | #define QUADSPI_CR_SSHIFT_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 13280 | #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13281 | #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */ |
| AnnaBridge | 167:e84263d55307 | 13282 | #define QUADSPI_CR_DFM_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 13283 | #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 13284 | #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */ |
| AnnaBridge | 167:e84263d55307 | 13285 | #define QUADSPI_CR_FSEL_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 13286 | #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 13287 | #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ |
| AnnaBridge | 167:e84263d55307 | 13288 | #define QUADSPI_CR_FTHRES_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13289 | #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 167:e84263d55307 | 13290 | #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ |
| AnnaBridge | 167:e84263d55307 | 13291 | #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13292 | #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 13293 | #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 13294 | #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 13295 | #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 13296 | #define QUADSPI_CR_TEIE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13297 | #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 13298 | #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 13299 | #define QUADSPI_CR_TCIE_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 13300 | #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13301 | #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 13302 | #define QUADSPI_CR_FTIE_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 13303 | #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 13304 | #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 13305 | #define QUADSPI_CR_SMIE_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 13306 | #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 13307 | #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 13308 | #define QUADSPI_CR_TOIE_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 13309 | #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 13310 | #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 13311 | #define QUADSPI_CR_APMS_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 13312 | #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 13313 | #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 13314 | #define QUADSPI_CR_PMM_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 13315 | #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 13316 | #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */ |
| AnnaBridge | 167:e84263d55307 | 13317 | #define QUADSPI_CR_PRESCALER_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 13318 | #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 13319 | #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */ |
| AnnaBridge | 167:e84263d55307 | 13320 | #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 13321 | #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 13322 | #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 13323 | #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 13324 | #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 13325 | #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 13326 | #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 13327 | #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */ |
| mbed_official | 19:112740acecfa | 13328 | |
| mbed_official | 19:112740acecfa | 13329 | /***************** Bit definition for QUADSPI_DCR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 13330 | #define QUADSPI_DCR_CKMODE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13331 | #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13332 | #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */ |
| AnnaBridge | 167:e84263d55307 | 13333 | #define QUADSPI_DCR_CSHT_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13334 | #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 167:e84263d55307 | 13335 | #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */ |
| AnnaBridge | 167:e84263d55307 | 13336 | #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13337 | #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 13338 | #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 13339 | #define QUADSPI_DCR_FSIZE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13340 | #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */ |
| AnnaBridge | 167:e84263d55307 | 13341 | #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */ |
| AnnaBridge | 167:e84263d55307 | 13342 | #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 13343 | #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13344 | #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 13345 | #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 13346 | #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */ |
| mbed_official | 19:112740acecfa | 13347 | |
| mbed_official | 19:112740acecfa | 13348 | /****************** Bit definition for QUADSPI_SR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 13349 | #define QUADSPI_SR_TEF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13350 | #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13351 | #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */ |
| AnnaBridge | 167:e84263d55307 | 13352 | #define QUADSPI_SR_TCF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13353 | #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13354 | #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */ |
| AnnaBridge | 167:e84263d55307 | 13355 | #define QUADSPI_SR_FTF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 13356 | #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13357 | #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */ |
| AnnaBridge | 167:e84263d55307 | 13358 | #define QUADSPI_SR_SMF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 13359 | #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13360 | #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */ |
| AnnaBridge | 167:e84263d55307 | 13361 | #define QUADSPI_SR_TOF_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 13362 | #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13363 | #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */ |
| AnnaBridge | 167:e84263d55307 | 13364 | #define QUADSPI_SR_BUSY_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 13365 | #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 13366 | #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */ |
| AnnaBridge | 167:e84263d55307 | 13367 | #define QUADSPI_SR_FLEVEL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13368 | #define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ |
| AnnaBridge | 167:e84263d55307 | 13369 | #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */ |
| AnnaBridge | 167:e84263d55307 | 13370 | #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13371 | #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 13372 | #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 13373 | #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 13374 | #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 13375 | #define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */ |
| mbed_official | 19:112740acecfa | 13376 | |
| mbed_official | 19:112740acecfa | 13377 | /****************** Bit definition for QUADSPI_FCR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 13378 | #define QUADSPI_FCR_CTEF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13379 | #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13380 | #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */ |
| AnnaBridge | 167:e84263d55307 | 13381 | #define QUADSPI_FCR_CTCF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13382 | #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13383 | #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */ |
| AnnaBridge | 167:e84263d55307 | 13384 | #define QUADSPI_FCR_CSMF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 13385 | #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13386 | #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ |
| AnnaBridge | 167:e84263d55307 | 13387 | #define QUADSPI_FCR_CTOF_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 13388 | #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13389 | #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */ |
| mbed_official | 19:112740acecfa | 13390 | |
| mbed_official | 19:112740acecfa | 13391 | /****************** Bit definition for QUADSPI_DLR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 13392 | #define QUADSPI_DLR_DL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13393 | #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 13394 | #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */ |
| mbed_official | 19:112740acecfa | 13395 | |
| mbed_official | 19:112740acecfa | 13396 | /****************** Bit definition for QUADSPI_CCR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 13397 | #define QUADSPI_CCR_INSTRUCTION_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13398 | #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 13399 | #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */ |
| AnnaBridge | 167:e84263d55307 | 13400 | #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13401 | #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13402 | #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13403 | #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13404 | #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13405 | #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 13406 | #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 13407 | #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 13408 | #define QUADSPI_CCR_IMODE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13409 | #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 13410 | #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */ |
| AnnaBridge | 167:e84263d55307 | 13411 | #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13412 | #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 13413 | #define QUADSPI_CCR_ADMODE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 13414 | #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 13415 | #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */ |
| AnnaBridge | 167:e84263d55307 | 13416 | #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 13417 | #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 13418 | #define QUADSPI_CCR_ADSIZE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 13419 | #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 167:e84263d55307 | 13420 | #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */ |
| AnnaBridge | 167:e84263d55307 | 13421 | #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 13422 | #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 13423 | #define QUADSPI_CCR_ABMODE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 13424 | #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 13425 | #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */ |
| AnnaBridge | 167:e84263d55307 | 13426 | #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 13427 | #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 13428 | #define QUADSPI_CCR_ABSIZE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13429 | #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 13430 | #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */ |
| AnnaBridge | 167:e84263d55307 | 13431 | #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 13432 | #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13433 | #define QUADSPI_CCR_DCYC_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 13434 | #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */ |
| AnnaBridge | 167:e84263d55307 | 13435 | #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */ |
| AnnaBridge | 167:e84263d55307 | 13436 | #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 13437 | #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 13438 | #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 13439 | #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 13440 | #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 13441 | #define QUADSPI_CCR_DMODE_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 13442 | #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 167:e84263d55307 | 13443 | #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */ |
| AnnaBridge | 167:e84263d55307 | 13444 | #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 13445 | #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 13446 | #define QUADSPI_CCR_FMODE_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 13447 | #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 167:e84263d55307 | 13448 | #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */ |
| AnnaBridge | 167:e84263d55307 | 13449 | #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 13450 | #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 13451 | #define QUADSPI_CCR_SIOO_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 13452 | #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 13453 | #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */ |
| AnnaBridge | 167:e84263d55307 | 13454 | #define QUADSPI_CCR_DHHC_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 13455 | #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 13456 | #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */ |
| AnnaBridge | 167:e84263d55307 | 13457 | #define QUADSPI_CCR_DDRM_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 13458 | #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 13459 | #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */ |
| mbed_official | 19:112740acecfa | 13460 | /****************** Bit definition for QUADSPI_AR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 13461 | #define QUADSPI_AR_ADDRESS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13462 | #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 13463 | #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */ |
| mbed_official | 19:112740acecfa | 13464 | |
| mbed_official | 19:112740acecfa | 13465 | /****************** Bit definition for QUADSPI_ABR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 13466 | #define QUADSPI_ABR_ALTERNATE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13467 | #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 13468 | #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */ |
| mbed_official | 19:112740acecfa | 13469 | |
| mbed_official | 19:112740acecfa | 13470 | /****************** Bit definition for QUADSPI_DR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 13471 | #define QUADSPI_DR_DATA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13472 | #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 13473 | #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */ |
| mbed_official | 19:112740acecfa | 13474 | |
| mbed_official | 19:112740acecfa | 13475 | /****************** Bit definition for QUADSPI_PSMKR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 13476 | #define QUADSPI_PSMKR_MASK_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13477 | #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 13478 | #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */ |
| mbed_official | 19:112740acecfa | 13479 | |
| mbed_official | 19:112740acecfa | 13480 | /****************** Bit definition for QUADSPI_PSMAR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 13481 | #define QUADSPI_PSMAR_MATCH_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13482 | #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 13483 | #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */ |
| mbed_official | 19:112740acecfa | 13484 | |
| mbed_official | 19:112740acecfa | 13485 | /****************** Bit definition for QUADSPI_PIR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 13486 | #define QUADSPI_PIR_INTERVAL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13487 | #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 13488 | #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */ |
| mbed_official | 19:112740acecfa | 13489 | |
| mbed_official | 19:112740acecfa | 13490 | /****************** Bit definition for QUADSPI_LPTR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 13491 | #define QUADSPI_LPTR_TIMEOUT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13492 | #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 13493 | #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */ |
| mbed_official | 19:112740acecfa | 13494 | |
| mbed_official | 19:112740acecfa | 13495 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 13496 | /* */ |
| mbed_official | 19:112740acecfa | 13497 | /* Reset and Clock Control */ |
| mbed_official | 19:112740acecfa | 13498 | /* */ |
| mbed_official | 19:112740acecfa | 13499 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 13500 | /******************** Bit definition for RCC_CR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 13501 | #define RCC_CR_HSION_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13502 | #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13503 | #define RCC_CR_HSION RCC_CR_HSION_Msk |
| AnnaBridge | 167:e84263d55307 | 13504 | #define RCC_CR_HSIRDY_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13505 | #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13506 | #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk |
| AnnaBridge | 167:e84263d55307 | 13507 | |
| AnnaBridge | 167:e84263d55307 | 13508 | #define RCC_CR_HSITRIM_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 13509 | #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ |
| AnnaBridge | 167:e84263d55307 | 13510 | #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk |
| AnnaBridge | 167:e84263d55307 | 13511 | #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13512 | #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13513 | #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 13514 | #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 13515 | #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 13516 | |
| AnnaBridge | 167:e84263d55307 | 13517 | #define RCC_CR_HSICAL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13518 | #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 13519 | #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk |
| AnnaBridge | 167:e84263d55307 | 13520 | #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13521 | #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 13522 | #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 13523 | #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 13524 | #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 13525 | #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 13526 | #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 13527 | #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 13528 | |
| AnnaBridge | 167:e84263d55307 | 13529 | #define RCC_CR_HSEON_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13530 | #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 13531 | #define RCC_CR_HSEON RCC_CR_HSEON_Msk |
| AnnaBridge | 167:e84263d55307 | 13532 | #define RCC_CR_HSERDY_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 13533 | #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13534 | #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk |
| AnnaBridge | 167:e84263d55307 | 13535 | #define RCC_CR_HSEBYP_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 13536 | #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 13537 | #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk |
| AnnaBridge | 167:e84263d55307 | 13538 | #define RCC_CR_CSSON_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 13539 | #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 13540 | #define RCC_CR_CSSON RCC_CR_CSSON_Msk |
| AnnaBridge | 167:e84263d55307 | 13541 | #define RCC_CR_PLLON_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 13542 | #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 13543 | #define RCC_CR_PLLON RCC_CR_PLLON_Msk |
| AnnaBridge | 167:e84263d55307 | 13544 | #define RCC_CR_PLLRDY_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 13545 | #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 13546 | #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk |
| AnnaBridge | 167:e84263d55307 | 13547 | /* |
| AnnaBridge | 167:e84263d55307 | 13548 | * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) |
| AnnaBridge | 167:e84263d55307 | 13549 | */ |
| AnnaBridge | 167:e84263d55307 | 13550 | #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */ |
| AnnaBridge | 167:e84263d55307 | 13551 | |
| AnnaBridge | 167:e84263d55307 | 13552 | #define RCC_CR_PLLI2SON_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 13553 | #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 13554 | #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk |
| AnnaBridge | 167:e84263d55307 | 13555 | #define RCC_CR_PLLI2SRDY_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 13556 | #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 13557 | #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk |
| AnnaBridge | 167:e84263d55307 | 13558 | /* |
| AnnaBridge | 167:e84263d55307 | 13559 | * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) |
| AnnaBridge | 167:e84263d55307 | 13560 | */ |
| AnnaBridge | 167:e84263d55307 | 13561 | #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */ |
| AnnaBridge | 167:e84263d55307 | 13562 | |
| AnnaBridge | 167:e84263d55307 | 13563 | #define RCC_CR_PLLSAION_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 13564 | #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 13565 | #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk |
| AnnaBridge | 167:e84263d55307 | 13566 | #define RCC_CR_PLLSAIRDY_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 13567 | #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 13568 | #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk |
| mbed_official | 19:112740acecfa | 13569 | |
| mbed_official | 19:112740acecfa | 13570 | /******************** Bit definition for RCC_PLLCFGR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 13571 | #define RCC_PLLCFGR_PLLM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13572 | #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 167:e84263d55307 | 13573 | #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk |
| AnnaBridge | 167:e84263d55307 | 13574 | #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13575 | #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13576 | #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13577 | #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13578 | #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13579 | #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 13580 | |
| AnnaBridge | 167:e84263d55307 | 13581 | #define RCC_PLLCFGR_PLLN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 13582 | #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */ |
| AnnaBridge | 167:e84263d55307 | 13583 | #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk |
| AnnaBridge | 167:e84263d55307 | 13584 | #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 13585 | #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 13586 | #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13587 | #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 13588 | #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 13589 | #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 13590 | #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 13591 | #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 13592 | #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 13593 | |
| AnnaBridge | 167:e84263d55307 | 13594 | #define RCC_PLLCFGR_PLLP_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13595 | #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 13596 | #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk |
| AnnaBridge | 167:e84263d55307 | 13597 | #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 13598 | #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13599 | |
| AnnaBridge | 167:e84263d55307 | 13600 | #define RCC_PLLCFGR_PLLSRC_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 13601 | #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 13602 | #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk |
| AnnaBridge | 167:e84263d55307 | 13603 | #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 13604 | #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 13605 | #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk |
| AnnaBridge | 167:e84263d55307 | 13606 | #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U |
| AnnaBridge | 167:e84263d55307 | 13607 | |
| AnnaBridge | 167:e84263d55307 | 13608 | #define RCC_PLLCFGR_PLLQ_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 13609 | #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 13610 | #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk |
| AnnaBridge | 167:e84263d55307 | 13611 | #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 13612 | #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 13613 | #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 13614 | #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 13615 | |
| AnnaBridge | 167:e84263d55307 | 13616 | #define RCC_PLLCFGR_PLLR_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 13617 | #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */ |
| AnnaBridge | 167:e84263d55307 | 13618 | #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk |
| AnnaBridge | 167:e84263d55307 | 13619 | #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 13620 | #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 13621 | #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */ |
| mbed_official | 19:112740acecfa | 13622 | |
| mbed_official | 19:112740acecfa | 13623 | /******************** Bit definition for RCC_CFGR register ******************/ |
| mbed_official | 19:112740acecfa | 13624 | /*!< SW configuration */ |
| AnnaBridge | 167:e84263d55307 | 13625 | #define RCC_CFGR_SW_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13626 | #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 13627 | #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ |
| AnnaBridge | 167:e84263d55307 | 13628 | #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13629 | #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13630 | |
| AnnaBridge | 167:e84263d55307 | 13631 | #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ |
| AnnaBridge | 167:e84263d55307 | 13632 | #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ |
| AnnaBridge | 167:e84263d55307 | 13633 | #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ |
| mbed_official | 19:112740acecfa | 13634 | |
| mbed_official | 19:112740acecfa | 13635 | /*!< SWS configuration */ |
| AnnaBridge | 167:e84263d55307 | 13636 | #define RCC_CFGR_SWS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 13637 | #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 13638 | #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ |
| AnnaBridge | 167:e84263d55307 | 13639 | #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13640 | #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13641 | |
| AnnaBridge | 167:e84263d55307 | 13642 | #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ |
| AnnaBridge | 167:e84263d55307 | 13643 | #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ |
| AnnaBridge | 167:e84263d55307 | 13644 | #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ |
| mbed_official | 19:112740acecfa | 13645 | |
| mbed_official | 19:112740acecfa | 13646 | /*!< HPRE configuration */ |
| AnnaBridge | 167:e84263d55307 | 13647 | #define RCC_CFGR_HPRE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 13648 | #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 13649 | #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ |
| AnnaBridge | 167:e84263d55307 | 13650 | #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13651 | #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 13652 | #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 13653 | #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 13654 | |
| AnnaBridge | 167:e84263d55307 | 13655 | #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ |
| AnnaBridge | 167:e84263d55307 | 13656 | #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ |
| AnnaBridge | 167:e84263d55307 | 13657 | #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ |
| AnnaBridge | 167:e84263d55307 | 13658 | #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ |
| AnnaBridge | 167:e84263d55307 | 13659 | #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ |
| AnnaBridge | 167:e84263d55307 | 13660 | #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ |
| AnnaBridge | 167:e84263d55307 | 13661 | #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ |
| AnnaBridge | 167:e84263d55307 | 13662 | #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ |
| AnnaBridge | 167:e84263d55307 | 13663 | #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ |
| mbed_official | 19:112740acecfa | 13664 | |
| mbed_official | 19:112740acecfa | 13665 | /*!< PPRE1 configuration */ |
| AnnaBridge | 167:e84263d55307 | 13666 | #define RCC_CFGR_PPRE1_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 13667 | #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */ |
| AnnaBridge | 167:e84263d55307 | 13668 | #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ |
| AnnaBridge | 167:e84263d55307 | 13669 | #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 13670 | #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 13671 | #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 13672 | |
| AnnaBridge | 167:e84263d55307 | 13673 | #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ |
| AnnaBridge | 167:e84263d55307 | 13674 | #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */ |
| AnnaBridge | 167:e84263d55307 | 13675 | #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */ |
| AnnaBridge | 167:e84263d55307 | 13676 | #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */ |
| AnnaBridge | 167:e84263d55307 | 13677 | #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */ |
| mbed_official | 19:112740acecfa | 13678 | |
| mbed_official | 19:112740acecfa | 13679 | /*!< PPRE2 configuration */ |
| AnnaBridge | 167:e84263d55307 | 13680 | #define RCC_CFGR_PPRE2_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 13681 | #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */ |
| AnnaBridge | 167:e84263d55307 | 13682 | #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ |
| AnnaBridge | 167:e84263d55307 | 13683 | #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 13684 | #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 13685 | #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 13686 | |
| AnnaBridge | 167:e84263d55307 | 13687 | #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ |
| AnnaBridge | 167:e84263d55307 | 13688 | #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */ |
| AnnaBridge | 167:e84263d55307 | 13689 | #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */ |
| AnnaBridge | 167:e84263d55307 | 13690 | #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */ |
| AnnaBridge | 167:e84263d55307 | 13691 | #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */ |
| mbed_official | 19:112740acecfa | 13692 | |
| mbed_official | 19:112740acecfa | 13693 | /*!< RTCPRE configuration */ |
| AnnaBridge | 167:e84263d55307 | 13694 | #define RCC_CFGR_RTCPRE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13695 | #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */ |
| AnnaBridge | 167:e84263d55307 | 13696 | #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk |
| AnnaBridge | 167:e84263d55307 | 13697 | #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 13698 | #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13699 | #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 13700 | #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 13701 | #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */ |
| mbed_official | 19:112740acecfa | 13702 | |
| mbed_official | 19:112740acecfa | 13703 | /*!< MCO1 configuration */ |
| AnnaBridge | 167:e84263d55307 | 13704 | #define RCC_CFGR_MCO1_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 13705 | #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 167:e84263d55307 | 13706 | #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk |
| AnnaBridge | 167:e84263d55307 | 13707 | #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 13708 | #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 13709 | |
| AnnaBridge | 167:e84263d55307 | 13710 | #define RCC_CFGR_I2SSRC_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 13711 | #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 13712 | #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk |
| AnnaBridge | 167:e84263d55307 | 13713 | |
| AnnaBridge | 167:e84263d55307 | 13714 | #define RCC_CFGR_MCO1PRE_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 13715 | #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 167:e84263d55307 | 13716 | #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk |
| AnnaBridge | 167:e84263d55307 | 13717 | #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 13718 | #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 13719 | #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 13720 | |
| AnnaBridge | 167:e84263d55307 | 13721 | #define RCC_CFGR_MCO2PRE_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 13722 | #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */ |
| AnnaBridge | 167:e84263d55307 | 13723 | #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk |
| AnnaBridge | 167:e84263d55307 | 13724 | #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 13725 | #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 13726 | #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 13727 | |
| AnnaBridge | 167:e84263d55307 | 13728 | #define RCC_CFGR_MCO2_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 13729 | #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 167:e84263d55307 | 13730 | #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk |
| AnnaBridge | 167:e84263d55307 | 13731 | #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 13732 | #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */ |
| mbed_official | 19:112740acecfa | 13733 | |
| mbed_official | 19:112740acecfa | 13734 | /******************** Bit definition for RCC_CIR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 13735 | #define RCC_CIR_LSIRDYF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13736 | #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13737 | #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk |
| AnnaBridge | 167:e84263d55307 | 13738 | #define RCC_CIR_LSERDYF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13739 | #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13740 | #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk |
| AnnaBridge | 167:e84263d55307 | 13741 | #define RCC_CIR_HSIRDYF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 13742 | #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13743 | #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk |
| AnnaBridge | 167:e84263d55307 | 13744 | #define RCC_CIR_HSERDYF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 13745 | #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13746 | #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk |
| AnnaBridge | 167:e84263d55307 | 13747 | #define RCC_CIR_PLLRDYF_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 13748 | #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13749 | #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk |
| AnnaBridge | 167:e84263d55307 | 13750 | #define RCC_CIR_PLLI2SRDYF_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 13751 | #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 13752 | #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk |
| AnnaBridge | 167:e84263d55307 | 13753 | |
| AnnaBridge | 167:e84263d55307 | 13754 | #define RCC_CIR_PLLSAIRDYF_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 13755 | #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 13756 | #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk |
| AnnaBridge | 167:e84263d55307 | 13757 | #define RCC_CIR_CSSF_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 13758 | #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 13759 | #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk |
| AnnaBridge | 167:e84263d55307 | 13760 | #define RCC_CIR_LSIRDYIE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13761 | #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13762 | #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk |
| AnnaBridge | 167:e84263d55307 | 13763 | #define RCC_CIR_LSERDYIE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 13764 | #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 13765 | #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk |
| AnnaBridge | 167:e84263d55307 | 13766 | #define RCC_CIR_HSIRDYIE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 13767 | #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 13768 | #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk |
| AnnaBridge | 167:e84263d55307 | 13769 | #define RCC_CIR_HSERDYIE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 13770 | #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 13771 | #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk |
| AnnaBridge | 167:e84263d55307 | 13772 | #define RCC_CIR_PLLRDYIE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 13773 | #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 13774 | #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk |
| AnnaBridge | 167:e84263d55307 | 13775 | #define RCC_CIR_PLLI2SRDYIE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 13776 | #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 13777 | #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk |
| AnnaBridge | 167:e84263d55307 | 13778 | |
| AnnaBridge | 167:e84263d55307 | 13779 | #define RCC_CIR_PLLSAIRDYIE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 13780 | #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 13781 | #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk |
| AnnaBridge | 167:e84263d55307 | 13782 | #define RCC_CIR_LSIRDYC_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13783 | #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 13784 | #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk |
| AnnaBridge | 167:e84263d55307 | 13785 | #define RCC_CIR_LSERDYC_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 13786 | #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13787 | #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk |
| AnnaBridge | 167:e84263d55307 | 13788 | #define RCC_CIR_HSIRDYC_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 13789 | #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 13790 | #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk |
| AnnaBridge | 167:e84263d55307 | 13791 | #define RCC_CIR_HSERDYC_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 13792 | #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 13793 | #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk |
| AnnaBridge | 167:e84263d55307 | 13794 | #define RCC_CIR_PLLRDYC_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 13795 | #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 13796 | #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk |
| AnnaBridge | 167:e84263d55307 | 13797 | #define RCC_CIR_PLLI2SRDYC_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 13798 | #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 13799 | #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk |
| AnnaBridge | 167:e84263d55307 | 13800 | #define RCC_CIR_PLLSAIRDYC_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 13801 | #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 13802 | #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk |
| AnnaBridge | 167:e84263d55307 | 13803 | |
| AnnaBridge | 167:e84263d55307 | 13804 | #define RCC_CIR_CSSC_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 13805 | #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 13806 | #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk |
| mbed_official | 19:112740acecfa | 13807 | |
| mbed_official | 19:112740acecfa | 13808 | /******************** Bit definition for RCC_AHB1RSTR register **************/ |
| AnnaBridge | 167:e84263d55307 | 13809 | #define RCC_AHB1RSTR_GPIOARST_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13810 | #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13811 | #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk |
| AnnaBridge | 167:e84263d55307 | 13812 | #define RCC_AHB1RSTR_GPIOBRST_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13813 | #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13814 | #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13815 | #define RCC_AHB1RSTR_GPIOCRST_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 13816 | #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13817 | #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13818 | #define RCC_AHB1RSTR_GPIODRST_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 13819 | #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13820 | #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13821 | #define RCC_AHB1RSTR_GPIOERST_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 13822 | #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13823 | #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk |
| AnnaBridge | 167:e84263d55307 | 13824 | #define RCC_AHB1RSTR_GPIOFRST_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 13825 | #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 13826 | #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13827 | #define RCC_AHB1RSTR_GPIOGRST_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 13828 | #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 13829 | #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13830 | #define RCC_AHB1RSTR_GPIOHRST_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 13831 | #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 13832 | #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13833 | #define RCC_AHB1RSTR_GPIOIRST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13834 | #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13835 | #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13836 | #define RCC_AHB1RSTR_GPIOJRST_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 13837 | #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 13838 | #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13839 | #define RCC_AHB1RSTR_GPIOKRST_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 13840 | #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 13841 | #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13842 | #define RCC_AHB1RSTR_CRCRST_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 13843 | #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 13844 | #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13845 | #define RCC_AHB1RSTR_DMA1RST_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 13846 | #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 13847 | #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13848 | #define RCC_AHB1RSTR_DMA2RST_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 13849 | #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 13850 | #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13851 | #define RCC_AHB1RSTR_DMA2DRST_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 13852 | #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 13853 | #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13854 | #define RCC_AHB1RSTR_ETHMACRST_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 13855 | #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 13856 | #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13857 | #define RCC_AHB1RSTR_OTGHRST_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 13858 | #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 13859 | #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk |
| mbed_official | 19:112740acecfa | 13860 | |
| mbed_official | 19:112740acecfa | 13861 | /******************** Bit definition for RCC_AHB2RSTR register **************/ |
| AnnaBridge | 167:e84263d55307 | 13862 | #define RCC_AHB2RSTR_DCMIRST_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13863 | #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13864 | #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13865 | #define RCC_AHB2RSTR_RNGRST_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 13866 | #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 13867 | #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13868 | #define RCC_AHB2RSTR_OTGFSRST_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 13869 | #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 13870 | #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk |
| mbed_official | 19:112740acecfa | 13871 | /******************** Bit definition for RCC_AHB3RSTR register **************/ |
| AnnaBridge | 167:e84263d55307 | 13872 | #define RCC_AHB3RSTR_FMCRST_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13873 | #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13874 | #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13875 | #define RCC_AHB3RSTR_QSPIRST_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13876 | #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13877 | #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13878 | |
| mbed_official | 19:112740acecfa | 13879 | |
| mbed_official | 19:112740acecfa | 13880 | /******************** Bit definition for RCC_APB1RSTR register **************/ |
| AnnaBridge | 167:e84263d55307 | 13881 | #define RCC_APB1RSTR_TIM2RST_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13882 | #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13883 | #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13884 | #define RCC_APB1RSTR_TIM3RST_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13885 | #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13886 | #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13887 | #define RCC_APB1RSTR_TIM4RST_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 13888 | #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 13889 | #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13890 | #define RCC_APB1RSTR_TIM5RST_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 13891 | #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 13892 | #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13893 | #define RCC_APB1RSTR_TIM6RST_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 13894 | #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13895 | #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13896 | #define RCC_APB1RSTR_TIM7RST_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 13897 | #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 13898 | #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13899 | #define RCC_APB1RSTR_TIM12RST_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 13900 | #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 13901 | #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13902 | #define RCC_APB1RSTR_TIM13RST_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 13903 | #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 13904 | #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13905 | #define RCC_APB1RSTR_TIM14RST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13906 | #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13907 | #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13908 | #define RCC_APB1RSTR_WWDGRST_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 13909 | #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 13910 | #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13911 | #define RCC_APB1RSTR_SPI2RST_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 13912 | #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 13913 | #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13914 | #define RCC_APB1RSTR_SPI3RST_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 13915 | #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 13916 | #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13917 | #define RCC_APB1RSTR_USART2RST_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 13918 | #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13919 | #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13920 | #define RCC_APB1RSTR_USART3RST_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 13921 | #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 13922 | #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13923 | #define RCC_APB1RSTR_UART4RST_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 13924 | #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 13925 | #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13926 | #define RCC_APB1RSTR_UART5RST_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 13927 | #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 13928 | #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13929 | #define RCC_APB1RSTR_I2C1RST_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 13930 | #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 13931 | #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13932 | #define RCC_APB1RSTR_I2C2RST_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 13933 | #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 13934 | #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13935 | #define RCC_APB1RSTR_I2C3RST_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 13936 | #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 13937 | #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13938 | #define RCC_APB1RSTR_CAN1RST_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 13939 | #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 13940 | #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13941 | #define RCC_APB1RSTR_CAN2RST_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 13942 | #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 13943 | #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13944 | #define RCC_APB1RSTR_PWRRST_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 13945 | #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 13946 | #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13947 | #define RCC_APB1RSTR_DACRST_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 13948 | #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 13949 | #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13950 | #define RCC_APB1RSTR_UART7RST_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 13951 | #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 13952 | #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13953 | #define RCC_APB1RSTR_UART8RST_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 13954 | #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 13955 | #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk |
| mbed_official | 19:112740acecfa | 13956 | |
| mbed_official | 19:112740acecfa | 13957 | /******************** Bit definition for RCC_APB2RSTR register **************/ |
| AnnaBridge | 167:e84263d55307 | 13958 | #define RCC_APB2RSTR_TIM1RST_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 13959 | #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 13960 | #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13961 | #define RCC_APB2RSTR_TIM8RST_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 13962 | #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 13963 | #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13964 | #define RCC_APB2RSTR_USART1RST_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 13965 | #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 13966 | #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13967 | #define RCC_APB2RSTR_USART6RST_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 13968 | #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 13969 | #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13970 | #define RCC_APB2RSTR_ADCRST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 13971 | #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 13972 | #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13973 | #define RCC_APB2RSTR_SDIORST_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 13974 | #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 13975 | #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk |
| AnnaBridge | 167:e84263d55307 | 13976 | #define RCC_APB2RSTR_SPI1RST_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 13977 | #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 13978 | #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13979 | #define RCC_APB2RSTR_SPI4RST_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 13980 | #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 13981 | #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13982 | #define RCC_APB2RSTR_SYSCFGRST_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 13983 | #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 13984 | #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk |
| AnnaBridge | 167:e84263d55307 | 13985 | #define RCC_APB2RSTR_TIM9RST_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 13986 | #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 13987 | #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13988 | #define RCC_APB2RSTR_TIM10RST_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 13989 | #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 13990 | #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13991 | #define RCC_APB2RSTR_TIM11RST_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 13992 | #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 13993 | #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13994 | #define RCC_APB2RSTR_SPI5RST_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 13995 | #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 13996 | #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk |
| AnnaBridge | 167:e84263d55307 | 13997 | #define RCC_APB2RSTR_SPI6RST_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 13998 | #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 13999 | #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk |
| AnnaBridge | 167:e84263d55307 | 14000 | #define RCC_APB2RSTR_SAI1RST_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 14001 | #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14002 | #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk |
| AnnaBridge | 167:e84263d55307 | 14003 | #define RCC_APB2RSTR_LTDCRST_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 14004 | #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14005 | #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk |
| AnnaBridge | 167:e84263d55307 | 14006 | #define RCC_APB2RSTR_DSIRST_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 14007 | #define RCC_APB2RSTR_DSIRST_Msk (0x1U << RCC_APB2RSTR_DSIRST_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 14008 | #define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk |
| mbed_official | 19:112740acecfa | 14009 | |
| mbed_official | 19:112740acecfa | 14010 | /* Old SPI1RST bit definition, maintained for legacy purpose */ |
| mbed_official | 19:112740acecfa | 14011 | #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST |
| mbed_official | 19:112740acecfa | 14012 | |
| mbed_official | 19:112740acecfa | 14013 | /******************** Bit definition for RCC_AHB1ENR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 14014 | #define RCC_AHB1ENR_GPIOAEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14015 | #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14016 | #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14017 | #define RCC_AHB1ENR_GPIOBEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14018 | #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14019 | #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14020 | #define RCC_AHB1ENR_GPIOCEN_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 14021 | #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14022 | #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14023 | #define RCC_AHB1ENR_GPIODEN_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 14024 | #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 14025 | #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14026 | #define RCC_AHB1ENR_GPIOEEN_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14027 | #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14028 | #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14029 | #define RCC_AHB1ENR_GPIOFEN_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 14030 | #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14031 | #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14032 | #define RCC_AHB1ENR_GPIOGEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14033 | #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14034 | #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14035 | #define RCC_AHB1ENR_GPIOHEN_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 14036 | #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14037 | #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14038 | #define RCC_AHB1ENR_GPIOIEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14039 | #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14040 | #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14041 | #define RCC_AHB1ENR_GPIOJEN_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 14042 | #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14043 | #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14044 | #define RCC_AHB1ENR_GPIOKEN_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 14045 | #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14046 | #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14047 | #define RCC_AHB1ENR_CRCEN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 14048 | #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14049 | #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14050 | #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 14051 | #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 14052 | #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14053 | #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 14054 | #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 14055 | #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14056 | #define RCC_AHB1ENR_DMA1EN_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 14057 | #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14058 | #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14059 | #define RCC_AHB1ENR_DMA2EN_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 14060 | #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14061 | #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14062 | #define RCC_AHB1ENR_DMA2DEN_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 14063 | #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 14064 | #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14065 | #define RCC_AHB1ENR_ETHMACEN_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 14066 | #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 14067 | #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14068 | #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 14069 | #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14070 | #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14071 | #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 14072 | #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 14073 | #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14074 | #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 14075 | #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 14076 | #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14077 | #define RCC_AHB1ENR_OTGHSEN_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 14078 | #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 14079 | #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14080 | #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 14081 | #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 14082 | #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk |
| mbed_official | 19:112740acecfa | 14083 | /******************** Bit definition for RCC_AHB2ENR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 14084 | /* |
| AnnaBridge | 167:e84263d55307 | 14085 | * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) |
| AnnaBridge | 167:e84263d55307 | 14086 | */ |
| AnnaBridge | 167:e84263d55307 | 14087 | #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */ |
| AnnaBridge | 167:e84263d55307 | 14088 | |
| AnnaBridge | 167:e84263d55307 | 14089 | #define RCC_AHB2ENR_DCMIEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14090 | #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14091 | #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14092 | #define RCC_AHB2ENR_RNGEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14093 | #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14094 | #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14095 | #define RCC_AHB2ENR_OTGFSEN_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 14096 | #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14097 | #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk |
| mbed_official | 19:112740acecfa | 14098 | |
| mbed_official | 19:112740acecfa | 14099 | /******************** Bit definition for RCC_AHB3ENR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 14100 | /* |
| AnnaBridge | 167:e84263d55307 | 14101 | * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) |
| AnnaBridge | 167:e84263d55307 | 14102 | */ |
| AnnaBridge | 167:e84263d55307 | 14103 | #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */ |
| AnnaBridge | 167:e84263d55307 | 14104 | |
| AnnaBridge | 167:e84263d55307 | 14105 | #define RCC_AHB3ENR_FMCEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14106 | #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14107 | #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14108 | #define RCC_AHB3ENR_QSPIEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14109 | #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14110 | #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk |
| mbed_official | 19:112740acecfa | 14111 | |
| mbed_official | 19:112740acecfa | 14112 | /******************** Bit definition for RCC_APB1ENR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 14113 | #define RCC_APB1ENR_TIM2EN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14114 | #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14115 | #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14116 | #define RCC_APB1ENR_TIM3EN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14117 | #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14118 | #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14119 | #define RCC_APB1ENR_TIM4EN_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 14120 | #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14121 | #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14122 | #define RCC_APB1ENR_TIM5EN_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 14123 | #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 14124 | #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14125 | #define RCC_APB1ENR_TIM6EN_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14126 | #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14127 | #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14128 | #define RCC_APB1ENR_TIM7EN_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 14129 | #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14130 | #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14131 | #define RCC_APB1ENR_TIM12EN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14132 | #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14133 | #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14134 | #define RCC_APB1ENR_TIM13EN_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 14135 | #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14136 | #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14137 | #define RCC_APB1ENR_TIM14EN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14138 | #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14139 | #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14140 | #define RCC_APB1ENR_WWDGEN_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 14141 | #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14142 | #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14143 | #define RCC_APB1ENR_SPI2EN_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 14144 | #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14145 | #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14146 | #define RCC_APB1ENR_SPI3EN_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 14147 | #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 14148 | #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14149 | #define RCC_APB1ENR_USART2EN_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 14150 | #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14151 | #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14152 | #define RCC_APB1ENR_USART3EN_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 14153 | #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 14154 | #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14155 | #define RCC_APB1ENR_UART4EN_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 14156 | #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 14157 | #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14158 | #define RCC_APB1ENR_UART5EN_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 14159 | #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 14160 | #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14161 | #define RCC_APB1ENR_I2C1EN_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 14162 | #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14163 | #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14164 | #define RCC_APB1ENR_I2C2EN_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 14165 | #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14166 | #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14167 | #define RCC_APB1ENR_I2C3EN_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 14168 | #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 14169 | #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14170 | #define RCC_APB1ENR_CAN1EN_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 14171 | #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 14172 | #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14173 | #define RCC_APB1ENR_CAN2EN_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 14174 | #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14175 | #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14176 | #define RCC_APB1ENR_PWREN_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 14177 | #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 14178 | #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk |
| AnnaBridge | 167:e84263d55307 | 14179 | #define RCC_APB1ENR_DACEN_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 14180 | #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 14181 | #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14182 | #define RCC_APB1ENR_UART7EN_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 14183 | #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 14184 | #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14185 | #define RCC_APB1ENR_UART8EN_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 14186 | #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 14187 | #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk |
| mbed_official | 19:112740acecfa | 14188 | |
| mbed_official | 19:112740acecfa | 14189 | /******************** Bit definition for RCC_APB2ENR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 14190 | #define RCC_APB2ENR_TIM1EN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14191 | #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14192 | #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14193 | #define RCC_APB2ENR_TIM8EN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14194 | #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14195 | #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14196 | #define RCC_APB2ENR_USART1EN_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14197 | #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14198 | #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14199 | #define RCC_APB2ENR_USART6EN_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 14200 | #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14201 | #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14202 | #define RCC_APB2ENR_ADC1EN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14203 | #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14204 | #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14205 | #define RCC_APB2ENR_ADC2EN_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 14206 | #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14207 | #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14208 | #define RCC_APB2ENR_ADC3EN_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 14209 | #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14210 | #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14211 | #define RCC_APB2ENR_SDIOEN_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 14212 | #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14213 | #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14214 | #define RCC_APB2ENR_SPI1EN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 14215 | #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14216 | #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14217 | #define RCC_APB2ENR_SPI4EN_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 14218 | #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 14219 | #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14220 | #define RCC_APB2ENR_SYSCFGEN_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 14221 | #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14222 | #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14223 | #define RCC_APB2ENR_TIM9EN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14224 | #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14225 | #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14226 | #define RCC_APB2ENR_TIM10EN_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 14227 | #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14228 | #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14229 | #define RCC_APB2ENR_TIM11EN_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 14230 | #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 14231 | #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14232 | #define RCC_APB2ENR_SPI5EN_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 14233 | #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 14234 | #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14235 | #define RCC_APB2ENR_SPI6EN_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 14236 | #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14237 | #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14238 | #define RCC_APB2ENR_SAI1EN_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 14239 | #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14240 | #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk |
| AnnaBridge | 167:e84263d55307 | 14241 | #define RCC_APB2ENR_LTDCEN_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 14242 | #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14243 | #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14244 | #define RCC_APB2ENR_DSIEN_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 14245 | #define RCC_APB2ENR_DSIEN_Msk (0x1U << RCC_APB2ENR_DSIEN_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 14246 | #define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk |
| mbed_official | 19:112740acecfa | 14247 | |
| mbed_official | 19:112740acecfa | 14248 | /******************** Bit definition for RCC_AHB1LPENR register *************/ |
| AnnaBridge | 167:e84263d55307 | 14249 | #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14250 | #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14251 | #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14252 | #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14253 | #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14254 | #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14255 | #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 14256 | #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14257 | #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14258 | #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 14259 | #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 14260 | #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14261 | #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14262 | #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14263 | #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14264 | #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 14265 | #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14266 | #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14267 | #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14268 | #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14269 | #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14270 | #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 14271 | #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14272 | #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14273 | #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14274 | #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14275 | #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14276 | #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 14277 | #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14278 | #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14279 | #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 14280 | #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14281 | #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14282 | #define RCC_AHB1LPENR_CRCLPEN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 14283 | #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14284 | #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14285 | #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 14286 | #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 14287 | #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14288 | #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14289 | #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14290 | #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14291 | #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 14292 | #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14293 | #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14294 | #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 14295 | #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 14296 | #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14297 | #define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 14298 | #define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 14299 | #define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14300 | #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 14301 | #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14302 | #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14303 | #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 14304 | #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14305 | #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14306 | #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 14307 | #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 14308 | #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14309 | |
| AnnaBridge | 167:e84263d55307 | 14310 | #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 14311 | #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 14312 | #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14313 | #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 14314 | #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14315 | #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14316 | #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 14317 | #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 14318 | #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14319 | #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 14320 | #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 14321 | #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14322 | #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 14323 | #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 14324 | #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14325 | #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 14326 | #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 14327 | #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk |
| mbed_official | 19:112740acecfa | 14328 | |
| mbed_official | 19:112740acecfa | 14329 | /******************** Bit definition for RCC_AHB2LPENR register *************/ |
| AnnaBridge | 167:e84263d55307 | 14330 | #define RCC_AHB2LPENR_DCMILPEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14331 | #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14332 | #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14333 | #define RCC_AHB2LPENR_RNGLPEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14334 | #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14335 | #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14336 | #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 14337 | #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14338 | #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk |
| mbed_official | 19:112740acecfa | 14339 | |
| mbed_official | 19:112740acecfa | 14340 | /******************** Bit definition for RCC_AHB3LPENR register *************/ |
| AnnaBridge | 167:e84263d55307 | 14341 | #define RCC_AHB3LPENR_FMCLPEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14342 | #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14343 | #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14344 | #define RCC_AHB3LPENR_QSPILPEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14345 | #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14346 | #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk |
| mbed_official | 19:112740acecfa | 14347 | |
| mbed_official | 19:112740acecfa | 14348 | /******************** Bit definition for RCC_APB1LPENR register *************/ |
| AnnaBridge | 167:e84263d55307 | 14349 | #define RCC_APB1LPENR_TIM2LPEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14350 | #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14351 | #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14352 | #define RCC_APB1LPENR_TIM3LPEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14353 | #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14354 | #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14355 | #define RCC_APB1LPENR_TIM4LPEN_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 14356 | #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14357 | #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14358 | #define RCC_APB1LPENR_TIM5LPEN_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 14359 | #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 14360 | #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14361 | #define RCC_APB1LPENR_TIM6LPEN_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14362 | #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14363 | #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14364 | #define RCC_APB1LPENR_TIM7LPEN_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 14365 | #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14366 | #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14367 | #define RCC_APB1LPENR_TIM12LPEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14368 | #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14369 | #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14370 | #define RCC_APB1LPENR_TIM13LPEN_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 14371 | #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14372 | #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14373 | #define RCC_APB1LPENR_TIM14LPEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14374 | #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14375 | #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14376 | #define RCC_APB1LPENR_WWDGLPEN_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 14377 | #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14378 | #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14379 | #define RCC_APB1LPENR_SPI2LPEN_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 14380 | #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14381 | #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14382 | #define RCC_APB1LPENR_SPI3LPEN_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 14383 | #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 14384 | #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14385 | #define RCC_APB1LPENR_USART2LPEN_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 14386 | #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14387 | #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14388 | #define RCC_APB1LPENR_USART3LPEN_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 14389 | #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 14390 | #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14391 | #define RCC_APB1LPENR_UART4LPEN_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 14392 | #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 14393 | #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14394 | #define RCC_APB1LPENR_UART5LPEN_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 14395 | #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 14396 | #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14397 | #define RCC_APB1LPENR_I2C1LPEN_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 14398 | #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14399 | #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14400 | #define RCC_APB1LPENR_I2C2LPEN_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 14401 | #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14402 | #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14403 | #define RCC_APB1LPENR_I2C3LPEN_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 14404 | #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 14405 | #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14406 | #define RCC_APB1LPENR_CAN1LPEN_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 14407 | #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 14408 | #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14409 | #define RCC_APB1LPENR_CAN2LPEN_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 14410 | #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14411 | #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14412 | #define RCC_APB1LPENR_PWRLPEN_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 14413 | #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 14414 | #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14415 | #define RCC_APB1LPENR_DACLPEN_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 14416 | #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 14417 | #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14418 | #define RCC_APB1LPENR_UART7LPEN_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 14419 | #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 14420 | #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14421 | #define RCC_APB1LPENR_UART8LPEN_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 14422 | #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 14423 | #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk |
| mbed_official | 19:112740acecfa | 14424 | |
| mbed_official | 19:112740acecfa | 14425 | /******************** Bit definition for RCC_APB2LPENR register *************/ |
| AnnaBridge | 167:e84263d55307 | 14426 | #define RCC_APB2LPENR_TIM1LPEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14427 | #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14428 | #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14429 | #define RCC_APB2LPENR_TIM8LPEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14430 | #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14431 | #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14432 | #define RCC_APB2LPENR_USART1LPEN_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14433 | #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14434 | #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14435 | #define RCC_APB2LPENR_USART6LPEN_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 14436 | #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14437 | #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14438 | #define RCC_APB2LPENR_ADC1LPEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14439 | #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14440 | #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14441 | #define RCC_APB2LPENR_ADC2LPEN_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 14442 | #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14443 | #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14444 | #define RCC_APB2LPENR_ADC3LPEN_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 14445 | #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14446 | #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14447 | #define RCC_APB2LPENR_SDIOLPEN_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 14448 | #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14449 | #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14450 | #define RCC_APB2LPENR_SPI1LPEN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 14451 | #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14452 | #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14453 | #define RCC_APB2LPENR_SPI4LPEN_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 14454 | #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 14455 | #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14456 | #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 14457 | #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14458 | #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14459 | #define RCC_APB2LPENR_TIM9LPEN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14460 | #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14461 | #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14462 | #define RCC_APB2LPENR_TIM10LPEN_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 14463 | #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14464 | #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14465 | #define RCC_APB2LPENR_TIM11LPEN_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 14466 | #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 14467 | #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14468 | #define RCC_APB2LPENR_SPI5LPEN_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 14469 | #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 14470 | #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14471 | #define RCC_APB2LPENR_SPI6LPEN_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 14472 | #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14473 | #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14474 | #define RCC_APB2LPENR_SAI1LPEN_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 14475 | #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14476 | #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14477 | #define RCC_APB2LPENR_LTDCLPEN_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 14478 | #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14479 | #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14480 | #define RCC_APB2LPENR_DSILPEN_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 14481 | #define RCC_APB2LPENR_DSILPEN_Msk (0x1U << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 14482 | #define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk |
| mbed_official | 19:112740acecfa | 14483 | |
| mbed_official | 19:112740acecfa | 14484 | /******************** Bit definition for RCC_BDCR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 14485 | #define RCC_BDCR_LSEON_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14486 | #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14487 | #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk |
| AnnaBridge | 167:e84263d55307 | 14488 | #define RCC_BDCR_LSERDY_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14489 | #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14490 | #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk |
| AnnaBridge | 167:e84263d55307 | 14491 | #define RCC_BDCR_LSEBYP_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 14492 | #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14493 | #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk |
| AnnaBridge | 167:e84263d55307 | 14494 | #define RCC_BDCR_LSEMOD_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 14495 | #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 14496 | #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk |
| AnnaBridge | 167:e84263d55307 | 14497 | |
| AnnaBridge | 167:e84263d55307 | 14498 | #define RCC_BDCR_RTCSEL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14499 | #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 14500 | #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 14501 | #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14502 | #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14503 | |
| AnnaBridge | 167:e84263d55307 | 14504 | #define RCC_BDCR_RTCEN_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 14505 | #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 14506 | #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14507 | #define RCC_BDCR_BDRST_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14508 | #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14509 | #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk |
| mbed_official | 19:112740acecfa | 14510 | |
| mbed_official | 19:112740acecfa | 14511 | /******************** Bit definition for RCC_CSR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 14512 | #define RCC_CSR_LSION_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14513 | #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14514 | #define RCC_CSR_LSION RCC_CSR_LSION_Msk |
| AnnaBridge | 167:e84263d55307 | 14515 | #define RCC_CSR_LSIRDY_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14516 | #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14517 | #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk |
| AnnaBridge | 167:e84263d55307 | 14518 | #define RCC_CSR_RMVF_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 14519 | #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 14520 | #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk |
| AnnaBridge | 167:e84263d55307 | 14521 | #define RCC_CSR_BORRSTF_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 14522 | #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 14523 | #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk |
| AnnaBridge | 167:e84263d55307 | 14524 | #define RCC_CSR_PINRSTF_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 14525 | #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14526 | #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk |
| AnnaBridge | 167:e84263d55307 | 14527 | #define RCC_CSR_PORRSTF_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 14528 | #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 14529 | #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk |
| AnnaBridge | 167:e84263d55307 | 14530 | #define RCC_CSR_SFTRSTF_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 14531 | #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 14532 | #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk |
| AnnaBridge | 167:e84263d55307 | 14533 | #define RCC_CSR_IWDGRSTF_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 14534 | #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 14535 | #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk |
| AnnaBridge | 167:e84263d55307 | 14536 | #define RCC_CSR_WWDGRSTF_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 14537 | #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 14538 | #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk |
| AnnaBridge | 167:e84263d55307 | 14539 | #define RCC_CSR_LPWRRSTF_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 14540 | #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 14541 | #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk |
| AnnaBridge | 167:e84263d55307 | 14542 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 14543 | #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF |
| AnnaBridge | 167:e84263d55307 | 14544 | #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF |
| mbed_official | 19:112740acecfa | 14545 | |
| mbed_official | 19:112740acecfa | 14546 | /******************** Bit definition for RCC_SSCGR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 14547 | #define RCC_SSCGR_MODPER_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14548 | #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */ |
| AnnaBridge | 167:e84263d55307 | 14549 | #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk |
| AnnaBridge | 167:e84263d55307 | 14550 | #define RCC_SSCGR_INCSTEP_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 14551 | #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */ |
| AnnaBridge | 167:e84263d55307 | 14552 | #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk |
| AnnaBridge | 167:e84263d55307 | 14553 | #define RCC_SSCGR_SPREADSEL_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 14554 | #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 14555 | #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 14556 | #define RCC_SSCGR_SSCGEN_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 14557 | #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 14558 | #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk |
| mbed_official | 19:112740acecfa | 14559 | |
| mbed_official | 19:112740acecfa | 14560 | /******************** Bit definition for RCC_PLLI2SCFGR register ************/ |
| AnnaBridge | 167:e84263d55307 | 14561 | #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14562 | #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */ |
| AnnaBridge | 167:e84263d55307 | 14563 | #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk |
| AnnaBridge | 167:e84263d55307 | 14564 | #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14565 | #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14566 | #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14567 | #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14568 | #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14569 | #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14570 | #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14571 | #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 14572 | #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14573 | |
| AnnaBridge | 167:e84263d55307 | 14574 | #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 14575 | #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 14576 | #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk |
| AnnaBridge | 167:e84263d55307 | 14577 | #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 14578 | #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 14579 | #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14580 | #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 14581 | #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 14582 | #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */ |
| AnnaBridge | 167:e84263d55307 | 14583 | #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk |
| AnnaBridge | 167:e84263d55307 | 14584 | #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 14585 | #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 14586 | #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */ |
| mbed_official | 19:112740acecfa | 14587 | |
| mbed_official | 19:112740acecfa | 14588 | /******************** Bit definition for RCC_PLLSAICFGR register ************/ |
| AnnaBridge | 167:e84263d55307 | 14589 | #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14590 | #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */ |
| AnnaBridge | 167:e84263d55307 | 14591 | #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk |
| AnnaBridge | 167:e84263d55307 | 14592 | #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14593 | #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14594 | #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14595 | #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14596 | #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14597 | #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14598 | #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14599 | #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 14600 | #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14601 | |
| AnnaBridge | 167:e84263d55307 | 14602 | #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14603 | #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 14604 | #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk |
| AnnaBridge | 167:e84263d55307 | 14605 | #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14606 | #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14607 | |
| AnnaBridge | 167:e84263d55307 | 14608 | #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 14609 | #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 14610 | #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk |
| AnnaBridge | 167:e84263d55307 | 14611 | #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 14612 | #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 14613 | #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14614 | #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 14615 | |
| AnnaBridge | 167:e84263d55307 | 14616 | #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 14617 | #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */ |
| AnnaBridge | 167:e84263d55307 | 14618 | #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk |
| AnnaBridge | 167:e84263d55307 | 14619 | #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 14620 | #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 14621 | #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */ |
| mbed_official | 19:112740acecfa | 14622 | |
| mbed_official | 19:112740acecfa | 14623 | /******************** Bit definition for RCC_DCKCFGR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 14624 | #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14625 | #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 167:e84263d55307 | 14626 | #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk |
| AnnaBridge | 167:e84263d55307 | 14627 | #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14628 | #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14629 | #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14630 | #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 14631 | #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14632 | |
| AnnaBridge | 167:e84263d55307 | 14633 | #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14634 | #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 167:e84263d55307 | 14635 | #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk |
| AnnaBridge | 167:e84263d55307 | 14636 | #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14637 | #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14638 | #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14639 | #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14640 | #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14641 | #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14642 | #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 14643 | #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk |
| AnnaBridge | 167:e84263d55307 | 14644 | #define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14645 | #define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14646 | |
| AnnaBridge | 167:e84263d55307 | 14647 | #define RCC_DCKCFGR_SAI1ASRC_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 14648 | #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 14649 | #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk |
| AnnaBridge | 167:e84263d55307 | 14650 | #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 14651 | #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14652 | #define RCC_DCKCFGR_SAI1BSRC_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 14653 | #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 167:e84263d55307 | 14654 | #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk |
| AnnaBridge | 167:e84263d55307 | 14655 | #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14656 | #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 14657 | #define RCC_DCKCFGR_TIMPRE_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 14658 | #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 14659 | #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk |
| AnnaBridge | 167:e84263d55307 | 14660 | #define RCC_DCKCFGR_CK48MSEL_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 14661 | #define RCC_DCKCFGR_CK48MSEL_Msk (0x1U << RCC_DCKCFGR_CK48MSEL_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 14662 | #define RCC_DCKCFGR_CK48MSEL RCC_DCKCFGR_CK48MSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 14663 | #define RCC_DCKCFGR_SDIOSEL_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 14664 | #define RCC_DCKCFGR_SDIOSEL_Msk (0x1U << RCC_DCKCFGR_SDIOSEL_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 14665 | #define RCC_DCKCFGR_SDIOSEL RCC_DCKCFGR_SDIOSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 14666 | #define RCC_DCKCFGR_DSISEL_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 14667 | #define RCC_DCKCFGR_DSISEL_Msk (0x1U << RCC_DCKCFGR_DSISEL_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 14668 | #define RCC_DCKCFGR_DSISEL RCC_DCKCFGR_DSISEL_Msk |
| AnnaBridge | 167:e84263d55307 | 14669 | |
| mbed_official | 19:112740acecfa | 14670 | |
| mbed_official | 19:112740acecfa | 14671 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 14672 | /* */ |
| mbed_official | 19:112740acecfa | 14673 | /* RNG */ |
| mbed_official | 19:112740acecfa | 14674 | /* */ |
| mbed_official | 19:112740acecfa | 14675 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 14676 | /******************** Bits definition for RNG_CR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 14677 | #define RNG_CR_RNGEN_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 14678 | #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14679 | #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk |
| AnnaBridge | 167:e84263d55307 | 14680 | #define RNG_CR_IE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 14681 | #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 14682 | #define RNG_CR_IE RNG_CR_IE_Msk |
| mbed_official | 19:112740acecfa | 14683 | |
| mbed_official | 19:112740acecfa | 14684 | /******************** Bits definition for RNG_SR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 14685 | #define RNG_SR_DRDY_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14686 | #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14687 | #define RNG_SR_DRDY RNG_SR_DRDY_Msk |
| AnnaBridge | 167:e84263d55307 | 14688 | #define RNG_SR_CECS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14689 | #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14690 | #define RNG_SR_CECS RNG_SR_CECS_Msk |
| AnnaBridge | 167:e84263d55307 | 14691 | #define RNG_SR_SECS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 14692 | #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14693 | #define RNG_SR_SECS RNG_SR_SECS_Msk |
| AnnaBridge | 167:e84263d55307 | 14694 | #define RNG_SR_CEIS_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 14695 | #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14696 | #define RNG_SR_CEIS RNG_SR_CEIS_Msk |
| AnnaBridge | 167:e84263d55307 | 14697 | #define RNG_SR_SEIS_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14698 | #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14699 | #define RNG_SR_SEIS RNG_SR_SEIS_Msk |
| mbed_official | 19:112740acecfa | 14700 | |
| mbed_official | 19:112740acecfa | 14701 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 14702 | /* */ |
| mbed_official | 19:112740acecfa | 14703 | /* Real-Time Clock (RTC) */ |
| mbed_official | 19:112740acecfa | 14704 | /* */ |
| mbed_official | 19:112740acecfa | 14705 | /******************************************************************************/ |
| AnnaBridge | 167:e84263d55307 | 14706 | /* |
| AnnaBridge | 167:e84263d55307 | 14707 | * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) |
| AnnaBridge | 167:e84263d55307 | 14708 | */ |
| AnnaBridge | 167:e84263d55307 | 14709 | #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ |
| AnnaBridge | 167:e84263d55307 | 14710 | #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */ |
| mbed_official | 19:112740acecfa | 14711 | /******************** Bits definition for RTC_TR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 14712 | #define RTC_TR_PM_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 14713 | #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14714 | #define RTC_TR_PM RTC_TR_PM_Msk |
| AnnaBridge | 167:e84263d55307 | 14715 | #define RTC_TR_HT_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 14716 | #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 14717 | #define RTC_TR_HT RTC_TR_HT_Msk |
| AnnaBridge | 167:e84263d55307 | 14718 | #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 14719 | #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14720 | #define RTC_TR_HU_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14721 | #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 14722 | #define RTC_TR_HU RTC_TR_HU_Msk |
| AnnaBridge | 167:e84263d55307 | 14723 | #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14724 | #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14725 | #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 14726 | #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 14727 | #define RTC_TR_MNT_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 14728 | #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 167:e84263d55307 | 14729 | #define RTC_TR_MNT RTC_TR_MNT_Msk |
| AnnaBridge | 167:e84263d55307 | 14730 | #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14731 | #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 14732 | #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14733 | #define RTC_TR_MNU_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14734 | #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 14735 | #define RTC_TR_MNU RTC_TR_MNU_Msk |
| AnnaBridge | 167:e84263d55307 | 14736 | #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14737 | #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14738 | #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14739 | #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14740 | #define RTC_TR_ST_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14741 | #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 14742 | #define RTC_TR_ST RTC_TR_ST_Msk |
| AnnaBridge | 167:e84263d55307 | 14743 | #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14744 | #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14745 | #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14746 | #define RTC_TR_SU_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14747 | #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 14748 | #define RTC_TR_SU RTC_TR_SU_Msk |
| AnnaBridge | 167:e84263d55307 | 14749 | #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14750 | #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14751 | #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14752 | #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ |
| mbed_official | 19:112740acecfa | 14753 | |
| mbed_official | 19:112740acecfa | 14754 | /******************** Bits definition for RTC_DR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 14755 | #define RTC_DR_YT_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 14756 | #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 14757 | #define RTC_DR_YT RTC_DR_YT_Msk |
| AnnaBridge | 167:e84263d55307 | 14758 | #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 14759 | #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14760 | #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14761 | #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 14762 | #define RTC_DR_YU_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14763 | #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 14764 | #define RTC_DR_YU RTC_DR_YU_Msk |
| AnnaBridge | 167:e84263d55307 | 14765 | #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14766 | #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14767 | #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 14768 | #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 14769 | #define RTC_DR_WDU_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 14770 | #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ |
| AnnaBridge | 167:e84263d55307 | 14771 | #define RTC_DR_WDU RTC_DR_WDU_Msk |
| AnnaBridge | 167:e84263d55307 | 14772 | #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 14773 | #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14774 | #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 14775 | #define RTC_DR_MT_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 14776 | #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14777 | #define RTC_DR_MT RTC_DR_MT_Msk |
| AnnaBridge | 167:e84263d55307 | 14778 | #define RTC_DR_MU_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14779 | #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 14780 | #define RTC_DR_MU RTC_DR_MU_Msk |
| AnnaBridge | 167:e84263d55307 | 14781 | #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14782 | #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14783 | #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14784 | #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14785 | #define RTC_DR_DT_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14786 | #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 14787 | #define RTC_DR_DT RTC_DR_DT_Msk |
| AnnaBridge | 167:e84263d55307 | 14788 | #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14789 | #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14790 | #define RTC_DR_DU_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14791 | #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 14792 | #define RTC_DR_DU RTC_DR_DU_Msk |
| AnnaBridge | 167:e84263d55307 | 14793 | #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14794 | #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14795 | #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14796 | #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ |
| mbed_official | 19:112740acecfa | 14797 | |
| mbed_official | 19:112740acecfa | 14798 | /******************** Bits definition for RTC_CR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 14799 | #define RTC_CR_COE_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 14800 | #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 14801 | #define RTC_CR_COE RTC_CR_COE_Msk |
| AnnaBridge | 167:e84263d55307 | 14802 | #define RTC_CR_OSEL_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 14803 | #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 167:e84263d55307 | 14804 | #define RTC_CR_OSEL RTC_CR_OSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 14805 | #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14806 | #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14807 | #define RTC_CR_POL_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 14808 | #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 14809 | #define RTC_CR_POL RTC_CR_POL_Msk |
| AnnaBridge | 167:e84263d55307 | 14810 | #define RTC_CR_COSEL_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 14811 | #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 14812 | #define RTC_CR_COSEL RTC_CR_COSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 14813 | #define RTC_CR_BKP_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 14814 | #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 14815 | #define RTC_CR_BKP RTC_CR_BKP_Msk |
| AnnaBridge | 167:e84263d55307 | 14816 | #define RTC_CR_SUB1H_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 14817 | #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14818 | #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk |
| AnnaBridge | 167:e84263d55307 | 14819 | #define RTC_CR_ADD1H_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14820 | #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14821 | #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk |
| AnnaBridge | 167:e84263d55307 | 14822 | #define RTC_CR_TSIE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 14823 | #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 14824 | #define RTC_CR_TSIE RTC_CR_TSIE_Msk |
| AnnaBridge | 167:e84263d55307 | 14825 | #define RTC_CR_WUTIE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 14826 | #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14827 | #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk |
| AnnaBridge | 167:e84263d55307 | 14828 | #define RTC_CR_ALRBIE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 14829 | #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 14830 | #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk |
| AnnaBridge | 167:e84263d55307 | 14831 | #define RTC_CR_ALRAIE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 14832 | #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14833 | #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk |
| AnnaBridge | 167:e84263d55307 | 14834 | #define RTC_CR_TSE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 14835 | #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14836 | #define RTC_CR_TSE RTC_CR_TSE_Msk |
| AnnaBridge | 167:e84263d55307 | 14837 | #define RTC_CR_WUTE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 14838 | #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14839 | #define RTC_CR_WUTE RTC_CR_WUTE_Msk |
| AnnaBridge | 167:e84263d55307 | 14840 | #define RTC_CR_ALRBE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 14841 | #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14842 | #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk |
| AnnaBridge | 167:e84263d55307 | 14843 | #define RTC_CR_ALRAE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14844 | #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14845 | #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk |
| AnnaBridge | 167:e84263d55307 | 14846 | #define RTC_CR_DCE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 14847 | #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14848 | #define RTC_CR_DCE RTC_CR_DCE_Msk |
| AnnaBridge | 167:e84263d55307 | 14849 | #define RTC_CR_FMT_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14850 | #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14851 | #define RTC_CR_FMT RTC_CR_FMT_Msk |
| AnnaBridge | 167:e84263d55307 | 14852 | #define RTC_CR_BYPSHAD_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 14853 | #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14854 | #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk |
| AnnaBridge | 167:e84263d55307 | 14855 | #define RTC_CR_REFCKON_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14856 | #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14857 | #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk |
| AnnaBridge | 167:e84263d55307 | 14858 | #define RTC_CR_TSEDGE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 14859 | #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 14860 | #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk |
| AnnaBridge | 167:e84263d55307 | 14861 | #define RTC_CR_WUCKSEL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14862 | #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 14863 | #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 14864 | #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14865 | #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14866 | #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14867 | |
| AnnaBridge | 167:e84263d55307 | 14868 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 14869 | #define RTC_CR_BCK RTC_CR_BKP |
| mbed_official | 19:112740acecfa | 14870 | |
| mbed_official | 19:112740acecfa | 14871 | /******************** Bits definition for RTC_ISR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 14872 | #define RTC_ISR_RECALPF_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14873 | #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14874 | #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk |
| AnnaBridge | 167:e84263d55307 | 14875 | #define RTC_ISR_TAMP1F_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 14876 | #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 14877 | #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk |
| AnnaBridge | 167:e84263d55307 | 14878 | #define RTC_ISR_TAMP2F_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 14879 | #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14880 | #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk |
| AnnaBridge | 167:e84263d55307 | 14881 | #define RTC_ISR_TSOVF_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 14882 | #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14883 | #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk |
| AnnaBridge | 167:e84263d55307 | 14884 | #define RTC_ISR_TSF_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 14885 | #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14886 | #define RTC_ISR_TSF RTC_ISR_TSF_Msk |
| AnnaBridge | 167:e84263d55307 | 14887 | #define RTC_ISR_WUTF_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 14888 | #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14889 | #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk |
| AnnaBridge | 167:e84263d55307 | 14890 | #define RTC_ISR_ALRBF_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 14891 | #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14892 | #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk |
| AnnaBridge | 167:e84263d55307 | 14893 | #define RTC_ISR_ALRAF_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14894 | #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14895 | #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk |
| AnnaBridge | 167:e84263d55307 | 14896 | #define RTC_ISR_INIT_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 14897 | #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14898 | #define RTC_ISR_INIT RTC_ISR_INIT_Msk |
| AnnaBridge | 167:e84263d55307 | 14899 | #define RTC_ISR_INITF_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 14900 | #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 14901 | #define RTC_ISR_INITF RTC_ISR_INITF_Msk |
| AnnaBridge | 167:e84263d55307 | 14902 | #define RTC_ISR_RSF_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 14903 | #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 14904 | #define RTC_ISR_RSF RTC_ISR_RSF_Msk |
| AnnaBridge | 167:e84263d55307 | 14905 | #define RTC_ISR_INITS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14906 | #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 14907 | #define RTC_ISR_INITS RTC_ISR_INITS_Msk |
| AnnaBridge | 167:e84263d55307 | 14908 | #define RTC_ISR_SHPF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 14909 | #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 14910 | #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk |
| AnnaBridge | 167:e84263d55307 | 14911 | #define RTC_ISR_WUTWF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 14912 | #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 14913 | #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk |
| AnnaBridge | 167:e84263d55307 | 14914 | #define RTC_ISR_ALRBWF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 14915 | #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 14916 | #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk |
| AnnaBridge | 167:e84263d55307 | 14917 | #define RTC_ISR_ALRAWF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14918 | #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 14919 | #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk |
| mbed_official | 19:112740acecfa | 14920 | |
| mbed_official | 19:112740acecfa | 14921 | /******************** Bits definition for RTC_PRER register *****************/ |
| AnnaBridge | 167:e84263d55307 | 14922 | #define RTC_PRER_PREDIV_A_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14923 | #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ |
| AnnaBridge | 167:e84263d55307 | 14924 | #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk |
| AnnaBridge | 167:e84263d55307 | 14925 | #define RTC_PRER_PREDIV_S_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14926 | #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 167:e84263d55307 | 14927 | #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk |
| mbed_official | 19:112740acecfa | 14928 | |
| mbed_official | 19:112740acecfa | 14929 | /******************** Bits definition for RTC_WUTR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 14930 | #define RTC_WUTR_WUT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14931 | #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 14932 | #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk |
| mbed_official | 19:112740acecfa | 14933 | |
| mbed_official | 19:112740acecfa | 14934 | /******************** Bits definition for RTC_CALIBR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 14935 | #define RTC_CALIBR_DCS_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 14936 | #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14937 | #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk |
| AnnaBridge | 167:e84263d55307 | 14938 | #define RTC_CALIBR_DC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 14939 | #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 167:e84263d55307 | 14940 | #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk |
| mbed_official | 19:112740acecfa | 14941 | |
| mbed_official | 19:112740acecfa | 14942 | /******************** Bits definition for RTC_ALRMAR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 14943 | #define RTC_ALRMAR_MSK4_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 14944 | #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 14945 | #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk |
| AnnaBridge | 167:e84263d55307 | 14946 | #define RTC_ALRMAR_WDSEL_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 14947 | #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 14948 | #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 14949 | #define RTC_ALRMAR_DT_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 14950 | #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 14951 | #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk |
| AnnaBridge | 167:e84263d55307 | 14952 | #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 14953 | #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 14954 | #define RTC_ALRMAR_DU_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 14955 | #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 14956 | #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk |
| AnnaBridge | 167:e84263d55307 | 14957 | #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 14958 | #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 14959 | #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 14960 | #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 14961 | #define RTC_ALRMAR_MSK3_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 14962 | #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 14963 | #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk |
| AnnaBridge | 167:e84263d55307 | 14964 | #define RTC_ALRMAR_PM_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 14965 | #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 14966 | #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk |
| AnnaBridge | 167:e84263d55307 | 14967 | #define RTC_ALRMAR_HT_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 14968 | #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 14969 | #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk |
| AnnaBridge | 167:e84263d55307 | 14970 | #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 14971 | #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 14972 | #define RTC_ALRMAR_HU_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 14973 | #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 14974 | #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk |
| AnnaBridge | 167:e84263d55307 | 14975 | #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 14976 | #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 14977 | #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 14978 | #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 14979 | #define RTC_ALRMAR_MSK2_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 14980 | #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 14981 | #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk |
| AnnaBridge | 167:e84263d55307 | 14982 | #define RTC_ALRMAR_MNT_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 14983 | #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 167:e84263d55307 | 14984 | #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk |
| AnnaBridge | 167:e84263d55307 | 14985 | #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 14986 | #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 14987 | #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 14988 | #define RTC_ALRMAR_MNU_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 14989 | #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 14990 | #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk |
| AnnaBridge | 167:e84263d55307 | 14991 | #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 14992 | #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 14993 | #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 14994 | #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 14995 | #define RTC_ALRMAR_MSK1_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 14996 | #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 14997 | #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk |
| AnnaBridge | 167:e84263d55307 | 14998 | #define RTC_ALRMAR_ST_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 14999 | #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 15000 | #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk |
| AnnaBridge | 167:e84263d55307 | 15001 | #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15002 | #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15003 | #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15004 | #define RTC_ALRMAR_SU_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15005 | #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 15006 | #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk |
| AnnaBridge | 167:e84263d55307 | 15007 | #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15008 | #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15009 | #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15010 | #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ |
| mbed_official | 19:112740acecfa | 15011 | |
| mbed_official | 19:112740acecfa | 15012 | /******************** Bits definition for RTC_ALRMBR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15013 | #define RTC_ALRMBR_MSK4_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 15014 | #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 15015 | #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk |
| AnnaBridge | 167:e84263d55307 | 15016 | #define RTC_ALRMBR_WDSEL_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 15017 | #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 15018 | #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 15019 | #define RTC_ALRMBR_DT_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 15020 | #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 167:e84263d55307 | 15021 | #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk |
| AnnaBridge | 167:e84263d55307 | 15022 | #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 15023 | #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 15024 | #define RTC_ALRMBR_DU_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 15025 | #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 15026 | #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk |
| AnnaBridge | 167:e84263d55307 | 15027 | #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 15028 | #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 15029 | #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 15030 | #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 15031 | #define RTC_ALRMBR_MSK3_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 15032 | #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 15033 | #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk |
| AnnaBridge | 167:e84263d55307 | 15034 | #define RTC_ALRMBR_PM_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 15035 | #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 15036 | #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk |
| AnnaBridge | 167:e84263d55307 | 15037 | #define RTC_ALRMBR_HT_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 15038 | #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 15039 | #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk |
| AnnaBridge | 167:e84263d55307 | 15040 | #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 15041 | #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 15042 | #define RTC_ALRMBR_HU_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 15043 | #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 15044 | #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk |
| AnnaBridge | 167:e84263d55307 | 15045 | #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 15046 | #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 15047 | #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 15048 | #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 15049 | #define RTC_ALRMBR_MSK2_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 15050 | #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 15051 | #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk |
| AnnaBridge | 167:e84263d55307 | 15052 | #define RTC_ALRMBR_MNT_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 15053 | #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 167:e84263d55307 | 15054 | #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk |
| AnnaBridge | 167:e84263d55307 | 15055 | #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 15056 | #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15057 | #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 15058 | #define RTC_ALRMBR_MNU_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15059 | #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 15060 | #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk |
| AnnaBridge | 167:e84263d55307 | 15061 | #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15062 | #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15063 | #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15064 | #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15065 | #define RTC_ALRMBR_MSK1_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 15066 | #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 15067 | #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk |
| AnnaBridge | 167:e84263d55307 | 15068 | #define RTC_ALRMBR_ST_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15069 | #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 15070 | #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk |
| AnnaBridge | 167:e84263d55307 | 15071 | #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15072 | #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15073 | #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15074 | #define RTC_ALRMBR_SU_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15075 | #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 15076 | #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk |
| AnnaBridge | 167:e84263d55307 | 15077 | #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15078 | #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15079 | #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15080 | #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ |
| mbed_official | 19:112740acecfa | 15081 | |
| mbed_official | 19:112740acecfa | 15082 | /******************** Bits definition for RTC_WPR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15083 | #define RTC_WPR_KEY_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15084 | #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 15085 | #define RTC_WPR_KEY RTC_WPR_KEY_Msk |
| mbed_official | 19:112740acecfa | 15086 | |
| mbed_official | 19:112740acecfa | 15087 | /******************** Bits definition for RTC_SSR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15088 | #define RTC_SSR_SS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15089 | #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 15090 | #define RTC_SSR_SS RTC_SSR_SS_Msk |
| mbed_official | 19:112740acecfa | 15091 | |
| mbed_official | 19:112740acecfa | 15092 | /******************** Bits definition for RTC_SHIFTR register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15093 | #define RTC_SHIFTR_SUBFS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15094 | #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 167:e84263d55307 | 15095 | #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk |
| AnnaBridge | 167:e84263d55307 | 15096 | #define RTC_SHIFTR_ADD1S_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 15097 | #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 15098 | #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk |
| mbed_official | 19:112740acecfa | 15099 | |
| mbed_official | 19:112740acecfa | 15100 | /******************** Bits definition for RTC_TSTR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 15101 | #define RTC_TSTR_PM_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 15102 | #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 15103 | #define RTC_TSTR_PM RTC_TSTR_PM_Msk |
| AnnaBridge | 167:e84263d55307 | 15104 | #define RTC_TSTR_HT_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 15105 | #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 15106 | #define RTC_TSTR_HT RTC_TSTR_HT_Msk |
| AnnaBridge | 167:e84263d55307 | 15107 | #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 15108 | #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 15109 | #define RTC_TSTR_HU_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 15110 | #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 167:e84263d55307 | 15111 | #define RTC_TSTR_HU RTC_TSTR_HU_Msk |
| AnnaBridge | 167:e84263d55307 | 15112 | #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 15113 | #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 15114 | #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 15115 | #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 15116 | #define RTC_TSTR_MNT_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 15117 | #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 167:e84263d55307 | 15118 | #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk |
| AnnaBridge | 167:e84263d55307 | 15119 | #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 15120 | #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15121 | #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 15122 | #define RTC_TSTR_MNU_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15123 | #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 15124 | #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk |
| AnnaBridge | 167:e84263d55307 | 15125 | #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15126 | #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15127 | #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15128 | #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15129 | #define RTC_TSTR_ST_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15130 | #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 15131 | #define RTC_TSTR_ST RTC_TSTR_ST_Msk |
| AnnaBridge | 167:e84263d55307 | 15132 | #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15133 | #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15134 | #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15135 | #define RTC_TSTR_SU_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15136 | #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 15137 | #define RTC_TSTR_SU RTC_TSTR_SU_Msk |
| AnnaBridge | 167:e84263d55307 | 15138 | #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15139 | #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15140 | #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15141 | #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ |
| mbed_official | 19:112740acecfa | 15142 | |
| mbed_official | 19:112740acecfa | 15143 | /******************** Bits definition for RTC_TSDR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 15144 | #define RTC_TSDR_WDU_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 15145 | #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ |
| AnnaBridge | 167:e84263d55307 | 15146 | #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk |
| AnnaBridge | 167:e84263d55307 | 15147 | #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15148 | #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 15149 | #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 15150 | #define RTC_TSDR_MT_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 15151 | #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 15152 | #define RTC_TSDR_MT RTC_TSDR_MT_Msk |
| AnnaBridge | 167:e84263d55307 | 15153 | #define RTC_TSDR_MU_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15154 | #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 15155 | #define RTC_TSDR_MU RTC_TSDR_MU_Msk |
| AnnaBridge | 167:e84263d55307 | 15156 | #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15157 | #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15158 | #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15159 | #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15160 | #define RTC_TSDR_DT_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15161 | #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 15162 | #define RTC_TSDR_DT RTC_TSDR_DT_Msk |
| AnnaBridge | 167:e84263d55307 | 15163 | #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15164 | #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15165 | #define RTC_TSDR_DU_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15166 | #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 15167 | #define RTC_TSDR_DU RTC_TSDR_DU_Msk |
| AnnaBridge | 167:e84263d55307 | 15168 | #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15169 | #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15170 | #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15171 | #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ |
| mbed_official | 19:112740acecfa | 15172 | |
| mbed_official | 19:112740acecfa | 15173 | /******************** Bits definition for RTC_TSSSR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15174 | #define RTC_TSSSR_SS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15175 | #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 15176 | #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk |
| mbed_official | 19:112740acecfa | 15177 | |
| mbed_official | 19:112740acecfa | 15178 | /******************** Bits definition for RTC_CAL register *****************/ |
| AnnaBridge | 167:e84263d55307 | 15179 | #define RTC_CALR_CALP_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 15180 | #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 15181 | #define RTC_CALR_CALP RTC_CALR_CALP_Msk |
| AnnaBridge | 167:e84263d55307 | 15182 | #define RTC_CALR_CALW8_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 15183 | #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 15184 | #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk |
| AnnaBridge | 167:e84263d55307 | 15185 | #define RTC_CALR_CALW16_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 15186 | #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15187 | #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk |
| AnnaBridge | 167:e84263d55307 | 15188 | #define RTC_CALR_CALM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15189 | #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ |
| AnnaBridge | 167:e84263d55307 | 15190 | #define RTC_CALR_CALM RTC_CALR_CALM_Msk |
| AnnaBridge | 167:e84263d55307 | 15191 | #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15192 | #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15193 | #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15194 | #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15195 | #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15196 | #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15197 | #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15198 | #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 15199 | #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ |
| mbed_official | 19:112740acecfa | 15200 | |
| mbed_official | 19:112740acecfa | 15201 | /******************** Bits definition for RTC_TAFCR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15202 | #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 15203 | #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 15204 | #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk |
| AnnaBridge | 167:e84263d55307 | 15205 | #define RTC_TAFCR_TSINSEL_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 15206 | #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 15207 | #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 15208 | #define RTC_TAFCR_TAMP1INSEL_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 15209 | #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 15210 | #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk |
| AnnaBridge | 167:e84263d55307 | 15211 | #define RTC_TAFCR_TAMPPUDIS_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 15212 | #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 15213 | #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk |
| AnnaBridge | 167:e84263d55307 | 15214 | #define RTC_TAFCR_TAMPPRCH_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 15215 | #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ |
| AnnaBridge | 167:e84263d55307 | 15216 | #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk |
| AnnaBridge | 167:e84263d55307 | 15217 | #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15218 | #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 15219 | #define RTC_TAFCR_TAMPFLT_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 15220 | #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ |
| AnnaBridge | 167:e84263d55307 | 15221 | #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk |
| AnnaBridge | 167:e84263d55307 | 15222 | #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15223 | #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 15224 | #define RTC_TAFCR_TAMPFREQ_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15225 | #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 167:e84263d55307 | 15226 | #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk |
| AnnaBridge | 167:e84263d55307 | 15227 | #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15228 | #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15229 | #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15230 | #define RTC_TAFCR_TAMPTS_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 15231 | #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 15232 | #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk |
| AnnaBridge | 167:e84263d55307 | 15233 | #define RTC_TAFCR_TAMP2TRG_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15234 | #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15235 | #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk |
| AnnaBridge | 167:e84263d55307 | 15236 | #define RTC_TAFCR_TAMP2E_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 15237 | #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15238 | #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk |
| AnnaBridge | 167:e84263d55307 | 15239 | #define RTC_TAFCR_TAMPIE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 15240 | #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15241 | #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk |
| AnnaBridge | 167:e84263d55307 | 15242 | #define RTC_TAFCR_TAMP1TRG_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 15243 | #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15244 | #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk |
| AnnaBridge | 167:e84263d55307 | 15245 | #define RTC_TAFCR_TAMP1E_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15246 | #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15247 | #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk |
| AnnaBridge | 167:e84263d55307 | 15248 | |
| AnnaBridge | 167:e84263d55307 | 15249 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 15250 | #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL |
| mbed_official | 19:112740acecfa | 15251 | |
| mbed_official | 19:112740acecfa | 15252 | /******************** Bits definition for RTC_ALRMASSR register *************/ |
| AnnaBridge | 167:e84263d55307 | 15253 | #define RTC_ALRMASSR_MASKSS_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 15254 | #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 15255 | #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk |
| AnnaBridge | 167:e84263d55307 | 15256 | #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 15257 | #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 15258 | #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 15259 | #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 15260 | #define RTC_ALRMASSR_SS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15261 | #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 167:e84263d55307 | 15262 | #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk |
| mbed_official | 19:112740acecfa | 15263 | |
| mbed_official | 19:112740acecfa | 15264 | /******************** Bits definition for RTC_ALRMBSSR register *************/ |
| AnnaBridge | 167:e84263d55307 | 15265 | #define RTC_ALRMBSSR_MASKSS_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 15266 | #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 167:e84263d55307 | 15267 | #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk |
| AnnaBridge | 167:e84263d55307 | 15268 | #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 15269 | #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 15270 | #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 15271 | #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 15272 | #define RTC_ALRMBSSR_SS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15273 | #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 167:e84263d55307 | 15274 | #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk |
| mbed_official | 19:112740acecfa | 15275 | |
| mbed_official | 19:112740acecfa | 15276 | /******************** Bits definition for RTC_BKP0R register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15277 | #define RTC_BKP0R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15278 | #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15279 | #define RTC_BKP0R RTC_BKP0R_Msk |
| mbed_official | 19:112740acecfa | 15280 | |
| mbed_official | 19:112740acecfa | 15281 | /******************** Bits definition for RTC_BKP1R register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15282 | #define RTC_BKP1R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15283 | #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15284 | #define RTC_BKP1R RTC_BKP1R_Msk |
| mbed_official | 19:112740acecfa | 15285 | |
| mbed_official | 19:112740acecfa | 15286 | /******************** Bits definition for RTC_BKP2R register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15287 | #define RTC_BKP2R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15288 | #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15289 | #define RTC_BKP2R RTC_BKP2R_Msk |
| mbed_official | 19:112740acecfa | 15290 | |
| mbed_official | 19:112740acecfa | 15291 | /******************** Bits definition for RTC_BKP3R register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15292 | #define RTC_BKP3R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15293 | #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15294 | #define RTC_BKP3R RTC_BKP3R_Msk |
| mbed_official | 19:112740acecfa | 15295 | |
| mbed_official | 19:112740acecfa | 15296 | /******************** Bits definition for RTC_BKP4R register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15297 | #define RTC_BKP4R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15298 | #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15299 | #define RTC_BKP4R RTC_BKP4R_Msk |
| mbed_official | 19:112740acecfa | 15300 | |
| mbed_official | 19:112740acecfa | 15301 | /******************** Bits definition for RTC_BKP5R register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15302 | #define RTC_BKP5R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15303 | #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15304 | #define RTC_BKP5R RTC_BKP5R_Msk |
| mbed_official | 19:112740acecfa | 15305 | |
| mbed_official | 19:112740acecfa | 15306 | /******************** Bits definition for RTC_BKP6R register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15307 | #define RTC_BKP6R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15308 | #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15309 | #define RTC_BKP6R RTC_BKP6R_Msk |
| mbed_official | 19:112740acecfa | 15310 | |
| mbed_official | 19:112740acecfa | 15311 | /******************** Bits definition for RTC_BKP7R register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15312 | #define RTC_BKP7R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15313 | #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15314 | #define RTC_BKP7R RTC_BKP7R_Msk |
| mbed_official | 19:112740acecfa | 15315 | |
| mbed_official | 19:112740acecfa | 15316 | /******************** Bits definition for RTC_BKP8R register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15317 | #define RTC_BKP8R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15318 | #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15319 | #define RTC_BKP8R RTC_BKP8R_Msk |
| mbed_official | 19:112740acecfa | 15320 | |
| mbed_official | 19:112740acecfa | 15321 | /******************** Bits definition for RTC_BKP9R register ****************/ |
| AnnaBridge | 167:e84263d55307 | 15322 | #define RTC_BKP9R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15323 | #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15324 | #define RTC_BKP9R RTC_BKP9R_Msk |
| mbed_official | 19:112740acecfa | 15325 | |
| mbed_official | 19:112740acecfa | 15326 | /******************** Bits definition for RTC_BKP10R register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15327 | #define RTC_BKP10R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15328 | #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15329 | #define RTC_BKP10R RTC_BKP10R_Msk |
| mbed_official | 19:112740acecfa | 15330 | |
| mbed_official | 19:112740acecfa | 15331 | /******************** Bits definition for RTC_BKP11R register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15332 | #define RTC_BKP11R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15333 | #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15334 | #define RTC_BKP11R RTC_BKP11R_Msk |
| mbed_official | 19:112740acecfa | 15335 | |
| mbed_official | 19:112740acecfa | 15336 | /******************** Bits definition for RTC_BKP12R register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15337 | #define RTC_BKP12R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15338 | #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15339 | #define RTC_BKP12R RTC_BKP12R_Msk |
| mbed_official | 19:112740acecfa | 15340 | |
| mbed_official | 19:112740acecfa | 15341 | /******************** Bits definition for RTC_BKP13R register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15342 | #define RTC_BKP13R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15343 | #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15344 | #define RTC_BKP13R RTC_BKP13R_Msk |
| mbed_official | 19:112740acecfa | 15345 | |
| mbed_official | 19:112740acecfa | 15346 | /******************** Bits definition for RTC_BKP14R register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15347 | #define RTC_BKP14R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15348 | #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15349 | #define RTC_BKP14R RTC_BKP14R_Msk |
| mbed_official | 19:112740acecfa | 15350 | |
| mbed_official | 19:112740acecfa | 15351 | /******************** Bits definition for RTC_BKP15R register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15352 | #define RTC_BKP15R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15353 | #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15354 | #define RTC_BKP15R RTC_BKP15R_Msk |
| mbed_official | 19:112740acecfa | 15355 | |
| mbed_official | 19:112740acecfa | 15356 | /******************** Bits definition for RTC_BKP16R register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15357 | #define RTC_BKP16R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15358 | #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15359 | #define RTC_BKP16R RTC_BKP16R_Msk |
| mbed_official | 19:112740acecfa | 15360 | |
| mbed_official | 19:112740acecfa | 15361 | /******************** Bits definition for RTC_BKP17R register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15362 | #define RTC_BKP17R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15363 | #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15364 | #define RTC_BKP17R RTC_BKP17R_Msk |
| mbed_official | 19:112740acecfa | 15365 | |
| mbed_official | 19:112740acecfa | 15366 | /******************** Bits definition for RTC_BKP18R register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15367 | #define RTC_BKP18R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15368 | #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15369 | #define RTC_BKP18R RTC_BKP18R_Msk |
| mbed_official | 19:112740acecfa | 15370 | |
| mbed_official | 19:112740acecfa | 15371 | /******************** Bits definition for RTC_BKP19R register ***************/ |
| AnnaBridge | 167:e84263d55307 | 15372 | #define RTC_BKP19R_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15373 | #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15374 | #define RTC_BKP19R RTC_BKP19R_Msk |
| AnnaBridge | 167:e84263d55307 | 15375 | |
| AnnaBridge | 167:e84263d55307 | 15376 | /******************** Number of backup registers ******************************/ |
| AnnaBridge | 167:e84263d55307 | 15377 | #define RTC_BKP_NUMBER 0x000000014U |
| AnnaBridge | 167:e84263d55307 | 15378 | |
| mbed_official | 19:112740acecfa | 15379 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 15380 | /* */ |
| mbed_official | 19:112740acecfa | 15381 | /* Serial Audio Interface */ |
| mbed_official | 19:112740acecfa | 15382 | /* */ |
| mbed_official | 19:112740acecfa | 15383 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 15384 | /******************** Bit definition for SAI_GCR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15385 | #define SAI_GCR_SYNCIN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15386 | #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 15387 | #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ |
| AnnaBridge | 167:e84263d55307 | 15388 | #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15389 | #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15390 | |
| AnnaBridge | 167:e84263d55307 | 15391 | #define SAI_GCR_SYNCOUT_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15392 | #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 15393 | #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ |
| AnnaBridge | 167:e84263d55307 | 15394 | #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15395 | #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ |
| mbed_official | 19:112740acecfa | 15396 | |
| mbed_official | 19:112740acecfa | 15397 | /******************* Bit definition for SAI_xCR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15398 | #define SAI_xCR1_MODE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15399 | #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 15400 | #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */ |
| AnnaBridge | 167:e84263d55307 | 15401 | #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15402 | #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15403 | |
| AnnaBridge | 167:e84263d55307 | 15404 | #define SAI_xCR1_PRTCFG_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 15405 | #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 15406 | #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */ |
| AnnaBridge | 167:e84263d55307 | 15407 | #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15408 | #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15409 | |
| AnnaBridge | 167:e84263d55307 | 15410 | #define SAI_xCR1_DS_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 15411 | #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */ |
| AnnaBridge | 167:e84263d55307 | 15412 | #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */ |
| AnnaBridge | 167:e84263d55307 | 15413 | #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15414 | #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15415 | #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 15416 | |
| AnnaBridge | 167:e84263d55307 | 15417 | #define SAI_xCR1_LSBFIRST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15418 | #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15419 | #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */ |
| AnnaBridge | 167:e84263d55307 | 15420 | #define SAI_xCR1_CKSTR_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 15421 | #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15422 | #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */ |
| AnnaBridge | 167:e84263d55307 | 15423 | |
| AnnaBridge | 167:e84263d55307 | 15424 | #define SAI_xCR1_SYNCEN_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 15425 | #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 15426 | #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */ |
| AnnaBridge | 167:e84263d55307 | 15427 | #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15428 | #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15429 | |
| AnnaBridge | 167:e84263d55307 | 15430 | #define SAI_xCR1_MONO_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 15431 | #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 15432 | #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */ |
| AnnaBridge | 167:e84263d55307 | 15433 | #define SAI_xCR1_OUTDRIV_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 15434 | #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15435 | #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */ |
| AnnaBridge | 167:e84263d55307 | 15436 | #define SAI_xCR1_SAIEN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 15437 | #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 15438 | #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */ |
| AnnaBridge | 167:e84263d55307 | 15439 | #define SAI_xCR1_DMAEN_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 15440 | #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 15441 | #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */ |
| AnnaBridge | 167:e84263d55307 | 15442 | #define SAI_xCR1_NODIV_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 15443 | #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 15444 | #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */ |
| AnnaBridge | 167:e84263d55307 | 15445 | |
| AnnaBridge | 167:e84263d55307 | 15446 | #define SAI_xCR1_MCKDIV_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 15447 | #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 167:e84263d55307 | 15448 | #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */ |
| AnnaBridge | 167:e84263d55307 | 15449 | #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 15450 | #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 15451 | #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 15452 | #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */ |
| mbed_official | 19:112740acecfa | 15453 | |
| mbed_official | 19:112740acecfa | 15454 | /******************* Bit definition for SAI_xCR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15455 | #define SAI_xCR2_FTH_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15456 | #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 15457 | #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */ |
| AnnaBridge | 167:e84263d55307 | 15458 | #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15459 | #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15460 | #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15461 | |
| AnnaBridge | 167:e84263d55307 | 15462 | #define SAI_xCR2_FFLUSH_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 15463 | #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15464 | #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */ |
| AnnaBridge | 167:e84263d55307 | 15465 | #define SAI_xCR2_TRIS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15466 | #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15467 | #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */ |
| AnnaBridge | 167:e84263d55307 | 15468 | #define SAI_xCR2_MUTE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 15469 | #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15470 | #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */ |
| AnnaBridge | 167:e84263d55307 | 15471 | #define SAI_xCR2_MUTEVAL_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 15472 | #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15473 | #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */ |
| AnnaBridge | 167:e84263d55307 | 15474 | |
| AnnaBridge | 167:e84263d55307 | 15475 | #define SAI_xCR2_MUTECNT_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 15476 | #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */ |
| AnnaBridge | 167:e84263d55307 | 15477 | #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */ |
| AnnaBridge | 167:e84263d55307 | 15478 | #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 15479 | #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15480 | #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15481 | #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15482 | #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15483 | #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 15484 | |
| AnnaBridge | 167:e84263d55307 | 15485 | #define SAI_xCR2_CPL_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 15486 | #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15487 | #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */ |
| AnnaBridge | 167:e84263d55307 | 15488 | |
| AnnaBridge | 167:e84263d55307 | 15489 | #define SAI_xCR2_COMP_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 15490 | #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 15491 | #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */ |
| AnnaBridge | 167:e84263d55307 | 15492 | #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 15493 | #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */ |
| mbed_official | 19:112740acecfa | 15494 | |
| mbed_official | 19:112740acecfa | 15495 | /****************** Bit definition for SAI_xFRCR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15496 | #define SAI_xFRCR_FRL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15497 | #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 15498 | #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */ |
| AnnaBridge | 167:e84263d55307 | 15499 | #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15500 | #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15501 | #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15502 | #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15503 | #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15504 | #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15505 | #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15506 | #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 15507 | |
| AnnaBridge | 167:e84263d55307 | 15508 | #define SAI_xFRCR_FSALL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15509 | #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */ |
| AnnaBridge | 167:e84263d55307 | 15510 | #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */ |
| AnnaBridge | 167:e84263d55307 | 15511 | #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15512 | #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15513 | #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15514 | #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15515 | #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 15516 | #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15517 | #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 15518 | |
| AnnaBridge | 167:e84263d55307 | 15519 | #define SAI_xFRCR_FSDEF_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 15520 | #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 15521 | #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */ |
| AnnaBridge | 167:e84263d55307 | 15522 | #define SAI_xFRCR_FSPOL_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 15523 | #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 15524 | #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */ |
| AnnaBridge | 167:e84263d55307 | 15525 | #define SAI_xFRCR_FSOFF_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 15526 | #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 15527 | #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */ |
| <> | 144:ef7eb2e8f9f7 | 15528 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 15529 | #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL |
| mbed_official | 19:112740acecfa | 15530 | |
| mbed_official | 19:112740acecfa | 15531 | /****************** Bit definition for SAI_xSLOTR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15532 | #define SAI_xSLOTR_FBOFF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15533 | #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 167:e84263d55307 | 15534 | #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */ |
| AnnaBridge | 167:e84263d55307 | 15535 | #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15536 | #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15537 | #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15538 | #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15539 | #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15540 | |
| AnnaBridge | 167:e84263d55307 | 15541 | #define SAI_xSLOTR_SLOTSZ_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 15542 | #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 15543 | #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */ |
| AnnaBridge | 167:e84263d55307 | 15544 | #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15545 | #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 15546 | |
| AnnaBridge | 167:e84263d55307 | 15547 | #define SAI_xSLOTR_NBSLOT_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15548 | #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 15549 | #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */ |
| AnnaBridge | 167:e84263d55307 | 15550 | #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15551 | #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15552 | #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15553 | #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15554 | |
| AnnaBridge | 167:e84263d55307 | 15555 | #define SAI_xSLOTR_SLOTEN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 15556 | #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 15557 | #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */ |
| mbed_official | 19:112740acecfa | 15558 | |
| mbed_official | 19:112740acecfa | 15559 | /******************* Bit definition for SAI_xIMR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15560 | #define SAI_xIMR_OVRUDRIE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15561 | #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15562 | #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 15563 | #define SAI_xIMR_MUTEDETIE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 15564 | #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15565 | #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 15566 | #define SAI_xIMR_WCKCFGIE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 15567 | #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15568 | #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 15569 | #define SAI_xIMR_FREQIE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 15570 | #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15571 | #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 15572 | #define SAI_xIMR_CNRDYIE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15573 | #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15574 | #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 15575 | #define SAI_xIMR_AFSDETIE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 15576 | #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15577 | #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 15578 | #define SAI_xIMR_LFSDETIE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 15579 | #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15580 | #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */ |
| mbed_official | 19:112740acecfa | 15581 | |
| mbed_official | 19:112740acecfa | 15582 | /******************** Bit definition for SAI_xSR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15583 | #define SAI_xSR_OVRUDR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15584 | #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15585 | #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */ |
| AnnaBridge | 167:e84263d55307 | 15586 | #define SAI_xSR_MUTEDET_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 15587 | #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15588 | #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */ |
| AnnaBridge | 167:e84263d55307 | 15589 | #define SAI_xSR_WCKCFG_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 15590 | #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15591 | #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */ |
| AnnaBridge | 167:e84263d55307 | 15592 | #define SAI_xSR_FREQ_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 15593 | #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15594 | #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */ |
| AnnaBridge | 167:e84263d55307 | 15595 | #define SAI_xSR_CNRDY_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15596 | #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15597 | #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */ |
| AnnaBridge | 167:e84263d55307 | 15598 | #define SAI_xSR_AFSDET_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 15599 | #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15600 | #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */ |
| AnnaBridge | 167:e84263d55307 | 15601 | #define SAI_xSR_LFSDET_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 15602 | #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15603 | #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */ |
| AnnaBridge | 167:e84263d55307 | 15604 | |
| AnnaBridge | 167:e84263d55307 | 15605 | #define SAI_xSR_FLVL_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 15606 | #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 167:e84263d55307 | 15607 | #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */ |
| AnnaBridge | 167:e84263d55307 | 15608 | #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 15609 | #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 15610 | #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */ |
| mbed_official | 19:112740acecfa | 15611 | |
| mbed_official | 19:112740acecfa | 15612 | /****************** Bit definition for SAI_xCLRFR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15613 | #define SAI_xCLRFR_COVRUDR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15614 | #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15615 | #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */ |
| AnnaBridge | 167:e84263d55307 | 15616 | #define SAI_xCLRFR_CMUTEDET_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 15617 | #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15618 | #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */ |
| AnnaBridge | 167:e84263d55307 | 15619 | #define SAI_xCLRFR_CWCKCFG_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 15620 | #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15621 | #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */ |
| AnnaBridge | 167:e84263d55307 | 15622 | #define SAI_xCLRFR_CFREQ_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 15623 | #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15624 | #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */ |
| AnnaBridge | 167:e84263d55307 | 15625 | #define SAI_xCLRFR_CCNRDY_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15626 | #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15627 | #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */ |
| AnnaBridge | 167:e84263d55307 | 15628 | #define SAI_xCLRFR_CAFSDET_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 15629 | #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15630 | #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */ |
| AnnaBridge | 167:e84263d55307 | 15631 | #define SAI_xCLRFR_CLFSDET_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 15632 | #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15633 | #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */ |
| mbed_official | 19:112740acecfa | 15634 | |
| mbed_official | 19:112740acecfa | 15635 | /****************** Bit definition for SAI_xDR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15636 | #define SAI_xDR_DATA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15637 | #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15638 | #define SAI_xDR_DATA SAI_xDR_DATA_Msk |
| mbed_official | 19:112740acecfa | 15639 | |
| mbed_official | 19:112740acecfa | 15640 | |
| mbed_official | 19:112740acecfa | 15641 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 15642 | /* */ |
| mbed_official | 19:112740acecfa | 15643 | /* SD host Interface */ |
| mbed_official | 19:112740acecfa | 15644 | /* */ |
| mbed_official | 19:112740acecfa | 15645 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 15646 | /****************** Bit definition for SDIO_POWER register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15647 | #define SDIO_POWER_PWRCTRL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15648 | #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 15649 | #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */ |
| AnnaBridge | 167:e84263d55307 | 15650 | #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */ |
| AnnaBridge | 167:e84263d55307 | 15651 | #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */ |
| mbed_official | 19:112740acecfa | 15652 | |
| mbed_official | 19:112740acecfa | 15653 | /****************** Bit definition for SDIO_CLKCR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15654 | #define SDIO_CLKCR_CLKDIV_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15655 | #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 15656 | #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */ |
| AnnaBridge | 167:e84263d55307 | 15657 | #define SDIO_CLKCR_CLKEN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15658 | #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15659 | #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */ |
| AnnaBridge | 167:e84263d55307 | 15660 | #define SDIO_CLKCR_PWRSAV_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 15661 | #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15662 | #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */ |
| AnnaBridge | 167:e84263d55307 | 15663 | #define SDIO_CLKCR_BYPASS_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 15664 | #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15665 | #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */ |
| AnnaBridge | 167:e84263d55307 | 15666 | |
| AnnaBridge | 167:e84263d55307 | 15667 | #define SDIO_CLKCR_WIDBUS_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 15668 | #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ |
| AnnaBridge | 167:e84263d55307 | 15669 | #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
| AnnaBridge | 167:e84263d55307 | 15670 | #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */ |
| AnnaBridge | 167:e84263d55307 | 15671 | #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */ |
| AnnaBridge | 167:e84263d55307 | 15672 | |
| AnnaBridge | 167:e84263d55307 | 15673 | #define SDIO_CLKCR_NEGEDGE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 15674 | #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15675 | #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */ |
| AnnaBridge | 167:e84263d55307 | 15676 | #define SDIO_CLKCR_HWFC_EN_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 15677 | #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 15678 | #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */ |
| mbed_official | 19:112740acecfa | 15679 | |
| mbed_official | 19:112740acecfa | 15680 | /******************* Bit definition for SDIO_ARG register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15681 | #define SDIO_ARG_CMDARG_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15682 | #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15683 | #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */ |
| mbed_official | 19:112740acecfa | 15684 | |
| mbed_official | 19:112740acecfa | 15685 | /******************* Bit definition for SDIO_CMD register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15686 | #define SDIO_CMD_CMDINDEX_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15687 | #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 167:e84263d55307 | 15688 | #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */ |
| AnnaBridge | 167:e84263d55307 | 15689 | |
| AnnaBridge | 167:e84263d55307 | 15690 | #define SDIO_CMD_WAITRESP_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 15691 | #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 15692 | #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */ |
| AnnaBridge | 167:e84263d55307 | 15693 | #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 15694 | #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */ |
| AnnaBridge | 167:e84263d55307 | 15695 | |
| AnnaBridge | 167:e84263d55307 | 15696 | #define SDIO_CMD_WAITINT_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15697 | #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15698 | #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */ |
| AnnaBridge | 167:e84263d55307 | 15699 | #define SDIO_CMD_WAITPEND_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 15700 | #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15701 | #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
| AnnaBridge | 167:e84263d55307 | 15702 | #define SDIO_CMD_CPSMEN_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 15703 | #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15704 | #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */ |
| AnnaBridge | 167:e84263d55307 | 15705 | #define SDIO_CMD_SDIOSUSPEND_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 15706 | #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15707 | #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */ |
| mbed_official | 19:112740acecfa | 15708 | |
| mbed_official | 19:112740acecfa | 15709 | /***************** Bit definition for SDIO_RESPCMD register *****************/ |
| AnnaBridge | 167:e84263d55307 | 15710 | #define SDIO_RESPCMD_RESPCMD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15711 | #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 167:e84263d55307 | 15712 | #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */ |
| mbed_official | 19:112740acecfa | 15713 | |
| mbed_official | 19:112740acecfa | 15714 | /****************** Bit definition for SDIO_RESP0 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15715 | #define SDIO_RESP0_CARDSTATUS0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15716 | #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15717 | #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */ |
| mbed_official | 19:112740acecfa | 15718 | |
| mbed_official | 19:112740acecfa | 15719 | /****************** Bit definition for SDIO_RESP1 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15720 | #define SDIO_RESP1_CARDSTATUS1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15721 | #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15722 | #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */ |
| mbed_official | 19:112740acecfa | 15723 | |
| mbed_official | 19:112740acecfa | 15724 | /****************** Bit definition for SDIO_RESP2 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15725 | #define SDIO_RESP2_CARDSTATUS2_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15726 | #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15727 | #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */ |
| mbed_official | 19:112740acecfa | 15728 | |
| mbed_official | 19:112740acecfa | 15729 | /****************** Bit definition for SDIO_RESP3 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15730 | #define SDIO_RESP3_CARDSTATUS3_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15731 | #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15732 | #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */ |
| mbed_official | 19:112740acecfa | 15733 | |
| mbed_official | 19:112740acecfa | 15734 | /****************** Bit definition for SDIO_RESP4 register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15735 | #define SDIO_RESP4_CARDSTATUS4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15736 | #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15737 | #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */ |
| mbed_official | 19:112740acecfa | 15738 | |
| mbed_official | 19:112740acecfa | 15739 | /****************** Bit definition for SDIO_DTIMER register *****************/ |
| AnnaBridge | 167:e84263d55307 | 15740 | #define SDIO_DTIMER_DATATIME_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15741 | #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15742 | #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */ |
| mbed_official | 19:112740acecfa | 15743 | |
| mbed_official | 19:112740acecfa | 15744 | /****************** Bit definition for SDIO_DLEN register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15745 | #define SDIO_DLEN_DATALENGTH_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15746 | #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15747 | #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */ |
| mbed_official | 19:112740acecfa | 15748 | |
| mbed_official | 19:112740acecfa | 15749 | /****************** Bit definition for SDIO_DCTRL register ******************/ |
| AnnaBridge | 167:e84263d55307 | 15750 | #define SDIO_DCTRL_DTEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15751 | #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15752 | #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */ |
| AnnaBridge | 167:e84263d55307 | 15753 | #define SDIO_DCTRL_DTDIR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 15754 | #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15755 | #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */ |
| AnnaBridge | 167:e84263d55307 | 15756 | #define SDIO_DCTRL_DTMODE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 15757 | #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15758 | #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */ |
| AnnaBridge | 167:e84263d55307 | 15759 | #define SDIO_DCTRL_DMAEN_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 15760 | #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15761 | #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */ |
| AnnaBridge | 167:e84263d55307 | 15762 | |
| AnnaBridge | 167:e84263d55307 | 15763 | #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15764 | #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 15765 | #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */ |
| AnnaBridge | 167:e84263d55307 | 15766 | #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 15767 | #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 15768 | #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 15769 | #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */ |
| AnnaBridge | 167:e84263d55307 | 15770 | |
| AnnaBridge | 167:e84263d55307 | 15771 | #define SDIO_DCTRL_RWSTART_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15772 | #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15773 | #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */ |
| AnnaBridge | 167:e84263d55307 | 15774 | #define SDIO_DCTRL_RWSTOP_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 15775 | #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 15776 | #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */ |
| AnnaBridge | 167:e84263d55307 | 15777 | #define SDIO_DCTRL_RWMOD_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 15778 | #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15779 | #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */ |
| AnnaBridge | 167:e84263d55307 | 15780 | #define SDIO_DCTRL_SDIOEN_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 15781 | #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15782 | #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */ |
| mbed_official | 19:112740acecfa | 15783 | |
| mbed_official | 19:112740acecfa | 15784 | /****************** Bit definition for SDIO_DCOUNT register *****************/ |
| AnnaBridge | 167:e84263d55307 | 15785 | #define SDIO_DCOUNT_DATACOUNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15786 | #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15787 | #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */ |
| mbed_official | 19:112740acecfa | 15788 | |
| mbed_official | 19:112740acecfa | 15789 | /****************** Bit definition for SDIO_STA register ********************/ |
| AnnaBridge | 167:e84263d55307 | 15790 | #define SDIO_STA_CCRCFAIL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15791 | #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15792 | #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */ |
| AnnaBridge | 167:e84263d55307 | 15793 | #define SDIO_STA_DCRCFAIL_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 15794 | #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15795 | #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */ |
| AnnaBridge | 167:e84263d55307 | 15796 | #define SDIO_STA_CTIMEOUT_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 15797 | #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15798 | #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */ |
| AnnaBridge | 167:e84263d55307 | 15799 | #define SDIO_STA_DTIMEOUT_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 15800 | #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15801 | #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */ |
| AnnaBridge | 167:e84263d55307 | 15802 | #define SDIO_STA_TXUNDERR_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15803 | #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15804 | #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */ |
| AnnaBridge | 167:e84263d55307 | 15805 | #define SDIO_STA_RXOVERR_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 15806 | #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15807 | #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */ |
| AnnaBridge | 167:e84263d55307 | 15808 | #define SDIO_STA_CMDREND_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 15809 | #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15810 | #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */ |
| AnnaBridge | 167:e84263d55307 | 15811 | #define SDIO_STA_CMDSENT_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 15812 | #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 15813 | #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */ |
| AnnaBridge | 167:e84263d55307 | 15814 | #define SDIO_STA_DATAEND_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15815 | #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15816 | #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */ |
| AnnaBridge | 167:e84263d55307 | 15817 | #define SDIO_STA_DBCKEND_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 15818 | #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15819 | #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */ |
| AnnaBridge | 167:e84263d55307 | 15820 | #define SDIO_STA_CMDACT_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 15821 | #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15822 | #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */ |
| AnnaBridge | 167:e84263d55307 | 15823 | #define SDIO_STA_TXACT_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 15824 | #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 15825 | #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */ |
| AnnaBridge | 167:e84263d55307 | 15826 | #define SDIO_STA_RXACT_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 15827 | #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15828 | #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */ |
| AnnaBridge | 167:e84263d55307 | 15829 | #define SDIO_STA_TXFIFOHE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 15830 | #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 15831 | #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
| AnnaBridge | 167:e84263d55307 | 15832 | #define SDIO_STA_RXFIFOHF_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 15833 | #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 15834 | #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
| AnnaBridge | 167:e84263d55307 | 15835 | #define SDIO_STA_TXFIFOF_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 15836 | #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 15837 | #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */ |
| AnnaBridge | 167:e84263d55307 | 15838 | #define SDIO_STA_RXFIFOF_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 15839 | #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 15840 | #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */ |
| AnnaBridge | 167:e84263d55307 | 15841 | #define SDIO_STA_TXFIFOE_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 15842 | #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 15843 | #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */ |
| AnnaBridge | 167:e84263d55307 | 15844 | #define SDIO_STA_RXFIFOE_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 15845 | #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 15846 | #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */ |
| AnnaBridge | 167:e84263d55307 | 15847 | #define SDIO_STA_TXDAVL_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 15848 | #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 15849 | #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */ |
| AnnaBridge | 167:e84263d55307 | 15850 | #define SDIO_STA_RXDAVL_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 15851 | #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 15852 | #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */ |
| AnnaBridge | 167:e84263d55307 | 15853 | #define SDIO_STA_SDIOIT_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 15854 | #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 15855 | #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */ |
| mbed_official | 19:112740acecfa | 15856 | |
| mbed_official | 19:112740acecfa | 15857 | /******************* Bit definition for SDIO_ICR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15858 | #define SDIO_ICR_CCRCFAILC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15859 | #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15860 | #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */ |
| AnnaBridge | 167:e84263d55307 | 15861 | #define SDIO_ICR_DCRCFAILC_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 15862 | #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15863 | #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */ |
| AnnaBridge | 167:e84263d55307 | 15864 | #define SDIO_ICR_CTIMEOUTC_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 15865 | #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15866 | #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */ |
| AnnaBridge | 167:e84263d55307 | 15867 | #define SDIO_ICR_DTIMEOUTC_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 15868 | #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15869 | #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */ |
| AnnaBridge | 167:e84263d55307 | 15870 | #define SDIO_ICR_TXUNDERRC_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15871 | #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15872 | #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */ |
| AnnaBridge | 167:e84263d55307 | 15873 | #define SDIO_ICR_RXOVERRC_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 15874 | #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15875 | #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */ |
| AnnaBridge | 167:e84263d55307 | 15876 | #define SDIO_ICR_CMDRENDC_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 15877 | #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15878 | #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */ |
| AnnaBridge | 167:e84263d55307 | 15879 | #define SDIO_ICR_CMDSENTC_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 15880 | #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 15881 | #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */ |
| AnnaBridge | 167:e84263d55307 | 15882 | #define SDIO_ICR_DATAENDC_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15883 | #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15884 | #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */ |
| AnnaBridge | 167:e84263d55307 | 15885 | #define SDIO_ICR_DBCKENDC_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 15886 | #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15887 | #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */ |
| AnnaBridge | 167:e84263d55307 | 15888 | #define SDIO_ICR_SDIOITC_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 15889 | #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 15890 | #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */ |
| mbed_official | 19:112740acecfa | 15891 | |
| mbed_official | 19:112740acecfa | 15892 | /****************** Bit definition for SDIO_MASK register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15893 | #define SDIO_MASK_CCRCFAILIE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15894 | #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15895 | #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15896 | #define SDIO_MASK_DCRCFAILIE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 15897 | #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15898 | #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15899 | #define SDIO_MASK_CTIMEOUTIE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 15900 | #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15901 | #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15902 | #define SDIO_MASK_DTIMEOUTIE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 15903 | #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15904 | #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15905 | #define SDIO_MASK_TXUNDERRIE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 15906 | #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15907 | #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15908 | #define SDIO_MASK_RXOVERRIE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 15909 | #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15910 | #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15911 | #define SDIO_MASK_CMDRENDIE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 15912 | #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15913 | #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15914 | #define SDIO_MASK_CMDSENTIE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 15915 | #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 15916 | #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15917 | #define SDIO_MASK_DATAENDIE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 15918 | #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 15919 | #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15920 | #define SDIO_MASK_DBCKENDIE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 15921 | #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 15922 | #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15923 | #define SDIO_MASK_CMDACTIE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 15924 | #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 15925 | #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15926 | #define SDIO_MASK_TXACTIE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 15927 | #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 15928 | #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15929 | #define SDIO_MASK_RXACTIE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 15930 | #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 15931 | #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */ |
| AnnaBridge | 167:e84263d55307 | 15932 | #define SDIO_MASK_TXFIFOHEIE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 15933 | #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 15934 | #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15935 | #define SDIO_MASK_RXFIFOHFIE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 15936 | #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 15937 | #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15938 | #define SDIO_MASK_TXFIFOFIE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 15939 | #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 15940 | #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15941 | #define SDIO_MASK_RXFIFOFIE_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 15942 | #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 15943 | #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15944 | #define SDIO_MASK_TXFIFOEIE_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 15945 | #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 15946 | #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15947 | #define SDIO_MASK_RXFIFOEIE_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 15948 | #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 15949 | #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15950 | #define SDIO_MASK_TXDAVLIE_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 15951 | #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 15952 | #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15953 | #define SDIO_MASK_RXDAVLIE_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 15954 | #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 15955 | #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 15956 | #define SDIO_MASK_SDIOITIE_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 15957 | #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 15958 | #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */ |
| mbed_official | 19:112740acecfa | 15959 | |
| mbed_official | 19:112740acecfa | 15960 | /***************** Bit definition for SDIO_FIFOCNT register *****************/ |
| AnnaBridge | 167:e84263d55307 | 15961 | #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15962 | #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15963 | #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */ |
| mbed_official | 19:112740acecfa | 15964 | |
| mbed_official | 19:112740acecfa | 15965 | /****************** Bit definition for SDIO_FIFO register *******************/ |
| AnnaBridge | 167:e84263d55307 | 15966 | #define SDIO_FIFO_FIFODATA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15967 | #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 15968 | #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */ |
| mbed_official | 19:112740acecfa | 15969 | |
| mbed_official | 19:112740acecfa | 15970 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 15971 | /* */ |
| mbed_official | 19:112740acecfa | 15972 | /* Serial Peripheral Interface */ |
| mbed_official | 19:112740acecfa | 15973 | /* */ |
| mbed_official | 19:112740acecfa | 15974 | /******************************************************************************/ |
| AnnaBridge | 167:e84263d55307 | 15975 | #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */ |
| AnnaBridge | 167:e84263d55307 | 15976 | |
| mbed_official | 19:112740acecfa | 15977 | /******************* Bit definition for SPI_CR1 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 15978 | #define SPI_CR1_CPHA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 15979 | #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 15980 | #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ |
| AnnaBridge | 167:e84263d55307 | 15981 | #define SPI_CR1_CPOL_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 15982 | #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 15983 | #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ |
| AnnaBridge | 167:e84263d55307 | 15984 | #define SPI_CR1_MSTR_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 15985 | #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 15986 | #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ |
| AnnaBridge | 167:e84263d55307 | 15987 | |
| AnnaBridge | 167:e84263d55307 | 15988 | #define SPI_CR1_BR_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 15989 | #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 167:e84263d55307 | 15990 | #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ |
| AnnaBridge | 167:e84263d55307 | 15991 | #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 15992 | #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 15993 | #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 15994 | |
| AnnaBridge | 167:e84263d55307 | 15995 | #define SPI_CR1_SPE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 15996 | #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 15997 | #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ |
| AnnaBridge | 167:e84263d55307 | 15998 | #define SPI_CR1_LSBFIRST_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 15999 | #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16000 | #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ |
| AnnaBridge | 167:e84263d55307 | 16001 | #define SPI_CR1_SSI_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16002 | #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 16003 | #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ |
| AnnaBridge | 167:e84263d55307 | 16004 | #define SPI_CR1_SSM_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 16005 | #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 16006 | #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ |
| AnnaBridge | 167:e84263d55307 | 16007 | #define SPI_CR1_RXONLY_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16008 | #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 16009 | #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ |
| AnnaBridge | 167:e84263d55307 | 16010 | #define SPI_CR1_DFF_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 16011 | #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 16012 | #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */ |
| AnnaBridge | 167:e84263d55307 | 16013 | #define SPI_CR1_CRCNEXT_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16014 | #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 16015 | #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ |
| AnnaBridge | 167:e84263d55307 | 16016 | #define SPI_CR1_CRCEN_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 16017 | #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 16018 | #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ |
| AnnaBridge | 167:e84263d55307 | 16019 | #define SPI_CR1_BIDIOE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 16020 | #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 16021 | #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ |
| AnnaBridge | 167:e84263d55307 | 16022 | #define SPI_CR1_BIDIMODE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 16023 | #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 16024 | #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ |
| mbed_official | 19:112740acecfa | 16025 | |
| mbed_official | 19:112740acecfa | 16026 | /******************* Bit definition for SPI_CR2 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16027 | #define SPI_CR2_RXDMAEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16028 | #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16029 | #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */ |
| AnnaBridge | 167:e84263d55307 | 16030 | #define SPI_CR2_TXDMAEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 16031 | #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 16032 | #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */ |
| AnnaBridge | 167:e84263d55307 | 16033 | #define SPI_CR2_SSOE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16034 | #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16035 | #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */ |
| AnnaBridge | 167:e84263d55307 | 16036 | #define SPI_CR2_FRF_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16037 | #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 16038 | #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */ |
| AnnaBridge | 167:e84263d55307 | 16039 | #define SPI_CR2_ERRIE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 16040 | #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 16041 | #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 16042 | #define SPI_CR2_RXNEIE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 16043 | #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 16044 | #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 16045 | #define SPI_CR2_TXEIE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16046 | #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16047 | #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */ |
| mbed_official | 19:112740acecfa | 16048 | |
| mbed_official | 19:112740acecfa | 16049 | /******************** Bit definition for SPI_SR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16050 | #define SPI_SR_RXNE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16051 | #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16052 | #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */ |
| AnnaBridge | 167:e84263d55307 | 16053 | #define SPI_SR_TXE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 16054 | #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 16055 | #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */ |
| AnnaBridge | 167:e84263d55307 | 16056 | #define SPI_SR_CHSIDE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16057 | #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16058 | #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */ |
| AnnaBridge | 167:e84263d55307 | 16059 | #define SPI_SR_UDR_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 16060 | #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 16061 | #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */ |
| AnnaBridge | 167:e84263d55307 | 16062 | #define SPI_SR_CRCERR_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16063 | #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 16064 | #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */ |
| AnnaBridge | 167:e84263d55307 | 16065 | #define SPI_SR_MODF_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 16066 | #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 16067 | #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */ |
| AnnaBridge | 167:e84263d55307 | 16068 | #define SPI_SR_OVR_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 16069 | #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 16070 | #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */ |
| AnnaBridge | 167:e84263d55307 | 16071 | #define SPI_SR_BSY_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16072 | #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16073 | #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */ |
| AnnaBridge | 167:e84263d55307 | 16074 | #define SPI_SR_FRE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16075 | #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 16076 | #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */ |
| mbed_official | 19:112740acecfa | 16077 | |
| mbed_official | 19:112740acecfa | 16078 | /******************** Bit definition for SPI_DR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16079 | #define SPI_DR_DR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16080 | #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 16081 | #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ |
| mbed_official | 19:112740acecfa | 16082 | |
| mbed_official | 19:112740acecfa | 16083 | /******************* Bit definition for SPI_CRCPR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 16084 | #define SPI_CRCPR_CRCPOLY_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16085 | #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 16086 | #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ |
| mbed_official | 19:112740acecfa | 16087 | |
| mbed_official | 19:112740acecfa | 16088 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 16089 | #define SPI_RXCRCR_RXCRC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16090 | #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 16091 | #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ |
| mbed_official | 19:112740acecfa | 16092 | |
| mbed_official | 19:112740acecfa | 16093 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 16094 | #define SPI_TXCRCR_TXCRC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16095 | #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 16096 | #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ |
| mbed_official | 19:112740acecfa | 16097 | |
| mbed_official | 19:112740acecfa | 16098 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 16099 | #define SPI_I2SCFGR_CHLEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16100 | #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16101 | #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ |
| AnnaBridge | 167:e84263d55307 | 16102 | |
| AnnaBridge | 167:e84263d55307 | 16103 | #define SPI_I2SCFGR_DATLEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 16104 | #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 167:e84263d55307 | 16105 | #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ |
| AnnaBridge | 167:e84263d55307 | 16106 | #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 16107 | #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16108 | |
| AnnaBridge | 167:e84263d55307 | 16109 | #define SPI_I2SCFGR_CKPOL_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 16110 | #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 16111 | #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ |
| AnnaBridge | 167:e84263d55307 | 16112 | |
| AnnaBridge | 167:e84263d55307 | 16113 | #define SPI_I2SCFGR_I2SSTD_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16114 | #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 16115 | #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ |
| AnnaBridge | 167:e84263d55307 | 16116 | #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 16117 | #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 16118 | |
| AnnaBridge | 167:e84263d55307 | 16119 | #define SPI_I2SCFGR_PCMSYNC_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16120 | #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16121 | #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ |
| AnnaBridge | 167:e84263d55307 | 16122 | |
| AnnaBridge | 167:e84263d55307 | 16123 | #define SPI_I2SCFGR_I2SCFG_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16124 | #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 16125 | #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ |
| AnnaBridge | 167:e84263d55307 | 16126 | #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 16127 | #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 16128 | |
| AnnaBridge | 167:e84263d55307 | 16129 | #define SPI_I2SCFGR_I2SE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16130 | #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 16131 | #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ |
| AnnaBridge | 167:e84263d55307 | 16132 | #define SPI_I2SCFGR_I2SMOD_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 16133 | #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 16134 | #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ |
| AnnaBridge | 167:e84263d55307 | 16135 | #define SPI_I2SCFGR_ASTRTEN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16136 | #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 16137 | #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */ |
| mbed_official | 19:112740acecfa | 16138 | |
| mbed_official | 19:112740acecfa | 16139 | /****************** Bit definition for SPI_I2SPR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16140 | #define SPI_I2SPR_I2SDIV_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16141 | #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 16142 | #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ |
| AnnaBridge | 167:e84263d55307 | 16143 | #define SPI_I2SPR_ODD_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16144 | #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 16145 | #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ |
| AnnaBridge | 167:e84263d55307 | 16146 | #define SPI_I2SPR_MCKOE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 16147 | #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 16148 | #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ |
| mbed_official | 19:112740acecfa | 16149 | |
| mbed_official | 19:112740acecfa | 16150 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 16151 | /* */ |
| mbed_official | 19:112740acecfa | 16152 | /* SYSCFG */ |
| mbed_official | 19:112740acecfa | 16153 | /* */ |
| mbed_official | 19:112740acecfa | 16154 | /******************************************************************************/ |
| AnnaBridge | 167:e84263d55307 | 16155 | /****************** Bit definition for SYSCFG_MEMRMP register ***************/ |
| AnnaBridge | 167:e84263d55307 | 16156 | #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16157 | #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 16158 | #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ |
| AnnaBridge | 167:e84263d55307 | 16159 | #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16160 | #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 16161 | #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16162 | #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16163 | #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 16164 | #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */ |
| AnnaBridge | 167:e84263d55307 | 16165 | #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16166 | #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 16167 | #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */ |
| AnnaBridge | 167:e84263d55307 | 16168 | #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 16169 | /* Legacy Defines */ |
| AnnaBridge | 167:e84263d55307 | 16170 | #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC |
| mbed_official | 19:112740acecfa | 16171 | /****************** Bit definition for SYSCFG_PMC register ******************/ |
| AnnaBridge | 167:e84263d55307 | 16172 | #define SYSCFG_PMC_ADCxDC2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 16173 | #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 167:e84263d55307 | 16174 | #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */ |
| AnnaBridge | 167:e84263d55307 | 16175 | #define SYSCFG_PMC_ADC1DC2_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 16176 | #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 16177 | #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */ |
| AnnaBridge | 167:e84263d55307 | 16178 | #define SYSCFG_PMC_ADC2DC2_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 16179 | #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 16180 | #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */ |
| AnnaBridge | 167:e84263d55307 | 16181 | #define SYSCFG_PMC_ADC3DC2_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 16182 | #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 16183 | #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */ |
| AnnaBridge | 167:e84263d55307 | 16184 | #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 16185 | #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 16186 | #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */ |
| mbed_official | 19:112740acecfa | 16187 | |
| mbed_official | 19:112740acecfa | 16188 | /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 16189 | #define SYSCFG_EXTICR1_EXTI0_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16190 | #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 16191 | #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16192 | #define SYSCFG_EXTICR1_EXTI1_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16193 | #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 16194 | #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16195 | #define SYSCFG_EXTICR1_EXTI2_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16196 | #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 16197 | #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16198 | #define SYSCFG_EXTICR1_EXTI3_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16199 | #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 167:e84263d55307 | 16200 | #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16201 | /** |
| mbed_official | 19:112740acecfa | 16202 | * @brief EXTI0 configuration |
| AnnaBridge | 167:e84263d55307 | 16203 | */ |
| AnnaBridge | 167:e84263d55307 | 16204 | #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16205 | #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16206 | #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16207 | #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16208 | #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16209 | #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16210 | #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16211 | #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16212 | #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16213 | #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16214 | #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */ |
| AnnaBridge | 167:e84263d55307 | 16215 | |
| AnnaBridge | 167:e84263d55307 | 16216 | /** |
| mbed_official | 19:112740acecfa | 16217 | * @brief EXTI1 configuration |
| AnnaBridge | 167:e84263d55307 | 16218 | */ |
| AnnaBridge | 167:e84263d55307 | 16219 | #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16220 | #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16221 | #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16222 | #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16223 | #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16224 | #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16225 | #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16226 | #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16227 | #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16228 | #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16229 | #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */ |
| AnnaBridge | 167:e84263d55307 | 16230 | |
| AnnaBridge | 167:e84263d55307 | 16231 | /** |
| mbed_official | 19:112740acecfa | 16232 | * @brief EXTI2 configuration |
| AnnaBridge | 167:e84263d55307 | 16233 | */ |
| AnnaBridge | 167:e84263d55307 | 16234 | #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16235 | #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16236 | #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16237 | #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16238 | #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16239 | #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16240 | #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16241 | #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16242 | #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16243 | #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16244 | #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */ |
| AnnaBridge | 167:e84263d55307 | 16245 | |
| AnnaBridge | 167:e84263d55307 | 16246 | /** |
| mbed_official | 19:112740acecfa | 16247 | * @brief EXTI3 configuration |
| AnnaBridge | 167:e84263d55307 | 16248 | */ |
| AnnaBridge | 167:e84263d55307 | 16249 | #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */ |
| AnnaBridge | 167:e84263d55307 | 16250 | #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */ |
| AnnaBridge | 167:e84263d55307 | 16251 | #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */ |
| AnnaBridge | 167:e84263d55307 | 16252 | #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */ |
| AnnaBridge | 167:e84263d55307 | 16253 | #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */ |
| AnnaBridge | 167:e84263d55307 | 16254 | #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */ |
| AnnaBridge | 167:e84263d55307 | 16255 | #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */ |
| AnnaBridge | 167:e84263d55307 | 16256 | #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */ |
| AnnaBridge | 167:e84263d55307 | 16257 | #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */ |
| AnnaBridge | 167:e84263d55307 | 16258 | #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */ |
| AnnaBridge | 167:e84263d55307 | 16259 | #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */ |
| mbed_official | 19:112740acecfa | 16260 | |
| mbed_official | 19:112740acecfa | 16261 | /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 16262 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16263 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 16264 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16265 | #define SYSCFG_EXTICR2_EXTI5_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16266 | #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 16267 | #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16268 | #define SYSCFG_EXTICR2_EXTI6_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16269 | #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 16270 | #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16271 | #define SYSCFG_EXTICR2_EXTI7_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16272 | #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 167:e84263d55307 | 16273 | #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16274 | |
| AnnaBridge | 167:e84263d55307 | 16275 | /** |
| mbed_official | 19:112740acecfa | 16276 | * @brief EXTI4 configuration |
| AnnaBridge | 167:e84263d55307 | 16277 | */ |
| AnnaBridge | 167:e84263d55307 | 16278 | #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16279 | #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16280 | #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16281 | #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16282 | #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16283 | #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16284 | #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16285 | #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16286 | #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16287 | #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16288 | #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */ |
| AnnaBridge | 167:e84263d55307 | 16289 | |
| AnnaBridge | 167:e84263d55307 | 16290 | /** |
| mbed_official | 19:112740acecfa | 16291 | * @brief EXTI5 configuration |
| AnnaBridge | 167:e84263d55307 | 16292 | */ |
| AnnaBridge | 167:e84263d55307 | 16293 | #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16294 | #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16295 | #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16296 | #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16297 | #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16298 | #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16299 | #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16300 | #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16301 | #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16302 | #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16303 | #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */ |
| AnnaBridge | 167:e84263d55307 | 16304 | |
| AnnaBridge | 167:e84263d55307 | 16305 | /** |
| mbed_official | 19:112740acecfa | 16306 | * @brief EXTI6 configuration |
| AnnaBridge | 167:e84263d55307 | 16307 | */ |
| AnnaBridge | 167:e84263d55307 | 16308 | #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16309 | #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16310 | #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16311 | #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16312 | #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16313 | #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16314 | #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16315 | #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16316 | #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16317 | #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16318 | #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */ |
| AnnaBridge | 167:e84263d55307 | 16319 | |
| AnnaBridge | 167:e84263d55307 | 16320 | /** |
| mbed_official | 19:112740acecfa | 16321 | * @brief EXTI7 configuration |
| AnnaBridge | 167:e84263d55307 | 16322 | */ |
| AnnaBridge | 167:e84263d55307 | 16323 | #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */ |
| AnnaBridge | 167:e84263d55307 | 16324 | #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */ |
| AnnaBridge | 167:e84263d55307 | 16325 | #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */ |
| AnnaBridge | 167:e84263d55307 | 16326 | #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */ |
| AnnaBridge | 167:e84263d55307 | 16327 | #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */ |
| AnnaBridge | 167:e84263d55307 | 16328 | #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */ |
| AnnaBridge | 167:e84263d55307 | 16329 | #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */ |
| AnnaBridge | 167:e84263d55307 | 16330 | #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */ |
| AnnaBridge | 167:e84263d55307 | 16331 | #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */ |
| AnnaBridge | 167:e84263d55307 | 16332 | #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */ |
| AnnaBridge | 167:e84263d55307 | 16333 | #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */ |
| mbed_official | 19:112740acecfa | 16334 | |
| mbed_official | 19:112740acecfa | 16335 | /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 16336 | #define SYSCFG_EXTICR3_EXTI8_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16337 | #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 16338 | #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16339 | #define SYSCFG_EXTICR3_EXTI9_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16340 | #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 16341 | #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16342 | #define SYSCFG_EXTICR3_EXTI10_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16343 | #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 16344 | #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16345 | #define SYSCFG_EXTICR3_EXTI11_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16346 | #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 167:e84263d55307 | 16347 | #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16348 | |
| AnnaBridge | 167:e84263d55307 | 16349 | /** |
| mbed_official | 19:112740acecfa | 16350 | * @brief EXTI8 configuration |
| AnnaBridge | 167:e84263d55307 | 16351 | */ |
| AnnaBridge | 167:e84263d55307 | 16352 | #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */ |
| AnnaBridge | 167:e84263d55307 | 16353 | #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */ |
| AnnaBridge | 167:e84263d55307 | 16354 | #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */ |
| AnnaBridge | 167:e84263d55307 | 16355 | #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */ |
| AnnaBridge | 167:e84263d55307 | 16356 | #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */ |
| AnnaBridge | 167:e84263d55307 | 16357 | #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */ |
| AnnaBridge | 167:e84263d55307 | 16358 | #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */ |
| AnnaBridge | 167:e84263d55307 | 16359 | #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */ |
| AnnaBridge | 167:e84263d55307 | 16360 | #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */ |
| AnnaBridge | 167:e84263d55307 | 16361 | #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */ |
| AnnaBridge | 167:e84263d55307 | 16362 | |
| AnnaBridge | 167:e84263d55307 | 16363 | /** |
| mbed_official | 19:112740acecfa | 16364 | * @brief EXTI9 configuration |
| AnnaBridge | 167:e84263d55307 | 16365 | */ |
| AnnaBridge | 167:e84263d55307 | 16366 | #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */ |
| AnnaBridge | 167:e84263d55307 | 16367 | #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */ |
| AnnaBridge | 167:e84263d55307 | 16368 | #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */ |
| AnnaBridge | 167:e84263d55307 | 16369 | #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */ |
| AnnaBridge | 167:e84263d55307 | 16370 | #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */ |
| AnnaBridge | 167:e84263d55307 | 16371 | #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */ |
| AnnaBridge | 167:e84263d55307 | 16372 | #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */ |
| AnnaBridge | 167:e84263d55307 | 16373 | #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */ |
| AnnaBridge | 167:e84263d55307 | 16374 | #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */ |
| AnnaBridge | 167:e84263d55307 | 16375 | #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */ |
| AnnaBridge | 167:e84263d55307 | 16376 | |
| AnnaBridge | 167:e84263d55307 | 16377 | /** |
| mbed_official | 19:112740acecfa | 16378 | * @brief EXTI10 configuration |
| AnnaBridge | 167:e84263d55307 | 16379 | */ |
| AnnaBridge | 167:e84263d55307 | 16380 | #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */ |
| AnnaBridge | 167:e84263d55307 | 16381 | #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */ |
| AnnaBridge | 167:e84263d55307 | 16382 | #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */ |
| AnnaBridge | 167:e84263d55307 | 16383 | #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */ |
| AnnaBridge | 167:e84263d55307 | 16384 | #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */ |
| AnnaBridge | 167:e84263d55307 | 16385 | #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */ |
| AnnaBridge | 167:e84263d55307 | 16386 | #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */ |
| AnnaBridge | 167:e84263d55307 | 16387 | #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */ |
| AnnaBridge | 167:e84263d55307 | 16388 | #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */ |
| AnnaBridge | 167:e84263d55307 | 16389 | #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */ |
| AnnaBridge | 167:e84263d55307 | 16390 | |
| AnnaBridge | 167:e84263d55307 | 16391 | /** |
| mbed_official | 19:112740acecfa | 16392 | * @brief EXTI11 configuration |
| AnnaBridge | 167:e84263d55307 | 16393 | */ |
| AnnaBridge | 167:e84263d55307 | 16394 | #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */ |
| AnnaBridge | 167:e84263d55307 | 16395 | #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */ |
| AnnaBridge | 167:e84263d55307 | 16396 | #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */ |
| AnnaBridge | 167:e84263d55307 | 16397 | #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */ |
| AnnaBridge | 167:e84263d55307 | 16398 | #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */ |
| AnnaBridge | 167:e84263d55307 | 16399 | #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */ |
| AnnaBridge | 167:e84263d55307 | 16400 | #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */ |
| AnnaBridge | 167:e84263d55307 | 16401 | #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */ |
| AnnaBridge | 167:e84263d55307 | 16402 | #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */ |
| AnnaBridge | 167:e84263d55307 | 16403 | #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */ |
| mbed_official | 19:112740acecfa | 16404 | |
| mbed_official | 19:112740acecfa | 16405 | |
| mbed_official | 19:112740acecfa | 16406 | /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ |
| AnnaBridge | 167:e84263d55307 | 16407 | #define SYSCFG_EXTICR4_EXTI12_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16408 | #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 16409 | #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16410 | #define SYSCFG_EXTICR4_EXTI13_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16411 | #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 16412 | #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16413 | #define SYSCFG_EXTICR4_EXTI14_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16414 | #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 16415 | #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16416 | #define SYSCFG_EXTICR4_EXTI15_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16417 | #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 167:e84263d55307 | 16418 | #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */ |
| AnnaBridge | 167:e84263d55307 | 16419 | |
| AnnaBridge | 167:e84263d55307 | 16420 | /** |
| mbed_official | 19:112740acecfa | 16421 | * @brief EXTI12 configuration |
| AnnaBridge | 167:e84263d55307 | 16422 | */ |
| AnnaBridge | 167:e84263d55307 | 16423 | #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */ |
| AnnaBridge | 167:e84263d55307 | 16424 | #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */ |
| AnnaBridge | 167:e84263d55307 | 16425 | #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */ |
| AnnaBridge | 167:e84263d55307 | 16426 | #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */ |
| AnnaBridge | 167:e84263d55307 | 16427 | #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */ |
| AnnaBridge | 167:e84263d55307 | 16428 | #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */ |
| AnnaBridge | 167:e84263d55307 | 16429 | #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */ |
| AnnaBridge | 167:e84263d55307 | 16430 | #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */ |
| AnnaBridge | 167:e84263d55307 | 16431 | #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */ |
| AnnaBridge | 167:e84263d55307 | 16432 | #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */ |
| AnnaBridge | 167:e84263d55307 | 16433 | |
| AnnaBridge | 167:e84263d55307 | 16434 | /** |
| mbed_official | 19:112740acecfa | 16435 | * @brief EXTI13 configuration |
| AnnaBridge | 167:e84263d55307 | 16436 | */ |
| AnnaBridge | 167:e84263d55307 | 16437 | #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */ |
| AnnaBridge | 167:e84263d55307 | 16438 | #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */ |
| AnnaBridge | 167:e84263d55307 | 16439 | #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */ |
| AnnaBridge | 167:e84263d55307 | 16440 | #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */ |
| AnnaBridge | 167:e84263d55307 | 16441 | #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */ |
| AnnaBridge | 167:e84263d55307 | 16442 | #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */ |
| AnnaBridge | 167:e84263d55307 | 16443 | #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */ |
| AnnaBridge | 167:e84263d55307 | 16444 | #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */ |
| AnnaBridge | 167:e84263d55307 | 16445 | #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */ |
| AnnaBridge | 167:e84263d55307 | 16446 | #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */ |
| AnnaBridge | 167:e84263d55307 | 16447 | |
| AnnaBridge | 167:e84263d55307 | 16448 | /** |
| mbed_official | 19:112740acecfa | 16449 | * @brief EXTI14 configuration |
| AnnaBridge | 167:e84263d55307 | 16450 | */ |
| AnnaBridge | 167:e84263d55307 | 16451 | #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */ |
| AnnaBridge | 167:e84263d55307 | 16452 | #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */ |
| AnnaBridge | 167:e84263d55307 | 16453 | #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */ |
| AnnaBridge | 167:e84263d55307 | 16454 | #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */ |
| AnnaBridge | 167:e84263d55307 | 16455 | #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */ |
| AnnaBridge | 167:e84263d55307 | 16456 | #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */ |
| AnnaBridge | 167:e84263d55307 | 16457 | #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */ |
| AnnaBridge | 167:e84263d55307 | 16458 | #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */ |
| AnnaBridge | 167:e84263d55307 | 16459 | #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */ |
| AnnaBridge | 167:e84263d55307 | 16460 | #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */ |
| AnnaBridge | 167:e84263d55307 | 16461 | |
| AnnaBridge | 167:e84263d55307 | 16462 | /** |
| mbed_official | 19:112740acecfa | 16463 | * @brief EXTI15 configuration |
| AnnaBridge | 167:e84263d55307 | 16464 | */ |
| AnnaBridge | 167:e84263d55307 | 16465 | #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */ |
| AnnaBridge | 167:e84263d55307 | 16466 | #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */ |
| AnnaBridge | 167:e84263d55307 | 16467 | #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */ |
| AnnaBridge | 167:e84263d55307 | 16468 | #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */ |
| AnnaBridge | 167:e84263d55307 | 16469 | #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */ |
| AnnaBridge | 167:e84263d55307 | 16470 | #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */ |
| AnnaBridge | 167:e84263d55307 | 16471 | #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */ |
| AnnaBridge | 167:e84263d55307 | 16472 | #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */ |
| AnnaBridge | 167:e84263d55307 | 16473 | #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */ |
| AnnaBridge | 167:e84263d55307 | 16474 | #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */ |
| AnnaBridge | 167:e84263d55307 | 16475 | |
| AnnaBridge | 167:e84263d55307 | 16476 | /****************** Bit definition for SYSCFG_CMPCR register ****************/ |
| AnnaBridge | 167:e84263d55307 | 16477 | #define SYSCFG_CMPCR_CMP_PD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16478 | #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16479 | #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */ |
| AnnaBridge | 167:e84263d55307 | 16480 | #define SYSCFG_CMPCR_READY_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16481 | #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 16482 | #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */ |
| mbed_official | 19:112740acecfa | 16483 | |
| mbed_official | 19:112740acecfa | 16484 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 16485 | /* */ |
| mbed_official | 19:112740acecfa | 16486 | /* TIM */ |
| mbed_official | 19:112740acecfa | 16487 | /* */ |
| mbed_official | 19:112740acecfa | 16488 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 16489 | /******************* Bit definition for TIM_CR1 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16490 | #define TIM_CR1_CEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16491 | #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16492 | #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ |
| AnnaBridge | 167:e84263d55307 | 16493 | #define TIM_CR1_UDIS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 16494 | #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 16495 | #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ |
| AnnaBridge | 167:e84263d55307 | 16496 | #define TIM_CR1_URS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16497 | #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16498 | #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ |
| AnnaBridge | 167:e84263d55307 | 16499 | #define TIM_CR1_OPM_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 16500 | #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 16501 | #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ |
| AnnaBridge | 167:e84263d55307 | 16502 | #define TIM_CR1_DIR_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16503 | #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 16504 | #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ |
| AnnaBridge | 167:e84263d55307 | 16505 | |
| AnnaBridge | 167:e84263d55307 | 16506 | #define TIM_CR1_CMS_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 16507 | #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 167:e84263d55307 | 16508 | #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
| AnnaBridge | 167:e84263d55307 | 16509 | #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 16510 | #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 16511 | |
| AnnaBridge | 167:e84263d55307 | 16512 | #define TIM_CR1_ARPE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16513 | #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16514 | #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ |
| AnnaBridge | 167:e84263d55307 | 16515 | |
| AnnaBridge | 167:e84263d55307 | 16516 | #define TIM_CR1_CKD_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16517 | #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 16518 | #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ |
| AnnaBridge | 167:e84263d55307 | 16519 | #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */ |
| AnnaBridge | 167:e84263d55307 | 16520 | #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */ |
| mbed_official | 19:112740acecfa | 16521 | |
| mbed_official | 19:112740acecfa | 16522 | /******************* Bit definition for TIM_CR2 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16523 | #define TIM_CR2_CCPC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16524 | #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16525 | #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ |
| AnnaBridge | 167:e84263d55307 | 16526 | #define TIM_CR2_CCUS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16527 | #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16528 | #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ |
| AnnaBridge | 167:e84263d55307 | 16529 | #define TIM_CR2_CCDS_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 16530 | #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 16531 | #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ |
| AnnaBridge | 167:e84263d55307 | 16532 | |
| AnnaBridge | 167:e84263d55307 | 16533 | #define TIM_CR2_MMS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16534 | #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 16535 | #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ |
| AnnaBridge | 167:e84263d55307 | 16536 | #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 16537 | #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 16538 | #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 16539 | |
| AnnaBridge | 167:e84263d55307 | 16540 | #define TIM_CR2_TI1S_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16541 | #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16542 | #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ |
| AnnaBridge | 167:e84263d55307 | 16543 | #define TIM_CR2_OIS1_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16544 | #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 16545 | #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ |
| AnnaBridge | 167:e84263d55307 | 16546 | #define TIM_CR2_OIS1N_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 16547 | #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 16548 | #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ |
| AnnaBridge | 167:e84263d55307 | 16549 | #define TIM_CR2_OIS2_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16550 | #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 16551 | #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ |
| AnnaBridge | 167:e84263d55307 | 16552 | #define TIM_CR2_OIS2N_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 16553 | #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 16554 | #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ |
| AnnaBridge | 167:e84263d55307 | 16555 | #define TIM_CR2_OIS3_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16556 | #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 16557 | #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ |
| AnnaBridge | 167:e84263d55307 | 16558 | #define TIM_CR2_OIS3N_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 16559 | #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 16560 | #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ |
| AnnaBridge | 167:e84263d55307 | 16561 | #define TIM_CR2_OIS4_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 16562 | #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 16563 | #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ |
| mbed_official | 19:112740acecfa | 16564 | |
| mbed_official | 19:112740acecfa | 16565 | /******************* Bit definition for TIM_SMCR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16566 | #define TIM_SMCR_SMS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16567 | #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 16568 | #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ |
| AnnaBridge | 167:e84263d55307 | 16569 | #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */ |
| AnnaBridge | 167:e84263d55307 | 16570 | #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */ |
| AnnaBridge | 167:e84263d55307 | 16571 | #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */ |
| AnnaBridge | 167:e84263d55307 | 16572 | |
| AnnaBridge | 167:e84263d55307 | 16573 | #define TIM_SMCR_TS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16574 | #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 16575 | #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ |
| AnnaBridge | 167:e84263d55307 | 16576 | #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 16577 | #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 16578 | #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 16579 | |
| AnnaBridge | 167:e84263d55307 | 16580 | #define TIM_SMCR_MSM_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16581 | #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16582 | #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ |
| AnnaBridge | 167:e84263d55307 | 16583 | |
| AnnaBridge | 167:e84263d55307 | 16584 | #define TIM_SMCR_ETF_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16585 | #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 16586 | #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ |
| AnnaBridge | 167:e84263d55307 | 16587 | #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */ |
| AnnaBridge | 167:e84263d55307 | 16588 | #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */ |
| AnnaBridge | 167:e84263d55307 | 16589 | #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */ |
| AnnaBridge | 167:e84263d55307 | 16590 | #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */ |
| AnnaBridge | 167:e84263d55307 | 16591 | |
| AnnaBridge | 167:e84263d55307 | 16592 | #define TIM_SMCR_ETPS_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16593 | #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 167:e84263d55307 | 16594 | #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ |
| AnnaBridge | 167:e84263d55307 | 16595 | #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */ |
| AnnaBridge | 167:e84263d55307 | 16596 | #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */ |
| AnnaBridge | 167:e84263d55307 | 16597 | |
| AnnaBridge | 167:e84263d55307 | 16598 | #define TIM_SMCR_ECE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 16599 | #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 16600 | #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ |
| AnnaBridge | 167:e84263d55307 | 16601 | #define TIM_SMCR_ETP_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 16602 | #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 16603 | #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ |
| mbed_official | 19:112740acecfa | 16604 | |
| mbed_official | 19:112740acecfa | 16605 | /******************* Bit definition for TIM_DIER register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16606 | #define TIM_DIER_UIE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16607 | #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16608 | #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 16609 | #define TIM_DIER_CC1IE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 16610 | #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 16611 | #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 16612 | #define TIM_DIER_CC2IE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16613 | #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16614 | #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 16615 | #define TIM_DIER_CC3IE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 16616 | #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 16617 | #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 16618 | #define TIM_DIER_CC4IE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16619 | #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 16620 | #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 16621 | #define TIM_DIER_COMIE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 16622 | #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 16623 | #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 16624 | #define TIM_DIER_TIE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 16625 | #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 16626 | #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 16627 | #define TIM_DIER_BIE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16628 | #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16629 | #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 16630 | #define TIM_DIER_UDE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16631 | #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 16632 | #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ |
| AnnaBridge | 167:e84263d55307 | 16633 | #define TIM_DIER_CC1DE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 16634 | #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 16635 | #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ |
| AnnaBridge | 167:e84263d55307 | 16636 | #define TIM_DIER_CC2DE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16637 | #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 16638 | #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ |
| AnnaBridge | 167:e84263d55307 | 16639 | #define TIM_DIER_CC3DE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 16640 | #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 16641 | #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ |
| AnnaBridge | 167:e84263d55307 | 16642 | #define TIM_DIER_CC4DE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16643 | #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 16644 | #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ |
| AnnaBridge | 167:e84263d55307 | 16645 | #define TIM_DIER_COMDE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 16646 | #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 16647 | #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ |
| AnnaBridge | 167:e84263d55307 | 16648 | #define TIM_DIER_TDE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 16649 | #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 16650 | #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ |
| mbed_official | 19:112740acecfa | 16651 | |
| mbed_official | 19:112740acecfa | 16652 | /******************** Bit definition for TIM_SR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16653 | #define TIM_SR_UIF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16654 | #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16655 | #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 16656 | #define TIM_SR_CC1IF_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 16657 | #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 16658 | #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 16659 | #define TIM_SR_CC2IF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16660 | #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16661 | #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 16662 | #define TIM_SR_CC3IF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 16663 | #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 16664 | #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 16665 | #define TIM_SR_CC4IF_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16666 | #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 16667 | #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 16668 | #define TIM_SR_COMIF_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 16669 | #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 16670 | #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 16671 | #define TIM_SR_TIF_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 16672 | #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 16673 | #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 16674 | #define TIM_SR_BIF_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16675 | #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16676 | #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ |
| AnnaBridge | 167:e84263d55307 | 16677 | #define TIM_SR_CC1OF_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 16678 | #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 16679 | #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ |
| AnnaBridge | 167:e84263d55307 | 16680 | #define TIM_SR_CC2OF_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16681 | #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 16682 | #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ |
| AnnaBridge | 167:e84263d55307 | 16683 | #define TIM_SR_CC3OF_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 16684 | #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 16685 | #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ |
| AnnaBridge | 167:e84263d55307 | 16686 | #define TIM_SR_CC4OF_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16687 | #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 16688 | #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ |
| mbed_official | 19:112740acecfa | 16689 | |
| mbed_official | 19:112740acecfa | 16690 | /******************* Bit definition for TIM_EGR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16691 | #define TIM_EGR_UG_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16692 | #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16693 | #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ |
| AnnaBridge | 167:e84263d55307 | 16694 | #define TIM_EGR_CC1G_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 16695 | #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 16696 | #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ |
| AnnaBridge | 167:e84263d55307 | 16697 | #define TIM_EGR_CC2G_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16698 | #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16699 | #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ |
| AnnaBridge | 167:e84263d55307 | 16700 | #define TIM_EGR_CC3G_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 16701 | #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 16702 | #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ |
| AnnaBridge | 167:e84263d55307 | 16703 | #define TIM_EGR_CC4G_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16704 | #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 16705 | #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ |
| AnnaBridge | 167:e84263d55307 | 16706 | #define TIM_EGR_COMG_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 16707 | #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 16708 | #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ |
| AnnaBridge | 167:e84263d55307 | 16709 | #define TIM_EGR_TG_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 16710 | #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 16711 | #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ |
| AnnaBridge | 167:e84263d55307 | 16712 | #define TIM_EGR_BG_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16713 | #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16714 | #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ |
| mbed_official | 19:112740acecfa | 16715 | |
| mbed_official | 19:112740acecfa | 16716 | /****************** Bit definition for TIM_CCMR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16717 | #define TIM_CCMR1_CC1S_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16718 | #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 16719 | #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
| AnnaBridge | 167:e84263d55307 | 16720 | #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */ |
| AnnaBridge | 167:e84263d55307 | 16721 | #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */ |
| AnnaBridge | 167:e84263d55307 | 16722 | |
| AnnaBridge | 167:e84263d55307 | 16723 | #define TIM_CCMR1_OC1FE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16724 | #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16725 | #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ |
| AnnaBridge | 167:e84263d55307 | 16726 | #define TIM_CCMR1_OC1PE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 16727 | #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 16728 | #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ |
| AnnaBridge | 167:e84263d55307 | 16729 | |
| AnnaBridge | 167:e84263d55307 | 16730 | #define TIM_CCMR1_OC1M_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16731 | #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 16732 | #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
| AnnaBridge | 167:e84263d55307 | 16733 | #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 16734 | #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 16735 | #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 16736 | |
| AnnaBridge | 167:e84263d55307 | 16737 | #define TIM_CCMR1_OC1CE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16738 | #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16739 | #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ |
| AnnaBridge | 167:e84263d55307 | 16740 | |
| AnnaBridge | 167:e84263d55307 | 16741 | #define TIM_CCMR1_CC2S_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16742 | #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 16743 | #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
| AnnaBridge | 167:e84263d55307 | 16744 | #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */ |
| AnnaBridge | 167:e84263d55307 | 16745 | #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */ |
| AnnaBridge | 167:e84263d55307 | 16746 | |
| AnnaBridge | 167:e84263d55307 | 16747 | #define TIM_CCMR1_OC2FE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16748 | #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 16749 | #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ |
| AnnaBridge | 167:e84263d55307 | 16750 | #define TIM_CCMR1_OC2PE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 16751 | #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 16752 | #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ |
| AnnaBridge | 167:e84263d55307 | 16753 | |
| AnnaBridge | 167:e84263d55307 | 16754 | #define TIM_CCMR1_OC2M_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16755 | #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 167:e84263d55307 | 16756 | #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
| AnnaBridge | 167:e84263d55307 | 16757 | #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */ |
| AnnaBridge | 167:e84263d55307 | 16758 | #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */ |
| AnnaBridge | 167:e84263d55307 | 16759 | #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */ |
| AnnaBridge | 167:e84263d55307 | 16760 | |
| AnnaBridge | 167:e84263d55307 | 16761 | #define TIM_CCMR1_OC2CE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 16762 | #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 16763 | #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ |
| mbed_official | 19:112740acecfa | 16764 | |
| mbed_official | 19:112740acecfa | 16765 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 19:112740acecfa | 16766 | |
| AnnaBridge | 167:e84263d55307 | 16767 | #define TIM_CCMR1_IC1PSC_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16768 | #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 16769 | #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
| AnnaBridge | 167:e84263d55307 | 16770 | #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */ |
| AnnaBridge | 167:e84263d55307 | 16771 | #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */ |
| AnnaBridge | 167:e84263d55307 | 16772 | |
| AnnaBridge | 167:e84263d55307 | 16773 | #define TIM_CCMR1_IC1F_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16774 | #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 16775 | #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
| AnnaBridge | 167:e84263d55307 | 16776 | #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 16777 | #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 16778 | #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 16779 | #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */ |
| AnnaBridge | 167:e84263d55307 | 16780 | |
| AnnaBridge | 167:e84263d55307 | 16781 | #define TIM_CCMR1_IC2PSC_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16782 | #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 16783 | #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
| AnnaBridge | 167:e84263d55307 | 16784 | #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */ |
| AnnaBridge | 167:e84263d55307 | 16785 | #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */ |
| AnnaBridge | 167:e84263d55307 | 16786 | |
| AnnaBridge | 167:e84263d55307 | 16787 | #define TIM_CCMR1_IC2F_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16788 | #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 167:e84263d55307 | 16789 | #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
| AnnaBridge | 167:e84263d55307 | 16790 | #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */ |
| AnnaBridge | 167:e84263d55307 | 16791 | #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */ |
| AnnaBridge | 167:e84263d55307 | 16792 | #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */ |
| AnnaBridge | 167:e84263d55307 | 16793 | #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */ |
| mbed_official | 19:112740acecfa | 16794 | |
| mbed_official | 19:112740acecfa | 16795 | /****************** Bit definition for TIM_CCMR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16796 | #define TIM_CCMR2_CC3S_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16797 | #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 16798 | #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
| AnnaBridge | 167:e84263d55307 | 16799 | #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */ |
| AnnaBridge | 167:e84263d55307 | 16800 | #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */ |
| AnnaBridge | 167:e84263d55307 | 16801 | |
| AnnaBridge | 167:e84263d55307 | 16802 | #define TIM_CCMR2_OC3FE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16803 | #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16804 | #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ |
| AnnaBridge | 167:e84263d55307 | 16805 | #define TIM_CCMR2_OC3PE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 16806 | #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 16807 | #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ |
| AnnaBridge | 167:e84263d55307 | 16808 | |
| AnnaBridge | 167:e84263d55307 | 16809 | #define TIM_CCMR2_OC3M_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16810 | #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 16811 | #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
| AnnaBridge | 167:e84263d55307 | 16812 | #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 16813 | #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 16814 | #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 16815 | |
| AnnaBridge | 167:e84263d55307 | 16816 | #define TIM_CCMR2_OC3CE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16817 | #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16818 | #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ |
| AnnaBridge | 167:e84263d55307 | 16819 | |
| AnnaBridge | 167:e84263d55307 | 16820 | #define TIM_CCMR2_CC4S_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16821 | #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 16822 | #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
| AnnaBridge | 167:e84263d55307 | 16823 | #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */ |
| AnnaBridge | 167:e84263d55307 | 16824 | #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */ |
| AnnaBridge | 167:e84263d55307 | 16825 | |
| AnnaBridge | 167:e84263d55307 | 16826 | #define TIM_CCMR2_OC4FE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16827 | #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 16828 | #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ |
| AnnaBridge | 167:e84263d55307 | 16829 | #define TIM_CCMR2_OC4PE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 16830 | #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 16831 | #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ |
| AnnaBridge | 167:e84263d55307 | 16832 | |
| AnnaBridge | 167:e84263d55307 | 16833 | #define TIM_CCMR2_OC4M_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16834 | #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 167:e84263d55307 | 16835 | #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
| AnnaBridge | 167:e84263d55307 | 16836 | #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */ |
| AnnaBridge | 167:e84263d55307 | 16837 | #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */ |
| AnnaBridge | 167:e84263d55307 | 16838 | #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */ |
| AnnaBridge | 167:e84263d55307 | 16839 | |
| AnnaBridge | 167:e84263d55307 | 16840 | #define TIM_CCMR2_OC4CE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 16841 | #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 16842 | #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ |
| mbed_official | 19:112740acecfa | 16843 | |
| mbed_official | 19:112740acecfa | 16844 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 19:112740acecfa | 16845 | |
| AnnaBridge | 167:e84263d55307 | 16846 | #define TIM_CCMR2_IC3PSC_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16847 | #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 16848 | #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
| AnnaBridge | 167:e84263d55307 | 16849 | #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */ |
| AnnaBridge | 167:e84263d55307 | 16850 | #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */ |
| AnnaBridge | 167:e84263d55307 | 16851 | |
| AnnaBridge | 167:e84263d55307 | 16852 | #define TIM_CCMR2_IC3F_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16853 | #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 167:e84263d55307 | 16854 | #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
| AnnaBridge | 167:e84263d55307 | 16855 | #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 16856 | #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 16857 | #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 16858 | #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */ |
| AnnaBridge | 167:e84263d55307 | 16859 | |
| AnnaBridge | 167:e84263d55307 | 16860 | #define TIM_CCMR2_IC4PSC_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16861 | #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 16862 | #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
| AnnaBridge | 167:e84263d55307 | 16863 | #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */ |
| AnnaBridge | 167:e84263d55307 | 16864 | #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */ |
| AnnaBridge | 167:e84263d55307 | 16865 | |
| AnnaBridge | 167:e84263d55307 | 16866 | #define TIM_CCMR2_IC4F_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16867 | #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 167:e84263d55307 | 16868 | #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
| AnnaBridge | 167:e84263d55307 | 16869 | #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */ |
| AnnaBridge | 167:e84263d55307 | 16870 | #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */ |
| AnnaBridge | 167:e84263d55307 | 16871 | #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */ |
| AnnaBridge | 167:e84263d55307 | 16872 | #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */ |
| mbed_official | 19:112740acecfa | 16873 | |
| mbed_official | 19:112740acecfa | 16874 | /******************* Bit definition for TIM_CCER register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16875 | #define TIM_CCER_CC1E_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16876 | #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 16877 | #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ |
| AnnaBridge | 167:e84263d55307 | 16878 | #define TIM_CCER_CC1P_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 16879 | #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 16880 | #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ |
| AnnaBridge | 167:e84263d55307 | 16881 | #define TIM_CCER_CC1NE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 16882 | #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 16883 | #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ |
| AnnaBridge | 167:e84263d55307 | 16884 | #define TIM_CCER_CC1NP_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 16885 | #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 16886 | #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ |
| AnnaBridge | 167:e84263d55307 | 16887 | #define TIM_CCER_CC2E_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 16888 | #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 16889 | #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ |
| AnnaBridge | 167:e84263d55307 | 16890 | #define TIM_CCER_CC2P_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 16891 | #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 16892 | #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ |
| AnnaBridge | 167:e84263d55307 | 16893 | #define TIM_CCER_CC2NE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 16894 | #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 16895 | #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ |
| AnnaBridge | 167:e84263d55307 | 16896 | #define TIM_CCER_CC2NP_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 16897 | #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 16898 | #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ |
| AnnaBridge | 167:e84263d55307 | 16899 | #define TIM_CCER_CC3E_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16900 | #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 16901 | #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ |
| AnnaBridge | 167:e84263d55307 | 16902 | #define TIM_CCER_CC3P_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 16903 | #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 16904 | #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ |
| AnnaBridge | 167:e84263d55307 | 16905 | #define TIM_CCER_CC3NE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16906 | #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 16907 | #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ |
| AnnaBridge | 167:e84263d55307 | 16908 | #define TIM_CCER_CC3NP_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 16909 | #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 16910 | #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ |
| AnnaBridge | 167:e84263d55307 | 16911 | #define TIM_CCER_CC4E_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16912 | #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 16913 | #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ |
| AnnaBridge | 167:e84263d55307 | 16914 | #define TIM_CCER_CC4P_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 16915 | #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 16916 | #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ |
| AnnaBridge | 167:e84263d55307 | 16917 | #define TIM_CCER_CC4NP_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 16918 | #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 16919 | #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ |
| mbed_official | 19:112740acecfa | 16920 | |
| mbed_official | 19:112740acecfa | 16921 | /******************* Bit definition for TIM_CNT register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16922 | #define TIM_CNT_CNT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16923 | #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 16924 | #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ |
| mbed_official | 19:112740acecfa | 16925 | |
| mbed_official | 19:112740acecfa | 16926 | /******************* Bit definition for TIM_PSC register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16927 | #define TIM_PSC_PSC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16928 | #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 16929 | #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ |
| mbed_official | 19:112740acecfa | 16930 | |
| mbed_official | 19:112740acecfa | 16931 | /******************* Bit definition for TIM_ARR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16932 | #define TIM_ARR_ARR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16933 | #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 16934 | #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ |
| mbed_official | 19:112740acecfa | 16935 | |
| mbed_official | 19:112740acecfa | 16936 | /******************* Bit definition for TIM_RCR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 16937 | #define TIM_RCR_REP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16938 | #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 16939 | #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ |
| mbed_official | 19:112740acecfa | 16940 | |
| mbed_official | 19:112740acecfa | 16941 | /******************* Bit definition for TIM_CCR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16942 | #define TIM_CCR1_CCR1_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16943 | #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 16944 | #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ |
| mbed_official | 19:112740acecfa | 16945 | |
| mbed_official | 19:112740acecfa | 16946 | /******************* Bit definition for TIM_CCR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16947 | #define TIM_CCR2_CCR2_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16948 | #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 16949 | #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ |
| mbed_official | 19:112740acecfa | 16950 | |
| mbed_official | 19:112740acecfa | 16951 | /******************* Bit definition for TIM_CCR3 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16952 | #define TIM_CCR3_CCR3_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16953 | #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 16954 | #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ |
| mbed_official | 19:112740acecfa | 16955 | |
| mbed_official | 19:112740acecfa | 16956 | /******************* Bit definition for TIM_CCR4 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16957 | #define TIM_CCR4_CCR4_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16958 | #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 16959 | #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ |
| mbed_official | 19:112740acecfa | 16960 | |
| mbed_official | 19:112740acecfa | 16961 | /******************* Bit definition for TIM_BDTR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 16962 | #define TIM_BDTR_DTG_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 16963 | #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 16964 | #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
| AnnaBridge | 167:e84263d55307 | 16965 | #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */ |
| AnnaBridge | 167:e84263d55307 | 16966 | #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */ |
| AnnaBridge | 167:e84263d55307 | 16967 | #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */ |
| AnnaBridge | 167:e84263d55307 | 16968 | #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */ |
| AnnaBridge | 167:e84263d55307 | 16969 | #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 16970 | #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 16971 | #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 16972 | #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */ |
| AnnaBridge | 167:e84263d55307 | 16973 | |
| AnnaBridge | 167:e84263d55307 | 16974 | #define TIM_BDTR_LOCK_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 16975 | #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 16976 | #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ |
| AnnaBridge | 167:e84263d55307 | 16977 | #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */ |
| AnnaBridge | 167:e84263d55307 | 16978 | #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */ |
| AnnaBridge | 167:e84263d55307 | 16979 | |
| AnnaBridge | 167:e84263d55307 | 16980 | #define TIM_BDTR_OSSI_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 16981 | #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 16982 | #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ |
| AnnaBridge | 167:e84263d55307 | 16983 | #define TIM_BDTR_OSSR_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 16984 | #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 16985 | #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ |
| AnnaBridge | 167:e84263d55307 | 16986 | #define TIM_BDTR_BKE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 16987 | #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 16988 | #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ |
| AnnaBridge | 167:e84263d55307 | 16989 | #define TIM_BDTR_BKP_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 16990 | #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 16991 | #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ |
| AnnaBridge | 167:e84263d55307 | 16992 | #define TIM_BDTR_AOE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 16993 | #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 16994 | #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ |
| AnnaBridge | 167:e84263d55307 | 16995 | #define TIM_BDTR_MOE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 16996 | #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 16997 | #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ |
| mbed_official | 19:112740acecfa | 16998 | |
| mbed_official | 19:112740acecfa | 16999 | /******************* Bit definition for TIM_DCR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 17000 | #define TIM_DCR_DBA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17001 | #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 167:e84263d55307 | 17002 | #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ |
| AnnaBridge | 167:e84263d55307 | 17003 | #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */ |
| AnnaBridge | 167:e84263d55307 | 17004 | #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */ |
| AnnaBridge | 167:e84263d55307 | 17005 | #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */ |
| AnnaBridge | 167:e84263d55307 | 17006 | #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */ |
| AnnaBridge | 167:e84263d55307 | 17007 | #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 17008 | |
| AnnaBridge | 167:e84263d55307 | 17009 | #define TIM_DCR_DBL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17010 | #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 167:e84263d55307 | 17011 | #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ |
| AnnaBridge | 167:e84263d55307 | 17012 | #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */ |
| AnnaBridge | 167:e84263d55307 | 17013 | #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */ |
| AnnaBridge | 167:e84263d55307 | 17014 | #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */ |
| AnnaBridge | 167:e84263d55307 | 17015 | #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */ |
| AnnaBridge | 167:e84263d55307 | 17016 | #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */ |
| mbed_official | 19:112740acecfa | 17017 | |
| mbed_official | 19:112740acecfa | 17018 | /******************* Bit definition for TIM_DMAR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 17019 | #define TIM_DMAR_DMAB_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17020 | #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 17021 | #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ |
| mbed_official | 19:112740acecfa | 17022 | |
| mbed_official | 19:112740acecfa | 17023 | /******************* Bit definition for TIM_OR register *********************/ |
| AnnaBridge | 167:e84263d55307 | 17024 | #define TIM_OR_TI1_RMP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17025 | #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 17026 | #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */ |
| AnnaBridge | 167:e84263d55307 | 17027 | #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17028 | #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17029 | |
| AnnaBridge | 167:e84263d55307 | 17030 | #define TIM_OR_TI4_RMP_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17031 | #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 17032 | #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */ |
| AnnaBridge | 167:e84263d55307 | 17033 | #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 17034 | #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */ |
| AnnaBridge | 167:e84263d55307 | 17035 | #define TIM_OR_ITR1_RMP_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 17036 | #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 17037 | #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */ |
| AnnaBridge | 167:e84263d55307 | 17038 | #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */ |
| AnnaBridge | 167:e84263d55307 | 17039 | #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */ |
| mbed_official | 19:112740acecfa | 17040 | |
| mbed_official | 19:112740acecfa | 17041 | |
| mbed_official | 19:112740acecfa | 17042 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17043 | /* */ |
| mbed_official | 19:112740acecfa | 17044 | /* Universal Synchronous Asynchronous Receiver Transmitter */ |
| mbed_official | 19:112740acecfa | 17045 | /* */ |
| mbed_official | 19:112740acecfa | 17046 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17047 | /******************* Bit definition for USART_SR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 17048 | #define USART_SR_PE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17049 | #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17050 | #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */ |
| AnnaBridge | 167:e84263d55307 | 17051 | #define USART_SR_FE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17052 | #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17053 | #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */ |
| AnnaBridge | 167:e84263d55307 | 17054 | #define USART_SR_NE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17055 | #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17056 | #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */ |
| AnnaBridge | 167:e84263d55307 | 17057 | #define USART_SR_ORE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17058 | #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17059 | #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */ |
| AnnaBridge | 167:e84263d55307 | 17060 | #define USART_SR_IDLE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17061 | #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17062 | #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */ |
| AnnaBridge | 167:e84263d55307 | 17063 | #define USART_SR_RXNE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17064 | #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17065 | #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */ |
| AnnaBridge | 167:e84263d55307 | 17066 | #define USART_SR_TC_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17067 | #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17068 | #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */ |
| AnnaBridge | 167:e84263d55307 | 17069 | #define USART_SR_TXE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 17070 | #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 17071 | #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */ |
| AnnaBridge | 167:e84263d55307 | 17072 | #define USART_SR_LBD_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17073 | #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 17074 | #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */ |
| AnnaBridge | 167:e84263d55307 | 17075 | #define USART_SR_CTS_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17076 | #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17077 | #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */ |
| mbed_official | 19:112740acecfa | 17078 | |
| mbed_official | 19:112740acecfa | 17079 | /******************* Bit definition for USART_DR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 17080 | #define USART_DR_DR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17081 | #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */ |
| AnnaBridge | 167:e84263d55307 | 17082 | #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */ |
| mbed_official | 19:112740acecfa | 17083 | |
| mbed_official | 19:112740acecfa | 17084 | /****************** Bit definition for USART_BRR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 17085 | #define USART_BRR_DIV_Fraction_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17086 | #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 17087 | #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */ |
| AnnaBridge | 167:e84263d55307 | 17088 | #define USART_BRR_DIV_Mantissa_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17089 | #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 167:e84263d55307 | 17090 | #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */ |
| mbed_official | 19:112740acecfa | 17091 | |
| mbed_official | 19:112740acecfa | 17092 | /****************** Bit definition for USART_CR1 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 17093 | #define USART_CR1_SBK_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17094 | #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17095 | #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */ |
| AnnaBridge | 167:e84263d55307 | 17096 | #define USART_CR1_RWU_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17097 | #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17098 | #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */ |
| AnnaBridge | 167:e84263d55307 | 17099 | #define USART_CR1_RE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17100 | #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17101 | #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */ |
| AnnaBridge | 167:e84263d55307 | 17102 | #define USART_CR1_TE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17103 | #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17104 | #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */ |
| AnnaBridge | 167:e84263d55307 | 17105 | #define USART_CR1_IDLEIE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17106 | #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17107 | #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 17108 | #define USART_CR1_RXNEIE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17109 | #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17110 | #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 17111 | #define USART_CR1_TCIE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17112 | #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17113 | #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 17114 | #define USART_CR1_TXEIE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 17115 | #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 182:a56a73fd2a6f | 17116 | #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 17117 | #define USART_CR1_PEIE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17118 | #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 17119 | #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 17120 | #define USART_CR1_PS_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17121 | #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17122 | #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */ |
| AnnaBridge | 167:e84263d55307 | 17123 | #define USART_CR1_PCE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 17124 | #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 17125 | #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */ |
| AnnaBridge | 167:e84263d55307 | 17126 | #define USART_CR1_WAKE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 17127 | #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 17128 | #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */ |
| AnnaBridge | 167:e84263d55307 | 17129 | #define USART_CR1_M_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 17130 | #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 17131 | #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */ |
| AnnaBridge | 167:e84263d55307 | 17132 | #define USART_CR1_UE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 17133 | #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 17134 | #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */ |
| AnnaBridge | 167:e84263d55307 | 17135 | #define USART_CR1_OVER8_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 17136 | #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 17137 | #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */ |
| mbed_official | 19:112740acecfa | 17138 | |
| mbed_official | 19:112740acecfa | 17139 | /****************** Bit definition for USART_CR2 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 17140 | #define USART_CR2_ADD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17141 | #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 17142 | #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */ |
| AnnaBridge | 167:e84263d55307 | 17143 | #define USART_CR2_LBDL_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17144 | #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17145 | #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */ |
| AnnaBridge | 167:e84263d55307 | 17146 | #define USART_CR2_LBDIE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17147 | #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17148 | #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 17149 | #define USART_CR2_LBCL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17150 | #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 17151 | #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */ |
| AnnaBridge | 167:e84263d55307 | 17152 | #define USART_CR2_CPHA_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17153 | #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17154 | #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */ |
| AnnaBridge | 167:e84263d55307 | 17155 | #define USART_CR2_CPOL_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 17156 | #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 17157 | #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */ |
| AnnaBridge | 167:e84263d55307 | 17158 | #define USART_CR2_CLKEN_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 17159 | #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 17160 | #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */ |
| AnnaBridge | 167:e84263d55307 | 17161 | |
| AnnaBridge | 167:e84263d55307 | 17162 | #define USART_CR2_STOP_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 17163 | #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 167:e84263d55307 | 17164 | #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */ |
| AnnaBridge | 167:e84263d55307 | 17165 | #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */ |
| AnnaBridge | 167:e84263d55307 | 17166 | #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */ |
| AnnaBridge | 167:e84263d55307 | 17167 | |
| AnnaBridge | 167:e84263d55307 | 17168 | #define USART_CR2_LINEN_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 17169 | #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 17170 | #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */ |
| mbed_official | 19:112740acecfa | 17171 | |
| mbed_official | 19:112740acecfa | 17172 | /****************** Bit definition for USART_CR3 register *******************/ |
| AnnaBridge | 167:e84263d55307 | 17173 | #define USART_CR3_EIE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17174 | #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17175 | #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 17176 | #define USART_CR3_IREN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17177 | #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17178 | #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */ |
| AnnaBridge | 167:e84263d55307 | 17179 | #define USART_CR3_IRLP_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17180 | #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17181 | #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */ |
| AnnaBridge | 167:e84263d55307 | 17182 | #define USART_CR3_HDSEL_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17183 | #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17184 | #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */ |
| AnnaBridge | 167:e84263d55307 | 17185 | #define USART_CR3_NACK_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17186 | #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17187 | #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */ |
| AnnaBridge | 167:e84263d55307 | 17188 | #define USART_CR3_SCEN_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17189 | #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17190 | #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */ |
| AnnaBridge | 167:e84263d55307 | 17191 | #define USART_CR3_DMAR_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17192 | #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17193 | #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */ |
| AnnaBridge | 167:e84263d55307 | 17194 | #define USART_CR3_DMAT_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 17195 | #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 17196 | #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */ |
| AnnaBridge | 167:e84263d55307 | 17197 | #define USART_CR3_RTSE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17198 | #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 17199 | #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */ |
| AnnaBridge | 167:e84263d55307 | 17200 | #define USART_CR3_CTSE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17201 | #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17202 | #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */ |
| AnnaBridge | 167:e84263d55307 | 17203 | #define USART_CR3_CTSIE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 17204 | #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 17205 | #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */ |
| AnnaBridge | 167:e84263d55307 | 17206 | #define USART_CR3_ONEBIT_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 17207 | #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 17208 | #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */ |
| mbed_official | 19:112740acecfa | 17209 | |
| mbed_official | 19:112740acecfa | 17210 | /****************** Bit definition for USART_GTPR register ******************/ |
| AnnaBridge | 167:e84263d55307 | 17211 | #define USART_GTPR_PSC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17212 | #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 17213 | #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */ |
| AnnaBridge | 167:e84263d55307 | 17214 | #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */ |
| AnnaBridge | 167:e84263d55307 | 17215 | #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */ |
| AnnaBridge | 167:e84263d55307 | 17216 | #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */ |
| AnnaBridge | 167:e84263d55307 | 17217 | #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */ |
| AnnaBridge | 167:e84263d55307 | 17218 | #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 17219 | #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 17220 | #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */ |
| AnnaBridge | 167:e84263d55307 | 17221 | #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */ |
| AnnaBridge | 167:e84263d55307 | 17222 | |
| AnnaBridge | 167:e84263d55307 | 17223 | #define USART_GTPR_GT_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17224 | #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 167:e84263d55307 | 17225 | #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */ |
| mbed_official | 19:112740acecfa | 17226 | |
| mbed_official | 19:112740acecfa | 17227 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17228 | /* */ |
| mbed_official | 19:112740acecfa | 17229 | /* Window WATCHDOG */ |
| mbed_official | 19:112740acecfa | 17230 | /* */ |
| mbed_official | 19:112740acecfa | 17231 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17232 | /******************* Bit definition for WWDG_CR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 17233 | #define WWDG_CR_T_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17234 | #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ |
| AnnaBridge | 167:e84263d55307 | 17235 | #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
| AnnaBridge | 167:e84263d55307 | 17236 | #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */ |
| AnnaBridge | 167:e84263d55307 | 17237 | #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */ |
| AnnaBridge | 167:e84263d55307 | 17238 | #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */ |
| AnnaBridge | 167:e84263d55307 | 17239 | #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */ |
| AnnaBridge | 167:e84263d55307 | 17240 | #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */ |
| AnnaBridge | 167:e84263d55307 | 17241 | #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */ |
| AnnaBridge | 167:e84263d55307 | 17242 | #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */ |
| <> | 144:ef7eb2e8f9f7 | 17243 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 17244 | #define WWDG_CR_T0 WWDG_CR_T_0 |
| <> | 144:ef7eb2e8f9f7 | 17245 | #define WWDG_CR_T1 WWDG_CR_T_1 |
| <> | 144:ef7eb2e8f9f7 | 17246 | #define WWDG_CR_T2 WWDG_CR_T_2 |
| <> | 144:ef7eb2e8f9f7 | 17247 | #define WWDG_CR_T3 WWDG_CR_T_3 |
| <> | 144:ef7eb2e8f9f7 | 17248 | #define WWDG_CR_T4 WWDG_CR_T_4 |
| <> | 144:ef7eb2e8f9f7 | 17249 | #define WWDG_CR_T5 WWDG_CR_T_5 |
| <> | 144:ef7eb2e8f9f7 | 17250 | #define WWDG_CR_T6 WWDG_CR_T_6 |
| <> | 144:ef7eb2e8f9f7 | 17251 | |
| AnnaBridge | 167:e84263d55307 | 17252 | #define WWDG_CR_WDGA_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 17253 | #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 17254 | #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ |
| mbed_official | 19:112740acecfa | 17255 | |
| mbed_official | 19:112740acecfa | 17256 | /******************* Bit definition for WWDG_CFR register *******************/ |
| AnnaBridge | 167:e84263d55307 | 17257 | #define WWDG_CFR_W_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17258 | #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ |
| AnnaBridge | 167:e84263d55307 | 17259 | #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ |
| AnnaBridge | 167:e84263d55307 | 17260 | #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */ |
| AnnaBridge | 167:e84263d55307 | 17261 | #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */ |
| AnnaBridge | 167:e84263d55307 | 17262 | #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */ |
| AnnaBridge | 167:e84263d55307 | 17263 | #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */ |
| AnnaBridge | 167:e84263d55307 | 17264 | #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */ |
| AnnaBridge | 167:e84263d55307 | 17265 | #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */ |
| AnnaBridge | 167:e84263d55307 | 17266 | #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */ |
| <> | 144:ef7eb2e8f9f7 | 17267 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 17268 | #define WWDG_CFR_W0 WWDG_CFR_W_0 |
| <> | 144:ef7eb2e8f9f7 | 17269 | #define WWDG_CFR_W1 WWDG_CFR_W_1 |
| <> | 144:ef7eb2e8f9f7 | 17270 | #define WWDG_CFR_W2 WWDG_CFR_W_2 |
| <> | 144:ef7eb2e8f9f7 | 17271 | #define WWDG_CFR_W3 WWDG_CFR_W_3 |
| <> | 144:ef7eb2e8f9f7 | 17272 | #define WWDG_CFR_W4 WWDG_CFR_W_4 |
| <> | 144:ef7eb2e8f9f7 | 17273 | #define WWDG_CFR_W5 WWDG_CFR_W_5 |
| <> | 144:ef7eb2e8f9f7 | 17274 | #define WWDG_CFR_W6 WWDG_CFR_W_6 |
| <> | 144:ef7eb2e8f9f7 | 17275 | |
| AnnaBridge | 167:e84263d55307 | 17276 | #define WWDG_CFR_WDGTB_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 17277 | #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ |
| AnnaBridge | 167:e84263d55307 | 17278 | #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */ |
| AnnaBridge | 167:e84263d55307 | 17279 | #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */ |
| AnnaBridge | 167:e84263d55307 | 17280 | #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */ |
| <> | 144:ef7eb2e8f9f7 | 17281 | /* Legacy defines */ |
| <> | 144:ef7eb2e8f9f7 | 17282 | #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
| <> | 144:ef7eb2e8f9f7 | 17283 | #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
| <> | 144:ef7eb2e8f9f7 | 17284 | |
| AnnaBridge | 167:e84263d55307 | 17285 | #define WWDG_CFR_EWI_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17286 | #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17287 | #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ |
| mbed_official | 19:112740acecfa | 17288 | |
| mbed_official | 19:112740acecfa | 17289 | /******************* Bit definition for WWDG_SR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 17290 | #define WWDG_SR_EWIF_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17291 | #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17292 | #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ |
| mbed_official | 19:112740acecfa | 17293 | |
| mbed_official | 19:112740acecfa | 17294 | |
| mbed_official | 19:112740acecfa | 17295 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17296 | /* */ |
| mbed_official | 19:112740acecfa | 17297 | /* DBG */ |
| mbed_official | 19:112740acecfa | 17298 | /* */ |
| mbed_official | 19:112740acecfa | 17299 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17300 | /******************** Bit definition for DBGMCU_IDCODE register *************/ |
| AnnaBridge | 167:e84263d55307 | 17301 | #define DBGMCU_IDCODE_DEV_ID_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17302 | #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 17303 | #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk |
| AnnaBridge | 167:e84263d55307 | 17304 | #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 17305 | #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 17306 | #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk |
| mbed_official | 19:112740acecfa | 17307 | |
| mbed_official | 19:112740acecfa | 17308 | /******************** Bit definition for DBGMCU_CR register *****************/ |
| AnnaBridge | 167:e84263d55307 | 17309 | #define DBGMCU_CR_DBG_SLEEP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17310 | #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17311 | #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk |
| AnnaBridge | 167:e84263d55307 | 17312 | #define DBGMCU_CR_DBG_STOP_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17313 | #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17314 | #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17315 | #define DBGMCU_CR_DBG_STANDBY_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17316 | #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17317 | #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk |
| AnnaBridge | 167:e84263d55307 | 17318 | #define DBGMCU_CR_TRACE_IOEN_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17319 | #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17320 | #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk |
| AnnaBridge | 167:e84263d55307 | 17321 | |
| AnnaBridge | 167:e84263d55307 | 17322 | #define DBGMCU_CR_TRACE_MODE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17323 | #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 17324 | #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk |
| AnnaBridge | 167:e84263d55307 | 17325 | #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17326 | #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ |
| mbed_official | 19:112740acecfa | 17327 | |
| mbed_official | 19:112740acecfa | 17328 | /******************** Bit definition for DBGMCU_APB1_FZ register ************/ |
| AnnaBridge | 167:e84263d55307 | 17329 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17330 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17331 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17332 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17333 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17334 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17335 | #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17336 | #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17337 | #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17338 | #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17339 | #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17340 | #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17341 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17342 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17343 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17344 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17345 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17346 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17347 | #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17348 | #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17349 | #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17350 | #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 17351 | #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 17352 | #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17353 | #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17354 | #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 17355 | #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17356 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 17357 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 17358 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17359 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 17360 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 17361 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17362 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 17363 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 17364 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17365 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 17366 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 17367 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk |
| AnnaBridge | 167:e84263d55307 | 17368 | #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 17369 | #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 17370 | #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk |
| AnnaBridge | 167:e84263d55307 | 17371 | #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 17372 | #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 17373 | #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk |
| AnnaBridge | 167:e84263d55307 | 17374 | #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 17375 | #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 17376 | #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk |
| AnnaBridge | 167:e84263d55307 | 17377 | #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 17378 | #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 17379 | #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17380 | #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 17381 | #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 17382 | #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk |
| mbed_official | 19:112740acecfa | 17383 | /* Old IWDGSTOP bit definition, maintained for legacy purpose */ |
| mbed_official | 19:112740acecfa | 17384 | #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP |
| mbed_official | 19:112740acecfa | 17385 | |
| mbed_official | 19:112740acecfa | 17386 | /******************** Bit definition for DBGMCU_APB2_FZ register ************/ |
| AnnaBridge | 167:e84263d55307 | 17387 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17388 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17389 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17390 | #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17391 | #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17392 | #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17393 | #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 17394 | #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 17395 | #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17396 | #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 17397 | #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 17398 | #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk |
| AnnaBridge | 167:e84263d55307 | 17399 | #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 17400 | #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 17401 | #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk |
| mbed_official | 19:112740acecfa | 17402 | |
| mbed_official | 19:112740acecfa | 17403 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17404 | /* */ |
| mbed_official | 19:112740acecfa | 17405 | /* Ethernet MAC Registers bits definitions */ |
| mbed_official | 19:112740acecfa | 17406 | /* */ |
| mbed_official | 19:112740acecfa | 17407 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17408 | /* Bit definition for Ethernet MAC Control Register register */ |
| AnnaBridge | 167:e84263d55307 | 17409 | #define ETH_MACCR_WD_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 17410 | #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 17411 | #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */ |
| AnnaBridge | 167:e84263d55307 | 17412 | #define ETH_MACCR_JD_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 17413 | #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 17414 | #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */ |
| AnnaBridge | 167:e84263d55307 | 17415 | #define ETH_MACCR_IFG_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 17416 | #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */ |
| AnnaBridge | 167:e84263d55307 | 17417 | #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */ |
| AnnaBridge | 167:e84263d55307 | 17418 | #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */ |
| AnnaBridge | 167:e84263d55307 | 17419 | #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */ |
| AnnaBridge | 167:e84263d55307 | 17420 | #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */ |
| AnnaBridge | 167:e84263d55307 | 17421 | #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */ |
| AnnaBridge | 167:e84263d55307 | 17422 | #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */ |
| AnnaBridge | 167:e84263d55307 | 17423 | #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */ |
| AnnaBridge | 167:e84263d55307 | 17424 | #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */ |
| AnnaBridge | 167:e84263d55307 | 17425 | #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */ |
| AnnaBridge | 167:e84263d55307 | 17426 | #define ETH_MACCR_CSD_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 17427 | #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 17428 | #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */ |
| AnnaBridge | 167:e84263d55307 | 17429 | #define ETH_MACCR_FES_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 17430 | #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 17431 | #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */ |
| AnnaBridge | 167:e84263d55307 | 17432 | #define ETH_MACCR_ROD_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 17433 | #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 17434 | #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */ |
| AnnaBridge | 167:e84263d55307 | 17435 | #define ETH_MACCR_LM_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 17436 | #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 17437 | #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */ |
| AnnaBridge | 167:e84263d55307 | 17438 | #define ETH_MACCR_DM_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 17439 | #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 17440 | #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */ |
| AnnaBridge | 167:e84263d55307 | 17441 | #define ETH_MACCR_IPCO_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 17442 | #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 17443 | #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */ |
| AnnaBridge | 167:e84263d55307 | 17444 | #define ETH_MACCR_RD_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17445 | #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17446 | #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */ |
| AnnaBridge | 167:e84263d55307 | 17447 | #define ETH_MACCR_APCS_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 17448 | #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 17449 | #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */ |
| AnnaBridge | 167:e84263d55307 | 17450 | #define ETH_MACCR_BL_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17451 | #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 167:e84263d55307 | 17452 | #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling |
| mbed_official | 19:112740acecfa | 17453 | a transmission attempt during retries after a collision: 0 =< r <2^k */ |
| AnnaBridge | 167:e84263d55307 | 17454 | #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */ |
| AnnaBridge | 167:e84263d55307 | 17455 | #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */ |
| AnnaBridge | 167:e84263d55307 | 17456 | #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */ |
| AnnaBridge | 167:e84263d55307 | 17457 | #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */ |
| AnnaBridge | 167:e84263d55307 | 17458 | #define ETH_MACCR_DC_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17459 | #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17460 | #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */ |
| AnnaBridge | 167:e84263d55307 | 17461 | #define ETH_MACCR_TE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17462 | #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17463 | #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */ |
| AnnaBridge | 167:e84263d55307 | 17464 | #define ETH_MACCR_RE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17465 | #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17466 | #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */ |
| mbed_official | 19:112740acecfa | 17467 | |
| mbed_official | 19:112740acecfa | 17468 | /* Bit definition for Ethernet MAC Frame Filter Register */ |
| AnnaBridge | 167:e84263d55307 | 17469 | #define ETH_MACFFR_RA_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 17470 | #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 17471 | #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */ |
| AnnaBridge | 167:e84263d55307 | 17472 | #define ETH_MACFFR_HPF_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 17473 | #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 17474 | #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */ |
| AnnaBridge | 167:e84263d55307 | 17475 | #define ETH_MACFFR_SAF_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17476 | #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17477 | #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */ |
| AnnaBridge | 167:e84263d55307 | 17478 | #define ETH_MACFFR_SAIF_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17479 | #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 17480 | #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */ |
| AnnaBridge | 167:e84263d55307 | 17481 | #define ETH_MACFFR_PCF_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17482 | #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 17483 | #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */ |
| AnnaBridge | 167:e84263d55307 | 17484 | #define ETH_MACFFR_PCF_BlockAll_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17485 | #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17486 | #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */ |
| AnnaBridge | 167:e84263d55307 | 17487 | #define ETH_MACFFR_PCF_ForwardAll_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 17488 | #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 17489 | #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */ |
| AnnaBridge | 167:e84263d55307 | 17490 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17491 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 167:e84263d55307 | 17492 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */ |
| AnnaBridge | 167:e84263d55307 | 17493 | #define ETH_MACFFR_BFD_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17494 | #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17495 | #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */ |
| AnnaBridge | 167:e84263d55307 | 17496 | #define ETH_MACFFR_PAM_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17497 | #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17498 | #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */ |
| AnnaBridge | 167:e84263d55307 | 17499 | #define ETH_MACFFR_DAIF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17500 | #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17501 | #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */ |
| AnnaBridge | 167:e84263d55307 | 17502 | #define ETH_MACFFR_HM_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17503 | #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17504 | #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */ |
| AnnaBridge | 167:e84263d55307 | 17505 | #define ETH_MACFFR_HU_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17506 | #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17507 | #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */ |
| AnnaBridge | 167:e84263d55307 | 17508 | #define ETH_MACFFR_PM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17509 | #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17510 | #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */ |
| mbed_official | 19:112740acecfa | 17511 | |
| mbed_official | 19:112740acecfa | 17512 | /* Bit definition for Ethernet MAC Hash Table High Register */ |
| AnnaBridge | 167:e84263d55307 | 17513 | #define ETH_MACHTHR_HTH_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17514 | #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17515 | #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */ |
| mbed_official | 19:112740acecfa | 17516 | |
| mbed_official | 19:112740acecfa | 17517 | /* Bit definition for Ethernet MAC Hash Table Low Register */ |
| AnnaBridge | 167:e84263d55307 | 17518 | #define ETH_MACHTLR_HTL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17519 | #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17520 | #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */ |
| mbed_official | 19:112740acecfa | 17521 | |
| mbed_official | 19:112740acecfa | 17522 | /* Bit definition for Ethernet MAC MII Address Register */ |
| AnnaBridge | 167:e84263d55307 | 17523 | #define ETH_MACMIIAR_PA_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 17524 | #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */ |
| AnnaBridge | 167:e84263d55307 | 17525 | #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */ |
| AnnaBridge | 167:e84263d55307 | 17526 | #define ETH_MACMIIAR_MR_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17527 | #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 167:e84263d55307 | 17528 | #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */ |
| AnnaBridge | 167:e84263d55307 | 17529 | #define ETH_MACMIIAR_CR_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17530 | #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */ |
| AnnaBridge | 167:e84263d55307 | 17531 | #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */ |
| AnnaBridge | 167:e84263d55307 | 17532 | #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ |
| AnnaBridge | 167:e84263d55307 | 17533 | #define ETH_MACMIIAR_CR_Div62_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17534 | #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17535 | #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ |
| AnnaBridge | 167:e84263d55307 | 17536 | #define ETH_MACMIIAR_CR_Div16_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17537 | #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17538 | #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
| AnnaBridge | 167:e84263d55307 | 17539 | #define ETH_MACMIIAR_CR_Div26_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17540 | #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 167:e84263d55307 | 17541 | #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
| AnnaBridge | 167:e84263d55307 | 17542 | #define ETH_MACMIIAR_CR_Div102_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17543 | #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17544 | #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ |
| AnnaBridge | 167:e84263d55307 | 17545 | #define ETH_MACMIIAR_MW_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17546 | #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17547 | #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */ |
| AnnaBridge | 167:e84263d55307 | 17548 | #define ETH_MACMIIAR_MB_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17549 | #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17550 | #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */ |
| AnnaBridge | 167:e84263d55307 | 17551 | |
| mbed_official | 19:112740acecfa | 17552 | /* Bit definition for Ethernet MAC MII Data Register */ |
| AnnaBridge | 167:e84263d55307 | 17553 | #define ETH_MACMIIDR_MD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17554 | #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 17555 | #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */ |
| mbed_official | 19:112740acecfa | 17556 | |
| mbed_official | 19:112740acecfa | 17557 | /* Bit definition for Ethernet MAC Flow Control Register */ |
| AnnaBridge | 167:e84263d55307 | 17558 | #define ETH_MACFCR_PT_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 17559 | #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 17560 | #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */ |
| AnnaBridge | 167:e84263d55307 | 17561 | #define ETH_MACFCR_ZQPD_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 17562 | #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 17563 | #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */ |
| AnnaBridge | 167:e84263d55307 | 17564 | #define ETH_MACFCR_PLT_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17565 | #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 17566 | #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */ |
| AnnaBridge | 167:e84263d55307 | 17567 | #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */ |
| AnnaBridge | 167:e84263d55307 | 17568 | #define ETH_MACFCR_PLT_Minus28_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17569 | #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17570 | #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */ |
| AnnaBridge | 167:e84263d55307 | 17571 | #define ETH_MACFCR_PLT_Minus144_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17572 | #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17573 | #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */ |
| AnnaBridge | 167:e84263d55307 | 17574 | #define ETH_MACFCR_PLT_Minus256_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17575 | #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 167:e84263d55307 | 17576 | #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */ |
| AnnaBridge | 167:e84263d55307 | 17577 | #define ETH_MACFCR_UPFD_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17578 | #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17579 | #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */ |
| AnnaBridge | 167:e84263d55307 | 17580 | #define ETH_MACFCR_RFCE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17581 | #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17582 | #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */ |
| AnnaBridge | 167:e84263d55307 | 17583 | #define ETH_MACFCR_TFCE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17584 | #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17585 | #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */ |
| AnnaBridge | 167:e84263d55307 | 17586 | #define ETH_MACFCR_FCBBPA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17587 | #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17588 | #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */ |
| mbed_official | 19:112740acecfa | 17589 | |
| mbed_official | 19:112740acecfa | 17590 | /* Bit definition for Ethernet MAC VLAN Tag Register */ |
| AnnaBridge | 167:e84263d55307 | 17591 | #define ETH_MACVLANTR_VLANTC_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 17592 | #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 17593 | #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */ |
| AnnaBridge | 167:e84263d55307 | 17594 | #define ETH_MACVLANTR_VLANTI_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17595 | #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 17596 | #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */ |
| mbed_official | 19:112740acecfa | 17597 | |
| mbed_official | 19:112740acecfa | 17598 | /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ |
| AnnaBridge | 167:e84263d55307 | 17599 | #define ETH_MACRWUFFR_D_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17600 | #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17601 | #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */ |
| mbed_official | 19:112740acecfa | 17602 | /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. |
| mbed_official | 19:112740acecfa | 17603 | Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ |
| mbed_official | 19:112740acecfa | 17604 | /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask |
| mbed_official | 19:112740acecfa | 17605 | Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask |
| mbed_official | 19:112740acecfa | 17606 | Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask |
| mbed_official | 19:112740acecfa | 17607 | Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask |
| mbed_official | 19:112740acecfa | 17608 | Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - |
| mbed_official | 19:112740acecfa | 17609 | RSVD - Filter1 Command - RSVD - Filter0 Command |
| mbed_official | 19:112740acecfa | 17610 | Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset |
| mbed_official | 19:112740acecfa | 17611 | Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 |
| mbed_official | 19:112740acecfa | 17612 | Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ |
| mbed_official | 19:112740acecfa | 17613 | |
| mbed_official | 19:112740acecfa | 17614 | /* Bit definition for Ethernet MAC PMT Control and Status Register */ |
| AnnaBridge | 167:e84263d55307 | 17615 | #define ETH_MACPMTCSR_WFFRPR_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 17616 | #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 17617 | #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */ |
| AnnaBridge | 167:e84263d55307 | 17618 | #define ETH_MACPMTCSR_GU_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17619 | #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17620 | #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */ |
| AnnaBridge | 167:e84263d55307 | 17621 | #define ETH_MACPMTCSR_WFR_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17622 | #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17623 | #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */ |
| AnnaBridge | 167:e84263d55307 | 17624 | #define ETH_MACPMTCSR_MPR_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17625 | #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17626 | #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */ |
| AnnaBridge | 167:e84263d55307 | 17627 | #define ETH_MACPMTCSR_WFE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17628 | #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17629 | #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */ |
| AnnaBridge | 167:e84263d55307 | 17630 | #define ETH_MACPMTCSR_MPE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17631 | #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17632 | #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */ |
| AnnaBridge | 167:e84263d55307 | 17633 | #define ETH_MACPMTCSR_PD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17634 | #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17635 | #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */ |
| AnnaBridge | 167:e84263d55307 | 17636 | |
| AnnaBridge | 167:e84263d55307 | 17637 | /* Bit definition for Ethernet MAC debug Register */ |
| AnnaBridge | 167:e84263d55307 | 17638 | #define ETH_MACDBGR_TFF_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 17639 | #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 17640 | #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */ |
| AnnaBridge | 167:e84263d55307 | 17641 | #define ETH_MACDBGR_TFNE_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 17642 | #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 17643 | #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */ |
| AnnaBridge | 167:e84263d55307 | 17644 | #define ETH_MACDBGR_TFWA_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 17645 | #define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 17646 | #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */ |
| AnnaBridge | 167:e84263d55307 | 17647 | #define ETH_MACDBGR_TFRS_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 17648 | #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 17649 | #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */ |
| AnnaBridge | 167:e84263d55307 | 17650 | #define ETH_MACDBGR_TFRS_WRITING_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 17651 | #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 17652 | #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */ |
| AnnaBridge | 167:e84263d55307 | 17653 | #define ETH_MACDBGR_TFRS_WAITING_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 17654 | #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 17655 | #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */ |
| AnnaBridge | 167:e84263d55307 | 17656 | #define ETH_MACDBGR_TFRS_READ_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 17657 | #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 17658 | #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */ |
| AnnaBridge | 167:e84263d55307 | 17659 | #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */ |
| AnnaBridge | 167:e84263d55307 | 17660 | #define ETH_MACDBGR_MTP_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 17661 | #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 17662 | #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */ |
| AnnaBridge | 167:e84263d55307 | 17663 | #define ETH_MACDBGR_MTFCS_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 17664 | #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */ |
| AnnaBridge | 167:e84263d55307 | 17665 | #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */ |
| AnnaBridge | 167:e84263d55307 | 17666 | #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 17667 | #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */ |
| AnnaBridge | 167:e84263d55307 | 17668 | #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */ |
| AnnaBridge | 167:e84263d55307 | 17669 | #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 17670 | #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 17671 | #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */ |
| AnnaBridge | 167:e84263d55307 | 17672 | #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 17673 | #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 17674 | #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */ |
| AnnaBridge | 167:e84263d55307 | 17675 | #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */ |
| AnnaBridge | 167:e84263d55307 | 17676 | #define ETH_MACDBGR_MMTEA_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 17677 | #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 17678 | #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */ |
| AnnaBridge | 167:e84263d55307 | 17679 | #define ETH_MACDBGR_RFFL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17680 | #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 17681 | #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */ |
| AnnaBridge | 167:e84263d55307 | 17682 | #define ETH_MACDBGR_RFFL_FULL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17683 | #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 167:e84263d55307 | 17684 | #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */ |
| AnnaBridge | 167:e84263d55307 | 17685 | #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17686 | #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17687 | #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */ |
| AnnaBridge | 167:e84263d55307 | 17688 | #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17689 | #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 17690 | #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */ |
| AnnaBridge | 167:e84263d55307 | 17691 | #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */ |
| AnnaBridge | 167:e84263d55307 | 17692 | #define ETH_MACDBGR_RFRCS_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17693 | #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 167:e84263d55307 | 17694 | #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */ |
| AnnaBridge | 167:e84263d55307 | 17695 | #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17696 | #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 167:e84263d55307 | 17697 | #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */ |
| AnnaBridge | 167:e84263d55307 | 17698 | #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17699 | #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17700 | #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */ |
| AnnaBridge | 167:e84263d55307 | 17701 | #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17702 | #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17703 | #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */ |
| AnnaBridge | 167:e84263d55307 | 17704 | #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */ |
| AnnaBridge | 167:e84263d55307 | 17705 | #define ETH_MACDBGR_RFWRA_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17706 | #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17707 | #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */ |
| AnnaBridge | 167:e84263d55307 | 17708 | #define ETH_MACDBGR_MSFRWCS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17709 | #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 167:e84263d55307 | 17710 | #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */ |
| AnnaBridge | 167:e84263d55307 | 17711 | #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17712 | #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17713 | #define ETH_MACDBGR_MMRPEA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17714 | #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17715 | #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */ |
| mbed_official | 19:112740acecfa | 17716 | |
| mbed_official | 19:112740acecfa | 17717 | /* Bit definition for Ethernet MAC Status Register */ |
| AnnaBridge | 167:e84263d55307 | 17718 | #define ETH_MACSR_TSTS_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17719 | #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17720 | #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */ |
| AnnaBridge | 167:e84263d55307 | 17721 | #define ETH_MACSR_MMCTS_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17722 | #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17723 | #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */ |
| AnnaBridge | 167:e84263d55307 | 17724 | #define ETH_MACSR_MMMCRS_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17725 | #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17726 | #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */ |
| AnnaBridge | 167:e84263d55307 | 17727 | #define ETH_MACSR_MMCS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17728 | #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17729 | #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */ |
| AnnaBridge | 167:e84263d55307 | 17730 | #define ETH_MACSR_PMTS_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17731 | #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17732 | #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */ |
| mbed_official | 19:112740acecfa | 17733 | |
| mbed_official | 19:112740acecfa | 17734 | /* Bit definition for Ethernet MAC Interrupt Mask Register */ |
| AnnaBridge | 167:e84263d55307 | 17735 | #define ETH_MACIMR_TSTIM_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17736 | #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17737 | #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 17738 | #define ETH_MACIMR_PMTIM_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17739 | #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17740 | #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */ |
| mbed_official | 19:112740acecfa | 17741 | |
| mbed_official | 19:112740acecfa | 17742 | /* Bit definition for Ethernet MAC Address0 High Register */ |
| AnnaBridge | 167:e84263d55307 | 17743 | #define ETH_MACA0HR_MACA0H_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17744 | #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 17745 | #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */ |
| mbed_official | 19:112740acecfa | 17746 | |
| mbed_official | 19:112740acecfa | 17747 | /* Bit definition for Ethernet MAC Address0 Low Register */ |
| AnnaBridge | 167:e84263d55307 | 17748 | #define ETH_MACA0LR_MACA0L_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17749 | #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17750 | #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */ |
| mbed_official | 19:112740acecfa | 17751 | |
| mbed_official | 19:112740acecfa | 17752 | /* Bit definition for Ethernet MAC Address1 High Register */ |
| AnnaBridge | 167:e84263d55307 | 17753 | #define ETH_MACA1HR_AE_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 17754 | #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 17755 | #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */ |
| AnnaBridge | 167:e84263d55307 | 17756 | #define ETH_MACA1HR_SA_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 17757 | #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 17758 | #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */ |
| AnnaBridge | 167:e84263d55307 | 17759 | #define ETH_MACA1HR_MBC_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 17760 | #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */ |
| AnnaBridge | 167:e84263d55307 | 17761 | #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
| AnnaBridge | 167:e84263d55307 | 17762 | #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
| AnnaBridge | 167:e84263d55307 | 17763 | #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
| AnnaBridge | 167:e84263d55307 | 17764 | #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
| AnnaBridge | 167:e84263d55307 | 17765 | #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
| AnnaBridge | 167:e84263d55307 | 17766 | #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
| AnnaBridge | 167:e84263d55307 | 17767 | #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */ |
| AnnaBridge | 167:e84263d55307 | 17768 | #define ETH_MACA1HR_MACA1H_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17769 | #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 17770 | #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */ |
| mbed_official | 19:112740acecfa | 17771 | |
| mbed_official | 19:112740acecfa | 17772 | /* Bit definition for Ethernet MAC Address1 Low Register */ |
| AnnaBridge | 167:e84263d55307 | 17773 | #define ETH_MACA1LR_MACA1L_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17774 | #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17775 | #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */ |
| mbed_official | 19:112740acecfa | 17776 | |
| mbed_official | 19:112740acecfa | 17777 | /* Bit definition for Ethernet MAC Address2 High Register */ |
| AnnaBridge | 167:e84263d55307 | 17778 | #define ETH_MACA2HR_AE_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 17779 | #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 17780 | #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */ |
| AnnaBridge | 167:e84263d55307 | 17781 | #define ETH_MACA2HR_SA_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 17782 | #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 17783 | #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */ |
| AnnaBridge | 167:e84263d55307 | 17784 | #define ETH_MACA2HR_MBC_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 17785 | #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */ |
| AnnaBridge | 167:e84263d55307 | 17786 | #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */ |
| AnnaBridge | 167:e84263d55307 | 17787 | #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
| AnnaBridge | 167:e84263d55307 | 17788 | #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
| AnnaBridge | 167:e84263d55307 | 17789 | #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
| AnnaBridge | 167:e84263d55307 | 17790 | #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
| AnnaBridge | 167:e84263d55307 | 17791 | #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
| AnnaBridge | 167:e84263d55307 | 17792 | #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ |
| AnnaBridge | 167:e84263d55307 | 17793 | #define ETH_MACA2HR_MACA2H_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17794 | #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 17795 | #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */ |
| mbed_official | 19:112740acecfa | 17796 | |
| mbed_official | 19:112740acecfa | 17797 | /* Bit definition for Ethernet MAC Address2 Low Register */ |
| AnnaBridge | 167:e84263d55307 | 17798 | #define ETH_MACA2LR_MACA2L_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17799 | #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17800 | #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */ |
| mbed_official | 19:112740acecfa | 17801 | |
| mbed_official | 19:112740acecfa | 17802 | /* Bit definition for Ethernet MAC Address3 High Register */ |
| AnnaBridge | 167:e84263d55307 | 17803 | #define ETH_MACA3HR_AE_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 17804 | #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 17805 | #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */ |
| AnnaBridge | 167:e84263d55307 | 17806 | #define ETH_MACA3HR_SA_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 17807 | #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 17808 | #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */ |
| AnnaBridge | 167:e84263d55307 | 17809 | #define ETH_MACA3HR_MBC_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 17810 | #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */ |
| AnnaBridge | 167:e84263d55307 | 17811 | #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */ |
| AnnaBridge | 167:e84263d55307 | 17812 | #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
| AnnaBridge | 167:e84263d55307 | 17813 | #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
| AnnaBridge | 167:e84263d55307 | 17814 | #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
| AnnaBridge | 167:e84263d55307 | 17815 | #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
| AnnaBridge | 167:e84263d55307 | 17816 | #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
| AnnaBridge | 167:e84263d55307 | 17817 | #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ |
| AnnaBridge | 167:e84263d55307 | 17818 | #define ETH_MACA3HR_MACA3H_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17819 | #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 17820 | #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */ |
| mbed_official | 19:112740acecfa | 17821 | |
| mbed_official | 19:112740acecfa | 17822 | /* Bit definition for Ethernet MAC Address3 Low Register */ |
| AnnaBridge | 167:e84263d55307 | 17823 | #define ETH_MACA3LR_MACA3L_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17824 | #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17825 | #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */ |
| mbed_official | 19:112740acecfa | 17826 | |
| mbed_official | 19:112740acecfa | 17827 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17828 | /* Ethernet MMC Registers bits definition */ |
| mbed_official | 19:112740acecfa | 17829 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17830 | |
| mbed_official | 19:112740acecfa | 17831 | /* Bit definition for Ethernet MMC Contol Register */ |
| AnnaBridge | 167:e84263d55307 | 17832 | #define ETH_MMCCR_MCFHP_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17833 | #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17834 | #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */ |
| AnnaBridge | 167:e84263d55307 | 17835 | #define ETH_MMCCR_MCP_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17836 | #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17837 | #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */ |
| AnnaBridge | 167:e84263d55307 | 17838 | #define ETH_MMCCR_MCF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17839 | #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17840 | #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */ |
| AnnaBridge | 167:e84263d55307 | 17841 | #define ETH_MMCCR_ROR_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17842 | #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17843 | #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */ |
| AnnaBridge | 167:e84263d55307 | 17844 | #define ETH_MMCCR_CSR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17845 | #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17846 | #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */ |
| AnnaBridge | 167:e84263d55307 | 17847 | #define ETH_MMCCR_CR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17848 | #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17849 | #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */ |
| mbed_official | 19:112740acecfa | 17850 | |
| mbed_official | 19:112740acecfa | 17851 | /* Bit definition for Ethernet MMC Receive Interrupt Register */ |
| AnnaBridge | 167:e84263d55307 | 17852 | #define ETH_MMCRIR_RGUFS_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 17853 | #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 17854 | #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */ |
| AnnaBridge | 167:e84263d55307 | 17855 | #define ETH_MMCRIR_RFAES_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17856 | #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17857 | #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */ |
| AnnaBridge | 167:e84263d55307 | 17858 | #define ETH_MMCRIR_RFCES_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17859 | #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17860 | #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */ |
| mbed_official | 19:112740acecfa | 17861 | |
| mbed_official | 19:112740acecfa | 17862 | /* Bit definition for Ethernet MMC Transmit Interrupt Register */ |
| AnnaBridge | 167:e84263d55307 | 17863 | #define ETH_MMCTIR_TGFS_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 17864 | #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 17865 | #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */ |
| AnnaBridge | 167:e84263d55307 | 17866 | #define ETH_MMCTIR_TGFMSCS_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 17867 | #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 17868 | #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */ |
| AnnaBridge | 167:e84263d55307 | 17869 | #define ETH_MMCTIR_TGFSCS_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 17870 | #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 17871 | #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */ |
| mbed_official | 19:112740acecfa | 17872 | |
| mbed_official | 19:112740acecfa | 17873 | /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ |
| AnnaBridge | 167:e84263d55307 | 17874 | #define ETH_MMCRIMR_RGUFM_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 17875 | #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 17876 | #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
| AnnaBridge | 167:e84263d55307 | 17877 | #define ETH_MMCRIMR_RFAEM_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 17878 | #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 17879 | #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
| AnnaBridge | 167:e84263d55307 | 17880 | #define ETH_MMCRIMR_RFCEM_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17881 | #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17882 | #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
| mbed_official | 19:112740acecfa | 17883 | |
| mbed_official | 19:112740acecfa | 17884 | /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ |
| AnnaBridge | 167:e84263d55307 | 17885 | #define ETH_MMCTIMR_TGFM_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 17886 | #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 17887 | #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
| AnnaBridge | 167:e84263d55307 | 17888 | #define ETH_MMCTIMR_TGFMSCM_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 17889 | #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 17890 | #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
| AnnaBridge | 167:e84263d55307 | 17891 | #define ETH_MMCTIMR_TGFSCM_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 17892 | #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 17893 | #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
| mbed_official | 19:112740acecfa | 17894 | |
| mbed_official | 19:112740acecfa | 17895 | /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ |
| AnnaBridge | 167:e84263d55307 | 17896 | #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17897 | #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17898 | #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
| mbed_official | 19:112740acecfa | 17899 | |
| mbed_official | 19:112740acecfa | 17900 | /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ |
| AnnaBridge | 167:e84263d55307 | 17901 | #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17902 | #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17903 | #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
| mbed_official | 19:112740acecfa | 17904 | |
| mbed_official | 19:112740acecfa | 17905 | /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ |
| AnnaBridge | 167:e84263d55307 | 17906 | #define ETH_MMCTGFCR_TGFC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17907 | #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17908 | #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */ |
| mbed_official | 19:112740acecfa | 17909 | |
| mbed_official | 19:112740acecfa | 17910 | /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ |
| AnnaBridge | 167:e84263d55307 | 17911 | #define ETH_MMCRFCECR_RFCEC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17912 | #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17913 | #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */ |
| mbed_official | 19:112740acecfa | 17914 | |
| mbed_official | 19:112740acecfa | 17915 | /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ |
| AnnaBridge | 167:e84263d55307 | 17916 | #define ETH_MMCRFAECR_RFAEC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17917 | #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17918 | #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */ |
| mbed_official | 19:112740acecfa | 17919 | |
| mbed_official | 19:112740acecfa | 17920 | /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ |
| AnnaBridge | 167:e84263d55307 | 17921 | #define ETH_MMCRGUFCR_RGUFC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17922 | #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17923 | #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */ |
| mbed_official | 19:112740acecfa | 17924 | |
| mbed_official | 19:112740acecfa | 17925 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17926 | /* Ethernet PTP Registers bits definition */ |
| mbed_official | 19:112740acecfa | 17927 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 17928 | |
| mbed_official | 19:112740acecfa | 17929 | /* Bit definition for Ethernet PTP Time Stamp Contol Register */ |
| AnnaBridge | 167:e84263d55307 | 17930 | #define ETH_PTPTSCR_TSCNT_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 17931 | #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 167:e84263d55307 | 17932 | #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */ |
| AnnaBridge | 167:e84263d55307 | 17933 | #define ETH_PTPTSSR_TSSMRME_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 17934 | #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 17935 | #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ |
| AnnaBridge | 167:e84263d55307 | 17936 | #define ETH_PTPTSSR_TSSEME_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 17937 | #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 17938 | #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */ |
| AnnaBridge | 167:e84263d55307 | 17939 | #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 17940 | #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 17941 | #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ |
| AnnaBridge | 167:e84263d55307 | 17942 | #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 17943 | #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 17944 | #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ |
| AnnaBridge | 167:e84263d55307 | 17945 | #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 17946 | #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 17947 | #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ |
| AnnaBridge | 167:e84263d55307 | 17948 | #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 17949 | #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 17950 | #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ |
| AnnaBridge | 167:e84263d55307 | 17951 | #define ETH_PTPTSSR_TSSSR_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 17952 | #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 17953 | #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ |
| AnnaBridge | 167:e84263d55307 | 17954 | #define ETH_PTPTSSR_TSSARFE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 17955 | #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 17956 | #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ |
| AnnaBridge | 167:e84263d55307 | 17957 | |
| AnnaBridge | 167:e84263d55307 | 17958 | #define ETH_PTPTSCR_TSARU_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 17959 | #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 17960 | #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */ |
| AnnaBridge | 167:e84263d55307 | 17961 | #define ETH_PTPTSCR_TSITE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 17962 | #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 17963 | #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */ |
| AnnaBridge | 167:e84263d55307 | 17964 | #define ETH_PTPTSCR_TSSTU_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 17965 | #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 17966 | #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */ |
| AnnaBridge | 167:e84263d55307 | 17967 | #define ETH_PTPTSCR_TSSTI_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 17968 | #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 17969 | #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */ |
| AnnaBridge | 167:e84263d55307 | 17970 | #define ETH_PTPTSCR_TSFCU_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 17971 | #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 17972 | #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */ |
| AnnaBridge | 167:e84263d55307 | 17973 | #define ETH_PTPTSCR_TSE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17974 | #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 17975 | #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */ |
| mbed_official | 19:112740acecfa | 17976 | |
| mbed_official | 19:112740acecfa | 17977 | /* Bit definition for Ethernet PTP Sub-Second Increment Register */ |
| AnnaBridge | 167:e84263d55307 | 17978 | #define ETH_PTPSSIR_STSSI_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17979 | #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 167:e84263d55307 | 17980 | #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */ |
| mbed_official | 19:112740acecfa | 17981 | |
| mbed_official | 19:112740acecfa | 17982 | /* Bit definition for Ethernet PTP Time Stamp High Register */ |
| AnnaBridge | 167:e84263d55307 | 17983 | #define ETH_PTPTSHR_STS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17984 | #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17985 | #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */ |
| mbed_official | 19:112740acecfa | 17986 | |
| mbed_official | 19:112740acecfa | 17987 | /* Bit definition for Ethernet PTP Time Stamp Low Register */ |
| AnnaBridge | 167:e84263d55307 | 17988 | #define ETH_PTPTSLR_STPNS_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 17989 | #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 17990 | #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */ |
| AnnaBridge | 167:e84263d55307 | 17991 | #define ETH_PTPTSLR_STSS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17992 | #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17993 | #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */ |
| mbed_official | 19:112740acecfa | 17994 | |
| mbed_official | 19:112740acecfa | 17995 | /* Bit definition for Ethernet PTP Time Stamp High Update Register */ |
| AnnaBridge | 167:e84263d55307 | 17996 | #define ETH_PTPTSHUR_TSUS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 17997 | #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 17998 | #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */ |
| mbed_official | 19:112740acecfa | 17999 | |
| mbed_official | 19:112740acecfa | 18000 | /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ |
| AnnaBridge | 167:e84263d55307 | 18001 | #define ETH_PTPTSLUR_TSUPNS_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 18002 | #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 18003 | #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */ |
| AnnaBridge | 167:e84263d55307 | 18004 | #define ETH_PTPTSLUR_TSUSS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18005 | #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18006 | #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */ |
| mbed_official | 19:112740acecfa | 18007 | |
| mbed_official | 19:112740acecfa | 18008 | /* Bit definition for Ethernet PTP Time Stamp Addend Register */ |
| AnnaBridge | 167:e84263d55307 | 18009 | #define ETH_PTPTSAR_TSA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18010 | #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18011 | #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */ |
| mbed_official | 19:112740acecfa | 18012 | |
| mbed_official | 19:112740acecfa | 18013 | /* Bit definition for Ethernet PTP Target Time High Register */ |
| AnnaBridge | 167:e84263d55307 | 18014 | #define ETH_PTPTTHR_TTSH_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18015 | #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18016 | #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */ |
| mbed_official | 19:112740acecfa | 18017 | |
| mbed_official | 19:112740acecfa | 18018 | /* Bit definition for Ethernet PTP Target Time Low Register */ |
| AnnaBridge | 167:e84263d55307 | 18019 | #define ETH_PTPTTLR_TTSL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18020 | #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18021 | #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */ |
| mbed_official | 19:112740acecfa | 18022 | |
| mbed_official | 19:112740acecfa | 18023 | /* Bit definition for Ethernet PTP Time Stamp Status Register */ |
| AnnaBridge | 167:e84263d55307 | 18024 | #define ETH_PTPTSSR_TSTTR_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 18025 | #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18026 | #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */ |
| AnnaBridge | 167:e84263d55307 | 18027 | #define ETH_PTPTSSR_TSSO_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18028 | #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18029 | #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ |
| mbed_official | 19:112740acecfa | 18030 | |
| mbed_official | 19:112740acecfa | 18031 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 18032 | /* Ethernet DMA Registers bits definition */ |
| mbed_official | 19:112740acecfa | 18033 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 18034 | |
| mbed_official | 19:112740acecfa | 18035 | /* Bit definition for Ethernet DMA Bus Mode Register */ |
| AnnaBridge | 167:e84263d55307 | 18036 | #define ETH_DMABMR_AAB_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 18037 | #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 18038 | #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */ |
| AnnaBridge | 167:e84263d55307 | 18039 | #define ETH_DMABMR_FPM_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 18040 | #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 18041 | #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */ |
| AnnaBridge | 167:e84263d55307 | 18042 | #define ETH_DMABMR_USP_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 18043 | #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 18044 | #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */ |
| AnnaBridge | 167:e84263d55307 | 18045 | #define ETH_DMABMR_RDP_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18046 | #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */ |
| AnnaBridge | 167:e84263d55307 | 18047 | #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */ |
| AnnaBridge | 167:e84263d55307 | 18048 | #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| AnnaBridge | 167:e84263d55307 | 18049 | #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| AnnaBridge | 167:e84263d55307 | 18050 | #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| AnnaBridge | 167:e84263d55307 | 18051 | #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| AnnaBridge | 167:e84263d55307 | 18052 | #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| AnnaBridge | 167:e84263d55307 | 18053 | #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| AnnaBridge | 167:e84263d55307 | 18054 | #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| AnnaBridge | 167:e84263d55307 | 18055 | #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| AnnaBridge | 167:e84263d55307 | 18056 | #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| AnnaBridge | 167:e84263d55307 | 18057 | #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| AnnaBridge | 167:e84263d55307 | 18058 | #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| AnnaBridge | 167:e84263d55307 | 18059 | #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| AnnaBridge | 167:e84263d55307 | 18060 | #define ETH_DMABMR_FB_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18061 | #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 18062 | #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */ |
| AnnaBridge | 167:e84263d55307 | 18063 | #define ETH_DMABMR_RTPR_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 18064 | #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 18065 | #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */ |
| AnnaBridge | 167:e84263d55307 | 18066 | #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */ |
| AnnaBridge | 167:e84263d55307 | 18067 | #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */ |
| AnnaBridge | 167:e84263d55307 | 18068 | #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */ |
| AnnaBridge | 167:e84263d55307 | 18069 | #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */ |
| AnnaBridge | 167:e84263d55307 | 18070 | #define ETH_DMABMR_PBL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18071 | #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */ |
| AnnaBridge | 167:e84263d55307 | 18072 | #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */ |
| AnnaBridge | 167:e84263d55307 | 18073 | #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| AnnaBridge | 167:e84263d55307 | 18074 | #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| AnnaBridge | 167:e84263d55307 | 18075 | #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| AnnaBridge | 167:e84263d55307 | 18076 | #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| AnnaBridge | 167:e84263d55307 | 18077 | #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| AnnaBridge | 167:e84263d55307 | 18078 | #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| AnnaBridge | 167:e84263d55307 | 18079 | #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| AnnaBridge | 167:e84263d55307 | 18080 | #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| AnnaBridge | 167:e84263d55307 | 18081 | #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| AnnaBridge | 167:e84263d55307 | 18082 | #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| AnnaBridge | 167:e84263d55307 | 18083 | #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| AnnaBridge | 167:e84263d55307 | 18084 | #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| AnnaBridge | 167:e84263d55307 | 18085 | #define ETH_DMABMR_EDE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 18086 | #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18087 | #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */ |
| AnnaBridge | 167:e84263d55307 | 18088 | #define ETH_DMABMR_DSL_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18089 | #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */ |
| AnnaBridge | 167:e84263d55307 | 18090 | #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */ |
| AnnaBridge | 167:e84263d55307 | 18091 | #define ETH_DMABMR_DA_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18092 | #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18093 | #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */ |
| AnnaBridge | 167:e84263d55307 | 18094 | #define ETH_DMABMR_SR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18095 | #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18096 | #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */ |
| mbed_official | 19:112740acecfa | 18097 | |
| mbed_official | 19:112740acecfa | 18098 | /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ |
| AnnaBridge | 167:e84263d55307 | 18099 | #define ETH_DMATPDR_TPD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18100 | #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18101 | #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */ |
| mbed_official | 19:112740acecfa | 18102 | |
| mbed_official | 19:112740acecfa | 18103 | /* Bit definition for Ethernet DMA Receive Poll Demand Register */ |
| AnnaBridge | 167:e84263d55307 | 18104 | #define ETH_DMARPDR_RPD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18105 | #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18106 | #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */ |
| mbed_official | 19:112740acecfa | 18107 | |
| mbed_official | 19:112740acecfa | 18108 | /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ |
| AnnaBridge | 167:e84263d55307 | 18109 | #define ETH_DMARDLAR_SRL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18110 | #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18111 | #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */ |
| mbed_official | 19:112740acecfa | 18112 | |
| mbed_official | 19:112740acecfa | 18113 | /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ |
| AnnaBridge | 167:e84263d55307 | 18114 | #define ETH_DMATDLAR_STL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18115 | #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18116 | #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */ |
| mbed_official | 19:112740acecfa | 18117 | |
| mbed_official | 19:112740acecfa | 18118 | /* Bit definition for Ethernet DMA Status Register */ |
| AnnaBridge | 167:e84263d55307 | 18119 | #define ETH_DMASR_TSTS_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 18120 | #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 18121 | #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */ |
| AnnaBridge | 167:e84263d55307 | 18122 | #define ETH_DMASR_PMTS_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 18123 | #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 18124 | #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */ |
| AnnaBridge | 167:e84263d55307 | 18125 | #define ETH_DMASR_MMCS_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 18126 | #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 18127 | #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */ |
| AnnaBridge | 167:e84263d55307 | 18128 | #define ETH_DMASR_EBS_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 18129 | #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */ |
| AnnaBridge | 167:e84263d55307 | 18130 | #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */ |
| mbed_official | 19:112740acecfa | 18131 | /* combination with EBS[2:0] for GetFlagStatus function */ |
| AnnaBridge | 167:e84263d55307 | 18132 | #define ETH_DMASR_EBS_DescAccess_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 18133 | #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 18134 | #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */ |
| AnnaBridge | 167:e84263d55307 | 18135 | #define ETH_DMASR_EBS_ReadTransf_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 18136 | #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 18137 | #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */ |
| AnnaBridge | 167:e84263d55307 | 18138 | #define ETH_DMASR_EBS_DataTransfTx_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 18139 | #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 18140 | #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */ |
| AnnaBridge | 167:e84263d55307 | 18141 | #define ETH_DMASR_TPS_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 18142 | #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */ |
| AnnaBridge | 167:e84263d55307 | 18143 | #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */ |
| AnnaBridge | 167:e84263d55307 | 18144 | #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */ |
| AnnaBridge | 167:e84263d55307 | 18145 | #define ETH_DMASR_TPS_Fetching_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 18146 | #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 18147 | #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */ |
| AnnaBridge | 167:e84263d55307 | 18148 | #define ETH_DMASR_TPS_Waiting_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 18149 | #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 18150 | #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */ |
| AnnaBridge | 167:e84263d55307 | 18151 | #define ETH_DMASR_TPS_Reading_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 18152 | #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 18153 | #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */ |
| AnnaBridge | 167:e84263d55307 | 18154 | #define ETH_DMASR_TPS_Suspended_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 18155 | #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 167:e84263d55307 | 18156 | #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */ |
| AnnaBridge | 167:e84263d55307 | 18157 | #define ETH_DMASR_TPS_Closing_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 18158 | #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */ |
| AnnaBridge | 167:e84263d55307 | 18159 | #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */ |
| AnnaBridge | 167:e84263d55307 | 18160 | #define ETH_DMASR_RPS_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18161 | #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */ |
| AnnaBridge | 167:e84263d55307 | 18162 | #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */ |
| AnnaBridge | 167:e84263d55307 | 18163 | #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */ |
| AnnaBridge | 167:e84263d55307 | 18164 | #define ETH_DMASR_RPS_Fetching_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18165 | #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 18166 | #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */ |
| AnnaBridge | 167:e84263d55307 | 18167 | #define ETH_DMASR_RPS_Waiting_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18168 | #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */ |
| AnnaBridge | 167:e84263d55307 | 18169 | #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */ |
| AnnaBridge | 167:e84263d55307 | 18170 | #define ETH_DMASR_RPS_Suspended_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 18171 | #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 18172 | #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */ |
| AnnaBridge | 167:e84263d55307 | 18173 | #define ETH_DMASR_RPS_Closing_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18174 | #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */ |
| AnnaBridge | 167:e84263d55307 | 18175 | #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ |
| AnnaBridge | 167:e84263d55307 | 18176 | #define ETH_DMASR_RPS_Queuing_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18177 | #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ |
| AnnaBridge | 167:e84263d55307 | 18178 | #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ |
| AnnaBridge | 167:e84263d55307 | 18179 | #define ETH_DMASR_NIS_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18180 | #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 18181 | #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ |
| AnnaBridge | 167:e84263d55307 | 18182 | #define ETH_DMASR_AIS_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 18183 | #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 18184 | #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */ |
| AnnaBridge | 167:e84263d55307 | 18185 | #define ETH_DMASR_ERS_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 18186 | #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 18187 | #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */ |
| AnnaBridge | 167:e84263d55307 | 18188 | #define ETH_DMASR_FBES_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 18189 | #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 18190 | #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */ |
| AnnaBridge | 167:e84263d55307 | 18191 | #define ETH_DMASR_ETS_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 18192 | #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 18193 | #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */ |
| AnnaBridge | 167:e84263d55307 | 18194 | #define ETH_DMASR_RWTS_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 18195 | #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 18196 | #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */ |
| AnnaBridge | 167:e84263d55307 | 18197 | #define ETH_DMASR_RPSS_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18198 | #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18199 | #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */ |
| AnnaBridge | 167:e84263d55307 | 18200 | #define ETH_DMASR_RBUS_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 18201 | #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18202 | #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */ |
| AnnaBridge | 167:e84263d55307 | 18203 | #define ETH_DMASR_RS_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 18204 | #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18205 | #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */ |
| AnnaBridge | 167:e84263d55307 | 18206 | #define ETH_DMASR_TUS_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 18207 | #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18208 | #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */ |
| AnnaBridge | 167:e84263d55307 | 18209 | #define ETH_DMASR_ROS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18210 | #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18211 | #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */ |
| AnnaBridge | 167:e84263d55307 | 18212 | #define ETH_DMASR_TJTS_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 18213 | #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 18214 | #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */ |
| AnnaBridge | 167:e84263d55307 | 18215 | #define ETH_DMASR_TBUS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18216 | #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18217 | #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */ |
| AnnaBridge | 167:e84263d55307 | 18218 | #define ETH_DMASR_TPSS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18219 | #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18220 | #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */ |
| AnnaBridge | 167:e84263d55307 | 18221 | #define ETH_DMASR_TS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18222 | #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18223 | #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */ |
| mbed_official | 19:112740acecfa | 18224 | |
| mbed_official | 19:112740acecfa | 18225 | /* Bit definition for Ethernet DMA Operation Mode Register */ |
| AnnaBridge | 167:e84263d55307 | 18226 | #define ETH_DMAOMR_DTCEFD_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 18227 | #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 18228 | #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */ |
| AnnaBridge | 167:e84263d55307 | 18229 | #define ETH_DMAOMR_RSF_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 18230 | #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 18231 | #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */ |
| AnnaBridge | 167:e84263d55307 | 18232 | #define ETH_DMAOMR_DFRF_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 18233 | #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 18234 | #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */ |
| AnnaBridge | 167:e84263d55307 | 18235 | #define ETH_DMAOMR_TSF_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 18236 | #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 18237 | #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */ |
| AnnaBridge | 167:e84263d55307 | 18238 | #define ETH_DMAOMR_FTF_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 18239 | #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 18240 | #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */ |
| AnnaBridge | 167:e84263d55307 | 18241 | #define ETH_DMAOMR_TTC_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 18242 | #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */ |
| AnnaBridge | 167:e84263d55307 | 18243 | #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */ |
| AnnaBridge | 167:e84263d55307 | 18244 | #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18245 | #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18246 | #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18247 | #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18248 | #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18249 | #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18250 | #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18251 | #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18252 | #define ETH_DMAOMR_ST_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 18253 | #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 18254 | #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */ |
| AnnaBridge | 167:e84263d55307 | 18255 | #define ETH_DMAOMR_FEF_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 18256 | #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18257 | #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */ |
| AnnaBridge | 167:e84263d55307 | 18258 | #define ETH_DMAOMR_FUGF_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 18259 | #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18260 | #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */ |
| AnnaBridge | 167:e84263d55307 | 18261 | #define ETH_DMAOMR_RTC_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 18262 | #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */ |
| AnnaBridge | 167:e84263d55307 | 18263 | #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */ |
| AnnaBridge | 167:e84263d55307 | 18264 | #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18265 | #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18266 | #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18267 | #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
| AnnaBridge | 167:e84263d55307 | 18268 | #define ETH_DMAOMR_OSF_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18269 | #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18270 | #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */ |
| AnnaBridge | 167:e84263d55307 | 18271 | #define ETH_DMAOMR_SR_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18272 | #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18273 | #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */ |
| mbed_official | 19:112740acecfa | 18274 | |
| mbed_official | 19:112740acecfa | 18275 | /* Bit definition for Ethernet DMA Interrupt Enable Register */ |
| AnnaBridge | 167:e84263d55307 | 18276 | #define ETH_DMAIER_NISE_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18277 | #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 18278 | #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */ |
| AnnaBridge | 167:e84263d55307 | 18279 | #define ETH_DMAIER_AISE_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 18280 | #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 18281 | #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */ |
| AnnaBridge | 167:e84263d55307 | 18282 | #define ETH_DMAIER_ERIE_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 18283 | #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 18284 | #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18285 | #define ETH_DMAIER_FBEIE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 18286 | #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 18287 | #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18288 | #define ETH_DMAIER_ETIE_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 18289 | #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 18290 | #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18291 | #define ETH_DMAIER_RWTIE_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 18292 | #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 18293 | #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18294 | #define ETH_DMAIER_RPSIE_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18295 | #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18296 | #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18297 | #define ETH_DMAIER_RBUIE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 18298 | #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18299 | #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18300 | #define ETH_DMAIER_RIE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 18301 | #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18302 | #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18303 | #define ETH_DMAIER_TUIE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 18304 | #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18305 | #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18306 | #define ETH_DMAIER_ROIE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18307 | #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18308 | #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18309 | #define ETH_DMAIER_TJTIE_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 18310 | #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 18311 | #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18312 | #define ETH_DMAIER_TBUIE_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18313 | #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18314 | #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18315 | #define ETH_DMAIER_TPSIE_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18316 | #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18317 | #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */ |
| AnnaBridge | 167:e84263d55307 | 18318 | #define ETH_DMAIER_TIE_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18319 | #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18320 | #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */ |
| mbed_official | 19:112740acecfa | 18321 | |
| mbed_official | 19:112740acecfa | 18322 | /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ |
| AnnaBridge | 167:e84263d55307 | 18323 | #define ETH_DMAMFBOCR_OFOC_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 18324 | #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 18325 | #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */ |
| AnnaBridge | 167:e84263d55307 | 18326 | #define ETH_DMAMFBOCR_MFA_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18327 | #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */ |
| AnnaBridge | 167:e84263d55307 | 18328 | #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */ |
| AnnaBridge | 167:e84263d55307 | 18329 | #define ETH_DMAMFBOCR_OMFC_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18330 | #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 18331 | #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */ |
| AnnaBridge | 167:e84263d55307 | 18332 | #define ETH_DMAMFBOCR_MFC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18333 | #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18334 | #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */ |
| mbed_official | 19:112740acecfa | 18335 | |
| mbed_official | 19:112740acecfa | 18336 | /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ |
| AnnaBridge | 167:e84263d55307 | 18337 | #define ETH_DMACHTDR_HTDAP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18338 | #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18339 | #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */ |
| mbed_official | 19:112740acecfa | 18340 | |
| mbed_official | 19:112740acecfa | 18341 | /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ |
| AnnaBridge | 167:e84263d55307 | 18342 | #define ETH_DMACHRDR_HRDAP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18343 | #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18344 | #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */ |
| mbed_official | 19:112740acecfa | 18345 | |
| mbed_official | 19:112740acecfa | 18346 | /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ |
| AnnaBridge | 167:e84263d55307 | 18347 | #define ETH_DMACHTBAR_HTBAP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18348 | #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18349 | #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */ |
| mbed_official | 19:112740acecfa | 18350 | |
| mbed_official | 19:112740acecfa | 18351 | /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ |
| AnnaBridge | 167:e84263d55307 | 18352 | #define ETH_DMACHRBAR_HRBAP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18353 | #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 18354 | #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */ |
| mbed_official | 19:112740acecfa | 18355 | |
| mbed_official | 19:112740acecfa | 18356 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 18357 | /* */ |
| mbed_official | 19:112740acecfa | 18358 | /* USB_OTG */ |
| mbed_official | 19:112740acecfa | 18359 | /* */ |
| mbed_official | 19:112740acecfa | 18360 | /******************************************************************************/ |
| AnnaBridge | 167:e84263d55307 | 18361 | /******************** Bit definition for USB_OTG_GOTGCTL register ***********/ |
| AnnaBridge | 167:e84263d55307 | 18362 | #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18363 | #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18364 | #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ |
| AnnaBridge | 167:e84263d55307 | 18365 | #define USB_OTG_GOTGCTL_SRQ_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18366 | #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18367 | #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ |
| AnnaBridge | 167:e84263d55307 | 18368 | #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18369 | #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18370 | #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ |
| AnnaBridge | 167:e84263d55307 | 18371 | #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 18372 | #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 18373 | #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ |
| AnnaBridge | 167:e84263d55307 | 18374 | #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18375 | #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18376 | #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ |
| AnnaBridge | 167:e84263d55307 | 18377 | #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 18378 | #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18379 | #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ |
| AnnaBridge | 167:e84263d55307 | 18380 | #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 18381 | #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18382 | #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ |
| AnnaBridge | 167:e84263d55307 | 18383 | #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 18384 | #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18385 | #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ |
| AnnaBridge | 167:e84263d55307 | 18386 | #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18387 | #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18388 | #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ |
| AnnaBridge | 167:e84263d55307 | 18389 | #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 18390 | #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 18391 | #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ |
| AnnaBridge | 167:e84263d55307 | 18392 | #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 18393 | #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 18394 | #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ |
| AnnaBridge | 167:e84263d55307 | 18395 | #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 18396 | #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 18397 | #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ |
| AnnaBridge | 167:e84263d55307 | 18398 | #define USB_OTG_GOTGCTL_EHEN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 18399 | #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 18400 | #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ |
| AnnaBridge | 167:e84263d55307 | 18401 | #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18402 | #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 18403 | #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ |
| AnnaBridge | 167:e84263d55307 | 18404 | #define USB_OTG_GOTGCTL_DBCT_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18405 | #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 18406 | #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ |
| AnnaBridge | 167:e84263d55307 | 18407 | #define USB_OTG_GOTGCTL_ASVLD_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 18408 | #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 18409 | #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ |
| AnnaBridge | 167:e84263d55307 | 18410 | #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 18411 | #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 18412 | #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */ |
| AnnaBridge | 167:e84263d55307 | 18413 | #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 18414 | #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 18415 | #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ |
| mbed_official | 19:112740acecfa | 18416 | |
| mbed_official | 19:112740acecfa | 18417 | /******************** Bit definition forUSB_OTG_HCFG register ********************/ |
| mbed_official | 19:112740acecfa | 18418 | |
| AnnaBridge | 167:e84263d55307 | 18419 | #define USB_OTG_HCFG_FSLSPCS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18420 | #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 18421 | #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ |
| AnnaBridge | 167:e84263d55307 | 18422 | #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18423 | #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18424 | #define USB_OTG_HCFG_FSLSS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18425 | #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18426 | #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ |
| AnnaBridge | 167:e84263d55307 | 18427 | |
| AnnaBridge | 167:e84263d55307 | 18428 | /******************** Bit definition for USB_OTG_DCFG register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18429 | |
| AnnaBridge | 167:e84263d55307 | 18430 | #define USB_OTG_DCFG_DSPD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18431 | #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 167:e84263d55307 | 18432 | #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ |
| AnnaBridge | 167:e84263d55307 | 18433 | #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18434 | #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18435 | #define USB_OTG_DCFG_NZLSOHSK_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18436 | #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18437 | #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ |
| AnnaBridge | 167:e84263d55307 | 18438 | |
| AnnaBridge | 167:e84263d55307 | 18439 | #define USB_OTG_DCFG_DAD_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18440 | #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ |
| AnnaBridge | 167:e84263d55307 | 18441 | #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ |
| AnnaBridge | 167:e84263d55307 | 18442 | #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18443 | #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18444 | #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18445 | #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18446 | #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18447 | #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 18448 | #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 18449 | |
| AnnaBridge | 167:e84263d55307 | 18450 | #define USB_OTG_DCFG_PFIVL_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 18451 | #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ |
| AnnaBridge | 167:e84263d55307 | 18452 | #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ |
| AnnaBridge | 167:e84263d55307 | 18453 | #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 18454 | #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 18455 | |
| AnnaBridge | 167:e84263d55307 | 18456 | #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 18457 | #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 167:e84263d55307 | 18458 | #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ |
| AnnaBridge | 167:e84263d55307 | 18459 | #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 18460 | #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 18461 | |
| AnnaBridge | 167:e84263d55307 | 18462 | /******************** Bit definition for USB_OTG_PCGCR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18463 | #define USB_OTG_PCGCR_STPPCLK_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18464 | #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18465 | #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ |
| AnnaBridge | 167:e84263d55307 | 18466 | #define USB_OTG_PCGCR_GATEHCLK_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18467 | #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18468 | #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ |
| AnnaBridge | 167:e84263d55307 | 18469 | #define USB_OTG_PCGCR_PHYSUSP_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18470 | #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18471 | #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ |
| AnnaBridge | 167:e84263d55307 | 18472 | |
| AnnaBridge | 167:e84263d55307 | 18473 | /******************** Bit definition for USB_OTG_GOTGINT register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18474 | #define USB_OTG_GOTGINT_SEDET_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18475 | #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18476 | #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ |
| AnnaBridge | 167:e84263d55307 | 18477 | #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18478 | #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18479 | #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ |
| AnnaBridge | 167:e84263d55307 | 18480 | #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 18481 | #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 18482 | #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ |
| AnnaBridge | 167:e84263d55307 | 18483 | #define USB_OTG_GOTGINT_HNGDET_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18484 | #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 18485 | #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ |
| AnnaBridge | 167:e84263d55307 | 18486 | #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 18487 | #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 18488 | #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ |
| AnnaBridge | 167:e84263d55307 | 18489 | #define USB_OTG_GOTGINT_DBCDNE_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 18490 | #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 18491 | #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ |
| AnnaBridge | 167:e84263d55307 | 18492 | #define USB_OTG_GOTGINT_IDCHNG_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 18493 | #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 18494 | #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */ |
| AnnaBridge | 167:e84263d55307 | 18495 | |
| AnnaBridge | 167:e84263d55307 | 18496 | /******************** Bit definition for USB_OTG_DCTL register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18497 | #define USB_OTG_DCTL_RWUSIG_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18498 | #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18499 | #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ |
| AnnaBridge | 167:e84263d55307 | 18500 | #define USB_OTG_DCTL_SDIS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18501 | #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18502 | #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ |
| AnnaBridge | 167:e84263d55307 | 18503 | #define USB_OTG_DCTL_GINSTS_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18504 | #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18505 | #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ |
| AnnaBridge | 167:e84263d55307 | 18506 | #define USB_OTG_DCTL_GONSTS_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 18507 | #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 18508 | #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ |
| AnnaBridge | 167:e84263d55307 | 18509 | |
| AnnaBridge | 167:e84263d55307 | 18510 | #define USB_OTG_DCTL_TCTL_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18511 | #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 167:e84263d55307 | 18512 | #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ |
| AnnaBridge | 167:e84263d55307 | 18513 | #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18514 | #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18515 | #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18516 | #define USB_OTG_DCTL_SGINAK_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 18517 | #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18518 | #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ |
| AnnaBridge | 167:e84263d55307 | 18519 | #define USB_OTG_DCTL_CGINAK_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18520 | #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18521 | #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ |
| AnnaBridge | 167:e84263d55307 | 18522 | #define USB_OTG_DCTL_SGONAK_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 18523 | #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 18524 | #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ |
| AnnaBridge | 167:e84263d55307 | 18525 | #define USB_OTG_DCTL_CGONAK_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 18526 | #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 18527 | #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ |
| AnnaBridge | 167:e84263d55307 | 18528 | #define USB_OTG_DCTL_POPRGDNE_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 18529 | #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 18530 | #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ |
| AnnaBridge | 167:e84263d55307 | 18531 | |
| AnnaBridge | 167:e84263d55307 | 18532 | /******************** Bit definition for USB_OTG_HFIR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18533 | #define USB_OTG_HFIR_FRIVL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18534 | #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18535 | #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ |
| AnnaBridge | 167:e84263d55307 | 18536 | |
| AnnaBridge | 167:e84263d55307 | 18537 | /******************** Bit definition for USB_OTG_HFNUM register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18538 | #define USB_OTG_HFNUM_FRNUM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18539 | #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18540 | #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ |
| AnnaBridge | 167:e84263d55307 | 18541 | #define USB_OTG_HFNUM_FTREM_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18542 | #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 18543 | #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ |
| AnnaBridge | 167:e84263d55307 | 18544 | |
| AnnaBridge | 167:e84263d55307 | 18545 | /******************** Bit definition for USB_OTG_DSTS register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18546 | #define USB_OTG_DSTS_SUSPSTS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18547 | #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18548 | #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ |
| AnnaBridge | 167:e84263d55307 | 18549 | |
| AnnaBridge | 167:e84263d55307 | 18550 | #define USB_OTG_DSTS_ENUMSPD_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18551 | #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 167:e84263d55307 | 18552 | #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ |
| AnnaBridge | 167:e84263d55307 | 18553 | #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18554 | #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18555 | #define USB_OTG_DSTS_EERR_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 18556 | #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 18557 | #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ |
| AnnaBridge | 167:e84263d55307 | 18558 | #define USB_OTG_DSTS_FNSOF_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18559 | #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ |
| AnnaBridge | 167:e84263d55307 | 18560 | #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ |
| AnnaBridge | 167:e84263d55307 | 18561 | |
| AnnaBridge | 167:e84263d55307 | 18562 | /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18563 | #define USB_OTG_GAHBCFG_GINT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18564 | #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18565 | #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18566 | #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18567 | #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ |
| AnnaBridge | 167:e84263d55307 | 18568 | #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ |
| AnnaBridge | 167:e84263d55307 | 18569 | #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ |
| AnnaBridge | 167:e84263d55307 | 18570 | #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ |
| AnnaBridge | 167:e84263d55307 | 18571 | #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ |
| AnnaBridge | 167:e84263d55307 | 18572 | #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ |
| AnnaBridge | 167:e84263d55307 | 18573 | #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ |
| AnnaBridge | 167:e84263d55307 | 18574 | #define USB_OTG_GAHBCFG_DMAEN_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 18575 | #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18576 | #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ |
| AnnaBridge | 167:e84263d55307 | 18577 | #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 18578 | #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18579 | #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ |
| AnnaBridge | 167:e84263d55307 | 18580 | #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18581 | #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18582 | #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ |
| AnnaBridge | 167:e84263d55307 | 18583 | |
| AnnaBridge | 167:e84263d55307 | 18584 | /******************** Bit definition for USB_OTG_GUSBCFG register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18585 | |
| AnnaBridge | 167:e84263d55307 | 18586 | #define USB_OTG_GUSBCFG_TOCAL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18587 | #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 167:e84263d55307 | 18588 | #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ |
| AnnaBridge | 167:e84263d55307 | 18589 | #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18590 | #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18591 | #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18592 | #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 18593 | #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18594 | #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ |
| AnnaBridge | 167:e84263d55307 | 18595 | #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18596 | #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18597 | #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ |
| AnnaBridge | 167:e84263d55307 | 18598 | #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 18599 | #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 18600 | #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ |
| AnnaBridge | 167:e84263d55307 | 18601 | #define USB_OTG_GUSBCFG_TRDT_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 18602 | #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ |
| AnnaBridge | 167:e84263d55307 | 18603 | #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ |
| AnnaBridge | 167:e84263d55307 | 18604 | #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 18605 | #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 18606 | #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 18607 | #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 18608 | #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 18609 | #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 18610 | #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ |
| AnnaBridge | 167:e84263d55307 | 18611 | #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18612 | #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 18613 | #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ |
| AnnaBridge | 167:e84263d55307 | 18614 | #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 18615 | #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 18616 | #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ |
| AnnaBridge | 167:e84263d55307 | 18617 | #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 18618 | #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 18619 | #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ |
| AnnaBridge | 167:e84263d55307 | 18620 | #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 18621 | #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 18622 | #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ |
| AnnaBridge | 167:e84263d55307 | 18623 | #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 18624 | #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 18625 | #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ |
| AnnaBridge | 167:e84263d55307 | 18626 | #define USB_OTG_GUSBCFG_TSDPS_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 18627 | #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 18628 | #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ |
| AnnaBridge | 167:e84263d55307 | 18629 | #define USB_OTG_GUSBCFG_PCCI_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 18630 | #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 18631 | #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ |
| AnnaBridge | 167:e84263d55307 | 18632 | #define USB_OTG_GUSBCFG_PTCI_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 18633 | #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 18634 | #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ |
| AnnaBridge | 167:e84263d55307 | 18635 | #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 18636 | #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 18637 | #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ |
| AnnaBridge | 167:e84263d55307 | 18638 | #define USB_OTG_GUSBCFG_FHMOD_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 18639 | #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 18640 | #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ |
| AnnaBridge | 167:e84263d55307 | 18641 | #define USB_OTG_GUSBCFG_FDMOD_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 18642 | #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 18643 | #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ |
| AnnaBridge | 167:e84263d55307 | 18644 | #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 18645 | #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 18646 | #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ |
| AnnaBridge | 167:e84263d55307 | 18647 | |
| AnnaBridge | 167:e84263d55307 | 18648 | /******************** Bit definition for USB_OTG_GRSTCTL register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18649 | #define USB_OTG_GRSTCTL_CSRST_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18650 | #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18651 | #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ |
| AnnaBridge | 167:e84263d55307 | 18652 | #define USB_OTG_GRSTCTL_HSRST_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18653 | #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18654 | #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ |
| AnnaBridge | 167:e84263d55307 | 18655 | #define USB_OTG_GRSTCTL_FCRST_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18656 | #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18657 | #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ |
| AnnaBridge | 167:e84263d55307 | 18658 | #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18659 | #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18660 | #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ |
| AnnaBridge | 167:e84263d55307 | 18661 | #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 18662 | #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18663 | #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ |
| AnnaBridge | 167:e84263d55307 | 18664 | |
| AnnaBridge | 167:e84263d55307 | 18665 | |
| AnnaBridge | 167:e84263d55307 | 18666 | #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 18667 | #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 167:e84263d55307 | 18668 | #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ |
| AnnaBridge | 167:e84263d55307 | 18669 | #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18670 | #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18671 | #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18672 | #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 18673 | #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 18674 | #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 18675 | #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 18676 | #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ |
| AnnaBridge | 167:e84263d55307 | 18677 | #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 18678 | #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 18679 | #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ |
| AnnaBridge | 167:e84263d55307 | 18680 | |
| AnnaBridge | 167:e84263d55307 | 18681 | /******************** Bit definition for USB_OTG_DIEPMSK register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18682 | #define USB_OTG_DIEPMSK_XFRCM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18683 | #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18684 | #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18685 | #define USB_OTG_DIEPMSK_EPDM_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18686 | #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18687 | #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18688 | #define USB_OTG_DIEPMSK_TOM_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 18689 | #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 18690 | #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ |
| AnnaBridge | 167:e84263d55307 | 18691 | #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18692 | #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18693 | #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
| AnnaBridge | 167:e84263d55307 | 18694 | #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 18695 | #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18696 | #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
| AnnaBridge | 167:e84263d55307 | 18697 | #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 18698 | #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18699 | #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
| AnnaBridge | 167:e84263d55307 | 18700 | #define USB_OTG_DIEPMSK_TXFURM_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18701 | #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18702 | #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ |
| AnnaBridge | 167:e84263d55307 | 18703 | #define USB_OTG_DIEPMSK_BIM_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 18704 | #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 18705 | #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18706 | |
| AnnaBridge | 167:e84263d55307 | 18707 | /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18708 | #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18709 | #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18710 | #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ |
| AnnaBridge | 167:e84263d55307 | 18711 | #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18712 | #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 18713 | #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ |
| AnnaBridge | 167:e84263d55307 | 18714 | #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 18715 | #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 18716 | #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 18717 | #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 18718 | #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 18719 | #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 18720 | #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 18721 | #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 18722 | |
| AnnaBridge | 167:e84263d55307 | 18723 | #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 18724 | #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 167:e84263d55307 | 18725 | #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ |
| AnnaBridge | 167:e84263d55307 | 18726 | #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 18727 | #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 18728 | #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 18729 | #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 18730 | #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 18731 | #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 18732 | #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 18733 | #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 18734 | |
| AnnaBridge | 167:e84263d55307 | 18735 | /******************** Bit definition for USB_OTG_HAINT register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18736 | #define USB_OTG_HAINT_HAINT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18737 | #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18738 | #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ |
| AnnaBridge | 167:e84263d55307 | 18739 | |
| AnnaBridge | 167:e84263d55307 | 18740 | /******************** Bit definition for USB_OTG_DOEPMSK register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18741 | #define USB_OTG_DOEPMSK_XFRCM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18742 | #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18743 | #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18744 | #define USB_OTG_DOEPMSK_EPDM_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18745 | #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18746 | #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18747 | #define USB_OTG_DOEPMSK_STUPM_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 18748 | #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 18749 | #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ |
| AnnaBridge | 167:e84263d55307 | 18750 | #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18751 | #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18752 | #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ |
| AnnaBridge | 167:e84263d55307 | 18753 | #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 18754 | #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18755 | #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ |
| AnnaBridge | 167:e84263d55307 | 18756 | #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 18757 | #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18758 | #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ |
| AnnaBridge | 167:e84263d55307 | 18759 | #define USB_OTG_DOEPMSK_OPEM_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 18760 | #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 18761 | #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ |
| AnnaBridge | 167:e84263d55307 | 18762 | #define USB_OTG_DOEPMSK_BOIM_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 18763 | #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 18764 | #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18765 | |
| AnnaBridge | 167:e84263d55307 | 18766 | /******************** Bit definition for USB_OTG_GINTSTS register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18767 | #define USB_OTG_GINTSTS_CMOD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18768 | #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 18769 | #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ |
| AnnaBridge | 167:e84263d55307 | 18770 | #define USB_OTG_GINTSTS_MMIS_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18771 | #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18772 | #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18773 | #define USB_OTG_GINTSTS_OTGINT_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18774 | #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18775 | #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18776 | #define USB_OTG_GINTSTS_SOF_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 18777 | #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 18778 | #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ |
| AnnaBridge | 167:e84263d55307 | 18779 | #define USB_OTG_GINTSTS_RXFLVL_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18780 | #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18781 | #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ |
| AnnaBridge | 167:e84263d55307 | 18782 | #define USB_OTG_GINTSTS_NPTXFE_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 18783 | #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18784 | #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ |
| AnnaBridge | 167:e84263d55307 | 18785 | #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 18786 | #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18787 | #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ |
| AnnaBridge | 167:e84263d55307 | 18788 | #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 18789 | #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18790 | #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ |
| AnnaBridge | 167:e84263d55307 | 18791 | #define USB_OTG_GINTSTS_ESUSP_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 18792 | #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 18793 | #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ |
| AnnaBridge | 167:e84263d55307 | 18794 | #define USB_OTG_GINTSTS_USBSUSP_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 18795 | #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 18796 | #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ |
| AnnaBridge | 167:e84263d55307 | 18797 | #define USB_OTG_GINTSTS_USBRST_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 18798 | #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 18799 | #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ |
| AnnaBridge | 167:e84263d55307 | 18800 | #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 18801 | #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 18802 | #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ |
| AnnaBridge | 167:e84263d55307 | 18803 | #define USB_OTG_GINTSTS_ISOODRP_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 18804 | #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 18805 | #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18806 | #define USB_OTG_GINTSTS_EOPF_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 18807 | #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 18808 | #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18809 | #define USB_OTG_GINTSTS_IEPINT_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 18810 | #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 18811 | #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18812 | #define USB_OTG_GINTSTS_OEPINT_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 18813 | #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 18814 | #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18815 | #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 18816 | #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 18817 | #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ |
| AnnaBridge | 167:e84263d55307 | 18818 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 18819 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 18820 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ |
| AnnaBridge | 167:e84263d55307 | 18821 | #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 18822 | #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 18823 | #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ |
| AnnaBridge | 167:e84263d55307 | 18824 | #define USB_OTG_GINTSTS_RSTDET_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 18825 | #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 18826 | #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18827 | #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 18828 | #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 18829 | #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18830 | #define USB_OTG_GINTSTS_HCINT_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 18831 | #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 18832 | #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18833 | #define USB_OTG_GINTSTS_PTXFE_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 18834 | #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 18835 | #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ |
| AnnaBridge | 167:e84263d55307 | 18836 | #define USB_OTG_GINTSTS_LPMINT_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 18837 | #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 18838 | #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18839 | #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 18840 | #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 18841 | #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ |
| AnnaBridge | 167:e84263d55307 | 18842 | #define USB_OTG_GINTSTS_DISCINT_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 18843 | #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 18844 | #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18845 | #define USB_OTG_GINTSTS_SRQINT_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 18846 | #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 18847 | #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18848 | #define USB_OTG_GINTSTS_WKUINT_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 18849 | #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 18850 | #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ |
| AnnaBridge | 167:e84263d55307 | 18851 | |
| AnnaBridge | 167:e84263d55307 | 18852 | /******************** Bit definition for USB_OTG_GINTMSK register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18853 | #define USB_OTG_GINTMSK_MMISM_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 18854 | #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 18855 | #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18856 | #define USB_OTG_GINTMSK_OTGINT_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 18857 | #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 18858 | #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18859 | #define USB_OTG_GINTMSK_SOFM_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 18860 | #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 18861 | #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ |
| AnnaBridge | 167:e84263d55307 | 18862 | #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18863 | #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 18864 | #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ |
| AnnaBridge | 167:e84263d55307 | 18865 | #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 18866 | #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 18867 | #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ |
| AnnaBridge | 167:e84263d55307 | 18868 | #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 18869 | #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 18870 | #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ |
| AnnaBridge | 167:e84263d55307 | 18871 | #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 18872 | #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 18873 | #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ |
| AnnaBridge | 167:e84263d55307 | 18874 | #define USB_OTG_GINTMSK_ESUSPM_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 18875 | #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 18876 | #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ |
| AnnaBridge | 167:e84263d55307 | 18877 | #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 18878 | #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 18879 | #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ |
| AnnaBridge | 167:e84263d55307 | 18880 | #define USB_OTG_GINTMSK_USBRST_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 18881 | #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 18882 | #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ |
| AnnaBridge | 167:e84263d55307 | 18883 | #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 18884 | #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 18885 | #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ |
| AnnaBridge | 167:e84263d55307 | 18886 | #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 18887 | #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 18888 | #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18889 | #define USB_OTG_GINTMSK_EOPFM_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 18890 | #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 18891 | #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18892 | #define USB_OTG_GINTMSK_EPMISM_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18893 | #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 18894 | #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18895 | #define USB_OTG_GINTMSK_IEPINT_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 18896 | #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 18897 | #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18898 | #define USB_OTG_GINTMSK_OEPINT_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 18899 | #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 18900 | #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18901 | #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 18902 | #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 18903 | #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ |
| AnnaBridge | 167:e84263d55307 | 18904 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 18905 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 18906 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ |
| AnnaBridge | 167:e84263d55307 | 18907 | #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 18908 | #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 18909 | #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ |
| AnnaBridge | 167:e84263d55307 | 18910 | #define USB_OTG_GINTMSK_RSTDEM_Pos (23U) |
| AnnaBridge | 167:e84263d55307 | 18911 | #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 18912 | #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18913 | #define USB_OTG_GINTMSK_PRTIM_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 18914 | #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 18915 | #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18916 | #define USB_OTG_GINTMSK_HCIM_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 18917 | #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 18918 | #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18919 | #define USB_OTG_GINTMSK_PTXFEM_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 18920 | #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 18921 | #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ |
| AnnaBridge | 167:e84263d55307 | 18922 | #define USB_OTG_GINTMSK_LPMINTM_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 18923 | #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 18924 | #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ |
| AnnaBridge | 167:e84263d55307 | 18925 | #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 18926 | #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 18927 | #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ |
| AnnaBridge | 167:e84263d55307 | 18928 | #define USB_OTG_GINTMSK_DISCINT_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 18929 | #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 18930 | #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18931 | #define USB_OTG_GINTMSK_SRQIM_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 18932 | #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 18933 | #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18934 | #define USB_OTG_GINTMSK_WUIM_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 18935 | #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 18936 | #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 18937 | |
| AnnaBridge | 167:e84263d55307 | 18938 | /******************** Bit definition for USB_OTG_DAINT register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18939 | #define USB_OTG_DAINT_IEPINT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18940 | #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18941 | #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ |
| AnnaBridge | 167:e84263d55307 | 18942 | #define USB_OTG_DAINT_OEPINT_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18943 | #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 18944 | #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ |
| AnnaBridge | 167:e84263d55307 | 18945 | |
| AnnaBridge | 167:e84263d55307 | 18946 | /******************** Bit definition for USB_OTG_HAINTMSK register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18947 | #define USB_OTG_HAINTMSK_HAINTM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18948 | #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18949 | #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ |
| mbed_official | 19:112740acecfa | 18950 | |
| mbed_official | 19:112740acecfa | 18951 | /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18952 | #define USB_OTG_GRXSTSP_EPNUM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18953 | #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 167:e84263d55307 | 18954 | #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ |
| AnnaBridge | 167:e84263d55307 | 18955 | #define USB_OTG_GRXSTSP_BCNT_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 18956 | #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ |
| AnnaBridge | 167:e84263d55307 | 18957 | #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ |
| AnnaBridge | 167:e84263d55307 | 18958 | #define USB_OTG_GRXSTSP_DPID_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 18959 | #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ |
| AnnaBridge | 167:e84263d55307 | 18960 | #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ |
| AnnaBridge | 167:e84263d55307 | 18961 | #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 18962 | #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ |
| AnnaBridge | 167:e84263d55307 | 18963 | #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ |
| AnnaBridge | 167:e84263d55307 | 18964 | |
| AnnaBridge | 167:e84263d55307 | 18965 | /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18966 | #define USB_OTG_DAINTMSK_IEPM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18967 | #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18968 | #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ |
| AnnaBridge | 167:e84263d55307 | 18969 | #define USB_OTG_DAINTMSK_OEPM_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18970 | #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 18971 | #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ |
| mbed_official | 19:112740acecfa | 18972 | |
| AnnaBridge | 167:e84263d55307 | 18973 | /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18974 | #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18975 | #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18976 | #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ |
| AnnaBridge | 167:e84263d55307 | 18977 | |
| AnnaBridge | 167:e84263d55307 | 18978 | /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18979 | #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18980 | #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18981 | #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ |
| mbed_official | 19:112740acecfa | 18982 | |
| mbed_official | 19:112740acecfa | 18983 | /******************** Bit definition for OTG register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18984 | #define USB_OTG_NPTXFSA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18985 | #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18986 | #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ |
| AnnaBridge | 167:e84263d55307 | 18987 | #define USB_OTG_NPTXFD_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18988 | #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 18989 | #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ |
| AnnaBridge | 167:e84263d55307 | 18990 | #define USB_OTG_TX0FSA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18991 | #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 18992 | #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ |
| AnnaBridge | 167:e84263d55307 | 18993 | #define USB_OTG_TX0FD_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 18994 | #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 18995 | #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ |
| mbed_official | 19:112740acecfa | 18996 | |
| mbed_official | 19:112740acecfa | 18997 | /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/ |
| AnnaBridge | 167:e84263d55307 | 18998 | #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 18999 | #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 167:e84263d55307 | 19000 | #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ |
| AnnaBridge | 167:e84263d55307 | 19001 | |
| AnnaBridge | 167:e84263d55307 | 19002 | /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19003 | #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19004 | #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 19005 | #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ |
| AnnaBridge | 167:e84263d55307 | 19006 | |
| AnnaBridge | 167:e84263d55307 | 19007 | #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 19008 | #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 167:e84263d55307 | 19009 | #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ |
| AnnaBridge | 167:e84263d55307 | 19010 | #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 19011 | #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 19012 | #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 19013 | #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 19014 | #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 19015 | #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 19016 | #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 19017 | #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 19018 | |
| AnnaBridge | 167:e84263d55307 | 19019 | #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 19020 | #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ |
| AnnaBridge | 167:e84263d55307 | 19021 | #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ |
| AnnaBridge | 167:e84263d55307 | 19022 | #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 19023 | #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 19024 | #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 19025 | #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 19026 | #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 19027 | #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 19028 | #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 19029 | |
| AnnaBridge | 167:e84263d55307 | 19030 | /******************** Bit definition for USB_OTG_DTHRCTL register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19031 | #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19032 | #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19033 | #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ |
| AnnaBridge | 167:e84263d55307 | 19034 | #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19035 | #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19036 | #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ |
| AnnaBridge | 167:e84263d55307 | 19037 | |
| AnnaBridge | 167:e84263d55307 | 19038 | #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 19039 | #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ |
| AnnaBridge | 167:e84263d55307 | 19040 | #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ |
| AnnaBridge | 167:e84263d55307 | 19041 | #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 19042 | #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 19043 | #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 19044 | #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 19045 | #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 19046 | #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 19047 | #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 19048 | #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 19049 | #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 19050 | #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 19051 | #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 19052 | #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ |
| AnnaBridge | 167:e84263d55307 | 19053 | |
| AnnaBridge | 167:e84263d55307 | 19054 | #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 19055 | #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ |
| AnnaBridge | 167:e84263d55307 | 19056 | #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ |
| AnnaBridge | 167:e84263d55307 | 19057 | #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 19058 | #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 19059 | #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 19060 | #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 19061 | #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 19062 | #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 19063 | #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 19064 | #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 19065 | #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 19066 | #define USB_OTG_DTHRCTL_ARPEN_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 19067 | #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 19068 | #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ |
| AnnaBridge | 167:e84263d55307 | 19069 | |
| AnnaBridge | 167:e84263d55307 | 19070 | /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19071 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19072 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 19073 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ |
| AnnaBridge | 167:e84263d55307 | 19074 | |
| AnnaBridge | 167:e84263d55307 | 19075 | /******************** Bit definition for USB_OTG_DEACHINT register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19076 | #define USB_OTG_DEACHINT_IEP1INT_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19077 | #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19078 | #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ |
| AnnaBridge | 167:e84263d55307 | 19079 | #define USB_OTG_DEACHINT_OEP1INT_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 19080 | #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 19081 | #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ |
| AnnaBridge | 167:e84263d55307 | 19082 | |
| AnnaBridge | 167:e84263d55307 | 19083 | /******************** Bit definition for USB_OTG_GCCFG register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19084 | #define USB_OTG_GCCFG_PWRDWN_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 19085 | #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 19086 | #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ |
| AnnaBridge | 167:e84263d55307 | 19087 | #define USB_OTG_GCCFG_VBDEN_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 19088 | #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 19089 | #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */ |
| mbed_official | 19:112740acecfa | 19090 | |
| mbed_official | 19:112740acecfa | 19091 | /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19092 | #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19093 | #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19094 | #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ |
| AnnaBridge | 167:e84263d55307 | 19095 | #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 19096 | #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 19097 | #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ |
| AnnaBridge | 167:e84263d55307 | 19098 | |
| AnnaBridge | 167:e84263d55307 | 19099 | /******************** Bit definition for USB_OTG_CID register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19100 | #define USB_OTG_CID_PRODUCT_ID_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19101 | #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 19102 | #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ |
| mbed_official | 19:112740acecfa | 19103 | |
| mbed_official | 19:112740acecfa | 19104 | /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19105 | #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19106 | #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19107 | #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */ |
| AnnaBridge | 167:e84263d55307 | 19108 | #define USB_OTG_GLPMCFG_LPMACK_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19109 | #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19110 | #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */ |
| AnnaBridge | 167:e84263d55307 | 19111 | #define USB_OTG_GLPMCFG_BESL_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 19112 | #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ |
| AnnaBridge | 167:e84263d55307 | 19113 | #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */ |
| AnnaBridge | 167:e84263d55307 | 19114 | #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 19115 | #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 19116 | #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */ |
| AnnaBridge | 167:e84263d55307 | 19117 | #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 19118 | #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 19119 | #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */ |
| AnnaBridge | 167:e84263d55307 | 19120 | #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 19121 | #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 167:e84263d55307 | 19122 | #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */ |
| AnnaBridge | 167:e84263d55307 | 19123 | #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 19124 | #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 19125 | #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */ |
| AnnaBridge | 167:e84263d55307 | 19126 | #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 19127 | #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ |
| AnnaBridge | 167:e84263d55307 | 19128 | #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */ |
| AnnaBridge | 167:e84263d55307 | 19129 | #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 19130 | #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 19131 | #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */ |
| AnnaBridge | 167:e84263d55307 | 19132 | #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 19133 | #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 19134 | #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */ |
| AnnaBridge | 167:e84263d55307 | 19135 | #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 19136 | #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ |
| AnnaBridge | 167:e84263d55307 | 19137 | #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */ |
| AnnaBridge | 167:e84263d55307 | 19138 | #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 19139 | #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ |
| AnnaBridge | 167:e84263d55307 | 19140 | #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */ |
| AnnaBridge | 167:e84263d55307 | 19141 | #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) |
| AnnaBridge | 167:e84263d55307 | 19142 | #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 19143 | #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */ |
| AnnaBridge | 167:e84263d55307 | 19144 | #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) |
| AnnaBridge | 167:e84263d55307 | 19145 | #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ |
| AnnaBridge | 167:e84263d55307 | 19146 | #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */ |
| AnnaBridge | 167:e84263d55307 | 19147 | #define USB_OTG_GLPMCFG_ENBESL_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 19148 | #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 19149 | #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */ |
| AnnaBridge | 167:e84263d55307 | 19150 | |
| AnnaBridge | 167:e84263d55307 | 19151 | /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19152 | #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19153 | #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19154 | #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19155 | #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19156 | #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19157 | #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19158 | #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 19159 | #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 19160 | #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ |
| AnnaBridge | 167:e84263d55307 | 19161 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 19162 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 19163 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
| AnnaBridge | 167:e84263d55307 | 19164 | #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 19165 | #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 19166 | #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
| AnnaBridge | 167:e84263d55307 | 19167 | #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 19168 | #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 19169 | #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
| AnnaBridge | 167:e84263d55307 | 19170 | #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 19171 | #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 19172 | #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ |
| AnnaBridge | 167:e84263d55307 | 19173 | #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 19174 | #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 19175 | #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19176 | #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 19177 | #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 19178 | #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19179 | |
| AnnaBridge | 167:e84263d55307 | 19180 | /******************** Bit definition for USB_OTG_HPRT register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19181 | #define USB_OTG_HPRT_PCSTS_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19182 | #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19183 | #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ |
| AnnaBridge | 167:e84263d55307 | 19184 | #define USB_OTG_HPRT_PCDET_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19185 | #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19186 | #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ |
| AnnaBridge | 167:e84263d55307 | 19187 | #define USB_OTG_HPRT_PENA_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 19188 | #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 19189 | #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ |
| AnnaBridge | 167:e84263d55307 | 19190 | #define USB_OTG_HPRT_PENCHNG_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 19191 | #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 19192 | #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ |
| AnnaBridge | 167:e84263d55307 | 19193 | #define USB_OTG_HPRT_POCA_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 19194 | #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 19195 | #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ |
| AnnaBridge | 167:e84263d55307 | 19196 | #define USB_OTG_HPRT_POCCHNG_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 19197 | #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 19198 | #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ |
| AnnaBridge | 167:e84263d55307 | 19199 | #define USB_OTG_HPRT_PRES_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 19200 | #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 19201 | #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ |
| AnnaBridge | 167:e84263d55307 | 19202 | #define USB_OTG_HPRT_PSUSP_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 19203 | #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 19204 | #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ |
| AnnaBridge | 167:e84263d55307 | 19205 | #define USB_OTG_HPRT_PRST_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 19206 | #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 19207 | #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ |
| AnnaBridge | 167:e84263d55307 | 19208 | |
| AnnaBridge | 167:e84263d55307 | 19209 | #define USB_OTG_HPRT_PLSTS_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 19210 | #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 167:e84263d55307 | 19211 | #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ |
| AnnaBridge | 167:e84263d55307 | 19212 | #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 19213 | #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 19214 | #define USB_OTG_HPRT_PPWR_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 19215 | #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 19216 | #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ |
| AnnaBridge | 167:e84263d55307 | 19217 | |
| AnnaBridge | 167:e84263d55307 | 19218 | #define USB_OTG_HPRT_PTCTL_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 19219 | #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ |
| AnnaBridge | 167:e84263d55307 | 19220 | #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ |
| AnnaBridge | 167:e84263d55307 | 19221 | #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 19222 | #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 19223 | #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 19224 | #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 19225 | |
| AnnaBridge | 167:e84263d55307 | 19226 | #define USB_OTG_HPRT_PSPD_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 19227 | #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ |
| AnnaBridge | 167:e84263d55307 | 19228 | #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ |
| AnnaBridge | 167:e84263d55307 | 19229 | #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 19230 | #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 19231 | |
| AnnaBridge | 167:e84263d55307 | 19232 | /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19233 | #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19234 | #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19235 | #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19236 | #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19237 | #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19238 | #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19239 | #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 19240 | #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 19241 | #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ |
| AnnaBridge | 167:e84263d55307 | 19242 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 19243 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 19244 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
| AnnaBridge | 167:e84263d55307 | 19245 | #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 19246 | #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 19247 | #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
| AnnaBridge | 167:e84263d55307 | 19248 | #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 19249 | #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 19250 | #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
| AnnaBridge | 167:e84263d55307 | 19251 | #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 19252 | #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 19253 | #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ |
| AnnaBridge | 167:e84263d55307 | 19254 | #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 19255 | #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 19256 | #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19257 | #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 19258 | #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 19259 | #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19260 | #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 19261 | #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 19262 | #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19263 | #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 19264 | #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 19265 | #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19266 | |
| AnnaBridge | 167:e84263d55307 | 19267 | /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19268 | #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19269 | #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 19270 | #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ |
| AnnaBridge | 167:e84263d55307 | 19271 | #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 19272 | #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 19273 | #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ |
| AnnaBridge | 167:e84263d55307 | 19274 | |
| AnnaBridge | 167:e84263d55307 | 19275 | /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19276 | #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19277 | #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 167:e84263d55307 | 19278 | #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ |
| AnnaBridge | 167:e84263d55307 | 19279 | #define USB_OTG_DIEPCTL_USBAEP_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 19280 | #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 19281 | #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ |
| AnnaBridge | 167:e84263d55307 | 19282 | #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 19283 | #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 19284 | #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ |
| AnnaBridge | 167:e84263d55307 | 19285 | #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 19286 | #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 19287 | #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ |
| AnnaBridge | 167:e84263d55307 | 19288 | |
| AnnaBridge | 167:e84263d55307 | 19289 | #define USB_OTG_DIEPCTL_EPTYP_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 19290 | #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 167:e84263d55307 | 19291 | #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ |
| AnnaBridge | 167:e84263d55307 | 19292 | #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 19293 | #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 19294 | #define USB_OTG_DIEPCTL_STALL_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 19295 | #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 19296 | #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ |
| AnnaBridge | 167:e84263d55307 | 19297 | |
| AnnaBridge | 167:e84263d55307 | 19298 | #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 19299 | #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ |
| AnnaBridge | 167:e84263d55307 | 19300 | #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ |
| AnnaBridge | 167:e84263d55307 | 19301 | #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 19302 | #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 19303 | #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 19304 | #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 19305 | #define USB_OTG_DIEPCTL_CNAK_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 19306 | #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 19307 | #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ |
| AnnaBridge | 167:e84263d55307 | 19308 | #define USB_OTG_DIEPCTL_SNAK_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 19309 | #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 19310 | #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ |
| AnnaBridge | 167:e84263d55307 | 19311 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 19312 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 19313 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ |
| AnnaBridge | 167:e84263d55307 | 19314 | #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 19315 | #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 19316 | #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ |
| AnnaBridge | 167:e84263d55307 | 19317 | #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 19318 | #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 19319 | #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ |
| AnnaBridge | 167:e84263d55307 | 19320 | #define USB_OTG_DIEPCTL_EPENA_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 19321 | #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 19322 | #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ |
| AnnaBridge | 167:e84263d55307 | 19323 | |
| AnnaBridge | 167:e84263d55307 | 19324 | /******************** Bit definition for USB_OTG_HCCHAR register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19325 | #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19326 | #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 167:e84263d55307 | 19327 | #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ |
| AnnaBridge | 167:e84263d55307 | 19328 | |
| AnnaBridge | 167:e84263d55307 | 19329 | #define USB_OTG_HCCHAR_EPNUM_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 19330 | #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ |
| AnnaBridge | 167:e84263d55307 | 19331 | #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ |
| AnnaBridge | 167:e84263d55307 | 19332 | #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 19333 | #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 19334 | #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 19335 | #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 19336 | #define USB_OTG_HCCHAR_EPDIR_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 19337 | #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 19338 | #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ |
| AnnaBridge | 167:e84263d55307 | 19339 | #define USB_OTG_HCCHAR_LSDEV_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 19340 | #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 19341 | #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ |
| AnnaBridge | 167:e84263d55307 | 19342 | |
| AnnaBridge | 167:e84263d55307 | 19343 | #define USB_OTG_HCCHAR_EPTYP_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 19344 | #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 167:e84263d55307 | 19345 | #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ |
| AnnaBridge | 167:e84263d55307 | 19346 | #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 19347 | #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 19348 | |
| AnnaBridge | 167:e84263d55307 | 19349 | #define USB_OTG_HCCHAR_MC_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 19350 | #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 167:e84263d55307 | 19351 | #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ |
| AnnaBridge | 167:e84263d55307 | 19352 | #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 19353 | #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 19354 | |
| AnnaBridge | 167:e84263d55307 | 19355 | #define USB_OTG_HCCHAR_DAD_Pos (22U) |
| AnnaBridge | 167:e84263d55307 | 19356 | #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ |
| AnnaBridge | 167:e84263d55307 | 19357 | #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ |
| AnnaBridge | 167:e84263d55307 | 19358 | #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 167:e84263d55307 | 19359 | #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 167:e84263d55307 | 19360 | #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 167:e84263d55307 | 19361 | #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 167:e84263d55307 | 19362 | #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 19363 | #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 19364 | #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 19365 | #define USB_OTG_HCCHAR_ODDFRM_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 19366 | #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 19367 | #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ |
| AnnaBridge | 167:e84263d55307 | 19368 | #define USB_OTG_HCCHAR_CHDIS_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 19369 | #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 19370 | #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ |
| AnnaBridge | 167:e84263d55307 | 19371 | #define USB_OTG_HCCHAR_CHENA_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 19372 | #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 19373 | #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ |
| AnnaBridge | 167:e84263d55307 | 19374 | |
| AnnaBridge | 167:e84263d55307 | 19375 | /******************** Bit definition for USB_OTG_HCSPLT register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19376 | |
| AnnaBridge | 167:e84263d55307 | 19377 | #define USB_OTG_HCSPLT_PRTADDR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19378 | #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ |
| AnnaBridge | 167:e84263d55307 | 19379 | #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ |
| AnnaBridge | 167:e84263d55307 | 19380 | #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19381 | #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19382 | #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 19383 | #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 19384 | #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 19385 | #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 19386 | #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 19387 | |
| AnnaBridge | 167:e84263d55307 | 19388 | #define USB_OTG_HCSPLT_HUBADDR_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 19389 | #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ |
| AnnaBridge | 167:e84263d55307 | 19390 | #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ |
| AnnaBridge | 167:e84263d55307 | 19391 | #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 19392 | #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 19393 | #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 19394 | #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 19395 | #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 19396 | #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 19397 | #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 19398 | |
| AnnaBridge | 167:e84263d55307 | 19399 | #define USB_OTG_HCSPLT_XACTPOS_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 19400 | #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 167:e84263d55307 | 19401 | #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ |
| AnnaBridge | 167:e84263d55307 | 19402 | #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 19403 | #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 19404 | #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 19405 | #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 167:e84263d55307 | 19406 | #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ |
| AnnaBridge | 167:e84263d55307 | 19407 | #define USB_OTG_HCSPLT_SPLITEN_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 19408 | #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 19409 | #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ |
| AnnaBridge | 167:e84263d55307 | 19410 | |
| AnnaBridge | 167:e84263d55307 | 19411 | /******************** Bit definition for USB_OTG_HCINT register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19412 | #define USB_OTG_HCINT_XFRC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19413 | #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19414 | #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ |
| AnnaBridge | 167:e84263d55307 | 19415 | #define USB_OTG_HCINT_CHH_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19416 | #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19417 | #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ |
| AnnaBridge | 167:e84263d55307 | 19418 | #define USB_OTG_HCINT_AHBERR_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 19419 | #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 19420 | #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ |
| AnnaBridge | 167:e84263d55307 | 19421 | #define USB_OTG_HCINT_STALL_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 19422 | #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 19423 | #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19424 | #define USB_OTG_HCINT_NAK_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 19425 | #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 19426 | #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19427 | #define USB_OTG_HCINT_ACK_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 19428 | #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 19429 | #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19430 | #define USB_OTG_HCINT_NYET_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 19431 | #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 19432 | #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19433 | #define USB_OTG_HCINT_TXERR_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 19434 | #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 19435 | #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ |
| AnnaBridge | 167:e84263d55307 | 19436 | #define USB_OTG_HCINT_BBERR_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 19437 | #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 19438 | #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ |
| AnnaBridge | 167:e84263d55307 | 19439 | #define USB_OTG_HCINT_FRMOR_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 19440 | #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 19441 | #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ |
| AnnaBridge | 167:e84263d55307 | 19442 | #define USB_OTG_HCINT_DTERR_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 19443 | #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 19444 | #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ |
| AnnaBridge | 167:e84263d55307 | 19445 | |
| AnnaBridge | 167:e84263d55307 | 19446 | /******************** Bit definition for USB_OTG_DIEPINT register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19447 | #define USB_OTG_DIEPINT_XFRC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19448 | #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19449 | #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19450 | #define USB_OTG_DIEPINT_EPDISD_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19451 | #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19452 | #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19453 | #define USB_OTG_DIEPINT_TOC_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 19454 | #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 19455 | #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ |
| AnnaBridge | 167:e84263d55307 | 19456 | #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 19457 | #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 19458 | #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ |
| AnnaBridge | 167:e84263d55307 | 19459 | #define USB_OTG_DIEPINT_INEPNE_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 19460 | #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 19461 | #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ |
| AnnaBridge | 167:e84263d55307 | 19462 | #define USB_OTG_DIEPINT_TXFE_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 19463 | #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 19464 | #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ |
| AnnaBridge | 167:e84263d55307 | 19465 | #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 19466 | #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 19467 | #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ |
| AnnaBridge | 167:e84263d55307 | 19468 | #define USB_OTG_DIEPINT_BNA_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 19469 | #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 19470 | #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19471 | #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) |
| AnnaBridge | 167:e84263d55307 | 19472 | #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 167:e84263d55307 | 19473 | #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ |
| AnnaBridge | 167:e84263d55307 | 19474 | #define USB_OTG_DIEPINT_BERR_Pos (12U) |
| AnnaBridge | 167:e84263d55307 | 19475 | #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 167:e84263d55307 | 19476 | #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19477 | #define USB_OTG_DIEPINT_NAK_Pos (13U) |
| AnnaBridge | 167:e84263d55307 | 19478 | #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 167:e84263d55307 | 19479 | #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ |
| mbed_official | 19:112740acecfa | 19480 | |
| mbed_official | 19:112740acecfa | 19481 | /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19482 | #define USB_OTG_HCINTMSK_XFRCM_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19483 | #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19484 | #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ |
| AnnaBridge | 167:e84263d55307 | 19485 | #define USB_OTG_HCINTMSK_CHHM_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19486 | #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19487 | #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ |
| AnnaBridge | 167:e84263d55307 | 19488 | #define USB_OTG_HCINTMSK_AHBERR_Pos (2U) |
| AnnaBridge | 167:e84263d55307 | 19489 | #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 167:e84263d55307 | 19490 | #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ |
| AnnaBridge | 167:e84263d55307 | 19491 | #define USB_OTG_HCINTMSK_STALLM_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 19492 | #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 19493 | #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19494 | #define USB_OTG_HCINTMSK_NAKM_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 19495 | #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 19496 | #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19497 | #define USB_OTG_HCINTMSK_ACKM_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 19498 | #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 19499 | #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19500 | #define USB_OTG_HCINTMSK_NYET_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 19501 | #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 19502 | #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ |
| AnnaBridge | 167:e84263d55307 | 19503 | #define USB_OTG_HCINTMSK_TXERRM_Pos (7U) |
| AnnaBridge | 167:e84263d55307 | 19504 | #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 167:e84263d55307 | 19505 | #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ |
| AnnaBridge | 167:e84263d55307 | 19506 | #define USB_OTG_HCINTMSK_BBERRM_Pos (8U) |
| AnnaBridge | 167:e84263d55307 | 19507 | #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 167:e84263d55307 | 19508 | #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ |
| AnnaBridge | 167:e84263d55307 | 19509 | #define USB_OTG_HCINTMSK_FRMORM_Pos (9U) |
| AnnaBridge | 167:e84263d55307 | 19510 | #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 167:e84263d55307 | 19511 | #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ |
| AnnaBridge | 167:e84263d55307 | 19512 | #define USB_OTG_HCINTMSK_DTERRM_Pos (10U) |
| AnnaBridge | 167:e84263d55307 | 19513 | #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 167:e84263d55307 | 19514 | #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ |
| mbed_official | 19:112740acecfa | 19515 | |
| mbed_official | 19:112740acecfa | 19516 | /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ |
| mbed_official | 19:112740acecfa | 19517 | |
| AnnaBridge | 167:e84263d55307 | 19518 | #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19519 | #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 167:e84263d55307 | 19520 | #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
| AnnaBridge | 167:e84263d55307 | 19521 | #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 19522 | #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
| AnnaBridge | 167:e84263d55307 | 19523 | #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ |
| AnnaBridge | 167:e84263d55307 | 19524 | #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 19525 | #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ |
| AnnaBridge | 167:e84263d55307 | 19526 | #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ |
| AnnaBridge | 167:e84263d55307 | 19527 | /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19528 | #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19529 | #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 167:e84263d55307 | 19530 | #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
| AnnaBridge | 167:e84263d55307 | 19531 | #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 19532 | #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
| AnnaBridge | 167:e84263d55307 | 19533 | #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ |
| AnnaBridge | 167:e84263d55307 | 19534 | #define USB_OTG_HCTSIZ_DOPING_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 19535 | #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 19536 | #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ |
| AnnaBridge | 167:e84263d55307 | 19537 | #define USB_OTG_HCTSIZ_DPID_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 19538 | #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ |
| AnnaBridge | 167:e84263d55307 | 19539 | #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ |
| AnnaBridge | 167:e84263d55307 | 19540 | #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 19541 | #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 19542 | |
| AnnaBridge | 167:e84263d55307 | 19543 | /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19544 | #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19545 | #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 19546 | #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ |
| AnnaBridge | 167:e84263d55307 | 19547 | |
| AnnaBridge | 167:e84263d55307 | 19548 | /******************** Bit definition for USB_OTG_HCDMA register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19549 | #define USB_OTG_HCDMA_DMAADDR_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19550 | #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 167:e84263d55307 | 19551 | #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ |
| AnnaBridge | 167:e84263d55307 | 19552 | |
| AnnaBridge | 167:e84263d55307 | 19553 | /******************** Bit definition for USB_OTG_DTXFSTS register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19554 | #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19555 | #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 19556 | #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ |
| AnnaBridge | 167:e84263d55307 | 19557 | |
| AnnaBridge | 167:e84263d55307 | 19558 | /******************** Bit definition for USB_OTG_DIEPTXF register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19559 | #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19560 | #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 167:e84263d55307 | 19561 | #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ |
| AnnaBridge | 167:e84263d55307 | 19562 | #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) |
| AnnaBridge | 167:e84263d55307 | 19563 | #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 167:e84263d55307 | 19564 | #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ |
| AnnaBridge | 167:e84263d55307 | 19565 | |
| AnnaBridge | 167:e84263d55307 | 19566 | /******************** Bit definition for USB_OTG_DOEPCTL register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19567 | |
| AnnaBridge | 167:e84263d55307 | 19568 | #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19569 | #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 167:e84263d55307 | 19570 | #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */ |
| AnnaBridge | 167:e84263d55307 | 19571 | #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) |
| AnnaBridge | 167:e84263d55307 | 19572 | #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 167:e84263d55307 | 19573 | #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ |
| AnnaBridge | 167:e84263d55307 | 19574 | #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) |
| AnnaBridge | 167:e84263d55307 | 19575 | #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 167:e84263d55307 | 19576 | #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ |
| AnnaBridge | 167:e84263d55307 | 19577 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) |
| AnnaBridge | 167:e84263d55307 | 19578 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 167:e84263d55307 | 19579 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ |
| AnnaBridge | 167:e84263d55307 | 19580 | #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 19581 | #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 19582 | #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ |
| AnnaBridge | 167:e84263d55307 | 19583 | #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) |
| AnnaBridge | 167:e84263d55307 | 19584 | #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 167:e84263d55307 | 19585 | #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ |
| AnnaBridge | 167:e84263d55307 | 19586 | #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 167:e84263d55307 | 19587 | #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 167:e84263d55307 | 19588 | #define USB_OTG_DOEPCTL_SNPM_Pos (20U) |
| AnnaBridge | 167:e84263d55307 | 19589 | #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 167:e84263d55307 | 19590 | #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */ |
| AnnaBridge | 167:e84263d55307 | 19591 | #define USB_OTG_DOEPCTL_STALL_Pos (21U) |
| AnnaBridge | 167:e84263d55307 | 19592 | #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 167:e84263d55307 | 19593 | #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */ |
| AnnaBridge | 167:e84263d55307 | 19594 | #define USB_OTG_DOEPCTL_CNAK_Pos (26U) |
| AnnaBridge | 167:e84263d55307 | 19595 | #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 167:e84263d55307 | 19596 | #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */ |
| AnnaBridge | 167:e84263d55307 | 19597 | #define USB_OTG_DOEPCTL_SNAK_Pos (27U) |
| AnnaBridge | 167:e84263d55307 | 19598 | #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 167:e84263d55307 | 19599 | #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ |
| AnnaBridge | 167:e84263d55307 | 19600 | #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) |
| AnnaBridge | 167:e84263d55307 | 19601 | #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 167:e84263d55307 | 19602 | #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ |
| AnnaBridge | 167:e84263d55307 | 19603 | #define USB_OTG_DOEPCTL_EPENA_Pos (31U) |
| AnnaBridge | 167:e84263d55307 | 19604 | #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 167:e84263d55307 | 19605 | #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */ |
| AnnaBridge | 167:e84263d55307 | 19606 | |
| AnnaBridge | 167:e84263d55307 | 19607 | /******************** Bit definition for USB_OTG_DOEPINT register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19608 | #define USB_OTG_DOEPINT_XFRC_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19609 | #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19610 | #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19611 | #define USB_OTG_DOEPINT_EPDISD_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19612 | #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19613 | #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19614 | #define USB_OTG_DOEPINT_STUP_Pos (3U) |
| AnnaBridge | 167:e84263d55307 | 19615 | #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 167:e84263d55307 | 19616 | #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ |
| AnnaBridge | 167:e84263d55307 | 19617 | #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 19618 | #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 19619 | #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ |
| AnnaBridge | 167:e84263d55307 | 19620 | #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U) |
| AnnaBridge | 167:e84263d55307 | 19621 | #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 167:e84263d55307 | 19622 | #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */ |
| AnnaBridge | 167:e84263d55307 | 19623 | #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) |
| AnnaBridge | 167:e84263d55307 | 19624 | #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 167:e84263d55307 | 19625 | #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ |
| AnnaBridge | 167:e84263d55307 | 19626 | #define USB_OTG_DOEPINT_NYET_Pos (14U) |
| AnnaBridge | 167:e84263d55307 | 19627 | #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 167:e84263d55307 | 19628 | #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ |
| AnnaBridge | 167:e84263d55307 | 19629 | |
| AnnaBridge | 167:e84263d55307 | 19630 | /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19631 | |
| AnnaBridge | 167:e84263d55307 | 19632 | #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19633 | #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 167:e84263d55307 | 19634 | #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
| AnnaBridge | 167:e84263d55307 | 19635 | #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) |
| AnnaBridge | 167:e84263d55307 | 19636 | #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
| AnnaBridge | 167:e84263d55307 | 19637 | #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ |
| AnnaBridge | 167:e84263d55307 | 19638 | |
| AnnaBridge | 167:e84263d55307 | 19639 | #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) |
| AnnaBridge | 167:e84263d55307 | 19640 | #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ |
| AnnaBridge | 167:e84263d55307 | 19641 | #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ |
| AnnaBridge | 167:e84263d55307 | 19642 | #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 167:e84263d55307 | 19643 | #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ |
| mbed_official | 19:112740acecfa | 19644 | |
| mbed_official | 19:112740acecfa | 19645 | /******************** Bit definition for PCGCCTL register ********************/ |
| AnnaBridge | 167:e84263d55307 | 19646 | #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) |
| AnnaBridge | 167:e84263d55307 | 19647 | #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 167:e84263d55307 | 19648 | #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ |
| AnnaBridge | 167:e84263d55307 | 19649 | #define USB_OTG_PCGCCTL_GATECLK_Pos (1U) |
| AnnaBridge | 167:e84263d55307 | 19650 | #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 167:e84263d55307 | 19651 | #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */ |
| AnnaBridge | 167:e84263d55307 | 19652 | #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) |
| AnnaBridge | 167:e84263d55307 | 19653 | #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 167:e84263d55307 | 19654 | #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ |
| mbed_official | 19:112740acecfa | 19655 | |
| AnnaBridge | 182:a56a73fd2a6f | 19656 | /* Legacy define */ |
| AnnaBridge | 182:a56a73fd2a6f | 19657 | /******************** Bit definition for OTG register ********************/ |
| AnnaBridge | 182:a56a73fd2a6f | 19658 | #define USB_OTG_CHNUM_Pos (0U) |
| AnnaBridge | 182:a56a73fd2a6f | 19659 | #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 182:a56a73fd2a6f | 19660 | #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ |
| AnnaBridge | 182:a56a73fd2a6f | 19661 | #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19662 | #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19663 | #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19664 | #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19665 | #define USB_OTG_BCNT_Pos (4U) |
| AnnaBridge | 182:a56a73fd2a6f | 19666 | #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19667 | #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ |
| AnnaBridge | 182:a56a73fd2a6f | 19668 | |
| AnnaBridge | 182:a56a73fd2a6f | 19669 | #define USB_OTG_DPID_Pos (15U) |
| AnnaBridge | 182:a56a73fd2a6f | 19670 | #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19671 | #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ |
| AnnaBridge | 182:a56a73fd2a6f | 19672 | #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19673 | #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19674 | |
| AnnaBridge | 182:a56a73fd2a6f | 19675 | #define USB_OTG_PKTSTS_Pos (17U) |
| AnnaBridge | 182:a56a73fd2a6f | 19676 | #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19677 | #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ |
| AnnaBridge | 182:a56a73fd2a6f | 19678 | #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19679 | #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19680 | #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19681 | #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19682 | |
| AnnaBridge | 182:a56a73fd2a6f | 19683 | #define USB_OTG_EPNUM_Pos (0U) |
| AnnaBridge | 182:a56a73fd2a6f | 19684 | #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 182:a56a73fd2a6f | 19685 | #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ |
| AnnaBridge | 182:a56a73fd2a6f | 19686 | #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19687 | #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19688 | #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19689 | #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19690 | |
| AnnaBridge | 182:a56a73fd2a6f | 19691 | #define USB_OTG_FRMNUM_Pos (21U) |
| AnnaBridge | 182:a56a73fd2a6f | 19692 | #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19693 | #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ |
| AnnaBridge | 182:a56a73fd2a6f | 19694 | #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19695 | #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19696 | #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 182:a56a73fd2a6f | 19697 | #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ |
| mbed_official | 19:112740acecfa | 19698 | /** |
| mbed_official | 19:112740acecfa | 19699 | * @} |
| mbed_official | 19:112740acecfa | 19700 | */ |
| mbed_official | 19:112740acecfa | 19701 | |
| mbed_official | 19:112740acecfa | 19702 | /** |
| mbed_official | 19:112740acecfa | 19703 | * @} |
| mbed_official | 19:112740acecfa | 19704 | */ |
| mbed_official | 19:112740acecfa | 19705 | |
| mbed_official | 19:112740acecfa | 19706 | /** @addtogroup Exported_macros |
| mbed_official | 19:112740acecfa | 19707 | * @{ |
| mbed_official | 19:112740acecfa | 19708 | */ |
| mbed_official | 19:112740acecfa | 19709 | |
| mbed_official | 19:112740acecfa | 19710 | /******************************* ADC Instances ********************************/ |
| mbed_official | 19:112740acecfa | 19711 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
| mbed_official | 19:112740acecfa | 19712 | ((INSTANCE) == ADC2) || \ |
| mbed_official | 19:112740acecfa | 19713 | ((INSTANCE) == ADC3)) |
| mbed_official | 19:112740acecfa | 19714 | |
| AnnaBridge | 167:e84263d55307 | 19715 | #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| AnnaBridge | 167:e84263d55307 | 19716 | |
| AnnaBridge | 167:e84263d55307 | 19717 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON) |
| AnnaBridge | 167:e84263d55307 | 19718 | |
| mbed_official | 19:112740acecfa | 19719 | /******************************* CAN Instances ********************************/ |
| mbed_official | 19:112740acecfa | 19720 | #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \ |
| mbed_official | 19:112740acecfa | 19721 | ((INSTANCE) == CAN2)) |
| mbed_official | 19:112740acecfa | 19722 | /******************************* CRC Instances ********************************/ |
| mbed_official | 19:112740acecfa | 19723 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| mbed_official | 19:112740acecfa | 19724 | |
| mbed_official | 19:112740acecfa | 19725 | /******************************* DAC Instances ********************************/ |
| AnnaBridge | 167:e84263d55307 | 19726 | #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| mbed_official | 19:112740acecfa | 19727 | |
| mbed_official | 19:112740acecfa | 19728 | /******************************* DCMI Instances *******************************/ |
| mbed_official | 19:112740acecfa | 19729 | #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI) |
| mbed_official | 19:112740acecfa | 19730 | |
| mbed_official | 19:112740acecfa | 19731 | /******************************* DMA2D Instances *******************************/ |
| mbed_official | 19:112740acecfa | 19732 | #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D) |
| mbed_official | 19:112740acecfa | 19733 | |
| mbed_official | 19:112740acecfa | 19734 | /******************************** DMA Instances *******************************/ |
| mbed_official | 19:112740acecfa | 19735 | #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \ |
| mbed_official | 19:112740acecfa | 19736 | ((INSTANCE) == DMA1_Stream1) || \ |
| mbed_official | 19:112740acecfa | 19737 | ((INSTANCE) == DMA1_Stream2) || \ |
| mbed_official | 19:112740acecfa | 19738 | ((INSTANCE) == DMA1_Stream3) || \ |
| mbed_official | 19:112740acecfa | 19739 | ((INSTANCE) == DMA1_Stream4) || \ |
| mbed_official | 19:112740acecfa | 19740 | ((INSTANCE) == DMA1_Stream5) || \ |
| mbed_official | 19:112740acecfa | 19741 | ((INSTANCE) == DMA1_Stream6) || \ |
| mbed_official | 19:112740acecfa | 19742 | ((INSTANCE) == DMA1_Stream7) || \ |
| mbed_official | 19:112740acecfa | 19743 | ((INSTANCE) == DMA2_Stream0) || \ |
| mbed_official | 19:112740acecfa | 19744 | ((INSTANCE) == DMA2_Stream1) || \ |
| mbed_official | 19:112740acecfa | 19745 | ((INSTANCE) == DMA2_Stream2) || \ |
| mbed_official | 19:112740acecfa | 19746 | ((INSTANCE) == DMA2_Stream3) || \ |
| mbed_official | 19:112740acecfa | 19747 | ((INSTANCE) == DMA2_Stream4) || \ |
| mbed_official | 19:112740acecfa | 19748 | ((INSTANCE) == DMA2_Stream5) || \ |
| mbed_official | 19:112740acecfa | 19749 | ((INSTANCE) == DMA2_Stream6) || \ |
| mbed_official | 19:112740acecfa | 19750 | ((INSTANCE) == DMA2_Stream7)) |
| mbed_official | 19:112740acecfa | 19751 | |
| mbed_official | 19:112740acecfa | 19752 | /******************************* GPIO Instances *******************************/ |
| mbed_official | 19:112740acecfa | 19753 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
| mbed_official | 19:112740acecfa | 19754 | ((INSTANCE) == GPIOB) || \ |
| mbed_official | 19:112740acecfa | 19755 | ((INSTANCE) == GPIOC) || \ |
| mbed_official | 19:112740acecfa | 19756 | ((INSTANCE) == GPIOD) || \ |
| mbed_official | 19:112740acecfa | 19757 | ((INSTANCE) == GPIOE) || \ |
| mbed_official | 19:112740acecfa | 19758 | ((INSTANCE) == GPIOF) || \ |
| mbed_official | 19:112740acecfa | 19759 | ((INSTANCE) == GPIOG) || \ |
| mbed_official | 19:112740acecfa | 19760 | ((INSTANCE) == GPIOH) || \ |
| mbed_official | 19:112740acecfa | 19761 | ((INSTANCE) == GPIOI) || \ |
| mbed_official | 19:112740acecfa | 19762 | ((INSTANCE) == GPIOJ) || \ |
| mbed_official | 19:112740acecfa | 19763 | ((INSTANCE) == GPIOK)) |
| mbed_official | 19:112740acecfa | 19764 | |
| mbed_official | 19:112740acecfa | 19765 | /******************************** I2C Instances *******************************/ |
| mbed_official | 19:112740acecfa | 19766 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
| mbed_official | 19:112740acecfa | 19767 | ((INSTANCE) == I2C2) || \ |
| mbed_official | 19:112740acecfa | 19768 | ((INSTANCE) == I2C3)) |
| mbed_official | 19:112740acecfa | 19769 | |
| AnnaBridge | 167:e84263d55307 | 19770 | /******************************* SMBUS Instances ******************************/ |
| AnnaBridge | 167:e84263d55307 | 19771 | #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE |
| AnnaBridge | 167:e84263d55307 | 19772 | |
| mbed_official | 19:112740acecfa | 19773 | /******************************** I2S Instances *******************************/ |
| AnnaBridge | 167:e84263d55307 | 19774 | |
| mbed_official | 19:112740acecfa | 19775 | #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ |
| AnnaBridge | 167:e84263d55307 | 19776 | ((INSTANCE) == SPI3)) |
| mbed_official | 19:112740acecfa | 19777 | |
| mbed_official | 19:112740acecfa | 19778 | /*************************** I2S Extended Instances ***************************/ |
| AnnaBridge | 167:e84263d55307 | 19779 | #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \ |
| AnnaBridge | 167:e84263d55307 | 19780 | ((INSTANCE) == I2S3ext)) |
| AnnaBridge | 167:e84263d55307 | 19781 | /* Legacy Defines */ |
| AnnaBridge | 167:e84263d55307 | 19782 | #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE |
| mbed_official | 19:112740acecfa | 19783 | |
| mbed_official | 19:112740acecfa | 19784 | /****************************** LTDC Instances ********************************/ |
| mbed_official | 19:112740acecfa | 19785 | #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| mbed_official | 19:112740acecfa | 19786 | /******************************* RNG Instances ********************************/ |
| mbed_official | 19:112740acecfa | 19787 | #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| mbed_official | 19:112740acecfa | 19788 | |
| mbed_official | 19:112740acecfa | 19789 | /****************************** RTC Instances *********************************/ |
| mbed_official | 19:112740acecfa | 19790 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| mbed_official | 19:112740acecfa | 19791 | |
| mbed_official | 19:112740acecfa | 19792 | /******************************* SAI Instances ********************************/ |
| <> | 144:ef7eb2e8f9f7 | 19793 | #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \ |
| mbed_official | 19:112740acecfa | 19794 | ((PERIPH) == SAI1_Block_B)) |
| <> | 144:ef7eb2e8f9f7 | 19795 | /* Legacy define */ |
| AnnaBridge | 167:e84263d55307 | 19796 | |
| <> | 144:ef7eb2e8f9f7 | 19797 | #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE |
| mbed_official | 19:112740acecfa | 19798 | |
| mbed_official | 19:112740acecfa | 19799 | /******************************** SPI Instances *******************************/ |
| AnnaBridge | 167:e84263d55307 | 19800 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
| AnnaBridge | 167:e84263d55307 | 19801 | ((INSTANCE) == SPI2) || \ |
| AnnaBridge | 167:e84263d55307 | 19802 | ((INSTANCE) == SPI3) || \ |
| AnnaBridge | 167:e84263d55307 | 19803 | ((INSTANCE) == SPI4) || \ |
| AnnaBridge | 167:e84263d55307 | 19804 | ((INSTANCE) == SPI5) || \ |
| mbed_official | 19:112740acecfa | 19805 | ((INSTANCE) == SPI6)) |
| mbed_official | 19:112740acecfa | 19806 | |
| mbed_official | 19:112740acecfa | 19807 | |
| mbed_official | 19:112740acecfa | 19808 | /****************** TIM Instances : All supported instances *******************/ |
| AnnaBridge | 167:e84263d55307 | 19809 | #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 19810 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 167:e84263d55307 | 19811 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 167:e84263d55307 | 19812 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 167:e84263d55307 | 19813 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 167:e84263d55307 | 19814 | ((INSTANCE) == TIM6) || \ |
| AnnaBridge | 167:e84263d55307 | 19815 | ((INSTANCE) == TIM7) || \ |
| AnnaBridge | 167:e84263d55307 | 19816 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 167:e84263d55307 | 19817 | ((INSTANCE) == TIM9) || \ |
| AnnaBridge | 167:e84263d55307 | 19818 | ((INSTANCE) == TIM10)|| \ |
| AnnaBridge | 167:e84263d55307 | 19819 | ((INSTANCE) == TIM11)|| \ |
| AnnaBridge | 167:e84263d55307 | 19820 | ((INSTANCE) == TIM12)|| \ |
| AnnaBridge | 167:e84263d55307 | 19821 | ((INSTANCE) == TIM13)|| \ |
| AnnaBridge | 167:e84263d55307 | 19822 | ((INSTANCE) == TIM14)) |
| mbed_official | 19:112740acecfa | 19823 | |
| mbed_official | 19:112740acecfa | 19824 | /************* TIM Instances : at least 1 capture/compare channel *************/ |
| mbed_official | 19:112740acecfa | 19825 | #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19826 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19827 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19828 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19829 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19830 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 19:112740acecfa | 19831 | ((INSTANCE) == TIM9) || \ |
| mbed_official | 19:112740acecfa | 19832 | ((INSTANCE) == TIM10) || \ |
| mbed_official | 19:112740acecfa | 19833 | ((INSTANCE) == TIM11) || \ |
| mbed_official | 19:112740acecfa | 19834 | ((INSTANCE) == TIM12) || \ |
| mbed_official | 19:112740acecfa | 19835 | ((INSTANCE) == TIM13) || \ |
| mbed_official | 19:112740acecfa | 19836 | ((INSTANCE) == TIM14)) |
| mbed_official | 19:112740acecfa | 19837 | |
| mbed_official | 19:112740acecfa | 19838 | /************ TIM Instances : at least 2 capture/compare channels *************/ |
| mbed_official | 19:112740acecfa | 19839 | #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19840 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19841 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19842 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19843 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19844 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 19:112740acecfa | 19845 | ((INSTANCE) == TIM9) || \ |
| AnnaBridge | 167:e84263d55307 | 19846 | ((INSTANCE) == TIM12)) |
| mbed_official | 19:112740acecfa | 19847 | |
| mbed_official | 19:112740acecfa | 19848 | /************ TIM Instances : at least 3 capture/compare channels *************/ |
| mbed_official | 19:112740acecfa | 19849 | #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19850 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19851 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19852 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19853 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19854 | ((INSTANCE) == TIM8)) |
| mbed_official | 19:112740acecfa | 19855 | |
| mbed_official | 19:112740acecfa | 19856 | /************ TIM Instances : at least 4 capture/compare channels *************/ |
| mbed_official | 19:112740acecfa | 19857 | #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19858 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19859 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19860 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19861 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19862 | ((INSTANCE) == TIM8)) |
| mbed_official | 19:112740acecfa | 19863 | |
| mbed_official | 19:112740acecfa | 19864 | /******************** TIM Instances : Advanced-control timers *****************/ |
| mbed_official | 19:112740acecfa | 19865 | #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 19866 | ((INSTANCE) == TIM8)) |
| mbed_official | 19:112740acecfa | 19867 | |
| mbed_official | 19:112740acecfa | 19868 | /******************* TIM Instances : Timer input XOR function *****************/ |
| mbed_official | 19:112740acecfa | 19869 | #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19870 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19871 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19872 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19873 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19874 | ((INSTANCE) == TIM8)) |
| mbed_official | 19:112740acecfa | 19875 | |
| mbed_official | 19:112740acecfa | 19876 | /****************** TIM Instances : DMA requests generation (UDE) *************/ |
| mbed_official | 19:112740acecfa | 19877 | #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19878 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19879 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19880 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19881 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19882 | ((INSTANCE) == TIM6) || \ |
| mbed_official | 19:112740acecfa | 19883 | ((INSTANCE) == TIM7) || \ |
| mbed_official | 19:112740acecfa | 19884 | ((INSTANCE) == TIM8)) |
| mbed_official | 19:112740acecfa | 19885 | |
| mbed_official | 19:112740acecfa | 19886 | /************ TIM Instances : DMA requests generation (CCxDE) *****************/ |
| mbed_official | 19:112740acecfa | 19887 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19888 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19889 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19890 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19891 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19892 | ((INSTANCE) == TIM8)) |
| mbed_official | 19:112740acecfa | 19893 | |
| mbed_official | 19:112740acecfa | 19894 | /************ TIM Instances : DMA requests generation (COMDE) *****************/ |
| mbed_official | 19:112740acecfa | 19895 | #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19896 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19897 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19898 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19899 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 167:e84263d55307 | 19900 | ((INSTANCE) == TIM8)) |
| mbed_official | 19:112740acecfa | 19901 | |
| mbed_official | 19:112740acecfa | 19902 | /******************** TIM Instances : DMA burst feature ***********************/ |
| mbed_official | 19:112740acecfa | 19903 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19904 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19905 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19906 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19907 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19908 | ((INSTANCE) == TIM8)) |
| mbed_official | 19:112740acecfa | 19909 | |
| mbed_official | 19:112740acecfa | 19910 | /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/ |
| AnnaBridge | 167:e84263d55307 | 19911 | #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 19912 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 167:e84263d55307 | 19913 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 167:e84263d55307 | 19914 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 167:e84263d55307 | 19915 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 167:e84263d55307 | 19916 | ((INSTANCE) == TIM6) || \ |
| AnnaBridge | 167:e84263d55307 | 19917 | ((INSTANCE) == TIM7) || \ |
| AnnaBridge | 167:e84263d55307 | 19918 | ((INSTANCE) == TIM8)) |
| mbed_official | 19:112740acecfa | 19919 | |
| mbed_official | 19:112740acecfa | 19920 | /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ |
| mbed_official | 19:112740acecfa | 19921 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19922 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19923 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19924 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19925 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19926 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 19:112740acecfa | 19927 | ((INSTANCE) == TIM9) || \ |
| mbed_official | 19:112740acecfa | 19928 | ((INSTANCE) == TIM12)) |
| mbed_official | 19:112740acecfa | 19929 | |
| mbed_official | 19:112740acecfa | 19930 | /********************** TIM Instances : 32 bit Counter ************************/ |
| mbed_official | 19:112740acecfa | 19931 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19932 | ((INSTANCE) == TIM5)) |
| mbed_official | 19:112740acecfa | 19933 | |
| mbed_official | 19:112740acecfa | 19934 | /***************** TIM Instances : external trigger input availabe ************/ |
| mbed_official | 19:112740acecfa | 19935 | #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 19:112740acecfa | 19936 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19937 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 19:112740acecfa | 19938 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 19:112740acecfa | 19939 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19940 | ((INSTANCE) == TIM8)) |
| mbed_official | 19:112740acecfa | 19941 | |
| mbed_official | 19:112740acecfa | 19942 | /****************** TIM Instances : remapping capability **********************/ |
| mbed_official | 19:112740acecfa | 19943 | #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
| mbed_official | 19:112740acecfa | 19944 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 19:112740acecfa | 19945 | ((INSTANCE) == TIM11)) |
| mbed_official | 19:112740acecfa | 19946 | |
| mbed_official | 19:112740acecfa | 19947 | /******************* TIM Instances : output(s) available **********************/ |
| mbed_official | 19:112740acecfa | 19948 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
| mbed_official | 19:112740acecfa | 19949 | ((((INSTANCE) == TIM1) && \ |
| mbed_official | 19:112740acecfa | 19950 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 19:112740acecfa | 19951 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 19:112740acecfa | 19952 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 19:112740acecfa | 19953 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 19:112740acecfa | 19954 | || \ |
| mbed_official | 19:112740acecfa | 19955 | (((INSTANCE) == TIM2) && \ |
| mbed_official | 19:112740acecfa | 19956 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 19:112740acecfa | 19957 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 19:112740acecfa | 19958 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 19:112740acecfa | 19959 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 19:112740acecfa | 19960 | || \ |
| mbed_official | 19:112740acecfa | 19961 | (((INSTANCE) == TIM3) && \ |
| mbed_official | 19:112740acecfa | 19962 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 19:112740acecfa | 19963 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 19:112740acecfa | 19964 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 19:112740acecfa | 19965 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 19:112740acecfa | 19966 | || \ |
| mbed_official | 19:112740acecfa | 19967 | (((INSTANCE) == TIM4) && \ |
| mbed_official | 19:112740acecfa | 19968 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 19:112740acecfa | 19969 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 19:112740acecfa | 19970 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 19:112740acecfa | 19971 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 19:112740acecfa | 19972 | || \ |
| mbed_official | 19:112740acecfa | 19973 | (((INSTANCE) == TIM5) && \ |
| mbed_official | 19:112740acecfa | 19974 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 19:112740acecfa | 19975 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 19:112740acecfa | 19976 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 19:112740acecfa | 19977 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 19:112740acecfa | 19978 | || \ |
| mbed_official | 19:112740acecfa | 19979 | (((INSTANCE) == TIM8) && \ |
| mbed_official | 19:112740acecfa | 19980 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 19:112740acecfa | 19981 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 19:112740acecfa | 19982 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 19:112740acecfa | 19983 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 19:112740acecfa | 19984 | || \ |
| mbed_official | 19:112740acecfa | 19985 | (((INSTANCE) == TIM9) && \ |
| mbed_official | 19:112740acecfa | 19986 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 19:112740acecfa | 19987 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
| mbed_official | 19:112740acecfa | 19988 | || \ |
| mbed_official | 19:112740acecfa | 19989 | (((INSTANCE) == TIM10) && \ |
| mbed_official | 19:112740acecfa | 19990 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
| mbed_official | 19:112740acecfa | 19991 | || \ |
| mbed_official | 19:112740acecfa | 19992 | (((INSTANCE) == TIM11) && \ |
| mbed_official | 19:112740acecfa | 19993 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
| mbed_official | 19:112740acecfa | 19994 | || \ |
| mbed_official | 19:112740acecfa | 19995 | (((INSTANCE) == TIM12) && \ |
| mbed_official | 19:112740acecfa | 19996 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 19:112740acecfa | 19997 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
| mbed_official | 19:112740acecfa | 19998 | || \ |
| mbed_official | 19:112740acecfa | 19999 | (((INSTANCE) == TIM13) && \ |
| mbed_official | 19:112740acecfa | 20000 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
| mbed_official | 19:112740acecfa | 20001 | || \ |
| mbed_official | 19:112740acecfa | 20002 | (((INSTANCE) == TIM14) && \ |
| mbed_official | 19:112740acecfa | 20003 | (((CHANNEL) == TIM_CHANNEL_1)))) |
| mbed_official | 19:112740acecfa | 20004 | |
| mbed_official | 19:112740acecfa | 20005 | /************ TIM Instances : complementary output(s) available ***************/ |
| mbed_official | 19:112740acecfa | 20006 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
| mbed_official | 19:112740acecfa | 20007 | ((((INSTANCE) == TIM1) && \ |
| mbed_official | 19:112740acecfa | 20008 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 19:112740acecfa | 20009 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 19:112740acecfa | 20010 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
| mbed_official | 19:112740acecfa | 20011 | || \ |
| mbed_official | 19:112740acecfa | 20012 | (((INSTANCE) == TIM8) && \ |
| mbed_official | 19:112740acecfa | 20013 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 19:112740acecfa | 20014 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 19:112740acecfa | 20015 | ((CHANNEL) == TIM_CHANNEL_3)))) |
| mbed_official | 19:112740acecfa | 20016 | |
| AnnaBridge | 167:e84263d55307 | 20017 | /****************** TIM Instances : supporting counting mode selection ********/ |
| AnnaBridge | 167:e84263d55307 | 20018 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 20019 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 167:e84263d55307 | 20020 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 167:e84263d55307 | 20021 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 167:e84263d55307 | 20022 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 167:e84263d55307 | 20023 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 167:e84263d55307 | 20024 | |
| AnnaBridge | 167:e84263d55307 | 20025 | /****************** TIM Instances : supporting clock division *****************/ |
| AnnaBridge | 167:e84263d55307 | 20026 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 20027 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 167:e84263d55307 | 20028 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 167:e84263d55307 | 20029 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 167:e84263d55307 | 20030 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 167:e84263d55307 | 20031 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 167:e84263d55307 | 20032 | ((INSTANCE) == TIM9) || \ |
| AnnaBridge | 167:e84263d55307 | 20033 | ((INSTANCE) == TIM10)|| \ |
| AnnaBridge | 167:e84263d55307 | 20034 | ((INSTANCE) == TIM11)|| \ |
| AnnaBridge | 167:e84263d55307 | 20035 | ((INSTANCE) == TIM12)|| \ |
| AnnaBridge | 167:e84263d55307 | 20036 | ((INSTANCE) == TIM13)|| \ |
| AnnaBridge | 167:e84263d55307 | 20037 | ((INSTANCE) == TIM14)) |
| AnnaBridge | 167:e84263d55307 | 20038 | |
| AnnaBridge | 167:e84263d55307 | 20039 | /****************** TIM Instances : supporting commutation event generation ***/ |
| AnnaBridge | 167:e84263d55307 | 20040 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \ |
| AnnaBridge | 167:e84263d55307 | 20041 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 167:e84263d55307 | 20042 | |
| AnnaBridge | 167:e84263d55307 | 20043 | |
| AnnaBridge | 167:e84263d55307 | 20044 | /****************** TIM Instances : supporting OCxREF clear *******************/ |
| AnnaBridge | 167:e84263d55307 | 20045 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 20046 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 167:e84263d55307 | 20047 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 167:e84263d55307 | 20048 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 167:e84263d55307 | 20049 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 167:e84263d55307 | 20050 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 167:e84263d55307 | 20051 | |
| AnnaBridge | 167:e84263d55307 | 20052 | /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ |
| AnnaBridge | 167:e84263d55307 | 20053 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 20054 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 167:e84263d55307 | 20055 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 167:e84263d55307 | 20056 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 167:e84263d55307 | 20057 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 167:e84263d55307 | 20058 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 167:e84263d55307 | 20059 | ((INSTANCE) == TIM9) || \ |
| AnnaBridge | 167:e84263d55307 | 20060 | ((INSTANCE) == TIM12)) |
| AnnaBridge | 167:e84263d55307 | 20061 | |
| AnnaBridge | 167:e84263d55307 | 20062 | /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ |
| AnnaBridge | 167:e84263d55307 | 20063 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 20064 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 167:e84263d55307 | 20065 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 167:e84263d55307 | 20066 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 167:e84263d55307 | 20067 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 167:e84263d55307 | 20068 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 167:e84263d55307 | 20069 | |
| AnnaBridge | 167:e84263d55307 | 20070 | /****************** TIM Instances : supporting repetition counter *************/ |
| AnnaBridge | 167:e84263d55307 | 20071 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 20072 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 167:e84263d55307 | 20073 | |
| AnnaBridge | 167:e84263d55307 | 20074 | /****************** TIM Instances : supporting encoder interface **************/ |
| AnnaBridge | 167:e84263d55307 | 20075 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 20076 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 167:e84263d55307 | 20077 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 167:e84263d55307 | 20078 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 167:e84263d55307 | 20079 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 167:e84263d55307 | 20080 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 167:e84263d55307 | 20081 | ((INSTANCE) == TIM9) || \ |
| AnnaBridge | 167:e84263d55307 | 20082 | ((INSTANCE) == TIM12)) |
| AnnaBridge | 167:e84263d55307 | 20083 | /****************** TIM Instances : supporting Hall sensor interface **********/ |
| AnnaBridge | 167:e84263d55307 | 20084 | #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 20085 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 167:e84263d55307 | 20086 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 167:e84263d55307 | 20087 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 167:e84263d55307 | 20088 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 167:e84263d55307 | 20089 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 167:e84263d55307 | 20090 | /****************** TIM Instances : supporting the break function *************/ |
| AnnaBridge | 167:e84263d55307 | 20091 | #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 167:e84263d55307 | 20092 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 167:e84263d55307 | 20093 | |
| mbed_official | 19:112740acecfa | 20094 | /******************** USART Instances : Synchronous mode **********************/ |
| mbed_official | 19:112740acecfa | 20095 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 19:112740acecfa | 20096 | ((INSTANCE) == USART2) || \ |
| mbed_official | 19:112740acecfa | 20097 | ((INSTANCE) == USART3) || \ |
| mbed_official | 19:112740acecfa | 20098 | ((INSTANCE) == USART6)) |
| mbed_official | 19:112740acecfa | 20099 | |
| AnnaBridge | 167:e84263d55307 | 20100 | /******************** UART Instances : Half-Duplex mode **********************/ |
| AnnaBridge | 167:e84263d55307 | 20101 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 167:e84263d55307 | 20102 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 167:e84263d55307 | 20103 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 167:e84263d55307 | 20104 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 167:e84263d55307 | 20105 | ((INSTANCE) == UART5) || \ |
| AnnaBridge | 167:e84263d55307 | 20106 | ((INSTANCE) == USART6) || \ |
| AnnaBridge | 167:e84263d55307 | 20107 | ((INSTANCE) == UART7) || \ |
| AnnaBridge | 167:e84263d55307 | 20108 | ((INSTANCE) == UART8)) |
| AnnaBridge | 167:e84263d55307 | 20109 | |
| AnnaBridge | 167:e84263d55307 | 20110 | /* Legacy defines */ |
| AnnaBridge | 167:e84263d55307 | 20111 | #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE |
| mbed_official | 19:112740acecfa | 20112 | |
| mbed_official | 19:112740acecfa | 20113 | /****************** UART Instances : Hardware Flow control ********************/ |
| mbed_official | 19:112740acecfa | 20114 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 19:112740acecfa | 20115 | ((INSTANCE) == USART2) || \ |
| mbed_official | 19:112740acecfa | 20116 | ((INSTANCE) == USART3) || \ |
| mbed_official | 19:112740acecfa | 20117 | ((INSTANCE) == USART6)) |
| AnnaBridge | 167:e84263d55307 | 20118 | /******************** UART Instances : LIN mode **********************/ |
| AnnaBridge | 167:e84263d55307 | 20119 | #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE |
| AnnaBridge | 167:e84263d55307 | 20120 | |
| AnnaBridge | 167:e84263d55307 | 20121 | /********************* UART Instances : Smart card mode ***********************/ |
| mbed_official | 19:112740acecfa | 20122 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 19:112740acecfa | 20123 | ((INSTANCE) == USART2) || \ |
| mbed_official | 19:112740acecfa | 20124 | ((INSTANCE) == USART3) || \ |
| mbed_official | 19:112740acecfa | 20125 | ((INSTANCE) == USART6)) |
| mbed_official | 19:112740acecfa | 20126 | |
| mbed_official | 19:112740acecfa | 20127 | /*********************** UART Instances : IRDA mode ***************************/ |
| mbed_official | 19:112740acecfa | 20128 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 19:112740acecfa | 20129 | ((INSTANCE) == USART2) || \ |
| mbed_official | 19:112740acecfa | 20130 | ((INSTANCE) == USART3) || \ |
| mbed_official | 19:112740acecfa | 20131 | ((INSTANCE) == UART4) || \ |
| mbed_official | 19:112740acecfa | 20132 | ((INSTANCE) == UART5) || \ |
| mbed_official | 19:112740acecfa | 20133 | ((INSTANCE) == USART6) || \ |
| mbed_official | 19:112740acecfa | 20134 | ((INSTANCE) == UART7) || \ |
| AnnaBridge | 167:e84263d55307 | 20135 | ((INSTANCE) == UART8)) |
| AnnaBridge | 167:e84263d55307 | 20136 | |
| <> | 144:ef7eb2e8f9f7 | 20137 | /*********************** PCD Instances ****************************************/ |
| <> | 144:ef7eb2e8f9f7 | 20138 | #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ |
| AnnaBridge | 167:e84263d55307 | 20139 | ((INSTANCE) == USB_OTG_HS)) |
| <> | 144:ef7eb2e8f9f7 | 20140 | |
| <> | 144:ef7eb2e8f9f7 | 20141 | /*********************** HCD Instances ****************************************/ |
| <> | 144:ef7eb2e8f9f7 | 20142 | #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ |
| <> | 144:ef7eb2e8f9f7 | 20143 | ((INSTANCE) == USB_OTG_HS)) |
| <> | 144:ef7eb2e8f9f7 | 20144 | |
| mbed_official | 19:112740acecfa | 20145 | /****************************** SDIO Instances ********************************/ |
| mbed_official | 19:112740acecfa | 20146 | #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) |
| mbed_official | 19:112740acecfa | 20147 | |
| mbed_official | 19:112740acecfa | 20148 | /****************************** IWDG Instances ********************************/ |
| mbed_official | 19:112740acecfa | 20149 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
| mbed_official | 19:112740acecfa | 20150 | |
| mbed_official | 19:112740acecfa | 20151 | /****************************** WWDG Instances ********************************/ |
| mbed_official | 19:112740acecfa | 20152 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
| mbed_official | 19:112740acecfa | 20153 | |
| AnnaBridge | 167:e84263d55307 | 20154 | |
| mbed_official | 19:112740acecfa | 20155 | /****************************** QSPI Instances ********************************/ |
| mbed_official | 19:112740acecfa | 20156 | #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| mbed_official | 19:112740acecfa | 20157 | /****************************** USB Exported Constants ************************/ |
| <> | 144:ef7eb2e8f9f7 | 20158 | #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U |
| <> | 144:ef7eb2e8f9f7 | 20159 | #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */ |
| <> | 144:ef7eb2e8f9f7 | 20160 | #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */ |
| <> | 144:ef7eb2e8f9f7 | 20161 | #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */ |
| <> | 144:ef7eb2e8f9f7 | 20162 | #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U |
| <> | 144:ef7eb2e8f9f7 | 20163 | #define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */ |
| <> | 144:ef7eb2e8f9f7 | 20164 | #define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */ |
| <> | 144:ef7eb2e8f9f7 | 20165 | #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */ |
| mbed_official | 19:112740acecfa | 20166 | |
| AnnaBridge | 167:e84263d55307 | 20167 | /* |
| AnnaBridge | 167:e84263d55307 | 20168 | * @brief Specific devices reset values definitions |
| AnnaBridge | 167:e84263d55307 | 20169 | */ |
| AnnaBridge | 167:e84263d55307 | 20170 | #define RCC_PLLCFGR_RST_VALUE 0x24003010U |
| AnnaBridge | 167:e84263d55307 | 20171 | #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U |
| AnnaBridge | 167:e84263d55307 | 20172 | #define RCC_PLLSAICFGR_RST_VALUE 0x24003000U |
| AnnaBridge | 167:e84263d55307 | 20173 | |
| AnnaBridge | 167:e84263d55307 | 20174 | #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/ |
| AnnaBridge | 167:e84263d55307 | 20175 | #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 20176 | #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 20177 | #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 20178 | #define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 20179 | #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 20180 | #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 20181 | #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */ |
| AnnaBridge | 167:e84263d55307 | 20182 | |
| AnnaBridge | 167:e84263d55307 | 20183 | #define RCC_PLLN_MIN_VALUE 50U |
| AnnaBridge | 167:e84263d55307 | 20184 | #define RCC_PLLN_MAX_VALUE 432U |
| AnnaBridge | 167:e84263d55307 | 20185 | |
| AnnaBridge | 167:e84263d55307 | 20186 | #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ |
| AnnaBridge | 167:e84263d55307 | 20187 | #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ |
| AnnaBridge | 167:e84263d55307 | 20188 | #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ |
| AnnaBridge | 167:e84263d55307 | 20189 | #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ |
| AnnaBridge | 167:e84263d55307 | 20190 | #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ |
| AnnaBridge | 167:e84263d55307 | 20191 | |
| AnnaBridge | 167:e84263d55307 | 20192 | #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ |
| AnnaBridge | 167:e84263d55307 | 20193 | #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ |
| AnnaBridge | 167:e84263d55307 | 20194 | #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ |
| AnnaBridge | 167:e84263d55307 | 20195 | #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */ |
| AnnaBridge | 167:e84263d55307 | 20196 | #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */ |
| AnnaBridge | 167:e84263d55307 | 20197 | |
| AnnaBridge | 167:e84263d55307 | 20198 | #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ |
| AnnaBridge | 167:e84263d55307 | 20199 | #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ |
| AnnaBridge | 167:e84263d55307 | 20200 | #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ |
| AnnaBridge | 167:e84263d55307 | 20201 | |
| AnnaBridge | 167:e84263d55307 | 20202 | /******************************************************************************/ |
| AnnaBridge | 167:e84263d55307 | 20203 | /* For a painless codes migration between the STM32F4xx device product */ |
| AnnaBridge | 167:e84263d55307 | 20204 | /* lines, the aliases defined below are put in place to overcome the */ |
| AnnaBridge | 167:e84263d55307 | 20205 | /* differences in the interrupt handlers and IRQn definitions. */ |
| AnnaBridge | 167:e84263d55307 | 20206 | /* No need to update developed interrupt code when moving across */ |
| AnnaBridge | 167:e84263d55307 | 20207 | /* product lines within the same STM32F4 Family */ |
| AnnaBridge | 167:e84263d55307 | 20208 | /******************************************************************************/ |
| AnnaBridge | 167:e84263d55307 | 20209 | /* Aliases for __IRQn */ |
| AnnaBridge | 167:e84263d55307 | 20210 | #define FSMC_IRQn FMC_IRQn |
| AnnaBridge | 167:e84263d55307 | 20211 | |
| AnnaBridge | 167:e84263d55307 | 20212 | /* Aliases for __IRQHandler */ |
| AnnaBridge | 167:e84263d55307 | 20213 | #define FSMC_IRQHandler FMC_IRQHandler |
| AnnaBridge | 167:e84263d55307 | 20214 | |
| mbed_official | 19:112740acecfa | 20215 | /** |
| mbed_official | 19:112740acecfa | 20216 | * @} |
| mbed_official | 19:112740acecfa | 20217 | */ |
| AnnaBridge | 167:e84263d55307 | 20218 | |
| mbed_official | 19:112740acecfa | 20219 | /** |
| mbed_official | 19:112740acecfa | 20220 | * @} |
| mbed_official | 19:112740acecfa | 20221 | */ |
| mbed_official | 19:112740acecfa | 20222 | |
| mbed_official | 19:112740acecfa | 20223 | /** |
| mbed_official | 19:112740acecfa | 20224 | * @} |
| mbed_official | 19:112740acecfa | 20225 | */ |
| mbed_official | 19:112740acecfa | 20226 | |
| mbed_official | 19:112740acecfa | 20227 | #ifdef __cplusplus |
| mbed_official | 19:112740acecfa | 20228 | } |
| mbed_official | 19:112740acecfa | 20229 | #endif /* __cplusplus */ |
| mbed_official | 19:112740acecfa | 20230 | |
| mbed_official | 19:112740acecfa | 20231 | #endif /* __STM32F469xx_H */ |
| mbed_official | 19:112740acecfa | 20232 | |
| mbed_official | 19:112740acecfa | 20233 | |
| mbed_official | 19:112740acecfa | 20234 | |
| mbed_official | 19:112740acecfa | 20235 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
