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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 168:9672193075cf 1 /* mbed Microcontroller Library
AnnaBridge 168:9672193075cf 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 168:9672193075cf 3 *
AnnaBridge 168:9672193075cf 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 168:9672193075cf 5 * you may not use this file except in compliance with the License.
AnnaBridge 168:9672193075cf 6 * You may obtain a copy of the License at
AnnaBridge 168:9672193075cf 7 *
AnnaBridge 168:9672193075cf 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 168:9672193075cf 9 *
AnnaBridge 168:9672193075cf 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 168:9672193075cf 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 168:9672193075cf 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 168:9672193075cf 13 * See the License for the specific language governing permissions and
AnnaBridge 168:9672193075cf 14 * limitations under the License.
AnnaBridge 168:9672193075cf 15 */
AnnaBridge 168:9672193075cf 16
AnnaBridge 168:9672193075cf 17 /**
AnnaBridge 168:9672193075cf 18 * This file configures the system clock as follows:
AnnaBridge 168:9672193075cf 19 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 20 * System clock source | 1- USE_PLL_HSE_EXTC | 3- USE_PLL_HSI
AnnaBridge 168:9672193075cf 21 * | (external 8 MHz clock) | (internal 16 MHz)
AnnaBridge 168:9672193075cf 22 * | 2- USE_PLL_HSE_XTAL |
AnnaBridge 168:9672193075cf 23 * | (external 8 MHz xtal) |
AnnaBridge 168:9672193075cf 24 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 25 * SYSCLK(MHz) | 180 | 180
AnnaBridge 168:9672193075cf 26 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 27 * AHBCLK (MHz) | 180 | 180
AnnaBridge 168:9672193075cf 28 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 29 * APB1CLK (MHz) | 45 | 45
AnnaBridge 168:9672193075cf 30 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 31 * APB2CLK (MHz) | 90 | 90
AnnaBridge 168:9672193075cf 32 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 33 * USB capable (48 MHz precise clock) | YES | YES (HSI calibration needed)
AnnaBridge 168:9672193075cf 34 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 35 **/
AnnaBridge 168:9672193075cf 36
AnnaBridge 168:9672193075cf 37 #include "stm32f4xx.h"
AnnaBridge 187:0387e8f68319 38 #include "mbed_error.h"
AnnaBridge 168:9672193075cf 39
AnnaBridge 168:9672193075cf 40 // clock source is selected with CLOCK_SOURCE in json config
AnnaBridge 168:9672193075cf 41 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
AnnaBridge 168:9672193075cf 42 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
AnnaBridge 168:9672193075cf 43 #define USE_PLL_HSI 0x2 // Use HSI internal clock
AnnaBridge 168:9672193075cf 44
AnnaBridge 168:9672193075cf 45 //#define DEBUG_MCO (1) // Output the MCO1/MCO2 on PA8/PC9 for debugging (0=OFF, 1=ON)
AnnaBridge 168:9672193075cf 46
AnnaBridge 168:9672193075cf 47
AnnaBridge 168:9672193075cf 48 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 168:9672193075cf 49 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 168:9672193075cf 50 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 168:9672193075cf 51
AnnaBridge 168:9672193075cf 52 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 53 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 168:9672193075cf 54 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
AnnaBridge 168:9672193075cf 55
AnnaBridge 168:9672193075cf 56
AnnaBridge 168:9672193075cf 57 /**
AnnaBridge 168:9672193075cf 58 * @brief Setup the microcontroller system
AnnaBridge 168:9672193075cf 59 * Initialize the FPU setting, vector table location and External memory
AnnaBridge 168:9672193075cf 60 * configuration.
AnnaBridge 168:9672193075cf 61 * @param None
AnnaBridge 168:9672193075cf 62 * @retval None
AnnaBridge 168:9672193075cf 63 */
AnnaBridge 168:9672193075cf 64 void SystemInit(void)
AnnaBridge 168:9672193075cf 65 {
AnnaBridge 168:9672193075cf 66 /* FPU settings ------------------------------------------------------------*/
AnnaBridge 168:9672193075cf 67 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 187:0387e8f68319 68 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
AnnaBridge 168:9672193075cf 69 #endif
AnnaBridge 168:9672193075cf 70 /* Reset the RCC clock configuration to the default reset state ------------*/
AnnaBridge 168:9672193075cf 71 /* Set HSION bit */
AnnaBridge 168:9672193075cf 72 RCC->CR |= (uint32_t)0x00000001;
AnnaBridge 168:9672193075cf 73
AnnaBridge 168:9672193075cf 74 /* Reset CFGR register */
AnnaBridge 168:9672193075cf 75 RCC->CFGR = 0x00000000;
AnnaBridge 168:9672193075cf 76
AnnaBridge 168:9672193075cf 77 /* Reset HSEON, CSSON and PLLON bits */
AnnaBridge 168:9672193075cf 78 RCC->CR &= (uint32_t)0xFEF6FFFF;
AnnaBridge 168:9672193075cf 79
AnnaBridge 168:9672193075cf 80 /* Reset PLLCFGR register */
AnnaBridge 168:9672193075cf 81 RCC->PLLCFGR = 0x24003010;
AnnaBridge 168:9672193075cf 82
AnnaBridge 168:9672193075cf 83 /* Reset HSEBYP bit */
AnnaBridge 168:9672193075cf 84 RCC->CR &= (uint32_t)0xFFFBFFFF;
AnnaBridge 168:9672193075cf 85
AnnaBridge 168:9672193075cf 86 /* Disable all interrupts */
AnnaBridge 168:9672193075cf 87 RCC->CIR = 0x00000000;
AnnaBridge 168:9672193075cf 88
AnnaBridge 168:9672193075cf 89 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
AnnaBridge 168:9672193075cf 90 SystemInit_ExtMemCtl();
AnnaBridge 168:9672193075cf 91 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
AnnaBridge 168:9672193075cf 92
AnnaBridge 168:9672193075cf 93 }
AnnaBridge 168:9672193075cf 94
AnnaBridge 168:9672193075cf 95
AnnaBridge 168:9672193075cf 96 /**
AnnaBridge 168:9672193075cf 97 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 168:9672193075cf 98 * AHB/APBx prescalers and Flash settings
AnnaBridge 168:9672193075cf 99 * @note This function should be called only once the RCC clock configuration
AnnaBridge 168:9672193075cf 100 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 168:9672193075cf 101 * @param None
AnnaBridge 168:9672193075cf 102 * @retval None
AnnaBridge 168:9672193075cf 103 */
AnnaBridge 168:9672193075cf 104
AnnaBridge 168:9672193075cf 105 void SetSysClock(void)
AnnaBridge 168:9672193075cf 106 {
AnnaBridge 168:9672193075cf 107 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
AnnaBridge 168:9672193075cf 108 /* 1- Try to start with HSE and external clock */
AnnaBridge 168:9672193075cf 109 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 168:9672193075cf 110 #endif
AnnaBridge 168:9672193075cf 111 {
AnnaBridge 168:9672193075cf 112 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
AnnaBridge 168:9672193075cf 113 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 168:9672193075cf 114 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 168:9672193075cf 115 #endif
AnnaBridge 168:9672193075cf 116 {
AnnaBridge 168:9672193075cf 117 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 118 /* 3- If fail start with HSI clock */
AnnaBridge 168:9672193075cf 119 if (SetSysClock_PLL_HSI() == 0)
AnnaBridge 168:9672193075cf 120 #endif
AnnaBridge 168:9672193075cf 121 {
AnnaBridge 187:0387e8f68319 122 {
AnnaBridge 187:0387e8f68319 123 error("SetSysClock failed\n");
AnnaBridge 168:9672193075cf 124 }
AnnaBridge 168:9672193075cf 125 }
AnnaBridge 168:9672193075cf 126 }
AnnaBridge 168:9672193075cf 127 }
AnnaBridge 168:9672193075cf 128
AnnaBridge 168:9672193075cf 129 // Output clock on MCO2 pin(PC9) for debugging purpose
AnnaBridge 168:9672193075cf 130 #if DEBUG_MCO == 1
AnnaBridge 168:9672193075cf 131 HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
AnnaBridge 168:9672193075cf 132 #endif
AnnaBridge 168:9672193075cf 133 }
AnnaBridge 168:9672193075cf 134
AnnaBridge 168:9672193075cf 135 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 168:9672193075cf 136 /******************************************************************************/
AnnaBridge 168:9672193075cf 137 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 168:9672193075cf 138 /******************************************************************************/
AnnaBridge 168:9672193075cf 139 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 168:9672193075cf 140 {
AnnaBridge 168:9672193075cf 141 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 142 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 143 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
AnnaBridge 168:9672193075cf 144
AnnaBridge 168:9672193075cf 145 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 146 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 147 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 148 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 149 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 168:9672193075cf 150
AnnaBridge 168:9672193075cf 151 // Enable HSE oscillator and activate PLL with HSE as source
AnnaBridge 168:9672193075cf 152 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 153 if (bypass == 0) {
AnnaBridge 168:9672193075cf 154 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
AnnaBridge 168:9672193075cf 155 } else {
AnnaBridge 168:9672193075cf 156 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
AnnaBridge 168:9672193075cf 157 }
AnnaBridge 168:9672193075cf 158
AnnaBridge 168:9672193075cf 159 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 160 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
AnnaBridge 168:9672193075cf 161 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
AnnaBridge 168:9672193075cf 162 RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
AnnaBridge 168:9672193075cf 163 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
AnnaBridge 168:9672193075cf 164 RCC_OscInitStruct.PLL.PLLQ = 7; //
AnnaBridge 168:9672193075cf 165 RCC_OscInitStruct.PLL.PLLR = 2; //
AnnaBridge 168:9672193075cf 166 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 167 return 0; // FAIL
AnnaBridge 168:9672193075cf 168 }
AnnaBridge 168:9672193075cf 169
AnnaBridge 168:9672193075cf 170 // Activate the OverDrive to reach the 180 MHz Frequency
AnnaBridge 168:9672193075cf 171 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
AnnaBridge 168:9672193075cf 172 return 0; // FAIL
AnnaBridge 168:9672193075cf 173 }
AnnaBridge 168:9672193075cf 174
AnnaBridge 168:9672193075cf 175 // Select PLLSAI output as USB clock source
AnnaBridge 168:9672193075cf 176 PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
AnnaBridge 168:9672193075cf 177 PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
AnnaBridge 168:9672193075cf 178 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
AnnaBridge 168:9672193075cf 179 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
AnnaBridge 168:9672193075cf 180 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
AnnaBridge 168:9672193075cf 181 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
AnnaBridge 168:9672193075cf 182
AnnaBridge 168:9672193075cf 183 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
AnnaBridge 168:9672193075cf 184 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
AnnaBridge 168:9672193075cf 185 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
AnnaBridge 168:9672193075cf 186 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
AnnaBridge 168:9672193075cf 187 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
AnnaBridge 168:9672193075cf 188 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
AnnaBridge 168:9672193075cf 189 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
AnnaBridge 168:9672193075cf 190 return 0; // FAIL
AnnaBridge 168:9672193075cf 191 }
AnnaBridge 168:9672193075cf 192
AnnaBridge 168:9672193075cf 193 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 168:9672193075cf 194 #if DEBUG_MCO == 1
AnnaBridge 187:0387e8f68319 195 if (bypass == 0) {
AnnaBridge 187:0387e8f68319 196 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
AnnaBridge 187:0387e8f68319 197 } else {
AnnaBridge 187:0387e8f68319 198 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
AnnaBridge 187:0387e8f68319 199 }
AnnaBridge 168:9672193075cf 200 #endif
AnnaBridge 168:9672193075cf 201
AnnaBridge 168:9672193075cf 202 return 1; // OK
AnnaBridge 168:9672193075cf 203 }
AnnaBridge 168:9672193075cf 204 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 168:9672193075cf 205
AnnaBridge 168:9672193075cf 206 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 207 /******************************************************************************/
AnnaBridge 168:9672193075cf 208 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 168:9672193075cf 209 /******************************************************************************/
AnnaBridge 168:9672193075cf 210 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 168:9672193075cf 211 {
AnnaBridge 168:9672193075cf 212 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 213 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 214 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
AnnaBridge 168:9672193075cf 215
AnnaBridge 168:9672193075cf 216 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 217 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 218 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 219 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 220 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 168:9672193075cf 221
AnnaBridge 168:9672193075cf 222 // Enable HSI oscillator and activate PLL with HSI as source
AnnaBridge 168:9672193075cf 223 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 224 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 168:9672193075cf 225 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 182:a56a73fd2a6f 226 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
AnnaBridge 168:9672193075cf 227 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 228 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
AnnaBridge 168:9672193075cf 229 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
AnnaBridge 168:9672193075cf 230 RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)
AnnaBridge 168:9672193075cf 231 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)
AnnaBridge 168:9672193075cf 232 RCC_OscInitStruct.PLL.PLLQ = 7; //
AnnaBridge 168:9672193075cf 233 RCC_OscInitStruct.PLL.PLLQ = 6; //
AnnaBridge 168:9672193075cf 234 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 235 return 0; // FAIL
AnnaBridge 168:9672193075cf 236 }
AnnaBridge 168:9672193075cf 237
AnnaBridge 168:9672193075cf 238 // Activate the OverDrive to reach the 180 MHz Frequency
AnnaBridge 168:9672193075cf 239 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
AnnaBridge 168:9672193075cf 240 return 0; // FAIL
AnnaBridge 168:9672193075cf 241 }
AnnaBridge 168:9672193075cf 242
AnnaBridge 168:9672193075cf 243 // Select PLLSAI output as USB clock source
AnnaBridge 168:9672193075cf 244 PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;
AnnaBridge 168:9672193075cf 245 PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
AnnaBridge 168:9672193075cf 246 PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
AnnaBridge 168:9672193075cf 247 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
AnnaBridge 168:9672193075cf 248 PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
AnnaBridge 168:9672193075cf 249 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
AnnaBridge 168:9672193075cf 250
AnnaBridge 168:9672193075cf 251 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 168:9672193075cf 252 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 168:9672193075cf 253 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
AnnaBridge 168:9672193075cf 254 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz
AnnaBridge 168:9672193075cf 255 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz
AnnaBridge 168:9672193075cf 256 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz
AnnaBridge 168:9672193075cf 257 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
AnnaBridge 168:9672193075cf 258 return 0; // FAIL
AnnaBridge 168:9672193075cf 259 }
AnnaBridge 168:9672193075cf 260
AnnaBridge 168:9672193075cf 261 // Output clock on MCO1 pin(PA8) for debugging purpose
AnnaBridge 168:9672193075cf 262 #if DEBUG_MCO == 1
AnnaBridge 168:9672193075cf 263 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
AnnaBridge 168:9672193075cf 264 #endif
AnnaBridge 168:9672193075cf 265
AnnaBridge 168:9672193075cf 266 return 1; // OK
AnnaBridge 168:9672193075cf 267 }
AnnaBridge 168:9672193075cf 268 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */