mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
<> 144:ef7eb2e8f9f7 2 ;* File Name : startup_stm32f303xe.s
<> 144:ef7eb2e8f9f7 3 ;* Author : MCD Application Team
Anna Bridge 186:707f6e361f3e 4 ;* Description : STM32F303xE devices vector table for MDK-ARM toolchain.
<> 144:ef7eb2e8f9f7 5 ;* This module performs:
<> 144:ef7eb2e8f9f7 6 ;* - Set the initial SP
<> 144:ef7eb2e8f9f7 7 ;* - Set the initial PC == Reset_Handler
<> 144:ef7eb2e8f9f7 8 ;* - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 9 ;* - Branches to __main in the C library (which eventually
<> 144:ef7eb2e8f9f7 10 ;* calls main()).
<> 144:ef7eb2e8f9f7 11 ;* After Reset the CortexM4 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 12 ;* priority is Privileged, and the Stack is set to Main.
Anna Bridge 186:707f6e361f3e 13 ;*
<> 144:ef7eb2e8f9f7 14 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 15 ;
<> 144:ef7eb2e8f9f7 16 ;* Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 17 ;* are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 18 ;* 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 19 ;* this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 20 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 21 ;* this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 22 ;* and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 23 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 24 ;* may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 25 ;* without specific prior written permission.
<> 144:ef7eb2e8f9f7 26 ;*
<> 144:ef7eb2e8f9f7 27 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 28 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 29 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 30 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 31 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 32 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 33 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 34 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 35 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 36 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 37 ;
<> 144:ef7eb2e8f9f7 38 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 ; Amount of memory (in bytes) allocated for Stack
<> 144:ef7eb2e8f9f7 41 ; Tailor this value to your application needs
<> 144:ef7eb2e8f9f7 42 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 43 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 44 ; </h>
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 Stack_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 49 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 Stack_Mem SPACE Stack_Size
<> 144:ef7eb2e8f9f7 52 __initial_sp EQU 0x20010000 ; Top of RAM
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 56 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 57 ; </h>
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 Heap_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 62 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 63 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 __heap_base
<> 144:ef7eb2e8f9f7 66 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 67 __heap_limit EQU (__initial_sp - Stack_Size)
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 PRESERVE8
<> 144:ef7eb2e8f9f7 70 THUMB
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 74 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 75 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 76 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 77 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 80 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 81 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 82 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 83 DCD MemManage_Handler ; MPU Fault Handler
<> 144:ef7eb2e8f9f7 84 DCD BusFault_Handler ; Bus Fault Handler
<> 144:ef7eb2e8f9f7 85 DCD UsageFault_Handler ; Usage Fault Handler
<> 144:ef7eb2e8f9f7 86 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 87 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 88 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 89 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 90 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 91 DCD DebugMon_Handler ; Debug Monitor Handler
<> 144:ef7eb2e8f9f7 92 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 93 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 94 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 ; External Interrupts
<> 144:ef7eb2e8f9f7 97 DCD WWDG_IRQHandler ; Window WatchDog
<> 144:ef7eb2e8f9f7 98 DCD PVD_IRQHandler ; PVD through EXTI Line detection
<> 144:ef7eb2e8f9f7 99 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
<> 144:ef7eb2e8f9f7 100 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
<> 144:ef7eb2e8f9f7 101 DCD FLASH_IRQHandler ; FLASH
<> 144:ef7eb2e8f9f7 102 DCD RCC_IRQHandler ; RCC
<> 144:ef7eb2e8f9f7 103 DCD EXTI0_IRQHandler ; EXTI Line0
<> 144:ef7eb2e8f9f7 104 DCD EXTI1_IRQHandler ; EXTI Line1
<> 144:ef7eb2e8f9f7 105 DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
<> 144:ef7eb2e8f9f7 106 DCD EXTI3_IRQHandler ; EXTI Line3
<> 144:ef7eb2e8f9f7 107 DCD EXTI4_IRQHandler ; EXTI Line4
<> 144:ef7eb2e8f9f7 108 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
<> 144:ef7eb2e8f9f7 109 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
<> 144:ef7eb2e8f9f7 110 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
<> 144:ef7eb2e8f9f7 111 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
<> 144:ef7eb2e8f9f7 112 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
<> 144:ef7eb2e8f9f7 113 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
<> 144:ef7eb2e8f9f7 114 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
<> 144:ef7eb2e8f9f7 115 DCD ADC1_2_IRQHandler ; ADC1 and ADC2
<> 144:ef7eb2e8f9f7 116 DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
<> 144:ef7eb2e8f9f7 117 DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
<> 144:ef7eb2e8f9f7 118 DCD CAN_RX1_IRQHandler ; CAN RX1
<> 144:ef7eb2e8f9f7 119 DCD CAN_SCE_IRQHandler ; CAN SCE
<> 144:ef7eb2e8f9f7 120 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
<> 144:ef7eb2e8f9f7 121 DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
<> 144:ef7eb2e8f9f7 122 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
<> 144:ef7eb2e8f9f7 123 DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
<> 144:ef7eb2e8f9f7 124 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
<> 144:ef7eb2e8f9f7 125 DCD TIM2_IRQHandler ; TIM2
<> 144:ef7eb2e8f9f7 126 DCD TIM3_IRQHandler ; TIM3
<> 144:ef7eb2e8f9f7 127 DCD TIM4_IRQHandler ; TIM4
<> 144:ef7eb2e8f9f7 128 DCD I2C1_EV_IRQHandler ; I2C1 Event
<> 144:ef7eb2e8f9f7 129 DCD I2C1_ER_IRQHandler ; I2C1 Error
<> 144:ef7eb2e8f9f7 130 DCD I2C2_EV_IRQHandler ; I2C2 Event
<> 144:ef7eb2e8f9f7 131 DCD I2C2_ER_IRQHandler ; I2C2 Error
<> 144:ef7eb2e8f9f7 132 DCD SPI1_IRQHandler ; SPI1
<> 144:ef7eb2e8f9f7 133 DCD SPI2_IRQHandler ; SPI2
<> 144:ef7eb2e8f9f7 134 DCD USART1_IRQHandler ; USART1
<> 144:ef7eb2e8f9f7 135 DCD USART2_IRQHandler ; USART2
<> 144:ef7eb2e8f9f7 136 DCD USART3_IRQHandler ; USART3
<> 144:ef7eb2e8f9f7 137 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
<> 144:ef7eb2e8f9f7 138 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
<> 144:ef7eb2e8f9f7 139 DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
<> 144:ef7eb2e8f9f7 140 DCD TIM8_BRK_IRQHandler ; TIM8 Break
<> 144:ef7eb2e8f9f7 141 DCD TIM8_UP_IRQHandler ; TIM8 Update
<> 144:ef7eb2e8f9f7 142 DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
<> 144:ef7eb2e8f9f7 143 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
<> 144:ef7eb2e8f9f7 144 DCD ADC3_IRQHandler ; ADC3
<> 144:ef7eb2e8f9f7 145 DCD FMC_IRQHandler ; FMC
<> 144:ef7eb2e8f9f7 146 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 147 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 148 DCD SPI3_IRQHandler ; SPI3
<> 144:ef7eb2e8f9f7 149 DCD UART4_IRQHandler ; UART4
<> 144:ef7eb2e8f9f7 150 DCD UART5_IRQHandler ; UART5
<> 144:ef7eb2e8f9f7 151 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
<> 144:ef7eb2e8f9f7 152 DCD TIM7_IRQHandler ; TIM7
<> 144:ef7eb2e8f9f7 153 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
<> 144:ef7eb2e8f9f7 154 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
<> 144:ef7eb2e8f9f7 155 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
<> 144:ef7eb2e8f9f7 156 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
<> 144:ef7eb2e8f9f7 157 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
<> 144:ef7eb2e8f9f7 158 DCD ADC4_IRQHandler ; ADC4
<> 144:ef7eb2e8f9f7 159 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 160 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 161 DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
<> 144:ef7eb2e8f9f7 162 DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
<> 144:ef7eb2e8f9f7 163 DCD COMP7_IRQHandler ; COMP7
<> 144:ef7eb2e8f9f7 164 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 165 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 166 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 167 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 168 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 169 DCD I2C3_EV_IRQHandler ; I2C3 Event
<> 144:ef7eb2e8f9f7 170 DCD I2C3_ER_IRQHandler ; I2C3 Error
<> 144:ef7eb2e8f9f7 171 DCD USB_HP_IRQHandler ; USB High Priority remap
<> 144:ef7eb2e8f9f7 172 DCD USB_LP_IRQHandler ; USB Low Priority remap
<> 144:ef7eb2e8f9f7 173 DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
<> 144:ef7eb2e8f9f7 174 DCD TIM20_BRK_IRQHandler ; TIM20 Break
<> 144:ef7eb2e8f9f7 175 DCD TIM20_UP_IRQHandler ; TIM20 Update
<> 144:ef7eb2e8f9f7 176 DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
<> 144:ef7eb2e8f9f7 177 DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
<> 144:ef7eb2e8f9f7 178 DCD FPU_IRQHandler ; FPU
<> 144:ef7eb2e8f9f7 179 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 180 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 181 DCD SPI4_IRQHandler ; SPI4
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 __Vectors_End
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 ; Reset handler
<> 144:ef7eb2e8f9f7 190 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 191 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 192 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 193 IMPORT __main
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 196 BLX R0
<> 144:ef7eb2e8f9f7 197 LDR R0, =__main
<> 144:ef7eb2e8f9f7 198 BX R0
<> 144:ef7eb2e8f9f7 199 ENDP
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 204 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 205 B .
<> 144:ef7eb2e8f9f7 206 ENDP
<> 144:ef7eb2e8f9f7 207 HardFault_Handler\
<> 144:ef7eb2e8f9f7 208 PROC
<> 144:ef7eb2e8f9f7 209 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 210 B .
<> 144:ef7eb2e8f9f7 211 ENDP
<> 144:ef7eb2e8f9f7 212 MemManage_Handler\
<> 144:ef7eb2e8f9f7 213 PROC
<> 144:ef7eb2e8f9f7 214 EXPORT MemManage_Handler [WEAK]
<> 144:ef7eb2e8f9f7 215 B .
<> 144:ef7eb2e8f9f7 216 ENDP
<> 144:ef7eb2e8f9f7 217 BusFault_Handler\
<> 144:ef7eb2e8f9f7 218 PROC
<> 144:ef7eb2e8f9f7 219 EXPORT BusFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 220 B .
<> 144:ef7eb2e8f9f7 221 ENDP
<> 144:ef7eb2e8f9f7 222 UsageFault_Handler\
<> 144:ef7eb2e8f9f7 223 PROC
<> 144:ef7eb2e8f9f7 224 EXPORT UsageFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 225 B .
<> 144:ef7eb2e8f9f7 226 ENDP
<> 144:ef7eb2e8f9f7 227 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 228 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 229 B .
<> 144:ef7eb2e8f9f7 230 ENDP
<> 144:ef7eb2e8f9f7 231 DebugMon_Handler\
<> 144:ef7eb2e8f9f7 232 PROC
<> 144:ef7eb2e8f9f7 233 EXPORT DebugMon_Handler [WEAK]
<> 144:ef7eb2e8f9f7 234 B .
<> 144:ef7eb2e8f9f7 235 ENDP
<> 144:ef7eb2e8f9f7 236 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 237 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 238 B .
<> 144:ef7eb2e8f9f7 239 ENDP
<> 144:ef7eb2e8f9f7 240 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 241 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 242 B .
<> 144:ef7eb2e8f9f7 243 ENDP
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 Default_Handler PROC
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 EXPORT WWDG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 248 EXPORT PVD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 249 EXPORT TAMP_STAMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 250 EXPORT RTC_WKUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 251 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 252 EXPORT RCC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 253 EXPORT EXTI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 254 EXPORT EXTI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 255 EXPORT EXTI2_TSC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 256 EXPORT EXTI3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 257 EXPORT EXTI4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 258 EXPORT DMA1_Channel1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 259 EXPORT DMA1_Channel2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 260 EXPORT DMA1_Channel3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 261 EXPORT DMA1_Channel4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 262 EXPORT DMA1_Channel5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 263 EXPORT DMA1_Channel6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 264 EXPORT DMA1_Channel7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 265 EXPORT ADC1_2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 266 EXPORT USB_HP_CAN_TX_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 267 EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 268 EXPORT CAN_RX1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 269 EXPORT CAN_SCE_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 270 EXPORT EXTI9_5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 271 EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 272 EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 273 EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 274 EXPORT TIM1_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 275 EXPORT TIM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 276 EXPORT TIM3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 277 EXPORT TIM4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 278 EXPORT I2C1_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 279 EXPORT I2C1_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 280 EXPORT I2C2_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 281 EXPORT I2C2_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 282 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 283 EXPORT SPI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 284 EXPORT USART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 285 EXPORT USART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 286 EXPORT USART3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 287 EXPORT EXTI15_10_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 288 EXPORT RTC_Alarm_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 289 EXPORT USBWakeUp_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 290 EXPORT TIM8_BRK_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 291 EXPORT TIM8_UP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 292 EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 293 EXPORT TIM8_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 294 EXPORT ADC3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 295 EXPORT FMC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 296 EXPORT SPI3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 297 EXPORT UART4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 298 EXPORT UART5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 299 EXPORT TIM6_DAC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 300 EXPORT TIM7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 301 EXPORT DMA2_Channel1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 302 EXPORT DMA2_Channel2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 303 EXPORT DMA2_Channel3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 304 EXPORT DMA2_Channel4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 305 EXPORT DMA2_Channel5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 306 EXPORT ADC4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 307 EXPORT COMP1_2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 308 EXPORT COMP4_5_6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 309 EXPORT COMP7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 310 EXPORT I2C3_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 311 EXPORT I2C3_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 312 EXPORT USB_HP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 313 EXPORT USB_LP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 314 EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 315 EXPORT TIM20_BRK_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 316 EXPORT TIM20_UP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 317 EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 318 EXPORT TIM20_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 319 EXPORT FPU_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 320 EXPORT SPI4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 323 PVD_IRQHandler
<> 144:ef7eb2e8f9f7 324 TAMP_STAMP_IRQHandler
<> 144:ef7eb2e8f9f7 325 RTC_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 326 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 327 RCC_IRQHandler
<> 144:ef7eb2e8f9f7 328 EXTI0_IRQHandler
<> 144:ef7eb2e8f9f7 329 EXTI1_IRQHandler
<> 144:ef7eb2e8f9f7 330 EXTI2_TSC_IRQHandler
<> 144:ef7eb2e8f9f7 331 EXTI3_IRQHandler
<> 144:ef7eb2e8f9f7 332 EXTI4_IRQHandler
<> 144:ef7eb2e8f9f7 333 DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 334 DMA1_Channel2_IRQHandler
<> 144:ef7eb2e8f9f7 335 DMA1_Channel3_IRQHandler
<> 144:ef7eb2e8f9f7 336 DMA1_Channel4_IRQHandler
<> 144:ef7eb2e8f9f7 337 DMA1_Channel5_IRQHandler
<> 144:ef7eb2e8f9f7 338 DMA1_Channel6_IRQHandler
<> 144:ef7eb2e8f9f7 339 DMA1_Channel7_IRQHandler
<> 144:ef7eb2e8f9f7 340 ADC1_2_IRQHandler
<> 144:ef7eb2e8f9f7 341 USB_HP_CAN_TX_IRQHandler
<> 144:ef7eb2e8f9f7 342 USB_LP_CAN_RX0_IRQHandler
<> 144:ef7eb2e8f9f7 343 CAN_RX1_IRQHandler
<> 144:ef7eb2e8f9f7 344 CAN_SCE_IRQHandler
<> 144:ef7eb2e8f9f7 345 EXTI9_5_IRQHandler
<> 144:ef7eb2e8f9f7 346 TIM1_BRK_TIM15_IRQHandler
<> 144:ef7eb2e8f9f7 347 TIM1_UP_TIM16_IRQHandler
<> 144:ef7eb2e8f9f7 348 TIM1_TRG_COM_TIM17_IRQHandler
<> 144:ef7eb2e8f9f7 349 TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 350 TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 351 TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 352 TIM4_IRQHandler
<> 144:ef7eb2e8f9f7 353 I2C1_EV_IRQHandler
<> 144:ef7eb2e8f9f7 354 I2C1_ER_IRQHandler
<> 144:ef7eb2e8f9f7 355 I2C2_EV_IRQHandler
<> 144:ef7eb2e8f9f7 356 I2C2_ER_IRQHandler
<> 144:ef7eb2e8f9f7 357 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 358 SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 359 USART1_IRQHandler
<> 144:ef7eb2e8f9f7 360 USART2_IRQHandler
<> 144:ef7eb2e8f9f7 361 USART3_IRQHandler
<> 144:ef7eb2e8f9f7 362 EXTI15_10_IRQHandler
<> 144:ef7eb2e8f9f7 363 RTC_Alarm_IRQHandler
<> 144:ef7eb2e8f9f7 364 USBWakeUp_IRQHandler
<> 144:ef7eb2e8f9f7 365 TIM8_BRK_IRQHandler
<> 144:ef7eb2e8f9f7 366 TIM8_UP_IRQHandler
<> 144:ef7eb2e8f9f7 367 TIM8_TRG_COM_IRQHandler
<> 144:ef7eb2e8f9f7 368 TIM8_CC_IRQHandler
<> 144:ef7eb2e8f9f7 369 ADC3_IRQHandler
<> 144:ef7eb2e8f9f7 370 FMC_IRQHandler
<> 144:ef7eb2e8f9f7 371 SPI3_IRQHandler
<> 144:ef7eb2e8f9f7 372 UART4_IRQHandler
<> 144:ef7eb2e8f9f7 373 UART5_IRQHandler
<> 144:ef7eb2e8f9f7 374 TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 375 TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 376 DMA2_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 377 DMA2_Channel2_IRQHandler
<> 144:ef7eb2e8f9f7 378 DMA2_Channel3_IRQHandler
<> 144:ef7eb2e8f9f7 379 DMA2_Channel4_IRQHandler
<> 144:ef7eb2e8f9f7 380 DMA2_Channel5_IRQHandler
<> 144:ef7eb2e8f9f7 381 ADC4_IRQHandler
<> 144:ef7eb2e8f9f7 382 COMP1_2_3_IRQHandler
<> 144:ef7eb2e8f9f7 383 COMP4_5_6_IRQHandler
<> 144:ef7eb2e8f9f7 384 COMP7_IRQHandler
<> 144:ef7eb2e8f9f7 385 I2C3_EV_IRQHandler
<> 144:ef7eb2e8f9f7 386 I2C3_ER_IRQHandler
<> 144:ef7eb2e8f9f7 387 USB_HP_IRQHandler
<> 144:ef7eb2e8f9f7 388 USB_LP_IRQHandler
<> 144:ef7eb2e8f9f7 389 USBWakeUp_RMP_IRQHandler
<> 144:ef7eb2e8f9f7 390 TIM20_BRK_IRQHandler
<> 144:ef7eb2e8f9f7 391 TIM20_UP_IRQHandler
<> 144:ef7eb2e8f9f7 392 TIM20_TRG_COM_IRQHandler
<> 144:ef7eb2e8f9f7 393 TIM20_CC_IRQHandler
<> 144:ef7eb2e8f9f7 394 FPU_IRQHandler
<> 144:ef7eb2e8f9f7 395 SPI4_IRQHandler
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 B .
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 ENDP
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 ALIGN
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 END
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****