mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 170:19eb464bc2be 1 /* mbed Microcontroller Library
Kojto 170:19eb464bc2be 2 * Copyright (c) 2006-2017 ARM Limited
Kojto 170:19eb464bc2be 3 *
Kojto 170:19eb464bc2be 4 * Licensed under the Apache License, Version 2.0 (the "License");
Kojto 170:19eb464bc2be 5 * you may not use this file except in compliance with the License.
Kojto 170:19eb464bc2be 6 * You may obtain a copy of the License at
Kojto 170:19eb464bc2be 7 *
Kojto 170:19eb464bc2be 8 * http://www.apache.org/licenses/LICENSE-2.0
Kojto 170:19eb464bc2be 9 *
Kojto 170:19eb464bc2be 10 * Unless required by applicable law or agreed to in writing, software
Kojto 170:19eb464bc2be 11 * distributed under the License is distributed on an "AS IS" BASIS,
Kojto 170:19eb464bc2be 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 170:19eb464bc2be 13 * See the License for the specific language governing permissions and
Kojto 170:19eb464bc2be 14 * limitations under the License.
Kojto 170:19eb464bc2be 15 */
Kojto 170:19eb464bc2be 16
Kojto 170:19eb464bc2be 17 /**
Kojto 170:19eb464bc2be 18 * This file configures the system clock as follows:
Kojto 170:19eb464bc2be 19 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
Kojto 170:19eb464bc2be 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
Kojto 170:19eb464bc2be 22 * | 3- USE_PLL_HSI (internal 8 MHz)
Kojto 170:19eb464bc2be 23 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 24 * SYSCLK(MHz) | 72
Kojto 170:19eb464bc2be 25 * AHBCLK (MHz) | 72
Kojto 170:19eb464bc2be 26 * APB1CLK (MHz) | 36
Kojto 170:19eb464bc2be 27 * APB2CLK (MHz) | 72
Kojto 170:19eb464bc2be 28 * USB capable | YES
Kojto 170:19eb464bc2be 29 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 30 */
Kojto 170:19eb464bc2be 31
Kojto 170:19eb464bc2be 32
Kojto 170:19eb464bc2be 33 #include "stm32f3xx.h"
AnnaBridge 187:0387e8f68319 34 #include "mbed_error.h"
Kojto 170:19eb464bc2be 35
Kojto 170:19eb464bc2be 36 /*!< Uncomment the following line if you need to relocate your vector Table in
Kojto 170:19eb464bc2be 37 Internal SRAM. */
Kojto 170:19eb464bc2be 38 /* #define VECT_TAB_SRAM */
Kojto 170:19eb464bc2be 39 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
Kojto 170:19eb464bc2be 40 This value must be a multiple of 0x200. */
Kojto 170:19eb464bc2be 41
Kojto 170:19eb464bc2be 42 // clock source is selected with CLOCK_SOURCE in json config
Kojto 170:19eb464bc2be 43 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
Kojto 170:19eb464bc2be 44 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
Kojto 170:19eb464bc2be 45 #define USE_PLL_HSI 0x2 // Use HSI internal clock
Kojto 170:19eb464bc2be 46
Kojto 170:19eb464bc2be 47 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
Kojto 170:19eb464bc2be 48 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
Kojto 170:19eb464bc2be 49 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
Kojto 170:19eb464bc2be 50
Kojto 170:19eb464bc2be 51 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 52 uint8_t SetSysClock_PLL_HSI(void);
Kojto 170:19eb464bc2be 53 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
Kojto 170:19eb464bc2be 54
Kojto 170:19eb464bc2be 55 /**
Kojto 170:19eb464bc2be 56 * @brief Setup the microcontroller system
Kojto 170:19eb464bc2be 57 * Initialize the FPU setting, vector table location and the PLL configuration is reset.
Kojto 170:19eb464bc2be 58 * @param None
Kojto 170:19eb464bc2be 59 * @retval None
Kojto 170:19eb464bc2be 60 */
Kojto 170:19eb464bc2be 61 void SystemInit(void)
Kojto 170:19eb464bc2be 62 {
Kojto 170:19eb464bc2be 63 /* FPU settings ------------------------------------------------------------*/
Kojto 170:19eb464bc2be 64 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 187:0387e8f68319 65 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
Kojto 170:19eb464bc2be 66 #endif
Kojto 170:19eb464bc2be 67
Kojto 170:19eb464bc2be 68 /* Reset the RCC clock configuration to the default reset state ------------*/
Kojto 170:19eb464bc2be 69 /* Set HSION bit */
Kojto 170:19eb464bc2be 70 RCC->CR |= 0x00000001U;
Kojto 170:19eb464bc2be 71
Kojto 170:19eb464bc2be 72 /* Reset CFGR register */
Kojto 170:19eb464bc2be 73 RCC->CFGR &= 0xF87FC00CU;
Kojto 170:19eb464bc2be 74
Kojto 170:19eb464bc2be 75 /* Reset HSEON, CSSON and PLLON bits */
Kojto 170:19eb464bc2be 76 RCC->CR &= 0xFEF6FFFFU;
Kojto 170:19eb464bc2be 77
Kojto 170:19eb464bc2be 78 /* Reset HSEBYP bit */
Kojto 170:19eb464bc2be 79 RCC->CR &= 0xFFFBFFFFU;
Kojto 170:19eb464bc2be 80
Kojto 170:19eb464bc2be 81 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
Kojto 170:19eb464bc2be 82 RCC->CFGR &= 0xFF80FFFFU;
Kojto 170:19eb464bc2be 83
Kojto 170:19eb464bc2be 84 /* Reset PREDIV1[3:0] bits */
Kojto 170:19eb464bc2be 85 RCC->CFGR2 &= 0xFFFFFFF0U;
Kojto 170:19eb464bc2be 86
Kojto 170:19eb464bc2be 87 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
Kojto 170:19eb464bc2be 88 RCC->CFGR3 &= 0xFF00FCCCU;
Kojto 170:19eb464bc2be 89
Kojto 170:19eb464bc2be 90 /* Disable all interrupts */
Kojto 170:19eb464bc2be 91 RCC->CIR = 0x00000000U;
Kojto 170:19eb464bc2be 92
Kojto 170:19eb464bc2be 93 #ifdef VECT_TAB_SRAM
Kojto 170:19eb464bc2be 94 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
Kojto 170:19eb464bc2be 95 #else
Kojto 170:19eb464bc2be 96 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
Kojto 170:19eb464bc2be 97 #endif
Kojto 170:19eb464bc2be 98
Kojto 170:19eb464bc2be 99 }
Kojto 170:19eb464bc2be 100
Kojto 170:19eb464bc2be 101
Kojto 170:19eb464bc2be 102 /**
Kojto 170:19eb464bc2be 103 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
Kojto 170:19eb464bc2be 104 * AHB/APBx prescalers and Flash settings
Kojto 170:19eb464bc2be 105 * @note This function should be called only once the RCC clock configuration
Kojto 170:19eb464bc2be 106 * is reset to the default reset state (done in SystemInit() function).
Kojto 170:19eb464bc2be 107 * @param None
Kojto 170:19eb464bc2be 108 * @retval None
Kojto 170:19eb464bc2be 109 */
Kojto 170:19eb464bc2be 110
Kojto 170:19eb464bc2be 111 void SetSysClock(void)
Kojto 170:19eb464bc2be 112 {
Kojto 170:19eb464bc2be 113 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
Kojto 170:19eb464bc2be 114 /* 1- Try to start with HSE and external clock */
Kojto 170:19eb464bc2be 115 if (SetSysClock_PLL_HSE(1) == 0)
Kojto 170:19eb464bc2be 116 #endif
Kojto 170:19eb464bc2be 117 {
Kojto 170:19eb464bc2be 118 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
Kojto 170:19eb464bc2be 119 /* 2- If fail try to start with HSE and external xtal */
Kojto 170:19eb464bc2be 120 if (SetSysClock_PLL_HSE(0) == 0)
Kojto 170:19eb464bc2be 121 #endif
Kojto 170:19eb464bc2be 122 {
Kojto 170:19eb464bc2be 123 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 124 /* 3- If fail start with HSI clock */
Kojto 170:19eb464bc2be 125 if (SetSysClock_PLL_HSI() == 0)
Kojto 170:19eb464bc2be 126 #endif
Kojto 170:19eb464bc2be 127 {
AnnaBridge 187:0387e8f68319 128 {
AnnaBridge 187:0387e8f68319 129 error("SetSysClock failed\n");
Kojto 170:19eb464bc2be 130 }
Kojto 170:19eb464bc2be 131 }
Kojto 170:19eb464bc2be 132 }
Kojto 170:19eb464bc2be 133 }
Kojto 170:19eb464bc2be 134
Kojto 170:19eb464bc2be 135 /* Output clock on MCO2 pin(PC9) for debugging purpose */
Kojto 170:19eb464bc2be 136 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
Kojto 170:19eb464bc2be 137 }
Kojto 170:19eb464bc2be 138
Kojto 170:19eb464bc2be 139 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
Kojto 170:19eb464bc2be 140 /******************************************************************************/
Kojto 170:19eb464bc2be 141 /* PLL (clocked by HSE) used as System clock source */
Kojto 170:19eb464bc2be 142 /******************************************************************************/
Kojto 170:19eb464bc2be 143 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
Kojto 170:19eb464bc2be 144 {
Kojto 170:19eb464bc2be 145 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Kojto 170:19eb464bc2be 146 RCC_OscInitTypeDef RCC_OscInitStruct;
Kojto 170:19eb464bc2be 147 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
Kojto 170:19eb464bc2be 148
Kojto 170:19eb464bc2be 149 /* Enable HSE oscillator and activate PLL with HSE as source */
Kojto 170:19eb464bc2be 150 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
Kojto 170:19eb464bc2be 151 if (bypass == 0) {
Kojto 170:19eb464bc2be 152 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
Kojto 170:19eb464bc2be 153 } else {
Kojto 170:19eb464bc2be 154 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
Kojto 170:19eb464bc2be 155 }
Kojto 170:19eb464bc2be 156 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 157 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
Kojto 170:19eb464bc2be 158 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
Kojto 170:19eb464bc2be 159 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
Kojto 170:19eb464bc2be 160 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 161 return 0; // FAIL
Kojto 170:19eb464bc2be 162 }
Kojto 170:19eb464bc2be 163
Kojto 170:19eb464bc2be 164 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
Kojto 170:19eb464bc2be 165 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 166 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
Kojto 170:19eb464bc2be 167 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
Kojto 170:19eb464bc2be 168 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
Kojto 170:19eb464bc2be 169 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
Kojto 170:19eb464bc2be 170 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
Kojto 170:19eb464bc2be 171 return 0; // FAIL
Kojto 170:19eb464bc2be 172 }
Kojto 170:19eb464bc2be 173
Kojto 170:19eb464bc2be 174 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
Kojto 170:19eb464bc2be 175 RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
Kojto 170:19eb464bc2be 176 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
Kojto 170:19eb464bc2be 177 return 0; // FAIL
Kojto 170:19eb464bc2be 178 }
Kojto 170:19eb464bc2be 179
Kojto 170:19eb464bc2be 180 /* Output clock on MCO1 pin(PA8) for debugging purpose */
Kojto 170:19eb464bc2be 181 //if (bypass == 0)
Kojto 170:19eb464bc2be 182 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
Kojto 170:19eb464bc2be 183 //else
Kojto 170:19eb464bc2be 184 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
Kojto 170:19eb464bc2be 185
Kojto 170:19eb464bc2be 186 return 1; // OK
Kojto 170:19eb464bc2be 187 }
Kojto 170:19eb464bc2be 188 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
Kojto 170:19eb464bc2be 189
Kojto 170:19eb464bc2be 190 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 191 /******************************************************************************/
Kojto 170:19eb464bc2be 192 /* PLL (clocked by HSI) used as System clock source */
Kojto 170:19eb464bc2be 193 /******************************************************************************/
Kojto 170:19eb464bc2be 194 uint8_t SetSysClock_PLL_HSI(void)
Kojto 170:19eb464bc2be 195 {
Kojto 170:19eb464bc2be 196 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Kojto 170:19eb464bc2be 197 RCC_OscInitTypeDef RCC_OscInitStruct;
Kojto 170:19eb464bc2be 198 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
Kojto 170:19eb464bc2be 199
Kojto 170:19eb464bc2be 200 /* Enable HSI oscillator and activate PLL with HSI as source */
Kojto 170:19eb464bc2be 201 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
Kojto 170:19eb464bc2be 202 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
Kojto 170:19eb464bc2be 203 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
Kojto 170:19eb464bc2be 204 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
Kojto 170:19eb464bc2be 205 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 206 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
Kojto 170:19eb464bc2be 207 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
Kojto 170:19eb464bc2be 208 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz/1 * 9)
Kojto 170:19eb464bc2be 209 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 210 return 0; // FAIL
Kojto 170:19eb464bc2be 211 }
Kojto 170:19eb464bc2be 212
Kojto 170:19eb464bc2be 213 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
Kojto 170:19eb464bc2be 214 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 215 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
Kojto 170:19eb464bc2be 216 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
Kojto 170:19eb464bc2be 217 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
Kojto 170:19eb464bc2be 218 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
Kojto 170:19eb464bc2be 219 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
Kojto 170:19eb464bc2be 220 return 0; // FAIL
Kojto 170:19eb464bc2be 221 }
Kojto 170:19eb464bc2be 222
Kojto 170:19eb464bc2be 223 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
Kojto 170:19eb464bc2be 224 RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
Kojto 170:19eb464bc2be 225 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
Kojto 170:19eb464bc2be 226 return 0; // FAIL
Kojto 170:19eb464bc2be 227 }
Kojto 170:19eb464bc2be 228
Kojto 170:19eb464bc2be 229 /* Output clock on MCO1 pin(PA8) for debugging purpose */
Kojto 170:19eb464bc2be 230 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
Kojto 170:19eb464bc2be 231
Kojto 170:19eb464bc2be 232 return 1; // OK
Kojto 170:19eb464bc2be 233 }
Kojto 170:19eb464bc2be 234 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */