mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pwr.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_pwr.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief PWR HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Power Controller (PWR) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 ******************************************************************************
<> 144:ef7eb2e8f9f7 14 * @attention
<> 144:ef7eb2e8f9f7 15 *
AnnaBridge 167:e84263d55307 16 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 19 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 20 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 21 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 23 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 24 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 26 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 27 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 39 *
<> 144:ef7eb2e8f9f7 40 ******************************************************************************
<> 144:ef7eb2e8f9f7 41 */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 44 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @defgroup PWR PWR
<> 144:ef7eb2e8f9f7 51 * @brief PWR HAL module driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #ifdef HAL_PWR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @addtogroup PWR_Private_Constants
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
AnnaBridge 167:e84263d55307 66 #define PVD_MODE_IT 0x00010000U
AnnaBridge 167:e84263d55307 67 #define PVD_MODE_EVT 0x00020000U
AnnaBridge 167:e84263d55307 68 #define PVD_RISING_EDGE 0x00000001U
AnnaBridge 167:e84263d55307 69 #define PVD_FALLING_EDGE 0x00000002U
<> 144:ef7eb2e8f9f7 70 /**
<> 144:ef7eb2e8f9f7 71 * @}
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /**
<> 144:ef7eb2e8f9f7 75 * @}
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 78 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 79 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 80 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @defgroup PWR_Exported_Functions PWR Exported Functions
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 87 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 @verbatim
<> 144:ef7eb2e8f9f7 90 ===============================================================================
<> 144:ef7eb2e8f9f7 91 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 92 ===============================================================================
<> 144:ef7eb2e8f9f7 93 [..]
<> 144:ef7eb2e8f9f7 94 After reset, the backup domain (RTC registers, RTC backup data
<> 144:ef7eb2e8f9f7 95 registers and backup SRAM) is protected against possible unwanted
<> 144:ef7eb2e8f9f7 96 write accesses.
<> 144:ef7eb2e8f9f7 97 To enable access to the RTC Domain and RTC registers, proceed as follows:
<> 144:ef7eb2e8f9f7 98 (+) Enable the Power Controller (PWR) APB1 interface clock using the
<> 144:ef7eb2e8f9f7 99 __HAL_RCC_PWR_CLK_ENABLE() macro.
<> 144:ef7eb2e8f9f7 100 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 @endverbatim
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 108 * @retval None
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110 void HAL_PWR_DeInit(void)
<> 144:ef7eb2e8f9f7 111 {
<> 144:ef7eb2e8f9f7 112 __HAL_RCC_PWR_FORCE_RESET();
<> 144:ef7eb2e8f9f7 113 __HAL_RCC_PWR_RELEASE_RESET();
<> 144:ef7eb2e8f9f7 114 }
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief Enables access to the backup domain (RTC registers, RTC
<> 144:ef7eb2e8f9f7 118 * backup data registers and backup SRAM).
<> 144:ef7eb2e8f9f7 119 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
<> 144:ef7eb2e8f9f7 120 * Backup Domain Access should be kept enabled.
<> 144:ef7eb2e8f9f7 121 * @retval None
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 void HAL_PWR_EnableBkUpAccess(void)
<> 144:ef7eb2e8f9f7 124 {
<> 144:ef7eb2e8f9f7 125 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
<> 144:ef7eb2e8f9f7 126 }
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /**
<> 144:ef7eb2e8f9f7 129 * @brief Disables access to the backup domain (RTC registers, RTC
<> 144:ef7eb2e8f9f7 130 * backup data registers and backup SRAM).
<> 144:ef7eb2e8f9f7 131 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
<> 144:ef7eb2e8f9f7 132 * Backup Domain Access should be kept enabled.
<> 144:ef7eb2e8f9f7 133 * @retval None
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135 void HAL_PWR_DisableBkUpAccess(void)
<> 144:ef7eb2e8f9f7 136 {
<> 144:ef7eb2e8f9f7 137 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @}
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 145 * @brief Low Power modes configuration functions
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 @verbatim
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 ===============================================================================
<> 144:ef7eb2e8f9f7 150 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 151 ===============================================================================
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 *** PVD configuration ***
<> 144:ef7eb2e8f9f7 154 =========================
<> 144:ef7eb2e8f9f7 155 [..]
<> 144:ef7eb2e8f9f7 156 (+) The PVD is used to monitor the VDD power supply by comparing it to a
<> 144:ef7eb2e8f9f7 157 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
<> 144:ef7eb2e8f9f7 158 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
<> 144:ef7eb2e8f9f7 159 than the PVD threshold. This event is internally connected to the EXTI
<> 144:ef7eb2e8f9f7 160 line16 and can generate an interrupt if enabled. This is done through
<> 144:ef7eb2e8f9f7 161 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
<> 144:ef7eb2e8f9f7 162 (+) The PVD is stopped in Standby mode.
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 *** Wake-up pin configuration ***
<> 144:ef7eb2e8f9f7 165 ================================
<> 144:ef7eb2e8f9f7 166 [..]
<> 144:ef7eb2e8f9f7 167 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
<> 144:ef7eb2e8f9f7 168 forced in input pull-down configuration and is active on rising edges.
<> 144:ef7eb2e8f9f7 169 (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 *** Low Power modes configuration ***
<> 144:ef7eb2e8f9f7 172 =====================================
<> 144:ef7eb2e8f9f7 173 [..]
<> 144:ef7eb2e8f9f7 174 The devices feature 3 low-power modes:
<> 144:ef7eb2e8f9f7 175 (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
<> 144:ef7eb2e8f9f7 176 (+) Stop mode: all clocks are stopped, regulator running, regulator
<> 144:ef7eb2e8f9f7 177 in low power mode
<> 144:ef7eb2e8f9f7 178 (+) Standby mode: 1.2V domain powered off.
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 *** Sleep mode ***
<> 144:ef7eb2e8f9f7 181 ==================
<> 144:ef7eb2e8f9f7 182 [..]
<> 144:ef7eb2e8f9f7 183 (+) Entry:
<> 144:ef7eb2e8f9f7 184 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
<> 144:ef7eb2e8f9f7 185 functions with
<> 144:ef7eb2e8f9f7 186 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
<> 144:ef7eb2e8f9f7 187 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 -@@- The Regulator parameter is not used for the STM32F2 family
<> 144:ef7eb2e8f9f7 190 and is kept as parameter just to maintain compatibility with the
<> 144:ef7eb2e8f9f7 191 lower power families (STM32L).
<> 144:ef7eb2e8f9f7 192 (+) Exit:
<> 144:ef7eb2e8f9f7 193 Any peripheral interrupt acknowledged by the nested vectored interrupt
<> 144:ef7eb2e8f9f7 194 controller (NVIC) can wake up the device from Sleep mode.
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 *** Stop mode ***
<> 144:ef7eb2e8f9f7 197 =================
<> 144:ef7eb2e8f9f7 198 [..]
<> 144:ef7eb2e8f9f7 199 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
<> 144:ef7eb2e8f9f7 200 and the HSE RC oscillators are disabled. Internal SRAM and register contents
<> 144:ef7eb2e8f9f7 201 are preserved.
<> 144:ef7eb2e8f9f7 202 The voltage regulator can be configured either in normal or low-power mode.
<> 144:ef7eb2e8f9f7 203 To minimize the consumption In Stop mode, FLASH can be powered off before
<> 144:ef7eb2e8f9f7 204 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
<> 144:ef7eb2e8f9f7 205 It can be switched on again by software after exiting the Stop mode using
<> 144:ef7eb2e8f9f7 206 the HAL_PWREx_DisableFlashPowerDown() function.
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 (+) Entry:
<> 144:ef7eb2e8f9f7 209 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
<> 144:ef7eb2e8f9f7 210 function with:
<> 144:ef7eb2e8f9f7 211 (++) Main regulator ON.
<> 144:ef7eb2e8f9f7 212 (++) Low Power regulator ON.
<> 144:ef7eb2e8f9f7 213 (+) Exit:
<> 144:ef7eb2e8f9f7 214 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 *** Standby mode ***
<> 144:ef7eb2e8f9f7 217 ====================
<> 144:ef7eb2e8f9f7 218 [..]
<> 144:ef7eb2e8f9f7 219 (+)
<> 144:ef7eb2e8f9f7 220 The Standby mode allows to achieve the lowest power consumption. It is based
<> 144:ef7eb2e8f9f7 221 on the Cortex-M3 deep sleep mode, with the voltage regulator disabled.
<> 144:ef7eb2e8f9f7 222 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
<> 144:ef7eb2e8f9f7 223 the HSE oscillator are also switched off. SRAM and register contents are lost
<> 144:ef7eb2e8f9f7 224 except for the RTC registers, RTC backup registers, backup SRAM and Standby
<> 144:ef7eb2e8f9f7 225 circuitry.
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 The voltage regulator is OFF.
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 (++) Entry:
<> 144:ef7eb2e8f9f7 230 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
<> 144:ef7eb2e8f9f7 231 (++) Exit:
<> 144:ef7eb2e8f9f7 232 (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
<> 144:ef7eb2e8f9f7 233 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 *** Auto-wake-up (AWU) from low-power mode ***
<> 144:ef7eb2e8f9f7 236 =============================================
<> 144:ef7eb2e8f9f7 237 [..]
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
<> 144:ef7eb2e8f9f7 240 Wake-up event, a tamper event or a time-stamp event, without depending on
<> 144:ef7eb2e8f9f7 241 an external interrupt (Auto-wake-up mode).
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
<> 144:ef7eb2e8f9f7 246 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
<> 144:ef7eb2e8f9f7 249 is necessary to configure the RTC to detect the tamper or time stamp event using the
<> 144:ef7eb2e8f9f7 250 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
<> 144:ef7eb2e8f9f7 253 configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 @endverbatim
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
<> 144:ef7eb2e8f9f7 261 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
<> 144:ef7eb2e8f9f7 262 * information for the PVD.
<> 144:ef7eb2e8f9f7 263 * @note Refer to the electrical characteristics of your device datasheet for
<> 144:ef7eb2e8f9f7 264 * more details about the voltage threshold corresponding to each
<> 144:ef7eb2e8f9f7 265 * detection level.
<> 144:ef7eb2e8f9f7 266 * @retval None
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 /* Check the parameters */
<> 144:ef7eb2e8f9f7 271 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
<> 144:ef7eb2e8f9f7 272 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Set PLS[7:5] bits according to PVDLevel value */
<> 144:ef7eb2e8f9f7 275 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 278 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 279 __HAL_PWR_PVD_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 280 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 281 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 284 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 __HAL_PWR_PVD_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Configure event mode */
<> 144:ef7eb2e8f9f7 290 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Configure the edge */
<> 144:ef7eb2e8f9f7 296 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 304 }
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @brief Enables the Power Voltage Detector(PVD).
<> 144:ef7eb2e8f9f7 309 * @retval None
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 void HAL_PWR_EnablePVD(void)
<> 144:ef7eb2e8f9f7 312 {
<> 144:ef7eb2e8f9f7 313 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @brief Disables the Power Voltage Detector(PVD).
<> 144:ef7eb2e8f9f7 318 * @retval None
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 void HAL_PWR_DisablePVD(void)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @brief Enables the Wake-up PINx functionality.
<> 144:ef7eb2e8f9f7 327 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
<> 144:ef7eb2e8f9f7 328 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 329 * @arg PWR_WAKEUP_PIN1
<> 144:ef7eb2e8f9f7 330 * @retval None
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 /* Check the parameter */
<> 144:ef7eb2e8f9f7 335 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* Enable the wake up pin */
<> 144:ef7eb2e8f9f7 338 SET_BIT(PWR->CSR, WakeUpPinx);
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @brief Disables the Wake-up PINx functionality.
<> 144:ef7eb2e8f9f7 343 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
<> 144:ef7eb2e8f9f7 344 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 345 * @arg PWR_WAKEUP_PIN1
<> 144:ef7eb2e8f9f7 346 * @retval None
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 /* Check the parameter */
<> 144:ef7eb2e8f9f7 351 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Disable the wake up pin */
<> 144:ef7eb2e8f9f7 354 CLEAR_BIT(PWR->CSR, WakeUpPinx);
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /**
<> 144:ef7eb2e8f9f7 358 * @brief Enters Sleep mode.
<> 144:ef7eb2e8f9f7 359 *
<> 144:ef7eb2e8f9f7 360 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 361 *
<> 144:ef7eb2e8f9f7 362 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
<> 144:ef7eb2e8f9f7 363 * systick interrupt when used as time base for Timeout
<> 144:ef7eb2e8f9f7 364 *
<> 144:ef7eb2e8f9f7 365 * @param Regulator: Specifies the regulator state in SLEEP mode.
<> 144:ef7eb2e8f9f7 366 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 367 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
<> 144:ef7eb2e8f9f7 368 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
<> 144:ef7eb2e8f9f7 369 * @note This parameter is not used for the STM32F2 family and is kept as parameter
<> 144:ef7eb2e8f9f7 370 * just to maintain compatibility with the lower power families.
<> 144:ef7eb2e8f9f7 371 * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 372 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 373 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
<> 144:ef7eb2e8f9f7 374 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
<> 144:ef7eb2e8f9f7 375 * @retval None
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
<> 144:ef7eb2e8f9f7 378 {
AnnaBridge 167:e84263d55307 379 /* Prevent unused argument(s) compilation warning */
AnnaBridge 167:e84263d55307 380 UNUSED(Regulator);
AnnaBridge 167:e84263d55307 381
<> 144:ef7eb2e8f9f7 382 /* Check the parameters */
<> 144:ef7eb2e8f9f7 383 assert_param(IS_PWR_REGULATOR(Regulator));
<> 144:ef7eb2e8f9f7 384 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Clear SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 387 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Select SLEEP mode entry -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 390 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 393 __WFI();
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395 else
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 398 __SEV();
<> 144:ef7eb2e8f9f7 399 __WFE();
<> 144:ef7eb2e8f9f7 400 __WFE();
<> 144:ef7eb2e8f9f7 401 }
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /**
<> 144:ef7eb2e8f9f7 405 * @brief Enters Stop mode.
<> 144:ef7eb2e8f9f7 406 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 407 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
<> 144:ef7eb2e8f9f7 408 * the HSI RC oscillator is selected as system clock.
<> 144:ef7eb2e8f9f7 409 * @note When the voltage regulator operates in low power mode, an additional
<> 144:ef7eb2e8f9f7 410 * startup delay is incurred when waking up from Stop mode.
<> 144:ef7eb2e8f9f7 411 * By keeping the internal regulator ON during Stop mode, the consumption
<> 144:ef7eb2e8f9f7 412 * is higher although the startup time is reduced.
<> 144:ef7eb2e8f9f7 413 * @param Regulator: Specifies the regulator state in Stop mode.
<> 144:ef7eb2e8f9f7 414 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 415 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
<> 144:ef7eb2e8f9f7 416 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
<> 144:ef7eb2e8f9f7 417 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 418 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 419 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
<> 144:ef7eb2e8f9f7 420 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
<> 144:ef7eb2e8f9f7 421 * @retval None
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 /* Check the parameters */
<> 144:ef7eb2e8f9f7 426 assert_param(IS_PWR_REGULATOR(Regulator));
<> 144:ef7eb2e8f9f7 427 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
<> 144:ef7eb2e8f9f7 430 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 433 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Select Stop mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 436 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 439 __WFI();
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441 else
<> 144:ef7eb2e8f9f7 442 {
<> 144:ef7eb2e8f9f7 443 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 444 __SEV();
<> 144:ef7eb2e8f9f7 445 __WFE();
<> 144:ef7eb2e8f9f7 446 __WFE();
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 449 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @brief Enters Standby mode.
<> 144:ef7eb2e8f9f7 454 * @note In Standby mode, all I/O pins are high impedance except for:
<> 144:ef7eb2e8f9f7 455 * - Reset pad (still available)
<> 144:ef7eb2e8f9f7 456 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
<> 144:ef7eb2e8f9f7 457 * Alarm out, or RTC clock calibration out.
<> 144:ef7eb2e8f9f7 458 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
<> 144:ef7eb2e8f9f7 459 * - WKUP pin 1 (PA0) if enabled.
<> 144:ef7eb2e8f9f7 460 * @retval None
<> 144:ef7eb2e8f9f7 461 */
<> 144:ef7eb2e8f9f7 462 void HAL_PWR_EnterSTANDBYMode(void)
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 /* Select Standby mode */
<> 144:ef7eb2e8f9f7 465 SET_BIT(PWR->CR, PWR_CR_PDDS);
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 468 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* This option is used to ensure that store operations are completed */
<> 144:ef7eb2e8f9f7 471 #if defined ( __CC_ARM)
<> 144:ef7eb2e8f9f7 472 __force_stores();
<> 144:ef7eb2e8f9f7 473 #endif
<> 144:ef7eb2e8f9f7 474 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 475 __WFI();
<> 144:ef7eb2e8f9f7 476 }
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /**
<> 144:ef7eb2e8f9f7 479 * @brief This function handles the PWR PVD interrupt request.
<> 144:ef7eb2e8f9f7 480 * @note This API should be called under the PVD_IRQHandler().
<> 144:ef7eb2e8f9f7 481 * @retval None
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 void HAL_PWR_PVD_IRQHandler(void)
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 /* Check PWR Exti flag */
<> 144:ef7eb2e8f9f7 486 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 /* PWR PVD interrupt user callback */
<> 144:ef7eb2e8f9f7 489 HAL_PWR_PVDCallback();
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Clear PWR Exti pending bit */
<> 144:ef7eb2e8f9f7 492 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /**
<> 144:ef7eb2e8f9f7 497 * @brief PWR PVD interrupt callback
<> 144:ef7eb2e8f9f7 498 * @retval None
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 __weak void HAL_PWR_PVDCallback(void)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 503 the HAL_PWR_PVDCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 504 */
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /**
<> 144:ef7eb2e8f9f7 508 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
<> 144:ef7eb2e8f9f7 509 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
<> 144:ef7eb2e8f9f7 510 * re-enters SLEEP mode when an interruption handling is over.
<> 144:ef7eb2e8f9f7 511 * Setting this bit is useful when the processor is expected to run only on
<> 144:ef7eb2e8f9f7 512 * interruptions handling.
<> 144:ef7eb2e8f9f7 513 * @retval None
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515 void HAL_PWR_EnableSleepOnExit(void)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 /* Set SLEEPONEXIT bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 518 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /**
<> 144:ef7eb2e8f9f7 522 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
<> 144:ef7eb2e8f9f7 523 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
<> 144:ef7eb2e8f9f7 524 * re-enters SLEEP mode when an interruption handling is over.
<> 144:ef7eb2e8f9f7 525 * @retval None
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 void HAL_PWR_DisableSleepOnExit(void)
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 530 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @brief Enables CORTEX M3 SEVONPEND bit.
<> 144:ef7eb2e8f9f7 535 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
<> 144:ef7eb2e8f9f7 536 * WFE to wake up when an interrupt moves from inactive to pended.
<> 144:ef7eb2e8f9f7 537 * @retval None
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539 void HAL_PWR_EnableSEVOnPend(void)
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 /* Set SEVONPEND bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 542 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /**
<> 144:ef7eb2e8f9f7 546 * @brief Disables CORTEX M3 SEVONPEND bit.
<> 144:ef7eb2e8f9f7 547 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
<> 144:ef7eb2e8f9f7 548 * WFE to wake up when an interrupt moves from inactive to pended.
<> 144:ef7eb2e8f9f7 549 * @retval None
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551 void HAL_PWR_DisableSEVOnPend(void)
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 /* Clear SEVONPEND bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 554 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @}
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @}
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 #endif /* HAL_PWR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 566 /**
<> 144:ef7eb2e8f9f7 567 * @}
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /**
<> 144:ef7eb2e8f9f7 571 * @}
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/