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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_spi.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 187:0387e8f68319

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:e614a9f1c9e2	1	/**
AnnaBridge	165:e614a9f1c9e2	2	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	3	* @file stm32f1xx_ll_spi.h
AnnaBridge	165:e614a9f1c9e2	4	* @author MCD Application Team
AnnaBridge	165:e614a9f1c9e2	5	* @brief Header file of SPI LL module.
AnnaBridge	165:e614a9f1c9e2	6	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	7	* @attention
AnnaBridge	165:e614a9f1c9e2	8	*
AnnaBridge	165:e614a9f1c9e2	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	165:e614a9f1c9e2	10	*
AnnaBridge	165:e614a9f1c9e2	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	165:e614a9f1c9e2	12	* are permitted provided that the following conditions are met:
AnnaBridge	165:e614a9f1c9e2	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	165:e614a9f1c9e2	14	* this list of conditions and the following disclaimer.
AnnaBridge	165:e614a9f1c9e2	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	165:e614a9f1c9e2	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	165:e614a9f1c9e2	17	* and/or other materials provided with the distribution.
AnnaBridge	165:e614a9f1c9e2	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	165:e614a9f1c9e2	19	* may be used to endorse or promote products derived from this software
AnnaBridge	165:e614a9f1c9e2	20	* without specific prior written permission.
AnnaBridge	165:e614a9f1c9e2	21	*
AnnaBridge	165:e614a9f1c9e2	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	165:e614a9f1c9e2	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	165:e614a9f1c9e2	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	165:e614a9f1c9e2	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	165:e614a9f1c9e2	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	165:e614a9f1c9e2	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	165:e614a9f1c9e2	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	165:e614a9f1c9e2	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	165:e614a9f1c9e2	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	165:e614a9f1c9e2	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	165:e614a9f1c9e2	32	*
AnnaBridge	165:e614a9f1c9e2	33	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	34	*/
AnnaBridge	165:e614a9f1c9e2	35
AnnaBridge	165:e614a9f1c9e2	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	37	#ifndef __STM32F1xx_LL_SPI_H
AnnaBridge	165:e614a9f1c9e2	38	#define __STM32F1xx_LL_SPI_H
AnnaBridge	165:e614a9f1c9e2	39
AnnaBridge	165:e614a9f1c9e2	40	#ifdef __cplusplus
AnnaBridge	165:e614a9f1c9e2	41	extern "C" {
AnnaBridge	165:e614a9f1c9e2	42	#endif
AnnaBridge	165:e614a9f1c9e2	43
AnnaBridge	165:e614a9f1c9e2	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	45	#include "stm32f1xx.h"
AnnaBridge	165:e614a9f1c9e2	46
AnnaBridge	165:e614a9f1c9e2	47	/** @addtogroup STM32F1xx_LL_Driver
AnnaBridge	165:e614a9f1c9e2	48	* @{
AnnaBridge	165:e614a9f1c9e2	49	*/
AnnaBridge	165:e614a9f1c9e2	50
AnnaBridge	165:e614a9f1c9e2	51	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3)
AnnaBridge	165:e614a9f1c9e2	52
AnnaBridge	165:e614a9f1c9e2	53	/** @defgroup SPI_LL SPI
AnnaBridge	165:e614a9f1c9e2	54	* @{
AnnaBridge	165:e614a9f1c9e2	55	*/
AnnaBridge	165:e614a9f1c9e2	56
AnnaBridge	165:e614a9f1c9e2	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	59	/* Private macros ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	60
AnnaBridge	165:e614a9f1c9e2	61	/* Exported types ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	62	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	63	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge	165:e614a9f1c9e2	64	* @{
AnnaBridge	165:e614a9f1c9e2	65	*/
AnnaBridge	165:e614a9f1c9e2	66
AnnaBridge	165:e614a9f1c9e2	67	/**
AnnaBridge	165:e614a9f1c9e2	68	* @brief SPI Init structures definition
AnnaBridge	165:e614a9f1c9e2	69	*/
AnnaBridge	165:e614a9f1c9e2	70	typedef struct
AnnaBridge	165:e614a9f1c9e2	71	{
AnnaBridge	165:e614a9f1c9e2	72	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	165:e614a9f1c9e2	73	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	165:e614a9f1c9e2	74
AnnaBridge	165:e614a9f1c9e2	75	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	165:e614a9f1c9e2	76
AnnaBridge	165:e614a9f1c9e2	77	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	165:e614a9f1c9e2	78	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	165:e614a9f1c9e2	79
AnnaBridge	165:e614a9f1c9e2	80	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	165:e614a9f1c9e2	81
AnnaBridge	165:e614a9f1c9e2	82	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	165:e614a9f1c9e2	83	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	165:e614a9f1c9e2	84
AnnaBridge	165:e614a9f1c9e2	85	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	165:e614a9f1c9e2	86
AnnaBridge	165:e614a9f1c9e2	87	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	165:e614a9f1c9e2	88	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	165:e614a9f1c9e2	89
AnnaBridge	165:e614a9f1c9e2	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	165:e614a9f1c9e2	91
AnnaBridge	165:e614a9f1c9e2	92	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	165:e614a9f1c9e2	93	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	165:e614a9f1c9e2	94
AnnaBridge	165:e614a9f1c9e2	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	165:e614a9f1c9e2	96
AnnaBridge	165:e614a9f1c9e2	97	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	165:e614a9f1c9e2	98	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	165:e614a9f1c9e2	99
AnnaBridge	165:e614a9f1c9e2	100	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	165:e614a9f1c9e2	101
AnnaBridge	165:e614a9f1c9e2	102	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	165:e614a9f1c9e2	103	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	165:e614a9f1c9e2	104	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	165:e614a9f1c9e2	105
AnnaBridge	165:e614a9f1c9e2	106	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	165:e614a9f1c9e2	107
AnnaBridge	165:e614a9f1c9e2	108	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	165:e614a9f1c9e2	109	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	165:e614a9f1c9e2	110
AnnaBridge	165:e614a9f1c9e2	111	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	165:e614a9f1c9e2	112
AnnaBridge	165:e614a9f1c9e2	113	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	165:e614a9f1c9e2	114	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	165:e614a9f1c9e2	115
AnnaBridge	165:e614a9f1c9e2	116	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	165:e614a9f1c9e2	117
AnnaBridge	165:e614a9f1c9e2	118	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	165:e614a9f1c9e2	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge	165:e614a9f1c9e2	120
AnnaBridge	165:e614a9f1c9e2	121	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	165:e614a9f1c9e2	122
AnnaBridge	165:e614a9f1c9e2	123	} LL_SPI_InitTypeDef;
AnnaBridge	165:e614a9f1c9e2	124
AnnaBridge	165:e614a9f1c9e2	125	/**
AnnaBridge	165:e614a9f1c9e2	126	* @}
AnnaBridge	165:e614a9f1c9e2	127	*/
AnnaBridge	165:e614a9f1c9e2	128	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	129
AnnaBridge	165:e614a9f1c9e2	130	/* Exported constants --------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	131	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	165:e614a9f1c9e2	132	* @{
AnnaBridge	165:e614a9f1c9e2	133	*/
AnnaBridge	165:e614a9f1c9e2	134
AnnaBridge	165:e614a9f1c9e2	135	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	165:e614a9f1c9e2	136	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	165:e614a9f1c9e2	137	* @{
AnnaBridge	165:e614a9f1c9e2	138	*/
AnnaBridge	165:e614a9f1c9e2	139	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	165:e614a9f1c9e2	140	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	165:e614a9f1c9e2	141	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
AnnaBridge	165:e614a9f1c9e2	142	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
AnnaBridge	165:e614a9f1c9e2	143	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
AnnaBridge	165:e614a9f1c9e2	144	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
AnnaBridge	165:e614a9f1c9e2	145	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	165:e614a9f1c9e2	146	/**
AnnaBridge	165:e614a9f1c9e2	147	* @}
AnnaBridge	165:e614a9f1c9e2	148	*/
AnnaBridge	165:e614a9f1c9e2	149
AnnaBridge	165:e614a9f1c9e2	150	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	165:e614a9f1c9e2	151	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	165:e614a9f1c9e2	152	* @{
AnnaBridge	165:e614a9f1c9e2	153	*/
AnnaBridge	165:e614a9f1c9e2	154	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	165:e614a9f1c9e2	155	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	165:e614a9f1c9e2	156	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	165:e614a9f1c9e2	157	/**
AnnaBridge	165:e614a9f1c9e2	158	* @}
AnnaBridge	165:e614a9f1c9e2	159	*/
AnnaBridge	165:e614a9f1c9e2	160
AnnaBridge	165:e614a9f1c9e2	161	/** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge	165:e614a9f1c9e2	162	* @{
AnnaBridge	165:e614a9f1c9e2	163	*/
AnnaBridge	165:e614a9f1c9e2	164	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
AnnaBridge	165:e614a9f1c9e2	165	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
AnnaBridge	165:e614a9f1c9e2	166	/**
AnnaBridge	165:e614a9f1c9e2	167	* @}
AnnaBridge	165:e614a9f1c9e2	168	*/
AnnaBridge	165:e614a9f1c9e2	169
AnnaBridge	165:e614a9f1c9e2	170
AnnaBridge	165:e614a9f1c9e2	171	/** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge	165:e614a9f1c9e2	172	* @{
AnnaBridge	165:e614a9f1c9e2	173	*/
AnnaBridge	165:e614a9f1c9e2	174	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
AnnaBridge	165:e614a9f1c9e2	175	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
AnnaBridge	165:e614a9f1c9e2	176	/**
AnnaBridge	165:e614a9f1c9e2	177	* @}
AnnaBridge	165:e614a9f1c9e2	178	*/
AnnaBridge	165:e614a9f1c9e2	179
AnnaBridge	165:e614a9f1c9e2	180	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge	165:e614a9f1c9e2	181	* @{
AnnaBridge	165:e614a9f1c9e2	182	*/
AnnaBridge	165:e614a9f1c9e2	183	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
AnnaBridge	165:e614a9f1c9e2	184	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
AnnaBridge	165:e614a9f1c9e2	185	/**
AnnaBridge	165:e614a9f1c9e2	186	* @}
AnnaBridge	165:e614a9f1c9e2	187	*/
AnnaBridge	165:e614a9f1c9e2	188
AnnaBridge	165:e614a9f1c9e2	189	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	165:e614a9f1c9e2	190	* @{
AnnaBridge	165:e614a9f1c9e2	191	*/
AnnaBridge	165:e614a9f1c9e2	192	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
AnnaBridge	165:e614a9f1c9e2	193	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
AnnaBridge	165:e614a9f1c9e2	194	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
AnnaBridge	165:e614a9f1c9e2	195	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
AnnaBridge	165:e614a9f1c9e2	196	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
AnnaBridge	165:e614a9f1c9e2	197	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
AnnaBridge	165:e614a9f1c9e2	198	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
AnnaBridge	165:e614a9f1c9e2	199	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
AnnaBridge	165:e614a9f1c9e2	200	/**
AnnaBridge	165:e614a9f1c9e2	201	* @}
AnnaBridge	165:e614a9f1c9e2	202	*/
AnnaBridge	165:e614a9f1c9e2	203
AnnaBridge	165:e614a9f1c9e2	204	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	165:e614a9f1c9e2	205	* @{
AnnaBridge	165:e614a9f1c9e2	206	*/
AnnaBridge	165:e614a9f1c9e2	207	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
AnnaBridge	165:e614a9f1c9e2	208	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
AnnaBridge	165:e614a9f1c9e2	209	/**
AnnaBridge	165:e614a9f1c9e2	210	* @}
AnnaBridge	165:e614a9f1c9e2	211	*/
AnnaBridge	165:e614a9f1c9e2	212
AnnaBridge	165:e614a9f1c9e2	213	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	165:e614a9f1c9e2	214	* @{
AnnaBridge	165:e614a9f1c9e2	215	*/
AnnaBridge	165:e614a9f1c9e2	216	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
AnnaBridge	165:e614a9f1c9e2	217	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
AnnaBridge	165:e614a9f1c9e2	218	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
AnnaBridge	165:e614a9f1c9e2	219	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
AnnaBridge	165:e614a9f1c9e2	220	/**
AnnaBridge	165:e614a9f1c9e2	221	* @}
AnnaBridge	165:e614a9f1c9e2	222	*/
AnnaBridge	165:e614a9f1c9e2	223
AnnaBridge	165:e614a9f1c9e2	224	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge	165:e614a9f1c9e2	225	* @{
AnnaBridge	165:e614a9f1c9e2	226	*/
AnnaBridge	165:e614a9f1c9e2	227	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
AnnaBridge	165:e614a9f1c9e2	228	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
AnnaBridge	165:e614a9f1c9e2	229	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
AnnaBridge	165:e614a9f1c9e2	230	/**
AnnaBridge	165:e614a9f1c9e2	231	* @}
AnnaBridge	165:e614a9f1c9e2	232	*/
AnnaBridge	165:e614a9f1c9e2	233
AnnaBridge	165:e614a9f1c9e2	234	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge	165:e614a9f1c9e2	235	* @{
AnnaBridge	165:e614a9f1c9e2	236	*/
AnnaBridge	165:e614a9f1c9e2	237	#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /!< Data length for SPI transfer: 8 bits /
AnnaBridge	165:e614a9f1c9e2	238	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /!< Data length for SPI transfer: 16 bits /
AnnaBridge	165:e614a9f1c9e2	239	/**
AnnaBridge	165:e614a9f1c9e2	240	* @}
AnnaBridge	165:e614a9f1c9e2	241	*/
AnnaBridge	165:e614a9f1c9e2	242	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	243
AnnaBridge	165:e614a9f1c9e2	244	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	165:e614a9f1c9e2	245	* @{
AnnaBridge	165:e614a9f1c9e2	246	*/
AnnaBridge	165:e614a9f1c9e2	247	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
AnnaBridge	165:e614a9f1c9e2	248	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	165:e614a9f1c9e2	249	/**
AnnaBridge	165:e614a9f1c9e2	250	* @}
AnnaBridge	165:e614a9f1c9e2	251	*/
AnnaBridge	165:e614a9f1c9e2	252	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	253
AnnaBridge	165:e614a9f1c9e2	254	/**
AnnaBridge	165:e614a9f1c9e2	255	* @}
AnnaBridge	165:e614a9f1c9e2	256	*/
AnnaBridge	165:e614a9f1c9e2	257
AnnaBridge	165:e614a9f1c9e2	258	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	259	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	165:e614a9f1c9e2	260	* @{
AnnaBridge	165:e614a9f1c9e2	261	*/
AnnaBridge	165:e614a9f1c9e2	262
AnnaBridge	165:e614a9f1c9e2	263	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	165:e614a9f1c9e2	264	* @{
AnnaBridge	165:e614a9f1c9e2	265	*/
AnnaBridge	165:e614a9f1c9e2	266
AnnaBridge	165:e614a9f1c9e2	267	/**
AnnaBridge	165:e614a9f1c9e2	268	* @brief Write a value in SPI register
AnnaBridge	165:e614a9f1c9e2	269	* @param __INSTANCE__ SPI Instance
AnnaBridge	165:e614a9f1c9e2	270	* @param __REG__ Register to be written
AnnaBridge	165:e614a9f1c9e2	271	* @param __VALUE__ Value to be written in the register
AnnaBridge	165:e614a9f1c9e2	272	* @retval None
AnnaBridge	165:e614a9f1c9e2	273	*/
AnnaBridge	165:e614a9f1c9e2	274	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	165:e614a9f1c9e2	275
AnnaBridge	165:e614a9f1c9e2	276	/**
AnnaBridge	165:e614a9f1c9e2	277	* @brief Read a value in SPI register
AnnaBridge	165:e614a9f1c9e2	278	* @param __INSTANCE__ SPI Instance
AnnaBridge	165:e614a9f1c9e2	279	* @param __REG__ Register to be read
AnnaBridge	165:e614a9f1c9e2	280	* @retval Register value
AnnaBridge	165:e614a9f1c9e2	281	*/
AnnaBridge	165:e614a9f1c9e2	282	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	165:e614a9f1c9e2	283	/**
AnnaBridge	165:e614a9f1c9e2	284	* @}
AnnaBridge	165:e614a9f1c9e2	285	*/
AnnaBridge	165:e614a9f1c9e2	286
AnnaBridge	165:e614a9f1c9e2	287	/**
AnnaBridge	165:e614a9f1c9e2	288	* @}
AnnaBridge	165:e614a9f1c9e2	289	*/
AnnaBridge	165:e614a9f1c9e2	290
AnnaBridge	165:e614a9f1c9e2	291	/* Exported functions --------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	292	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	165:e614a9f1c9e2	293	* @{
AnnaBridge	165:e614a9f1c9e2	294	*/
AnnaBridge	165:e614a9f1c9e2	295
AnnaBridge	165:e614a9f1c9e2	296	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	165:e614a9f1c9e2	297	* @{
AnnaBridge	165:e614a9f1c9e2	298	*/
AnnaBridge	165:e614a9f1c9e2	299
AnnaBridge	165:e614a9f1c9e2	300	/**
AnnaBridge	165:e614a9f1c9e2	301	* @brief Enable SPI peripheral
AnnaBridge	165:e614a9f1c9e2	302	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	165:e614a9f1c9e2	303	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	304	* @retval None
AnnaBridge	165:e614a9f1c9e2	305	*/
AnnaBridge	165:e614a9f1c9e2	306	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	307	{
AnnaBridge	165:e614a9f1c9e2	308	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	165:e614a9f1c9e2	309	}
AnnaBridge	165:e614a9f1c9e2	310
AnnaBridge	165:e614a9f1c9e2	311	/**
AnnaBridge	165:e614a9f1c9e2	312	* @brief Disable SPI peripheral
AnnaBridge	165:e614a9f1c9e2	313	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	165:e614a9f1c9e2	314	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	165:e614a9f1c9e2	315	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	316	* @retval None
AnnaBridge	165:e614a9f1c9e2	317	*/
AnnaBridge	165:e614a9f1c9e2	318	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	319	{
AnnaBridge	165:e614a9f1c9e2	320	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	165:e614a9f1c9e2	321	}
AnnaBridge	165:e614a9f1c9e2	322
AnnaBridge	165:e614a9f1c9e2	323	/**
AnnaBridge	165:e614a9f1c9e2	324	* @brief Check if SPI peripheral is enabled
AnnaBridge	165:e614a9f1c9e2	325	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	165:e614a9f1c9e2	326	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	327	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	328	*/
AnnaBridge	165:e614a9f1c9e2	329	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	330	{
AnnaBridge	165:e614a9f1c9e2	331	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge	165:e614a9f1c9e2	332	}
AnnaBridge	165:e614a9f1c9e2	333
AnnaBridge	165:e614a9f1c9e2	334	/**
AnnaBridge	165:e614a9f1c9e2	335	* @brief Set SPI operation mode to Master or Slave
AnnaBridge	165:e614a9f1c9e2	336	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	165:e614a9f1c9e2	337	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge	165:e614a9f1c9e2	338	* CR1 SSI LL_SPI_SetMode
AnnaBridge	165:e614a9f1c9e2	339	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	340	* @param Mode This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	341	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	165:e614a9f1c9e2	342	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	165:e614a9f1c9e2	343	* @retval None
AnnaBridge	165:e614a9f1c9e2	344	*/
AnnaBridge	165:e614a9f1c9e2	345	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	165:e614a9f1c9e2	346	{
AnnaBridge	165:e614a9f1c9e2	347	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
AnnaBridge	165:e614a9f1c9e2	348	}
AnnaBridge	165:e614a9f1c9e2	349
AnnaBridge	165:e614a9f1c9e2	350	/**
AnnaBridge	165:e614a9f1c9e2	351	* @brief Get SPI operation mode (Master or Slave)
AnnaBridge	165:e614a9f1c9e2	352	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge	165:e614a9f1c9e2	353	* CR1 SSI LL_SPI_GetMode
AnnaBridge	165:e614a9f1c9e2	354	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	355	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	356	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	165:e614a9f1c9e2	357	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	165:e614a9f1c9e2	358	*/
AnnaBridge	165:e614a9f1c9e2	359	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	360	{
AnnaBridge	165:e614a9f1c9e2	361	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
AnnaBridge	165:e614a9f1c9e2	362	}
AnnaBridge	165:e614a9f1c9e2	363
AnnaBridge	165:e614a9f1c9e2	364
AnnaBridge	165:e614a9f1c9e2	365	/**
AnnaBridge	165:e614a9f1c9e2	366	* @brief Set clock phase
AnnaBridge	165:e614a9f1c9e2	367	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	165:e614a9f1c9e2	368	* This bit is not used in SPI TI mode.
AnnaBridge	165:e614a9f1c9e2	369	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge	165:e614a9f1c9e2	370	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	371	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	372	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	165:e614a9f1c9e2	373	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	165:e614a9f1c9e2	374	* @retval None
AnnaBridge	165:e614a9f1c9e2	375	*/
AnnaBridge	165:e614a9f1c9e2	376	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	165:e614a9f1c9e2	377	{
AnnaBridge	165:e614a9f1c9e2	378	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge	165:e614a9f1c9e2	379	}
AnnaBridge	165:e614a9f1c9e2	380
AnnaBridge	165:e614a9f1c9e2	381	/**
AnnaBridge	165:e614a9f1c9e2	382	* @brief Get clock phase
AnnaBridge	165:e614a9f1c9e2	383	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge	165:e614a9f1c9e2	384	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	385	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	386	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	165:e614a9f1c9e2	387	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	165:e614a9f1c9e2	388	*/
AnnaBridge	165:e614a9f1c9e2	389	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	390	{
AnnaBridge	165:e614a9f1c9e2	391	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge	165:e614a9f1c9e2	392	}
AnnaBridge	165:e614a9f1c9e2	393
AnnaBridge	165:e614a9f1c9e2	394	/**
AnnaBridge	165:e614a9f1c9e2	395	* @brief Set clock polarity
AnnaBridge	165:e614a9f1c9e2	396	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	165:e614a9f1c9e2	397	* This bit is not used in SPI TI mode.
AnnaBridge	165:e614a9f1c9e2	398	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge	165:e614a9f1c9e2	399	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	400	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	401	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	165:e614a9f1c9e2	402	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	165:e614a9f1c9e2	403	* @retval None
AnnaBridge	165:e614a9f1c9e2	404	*/
AnnaBridge	165:e614a9f1c9e2	405	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	165:e614a9f1c9e2	406	{
AnnaBridge	165:e614a9f1c9e2	407	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge	165:e614a9f1c9e2	408	}
AnnaBridge	165:e614a9f1c9e2	409
AnnaBridge	165:e614a9f1c9e2	410	/**
AnnaBridge	165:e614a9f1c9e2	411	* @brief Get clock polarity
AnnaBridge	165:e614a9f1c9e2	412	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge	165:e614a9f1c9e2	413	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	414	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	415	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	165:e614a9f1c9e2	416	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	165:e614a9f1c9e2	417	*/
AnnaBridge	165:e614a9f1c9e2	418	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	419	{
AnnaBridge	165:e614a9f1c9e2	420	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge	165:e614a9f1c9e2	421	}
AnnaBridge	165:e614a9f1c9e2	422
AnnaBridge	165:e614a9f1c9e2	423	/**
AnnaBridge	165:e614a9f1c9e2	424	* @brief Set baud rate prescaler
AnnaBridge	165:e614a9f1c9e2	425	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge	165:e614a9f1c9e2	426	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge	165:e614a9f1c9e2	427	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	428	* @param BaudRate This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	429	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	165:e614a9f1c9e2	430	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	165:e614a9f1c9e2	431	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	165:e614a9f1c9e2	432	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	165:e614a9f1c9e2	433	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	165:e614a9f1c9e2	434	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	165:e614a9f1c9e2	435	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	165:e614a9f1c9e2	436	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	165:e614a9f1c9e2	437	* @retval None
AnnaBridge	165:e614a9f1c9e2	438	*/
AnnaBridge	165:e614a9f1c9e2	439	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge	165:e614a9f1c9e2	440	{
AnnaBridge	165:e614a9f1c9e2	441	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge	165:e614a9f1c9e2	442	}
AnnaBridge	165:e614a9f1c9e2	443
AnnaBridge	165:e614a9f1c9e2	444	/**
AnnaBridge	165:e614a9f1c9e2	445	* @brief Get baud rate prescaler
AnnaBridge	165:e614a9f1c9e2	446	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge	165:e614a9f1c9e2	447	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	448	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	449	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	165:e614a9f1c9e2	450	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	165:e614a9f1c9e2	451	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	165:e614a9f1c9e2	452	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	165:e614a9f1c9e2	453	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	165:e614a9f1c9e2	454	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	165:e614a9f1c9e2	455	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	165:e614a9f1c9e2	456	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	165:e614a9f1c9e2	457	*/
AnnaBridge	165:e614a9f1c9e2	458	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	459	{
AnnaBridge	165:e614a9f1c9e2	460	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge	165:e614a9f1c9e2	461	}
AnnaBridge	165:e614a9f1c9e2	462
AnnaBridge	165:e614a9f1c9e2	463	/**
AnnaBridge	165:e614a9f1c9e2	464	* @brief Set transfer bit order
AnnaBridge	165:e614a9f1c9e2	465	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	165:e614a9f1c9e2	466	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge	165:e614a9f1c9e2	467	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	468	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	469	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	165:e614a9f1c9e2	470	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	165:e614a9f1c9e2	471	* @retval None
AnnaBridge	165:e614a9f1c9e2	472	*/
AnnaBridge	165:e614a9f1c9e2	473	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	165:e614a9f1c9e2	474	{
AnnaBridge	165:e614a9f1c9e2	475	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge	165:e614a9f1c9e2	476	}
AnnaBridge	165:e614a9f1c9e2	477
AnnaBridge	165:e614a9f1c9e2	478	/**
AnnaBridge	165:e614a9f1c9e2	479	* @brief Get transfer bit order
AnnaBridge	165:e614a9f1c9e2	480	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge	165:e614a9f1c9e2	481	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	482	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	483	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	165:e614a9f1c9e2	484	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	165:e614a9f1c9e2	485	*/
AnnaBridge	165:e614a9f1c9e2	486	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	487	{
AnnaBridge	165:e614a9f1c9e2	488	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge	165:e614a9f1c9e2	489	}
AnnaBridge	165:e614a9f1c9e2	490
AnnaBridge	165:e614a9f1c9e2	491	/**
AnnaBridge	165:e614a9f1c9e2	492	* @brief Set transfer direction mode
AnnaBridge	165:e614a9f1c9e2	493	* @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge	165:e614a9f1c9e2	494	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge	165:e614a9f1c9e2	495	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge	165:e614a9f1c9e2	496	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge	165:e614a9f1c9e2	497	* CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge	165:e614a9f1c9e2	498	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	499	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	500	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	165:e614a9f1c9e2	501	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	165:e614a9f1c9e2	502	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	165:e614a9f1c9e2	503	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	165:e614a9f1c9e2	504	* @retval None
AnnaBridge	165:e614a9f1c9e2	505	*/
AnnaBridge	165:e614a9f1c9e2	506	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	165:e614a9f1c9e2	507	{
AnnaBridge	165:e614a9f1c9e2	508	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge	165:e614a9f1c9e2	509	}
AnnaBridge	165:e614a9f1c9e2	510
AnnaBridge	165:e614a9f1c9e2	511	/**
AnnaBridge	165:e614a9f1c9e2	512	* @brief Get transfer direction mode
AnnaBridge	165:e614a9f1c9e2	513	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge	165:e614a9f1c9e2	514	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge	165:e614a9f1c9e2	515	* CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge	165:e614a9f1c9e2	516	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	517	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	518	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	165:e614a9f1c9e2	519	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	165:e614a9f1c9e2	520	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	165:e614a9f1c9e2	521	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	165:e614a9f1c9e2	522	*/
AnnaBridge	165:e614a9f1c9e2	523	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	524	{
AnnaBridge	165:e614a9f1c9e2	525	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
AnnaBridge	165:e614a9f1c9e2	526	}
AnnaBridge	165:e614a9f1c9e2	527
AnnaBridge	165:e614a9f1c9e2	528	/**
AnnaBridge	165:e614a9f1c9e2	529	* @brief Set frame data width
AnnaBridge	165:e614a9f1c9e2	530	* @rmtoll CR1 DFF LL_SPI_SetDataWidth
AnnaBridge	165:e614a9f1c9e2	531	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	532	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	533	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	165:e614a9f1c9e2	534	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	165:e614a9f1c9e2	535	* @retval None
AnnaBridge	165:e614a9f1c9e2	536	*/
AnnaBridge	165:e614a9f1c9e2	537	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	165:e614a9f1c9e2	538	{
AnnaBridge	165:e614a9f1c9e2	539	MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
AnnaBridge	165:e614a9f1c9e2	540	}
AnnaBridge	165:e614a9f1c9e2	541
AnnaBridge	165:e614a9f1c9e2	542	/**
AnnaBridge	165:e614a9f1c9e2	543	* @brief Get frame data width
AnnaBridge	165:e614a9f1c9e2	544	* @rmtoll CR1 DFF LL_SPI_GetDataWidth
AnnaBridge	165:e614a9f1c9e2	545	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	546	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	547	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	165:e614a9f1c9e2	548	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	165:e614a9f1c9e2	549	*/
AnnaBridge	165:e614a9f1c9e2	550	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	551	{
AnnaBridge	165:e614a9f1c9e2	552	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
AnnaBridge	165:e614a9f1c9e2	553	}
AnnaBridge	165:e614a9f1c9e2	554
AnnaBridge	165:e614a9f1c9e2	555	/**
AnnaBridge	165:e614a9f1c9e2	556	* @}
AnnaBridge	165:e614a9f1c9e2	557	*/
AnnaBridge	165:e614a9f1c9e2	558
AnnaBridge	165:e614a9f1c9e2	559	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge	165:e614a9f1c9e2	560	* @{
AnnaBridge	165:e614a9f1c9e2	561	*/
AnnaBridge	165:e614a9f1c9e2	562
AnnaBridge	165:e614a9f1c9e2	563	/**
AnnaBridge	165:e614a9f1c9e2	564	* @brief Enable CRC
AnnaBridge	165:e614a9f1c9e2	565	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	165:e614a9f1c9e2	566	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge	165:e614a9f1c9e2	567	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	568	* @retval None
AnnaBridge	165:e614a9f1c9e2	569	*/
AnnaBridge	165:e614a9f1c9e2	570	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	571	{
AnnaBridge	165:e614a9f1c9e2	572	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	165:e614a9f1c9e2	573	}
AnnaBridge	165:e614a9f1c9e2	574
AnnaBridge	165:e614a9f1c9e2	575	/**
AnnaBridge	165:e614a9f1c9e2	576	* @brief Disable CRC
AnnaBridge	165:e614a9f1c9e2	577	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	165:e614a9f1c9e2	578	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge	165:e614a9f1c9e2	579	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	580	* @retval None
AnnaBridge	165:e614a9f1c9e2	581	*/
AnnaBridge	165:e614a9f1c9e2	582	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	583	{
AnnaBridge	165:e614a9f1c9e2	584	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	165:e614a9f1c9e2	585	}
AnnaBridge	165:e614a9f1c9e2	586
AnnaBridge	165:e614a9f1c9e2	587	/**
AnnaBridge	165:e614a9f1c9e2	588	* @brief Check if CRC is enabled
AnnaBridge	165:e614a9f1c9e2	589	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	165:e614a9f1c9e2	590	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	165:e614a9f1c9e2	591	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	592	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	593	*/
AnnaBridge	165:e614a9f1c9e2	594	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	595	{
AnnaBridge	165:e614a9f1c9e2	596	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge	165:e614a9f1c9e2	597	}
AnnaBridge	165:e614a9f1c9e2	598
AnnaBridge	165:e614a9f1c9e2	599	/**
AnnaBridge	165:e614a9f1c9e2	600	* @brief Set CRCNext to transfer CRC on the line
AnnaBridge	165:e614a9f1c9e2	601	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge	165:e614a9f1c9e2	602	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge	165:e614a9f1c9e2	603	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	604	* @retval None
AnnaBridge	165:e614a9f1c9e2	605	*/
AnnaBridge	165:e614a9f1c9e2	606	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	607	{
AnnaBridge	165:e614a9f1c9e2	608	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	165:e614a9f1c9e2	609	}
AnnaBridge	165:e614a9f1c9e2	610
AnnaBridge	165:e614a9f1c9e2	611	/**
AnnaBridge	165:e614a9f1c9e2	612	* @brief Set polynomial for CRC calculation
AnnaBridge	165:e614a9f1c9e2	613	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	165:e614a9f1c9e2	614	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	615	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	165:e614a9f1c9e2	616	* @retval None
AnnaBridge	165:e614a9f1c9e2	617	*/
AnnaBridge	165:e614a9f1c9e2	618	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	165:e614a9f1c9e2	619	{
AnnaBridge	165:e614a9f1c9e2	620	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge	165:e614a9f1c9e2	621	}
AnnaBridge	165:e614a9f1c9e2	622
AnnaBridge	165:e614a9f1c9e2	623	/**
AnnaBridge	165:e614a9f1c9e2	624	* @brief Get polynomial for CRC calculation
AnnaBridge	165:e614a9f1c9e2	625	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	165:e614a9f1c9e2	626	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	627	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	165:e614a9f1c9e2	628	*/
AnnaBridge	165:e614a9f1c9e2	629	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	630	{
AnnaBridge	165:e614a9f1c9e2	631	return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge	165:e614a9f1c9e2	632	}
AnnaBridge	165:e614a9f1c9e2	633
AnnaBridge	165:e614a9f1c9e2	634	/**
AnnaBridge	165:e614a9f1c9e2	635	* @brief Get Rx CRC
AnnaBridge	165:e614a9f1c9e2	636	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	165:e614a9f1c9e2	637	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	638	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	165:e614a9f1c9e2	639	*/
AnnaBridge	165:e614a9f1c9e2	640	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	641	{
AnnaBridge	165:e614a9f1c9e2	642	return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge	165:e614a9f1c9e2	643	}
AnnaBridge	165:e614a9f1c9e2	644
AnnaBridge	165:e614a9f1c9e2	645	/**
AnnaBridge	165:e614a9f1c9e2	646	* @brief Get Tx CRC
AnnaBridge	165:e614a9f1c9e2	647	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	165:e614a9f1c9e2	648	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	649	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	165:e614a9f1c9e2	650	*/
AnnaBridge	165:e614a9f1c9e2	651	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	652	{
AnnaBridge	165:e614a9f1c9e2	653	return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge	165:e614a9f1c9e2	654	}
AnnaBridge	165:e614a9f1c9e2	655
AnnaBridge	165:e614a9f1c9e2	656	/**
AnnaBridge	165:e614a9f1c9e2	657	* @}
AnnaBridge	165:e614a9f1c9e2	658	*/
AnnaBridge	165:e614a9f1c9e2	659
AnnaBridge	165:e614a9f1c9e2	660	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge	165:e614a9f1c9e2	661	* @{
AnnaBridge	165:e614a9f1c9e2	662	*/
AnnaBridge	165:e614a9f1c9e2	663
AnnaBridge	165:e614a9f1c9e2	664	/**
AnnaBridge	165:e614a9f1c9e2	665	* @brief Set NSS mode
AnnaBridge	165:e614a9f1c9e2	666	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge	165:e614a9f1c9e2	667	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge	165:e614a9f1c9e2	668	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge	165:e614a9f1c9e2	669	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	670	* @param NSS This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	671	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	165:e614a9f1c9e2	672	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	165:e614a9f1c9e2	673	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	165:e614a9f1c9e2	674	* @retval None
AnnaBridge	165:e614a9f1c9e2	675	*/
AnnaBridge	165:e614a9f1c9e2	676	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	165:e614a9f1c9e2	677	{
AnnaBridge	165:e614a9f1c9e2	678	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge	165:e614a9f1c9e2	679	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge	165:e614a9f1c9e2	680	}
AnnaBridge	165:e614a9f1c9e2	681
AnnaBridge	165:e614a9f1c9e2	682	/**
AnnaBridge	165:e614a9f1c9e2	683	* @brief Get NSS mode
AnnaBridge	165:e614a9f1c9e2	684	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge	165:e614a9f1c9e2	685	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge	165:e614a9f1c9e2	686	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	687	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	688	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	165:e614a9f1c9e2	689	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	165:e614a9f1c9e2	690	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	165:e614a9f1c9e2	691	*/
AnnaBridge	165:e614a9f1c9e2	692	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	693	{
AnnaBridge	165:e614a9f1c9e2	694	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge	165:e614a9f1c9e2	695	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge	165:e614a9f1c9e2	696	return (Ssm \| Ssoe);
AnnaBridge	165:e614a9f1c9e2	697	}
AnnaBridge	165:e614a9f1c9e2	698
AnnaBridge	165:e614a9f1c9e2	699	/**
AnnaBridge	165:e614a9f1c9e2	700	* @}
AnnaBridge	165:e614a9f1c9e2	701	*/
AnnaBridge	165:e614a9f1c9e2	702
AnnaBridge	165:e614a9f1c9e2	703	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge	165:e614a9f1c9e2	704	* @{
AnnaBridge	165:e614a9f1c9e2	705	*/
AnnaBridge	165:e614a9f1c9e2	706
AnnaBridge	165:e614a9f1c9e2	707	/**
AnnaBridge	165:e614a9f1c9e2	708	* @brief Check if Rx buffer is not empty
AnnaBridge	165:e614a9f1c9e2	709	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge	165:e614a9f1c9e2	710	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	711	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	712	*/
AnnaBridge	165:e614a9f1c9e2	713	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	714	{
AnnaBridge	165:e614a9f1c9e2	715	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge	165:e614a9f1c9e2	716	}
AnnaBridge	165:e614a9f1c9e2	717
AnnaBridge	165:e614a9f1c9e2	718	/**
AnnaBridge	165:e614a9f1c9e2	719	* @brief Check if Tx buffer is empty
AnnaBridge	165:e614a9f1c9e2	720	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge	165:e614a9f1c9e2	721	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	722	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	723	*/
AnnaBridge	165:e614a9f1c9e2	724	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	725	{
AnnaBridge	165:e614a9f1c9e2	726	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge	165:e614a9f1c9e2	727	}
AnnaBridge	165:e614a9f1c9e2	728
AnnaBridge	165:e614a9f1c9e2	729	/**
AnnaBridge	165:e614a9f1c9e2	730	* @brief Get CRC error flag
AnnaBridge	165:e614a9f1c9e2	731	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	165:e614a9f1c9e2	732	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	733	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	734	*/
AnnaBridge	165:e614a9f1c9e2	735	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	736	{
AnnaBridge	165:e614a9f1c9e2	737	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge	165:e614a9f1c9e2	738	}
AnnaBridge	165:e614a9f1c9e2	739
AnnaBridge	165:e614a9f1c9e2	740	/**
AnnaBridge	165:e614a9f1c9e2	741	* @brief Get mode fault error flag
AnnaBridge	165:e614a9f1c9e2	742	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	165:e614a9f1c9e2	743	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	744	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	745	*/
AnnaBridge	165:e614a9f1c9e2	746	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	747	{
AnnaBridge	165:e614a9f1c9e2	748	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge	165:e614a9f1c9e2	749	}
AnnaBridge	165:e614a9f1c9e2	750
AnnaBridge	165:e614a9f1c9e2	751	/**
AnnaBridge	165:e614a9f1c9e2	752	* @brief Get overrun error flag
AnnaBridge	165:e614a9f1c9e2	753	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	165:e614a9f1c9e2	754	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	755	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	756	*/
AnnaBridge	165:e614a9f1c9e2	757	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	758	{
AnnaBridge	165:e614a9f1c9e2	759	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge	165:e614a9f1c9e2	760	}
AnnaBridge	165:e614a9f1c9e2	761
AnnaBridge	165:e614a9f1c9e2	762	/**
AnnaBridge	165:e614a9f1c9e2	763	* @brief Get busy flag
AnnaBridge	165:e614a9f1c9e2	764	* @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge	165:e614a9f1c9e2	765	* -When the SPI is correctly disabled
AnnaBridge	165:e614a9f1c9e2	766	* -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge	165:e614a9f1c9e2	767	* -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge	165:e614a9f1c9e2	768	* sent
AnnaBridge	165:e614a9f1c9e2	769	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge	165:e614a9f1c9e2	770	* each data transfer.
AnnaBridge	165:e614a9f1c9e2	771	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge	165:e614a9f1c9e2	772	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	773	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	774	*/
AnnaBridge	165:e614a9f1c9e2	775	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	776	{
AnnaBridge	165:e614a9f1c9e2	777	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge	165:e614a9f1c9e2	778	}
AnnaBridge	165:e614a9f1c9e2	779
AnnaBridge	165:e614a9f1c9e2	780
AnnaBridge	165:e614a9f1c9e2	781	/**
AnnaBridge	165:e614a9f1c9e2	782	* @brief Clear CRC error flag
AnnaBridge	165:e614a9f1c9e2	783	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge	165:e614a9f1c9e2	784	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	785	* @retval None
AnnaBridge	165:e614a9f1c9e2	786	*/
AnnaBridge	165:e614a9f1c9e2	787	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	788	{
AnnaBridge	165:e614a9f1c9e2	789	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge	165:e614a9f1c9e2	790	}
AnnaBridge	165:e614a9f1c9e2	791
AnnaBridge	165:e614a9f1c9e2	792	/**
AnnaBridge	165:e614a9f1c9e2	793	* @brief Clear mode fault error flag
AnnaBridge	165:e614a9f1c9e2	794	* @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge	165:e614a9f1c9e2	795	* register followed by a write access to the SPIx_CR1 register
AnnaBridge	165:e614a9f1c9e2	796	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge	165:e614a9f1c9e2	797	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	798	* @retval None
AnnaBridge	165:e614a9f1c9e2	799	*/
AnnaBridge	165:e614a9f1c9e2	800	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	801	{
AnnaBridge	165:e614a9f1c9e2	802	__IO uint32_t tmpreg;
AnnaBridge	165:e614a9f1c9e2	803	tmpreg = SPIx->SR;
AnnaBridge	165:e614a9f1c9e2	804	(void) tmpreg;
AnnaBridge	165:e614a9f1c9e2	805	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	165:e614a9f1c9e2	806	(void) tmpreg;
AnnaBridge	165:e614a9f1c9e2	807	}
AnnaBridge	165:e614a9f1c9e2	808
AnnaBridge	165:e614a9f1c9e2	809	/**
AnnaBridge	165:e614a9f1c9e2	810	* @brief Clear overrun error flag
AnnaBridge	165:e614a9f1c9e2	811	* @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge	165:e614a9f1c9e2	812	* register followed by a read access to the SPIx_SR register
AnnaBridge	165:e614a9f1c9e2	813	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge	165:e614a9f1c9e2	814	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	815	* @retval None
AnnaBridge	165:e614a9f1c9e2	816	*/
AnnaBridge	165:e614a9f1c9e2	817	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	818	{
AnnaBridge	165:e614a9f1c9e2	819	__IO uint32_t tmpreg;
AnnaBridge	165:e614a9f1c9e2	820	tmpreg = SPIx->DR;
AnnaBridge	165:e614a9f1c9e2	821	(void) tmpreg;
AnnaBridge	165:e614a9f1c9e2	822	tmpreg = SPIx->SR;
AnnaBridge	165:e614a9f1c9e2	823	(void) tmpreg;
AnnaBridge	165:e614a9f1c9e2	824	}
AnnaBridge	165:e614a9f1c9e2	825
AnnaBridge	165:e614a9f1c9e2	826
AnnaBridge	165:e614a9f1c9e2	827	/**
AnnaBridge	165:e614a9f1c9e2	828	* @}
AnnaBridge	165:e614a9f1c9e2	829	*/
AnnaBridge	165:e614a9f1c9e2	830
AnnaBridge	165:e614a9f1c9e2	831	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge	165:e614a9f1c9e2	832	* @{
AnnaBridge	165:e614a9f1c9e2	833	*/
AnnaBridge	165:e614a9f1c9e2	834
AnnaBridge	165:e614a9f1c9e2	835	/**
AnnaBridge	165:e614a9f1c9e2	836	* @brief Enable error interrupt
AnnaBridge	165:e614a9f1c9e2	837	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	165:e614a9f1c9e2	838	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge	165:e614a9f1c9e2	839	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	840	* @retval None
AnnaBridge	165:e614a9f1c9e2	841	*/
AnnaBridge	165:e614a9f1c9e2	842	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	843	{
AnnaBridge	165:e614a9f1c9e2	844	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	165:e614a9f1c9e2	845	}
AnnaBridge	165:e614a9f1c9e2	846
AnnaBridge	165:e614a9f1c9e2	847	/**
AnnaBridge	165:e614a9f1c9e2	848	* @brief Enable Rx buffer not empty interrupt
AnnaBridge	165:e614a9f1c9e2	849	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge	165:e614a9f1c9e2	850	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	851	* @retval None
AnnaBridge	165:e614a9f1c9e2	852	*/
AnnaBridge	165:e614a9f1c9e2	853	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	854	{
AnnaBridge	165:e614a9f1c9e2	855	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	165:e614a9f1c9e2	856	}
AnnaBridge	165:e614a9f1c9e2	857
AnnaBridge	165:e614a9f1c9e2	858	/**
AnnaBridge	165:e614a9f1c9e2	859	* @brief Enable Tx buffer empty interrupt
AnnaBridge	165:e614a9f1c9e2	860	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge	165:e614a9f1c9e2	861	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	862	* @retval None
AnnaBridge	165:e614a9f1c9e2	863	*/
AnnaBridge	165:e614a9f1c9e2	864	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	865	{
AnnaBridge	165:e614a9f1c9e2	866	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	165:e614a9f1c9e2	867	}
AnnaBridge	165:e614a9f1c9e2	868
AnnaBridge	165:e614a9f1c9e2	869	/**
AnnaBridge	165:e614a9f1c9e2	870	* @brief Disable error interrupt
AnnaBridge	165:e614a9f1c9e2	871	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	165:e614a9f1c9e2	872	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge	165:e614a9f1c9e2	873	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	874	* @retval None
AnnaBridge	165:e614a9f1c9e2	875	*/
AnnaBridge	165:e614a9f1c9e2	876	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	877	{
AnnaBridge	165:e614a9f1c9e2	878	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	165:e614a9f1c9e2	879	}
AnnaBridge	165:e614a9f1c9e2	880
AnnaBridge	165:e614a9f1c9e2	881	/**
AnnaBridge	165:e614a9f1c9e2	882	* @brief Disable Rx buffer not empty interrupt
AnnaBridge	165:e614a9f1c9e2	883	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge	165:e614a9f1c9e2	884	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	885	* @retval None
AnnaBridge	165:e614a9f1c9e2	886	*/
AnnaBridge	165:e614a9f1c9e2	887	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	888	{
AnnaBridge	165:e614a9f1c9e2	889	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	165:e614a9f1c9e2	890	}
AnnaBridge	165:e614a9f1c9e2	891
AnnaBridge	165:e614a9f1c9e2	892	/**
AnnaBridge	165:e614a9f1c9e2	893	* @brief Disable Tx buffer empty interrupt
AnnaBridge	165:e614a9f1c9e2	894	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge	165:e614a9f1c9e2	895	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	896	* @retval None
AnnaBridge	165:e614a9f1c9e2	897	*/
AnnaBridge	165:e614a9f1c9e2	898	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	899	{
AnnaBridge	165:e614a9f1c9e2	900	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	165:e614a9f1c9e2	901	}
AnnaBridge	165:e614a9f1c9e2	902
AnnaBridge	165:e614a9f1c9e2	903	/**
AnnaBridge	165:e614a9f1c9e2	904	* @brief Check if error interrupt is enabled
AnnaBridge	165:e614a9f1c9e2	905	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge	165:e614a9f1c9e2	906	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	907	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	908	*/
AnnaBridge	165:e614a9f1c9e2	909	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	910	{
AnnaBridge	165:e614a9f1c9e2	911	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge	165:e614a9f1c9e2	912	}
AnnaBridge	165:e614a9f1c9e2	913
AnnaBridge	165:e614a9f1c9e2	914	/**
AnnaBridge	165:e614a9f1c9e2	915	* @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge	165:e614a9f1c9e2	916	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge	165:e614a9f1c9e2	917	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	918	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	919	*/
AnnaBridge	165:e614a9f1c9e2	920	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	921	{
AnnaBridge	165:e614a9f1c9e2	922	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge	165:e614a9f1c9e2	923	}
AnnaBridge	165:e614a9f1c9e2	924
AnnaBridge	165:e614a9f1c9e2	925	/**
AnnaBridge	165:e614a9f1c9e2	926	* @brief Check if Tx buffer empty interrupt
AnnaBridge	165:e614a9f1c9e2	927	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge	165:e614a9f1c9e2	928	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	929	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	930	*/
AnnaBridge	165:e614a9f1c9e2	931	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	932	{
AnnaBridge	165:e614a9f1c9e2	933	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge	165:e614a9f1c9e2	934	}
AnnaBridge	165:e614a9f1c9e2	935
AnnaBridge	165:e614a9f1c9e2	936	/**
AnnaBridge	165:e614a9f1c9e2	937	* @}
AnnaBridge	165:e614a9f1c9e2	938	*/
AnnaBridge	165:e614a9f1c9e2	939
AnnaBridge	165:e614a9f1c9e2	940	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	165:e614a9f1c9e2	941	* @{
AnnaBridge	165:e614a9f1c9e2	942	*/
AnnaBridge	165:e614a9f1c9e2	943
AnnaBridge	165:e614a9f1c9e2	944	/**
AnnaBridge	165:e614a9f1c9e2	945	* @brief Enable DMA Rx
AnnaBridge	165:e614a9f1c9e2	946	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	165:e614a9f1c9e2	947	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	948	* @retval None
AnnaBridge	165:e614a9f1c9e2	949	*/
AnnaBridge	165:e614a9f1c9e2	950	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	951	{
AnnaBridge	165:e614a9f1c9e2	952	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	165:e614a9f1c9e2	953	}
AnnaBridge	165:e614a9f1c9e2	954
AnnaBridge	165:e614a9f1c9e2	955	/**
AnnaBridge	165:e614a9f1c9e2	956	* @brief Disable DMA Rx
AnnaBridge	165:e614a9f1c9e2	957	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	165:e614a9f1c9e2	958	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	959	* @retval None
AnnaBridge	165:e614a9f1c9e2	960	*/
AnnaBridge	165:e614a9f1c9e2	961	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	962	{
AnnaBridge	165:e614a9f1c9e2	963	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	165:e614a9f1c9e2	964	}
AnnaBridge	165:e614a9f1c9e2	965
AnnaBridge	165:e614a9f1c9e2	966	/**
AnnaBridge	165:e614a9f1c9e2	967	* @brief Check if DMA Rx is enabled
AnnaBridge	165:e614a9f1c9e2	968	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	165:e614a9f1c9e2	969	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	970	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	971	*/
AnnaBridge	165:e614a9f1c9e2	972	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	973	{
AnnaBridge	165:e614a9f1c9e2	974	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge	165:e614a9f1c9e2	975	}
AnnaBridge	165:e614a9f1c9e2	976
AnnaBridge	165:e614a9f1c9e2	977	/**
AnnaBridge	165:e614a9f1c9e2	978	* @brief Enable DMA Tx
AnnaBridge	165:e614a9f1c9e2	979	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	165:e614a9f1c9e2	980	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	981	* @retval None
AnnaBridge	165:e614a9f1c9e2	982	*/
AnnaBridge	165:e614a9f1c9e2	983	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	984	{
AnnaBridge	165:e614a9f1c9e2	985	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	165:e614a9f1c9e2	986	}
AnnaBridge	165:e614a9f1c9e2	987
AnnaBridge	165:e614a9f1c9e2	988	/**
AnnaBridge	165:e614a9f1c9e2	989	* @brief Disable DMA Tx
AnnaBridge	165:e614a9f1c9e2	990	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	165:e614a9f1c9e2	991	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	992	* @retval None
AnnaBridge	165:e614a9f1c9e2	993	*/
AnnaBridge	165:e614a9f1c9e2	994	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	995	{
AnnaBridge	165:e614a9f1c9e2	996	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	165:e614a9f1c9e2	997	}
AnnaBridge	165:e614a9f1c9e2	998
AnnaBridge	165:e614a9f1c9e2	999	/**
AnnaBridge	165:e614a9f1c9e2	1000	* @brief Check if DMA Tx is enabled
AnnaBridge	165:e614a9f1c9e2	1001	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	165:e614a9f1c9e2	1002	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1003	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1004	*/
AnnaBridge	165:e614a9f1c9e2	1005	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1006	{
AnnaBridge	165:e614a9f1c9e2	1007	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge	165:e614a9f1c9e2	1008	}
AnnaBridge	165:e614a9f1c9e2	1009
AnnaBridge	165:e614a9f1c9e2	1010	/**
AnnaBridge	165:e614a9f1c9e2	1011	* @brief Get the data register address used for DMA transfer
AnnaBridge	165:e614a9f1c9e2	1012	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge	165:e614a9f1c9e2	1013	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1014	* @retval Address of data register
AnnaBridge	165:e614a9f1c9e2	1015	*/
AnnaBridge	165:e614a9f1c9e2	1016	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1017	{
AnnaBridge	165:e614a9f1c9e2	1018	return (uint32_t) & (SPIx->DR);
AnnaBridge	165:e614a9f1c9e2	1019	}
AnnaBridge	165:e614a9f1c9e2	1020
AnnaBridge	165:e614a9f1c9e2	1021	/**
AnnaBridge	165:e614a9f1c9e2	1022	* @}
AnnaBridge	165:e614a9f1c9e2	1023	*/
AnnaBridge	165:e614a9f1c9e2	1024
AnnaBridge	165:e614a9f1c9e2	1025	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge	165:e614a9f1c9e2	1026	* @{
AnnaBridge	165:e614a9f1c9e2	1027	*/
AnnaBridge	165:e614a9f1c9e2	1028
AnnaBridge	165:e614a9f1c9e2	1029	/**
AnnaBridge	165:e614a9f1c9e2	1030	* @brief Read 8-Bits in the data register
AnnaBridge	165:e614a9f1c9e2	1031	* @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge	165:e614a9f1c9e2	1032	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1033	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	165:e614a9f1c9e2	1034	*/
AnnaBridge	165:e614a9f1c9e2	1035	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1036	{
AnnaBridge	165:e614a9f1c9e2	1037	return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge	165:e614a9f1c9e2	1038	}
AnnaBridge	165:e614a9f1c9e2	1039
AnnaBridge	165:e614a9f1c9e2	1040	/**
AnnaBridge	165:e614a9f1c9e2	1041	* @brief Read 16-Bits in the data register
AnnaBridge	165:e614a9f1c9e2	1042	* @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge	165:e614a9f1c9e2	1043	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1044	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	165:e614a9f1c9e2	1045	*/
AnnaBridge	165:e614a9f1c9e2	1046	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1047	{
AnnaBridge	165:e614a9f1c9e2	1048	return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge	165:e614a9f1c9e2	1049	}
AnnaBridge	165:e614a9f1c9e2	1050
AnnaBridge	165:e614a9f1c9e2	1051	/**
AnnaBridge	165:e614a9f1c9e2	1052	* @brief Write 8-Bits in the data register
AnnaBridge	165:e614a9f1c9e2	1053	* @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge	165:e614a9f1c9e2	1054	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1055	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	165:e614a9f1c9e2	1056	* @retval None
AnnaBridge	165:e614a9f1c9e2	1057	*/
AnnaBridge	165:e614a9f1c9e2	1058	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	165:e614a9f1c9e2	1059	{
AnnaBridge	165:e614a9f1c9e2	1060	SPIx->DR = TxData;
AnnaBridge	165:e614a9f1c9e2	1061	}
AnnaBridge	165:e614a9f1c9e2	1062
AnnaBridge	165:e614a9f1c9e2	1063	/**
AnnaBridge	165:e614a9f1c9e2	1064	* @brief Write 16-Bits in the data register
AnnaBridge	165:e614a9f1c9e2	1065	* @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge	165:e614a9f1c9e2	1066	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1067	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	165:e614a9f1c9e2	1068	* @retval None
AnnaBridge	165:e614a9f1c9e2	1069	*/
AnnaBridge	165:e614a9f1c9e2	1070	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	165:e614a9f1c9e2	1071	{
AnnaBridge	165:e614a9f1c9e2	1072	SPIx->DR = TxData;
AnnaBridge	165:e614a9f1c9e2	1073	}
AnnaBridge	165:e614a9f1c9e2	1074
AnnaBridge	165:e614a9f1c9e2	1075	/**
AnnaBridge	165:e614a9f1c9e2	1076	* @}
AnnaBridge	165:e614a9f1c9e2	1077	*/
AnnaBridge	165:e614a9f1c9e2	1078	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	1079	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	165:e614a9f1c9e2	1080	* @{
AnnaBridge	165:e614a9f1c9e2	1081	*/
AnnaBridge	165:e614a9f1c9e2	1082
AnnaBridge	165:e614a9f1c9e2	1083	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	165:e614a9f1c9e2	1084	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	165:e614a9f1c9e2	1085	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	165:e614a9f1c9e2	1086
AnnaBridge	165:e614a9f1c9e2	1087	/**
AnnaBridge	165:e614a9f1c9e2	1088	* @}
AnnaBridge	165:e614a9f1c9e2	1089	*/
AnnaBridge	165:e614a9f1c9e2	1090	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	1091	/**
AnnaBridge	165:e614a9f1c9e2	1092	* @}
AnnaBridge	165:e614a9f1c9e2	1093	*/
AnnaBridge	165:e614a9f1c9e2	1094
AnnaBridge	165:e614a9f1c9e2	1095	/**
AnnaBridge	165:e614a9f1c9e2	1096	* @}
AnnaBridge	165:e614a9f1c9e2	1097	*/
AnnaBridge	165:e614a9f1c9e2	1098
AnnaBridge	165:e614a9f1c9e2	1099	#if defined(SPI_I2S_SUPPORT)
AnnaBridge	165:e614a9f1c9e2	1100	/** @defgroup I2S_LL I2S
AnnaBridge	165:e614a9f1c9e2	1101	* @{
AnnaBridge	165:e614a9f1c9e2	1102	*/
AnnaBridge	165:e614a9f1c9e2	1103
AnnaBridge	165:e614a9f1c9e2	1104	/* Private variables ---------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	1105	/* Private constants ---------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	1106	/* Private macros ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	1107
AnnaBridge	165:e614a9f1c9e2	1108	/* Exported types ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	1109	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	1110	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
AnnaBridge	165:e614a9f1c9e2	1111	* @{
AnnaBridge	165:e614a9f1c9e2	1112	*/
AnnaBridge	165:e614a9f1c9e2	1113
AnnaBridge	165:e614a9f1c9e2	1114	/**
AnnaBridge	165:e614a9f1c9e2	1115	* @brief I2S Init structure definition
AnnaBridge	165:e614a9f1c9e2	1116	*/
AnnaBridge	165:e614a9f1c9e2	1117
AnnaBridge	165:e614a9f1c9e2	1118	typedef struct
AnnaBridge	165:e614a9f1c9e2	1119	{
AnnaBridge	165:e614a9f1c9e2	1120	uint32_t Mode; /*!< Specifies the I2S operating mode.
AnnaBridge	165:e614a9f1c9e2	1121	This parameter can be a value of @ref I2S_LL_EC_MODE
AnnaBridge	165:e614a9f1c9e2	1122
AnnaBridge	165:e614a9f1c9e2	1123	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
AnnaBridge	165:e614a9f1c9e2	1124
AnnaBridge	165:e614a9f1c9e2	1125	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
AnnaBridge	165:e614a9f1c9e2	1126	This parameter can be a value of @ref I2S_LL_EC_STANDARD
AnnaBridge	165:e614a9f1c9e2	1127
AnnaBridge	165:e614a9f1c9e2	1128	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
AnnaBridge	165:e614a9f1c9e2	1129
AnnaBridge	165:e614a9f1c9e2	1130
AnnaBridge	165:e614a9f1c9e2	1131	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
AnnaBridge	165:e614a9f1c9e2	1132	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
AnnaBridge	165:e614a9f1c9e2	1133
AnnaBridge	165:e614a9f1c9e2	1134	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
AnnaBridge	165:e614a9f1c9e2	1135
AnnaBridge	165:e614a9f1c9e2	1136
AnnaBridge	165:e614a9f1c9e2	1137	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
AnnaBridge	165:e614a9f1c9e2	1138	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
AnnaBridge	165:e614a9f1c9e2	1139
AnnaBridge	165:e614a9f1c9e2	1140	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
AnnaBridge	165:e614a9f1c9e2	1141
AnnaBridge	165:e614a9f1c9e2	1142
AnnaBridge	165:e614a9f1c9e2	1143	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
AnnaBridge	165:e614a9f1c9e2	1144	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
AnnaBridge	165:e614a9f1c9e2	1145
AnnaBridge	165:e614a9f1c9e2	1146	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
AnnaBridge	165:e614a9f1c9e2	1147	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
AnnaBridge	165:e614a9f1c9e2	1148
AnnaBridge	165:e614a9f1c9e2	1149
AnnaBridge	165:e614a9f1c9e2	1150	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
AnnaBridge	165:e614a9f1c9e2	1151	This parameter can be a value of @ref I2S_LL_EC_POLARITY
AnnaBridge	165:e614a9f1c9e2	1152
AnnaBridge	165:e614a9f1c9e2	1153	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
AnnaBridge	165:e614a9f1c9e2	1154
AnnaBridge	165:e614a9f1c9e2	1155	} LL_I2S_InitTypeDef;
AnnaBridge	165:e614a9f1c9e2	1156
AnnaBridge	165:e614a9f1c9e2	1157	/**
AnnaBridge	165:e614a9f1c9e2	1158	* @}
AnnaBridge	165:e614a9f1c9e2	1159	*/
AnnaBridge	165:e614a9f1c9e2	1160	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	165:e614a9f1c9e2	1161
AnnaBridge	165:e614a9f1c9e2	1162	/* Exported constants --------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	1163	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
AnnaBridge	165:e614a9f1c9e2	1164	* @{
AnnaBridge	165:e614a9f1c9e2	1165	*/
AnnaBridge	165:e614a9f1c9e2	1166
AnnaBridge	165:e614a9f1c9e2	1167	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	165:e614a9f1c9e2	1168	* @brief Flags defines which can be used with LL_I2S_ReadReg function
AnnaBridge	165:e614a9f1c9e2	1169	* @{
AnnaBridge	165:e614a9f1c9e2	1170	*/
AnnaBridge	165:e614a9f1c9e2	1171	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	165:e614a9f1c9e2	1172	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	165:e614a9f1c9e2	1173	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
AnnaBridge	165:e614a9f1c9e2	1174	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
AnnaBridge	165:e614a9f1c9e2	1175	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
AnnaBridge	165:e614a9f1c9e2	1176	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	165:e614a9f1c9e2	1177	/**
AnnaBridge	165:e614a9f1c9e2	1178	* @}
AnnaBridge	165:e614a9f1c9e2	1179	*/
AnnaBridge	165:e614a9f1c9e2	1180
AnnaBridge	165:e614a9f1c9e2	1181	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	165:e614a9f1c9e2	1182	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	165:e614a9f1c9e2	1183	* @{
AnnaBridge	165:e614a9f1c9e2	1184	*/
AnnaBridge	165:e614a9f1c9e2	1185	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	165:e614a9f1c9e2	1186	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	165:e614a9f1c9e2	1187	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	165:e614a9f1c9e2	1188	/**
AnnaBridge	165:e614a9f1c9e2	1189	* @}
AnnaBridge	165:e614a9f1c9e2	1190	*/
AnnaBridge	165:e614a9f1c9e2	1191
AnnaBridge	165:e614a9f1c9e2	1192	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
AnnaBridge	165:e614a9f1c9e2	1193	* @{
AnnaBridge	165:e614a9f1c9e2	1194	*/
AnnaBridge	165:e614a9f1c9e2	1195	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
AnnaBridge	165:e614a9f1c9e2	1196	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	165:e614a9f1c9e2	1197	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
AnnaBridge	165:e614a9f1c9e2	1198	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	165:e614a9f1c9e2	1199	/**
AnnaBridge	165:e614a9f1c9e2	1200	* @}
AnnaBridge	165:e614a9f1c9e2	1201	*/
AnnaBridge	165:e614a9f1c9e2	1202
AnnaBridge	165:e614a9f1c9e2	1203	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
AnnaBridge	165:e614a9f1c9e2	1204	* @{
AnnaBridge	165:e614a9f1c9e2	1205	*/
AnnaBridge	165:e614a9f1c9e2	1206	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
AnnaBridge	165:e614a9f1c9e2	1207	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
AnnaBridge	165:e614a9f1c9e2	1208	/**
AnnaBridge	165:e614a9f1c9e2	1209	* @}
AnnaBridge	165:e614a9f1c9e2	1210	*/
AnnaBridge	165:e614a9f1c9e2	1211
AnnaBridge	165:e614a9f1c9e2	1212	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
AnnaBridge	165:e614a9f1c9e2	1213	* @{
AnnaBridge	165:e614a9f1c9e2	1214	*/
AnnaBridge	165:e614a9f1c9e2	1215	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
AnnaBridge	165:e614a9f1c9e2	1216	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
AnnaBridge	165:e614a9f1c9e2	1217	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
AnnaBridge	165:e614a9f1c9e2	1218	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
AnnaBridge	165:e614a9f1c9e2	1219	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
AnnaBridge	165:e614a9f1c9e2	1220	/**
AnnaBridge	165:e614a9f1c9e2	1221	* @}
AnnaBridge	165:e614a9f1c9e2	1222	*/
AnnaBridge	165:e614a9f1c9e2	1223
AnnaBridge	165:e614a9f1c9e2	1224	/** @defgroup I2S_LL_EC_MODE Operation Mode
AnnaBridge	165:e614a9f1c9e2	1225	* @{
AnnaBridge	165:e614a9f1c9e2	1226	*/
AnnaBridge	165:e614a9f1c9e2	1227	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
AnnaBridge	165:e614a9f1c9e2	1228	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
AnnaBridge	165:e614a9f1c9e2	1229	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
AnnaBridge	165:e614a9f1c9e2	1230	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
AnnaBridge	165:e614a9f1c9e2	1231	/**
AnnaBridge	165:e614a9f1c9e2	1232	* @}
AnnaBridge	165:e614a9f1c9e2	1233	*/
AnnaBridge	165:e614a9f1c9e2	1234
AnnaBridge	165:e614a9f1c9e2	1235	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
AnnaBridge	165:e614a9f1c9e2	1236	* @{
AnnaBridge	165:e614a9f1c9e2	1237	*/
AnnaBridge	165:e614a9f1c9e2	1238	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
AnnaBridge	165:e614a9f1c9e2	1239	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
AnnaBridge	165:e614a9f1c9e2	1240	/**
AnnaBridge	165:e614a9f1c9e2	1241	* @}
AnnaBridge	165:e614a9f1c9e2	1242	*/
AnnaBridge	165:e614a9f1c9e2	1243
AnnaBridge	165:e614a9f1c9e2	1244	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	1245
AnnaBridge	165:e614a9f1c9e2	1246	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
AnnaBridge	165:e614a9f1c9e2	1247	* @{
AnnaBridge	165:e614a9f1c9e2	1248	*/
AnnaBridge	165:e614a9f1c9e2	1249	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
AnnaBridge	165:e614a9f1c9e2	1250	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
AnnaBridge	165:e614a9f1c9e2	1251	/**
AnnaBridge	165:e614a9f1c9e2	1252	* @}
AnnaBridge	165:e614a9f1c9e2	1253	*/
AnnaBridge	165:e614a9f1c9e2	1254
AnnaBridge	165:e614a9f1c9e2	1255	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
AnnaBridge	165:e614a9f1c9e2	1256	* @{
AnnaBridge	165:e614a9f1c9e2	1257	*/
AnnaBridge	165:e614a9f1c9e2	1258
AnnaBridge	165:e614a9f1c9e2	1259	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
AnnaBridge	165:e614a9f1c9e2	1260	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
AnnaBridge	165:e614a9f1c9e2	1261	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
AnnaBridge	165:e614a9f1c9e2	1262	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
AnnaBridge	165:e614a9f1c9e2	1263	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
AnnaBridge	165:e614a9f1c9e2	1264	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
AnnaBridge	165:e614a9f1c9e2	1265	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
AnnaBridge	165:e614a9f1c9e2	1266	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
AnnaBridge	165:e614a9f1c9e2	1267	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
AnnaBridge	165:e614a9f1c9e2	1268	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
AnnaBridge	165:e614a9f1c9e2	1269	/**
AnnaBridge	165:e614a9f1c9e2	1270	* @}
AnnaBridge	165:e614a9f1c9e2	1271	*/
AnnaBridge	165:e614a9f1c9e2	1272	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	1273
AnnaBridge	165:e614a9f1c9e2	1274	/**
AnnaBridge	165:e614a9f1c9e2	1275	* @}
AnnaBridge	165:e614a9f1c9e2	1276	*/
AnnaBridge	165:e614a9f1c9e2	1277
AnnaBridge	165:e614a9f1c9e2	1278	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	1279	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
AnnaBridge	165:e614a9f1c9e2	1280	* @{
AnnaBridge	165:e614a9f1c9e2	1281	*/
AnnaBridge	165:e614a9f1c9e2	1282
AnnaBridge	165:e614a9f1c9e2	1283	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	165:e614a9f1c9e2	1284	* @{
AnnaBridge	165:e614a9f1c9e2	1285	*/
AnnaBridge	165:e614a9f1c9e2	1286
AnnaBridge	165:e614a9f1c9e2	1287	/**
AnnaBridge	165:e614a9f1c9e2	1288	* @brief Write a value in I2S register
AnnaBridge	165:e614a9f1c9e2	1289	* @param __INSTANCE__ I2S Instance
AnnaBridge	165:e614a9f1c9e2	1290	* @param __REG__ Register to be written
AnnaBridge	165:e614a9f1c9e2	1291	* @param __VALUE__ Value to be written in the register
AnnaBridge	165:e614a9f1c9e2	1292	* @retval None
AnnaBridge	165:e614a9f1c9e2	1293	*/
AnnaBridge	165:e614a9f1c9e2	1294	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	165:e614a9f1c9e2	1295
AnnaBridge	165:e614a9f1c9e2	1296	/**
AnnaBridge	165:e614a9f1c9e2	1297	* @brief Read a value in I2S register
AnnaBridge	165:e614a9f1c9e2	1298	* @param __INSTANCE__ I2S Instance
AnnaBridge	165:e614a9f1c9e2	1299	* @param __REG__ Register to be read
AnnaBridge	165:e614a9f1c9e2	1300	* @retval Register value
AnnaBridge	165:e614a9f1c9e2	1301	*/
AnnaBridge	165:e614a9f1c9e2	1302	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	165:e614a9f1c9e2	1303	/**
AnnaBridge	165:e614a9f1c9e2	1304	* @}
AnnaBridge	165:e614a9f1c9e2	1305	*/
AnnaBridge	165:e614a9f1c9e2	1306
AnnaBridge	165:e614a9f1c9e2	1307	/**
AnnaBridge	165:e614a9f1c9e2	1308	* @}
AnnaBridge	165:e614a9f1c9e2	1309	*/
AnnaBridge	165:e614a9f1c9e2	1310
AnnaBridge	165:e614a9f1c9e2	1311
AnnaBridge	165:e614a9f1c9e2	1312	/* Exported functions --------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	1313
AnnaBridge	165:e614a9f1c9e2	1314	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
AnnaBridge	165:e614a9f1c9e2	1315	* @{
AnnaBridge	165:e614a9f1c9e2	1316	*/
AnnaBridge	165:e614a9f1c9e2	1317
AnnaBridge	165:e614a9f1c9e2	1318	/** @defgroup I2S_LL_EF_Configuration Configuration
AnnaBridge	165:e614a9f1c9e2	1319	* @{
AnnaBridge	165:e614a9f1c9e2	1320	*/
AnnaBridge	165:e614a9f1c9e2	1321
AnnaBridge	165:e614a9f1c9e2	1322	/**
AnnaBridge	165:e614a9f1c9e2	1323	* @brief Select I2S mode and Enable I2S peripheral
AnnaBridge	165:e614a9f1c9e2	1324	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
AnnaBridge	165:e614a9f1c9e2	1325	* I2SCFGR I2SE LL_I2S_Enable
AnnaBridge	165:e614a9f1c9e2	1326	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1327	* @retval None
AnnaBridge	165:e614a9f1c9e2	1328	*/
AnnaBridge	165:e614a9f1c9e2	1329	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1330	{
AnnaBridge	165:e614a9f1c9e2	1331	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	165:e614a9f1c9e2	1332	}
AnnaBridge	165:e614a9f1c9e2	1333
AnnaBridge	165:e614a9f1c9e2	1334	/**
AnnaBridge	165:e614a9f1c9e2	1335	* @brief Disable I2S peripheral
AnnaBridge	165:e614a9f1c9e2	1336	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
AnnaBridge	165:e614a9f1c9e2	1337	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1338	* @retval None
AnnaBridge	165:e614a9f1c9e2	1339	*/
AnnaBridge	165:e614a9f1c9e2	1340	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1341	{
AnnaBridge	165:e614a9f1c9e2	1342	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	165:e614a9f1c9e2	1343	}
AnnaBridge	165:e614a9f1c9e2	1344
AnnaBridge	165:e614a9f1c9e2	1345	/**
AnnaBridge	165:e614a9f1c9e2	1346	* @brief Check if I2S peripheral is enabled
AnnaBridge	165:e614a9f1c9e2	1347	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
AnnaBridge	165:e614a9f1c9e2	1348	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1349	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1350	*/
AnnaBridge	165:e614a9f1c9e2	1351	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1352	{
AnnaBridge	165:e614a9f1c9e2	1353	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
AnnaBridge	165:e614a9f1c9e2	1354	}
AnnaBridge	165:e614a9f1c9e2	1355
AnnaBridge	165:e614a9f1c9e2	1356	/**
AnnaBridge	165:e614a9f1c9e2	1357	* @brief Set I2S data frame length
AnnaBridge	165:e614a9f1c9e2	1358	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
AnnaBridge	165:e614a9f1c9e2	1359	* I2SCFGR CHLEN LL_I2S_SetDataFormat
AnnaBridge	165:e614a9f1c9e2	1360	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1361	* @param DataFormat This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1362	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	165:e614a9f1c9e2	1363	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	165:e614a9f1c9e2	1364	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	165:e614a9f1c9e2	1365	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	165:e614a9f1c9e2	1366	* @retval None
AnnaBridge	165:e614a9f1c9e2	1367	*/
AnnaBridge	165:e614a9f1c9e2	1368	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
AnnaBridge	165:e614a9f1c9e2	1369	{
AnnaBridge	165:e614a9f1c9e2	1370	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
AnnaBridge	165:e614a9f1c9e2	1371	}
AnnaBridge	165:e614a9f1c9e2	1372
AnnaBridge	165:e614a9f1c9e2	1373	/**
AnnaBridge	165:e614a9f1c9e2	1374	* @brief Get I2S data frame length
AnnaBridge	165:e614a9f1c9e2	1375	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
AnnaBridge	165:e614a9f1c9e2	1376	* I2SCFGR CHLEN LL_I2S_GetDataFormat
AnnaBridge	165:e614a9f1c9e2	1377	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1378	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1379	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	165:e614a9f1c9e2	1380	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	165:e614a9f1c9e2	1381	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	165:e614a9f1c9e2	1382	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	165:e614a9f1c9e2	1383	*/
AnnaBridge	165:e614a9f1c9e2	1384	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1385	{
AnnaBridge	165:e614a9f1c9e2	1386	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
AnnaBridge	165:e614a9f1c9e2	1387	}
AnnaBridge	165:e614a9f1c9e2	1388
AnnaBridge	165:e614a9f1c9e2	1389	/**
AnnaBridge	165:e614a9f1c9e2	1390	* @brief Set I2S clock polarity
AnnaBridge	165:e614a9f1c9e2	1391	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
AnnaBridge	165:e614a9f1c9e2	1392	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1393	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1394	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	165:e614a9f1c9e2	1395	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	165:e614a9f1c9e2	1396	* @retval None
AnnaBridge	165:e614a9f1c9e2	1397	*/
AnnaBridge	165:e614a9f1c9e2	1398	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	165:e614a9f1c9e2	1399	{
AnnaBridge	165:e614a9f1c9e2	1400	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
AnnaBridge	165:e614a9f1c9e2	1401	}
AnnaBridge	165:e614a9f1c9e2	1402
AnnaBridge	165:e614a9f1c9e2	1403	/**
AnnaBridge	165:e614a9f1c9e2	1404	* @brief Get I2S clock polarity
AnnaBridge	165:e614a9f1c9e2	1405	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
AnnaBridge	165:e614a9f1c9e2	1406	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1407	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1408	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	165:e614a9f1c9e2	1409	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	165:e614a9f1c9e2	1410	*/
AnnaBridge	165:e614a9f1c9e2	1411	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1412	{
AnnaBridge	165:e614a9f1c9e2	1413	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
AnnaBridge	165:e614a9f1c9e2	1414	}
AnnaBridge	165:e614a9f1c9e2	1415
AnnaBridge	165:e614a9f1c9e2	1416	/**
AnnaBridge	165:e614a9f1c9e2	1417	* @brief Set I2S standard protocol
AnnaBridge	165:e614a9f1c9e2	1418	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
AnnaBridge	165:e614a9f1c9e2	1419	* I2SCFGR PCMSYNC LL_I2S_SetStandard
AnnaBridge	165:e614a9f1c9e2	1420	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1421	* @param Standard This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1422	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	165:e614a9f1c9e2	1423	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	165:e614a9f1c9e2	1424	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	165:e614a9f1c9e2	1425	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	165:e614a9f1c9e2	1426	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	165:e614a9f1c9e2	1427	* @retval None
AnnaBridge	165:e614a9f1c9e2	1428	*/
AnnaBridge	165:e614a9f1c9e2	1429	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	165:e614a9f1c9e2	1430	{
AnnaBridge	165:e614a9f1c9e2	1431	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
AnnaBridge	165:e614a9f1c9e2	1432	}
AnnaBridge	165:e614a9f1c9e2	1433
AnnaBridge	165:e614a9f1c9e2	1434	/**
AnnaBridge	165:e614a9f1c9e2	1435	* @brief Get I2S standard protocol
AnnaBridge	165:e614a9f1c9e2	1436	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
AnnaBridge	165:e614a9f1c9e2	1437	* I2SCFGR PCMSYNC LL_I2S_GetStandard
AnnaBridge	165:e614a9f1c9e2	1438	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1439	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1440	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	165:e614a9f1c9e2	1441	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	165:e614a9f1c9e2	1442	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	165:e614a9f1c9e2	1443	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	165:e614a9f1c9e2	1444	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	165:e614a9f1c9e2	1445	*/
AnnaBridge	165:e614a9f1c9e2	1446	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1447	{
AnnaBridge	165:e614a9f1c9e2	1448	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
AnnaBridge	165:e614a9f1c9e2	1449	}
AnnaBridge	165:e614a9f1c9e2	1450
AnnaBridge	165:e614a9f1c9e2	1451	/**
AnnaBridge	165:e614a9f1c9e2	1452	* @brief Set I2S transfer mode
AnnaBridge	165:e614a9f1c9e2	1453	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
AnnaBridge	165:e614a9f1c9e2	1454	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1455	* @param Mode This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1456	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	165:e614a9f1c9e2	1457	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	165:e614a9f1c9e2	1458	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	165:e614a9f1c9e2	1459	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	165:e614a9f1c9e2	1460	* @retval None
AnnaBridge	165:e614a9f1c9e2	1461	*/
AnnaBridge	165:e614a9f1c9e2	1462	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	165:e614a9f1c9e2	1463	{
AnnaBridge	165:e614a9f1c9e2	1464	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
AnnaBridge	165:e614a9f1c9e2	1465	}
AnnaBridge	165:e614a9f1c9e2	1466
AnnaBridge	165:e614a9f1c9e2	1467	/**
AnnaBridge	165:e614a9f1c9e2	1468	* @brief Get I2S transfer mode
AnnaBridge	165:e614a9f1c9e2	1469	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
AnnaBridge	165:e614a9f1c9e2	1470	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1471	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1472	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	165:e614a9f1c9e2	1473	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	165:e614a9f1c9e2	1474	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	165:e614a9f1c9e2	1475	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	165:e614a9f1c9e2	1476	*/
AnnaBridge	165:e614a9f1c9e2	1477	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1478	{
AnnaBridge	165:e614a9f1c9e2	1479	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
AnnaBridge	165:e614a9f1c9e2	1480	}
AnnaBridge	165:e614a9f1c9e2	1481
AnnaBridge	165:e614a9f1c9e2	1482	/**
AnnaBridge	165:e614a9f1c9e2	1483	* @brief Set I2S linear prescaler
AnnaBridge	165:e614a9f1c9e2	1484	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
AnnaBridge	165:e614a9f1c9e2	1485	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1486	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	165:e614a9f1c9e2	1487	* @retval None
AnnaBridge	165:e614a9f1c9e2	1488	*/
AnnaBridge	165:e614a9f1c9e2	1489	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
AnnaBridge	165:e614a9f1c9e2	1490	{
AnnaBridge	165:e614a9f1c9e2	1491	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
AnnaBridge	165:e614a9f1c9e2	1492	}
AnnaBridge	165:e614a9f1c9e2	1493
AnnaBridge	165:e614a9f1c9e2	1494	/**
AnnaBridge	165:e614a9f1c9e2	1495	* @brief Get I2S linear prescaler
AnnaBridge	165:e614a9f1c9e2	1496	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
AnnaBridge	165:e614a9f1c9e2	1497	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1498	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	165:e614a9f1c9e2	1499	*/
AnnaBridge	165:e614a9f1c9e2	1500	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1501	{
AnnaBridge	165:e614a9f1c9e2	1502	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
AnnaBridge	165:e614a9f1c9e2	1503	}
AnnaBridge	165:e614a9f1c9e2	1504
AnnaBridge	165:e614a9f1c9e2	1505	/**
AnnaBridge	165:e614a9f1c9e2	1506	* @brief Set I2S parity prescaler
AnnaBridge	165:e614a9f1c9e2	1507	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
AnnaBridge	165:e614a9f1c9e2	1508	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1509	* @param PrescalerParity This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1510	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	165:e614a9f1c9e2	1511	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	165:e614a9f1c9e2	1512	* @retval None
AnnaBridge	165:e614a9f1c9e2	1513	*/
AnnaBridge	165:e614a9f1c9e2	1514	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
AnnaBridge	165:e614a9f1c9e2	1515	{
AnnaBridge	165:e614a9f1c9e2	1516	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
AnnaBridge	165:e614a9f1c9e2	1517	}
AnnaBridge	165:e614a9f1c9e2	1518
AnnaBridge	165:e614a9f1c9e2	1519	/**
AnnaBridge	165:e614a9f1c9e2	1520	* @brief Get I2S parity prescaler
AnnaBridge	165:e614a9f1c9e2	1521	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
AnnaBridge	165:e614a9f1c9e2	1522	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1523	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1524	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	165:e614a9f1c9e2	1525	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	165:e614a9f1c9e2	1526	*/
AnnaBridge	165:e614a9f1c9e2	1527	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1528	{
AnnaBridge	165:e614a9f1c9e2	1529	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
AnnaBridge	165:e614a9f1c9e2	1530	}
AnnaBridge	165:e614a9f1c9e2	1531
AnnaBridge	165:e614a9f1c9e2	1532	/**
AnnaBridge	165:e614a9f1c9e2	1533	* @brief Enable the master clock ouput (Pin MCK)
AnnaBridge	165:e614a9f1c9e2	1534	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
AnnaBridge	165:e614a9f1c9e2	1535	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1536	* @retval None
AnnaBridge	165:e614a9f1c9e2	1537	*/
AnnaBridge	165:e614a9f1c9e2	1538	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1539	{
AnnaBridge	165:e614a9f1c9e2	1540	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	165:e614a9f1c9e2	1541	}
AnnaBridge	165:e614a9f1c9e2	1542
AnnaBridge	165:e614a9f1c9e2	1543	/**
AnnaBridge	165:e614a9f1c9e2	1544	* @brief Disable the master clock ouput (Pin MCK)
AnnaBridge	165:e614a9f1c9e2	1545	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
AnnaBridge	165:e614a9f1c9e2	1546	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1547	* @retval None
AnnaBridge	165:e614a9f1c9e2	1548	*/
AnnaBridge	165:e614a9f1c9e2	1549	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1550	{
AnnaBridge	165:e614a9f1c9e2	1551	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	165:e614a9f1c9e2	1552	}
AnnaBridge	165:e614a9f1c9e2	1553
AnnaBridge	165:e614a9f1c9e2	1554	/**
AnnaBridge	165:e614a9f1c9e2	1555	* @brief Check if the master clock ouput (Pin MCK) is enabled
AnnaBridge	165:e614a9f1c9e2	1556	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
AnnaBridge	165:e614a9f1c9e2	1557	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1558	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1559	*/
AnnaBridge	165:e614a9f1c9e2	1560	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1561	{
AnnaBridge	165:e614a9f1c9e2	1562	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
AnnaBridge	165:e614a9f1c9e2	1563	}
AnnaBridge	165:e614a9f1c9e2	1564
AnnaBridge	165:e614a9f1c9e2	1565	/**
AnnaBridge	165:e614a9f1c9e2	1566	* @}
AnnaBridge	165:e614a9f1c9e2	1567	*/
AnnaBridge	165:e614a9f1c9e2	1568
AnnaBridge	165:e614a9f1c9e2	1569	/** @defgroup I2S_LL_EF_FLAG FLAG Management
AnnaBridge	165:e614a9f1c9e2	1570	* @{
AnnaBridge	165:e614a9f1c9e2	1571	*/
AnnaBridge	165:e614a9f1c9e2	1572
AnnaBridge	165:e614a9f1c9e2	1573	/**
AnnaBridge	165:e614a9f1c9e2	1574	* @brief Check if Rx buffer is not empty
AnnaBridge	165:e614a9f1c9e2	1575	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
AnnaBridge	165:e614a9f1c9e2	1576	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1577	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1578	*/
AnnaBridge	165:e614a9f1c9e2	1579	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1580	{
AnnaBridge	165:e614a9f1c9e2	1581	return LL_SPI_IsActiveFlag_RXNE(SPIx);
AnnaBridge	165:e614a9f1c9e2	1582	}
AnnaBridge	165:e614a9f1c9e2	1583
AnnaBridge	165:e614a9f1c9e2	1584	/**
AnnaBridge	165:e614a9f1c9e2	1585	* @brief Check if Tx buffer is empty
AnnaBridge	165:e614a9f1c9e2	1586	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
AnnaBridge	165:e614a9f1c9e2	1587	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1588	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1589	*/
AnnaBridge	165:e614a9f1c9e2	1590	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1591	{
AnnaBridge	165:e614a9f1c9e2	1592	return LL_SPI_IsActiveFlag_TXE(SPIx);
AnnaBridge	165:e614a9f1c9e2	1593	}
AnnaBridge	165:e614a9f1c9e2	1594
AnnaBridge	165:e614a9f1c9e2	1595	/**
AnnaBridge	165:e614a9f1c9e2	1596	* @brief Get busy flag
AnnaBridge	165:e614a9f1c9e2	1597	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
AnnaBridge	165:e614a9f1c9e2	1598	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1599	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1600	*/
AnnaBridge	165:e614a9f1c9e2	1601	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1602	{
AnnaBridge	165:e614a9f1c9e2	1603	return LL_SPI_IsActiveFlag_BSY(SPIx);
AnnaBridge	165:e614a9f1c9e2	1604	}
AnnaBridge	165:e614a9f1c9e2	1605
AnnaBridge	165:e614a9f1c9e2	1606	/**
AnnaBridge	165:e614a9f1c9e2	1607	* @brief Get overrun error flag
AnnaBridge	165:e614a9f1c9e2	1608	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
AnnaBridge	165:e614a9f1c9e2	1609	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1610	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1611	*/
AnnaBridge	165:e614a9f1c9e2	1612	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1613	{
AnnaBridge	165:e614a9f1c9e2	1614	return LL_SPI_IsActiveFlag_OVR(SPIx);
AnnaBridge	165:e614a9f1c9e2	1615	}
AnnaBridge	165:e614a9f1c9e2	1616
AnnaBridge	165:e614a9f1c9e2	1617	/**
AnnaBridge	165:e614a9f1c9e2	1618	* @brief Get underrun error flag
AnnaBridge	165:e614a9f1c9e2	1619	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
AnnaBridge	165:e614a9f1c9e2	1620	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1621	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1622	*/
AnnaBridge	165:e614a9f1c9e2	1623	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1624	{
AnnaBridge	165:e614a9f1c9e2	1625	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
AnnaBridge	165:e614a9f1c9e2	1626	}
AnnaBridge	165:e614a9f1c9e2	1627
AnnaBridge	165:e614a9f1c9e2	1628	/**
AnnaBridge	165:e614a9f1c9e2	1629	* @brief Get channel side flag.
AnnaBridge	165:e614a9f1c9e2	1630	* @note 0: Channel Left has to be transmitted or has been received\n
AnnaBridge	165:e614a9f1c9e2	1631	* 1: Channel Right has to be transmitted or has been received\n
AnnaBridge	165:e614a9f1c9e2	1632	* It has no significance in PCM mode.
AnnaBridge	165:e614a9f1c9e2	1633	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
AnnaBridge	165:e614a9f1c9e2	1634	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1635	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1636	*/
AnnaBridge	165:e614a9f1c9e2	1637	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1638	{
AnnaBridge	165:e614a9f1c9e2	1639	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
AnnaBridge	165:e614a9f1c9e2	1640	}
AnnaBridge	165:e614a9f1c9e2	1641
AnnaBridge	165:e614a9f1c9e2	1642	/**
AnnaBridge	165:e614a9f1c9e2	1643	* @brief Clear overrun error flag
AnnaBridge	165:e614a9f1c9e2	1644	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
AnnaBridge	165:e614a9f1c9e2	1645	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1646	* @retval None
AnnaBridge	165:e614a9f1c9e2	1647	*/
AnnaBridge	165:e614a9f1c9e2	1648	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1649	{
AnnaBridge	165:e614a9f1c9e2	1650	LL_SPI_ClearFlag_OVR(SPIx);
AnnaBridge	165:e614a9f1c9e2	1651	}
AnnaBridge	165:e614a9f1c9e2	1652
AnnaBridge	165:e614a9f1c9e2	1653	/**
AnnaBridge	165:e614a9f1c9e2	1654	* @brief Clear underrun error flag
AnnaBridge	165:e614a9f1c9e2	1655	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
AnnaBridge	165:e614a9f1c9e2	1656	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1657	* @retval None
AnnaBridge	165:e614a9f1c9e2	1658	*/
AnnaBridge	165:e614a9f1c9e2	1659	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1660	{
AnnaBridge	165:e614a9f1c9e2	1661	__IO uint32_t tmpreg;
AnnaBridge	165:e614a9f1c9e2	1662	tmpreg = SPIx->SR;
AnnaBridge	165:e614a9f1c9e2	1663	(void)tmpreg;
AnnaBridge	165:e614a9f1c9e2	1664	}
AnnaBridge	165:e614a9f1c9e2	1665
AnnaBridge	165:e614a9f1c9e2	1666	/**
AnnaBridge	165:e614a9f1c9e2	1667	* @}
AnnaBridge	165:e614a9f1c9e2	1668	*/
AnnaBridge	165:e614a9f1c9e2	1669
AnnaBridge	165:e614a9f1c9e2	1670	/** @defgroup I2S_LL_EF_IT Interrupt Management
AnnaBridge	165:e614a9f1c9e2	1671	* @{
AnnaBridge	165:e614a9f1c9e2	1672	*/
AnnaBridge	165:e614a9f1c9e2	1673
AnnaBridge	165:e614a9f1c9e2	1674	/**
AnnaBridge	165:e614a9f1c9e2	1675	* @brief Enable error IT
AnnaBridge	165:e614a9f1c9e2	1676	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	165:e614a9f1c9e2	1677	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
AnnaBridge	165:e614a9f1c9e2	1678	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1679	* @retval None
AnnaBridge	165:e614a9f1c9e2	1680	*/
AnnaBridge	165:e614a9f1c9e2	1681	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1682	{
AnnaBridge	165:e614a9f1c9e2	1683	LL_SPI_EnableIT_ERR(SPIx);
AnnaBridge	165:e614a9f1c9e2	1684	}
AnnaBridge	165:e614a9f1c9e2	1685
AnnaBridge	165:e614a9f1c9e2	1686	/**
AnnaBridge	165:e614a9f1c9e2	1687	* @brief Enable Rx buffer not empty IT
AnnaBridge	165:e614a9f1c9e2	1688	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
AnnaBridge	165:e614a9f1c9e2	1689	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1690	* @retval None
AnnaBridge	165:e614a9f1c9e2	1691	*/
AnnaBridge	165:e614a9f1c9e2	1692	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1693	{
AnnaBridge	165:e614a9f1c9e2	1694	LL_SPI_EnableIT_RXNE(SPIx);
AnnaBridge	165:e614a9f1c9e2	1695	}
AnnaBridge	165:e614a9f1c9e2	1696
AnnaBridge	165:e614a9f1c9e2	1697	/**
AnnaBridge	165:e614a9f1c9e2	1698	* @brief Enable Tx buffer empty IT
AnnaBridge	165:e614a9f1c9e2	1699	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
AnnaBridge	165:e614a9f1c9e2	1700	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1701	* @retval None
AnnaBridge	165:e614a9f1c9e2	1702	*/
AnnaBridge	165:e614a9f1c9e2	1703	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1704	{
AnnaBridge	165:e614a9f1c9e2	1705	LL_SPI_EnableIT_TXE(SPIx);
AnnaBridge	165:e614a9f1c9e2	1706	}
AnnaBridge	165:e614a9f1c9e2	1707
AnnaBridge	165:e614a9f1c9e2	1708	/**
AnnaBridge	165:e614a9f1c9e2	1709	* @brief Disable error IT
AnnaBridge	165:e614a9f1c9e2	1710	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	165:e614a9f1c9e2	1711	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
AnnaBridge	165:e614a9f1c9e2	1712	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1713	* @retval None
AnnaBridge	165:e614a9f1c9e2	1714	*/
AnnaBridge	165:e614a9f1c9e2	1715	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1716	{
AnnaBridge	165:e614a9f1c9e2	1717	LL_SPI_DisableIT_ERR(SPIx);
AnnaBridge	165:e614a9f1c9e2	1718	}
AnnaBridge	165:e614a9f1c9e2	1719
AnnaBridge	165:e614a9f1c9e2	1720	/**
AnnaBridge	165:e614a9f1c9e2	1721	* @brief Disable Rx buffer not empty IT
AnnaBridge	165:e614a9f1c9e2	1722	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
AnnaBridge	165:e614a9f1c9e2	1723	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1724	* @retval None
AnnaBridge	165:e614a9f1c9e2	1725	*/
AnnaBridge	165:e614a9f1c9e2	1726	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1727	{
AnnaBridge	165:e614a9f1c9e2	1728	LL_SPI_DisableIT_RXNE(SPIx);
AnnaBridge	165:e614a9f1c9e2	1729	}
AnnaBridge	165:e614a9f1c9e2	1730
AnnaBridge	165:e614a9f1c9e2	1731	/**
AnnaBridge	165:e614a9f1c9e2	1732	* @brief Disable Tx buffer empty IT
AnnaBridge	165:e614a9f1c9e2	1733	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
AnnaBridge	165:e614a9f1c9e2	1734	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1735	* @retval None
AnnaBridge	165:e614a9f1c9e2	1736	*/
AnnaBridge	165:e614a9f1c9e2	1737	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1738	{
AnnaBridge	165:e614a9f1c9e2	1739	LL_SPI_DisableIT_TXE(SPIx);
AnnaBridge	165:e614a9f1c9e2	1740	}
AnnaBridge	165:e614a9f1c9e2	1741
AnnaBridge	165:e614a9f1c9e2	1742	/**
AnnaBridge	165:e614a9f1c9e2	1743	* @brief Check if ERR IT is enabled
AnnaBridge	165:e614a9f1c9e2	1744	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
AnnaBridge	165:e614a9f1c9e2	1745	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1746	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1747	*/
AnnaBridge	165:e614a9f1c9e2	1748	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1749	{
AnnaBridge	165:e614a9f1c9e2	1750	return LL_SPI_IsEnabledIT_ERR(SPIx);
AnnaBridge	165:e614a9f1c9e2	1751	}
AnnaBridge	165:e614a9f1c9e2	1752
AnnaBridge	165:e614a9f1c9e2	1753	/**
AnnaBridge	165:e614a9f1c9e2	1754	* @brief Check if RXNE IT is enabled
AnnaBridge	165:e614a9f1c9e2	1755	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
AnnaBridge	165:e614a9f1c9e2	1756	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1757	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1758	*/
AnnaBridge	165:e614a9f1c9e2	1759	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1760	{
AnnaBridge	165:e614a9f1c9e2	1761	return LL_SPI_IsEnabledIT_RXNE(SPIx);
AnnaBridge	165:e614a9f1c9e2	1762	}
AnnaBridge	165:e614a9f1c9e2	1763
AnnaBridge	165:e614a9f1c9e2	1764	/**
AnnaBridge	165:e614a9f1c9e2	1765	* @brief Check if TXE IT is enabled
AnnaBridge	165:e614a9f1c9e2	1766	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
AnnaBridge	165:e614a9f1c9e2	1767	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1768	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1769	*/
AnnaBridge	165:e614a9f1c9e2	1770	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1771	{
AnnaBridge	165:e614a9f1c9e2	1772	return LL_SPI_IsEnabledIT_TXE(SPIx);
AnnaBridge	165:e614a9f1c9e2	1773	}
AnnaBridge	165:e614a9f1c9e2	1774
AnnaBridge	165:e614a9f1c9e2	1775	/**
AnnaBridge	165:e614a9f1c9e2	1776	* @}
AnnaBridge	165:e614a9f1c9e2	1777	*/
AnnaBridge	165:e614a9f1c9e2	1778
AnnaBridge	165:e614a9f1c9e2	1779	/** @defgroup I2S_LL_EF_DMA DMA Management
AnnaBridge	165:e614a9f1c9e2	1780	* @{
AnnaBridge	165:e614a9f1c9e2	1781	*/
AnnaBridge	165:e614a9f1c9e2	1782
AnnaBridge	165:e614a9f1c9e2	1783	/**
AnnaBridge	165:e614a9f1c9e2	1784	* @brief Enable DMA Rx
AnnaBridge	165:e614a9f1c9e2	1785	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
AnnaBridge	165:e614a9f1c9e2	1786	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1787	* @retval None
AnnaBridge	165:e614a9f1c9e2	1788	*/
AnnaBridge	165:e614a9f1c9e2	1789	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1790	{
AnnaBridge	165:e614a9f1c9e2	1791	LL_SPI_EnableDMAReq_RX(SPIx);
AnnaBridge	165:e614a9f1c9e2	1792	}
AnnaBridge	165:e614a9f1c9e2	1793
AnnaBridge	165:e614a9f1c9e2	1794	/**
AnnaBridge	165:e614a9f1c9e2	1795	* @brief Disable DMA Rx
AnnaBridge	165:e614a9f1c9e2	1796	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
AnnaBridge	165:e614a9f1c9e2	1797	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1798	* @retval None
AnnaBridge	165:e614a9f1c9e2	1799	*/
AnnaBridge	165:e614a9f1c9e2	1800	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1801	{
AnnaBridge	165:e614a9f1c9e2	1802	LL_SPI_DisableDMAReq_RX(SPIx);
AnnaBridge	165:e614a9f1c9e2	1803	}
AnnaBridge	165:e614a9f1c9e2	1804
AnnaBridge	165:e614a9f1c9e2	1805	/**
AnnaBridge	165:e614a9f1c9e2	1806	* @brief Check if DMA Rx is enabled
AnnaBridge	165:e614a9f1c9e2	1807	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
AnnaBridge	165:e614a9f1c9e2	1808	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1809	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1810	*/
AnnaBridge	165:e614a9f1c9e2	1811	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1812	{
AnnaBridge	165:e614a9f1c9e2	1813	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
AnnaBridge	165:e614a9f1c9e2	1814	}
AnnaBridge	165:e614a9f1c9e2	1815
AnnaBridge	165:e614a9f1c9e2	1816	/**
AnnaBridge	165:e614a9f1c9e2	1817	* @brief Enable DMA Tx
AnnaBridge	165:e614a9f1c9e2	1818	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
AnnaBridge	165:e614a9f1c9e2	1819	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1820	* @retval None
AnnaBridge	165:e614a9f1c9e2	1821	*/
AnnaBridge	165:e614a9f1c9e2	1822	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1823	{
AnnaBridge	165:e614a9f1c9e2	1824	LL_SPI_EnableDMAReq_TX(SPIx);
AnnaBridge	165:e614a9f1c9e2	1825	}
AnnaBridge	165:e614a9f1c9e2	1826
AnnaBridge	165:e614a9f1c9e2	1827	/**
AnnaBridge	165:e614a9f1c9e2	1828	* @brief Disable DMA Tx
AnnaBridge	165:e614a9f1c9e2	1829	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
AnnaBridge	165:e614a9f1c9e2	1830	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1831	* @retval None
AnnaBridge	165:e614a9f1c9e2	1832	*/
AnnaBridge	165:e614a9f1c9e2	1833	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1834	{
AnnaBridge	165:e614a9f1c9e2	1835	LL_SPI_DisableDMAReq_TX(SPIx);
AnnaBridge	165:e614a9f1c9e2	1836	}
AnnaBridge	165:e614a9f1c9e2	1837
AnnaBridge	165:e614a9f1c9e2	1838	/**
AnnaBridge	165:e614a9f1c9e2	1839	* @brief Check if DMA Tx is enabled
AnnaBridge	165:e614a9f1c9e2	1840	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
AnnaBridge	165:e614a9f1c9e2	1841	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1842	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1843	*/
AnnaBridge	165:e614a9f1c9e2	1844	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1845	{
AnnaBridge	165:e614a9f1c9e2	1846	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
AnnaBridge	165:e614a9f1c9e2	1847	}
AnnaBridge	165:e614a9f1c9e2	1848
AnnaBridge	165:e614a9f1c9e2	1849	/**
AnnaBridge	165:e614a9f1c9e2	1850	* @}
AnnaBridge	165:e614a9f1c9e2	1851	*/
AnnaBridge	165:e614a9f1c9e2	1852
AnnaBridge	165:e614a9f1c9e2	1853	/** @defgroup I2S_LL_EF_DATA DATA Management
AnnaBridge	165:e614a9f1c9e2	1854	* @{
AnnaBridge	165:e614a9f1c9e2	1855	*/
AnnaBridge	165:e614a9f1c9e2	1856
AnnaBridge	165:e614a9f1c9e2	1857	/**
AnnaBridge	165:e614a9f1c9e2	1858	* @brief Read 16-Bits in data register
AnnaBridge	165:e614a9f1c9e2	1859	* @rmtoll DR DR LL_I2S_ReceiveData16
AnnaBridge	165:e614a9f1c9e2	1860	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1861	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	165:e614a9f1c9e2	1862	*/
AnnaBridge	165:e614a9f1c9e2	1863	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	165:e614a9f1c9e2	1864	{
AnnaBridge	165:e614a9f1c9e2	1865	return LL_SPI_ReceiveData16(SPIx);
AnnaBridge	165:e614a9f1c9e2	1866	}
AnnaBridge	165:e614a9f1c9e2	1867
AnnaBridge	165:e614a9f1c9e2	1868	/**
AnnaBridge	165:e614a9f1c9e2	1869	* @brief Write 16-Bits in data register
AnnaBridge	165:e614a9f1c9e2	1870	* @rmtoll DR DR LL_I2S_TransmitData16
AnnaBridge	165:e614a9f1c9e2	1871	* @param SPIx SPI Instance
AnnaBridge	165:e614a9f1c9e2	1872	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	165:e614a9f1c9e2	1873	* @retval None
AnnaBridge	165:e614a9f1c9e2	1874	*/
AnnaBridge	165:e614a9f1c9e2	1875	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	165:e614a9f1c9e2	1876	{
AnnaBridge	165:e614a9f1c9e2	1877	LL_SPI_TransmitData16(SPIx, TxData);
AnnaBridge	165:e614a9f1c9e2	1878	}
AnnaBridge	165:e614a9f1c9e2	1879
AnnaBridge	165:e614a9f1c9e2	1880	/**
AnnaBridge	165:e614a9f1c9e2	1881	* @}
AnnaBridge	165:e614a9f1c9e2	1882	*/
AnnaBridge	165:e614a9f1c9e2	1883
AnnaBridge	165:e614a9f1c9e2	1884	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	1885	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	165:e614a9f1c9e2	1886	* @{
AnnaBridge	165:e614a9f1c9e2	1887	*/
AnnaBridge	165:e614a9f1c9e2	1888
AnnaBridge	165:e614a9f1c9e2	1889	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	165:e614a9f1c9e2	1890	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
AnnaBridge	165:e614a9f1c9e2	1891	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
AnnaBridge	165:e614a9f1c9e2	1892	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
AnnaBridge	165:e614a9f1c9e2	1893
AnnaBridge	165:e614a9f1c9e2	1894	/**
AnnaBridge	165:e614a9f1c9e2	1895	* @}
AnnaBridge	165:e614a9f1c9e2	1896	*/
AnnaBridge	165:e614a9f1c9e2	1897	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	1898
AnnaBridge	165:e614a9f1c9e2	1899	/**
AnnaBridge	165:e614a9f1c9e2	1900	* @}
AnnaBridge	165:e614a9f1c9e2	1901	*/
AnnaBridge	165:e614a9f1c9e2	1902
AnnaBridge	165:e614a9f1c9e2	1903	/**
AnnaBridge	165:e614a9f1c9e2	1904	* @}
AnnaBridge	165:e614a9f1c9e2	1905	*/
AnnaBridge	165:e614a9f1c9e2	1906	#endif /* SPI_I2S_SUPPORT */
AnnaBridge	165:e614a9f1c9e2	1907
AnnaBridge	165:e614a9f1c9e2	1908	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) */
AnnaBridge	165:e614a9f1c9e2	1909
AnnaBridge	165:e614a9f1c9e2	1910	/**
AnnaBridge	165:e614a9f1c9e2	1911	* @}
AnnaBridge	165:e614a9f1c9e2	1912	*/
AnnaBridge	165:e614a9f1c9e2	1913
AnnaBridge	165:e614a9f1c9e2	1914	#ifdef __cplusplus
AnnaBridge	165:e614a9f1c9e2	1915	}
AnnaBridge	165:e614a9f1c9e2	1916	#endif
AnnaBridge	165:e614a9f1c9e2	1917
AnnaBridge	165:e614a9f1c9e2	1918	#endif /* __STM32F1xx_LL_SPI_H */
AnnaBridge	165:e614a9f1c9e2	1919
AnnaBridge	165:e614a9f1c9e2	1920	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/