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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 187:0387e8f68319

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f1xx_hal_tim.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief TIM HAL module driver
<>	144:ef7eb2e8f9f7	6	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	7	* functionalities of the Timer (TIM) peripheral:
<>	144:ef7eb2e8f9f7	8	* + Time Base Initialization
<>	144:ef7eb2e8f9f7	9	* + Time Base Start
<>	144:ef7eb2e8f9f7	10	* + Time Base Start Interruption
<>	144:ef7eb2e8f9f7	11	* + Time Base Start DMA
<>	144:ef7eb2e8f9f7	12	* + Time Output Compare/PWM Initialization
<>	144:ef7eb2e8f9f7	13	* + Time Output Compare/PWM Channel Configuration
<>	144:ef7eb2e8f9f7	14	* + Time Output Compare/PWM Start
<>	144:ef7eb2e8f9f7	15	* + Time Output Compare/PWM Start Interruption
<>	144:ef7eb2e8f9f7	16	* + Time Output Compare/PWM Start DMA
<>	144:ef7eb2e8f9f7	17	* + Time Input Capture Initialization
<>	144:ef7eb2e8f9f7	18	* + Time Input Capture Channel Configuration
<>	144:ef7eb2e8f9f7	19	* + Time Input Capture Start
<>	144:ef7eb2e8f9f7	20	* + Time Input Capture Start Interruption
<>	144:ef7eb2e8f9f7	21	* + Time Input Capture Start DMA
<>	144:ef7eb2e8f9f7	22	* + Time One Pulse Initialization
<>	144:ef7eb2e8f9f7	23	* + Time One Pulse Channel Configuration
<>	144:ef7eb2e8f9f7	24	* + Time One Pulse Start
<>	144:ef7eb2e8f9f7	25	* + Time Encoder Interface Initialization
<>	144:ef7eb2e8f9f7	26	* + Time Encoder Interface Start
<>	144:ef7eb2e8f9f7	27	* + Time Encoder Interface Start Interruption
<>	144:ef7eb2e8f9f7	28	* + Time Encoder Interface Start DMA
<>	144:ef7eb2e8f9f7	29	* + Commutation Event configuration with Interruption and DMA
<>	144:ef7eb2e8f9f7	30	* + Time OCRef clear configuration
<>	144:ef7eb2e8f9f7	31	* + Time External Clock configuration
<>	144:ef7eb2e8f9f7	32	@verbatim
<>	144:ef7eb2e8f9f7	33	==============================================================================
<>	144:ef7eb2e8f9f7	34	##### TIMER Generic features #####
<>	144:ef7eb2e8f9f7	35	==============================================================================
<>	144:ef7eb2e8f9f7	36	[..] The Timer features include:
<>	144:ef7eb2e8f9f7	37	(#) 16-bit up, down, up/down auto-reload counter.
<>	144:ef7eb2e8f9f7	38	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
<>	144:ef7eb2e8f9f7	39	counter clock frequency either by any factor between 1 and 65536.
<>	144:ef7eb2e8f9f7	40	(#) Up to 4 independent channels for:
<>	144:ef7eb2e8f9f7	41	(++) Input Capture
<>	144:ef7eb2e8f9f7	42	(++) Output Compare
<>	144:ef7eb2e8f9f7	43	(++) PWM generation (Edge and Center-aligned Mode)
<>	144:ef7eb2e8f9f7	44	(++) One-pulse mode output
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	47	==============================================================================
<>	144:ef7eb2e8f9f7	48	[..]
<>	144:ef7eb2e8f9f7	49	(#) Initialize the TIM low level resources by implementing the following functions
<>	144:ef7eb2e8f9f7	50	depending from feature used :
<>	144:ef7eb2e8f9f7	51	(++) Time Base : HAL_TIM_Base_MspInit()
<>	144:ef7eb2e8f9f7	52	(++) Input Capture : HAL_TIM_IC_MspInit()
<>	144:ef7eb2e8f9f7	53	(++) Output Compare : HAL_TIM_OC_MspInit()
<>	144:ef7eb2e8f9f7	54	(++) PWM generation : HAL_TIM_PWM_MspInit()
<>	144:ef7eb2e8f9f7	55	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<>	144:ef7eb2e8f9f7	56	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<>	144:ef7eb2e8f9f7	57
<>	144:ef7eb2e8f9f7	58	(#) Initialize the TIM low level resources :
<>	144:ef7eb2e8f9f7	59	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	60	(##) TIM pins configuration
<>	144:ef7eb2e8f9f7	61	(+++) Enable the clock for the TIM GPIOs using the following function:
<>	144:ef7eb2e8f9f7	62	__HAL_RCC_GPIOx_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	63	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<>	144:ef7eb2e8f9f7	64
<>	144:ef7eb2e8f9f7	65	(#) The external Clock can be configured, if needed (the default clock is the
<>	144:ef7eb2e8f9f7	66	internal clock from the APBx), using the following function:
<>	144:ef7eb2e8f9f7	67	HAL_TIM_ConfigClockSource, the clock configuration should be done before
<>	144:ef7eb2e8f9f7	68	any start function.
<>	144:ef7eb2e8f9f7	69
<>	144:ef7eb2e8f9f7	70	(#) Configure the TIM in the desired functioning mode using one of the
<>	144:ef7eb2e8f9f7	71	Initialization function of this driver:
<>	144:ef7eb2e8f9f7	72	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<>	144:ef7eb2e8f9f7	73	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<>	144:ef7eb2e8f9f7	74	Output Compare signal.
<>	144:ef7eb2e8f9f7	75	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<>	144:ef7eb2e8f9f7	76	PWM signal.
<>	144:ef7eb2e8f9f7	77	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<>	144:ef7eb2e8f9f7	78	external signal.
<>	144:ef7eb2e8f9f7	79	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
<>	144:ef7eb2e8f9f7	80	in One Pulse Mode.
<>	144:ef7eb2e8f9f7	81	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<>	144:ef7eb2e8f9f7	82
<>	144:ef7eb2e8f9f7	83	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
<>	144:ef7eb2e8f9f7	84	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
<>	144:ef7eb2e8f9f7	85	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
<>	144:ef7eb2e8f9f7	86	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
<>	144:ef7eb2e8f9f7	87	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
<>	144:ef7eb2e8f9f7	88	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
<>	144:ef7eb2e8f9f7	89	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
<>	144:ef7eb2e8f9f7	90
<>	144:ef7eb2e8f9f7	91	(#) The DMA Burst is managed with the two following functions:
<>	144:ef7eb2e8f9f7	92	HAL_TIM_DMABurst_WriteStart()
<>	144:ef7eb2e8f9f7	93	HAL_TIM_DMABurst_ReadStart()
<>	144:ef7eb2e8f9f7	94
<>	144:ef7eb2e8f9f7	95	@endverbatim
<>	144:ef7eb2e8f9f7	96	******************************************************************************
<>	144:ef7eb2e8f9f7	97	* @attention
<>	144:ef7eb2e8f9f7	98	*
<>	144:ef7eb2e8f9f7	99	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	100	*
<>	144:ef7eb2e8f9f7	101	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	102	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	103	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	104	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	105	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	106	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	107	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	108	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	109	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	110	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	111	*
<>	144:ef7eb2e8f9f7	112	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	113	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	114	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	115	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	116	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	117	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	118	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	119	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	120	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	121	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	122	*
<>	144:ef7eb2e8f9f7	123	******************************************************************************
<>	144:ef7eb2e8f9f7	124	*/
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	127	#include "stm32f1xx_hal.h"
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	/** @addtogroup STM32F1xx_HAL_Driver
<>	144:ef7eb2e8f9f7	130	* @{
<>	144:ef7eb2e8f9f7	131	*/
<>	144:ef7eb2e8f9f7	132
<>	144:ef7eb2e8f9f7	133	/** @defgroup TIM TIM
<>	144:ef7eb2e8f9f7	134	* @brief TIM HAL module driver
<>	144:ef7eb2e8f9f7	135	* @{
<>	144:ef7eb2e8f9f7	136	*/
<>	144:ef7eb2e8f9f7	137
<>	144:ef7eb2e8f9f7	138	#ifdef HAL_TIM_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	141	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	142	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	143	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	144	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	145	/** @defgroup TIM_Private_Functions TIM Private Functions
<>	144:ef7eb2e8f9f7	146	* @{
<>	144:ef7eb2e8f9f7	147	*/
<>	144:ef7eb2e8f9f7	148	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	149	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	150	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	151	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	152	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	153	uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	154	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	155	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	156	uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	157	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	158	uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	159	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<>	144:ef7eb2e8f9f7	160	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
<>	144:ef7eb2e8f9f7	161	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
<>	144:ef7eb2e8f9f7	162	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	163	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	164	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	165	TIM_SlaveConfigTypeDef * sSlaveConfig);
<>	144:ef7eb2e8f9f7	166
<>	144:ef7eb2e8f9f7	167	/**
<>	144:ef7eb2e8f9f7	168	* @}
<>	144:ef7eb2e8f9f7	169	*/
<>	144:ef7eb2e8f9f7	170
<>	144:ef7eb2e8f9f7	171	/* Exported functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	172
<>	144:ef7eb2e8f9f7	173	/** @defgroup TIM_Exported_Functions TIM Exported Functions
<>	144:ef7eb2e8f9f7	174	* @{
<>	144:ef7eb2e8f9f7	175	*/
<>	144:ef7eb2e8f9f7	176
<>	144:ef7eb2e8f9f7	177	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
<>	144:ef7eb2e8f9f7	178	* @brief Time Base functions
<>	144:ef7eb2e8f9f7	179	*
<>	144:ef7eb2e8f9f7	180	@verbatim
<>	144:ef7eb2e8f9f7	181	==============================================================================
<>	144:ef7eb2e8f9f7	182	##### Time Base functions #####
<>	144:ef7eb2e8f9f7	183	==============================================================================
<>	144:ef7eb2e8f9f7	184	[..]
<>	144:ef7eb2e8f9f7	185	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	186	(+) Initialize and configure the TIM base.
<>	144:ef7eb2e8f9f7	187	(+) De-initialize the TIM base.
<>	144:ef7eb2e8f9f7	188	(+) Start the Time Base.
<>	144:ef7eb2e8f9f7	189	(+) Stop the Time Base.
<>	144:ef7eb2e8f9f7	190	(+) Start the Time Base and enable interrupt.
<>	144:ef7eb2e8f9f7	191	(+) Stop the Time Base and disable interrupt.
<>	144:ef7eb2e8f9f7	192	(+) Start the Time Base and enable DMA transfer.
<>	144:ef7eb2e8f9f7	193	(+) Stop the Time Base and disable DMA transfer.
<>	144:ef7eb2e8f9f7	194
<>	144:ef7eb2e8f9f7	195	@endverbatim
<>	144:ef7eb2e8f9f7	196	* @{
<>	144:ef7eb2e8f9f7	197	*/
<>	144:ef7eb2e8f9f7	198	/**
<>	144:ef7eb2e8f9f7	199	* @brief Initializes the TIM Time base Unit according to the specified
<>	144:ef7eb2e8f9f7	200	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	201	* @param htim : TIM Base handle
<>	144:ef7eb2e8f9f7	202	* @retval HAL status
<>	144:ef7eb2e8f9f7	203	*/
<>	144:ef7eb2e8f9f7	204	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	205	{
<>	144:ef7eb2e8f9f7	206	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	207	if(htim == NULL)
<>	144:ef7eb2e8f9f7	208	{
<>	144:ef7eb2e8f9f7	209	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	210	}
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212	/* Check the parameters */
<>	144:ef7eb2e8f9f7	213	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	214	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	215	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	165:e614a9f1c9e2	216	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	219	{
<>	144:ef7eb2e8f9f7	220	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	221	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	222
<>	144:ef7eb2e8f9f7	223	/* Init the low level hardware : GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	224	HAL_TIM_Base_MspInit(htim);
<>	144:ef7eb2e8f9f7	225	}
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	228	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	229
<>	144:ef7eb2e8f9f7	230	/* Set the Time Base configuration */
<>	144:ef7eb2e8f9f7	231	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	232
<>	144:ef7eb2e8f9f7	233	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	234	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236	return HAL_OK;
<>	144:ef7eb2e8f9f7	237	}
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	/**
<>	144:ef7eb2e8f9f7	240	* @brief DeInitializes the TIM Base peripheral
<>	144:ef7eb2e8f9f7	241	* @param htim : TIM Base handle
<>	144:ef7eb2e8f9f7	242	* @retval HAL status
<>	144:ef7eb2e8f9f7	243	*/
<>	144:ef7eb2e8f9f7	244	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	245	{
<>	144:ef7eb2e8f9f7	246	/* Check the parameters */
<>	144:ef7eb2e8f9f7	247	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	252	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	255	HAL_TIM_Base_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	256
<>	144:ef7eb2e8f9f7	257	/* Change TIM state */
<>	144:ef7eb2e8f9f7	258	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	259
<>	144:ef7eb2e8f9f7	260	/* Release Lock */
<>	144:ef7eb2e8f9f7	261	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	262
<>	144:ef7eb2e8f9f7	263	return HAL_OK;
<>	144:ef7eb2e8f9f7	264	}
<>	144:ef7eb2e8f9f7	265
<>	144:ef7eb2e8f9f7	266	/**
<>	144:ef7eb2e8f9f7	267	* @brief Initializes the TIM Base MSP.
<>	144:ef7eb2e8f9f7	268	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	269	* @retval None
<>	144:ef7eb2e8f9f7	270	*/
<>	144:ef7eb2e8f9f7	271	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	272	{
<>	144:ef7eb2e8f9f7	273	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	274	UNUSED(htim);
<>	144:ef7eb2e8f9f7	275	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	276	the HAL_TIM_Base_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	277	*/
<>	144:ef7eb2e8f9f7	278	}
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/**
<>	144:ef7eb2e8f9f7	281	* @brief DeInitializes TIM Base MSP.
<>	144:ef7eb2e8f9f7	282	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	283	* @retval None
<>	144:ef7eb2e8f9f7	284	*/
<>	144:ef7eb2e8f9f7	285	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	286	{
<>	144:ef7eb2e8f9f7	287	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	288	UNUSED(htim);
<>	144:ef7eb2e8f9f7	289	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	290	the HAL_TIM_Base_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	291	*/
<>	144:ef7eb2e8f9f7	292	}
<>	144:ef7eb2e8f9f7	293
<>	144:ef7eb2e8f9f7	294
<>	144:ef7eb2e8f9f7	295	/**
<>	144:ef7eb2e8f9f7	296	* @brief Starts the TIM Base generation.
<>	144:ef7eb2e8f9f7	297	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	298	* @retval HAL status
<>	144:ef7eb2e8f9f7	299	*/
<>	144:ef7eb2e8f9f7	300	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	301	{
<>	144:ef7eb2e8f9f7	302	/* Check the parameters */
<>	144:ef7eb2e8f9f7	303	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	304
<>	144:ef7eb2e8f9f7	305	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	306	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	309	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	310
<>	144:ef7eb2e8f9f7	311	/* Change the TIM state*/
<>	144:ef7eb2e8f9f7	312	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/* Return function status */
<>	144:ef7eb2e8f9f7	315	return HAL_OK;
<>	144:ef7eb2e8f9f7	316	}
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/**
<>	144:ef7eb2e8f9f7	319	* @brief Stops the TIM Base generation.
<>	144:ef7eb2e8f9f7	320	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	321	* @retval HAL status
<>	144:ef7eb2e8f9f7	322	*/
<>	144:ef7eb2e8f9f7	323	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	324	{
<>	144:ef7eb2e8f9f7	325	/* Check the parameters */
<>	144:ef7eb2e8f9f7	326	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	329	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	332	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334	/* Change the TIM state*/
<>	144:ef7eb2e8f9f7	335	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	336
<>	144:ef7eb2e8f9f7	337	/* Return function status */
<>	144:ef7eb2e8f9f7	338	return HAL_OK;
<>	144:ef7eb2e8f9f7	339	}
<>	144:ef7eb2e8f9f7	340
<>	144:ef7eb2e8f9f7	341	/**
<>	144:ef7eb2e8f9f7	342	* @brief Starts the TIM Base generation in interrupt mode.
<>	144:ef7eb2e8f9f7	343	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	344	* @retval HAL status
<>	144:ef7eb2e8f9f7	345	*/
<>	144:ef7eb2e8f9f7	346	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	347	{
<>	144:ef7eb2e8f9f7	348	/* Check the parameters */
<>	144:ef7eb2e8f9f7	349	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/* Enable the TIM Update interrupt */
<>	144:ef7eb2e8f9f7	352	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	353
<>	144:ef7eb2e8f9f7	354	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	355	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	/* Return function status */
<>	144:ef7eb2e8f9f7	358	return HAL_OK;
<>	144:ef7eb2e8f9f7	359	}
<>	144:ef7eb2e8f9f7	360
<>	144:ef7eb2e8f9f7	361	/**
<>	144:ef7eb2e8f9f7	362	* @brief Stops the TIM Base generation in interrupt mode.
<>	144:ef7eb2e8f9f7	363	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	364	* @retval HAL status
<>	144:ef7eb2e8f9f7	365	*/
<>	144:ef7eb2e8f9f7	366	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	367	{
<>	144:ef7eb2e8f9f7	368	/* Check the parameters */
<>	144:ef7eb2e8f9f7	369	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	370	/* Disable the TIM Update interrupt */
<>	144:ef7eb2e8f9f7	371	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	372
<>	144:ef7eb2e8f9f7	373	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	374	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/* Return function status */
<>	144:ef7eb2e8f9f7	377	return HAL_OK;
<>	144:ef7eb2e8f9f7	378	}
<>	144:ef7eb2e8f9f7	379
<>	144:ef7eb2e8f9f7	380	/**
<>	144:ef7eb2e8f9f7	381	* @brief Starts the TIM Base generation in DMA mode.
<>	144:ef7eb2e8f9f7	382	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	383	* @param pData : The source Buffer address.
<>	144:ef7eb2e8f9f7	384	* @param Length : The length of data to be transferred from memory to peripheral.
<>	144:ef7eb2e8f9f7	385	* @retval HAL status
<>	144:ef7eb2e8f9f7	386	*/
<>	144:ef7eb2e8f9f7	387	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	388	{
<>	144:ef7eb2e8f9f7	389	/* Check the parameters */
<>	144:ef7eb2e8f9f7	390	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	391
<>	144:ef7eb2e8f9f7	392	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	393	{
<>	144:ef7eb2e8f9f7	394	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	395	}
<>	144:ef7eb2e8f9f7	396	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	397	{
AnnaBridge	165:e614a9f1c9e2	398	if((pData == 0U) && (Length > 0U))
<>	144:ef7eb2e8f9f7	399	{
<>	144:ef7eb2e8f9f7	400	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	401	}
<>	144:ef7eb2e8f9f7	402	else
<>	144:ef7eb2e8f9f7	403	{
<>	144:ef7eb2e8f9f7	404	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	405	}
<>	144:ef7eb2e8f9f7	406	}
<>	144:ef7eb2e8f9f7	407	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	408	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	409
<>	144:ef7eb2e8f9f7	410	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	411	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	412
<>	144:ef7eb2e8f9f7	413	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	414	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/* Enable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	417	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<>	144:ef7eb2e8f9f7	418
<>	144:ef7eb2e8f9f7	419	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	420	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	/* Return function status */
<>	144:ef7eb2e8f9f7	423	return HAL_OK;
<>	144:ef7eb2e8f9f7	424	}
<>	144:ef7eb2e8f9f7	425
<>	144:ef7eb2e8f9f7	426	/**
<>	144:ef7eb2e8f9f7	427	* @brief Stops the TIM Base generation in DMA mode.
<>	144:ef7eb2e8f9f7	428	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	429	* @retval HAL status
<>	144:ef7eb2e8f9f7	430	*/
<>	144:ef7eb2e8f9f7	431	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	432	{
<>	144:ef7eb2e8f9f7	433	/* Check the parameters */
<>	144:ef7eb2e8f9f7	434	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	435
<>	144:ef7eb2e8f9f7	436	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	437	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<>	144:ef7eb2e8f9f7	438
<>	144:ef7eb2e8f9f7	439	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	440	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	441
<>	144:ef7eb2e8f9f7	442	/* Change the htim state */
<>	144:ef7eb2e8f9f7	443	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	444
<>	144:ef7eb2e8f9f7	445	/* Return function status */
<>	144:ef7eb2e8f9f7	446	return HAL_OK;
<>	144:ef7eb2e8f9f7	447	}
<>	144:ef7eb2e8f9f7	448
<>	144:ef7eb2e8f9f7	449	/**
<>	144:ef7eb2e8f9f7	450	* @}
<>	144:ef7eb2e8f9f7	451	*/
<>	144:ef7eb2e8f9f7	452
<>	144:ef7eb2e8f9f7	453	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
<>	144:ef7eb2e8f9f7	454	* @brief Time Output Compare functions
<>	144:ef7eb2e8f9f7	455	*
<>	144:ef7eb2e8f9f7	456	@verbatim
<>	144:ef7eb2e8f9f7	457	==============================================================================
<>	144:ef7eb2e8f9f7	458	##### Time Output Compare functions #####
<>	144:ef7eb2e8f9f7	459	==============================================================================
<>	144:ef7eb2e8f9f7	460	[..]
<>	144:ef7eb2e8f9f7	461	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	462	(+) Initialize and configure the TIM Output Compare.
<>	144:ef7eb2e8f9f7	463	(+) De-initialize the TIM Output Compare.
<>	144:ef7eb2e8f9f7	464	(+) Start the Time Output Compare.
<>	144:ef7eb2e8f9f7	465	(+) Stop the Time Output Compare.
<>	144:ef7eb2e8f9f7	466	(+) Start the Time Output Compare and enable interrupt.
<>	144:ef7eb2e8f9f7	467	(+) Stop the Time Output Compare and disable interrupt.
<>	144:ef7eb2e8f9f7	468	(+) Start the Time Output Compare and enable DMA transfer.
<>	144:ef7eb2e8f9f7	469	(+) Stop the Time Output Compare and disable DMA transfer.
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	@endverbatim
<>	144:ef7eb2e8f9f7	472	* @{
<>	144:ef7eb2e8f9f7	473	*/
<>	144:ef7eb2e8f9f7	474	/**
<>	144:ef7eb2e8f9f7	475	* @brief Initializes the TIM Output Compare according to the specified
<>	144:ef7eb2e8f9f7	476	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	477	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	478	* @retval HAL status
<>	144:ef7eb2e8f9f7	479	*/
<>	144:ef7eb2e8f9f7	480	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<>	144:ef7eb2e8f9f7	481	{
<>	144:ef7eb2e8f9f7	482	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	483	if(htim == NULL)
<>	144:ef7eb2e8f9f7	484	{
<>	144:ef7eb2e8f9f7	485	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	486	}
<>	144:ef7eb2e8f9f7	487
<>	144:ef7eb2e8f9f7	488	/* Check the parameters */
<>	144:ef7eb2e8f9f7	489	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	490	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	491	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	165:e614a9f1c9e2	492	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<>	144:ef7eb2e8f9f7	493
<>	144:ef7eb2e8f9f7	494	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	495	{
<>	144:ef7eb2e8f9f7	496	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	497	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	498
<>	144:ef7eb2e8f9f7	499	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	500	HAL_TIM_OC_MspInit(htim);
<>	144:ef7eb2e8f9f7	501	}
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	504	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	505
<>	144:ef7eb2e8f9f7	506	/* Init the base time for the Output Compare */
<>	144:ef7eb2e8f9f7	507	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	508
<>	144:ef7eb2e8f9f7	509	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	510	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512	return HAL_OK;
<>	144:ef7eb2e8f9f7	513	}
<>	144:ef7eb2e8f9f7	514
<>	144:ef7eb2e8f9f7	515	/**
<>	144:ef7eb2e8f9f7	516	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	517	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	518	* @retval HAL status
<>	144:ef7eb2e8f9f7	519	*/
<>	144:ef7eb2e8f9f7	520	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	521	{
<>	144:ef7eb2e8f9f7	522	/* Check the parameters */
<>	144:ef7eb2e8f9f7	523	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	524
<>	144:ef7eb2e8f9f7	525	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	526
<>	144:ef7eb2e8f9f7	527	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	528	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	531	HAL_TIM_OC_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	532
<>	144:ef7eb2e8f9f7	533	/* Change TIM state */
<>	144:ef7eb2e8f9f7	534	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	535
<>	144:ef7eb2e8f9f7	536	/* Release Lock */
<>	144:ef7eb2e8f9f7	537	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	538
<>	144:ef7eb2e8f9f7	539	return HAL_OK;
<>	144:ef7eb2e8f9f7	540	}
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542	/**
<>	144:ef7eb2e8f9f7	543	* @brief Initializes the TIM Output Compare MSP.
<>	144:ef7eb2e8f9f7	544	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	545	* @retval None
<>	144:ef7eb2e8f9f7	546	*/
<>	144:ef7eb2e8f9f7	547	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	548	{
<>	144:ef7eb2e8f9f7	549	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	550	UNUSED(htim);
<>	144:ef7eb2e8f9f7	551	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	552	the HAL_TIM_OC_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	553	*/
<>	144:ef7eb2e8f9f7	554	}
<>	144:ef7eb2e8f9f7	555
<>	144:ef7eb2e8f9f7	556	/**
<>	144:ef7eb2e8f9f7	557	* @brief DeInitializes TIM Output Compare MSP.
<>	144:ef7eb2e8f9f7	558	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	559	* @retval None
<>	144:ef7eb2e8f9f7	560	*/
<>	144:ef7eb2e8f9f7	561	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	562	{
<>	144:ef7eb2e8f9f7	563	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	564	UNUSED(htim);
<>	144:ef7eb2e8f9f7	565	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	566	the HAL_TIM_OC_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	567	*/
<>	144:ef7eb2e8f9f7	568	}
<>	144:ef7eb2e8f9f7	569
<>	144:ef7eb2e8f9f7	570	/**
<>	144:ef7eb2e8f9f7	571	* @brief Starts the TIM Output Compare signal generation.
<>	144:ef7eb2e8f9f7	572	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	573	* @param Channel : TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	574	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	575	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	576	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	577	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	578	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	579	* @retval HAL status
<>	144:ef7eb2e8f9f7	580	*/
<>	144:ef7eb2e8f9f7	581	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	582	{
<>	144:ef7eb2e8f9f7	583	/* Check the parameters */
<>	144:ef7eb2e8f9f7	584	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	585
<>	144:ef7eb2e8f9f7	586	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	587	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	590	{
<>	144:ef7eb2e8f9f7	591	/* Enable the main output */
<>	144:ef7eb2e8f9f7	592	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	593	}
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	596	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	/* Return function status */
<>	144:ef7eb2e8f9f7	599	return HAL_OK;
<>	144:ef7eb2e8f9f7	600	}
<>	144:ef7eb2e8f9f7	601
<>	144:ef7eb2e8f9f7	602	/**
<>	144:ef7eb2e8f9f7	603	* @brief Stops the TIM Output Compare signal generation.
<>	144:ef7eb2e8f9f7	604	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	605	* @param Channel : TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	606	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	607	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	608	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	609	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	610	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	611	* @retval HAL status
<>	144:ef7eb2e8f9f7	612	*/
<>	144:ef7eb2e8f9f7	613	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	614	{
<>	144:ef7eb2e8f9f7	615	/* Check the parameters */
<>	144:ef7eb2e8f9f7	616	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	617
<>	144:ef7eb2e8f9f7	618	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	619	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	620
<>	144:ef7eb2e8f9f7	621	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	622	{
<>	144:ef7eb2e8f9f7	623	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	624	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	625	}
<>	144:ef7eb2e8f9f7	626
<>	144:ef7eb2e8f9f7	627	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	628	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	629
<>	144:ef7eb2e8f9f7	630	/* Return function status */
<>	144:ef7eb2e8f9f7	631	return HAL_OK;
<>	144:ef7eb2e8f9f7	632	}
<>	144:ef7eb2e8f9f7	633
<>	144:ef7eb2e8f9f7	634	/**
<>	144:ef7eb2e8f9f7	635	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	636	* @param htim : TIM OC handle
<>	144:ef7eb2e8f9f7	637	* @param Channel : TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	638	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	639	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	640	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	641	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	642	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	643	* @retval HAL status
<>	144:ef7eb2e8f9f7	644	*/
<>	144:ef7eb2e8f9f7	645	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	646	{
<>	144:ef7eb2e8f9f7	647	/* Check the parameters */
<>	144:ef7eb2e8f9f7	648	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	649
<>	144:ef7eb2e8f9f7	650	switch (Channel)
<>	144:ef7eb2e8f9f7	651	{
<>	144:ef7eb2e8f9f7	652	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	653	{
<>	144:ef7eb2e8f9f7	654	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	655	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	656	}
<>	144:ef7eb2e8f9f7	657	break;
<>	144:ef7eb2e8f9f7	658
<>	144:ef7eb2e8f9f7	659	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	660	{
<>	144:ef7eb2e8f9f7	661	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	662	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	663	}
<>	144:ef7eb2e8f9f7	664	break;
<>	144:ef7eb2e8f9f7	665
<>	144:ef7eb2e8f9f7	666	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	667	{
<>	144:ef7eb2e8f9f7	668	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	669	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	670	}
<>	144:ef7eb2e8f9f7	671	break;
<>	144:ef7eb2e8f9f7	672
<>	144:ef7eb2e8f9f7	673	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	674	{
<>	144:ef7eb2e8f9f7	675	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	676	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	677	}
<>	144:ef7eb2e8f9f7	678	break;
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	default:
<>	144:ef7eb2e8f9f7	681	break;
<>	144:ef7eb2e8f9f7	682	}
<>	144:ef7eb2e8f9f7	683
<>	144:ef7eb2e8f9f7	684	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	685	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	686
<>	144:ef7eb2e8f9f7	687	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	688	{
<>	144:ef7eb2e8f9f7	689	/* Enable the main output */
<>	144:ef7eb2e8f9f7	690	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	691	}
<>	144:ef7eb2e8f9f7	692
<>	144:ef7eb2e8f9f7	693	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	694	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	695
<>	144:ef7eb2e8f9f7	696	/* Return function status */
<>	144:ef7eb2e8f9f7	697	return HAL_OK;
<>	144:ef7eb2e8f9f7	698	}
<>	144:ef7eb2e8f9f7	699
<>	144:ef7eb2e8f9f7	700	/**
<>	144:ef7eb2e8f9f7	701	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	702	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	703	* @param Channel : TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	704	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	705	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	706	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	707	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	708	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	709	* @retval HAL status
<>	144:ef7eb2e8f9f7	710	*/
<>	144:ef7eb2e8f9f7	711	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	712	{
<>	144:ef7eb2e8f9f7	713	/* Check the parameters */
<>	144:ef7eb2e8f9f7	714	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	715
<>	144:ef7eb2e8f9f7	716	switch (Channel)
<>	144:ef7eb2e8f9f7	717	{
<>	144:ef7eb2e8f9f7	718	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	719	{
<>	144:ef7eb2e8f9f7	720	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	721	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	722	}
<>	144:ef7eb2e8f9f7	723	break;
<>	144:ef7eb2e8f9f7	724
<>	144:ef7eb2e8f9f7	725	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	726	{
<>	144:ef7eb2e8f9f7	727	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	728	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	729	}
<>	144:ef7eb2e8f9f7	730	break;
<>	144:ef7eb2e8f9f7	731
<>	144:ef7eb2e8f9f7	732	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	733	{
<>	144:ef7eb2e8f9f7	734	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	735	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	736	}
<>	144:ef7eb2e8f9f7	737	break;
<>	144:ef7eb2e8f9f7	738
<>	144:ef7eb2e8f9f7	739	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	740	{
<>	144:ef7eb2e8f9f7	741	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	742	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	743	}
<>	144:ef7eb2e8f9f7	744	break;
<>	144:ef7eb2e8f9f7	745
<>	144:ef7eb2e8f9f7	746	default:
<>	144:ef7eb2e8f9f7	747	break;
<>	144:ef7eb2e8f9f7	748	}
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	751	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	752
<>	144:ef7eb2e8f9f7	753	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	754	{
<>	144:ef7eb2e8f9f7	755	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	756	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	757	}
<>	144:ef7eb2e8f9f7	758
<>	144:ef7eb2e8f9f7	759	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	760	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	/* Return function status */
<>	144:ef7eb2e8f9f7	763	return HAL_OK;
<>	144:ef7eb2e8f9f7	764	}
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	/**
<>	144:ef7eb2e8f9f7	767	* @brief Starts the TIM Output Compare signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	768	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	769	* @param Channel : TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	770	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	771	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	772	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	773	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	774	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	775	* @param pData : The source Buffer address.
<>	144:ef7eb2e8f9f7	776	* @param Length : The length of data to be transferred from memory to TIM peripheral
<>	144:ef7eb2e8f9f7	777	* @retval HAL status
<>	144:ef7eb2e8f9f7	778	*/
<>	144:ef7eb2e8f9f7	779	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	780	{
<>	144:ef7eb2e8f9f7	781	/* Check the parameters */
<>	144:ef7eb2e8f9f7	782	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	783
<>	144:ef7eb2e8f9f7	784	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	785	{
<>	144:ef7eb2e8f9f7	786	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	787	}
<>	144:ef7eb2e8f9f7	788	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	789	{
AnnaBridge	165:e614a9f1c9e2	790	if(((uint32_t)pData == 0U) && (Length > 0U))
<>	144:ef7eb2e8f9f7	791	{
<>	144:ef7eb2e8f9f7	792	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	793	}
<>	144:ef7eb2e8f9f7	794	else
<>	144:ef7eb2e8f9f7	795	{
<>	144:ef7eb2e8f9f7	796	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	797	}
<>	144:ef7eb2e8f9f7	798	}
<>	144:ef7eb2e8f9f7	799	switch (Channel)
<>	144:ef7eb2e8f9f7	800	{
<>	144:ef7eb2e8f9f7	801	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	802	{
<>	144:ef7eb2e8f9f7	803	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	804	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	805
<>	144:ef7eb2e8f9f7	806	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	807	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	808
<>	144:ef7eb2e8f9f7	809	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	810	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	813	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	814	}
<>	144:ef7eb2e8f9f7	815	break;
<>	144:ef7eb2e8f9f7	816
<>	144:ef7eb2e8f9f7	817	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	818	{
<>	144:ef7eb2e8f9f7	819	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	820	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	821
<>	144:ef7eb2e8f9f7	822	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	823	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	826	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	144:ef7eb2e8f9f7	827
<>	144:ef7eb2e8f9f7	828	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	829	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	830	}
<>	144:ef7eb2e8f9f7	831	break;
<>	144:ef7eb2e8f9f7	832
<>	144:ef7eb2e8f9f7	833	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	834	{
<>	144:ef7eb2e8f9f7	835	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	836	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	837
<>	144:ef7eb2e8f9f7	838	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	839	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	842	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	144:ef7eb2e8f9f7	843
<>	144:ef7eb2e8f9f7	844	/* Enable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	845	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	846	}
<>	144:ef7eb2e8f9f7	847	break;
<>	144:ef7eb2e8f9f7	848
<>	144:ef7eb2e8f9f7	849	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	850	{
<>	144:ef7eb2e8f9f7	851	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	852	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	853
<>	144:ef7eb2e8f9f7	854	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	855	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	858	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	861	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	862	}
<>	144:ef7eb2e8f9f7	863	break;
<>	144:ef7eb2e8f9f7	864
<>	144:ef7eb2e8f9f7	865	default:
<>	144:ef7eb2e8f9f7	866	break;
<>	144:ef7eb2e8f9f7	867	}
<>	144:ef7eb2e8f9f7	868
<>	144:ef7eb2e8f9f7	869	/* Enable the Output compare channel */
<>	144:ef7eb2e8f9f7	870	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	873	{
<>	144:ef7eb2e8f9f7	874	/* Enable the main output */
<>	144:ef7eb2e8f9f7	875	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	876	}
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	879	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/* Return function status */
<>	144:ef7eb2e8f9f7	882	return HAL_OK;
<>	144:ef7eb2e8f9f7	883	}
<>	144:ef7eb2e8f9f7	884
<>	144:ef7eb2e8f9f7	885	/**
<>	144:ef7eb2e8f9f7	886	* @brief Stops the TIM Output Compare signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	887	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	888	* @param Channel : TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	889	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	890	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	891	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	892	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	893	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	894	* @retval HAL status
<>	144:ef7eb2e8f9f7	895	*/
<>	144:ef7eb2e8f9f7	896	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	897	{
<>	144:ef7eb2e8f9f7	898	/* Check the parameters */
<>	144:ef7eb2e8f9f7	899	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	900
<>	144:ef7eb2e8f9f7	901	switch (Channel)
<>	144:ef7eb2e8f9f7	902	{
<>	144:ef7eb2e8f9f7	903	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	904	{
<>	144:ef7eb2e8f9f7	905	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	906	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	907	}
<>	144:ef7eb2e8f9f7	908	break;
<>	144:ef7eb2e8f9f7	909
<>	144:ef7eb2e8f9f7	910	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	911	{
<>	144:ef7eb2e8f9f7	912	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	913	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	914	}
<>	144:ef7eb2e8f9f7	915	break;
<>	144:ef7eb2e8f9f7	916
<>	144:ef7eb2e8f9f7	917	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	918	{
<>	144:ef7eb2e8f9f7	919	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	920	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	921	}
<>	144:ef7eb2e8f9f7	922	break;
<>	144:ef7eb2e8f9f7	923
<>	144:ef7eb2e8f9f7	924	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	925	{
<>	144:ef7eb2e8f9f7	926	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	927	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	928	}
<>	144:ef7eb2e8f9f7	929	break;
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931	default:
<>	144:ef7eb2e8f9f7	932	break;
<>	144:ef7eb2e8f9f7	933	}
<>	144:ef7eb2e8f9f7	934
<>	144:ef7eb2e8f9f7	935	/* Disable the Output compare channel */
<>	144:ef7eb2e8f9f7	936	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	937
<>	144:ef7eb2e8f9f7	938	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	939	{
<>	144:ef7eb2e8f9f7	940	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	941	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	942	}
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	945	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	/* Change the htim state */
<>	144:ef7eb2e8f9f7	948	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	/* Return function status */
<>	144:ef7eb2e8f9f7	951	return HAL_OK;
<>	144:ef7eb2e8f9f7	952	}
<>	144:ef7eb2e8f9f7	953
<>	144:ef7eb2e8f9f7	954	/**
<>	144:ef7eb2e8f9f7	955	* @}
<>	144:ef7eb2e8f9f7	956	*/
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
<>	144:ef7eb2e8f9f7	959	* @brief Time PWM functions
<>	144:ef7eb2e8f9f7	960	*
<>	144:ef7eb2e8f9f7	961	@verbatim
<>	144:ef7eb2e8f9f7	962	==============================================================================
<>	144:ef7eb2e8f9f7	963	##### Time PWM functions #####
<>	144:ef7eb2e8f9f7	964	==============================================================================
<>	144:ef7eb2e8f9f7	965	[..]
<>	144:ef7eb2e8f9f7	966	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	967	(+) Initialize and configure the TIM PWM.
<>	144:ef7eb2e8f9f7	968	(+) De-initialize the TIM PWM.
<>	144:ef7eb2e8f9f7	969	(+) Start the Time PWM.
<>	144:ef7eb2e8f9f7	970	(+) Stop the Time PWM.
<>	144:ef7eb2e8f9f7	971	(+) Start the Time PWM and enable interrupt.
<>	144:ef7eb2e8f9f7	972	(+) Stop the Time PWM and disable interrupt.
<>	144:ef7eb2e8f9f7	973	(+) Start the Time PWM and enable DMA transfer.
<>	144:ef7eb2e8f9f7	974	(+) Stop the Time PWM and disable DMA transfer.
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	@endverbatim
<>	144:ef7eb2e8f9f7	977	* @{
<>	144:ef7eb2e8f9f7	978	*/
<>	144:ef7eb2e8f9f7	979	/**
<>	144:ef7eb2e8f9f7	980	* @brief Initializes the TIM PWM Time Base according to the specified
<>	144:ef7eb2e8f9f7	981	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	982	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	983	* @retval HAL status
<>	144:ef7eb2e8f9f7	984	*/
<>	144:ef7eb2e8f9f7	985	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	986	{
<>	144:ef7eb2e8f9f7	987	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	988	if(htim == NULL)
<>	144:ef7eb2e8f9f7	989	{
<>	144:ef7eb2e8f9f7	990	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	991	}
<>	144:ef7eb2e8f9f7	992
<>	144:ef7eb2e8f9f7	993	/* Check the parameters */
<>	144:ef7eb2e8f9f7	994	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	995	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	996	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	165:e614a9f1c9e2	997	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1000	{
<>	144:ef7eb2e8f9f7	1001	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	1002	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	1003
<>	144:ef7eb2e8f9f7	1004	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1005	HAL_TIM_PWM_MspInit(htim);
<>	144:ef7eb2e8f9f7	1006	}
<>	144:ef7eb2e8f9f7	1007
<>	144:ef7eb2e8f9f7	1008	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	1009	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1010
<>	144:ef7eb2e8f9f7	1011	/* Init the base time for the PWM */
<>	144:ef7eb2e8f9f7	1012	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	1013
<>	144:ef7eb2e8f9f7	1014	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	1015	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1016
<>	144:ef7eb2e8f9f7	1017	return HAL_OK;
<>	144:ef7eb2e8f9f7	1018	}
<>	144:ef7eb2e8f9f7	1019
<>	144:ef7eb2e8f9f7	1020	/**
<>	144:ef7eb2e8f9f7	1021	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	1022	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1023	* @retval HAL status
<>	144:ef7eb2e8f9f7	1024	*/
<>	144:ef7eb2e8f9f7	1025	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1026	{
<>	144:ef7eb2e8f9f7	1027	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1028	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1029
<>	144:ef7eb2e8f9f7	1030	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	1033	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1036	HAL_TIM_PWM_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	/* Change TIM state */
<>	144:ef7eb2e8f9f7	1039	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	/* Release Lock */
<>	144:ef7eb2e8f9f7	1042	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1043
<>	144:ef7eb2e8f9f7	1044	return HAL_OK;
<>	144:ef7eb2e8f9f7	1045	}
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/**
<>	144:ef7eb2e8f9f7	1048	* @brief Initializes the TIM PWM MSP.
<>	144:ef7eb2e8f9f7	1049	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1050	* @retval None
<>	144:ef7eb2e8f9f7	1051	*/
<>	144:ef7eb2e8f9f7	1052	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1053	{
<>	144:ef7eb2e8f9f7	1054	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1055	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1056	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1057	the HAL_TIM_PWM_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1058	*/
<>	144:ef7eb2e8f9f7	1059	}
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	/**
<>	144:ef7eb2e8f9f7	1062	* @brief DeInitializes TIM PWM MSP.
<>	144:ef7eb2e8f9f7	1063	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1064	* @retval None
<>	144:ef7eb2e8f9f7	1065	*/
<>	144:ef7eb2e8f9f7	1066	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1067	{
<>	144:ef7eb2e8f9f7	1068	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1069	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1070	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1071	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1072	*/
<>	144:ef7eb2e8f9f7	1073	}
<>	144:ef7eb2e8f9f7	1074
<>	144:ef7eb2e8f9f7	1075	/**
<>	144:ef7eb2e8f9f7	1076	* @brief Starts the PWM signal generation.
<>	144:ef7eb2e8f9f7	1077	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1078	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1079	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1080	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1081	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1082	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1083	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1084	* @retval HAL status
<>	144:ef7eb2e8f9f7	1085	*/
<>	144:ef7eb2e8f9f7	1086	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1087	{
<>	144:ef7eb2e8f9f7	1088	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1089	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1090
<>	144:ef7eb2e8f9f7	1091	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1092	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1093
<>	144:ef7eb2e8f9f7	1094	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1095	{
<>	144:ef7eb2e8f9f7	1096	/* Enable the main output */
<>	144:ef7eb2e8f9f7	1097	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1098	}
<>	144:ef7eb2e8f9f7	1099
<>	144:ef7eb2e8f9f7	1100	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1101	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103	/* Return function status */
<>	144:ef7eb2e8f9f7	1104	return HAL_OK;
<>	144:ef7eb2e8f9f7	1105	}
<>	144:ef7eb2e8f9f7	1106
<>	144:ef7eb2e8f9f7	1107	/**
<>	144:ef7eb2e8f9f7	1108	* @brief Stops the PWM signal generation.
<>	144:ef7eb2e8f9f7	1109	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1110	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1111	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1112	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1113	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1114	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1115	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1116	* @retval HAL status
<>	144:ef7eb2e8f9f7	1117	*/
<>	144:ef7eb2e8f9f7	1118	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1119	{
<>	144:ef7eb2e8f9f7	1120	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1121	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1124	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1127	{
<>	144:ef7eb2e8f9f7	1128	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	1129	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1130	}
<>	144:ef7eb2e8f9f7	1131
<>	144:ef7eb2e8f9f7	1132	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1133	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1134
<>	144:ef7eb2e8f9f7	1135	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1136	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1137
<>	144:ef7eb2e8f9f7	1138	/* Return function status */
<>	144:ef7eb2e8f9f7	1139	return HAL_OK;
<>	144:ef7eb2e8f9f7	1140	}
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	/**
<>	144:ef7eb2e8f9f7	1143	* @brief Starts the PWM signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	1144	* @param htim : TIM handle
AnnaBridge	165:e614a9f1c9e2	1145	* @param Channel : TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	1146	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1147	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1148	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1149	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1150	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1151	* @retval HAL status
<>	144:ef7eb2e8f9f7	1152	*/
<>	144:ef7eb2e8f9f7	1153	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1154	{
<>	144:ef7eb2e8f9f7	1155	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1156	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1157
<>	144:ef7eb2e8f9f7	1158	switch (Channel)
<>	144:ef7eb2e8f9f7	1159	{
<>	144:ef7eb2e8f9f7	1160	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1161	{
<>	144:ef7eb2e8f9f7	1162	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1163	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1164	}
<>	144:ef7eb2e8f9f7	1165	break;
<>	144:ef7eb2e8f9f7	1166
<>	144:ef7eb2e8f9f7	1167	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1168	{
<>	144:ef7eb2e8f9f7	1169	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1170	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1171	}
<>	144:ef7eb2e8f9f7	1172	break;
<>	144:ef7eb2e8f9f7	1173
<>	144:ef7eb2e8f9f7	1174	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1175	{
<>	144:ef7eb2e8f9f7	1176	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1177	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1178	}
<>	144:ef7eb2e8f9f7	1179	break;
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1182	{
<>	144:ef7eb2e8f9f7	1183	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1184	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1185	}
<>	144:ef7eb2e8f9f7	1186	break;
<>	144:ef7eb2e8f9f7	1187
<>	144:ef7eb2e8f9f7	1188	default:
<>	144:ef7eb2e8f9f7	1189	break;
<>	144:ef7eb2e8f9f7	1190	}
<>	144:ef7eb2e8f9f7	1191
<>	144:ef7eb2e8f9f7	1192	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1193	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1194
<>	144:ef7eb2e8f9f7	1195	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1196	{
<>	144:ef7eb2e8f9f7	1197	/* Enable the main output */
<>	144:ef7eb2e8f9f7	1198	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1199	}
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1202	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1203
<>	144:ef7eb2e8f9f7	1204	/* Return function status */
<>	144:ef7eb2e8f9f7	1205	return HAL_OK;
<>	144:ef7eb2e8f9f7	1206	}
<>	144:ef7eb2e8f9f7	1207
<>	144:ef7eb2e8f9f7	1208	/**
<>	144:ef7eb2e8f9f7	1209	* @brief Stops the PWM signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	1210	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1211	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1212	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1213	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1214	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1215	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1216	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1217	* @retval HAL status
<>	144:ef7eb2e8f9f7	1218	*/
<>	144:ef7eb2e8f9f7	1219	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1220	{
<>	144:ef7eb2e8f9f7	1221	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1222	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1223
<>	144:ef7eb2e8f9f7	1224	switch (Channel)
<>	144:ef7eb2e8f9f7	1225	{
<>	144:ef7eb2e8f9f7	1226	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1227	{
<>	144:ef7eb2e8f9f7	1228	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1229	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1230	}
<>	144:ef7eb2e8f9f7	1231	break;
<>	144:ef7eb2e8f9f7	1232
<>	144:ef7eb2e8f9f7	1233	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1234	{
<>	144:ef7eb2e8f9f7	1235	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1236	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1237	}
<>	144:ef7eb2e8f9f7	1238	break;
<>	144:ef7eb2e8f9f7	1239
<>	144:ef7eb2e8f9f7	1240	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1241	{
<>	144:ef7eb2e8f9f7	1242	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1243	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1244	}
<>	144:ef7eb2e8f9f7	1245	break;
<>	144:ef7eb2e8f9f7	1246
<>	144:ef7eb2e8f9f7	1247	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1248	{
<>	144:ef7eb2e8f9f7	1249	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1250	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1251	}
<>	144:ef7eb2e8f9f7	1252	break;
<>	144:ef7eb2e8f9f7	1253
<>	144:ef7eb2e8f9f7	1254	default:
<>	144:ef7eb2e8f9f7	1255	break;
<>	144:ef7eb2e8f9f7	1256	}
<>	144:ef7eb2e8f9f7	1257
<>	144:ef7eb2e8f9f7	1258	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1259	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1260
<>	144:ef7eb2e8f9f7	1261	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1262	{
<>	144:ef7eb2e8f9f7	1263	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	1264	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1265	}
<>	144:ef7eb2e8f9f7	1266
<>	144:ef7eb2e8f9f7	1267	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1268	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1269
<>	144:ef7eb2e8f9f7	1270	/* Return function status */
<>	144:ef7eb2e8f9f7	1271	return HAL_OK;
<>	144:ef7eb2e8f9f7	1272	}
<>	144:ef7eb2e8f9f7	1273
<>	144:ef7eb2e8f9f7	1274	/**
<>	144:ef7eb2e8f9f7	1275	* @brief Starts the TIM PWM signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	1276	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1277	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1278	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1279	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1280	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1281	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1282	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1283	* @param pData : The source Buffer address.
<>	144:ef7eb2e8f9f7	1284	* @param Length : The length of data to be transferred from memory to TIM peripheral
<>	144:ef7eb2e8f9f7	1285	* @retval HAL status
<>	144:ef7eb2e8f9f7	1286	*/
<>	144:ef7eb2e8f9f7	1287	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	1288	{
<>	144:ef7eb2e8f9f7	1289	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1290	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	1293	{
<>	144:ef7eb2e8f9f7	1294	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1295	}
<>	144:ef7eb2e8f9f7	1296	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	1297	{
AnnaBridge	165:e614a9f1c9e2	1298	if(((uint32_t)pData == 0U) && (Length > 0U))
<>	144:ef7eb2e8f9f7	1299	{
<>	144:ef7eb2e8f9f7	1300	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1301	}
<>	144:ef7eb2e8f9f7	1302	else
<>	144:ef7eb2e8f9f7	1303	{
<>	144:ef7eb2e8f9f7	1304	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1305	}
<>	144:ef7eb2e8f9f7	1306	}
<>	144:ef7eb2e8f9f7	1307	switch (Channel)
<>	144:ef7eb2e8f9f7	1308	{
<>	144:ef7eb2e8f9f7	1309	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1310	{
<>	144:ef7eb2e8f9f7	1311	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1312	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1313
<>	144:ef7eb2e8f9f7	1314	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1315	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1316
<>	144:ef7eb2e8f9f7	1317	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1318	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	144:ef7eb2e8f9f7	1319
<>	144:ef7eb2e8f9f7	1320	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1321	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1322	}
<>	144:ef7eb2e8f9f7	1323	break;
<>	144:ef7eb2e8f9f7	1324
<>	144:ef7eb2e8f9f7	1325	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1326	{
<>	144:ef7eb2e8f9f7	1327	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1328	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1329
<>	144:ef7eb2e8f9f7	1330	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1331	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1332
<>	144:ef7eb2e8f9f7	1333	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1334	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	144:ef7eb2e8f9f7	1335
<>	144:ef7eb2e8f9f7	1336	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1337	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1338	}
<>	144:ef7eb2e8f9f7	1339	break;
<>	144:ef7eb2e8f9f7	1340
<>	144:ef7eb2e8f9f7	1341	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1342	{
<>	144:ef7eb2e8f9f7	1343	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1344	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1345
<>	144:ef7eb2e8f9f7	1346	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1347	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1348
<>	144:ef7eb2e8f9f7	1349	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1350	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	144:ef7eb2e8f9f7	1351
<>	144:ef7eb2e8f9f7	1352	/* Enable the TIM Output Capture/Compare 3 request */
<>	144:ef7eb2e8f9f7	1353	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1354	}
<>	144:ef7eb2e8f9f7	1355	break;
<>	144:ef7eb2e8f9f7	1356
<>	144:ef7eb2e8f9f7	1357	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1358	{
<>	144:ef7eb2e8f9f7	1359	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1360	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1361
<>	144:ef7eb2e8f9f7	1362	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1363	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1364
<>	144:ef7eb2e8f9f7	1365	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1366	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	144:ef7eb2e8f9f7	1367
<>	144:ef7eb2e8f9f7	1368	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1369	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1370	}
<>	144:ef7eb2e8f9f7	1371	break;
<>	144:ef7eb2e8f9f7	1372
<>	144:ef7eb2e8f9f7	1373	default:
<>	144:ef7eb2e8f9f7	1374	break;
<>	144:ef7eb2e8f9f7	1375	}
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1378	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1379
<>	144:ef7eb2e8f9f7	1380	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1381	{
<>	144:ef7eb2e8f9f7	1382	/* Enable the main output */
<>	144:ef7eb2e8f9f7	1383	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1384	}
<>	144:ef7eb2e8f9f7	1385
<>	144:ef7eb2e8f9f7	1386	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1387	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1388
<>	144:ef7eb2e8f9f7	1389	/* Return function status */
<>	144:ef7eb2e8f9f7	1390	return HAL_OK;
<>	144:ef7eb2e8f9f7	1391	}
<>	144:ef7eb2e8f9f7	1392
<>	144:ef7eb2e8f9f7	1393	/**
<>	144:ef7eb2e8f9f7	1394	* @brief Stops the TIM PWM signal generation in DMA mode.
<>	144:ef7eb2e8f9f7	1395	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1396	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1397	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1398	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1399	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1400	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1401	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1402	* @retval HAL status
<>	144:ef7eb2e8f9f7	1403	*/
<>	144:ef7eb2e8f9f7	1404	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1405	{
<>	144:ef7eb2e8f9f7	1406	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1407	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1408
<>	144:ef7eb2e8f9f7	1409	switch (Channel)
<>	144:ef7eb2e8f9f7	1410	{
<>	144:ef7eb2e8f9f7	1411	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1412	{
<>	144:ef7eb2e8f9f7	1413	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1414	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1415	}
<>	144:ef7eb2e8f9f7	1416	break;
<>	144:ef7eb2e8f9f7	1417
<>	144:ef7eb2e8f9f7	1418	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1419	{
<>	144:ef7eb2e8f9f7	1420	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1421	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1422	}
<>	144:ef7eb2e8f9f7	1423	break;
<>	144:ef7eb2e8f9f7	1424
<>	144:ef7eb2e8f9f7	1425	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1426	{
<>	144:ef7eb2e8f9f7	1427	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1428	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1429	}
<>	144:ef7eb2e8f9f7	1430	break;
<>	144:ef7eb2e8f9f7	1431
<>	144:ef7eb2e8f9f7	1432	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1433	{
<>	144:ef7eb2e8f9f7	1434	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1435	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1436	}
<>	144:ef7eb2e8f9f7	1437	break;
<>	144:ef7eb2e8f9f7	1438
<>	144:ef7eb2e8f9f7	1439	default:
<>	144:ef7eb2e8f9f7	1440	break;
<>	144:ef7eb2e8f9f7	1441	}
<>	144:ef7eb2e8f9f7	1442
<>	144:ef7eb2e8f9f7	1443	/* Disable the Capture compare channel */
<>	144:ef7eb2e8f9f7	1444	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1445
<>	144:ef7eb2e8f9f7	1446	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	1447	{
<>	144:ef7eb2e8f9f7	1448	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	1449	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1450	}
<>	144:ef7eb2e8f9f7	1451
<>	144:ef7eb2e8f9f7	1452	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1453	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1454
<>	144:ef7eb2e8f9f7	1455	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1456	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1457
<>	144:ef7eb2e8f9f7	1458	/* Return function status */
<>	144:ef7eb2e8f9f7	1459	return HAL_OK;
<>	144:ef7eb2e8f9f7	1460	}
<>	144:ef7eb2e8f9f7	1461
<>	144:ef7eb2e8f9f7	1462	/**
<>	144:ef7eb2e8f9f7	1463	* @}
<>	144:ef7eb2e8f9f7	1464	*/
<>	144:ef7eb2e8f9f7	1465
<>	144:ef7eb2e8f9f7	1466	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
<>	144:ef7eb2e8f9f7	1467	* @brief Time Input Capture functions
<>	144:ef7eb2e8f9f7	1468	*
<>	144:ef7eb2e8f9f7	1469	@verbatim
<>	144:ef7eb2e8f9f7	1470	==============================================================================
<>	144:ef7eb2e8f9f7	1471	##### Time Input Capture functions #####
<>	144:ef7eb2e8f9f7	1472	==============================================================================
<>	144:ef7eb2e8f9f7	1473	[..]
<>	144:ef7eb2e8f9f7	1474	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1475	(+) Initialize and configure the TIM Input Capture.
<>	144:ef7eb2e8f9f7	1476	(+) De-initialize the TIM Input Capture.
<>	144:ef7eb2e8f9f7	1477	(+) Start the Time Input Capture.
<>	144:ef7eb2e8f9f7	1478	(+) Stop the Time Input Capture.
<>	144:ef7eb2e8f9f7	1479	(+) Start the Time Input Capture and enable interrupt.
<>	144:ef7eb2e8f9f7	1480	(+) Stop the Time Input Capture and disable interrupt.
<>	144:ef7eb2e8f9f7	1481	(+) Start the Time Input Capture and enable DMA transfer.
<>	144:ef7eb2e8f9f7	1482	(+) Stop the Time Input Capture and disable DMA transfer.
<>	144:ef7eb2e8f9f7	1483
<>	144:ef7eb2e8f9f7	1484	@endverbatim
<>	144:ef7eb2e8f9f7	1485	* @{
<>	144:ef7eb2e8f9f7	1486	*/
<>	144:ef7eb2e8f9f7	1487	/**
<>	144:ef7eb2e8f9f7	1488	* @brief Initializes the TIM Input Capture Time base according to the specified
<>	144:ef7eb2e8f9f7	1489	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	1490	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1491	* @retval HAL status
<>	144:ef7eb2e8f9f7	1492	*/
<>	144:ef7eb2e8f9f7	1493	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1494	{
<>	144:ef7eb2e8f9f7	1495	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	1496	if(htim == NULL)
<>	144:ef7eb2e8f9f7	1497	{
<>	144:ef7eb2e8f9f7	1498	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1499	}
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1502	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1503	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	1504	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	165:e614a9f1c9e2	1505	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<>	144:ef7eb2e8f9f7	1506
<>	144:ef7eb2e8f9f7	1507	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1508	{
<>	144:ef7eb2e8f9f7	1509	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	1510	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	1511
<>	144:ef7eb2e8f9f7	1512	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1513	HAL_TIM_IC_MspInit(htim);
<>	144:ef7eb2e8f9f7	1514	}
<>	144:ef7eb2e8f9f7	1515
<>	144:ef7eb2e8f9f7	1516	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	1517	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1518
<>	144:ef7eb2e8f9f7	1519	/* Init the base time for the input capture */
<>	144:ef7eb2e8f9f7	1520	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	1521
<>	144:ef7eb2e8f9f7	1522	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	1523	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1524
<>	144:ef7eb2e8f9f7	1525	return HAL_OK;
<>	144:ef7eb2e8f9f7	1526	}
<>	144:ef7eb2e8f9f7	1527
<>	144:ef7eb2e8f9f7	1528	/**
<>	144:ef7eb2e8f9f7	1529	* @brief DeInitializes the TIM peripheral
<>	144:ef7eb2e8f9f7	1530	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1531	* @retval HAL status
<>	144:ef7eb2e8f9f7	1532	*/
<>	144:ef7eb2e8f9f7	1533	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1534	{
<>	144:ef7eb2e8f9f7	1535	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1536	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1537
<>	144:ef7eb2e8f9f7	1538	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1539
<>	144:ef7eb2e8f9f7	1540	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	1541	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1542
<>	144:ef7eb2e8f9f7	1543	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1544	HAL_TIM_IC_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	/* Change TIM state */
<>	144:ef7eb2e8f9f7	1547	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	1548
<>	144:ef7eb2e8f9f7	1549	/* Release Lock */
<>	144:ef7eb2e8f9f7	1550	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1551
<>	144:ef7eb2e8f9f7	1552	return HAL_OK;
<>	144:ef7eb2e8f9f7	1553	}
<>	144:ef7eb2e8f9f7	1554
<>	144:ef7eb2e8f9f7	1555	/**
<>	144:ef7eb2e8f9f7	1556	* @brief Initializes the TIM Input Capture MSP.
<>	144:ef7eb2e8f9f7	1557	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1558	* @retval None
<>	144:ef7eb2e8f9f7	1559	*/
<>	144:ef7eb2e8f9f7	1560	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1561	{
<>	144:ef7eb2e8f9f7	1562	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1563	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1564	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1565	the HAL_TIM_IC_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1566	*/
<>	144:ef7eb2e8f9f7	1567	}
<>	144:ef7eb2e8f9f7	1568
<>	144:ef7eb2e8f9f7	1569	/**
<>	144:ef7eb2e8f9f7	1570	* @brief DeInitializes TIM Input Capture MSP.
<>	144:ef7eb2e8f9f7	1571	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1572	* @retval None
<>	144:ef7eb2e8f9f7	1573	*/
<>	144:ef7eb2e8f9f7	1574	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	1575	{
<>	144:ef7eb2e8f9f7	1576	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1577	UNUSED(htim);
<>	144:ef7eb2e8f9f7	1578	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1579	the HAL_TIM_IC_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	1580	*/
<>	144:ef7eb2e8f9f7	1581	}
<>	144:ef7eb2e8f9f7	1582
<>	144:ef7eb2e8f9f7	1583	/**
<>	144:ef7eb2e8f9f7	1584	* @brief Starts the TIM Input Capture measurement.
<>	144:ef7eb2e8f9f7	1585	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1586	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1587	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1588	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1589	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1590	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1591	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1592	* @retval HAL status
<>	144:ef7eb2e8f9f7	1593	*/
<>	144:ef7eb2e8f9f7	1594	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1595	{
<>	144:ef7eb2e8f9f7	1596	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1597	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1598
<>	144:ef7eb2e8f9f7	1599	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1600	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1601
<>	144:ef7eb2e8f9f7	1602	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1603	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1604
<>	144:ef7eb2e8f9f7	1605	/* Return function status */
<>	144:ef7eb2e8f9f7	1606	return HAL_OK;
<>	144:ef7eb2e8f9f7	1607	}
<>	144:ef7eb2e8f9f7	1608
<>	144:ef7eb2e8f9f7	1609	/**
<>	144:ef7eb2e8f9f7	1610	* @brief Stops the TIM Input Capture measurement.
<>	144:ef7eb2e8f9f7	1611	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1612	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1613	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1614	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1615	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1616	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1617	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1618	* @retval HAL status
<>	144:ef7eb2e8f9f7	1619	*/
<>	144:ef7eb2e8f9f7	1620	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1621	{
<>	144:ef7eb2e8f9f7	1622	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1623	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1624
<>	144:ef7eb2e8f9f7	1625	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1626	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1627
<>	144:ef7eb2e8f9f7	1628	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1629	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1630
<>	144:ef7eb2e8f9f7	1631	/* Return function status */
<>	144:ef7eb2e8f9f7	1632	return HAL_OK;
<>	144:ef7eb2e8f9f7	1633	}
<>	144:ef7eb2e8f9f7	1634
<>	144:ef7eb2e8f9f7	1635	/**
<>	144:ef7eb2e8f9f7	1636	* @brief Starts the TIM Input Capture measurement in interrupt mode.
<>	144:ef7eb2e8f9f7	1637	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1638	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1639	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1640	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1641	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1642	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1643	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1644	* @retval HAL status
<>	144:ef7eb2e8f9f7	1645	*/
<>	144:ef7eb2e8f9f7	1646	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1647	{
<>	144:ef7eb2e8f9f7	1648	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1649	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1650
<>	144:ef7eb2e8f9f7	1651	switch (Channel)
<>	144:ef7eb2e8f9f7	1652	{
<>	144:ef7eb2e8f9f7	1653	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1654	{
<>	144:ef7eb2e8f9f7	1655	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1656	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1657	}
<>	144:ef7eb2e8f9f7	1658	break;
<>	144:ef7eb2e8f9f7	1659
<>	144:ef7eb2e8f9f7	1660	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1661	{
<>	144:ef7eb2e8f9f7	1662	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1663	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1664	}
<>	144:ef7eb2e8f9f7	1665	break;
<>	144:ef7eb2e8f9f7	1666
<>	144:ef7eb2e8f9f7	1667	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1668	{
<>	144:ef7eb2e8f9f7	1669	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1670	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1671	}
<>	144:ef7eb2e8f9f7	1672	break;
<>	144:ef7eb2e8f9f7	1673
<>	144:ef7eb2e8f9f7	1674	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1675	{
<>	144:ef7eb2e8f9f7	1676	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1677	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1678	}
<>	144:ef7eb2e8f9f7	1679	break;
<>	144:ef7eb2e8f9f7	1680
<>	144:ef7eb2e8f9f7	1681	default:
<>	144:ef7eb2e8f9f7	1682	break;
<>	144:ef7eb2e8f9f7	1683	}
<>	144:ef7eb2e8f9f7	1684	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1685	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1686
<>	144:ef7eb2e8f9f7	1687	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1688	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1689
<>	144:ef7eb2e8f9f7	1690	/* Return function status */
<>	144:ef7eb2e8f9f7	1691	return HAL_OK;
<>	144:ef7eb2e8f9f7	1692	}
<>	144:ef7eb2e8f9f7	1693
<>	144:ef7eb2e8f9f7	1694	/**
<>	144:ef7eb2e8f9f7	1695	* @brief Stops the TIM Input Capture measurement in interrupt mode.
<>	144:ef7eb2e8f9f7	1696	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	1697	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1698	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1699	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1700	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1701	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1702	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1703	* @retval HAL status
<>	144:ef7eb2e8f9f7	1704	*/
<>	144:ef7eb2e8f9f7	1705	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1706	{
<>	144:ef7eb2e8f9f7	1707	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1708	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1709
<>	144:ef7eb2e8f9f7	1710	switch (Channel)
<>	144:ef7eb2e8f9f7	1711	{
<>	144:ef7eb2e8f9f7	1712	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1713	{
<>	144:ef7eb2e8f9f7	1714	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1715	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1716	}
<>	144:ef7eb2e8f9f7	1717	break;
<>	144:ef7eb2e8f9f7	1718
<>	144:ef7eb2e8f9f7	1719	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1720	{
<>	144:ef7eb2e8f9f7	1721	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1722	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1723	}
<>	144:ef7eb2e8f9f7	1724	break;
<>	144:ef7eb2e8f9f7	1725
<>	144:ef7eb2e8f9f7	1726	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1727	{
<>	144:ef7eb2e8f9f7	1728	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1729	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1730	}
<>	144:ef7eb2e8f9f7	1731	break;
<>	144:ef7eb2e8f9f7	1732
<>	144:ef7eb2e8f9f7	1733	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1734	{
<>	144:ef7eb2e8f9f7	1735	/* Disable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1736	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1737	}
<>	144:ef7eb2e8f9f7	1738	break;
<>	144:ef7eb2e8f9f7	1739
<>	144:ef7eb2e8f9f7	1740	default:
<>	144:ef7eb2e8f9f7	1741	break;
<>	144:ef7eb2e8f9f7	1742	}
<>	144:ef7eb2e8f9f7	1743
<>	144:ef7eb2e8f9f7	1744	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1745	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1746
<>	144:ef7eb2e8f9f7	1747	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1748	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1749
<>	144:ef7eb2e8f9f7	1750	/* Return function status */
<>	144:ef7eb2e8f9f7	1751	return HAL_OK;
<>	144:ef7eb2e8f9f7	1752	}
<>	144:ef7eb2e8f9f7	1753
<>	144:ef7eb2e8f9f7	1754	/**
<>	144:ef7eb2e8f9f7	1755	* @brief Starts the TIM Input Capture measurement in DMA mode.
<>	144:ef7eb2e8f9f7	1756	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1757	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	1758	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1759	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1760	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1761	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1762	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1763	* @param pData : The destination Buffer address.
<>	144:ef7eb2e8f9f7	1764	* @param Length : The length of data to be transferred from TIM peripheral to memory.
<>	144:ef7eb2e8f9f7	1765	* @retval HAL status
<>	144:ef7eb2e8f9f7	1766	*/
<>	144:ef7eb2e8f9f7	1767	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	1768	{
<>	144:ef7eb2e8f9f7	1769	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1770	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1771	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1772
<>	144:ef7eb2e8f9f7	1773	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	1774	{
<>	144:ef7eb2e8f9f7	1775	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1776	}
<>	144:ef7eb2e8f9f7	1777	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	1778	{
AnnaBridge	165:e614a9f1c9e2	1779	if((pData == 0U) && (Length > 0U))
<>	144:ef7eb2e8f9f7	1780	{
<>	144:ef7eb2e8f9f7	1781	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1782	}
<>	144:ef7eb2e8f9f7	1783	else
<>	144:ef7eb2e8f9f7	1784	{
<>	144:ef7eb2e8f9f7	1785	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1786	}
<>	144:ef7eb2e8f9f7	1787	}
<>	144:ef7eb2e8f9f7	1788
<>	144:ef7eb2e8f9f7	1789	switch (Channel)
<>	144:ef7eb2e8f9f7	1790	{
<>	144:ef7eb2e8f9f7	1791	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1792	{
<>	144:ef7eb2e8f9f7	1793	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1794	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1795
<>	144:ef7eb2e8f9f7	1796	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1797	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1798
<>	144:ef7eb2e8f9f7	1799	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1800	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1801
<>	144:ef7eb2e8f9f7	1802	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1803	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1804	}
<>	144:ef7eb2e8f9f7	1805	break;
<>	144:ef7eb2e8f9f7	1806
<>	144:ef7eb2e8f9f7	1807	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1808	{
<>	144:ef7eb2e8f9f7	1809	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1810	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1811
<>	144:ef7eb2e8f9f7	1812	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1813	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1814
<>	144:ef7eb2e8f9f7	1815	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1816	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1817
<>	144:ef7eb2e8f9f7	1818	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1819	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1820	}
<>	144:ef7eb2e8f9f7	1821	break;
<>	144:ef7eb2e8f9f7	1822
<>	144:ef7eb2e8f9f7	1823	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1824	{
<>	144:ef7eb2e8f9f7	1825	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1826	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1827
<>	144:ef7eb2e8f9f7	1828	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1829	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1830
<>	144:ef7eb2e8f9f7	1831	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1832	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1833
<>	144:ef7eb2e8f9f7	1834	/* Enable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1835	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1836	}
<>	144:ef7eb2e8f9f7	1837	break;
<>	144:ef7eb2e8f9f7	1838
<>	144:ef7eb2e8f9f7	1839	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1840	{
<>	144:ef7eb2e8f9f7	1841	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1842	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	1843
<>	144:ef7eb2e8f9f7	1844	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1845	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1846
<>	144:ef7eb2e8f9f7	1847	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1848	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	1849
<>	144:ef7eb2e8f9f7	1850	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1851	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1852	}
<>	144:ef7eb2e8f9f7	1853	break;
<>	144:ef7eb2e8f9f7	1854
<>	144:ef7eb2e8f9f7	1855	default:
<>	144:ef7eb2e8f9f7	1856	break;
<>	144:ef7eb2e8f9f7	1857	}
<>	144:ef7eb2e8f9f7	1858
<>	144:ef7eb2e8f9f7	1859	/* Enable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1860	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	1861
<>	144:ef7eb2e8f9f7	1862	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1863	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1864
<>	144:ef7eb2e8f9f7	1865	/* Return function status */
<>	144:ef7eb2e8f9f7	1866	return HAL_OK;
<>	144:ef7eb2e8f9f7	1867	}
<>	144:ef7eb2e8f9f7	1868
<>	144:ef7eb2e8f9f7	1869	/**
<>	144:ef7eb2e8f9f7	1870	* @brief Stops the TIM Input Capture measurement in DMA mode.
<>	144:ef7eb2e8f9f7	1871	* @param htim : TIM Input Capture handle
<>	144:ef7eb2e8f9f7	1872	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	1873	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1874	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1875	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1876	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1877	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1878	* @retval HAL status
<>	144:ef7eb2e8f9f7	1879	*/
<>	144:ef7eb2e8f9f7	1880	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1881	{
<>	144:ef7eb2e8f9f7	1882	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1883	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1884	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1885
<>	144:ef7eb2e8f9f7	1886	switch (Channel)
<>	144:ef7eb2e8f9f7	1887	{
<>	144:ef7eb2e8f9f7	1888	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1889	{
<>	144:ef7eb2e8f9f7	1890	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1891	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1892	}
<>	144:ef7eb2e8f9f7	1893	break;
<>	144:ef7eb2e8f9f7	1894
<>	144:ef7eb2e8f9f7	1895	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1896	{
<>	144:ef7eb2e8f9f7	1897	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1898	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1899	}
<>	144:ef7eb2e8f9f7	1900	break;
<>	144:ef7eb2e8f9f7	1901
<>	144:ef7eb2e8f9f7	1902	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1903	{
<>	144:ef7eb2e8f9f7	1904	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1905	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1906	}
<>	144:ef7eb2e8f9f7	1907	break;
<>	144:ef7eb2e8f9f7	1908
<>	144:ef7eb2e8f9f7	1909	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1910	{
<>	144:ef7eb2e8f9f7	1911	/* Disable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1912	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1913	}
<>	144:ef7eb2e8f9f7	1914	break;
<>	144:ef7eb2e8f9f7	1915
<>	144:ef7eb2e8f9f7	1916	default:
<>	144:ef7eb2e8f9f7	1917	break;
<>	144:ef7eb2e8f9f7	1918	}
<>	144:ef7eb2e8f9f7	1919
<>	144:ef7eb2e8f9f7	1920	/* Disable the Input Capture channel */
<>	144:ef7eb2e8f9f7	1921	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	1922
<>	144:ef7eb2e8f9f7	1923	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1924	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1925
<>	144:ef7eb2e8f9f7	1926	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1927	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1928
<>	144:ef7eb2e8f9f7	1929	/* Return function status */
<>	144:ef7eb2e8f9f7	1930	return HAL_OK;
<>	144:ef7eb2e8f9f7	1931	}
<>	144:ef7eb2e8f9f7	1932	/**
<>	144:ef7eb2e8f9f7	1933	* @}
<>	144:ef7eb2e8f9f7	1934	*/
<>	144:ef7eb2e8f9f7	1935
<>	144:ef7eb2e8f9f7	1936	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
<>	144:ef7eb2e8f9f7	1937	* @brief Time One Pulse functions
<>	144:ef7eb2e8f9f7	1938	*
<>	144:ef7eb2e8f9f7	1939	@verbatim
<>	144:ef7eb2e8f9f7	1940	==============================================================================
<>	144:ef7eb2e8f9f7	1941	##### Time One Pulse functions #####
<>	144:ef7eb2e8f9f7	1942	==============================================================================
<>	144:ef7eb2e8f9f7	1943	[..]
<>	144:ef7eb2e8f9f7	1944	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1945	(+) Initialize and configure the TIM One Pulse.
<>	144:ef7eb2e8f9f7	1946	(+) De-initialize the TIM One Pulse.
<>	144:ef7eb2e8f9f7	1947	(+) Start the Time One Pulse.
<>	144:ef7eb2e8f9f7	1948	(+) Stop the Time One Pulse.
<>	144:ef7eb2e8f9f7	1949	(+) Start the Time One Pulse and enable interrupt.
<>	144:ef7eb2e8f9f7	1950	(+) Stop the Time One Pulse and disable interrupt.
<>	144:ef7eb2e8f9f7	1951	(+) Start the Time One Pulse and enable DMA transfer.
<>	144:ef7eb2e8f9f7	1952	(+) Stop the Time One Pulse and disable DMA transfer.
<>	144:ef7eb2e8f9f7	1953
<>	144:ef7eb2e8f9f7	1954	@endverbatim
<>	144:ef7eb2e8f9f7	1955	* @{
<>	144:ef7eb2e8f9f7	1956	*/
<>	144:ef7eb2e8f9f7	1957	/**
<>	144:ef7eb2e8f9f7	1958	* @brief Initializes the TIM One Pulse Time Base according to the specified
<>	144:ef7eb2e8f9f7	1959	* parameters in the TIM_HandleTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	1960	* @param htim : TIM OnePulse handle
<>	144:ef7eb2e8f9f7	1961	* @param OnePulseMode : Select the One pulse mode.
<>	144:ef7eb2e8f9f7	1962	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1963	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<>	144:ef7eb2e8f9f7	1964	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
<>	144:ef7eb2e8f9f7	1965	* @retval HAL status
<>	144:ef7eb2e8f9f7	1966	*/
<>	144:ef7eb2e8f9f7	1967	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<>	144:ef7eb2e8f9f7	1968	{
<>	144:ef7eb2e8f9f7	1969	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	1970	if(htim == NULL)
<>	144:ef7eb2e8f9f7	1971	{
<>	144:ef7eb2e8f9f7	1972	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1973	}
<>	144:ef7eb2e8f9f7	1974
<>	144:ef7eb2e8f9f7	1975	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1976	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1977	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	1978	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	165:e614a9f1c9e2	1979	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<>	144:ef7eb2e8f9f7	1980	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<>	144:ef7eb2e8f9f7	1981
<>	144:ef7eb2e8f9f7	1982	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1983	{
<>	144:ef7eb2e8f9f7	1984	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	1985	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	1986
<>	144:ef7eb2e8f9f7	1987	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	1988	HAL_TIM_OnePulse_MspInit(htim);
<>	144:ef7eb2e8f9f7	1989	}
<>	144:ef7eb2e8f9f7	1990
<>	144:ef7eb2e8f9f7	1991	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	1992	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1993
<>	144:ef7eb2e8f9f7	1994	/* Configure the Time base in the One Pulse Mode */
<>	144:ef7eb2e8f9f7	1995	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	1996
<>	144:ef7eb2e8f9f7	1997	/* Reset the OPM Bit */
<>	144:ef7eb2e8f9f7	1998	htim->Instance->CR1 &= ~TIM_CR1_OPM;
<>	144:ef7eb2e8f9f7	1999
<>	144:ef7eb2e8f9f7	2000	/* Configure the OPM Mode */
<>	144:ef7eb2e8f9f7	2001	htim->Instance->CR1 \|= OnePulseMode;
<>	144:ef7eb2e8f9f7	2002
<>	144:ef7eb2e8f9f7	2003	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	2004	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2005
<>	144:ef7eb2e8f9f7	2006	return HAL_OK;
<>	144:ef7eb2e8f9f7	2007	}
<>	144:ef7eb2e8f9f7	2008
<>	144:ef7eb2e8f9f7	2009	/**
<>	144:ef7eb2e8f9f7	2010	* @brief DeInitializes the TIM One Pulse
<>	144:ef7eb2e8f9f7	2011	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	2012	* @retval HAL status
<>	144:ef7eb2e8f9f7	2013	*/
<>	144:ef7eb2e8f9f7	2014	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2015	{
<>	144:ef7eb2e8f9f7	2016	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2017	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2018
<>	144:ef7eb2e8f9f7	2019	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2020
<>	144:ef7eb2e8f9f7	2021	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	2022	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2023
<>	144:ef7eb2e8f9f7	2024	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	2025	HAL_TIM_OnePulse_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	2026
<>	144:ef7eb2e8f9f7	2027	/* Change TIM state */
<>	144:ef7eb2e8f9f7	2028	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	2029
<>	144:ef7eb2e8f9f7	2030	/* Release Lock */
<>	144:ef7eb2e8f9f7	2031	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2032
<>	144:ef7eb2e8f9f7	2033	return HAL_OK;
<>	144:ef7eb2e8f9f7	2034	}
<>	144:ef7eb2e8f9f7	2035
<>	144:ef7eb2e8f9f7	2036	/**
<>	144:ef7eb2e8f9f7	2037	* @brief Initializes the TIM One Pulse MSP.
<>	144:ef7eb2e8f9f7	2038	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2039	* @retval None
<>	144:ef7eb2e8f9f7	2040	*/
<>	144:ef7eb2e8f9f7	2041	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2042	{
<>	144:ef7eb2e8f9f7	2043	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2044	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2045	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2046	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2047	*/
<>	144:ef7eb2e8f9f7	2048	}
<>	144:ef7eb2e8f9f7	2049
<>	144:ef7eb2e8f9f7	2050	/**
<>	144:ef7eb2e8f9f7	2051	* @brief DeInitializes TIM One Pulse MSP.
<>	144:ef7eb2e8f9f7	2052	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2053	* @retval None
<>	144:ef7eb2e8f9f7	2054	*/
<>	144:ef7eb2e8f9f7	2055	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2056	{
<>	144:ef7eb2e8f9f7	2057	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2058	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2059	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2060	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2061	*/
<>	144:ef7eb2e8f9f7	2062	}
<>	144:ef7eb2e8f9f7	2063
<>	144:ef7eb2e8f9f7	2064	/**
<>	144:ef7eb2e8f9f7	2065	* @brief Starts the TIM One Pulse signal generation.
<>	144:ef7eb2e8f9f7	2066	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	2067	* @param OutputChannel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2068	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2069	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2070	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2071	* @retval HAL status
<>	144:ef7eb2e8f9f7	2072	*/
<>	144:ef7eb2e8f9f7	2073	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2074	{
AnnaBridge	165:e614a9f1c9e2	2075	/* Prevent unused argument(s) compilation warning */
AnnaBridge	165:e614a9f1c9e2	2076	UNUSED(OutputChannel);
AnnaBridge	165:e614a9f1c9e2	2077
<>	144:ef7eb2e8f9f7	2078	/* Enable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2079	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2080	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2081	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2082	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<>	144:ef7eb2e8f9f7	2083
<>	144:ef7eb2e8f9f7	2084	No need to enable the counter, it's enabled automatically by hardware
<>	144:ef7eb2e8f9f7	2085	(the counter starts in response to a stimulus and generate a pulse */
<>	144:ef7eb2e8f9f7	2086
<>	144:ef7eb2e8f9f7	2087	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2088	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2089
<>	144:ef7eb2e8f9f7	2090	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2091	{
<>	144:ef7eb2e8f9f7	2092	/* Enable the main output */
<>	144:ef7eb2e8f9f7	2093	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2094	}
<>	144:ef7eb2e8f9f7	2095
<>	144:ef7eb2e8f9f7	2096	/* Return function status */
<>	144:ef7eb2e8f9f7	2097	return HAL_OK;
<>	144:ef7eb2e8f9f7	2098	}
<>	144:ef7eb2e8f9f7	2099
<>	144:ef7eb2e8f9f7	2100	/**
<>	144:ef7eb2e8f9f7	2101	* @brief Stops the TIM One Pulse signal generation.
<>	144:ef7eb2e8f9f7	2102	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	2103	* @param OutputChannel : TIM Channels to be disable
<>	144:ef7eb2e8f9f7	2104	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2105	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2106	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2107	* @retval HAL status
<>	144:ef7eb2e8f9f7	2108	*/
<>	144:ef7eb2e8f9f7	2109	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2110	{
AnnaBridge	165:e614a9f1c9e2	2111	/* Prevent unused argument(s) compilation warning */
AnnaBridge	165:e614a9f1c9e2	2112	UNUSED(OutputChannel);
AnnaBridge	165:e614a9f1c9e2	2113
<>	144:ef7eb2e8f9f7	2114	/* Disable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2115	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2116	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2117	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2118	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<>	144:ef7eb2e8f9f7	2119
<>	144:ef7eb2e8f9f7	2120	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2121	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2122
<>	144:ef7eb2e8f9f7	2123	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2124	{
<>	144:ef7eb2e8f9f7	2125	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	2126	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2127	}
<>	144:ef7eb2e8f9f7	2128
<>	144:ef7eb2e8f9f7	2129	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2130	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2131
<>	144:ef7eb2e8f9f7	2132	/* Return function status */
<>	144:ef7eb2e8f9f7	2133	return HAL_OK;
<>	144:ef7eb2e8f9f7	2134	}
<>	144:ef7eb2e8f9f7	2135
<>	144:ef7eb2e8f9f7	2136	/**
<>	144:ef7eb2e8f9f7	2137	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	2138	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	2139	* @param OutputChannel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2140	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2141	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2142	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2143	* @retval HAL status
<>	144:ef7eb2e8f9f7	2144	*/
<>	144:ef7eb2e8f9f7	2145	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2146	{
AnnaBridge	165:e614a9f1c9e2	2147	/* Prevent unused argument(s) compilation warning */
AnnaBridge	165:e614a9f1c9e2	2148	UNUSED(OutputChannel);
AnnaBridge	165:e614a9f1c9e2	2149
<>	144:ef7eb2e8f9f7	2150	/* Enable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2151	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2152	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2153	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2154	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<>	144:ef7eb2e8f9f7	2155
<>	144:ef7eb2e8f9f7	2156	No need to enable the counter, it's enabled automatically by hardware
<>	144:ef7eb2e8f9f7	2157	(the counter starts in response to a stimulus and generate a pulse */
<>	144:ef7eb2e8f9f7	2158
<>	144:ef7eb2e8f9f7	2159	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	2160	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2161
<>	144:ef7eb2e8f9f7	2162	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	2163	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2164
<>	144:ef7eb2e8f9f7	2165	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2166	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2167
<>	144:ef7eb2e8f9f7	2168	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2169	{
<>	144:ef7eb2e8f9f7	2170	/* Enable the main output */
<>	144:ef7eb2e8f9f7	2171	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2172	}
<>	144:ef7eb2e8f9f7	2173
<>	144:ef7eb2e8f9f7	2174	/* Return function status */
<>	144:ef7eb2e8f9f7	2175	return HAL_OK;
<>	144:ef7eb2e8f9f7	2176	}
<>	144:ef7eb2e8f9f7	2177
<>	144:ef7eb2e8f9f7	2178	/**
<>	144:ef7eb2e8f9f7	2179	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
<>	144:ef7eb2e8f9f7	2180	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	2181	* @param OutputChannel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2182	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2183	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2184	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2185	* @retval HAL status
<>	144:ef7eb2e8f9f7	2186	*/
<>	144:ef7eb2e8f9f7	2187	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	2188	{
AnnaBridge	165:e614a9f1c9e2	2189	/* Prevent unused argument(s) compilation warning */
AnnaBridge	165:e614a9f1c9e2	2190	UNUSED(OutputChannel);
AnnaBridge	165:e614a9f1c9e2	2191
<>	144:ef7eb2e8f9f7	2192	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	2193	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2194
<>	144:ef7eb2e8f9f7	2195	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	2196	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2197
<>	144:ef7eb2e8f9f7	2198	/* Disable the Capture compare and the Input Capture channels
<>	144:ef7eb2e8f9f7	2199	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2200	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<>	144:ef7eb2e8f9f7	2201	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<>	144:ef7eb2e8f9f7	2202	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<>	144:ef7eb2e8f9f7	2203	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2204	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2205
<>	144:ef7eb2e8f9f7	2206	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<>	144:ef7eb2e8f9f7	2207	{
<>	144:ef7eb2e8f9f7	2208	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	2209	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2210	}
<>	144:ef7eb2e8f9f7	2211
<>	144:ef7eb2e8f9f7	2212	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2213	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2214
<>	144:ef7eb2e8f9f7	2215	/* Return function status */
<>	144:ef7eb2e8f9f7	2216	return HAL_OK;
<>	144:ef7eb2e8f9f7	2217	}
<>	144:ef7eb2e8f9f7	2218
<>	144:ef7eb2e8f9f7	2219	/**
<>	144:ef7eb2e8f9f7	2220	* @}
<>	144:ef7eb2e8f9f7	2221	*/
<>	144:ef7eb2e8f9f7	2222
<>	144:ef7eb2e8f9f7	2223	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
<>	144:ef7eb2e8f9f7	2224	* @brief Time Encoder functions
<>	144:ef7eb2e8f9f7	2225	*
<>	144:ef7eb2e8f9f7	2226	@verbatim
<>	144:ef7eb2e8f9f7	2227	==============================================================================
<>	144:ef7eb2e8f9f7	2228	##### Time Encoder functions #####
<>	144:ef7eb2e8f9f7	2229	==============================================================================
<>	144:ef7eb2e8f9f7	2230	[..]
<>	144:ef7eb2e8f9f7	2231	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	2232	(+) Initialize and configure the TIM Encoder.
<>	144:ef7eb2e8f9f7	2233	(+) De-initialize the TIM Encoder.
<>	144:ef7eb2e8f9f7	2234	(+) Start the Time Encoder.
<>	144:ef7eb2e8f9f7	2235	(+) Stop the Time Encoder.
<>	144:ef7eb2e8f9f7	2236	(+) Start the Time Encoder and enable interrupt.
<>	144:ef7eb2e8f9f7	2237	(+) Stop the Time Encoder and disable interrupt.
<>	144:ef7eb2e8f9f7	2238	(+) Start the Time Encoder and enable DMA transfer.
<>	144:ef7eb2e8f9f7	2239	(+) Stop the Time Encoder and disable DMA transfer.
<>	144:ef7eb2e8f9f7	2240
<>	144:ef7eb2e8f9f7	2241	@endverbatim
<>	144:ef7eb2e8f9f7	2242	* @{
<>	144:ef7eb2e8f9f7	2243	*/
<>	144:ef7eb2e8f9f7	2244	/**
<>	144:ef7eb2e8f9f7	2245	* @brief Initializes the TIM Encoder Interface and create the associated handle.
<>	144:ef7eb2e8f9f7	2246	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2247	* @param sConfig : TIM Encoder Interface configuration structure
<>	144:ef7eb2e8f9f7	2248	* @retval HAL status
<>	144:ef7eb2e8f9f7	2249	*/
<>	144:ef7eb2e8f9f7	2250	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
<>	144:ef7eb2e8f9f7	2251	{
AnnaBridge	165:e614a9f1c9e2	2252	uint32_t tmpsmcr = 0U;
AnnaBridge	165:e614a9f1c9e2	2253	uint32_t tmpccmr1 = 0U;
AnnaBridge	165:e614a9f1c9e2	2254	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	2255
<>	144:ef7eb2e8f9f7	2256	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	2257	if(htim == NULL)
<>	144:ef7eb2e8f9f7	2258	{
<>	144:ef7eb2e8f9f7	2259	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2260	}
<>	144:ef7eb2e8f9f7	2261
<>	144:ef7eb2e8f9f7	2262	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2263	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
AnnaBridge	165:e614a9f1c9e2	2264	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
AnnaBridge	165:e614a9f1c9e2	2265	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
AnnaBridge	165:e614a9f1c9e2	2266	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<>	144:ef7eb2e8f9f7	2267	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<>	144:ef7eb2e8f9f7	2268	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<>	144:ef7eb2e8f9f7	2269	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<>	144:ef7eb2e8f9f7	2270	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<>	144:ef7eb2e8f9f7	2271	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<>	144:ef7eb2e8f9f7	2272	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<>	144:ef7eb2e8f9f7	2273	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<>	144:ef7eb2e8f9f7	2274	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<>	144:ef7eb2e8f9f7	2275	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<>	144:ef7eb2e8f9f7	2276
<>	144:ef7eb2e8f9f7	2277	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	2278	{
<>	144:ef7eb2e8f9f7	2279	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	2280	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	2281
<>	144:ef7eb2e8f9f7	2282	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	2283	HAL_TIM_Encoder_MspInit(htim);
<>	144:ef7eb2e8f9f7	2284	}
<>	144:ef7eb2e8f9f7	2285
<>	144:ef7eb2e8f9f7	2286	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	2287	htim->State= HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289	/* Reset the SMS bits */
<>	144:ef7eb2e8f9f7	2290	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	2291
<>	144:ef7eb2e8f9f7	2292	/* Configure the Time base in the Encoder Mode */
<>	144:ef7eb2e8f9f7	2293	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	2294
<>	144:ef7eb2e8f9f7	2295	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	2296	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	2297
<>	144:ef7eb2e8f9f7	2298	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	2299	tmpccmr1 = htim->Instance->CCMR1;
<>	144:ef7eb2e8f9f7	2300
<>	144:ef7eb2e8f9f7	2301	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	2302	tmpccer = htim->Instance->CCER;
<>	144:ef7eb2e8f9f7	2303
<>	144:ef7eb2e8f9f7	2304	/* Set the encoder Mode */
<>	144:ef7eb2e8f9f7	2305	tmpsmcr \|= sConfig->EncoderMode;
<>	144:ef7eb2e8f9f7	2306
<>	144:ef7eb2e8f9f7	2307	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
<>	144:ef7eb2e8f9f7	2308	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
AnnaBridge	165:e614a9f1c9e2	2309	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8U));
<>	144:ef7eb2e8f9f7	2310
<>	144:ef7eb2e8f9f7	2311	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<>	144:ef7eb2e8f9f7	2312	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
<>	144:ef7eb2e8f9f7	2313	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
AnnaBridge	165:e614a9f1c9e2	2314	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8U);
AnnaBridge	165:e614a9f1c9e2	2315	tmpccmr1 \|= (sConfig->IC1Filter << 4U) \| (sConfig->IC2Filter << 12U);
<>	144:ef7eb2e8f9f7	2316
<>	144:ef7eb2e8f9f7	2317	/* Set the TI1 and the TI2 Polarities */
<>	144:ef7eb2e8f9f7	2318	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
<>	144:ef7eb2e8f9f7	2319	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
AnnaBridge	165:e614a9f1c9e2	2320	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4U);
<>	144:ef7eb2e8f9f7	2321
<>	144:ef7eb2e8f9f7	2322	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	2323	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	2324
<>	144:ef7eb2e8f9f7	2325	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	2326	htim->Instance->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	2327
<>	144:ef7eb2e8f9f7	2328	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	2329	htim->Instance->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	2330
<>	144:ef7eb2e8f9f7	2331	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	2332	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2333
<>	144:ef7eb2e8f9f7	2334	return HAL_OK;
<>	144:ef7eb2e8f9f7	2335	}
<>	144:ef7eb2e8f9f7	2336
<>	144:ef7eb2e8f9f7	2337
<>	144:ef7eb2e8f9f7	2338	/**
<>	144:ef7eb2e8f9f7	2339	* @brief DeInitializes the TIM Encoder interface
<>	144:ef7eb2e8f9f7	2340	* @param htim : TIM Encoder handle
<>	144:ef7eb2e8f9f7	2341	* @retval HAL status
<>	144:ef7eb2e8f9f7	2342	*/
<>	144:ef7eb2e8f9f7	2343	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2344	{
<>	144:ef7eb2e8f9f7	2345	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2346	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2347
<>	144:ef7eb2e8f9f7	2348	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2349
<>	144:ef7eb2e8f9f7	2350	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	2351	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2352
<>	144:ef7eb2e8f9f7	2353	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	2354	HAL_TIM_Encoder_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	2355
<>	144:ef7eb2e8f9f7	2356	/* Change TIM state */
<>	144:ef7eb2e8f9f7	2357	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	2358
<>	144:ef7eb2e8f9f7	2359	/* Release Lock */
<>	144:ef7eb2e8f9f7	2360	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2361
<>	144:ef7eb2e8f9f7	2362	return HAL_OK;
<>	144:ef7eb2e8f9f7	2363	}
<>	144:ef7eb2e8f9f7	2364
<>	144:ef7eb2e8f9f7	2365	/**
<>	144:ef7eb2e8f9f7	2366	* @brief Initializes the TIM Encoder Interface MSP.
<>	144:ef7eb2e8f9f7	2367	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2368	* @retval None
<>	144:ef7eb2e8f9f7	2369	*/
<>	144:ef7eb2e8f9f7	2370	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2371	{
<>	144:ef7eb2e8f9f7	2372	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2373	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2374	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2375	the HAL_TIM_Encoder_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2376	*/
<>	144:ef7eb2e8f9f7	2377	}
<>	144:ef7eb2e8f9f7	2378
<>	144:ef7eb2e8f9f7	2379	/**
<>	144:ef7eb2e8f9f7	2380	* @brief DeInitializes TIM Encoder Interface MSP.
<>	144:ef7eb2e8f9f7	2381	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2382	* @retval None
<>	144:ef7eb2e8f9f7	2383	*/
<>	144:ef7eb2e8f9f7	2384	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2385	{
<>	144:ef7eb2e8f9f7	2386	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2387	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2388	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2389	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	2390	*/
<>	144:ef7eb2e8f9f7	2391	}
<>	144:ef7eb2e8f9f7	2392
<>	144:ef7eb2e8f9f7	2393	/**
<>	144:ef7eb2e8f9f7	2394	* @brief Starts the TIM Encoder Interface.
<>	144:ef7eb2e8f9f7	2395	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2396	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2397	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2398	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2399	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2400	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2401	* @retval HAL status
<>	144:ef7eb2e8f9f7	2402	*/
<>	144:ef7eb2e8f9f7	2403	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2404	{
<>	144:ef7eb2e8f9f7	2405	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2406	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2407
<>	144:ef7eb2e8f9f7	2408	/* Enable the encoder interface channels */
<>	144:ef7eb2e8f9f7	2409	switch (Channel)
<>	144:ef7eb2e8f9f7	2410	{
<>	144:ef7eb2e8f9f7	2411	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2412	{
<>	144:ef7eb2e8f9f7	2413	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2414	break;
<>	144:ef7eb2e8f9f7	2415	}
<>	144:ef7eb2e8f9f7	2416	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2417	{
<>	144:ef7eb2e8f9f7	2418	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2419	break;
<>	144:ef7eb2e8f9f7	2420	}
<>	144:ef7eb2e8f9f7	2421	default :
<>	144:ef7eb2e8f9f7	2422	{
<>	144:ef7eb2e8f9f7	2423	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2424	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2425	break;
<>	144:ef7eb2e8f9f7	2426	}
<>	144:ef7eb2e8f9f7	2427	}
<>	144:ef7eb2e8f9f7	2428	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2429	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2430
<>	144:ef7eb2e8f9f7	2431	/* Return function status */
<>	144:ef7eb2e8f9f7	2432	return HAL_OK;
<>	144:ef7eb2e8f9f7	2433	}
<>	144:ef7eb2e8f9f7	2434
<>	144:ef7eb2e8f9f7	2435	/**
<>	144:ef7eb2e8f9f7	2436	* @brief Stops the TIM Encoder Interface.
<>	144:ef7eb2e8f9f7	2437	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2438	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	2439	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2440	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2441	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2442	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2443	* @retval HAL status
<>	144:ef7eb2e8f9f7	2444	*/
<>	144:ef7eb2e8f9f7	2445	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2446	{
<>	144:ef7eb2e8f9f7	2447	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2448	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2449
<>	144:ef7eb2e8f9f7	2450	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2451	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2452	switch (Channel)
<>	144:ef7eb2e8f9f7	2453	{
<>	144:ef7eb2e8f9f7	2454	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2455	{
<>	144:ef7eb2e8f9f7	2456	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2457	break;
<>	144:ef7eb2e8f9f7	2458	}
<>	144:ef7eb2e8f9f7	2459	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2460	{
<>	144:ef7eb2e8f9f7	2461	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2462	break;
<>	144:ef7eb2e8f9f7	2463	}
<>	144:ef7eb2e8f9f7	2464	default :
<>	144:ef7eb2e8f9f7	2465	{
<>	144:ef7eb2e8f9f7	2466	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2467	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2468	break;
<>	144:ef7eb2e8f9f7	2469	}
<>	144:ef7eb2e8f9f7	2470	}
<>	144:ef7eb2e8f9f7	2471
<>	144:ef7eb2e8f9f7	2472	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2473	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2474
<>	144:ef7eb2e8f9f7	2475	/* Return function status */
<>	144:ef7eb2e8f9f7	2476	return HAL_OK;
<>	144:ef7eb2e8f9f7	2477	}
<>	144:ef7eb2e8f9f7	2478
<>	144:ef7eb2e8f9f7	2479	/**
<>	144:ef7eb2e8f9f7	2480	* @brief Starts the TIM Encoder Interface in interrupt mode.
<>	144:ef7eb2e8f9f7	2481	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2482	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2483	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2484	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2485	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2486	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2487	* @retval HAL status
<>	144:ef7eb2e8f9f7	2488	*/
<>	144:ef7eb2e8f9f7	2489	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2490	{
<>	144:ef7eb2e8f9f7	2491	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2492	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2493
<>	144:ef7eb2e8f9f7	2494	/* Enable the encoder interface channels */
<>	144:ef7eb2e8f9f7	2495	/* Enable the capture compare Interrupts 1 and/or 2 */
<>	144:ef7eb2e8f9f7	2496	switch (Channel)
<>	144:ef7eb2e8f9f7	2497	{
<>	144:ef7eb2e8f9f7	2498	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2499	{
<>	144:ef7eb2e8f9f7	2500	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2501	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2502	break;
<>	144:ef7eb2e8f9f7	2503	}
<>	144:ef7eb2e8f9f7	2504	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2505	{
<>	144:ef7eb2e8f9f7	2506	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2507	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2508	break;
<>	144:ef7eb2e8f9f7	2509	}
<>	144:ef7eb2e8f9f7	2510	default :
<>	144:ef7eb2e8f9f7	2511	{
<>	144:ef7eb2e8f9f7	2512	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2513	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2514	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2515	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2516	break;
<>	144:ef7eb2e8f9f7	2517	}
<>	144:ef7eb2e8f9f7	2518	}
<>	144:ef7eb2e8f9f7	2519
<>	144:ef7eb2e8f9f7	2520	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2521	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2522
<>	144:ef7eb2e8f9f7	2523	/* Return function status */
<>	144:ef7eb2e8f9f7	2524	return HAL_OK;
<>	144:ef7eb2e8f9f7	2525	}
<>	144:ef7eb2e8f9f7	2526
<>	144:ef7eb2e8f9f7	2527	/**
<>	144:ef7eb2e8f9f7	2528	* @brief Stops the TIM Encoder Interface in interrupt mode.
<>	144:ef7eb2e8f9f7	2529	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2530	* @param Channel : TIM Channels to be disabled
<>	144:ef7eb2e8f9f7	2531	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2532	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2533	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2534	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2535	* @retval HAL status
<>	144:ef7eb2e8f9f7	2536	*/
<>	144:ef7eb2e8f9f7	2537	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2538	{
<>	144:ef7eb2e8f9f7	2539	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2540	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2541
<>	144:ef7eb2e8f9f7	2542	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2543	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2544	if(Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	2545	{
<>	144:ef7eb2e8f9f7	2546	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2547
<>	144:ef7eb2e8f9f7	2548	/* Disable the capture compare Interrupts 1 */
<>	144:ef7eb2e8f9f7	2549	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2550	}
<>	144:ef7eb2e8f9f7	2551	else if(Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2552	{
<>	144:ef7eb2e8f9f7	2553	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2554
<>	144:ef7eb2e8f9f7	2555	/* Disable the capture compare Interrupts 2 */
<>	144:ef7eb2e8f9f7	2556	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2557	}
<>	144:ef7eb2e8f9f7	2558	else
<>	144:ef7eb2e8f9f7	2559	{
<>	144:ef7eb2e8f9f7	2560	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2561	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2562
<>	144:ef7eb2e8f9f7	2563	/* Disable the capture compare Interrupts 1 and 2 */
<>	144:ef7eb2e8f9f7	2564	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2565	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2566	}
<>	144:ef7eb2e8f9f7	2567
<>	144:ef7eb2e8f9f7	2568	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2569	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2570
<>	144:ef7eb2e8f9f7	2571	/* Change the htim state */
<>	144:ef7eb2e8f9f7	2572	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2573
<>	144:ef7eb2e8f9f7	2574	/* Return function status */
<>	144:ef7eb2e8f9f7	2575	return HAL_OK;
<>	144:ef7eb2e8f9f7	2576	}
<>	144:ef7eb2e8f9f7	2577
<>	144:ef7eb2e8f9f7	2578	/**
<>	144:ef7eb2e8f9f7	2579	* @brief Starts the TIM Encoder Interface in DMA mode.
<>	144:ef7eb2e8f9f7	2580	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2581	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2582	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2583	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2584	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2585	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2586	* @param pData1 : The destination Buffer address for IC1.
<>	144:ef7eb2e8f9f7	2587	* @param pData2 : The destination Buffer address for IC2.
<>	144:ef7eb2e8f9f7	2588	* @param Length : The length of data to be transferred from TIM peripheral to memory.
<>	144:ef7eb2e8f9f7	2589	* @retval HAL status
<>	144:ef7eb2e8f9f7	2590	*/
<>	144:ef7eb2e8f9f7	2591	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
<>	144:ef7eb2e8f9f7	2592	{
<>	144:ef7eb2e8f9f7	2593	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2594	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2595
<>	144:ef7eb2e8f9f7	2596	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	2597	{
<>	144:ef7eb2e8f9f7	2598	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2599	}
<>	144:ef7eb2e8f9f7	2600	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	2601	{
AnnaBridge	165:e614a9f1c9e2	2602	if((((pData1 == 0U) \|\| (pData2 == 0U) )) && (Length > 0U))
<>	144:ef7eb2e8f9f7	2603	{
<>	144:ef7eb2e8f9f7	2604	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2605	}
<>	144:ef7eb2e8f9f7	2606	else
<>	144:ef7eb2e8f9f7	2607	{
<>	144:ef7eb2e8f9f7	2608	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2609	}
<>	144:ef7eb2e8f9f7	2610	}
<>	144:ef7eb2e8f9f7	2611
<>	144:ef7eb2e8f9f7	2612	switch (Channel)
<>	144:ef7eb2e8f9f7	2613	{
<>	144:ef7eb2e8f9f7	2614	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2615	{
<>	144:ef7eb2e8f9f7	2616	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2617	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2618
<>	144:ef7eb2e8f9f7	2619	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2620	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2621
<>	144:ef7eb2e8f9f7	2622	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2623	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<>	144:ef7eb2e8f9f7	2624
<>	144:ef7eb2e8f9f7	2625	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2626	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2627
<>	144:ef7eb2e8f9f7	2628	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2629	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2630
<>	144:ef7eb2e8f9f7	2631	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2632	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2633	}
<>	144:ef7eb2e8f9f7	2634	break;
<>	144:ef7eb2e8f9f7	2635
<>	144:ef7eb2e8f9f7	2636	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2637	{
<>	144:ef7eb2e8f9f7	2638	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2639	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2640
<>	144:ef7eb2e8f9f7	2641	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2642	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
<>	144:ef7eb2e8f9f7	2643	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2644	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<>	144:ef7eb2e8f9f7	2645
<>	144:ef7eb2e8f9f7	2646	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2647	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2648
<>	144:ef7eb2e8f9f7	2649	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2650	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2651
<>	144:ef7eb2e8f9f7	2652	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2653	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2654	}
<>	144:ef7eb2e8f9f7	2655	break;
<>	144:ef7eb2e8f9f7	2656
<>	144:ef7eb2e8f9f7	2657	case TIM_CHANNEL_ALL:
<>	144:ef7eb2e8f9f7	2658	{
<>	144:ef7eb2e8f9f7	2659	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2660	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2661
<>	144:ef7eb2e8f9f7	2662	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2663	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2664
<>	144:ef7eb2e8f9f7	2665	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2666	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<>	144:ef7eb2e8f9f7	2667
<>	144:ef7eb2e8f9f7	2668	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	2669	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	2670
<>	144:ef7eb2e8f9f7	2671	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2672	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	2673
<>	144:ef7eb2e8f9f7	2674	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	2675	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<>	144:ef7eb2e8f9f7	2676
<>	144:ef7eb2e8f9f7	2677	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2678	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	2679
<>	144:ef7eb2e8f9f7	2680	/* Enable the Capture compare channel */
<>	144:ef7eb2e8f9f7	2681	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2682	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	2683
<>	144:ef7eb2e8f9f7	2684	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2685	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2686	/* Enable the TIM Input Capture DMA request */
<>	144:ef7eb2e8f9f7	2687	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2688	}
<>	144:ef7eb2e8f9f7	2689	break;
<>	144:ef7eb2e8f9f7	2690
<>	144:ef7eb2e8f9f7	2691	default:
<>	144:ef7eb2e8f9f7	2692	break;
<>	144:ef7eb2e8f9f7	2693	}
<>	144:ef7eb2e8f9f7	2694	/* Return function status */
<>	144:ef7eb2e8f9f7	2695	return HAL_OK;
<>	144:ef7eb2e8f9f7	2696	}
<>	144:ef7eb2e8f9f7	2697
<>	144:ef7eb2e8f9f7	2698	/**
<>	144:ef7eb2e8f9f7	2699	* @brief Stops the TIM Encoder Interface in DMA mode.
<>	144:ef7eb2e8f9f7	2700	* @param htim : TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	2701	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2702	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2703	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2704	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2705	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<>	144:ef7eb2e8f9f7	2706	* @retval HAL status
<>	144:ef7eb2e8f9f7	2707	*/
<>	144:ef7eb2e8f9f7	2708	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2709	{
<>	144:ef7eb2e8f9f7	2710	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2711	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2712
<>	144:ef7eb2e8f9f7	2713	/* Disable the Input Capture channels 1 and 2
<>	144:ef7eb2e8f9f7	2714	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<>	144:ef7eb2e8f9f7	2715	if(Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	2716	{
<>	144:ef7eb2e8f9f7	2717	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2718
<>	144:ef7eb2e8f9f7	2719	/* Disable the capture compare DMA Request 1 */
<>	144:ef7eb2e8f9f7	2720	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2721	}
<>	144:ef7eb2e8f9f7	2722	else if(Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	2723	{
<>	144:ef7eb2e8f9f7	2724	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2725
<>	144:ef7eb2e8f9f7	2726	/* Disable the capture compare DMA Request 2 */
<>	144:ef7eb2e8f9f7	2727	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2728	}
<>	144:ef7eb2e8f9f7	2729	else
<>	144:ef7eb2e8f9f7	2730	{
<>	144:ef7eb2e8f9f7	2731	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2732	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	2733
<>	144:ef7eb2e8f9f7	2734	/* Disable the capture compare DMA Request 1 and 2 */
<>	144:ef7eb2e8f9f7	2735	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	2736	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	2737	}
<>	144:ef7eb2e8f9f7	2738
<>	144:ef7eb2e8f9f7	2739	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2740	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	2741
<>	144:ef7eb2e8f9f7	2742	/* Change the htim state */
<>	144:ef7eb2e8f9f7	2743	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2744
<>	144:ef7eb2e8f9f7	2745	/* Return function status */
<>	144:ef7eb2e8f9f7	2746	return HAL_OK;
<>	144:ef7eb2e8f9f7	2747	}
<>	144:ef7eb2e8f9f7	2748
<>	144:ef7eb2e8f9f7	2749	/**
<>	144:ef7eb2e8f9f7	2750	* @}
<>	144:ef7eb2e8f9f7	2751	*/
<>	144:ef7eb2e8f9f7	2752	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
<>	144:ef7eb2e8f9f7	2753	* @brief IRQ handler management
<>	144:ef7eb2e8f9f7	2754	*
<>	144:ef7eb2e8f9f7	2755	@verbatim
<>	144:ef7eb2e8f9f7	2756	==============================================================================
<>	144:ef7eb2e8f9f7	2757	##### IRQ handler management #####
<>	144:ef7eb2e8f9f7	2758	==============================================================================
<>	144:ef7eb2e8f9f7	2759	[..]
<>	144:ef7eb2e8f9f7	2760	This section provides Timer IRQ handler function.
<>	144:ef7eb2e8f9f7	2761
<>	144:ef7eb2e8f9f7	2762	@endverbatim
<>	144:ef7eb2e8f9f7	2763	* @{
<>	144:ef7eb2e8f9f7	2764	*/
<>	144:ef7eb2e8f9f7	2765	/**
<>	144:ef7eb2e8f9f7	2766	* @brief This function handles TIM interrupts requests.
<>	144:ef7eb2e8f9f7	2767	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	2768	* @retval None
<>	144:ef7eb2e8f9f7	2769	*/
<>	144:ef7eb2e8f9f7	2770	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2771	{
<>	144:ef7eb2e8f9f7	2772	/* Capture compare 1 event */
<>	144:ef7eb2e8f9f7	2773	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<>	144:ef7eb2e8f9f7	2774	{
<>	144:ef7eb2e8f9f7	2775	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<>	144:ef7eb2e8f9f7	2776	{
<>	144:ef7eb2e8f9f7	2777	{
<>	144:ef7eb2e8f9f7	2778	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	2779	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	2780
<>	144:ef7eb2e8f9f7	2781	/* Input capture event */
AnnaBridge	165:e614a9f1c9e2	2782	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
<>	144:ef7eb2e8f9f7	2783	{
<>	144:ef7eb2e8f9f7	2784	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2785	}
<>	144:ef7eb2e8f9f7	2786	/* Output compare event */
<>	144:ef7eb2e8f9f7	2787	else
<>	144:ef7eb2e8f9f7	2788	{
<>	144:ef7eb2e8f9f7	2789	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2790	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2791	}
<>	144:ef7eb2e8f9f7	2792	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2793	}
<>	144:ef7eb2e8f9f7	2794	}
<>	144:ef7eb2e8f9f7	2795	}
<>	144:ef7eb2e8f9f7	2796	/* Capture compare 2 event */
<>	144:ef7eb2e8f9f7	2797	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<>	144:ef7eb2e8f9f7	2798	{
<>	144:ef7eb2e8f9f7	2799	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<>	144:ef7eb2e8f9f7	2800	{
<>	144:ef7eb2e8f9f7	2801	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	2802	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	2803	/* Input capture event */
AnnaBridge	165:e614a9f1c9e2	2804	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
<>	144:ef7eb2e8f9f7	2805	{
<>	144:ef7eb2e8f9f7	2806	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2807	}
<>	144:ef7eb2e8f9f7	2808	/* Output compare event */
<>	144:ef7eb2e8f9f7	2809	else
<>	144:ef7eb2e8f9f7	2810	{
<>	144:ef7eb2e8f9f7	2811	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2812	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2813	}
<>	144:ef7eb2e8f9f7	2814	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2815	}
<>	144:ef7eb2e8f9f7	2816	}
<>	144:ef7eb2e8f9f7	2817	/* Capture compare 3 event */
<>	144:ef7eb2e8f9f7	2818	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<>	144:ef7eb2e8f9f7	2819	{
<>	144:ef7eb2e8f9f7	2820	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<>	144:ef7eb2e8f9f7	2821	{
<>	144:ef7eb2e8f9f7	2822	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	2823	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	2824	/* Input capture event */
AnnaBridge	165:e614a9f1c9e2	2825	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
<>	144:ef7eb2e8f9f7	2826	{
<>	144:ef7eb2e8f9f7	2827	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2828	}
<>	144:ef7eb2e8f9f7	2829	/* Output compare event */
<>	144:ef7eb2e8f9f7	2830	else
<>	144:ef7eb2e8f9f7	2831	{
<>	144:ef7eb2e8f9f7	2832	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2833	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2834	}
<>	144:ef7eb2e8f9f7	2835	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2836	}
<>	144:ef7eb2e8f9f7	2837	}
<>	144:ef7eb2e8f9f7	2838	/* Capture compare 4 event */
<>	144:ef7eb2e8f9f7	2839	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<>	144:ef7eb2e8f9f7	2840	{
<>	144:ef7eb2e8f9f7	2841	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<>	144:ef7eb2e8f9f7	2842	{
<>	144:ef7eb2e8f9f7	2843	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	2844	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	2845	/* Input capture event */
AnnaBridge	165:e614a9f1c9e2	2846	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
<>	144:ef7eb2e8f9f7	2847	{
<>	144:ef7eb2e8f9f7	2848	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	2849	}
<>	144:ef7eb2e8f9f7	2850	/* Output compare event */
<>	144:ef7eb2e8f9f7	2851	else
<>	144:ef7eb2e8f9f7	2852	{
<>	144:ef7eb2e8f9f7	2853	HAL_TIM_OC_DelayElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2854	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	2855	}
<>	144:ef7eb2e8f9f7	2856	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	2857	}
<>	144:ef7eb2e8f9f7	2858	}
<>	144:ef7eb2e8f9f7	2859	/* TIM Update event */
<>	144:ef7eb2e8f9f7	2860	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<>	144:ef7eb2e8f9f7	2861	{
<>	144:ef7eb2e8f9f7	2862	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<>	144:ef7eb2e8f9f7	2863	{
<>	144:ef7eb2e8f9f7	2864	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<>	144:ef7eb2e8f9f7	2865	HAL_TIM_PeriodElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	2866	}
<>	144:ef7eb2e8f9f7	2867	}
<>	144:ef7eb2e8f9f7	2868	/* TIM Break input event */
<>	144:ef7eb2e8f9f7	2869	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
<>	144:ef7eb2e8f9f7	2870	{
<>	144:ef7eb2e8f9f7	2871	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
<>	144:ef7eb2e8f9f7	2872	{
<>	144:ef7eb2e8f9f7	2873	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
<>	144:ef7eb2e8f9f7	2874	HAL_TIMEx_BreakCallback(htim);
<>	144:ef7eb2e8f9f7	2875	}
<>	144:ef7eb2e8f9f7	2876	}
<>	144:ef7eb2e8f9f7	2877	/* TIM Trigger detection event */
<>	144:ef7eb2e8f9f7	2878	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<>	144:ef7eb2e8f9f7	2879	{
<>	144:ef7eb2e8f9f7	2880	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<>	144:ef7eb2e8f9f7	2881	{
<>	144:ef7eb2e8f9f7	2882	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	2883	HAL_TIM_TriggerCallback(htim);
<>	144:ef7eb2e8f9f7	2884	}
<>	144:ef7eb2e8f9f7	2885	}
<>	144:ef7eb2e8f9f7	2886	/* TIM commutation event */
<>	144:ef7eb2e8f9f7	2887	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
<>	144:ef7eb2e8f9f7	2888	{
<>	144:ef7eb2e8f9f7	2889	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
<>	144:ef7eb2e8f9f7	2890	{
<>	144:ef7eb2e8f9f7	2891	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
<>	144:ef7eb2e8f9f7	2892	HAL_TIMEx_CommutationCallback(htim);
<>	144:ef7eb2e8f9f7	2893	}
<>	144:ef7eb2e8f9f7	2894	}
<>	144:ef7eb2e8f9f7	2895	}
<>	144:ef7eb2e8f9f7	2896
<>	144:ef7eb2e8f9f7	2897	/**
<>	144:ef7eb2e8f9f7	2898	* @}
<>	144:ef7eb2e8f9f7	2899	*/
<>	144:ef7eb2e8f9f7	2900
<>	144:ef7eb2e8f9f7	2901	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<>	144:ef7eb2e8f9f7	2902	* @brief Peripheral Control functions
<>	144:ef7eb2e8f9f7	2903	*
<>	144:ef7eb2e8f9f7	2904	@verbatim
<>	144:ef7eb2e8f9f7	2905	==============================================================================
<>	144:ef7eb2e8f9f7	2906	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	2907	==============================================================================
<>	144:ef7eb2e8f9f7	2908	[..]
<>	144:ef7eb2e8f9f7	2909	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	2910	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<>	144:ef7eb2e8f9f7	2911	(+) Configure External Clock source.
<>	144:ef7eb2e8f9f7	2912	(+) Configure Complementary channels, break features and dead time.
<>	144:ef7eb2e8f9f7	2913	(+) Configure Master and the Slave synchronization.
<>	144:ef7eb2e8f9f7	2914	(+) Configure the DMA Burst Mode.
<>	144:ef7eb2e8f9f7	2915
<>	144:ef7eb2e8f9f7	2916	@endverbatim
<>	144:ef7eb2e8f9f7	2917	* @{
<>	144:ef7eb2e8f9f7	2918	*/
<>	144:ef7eb2e8f9f7	2919
<>	144:ef7eb2e8f9f7	2920	/**
<>	144:ef7eb2e8f9f7	2921	* @brief Initializes the TIM Output Compare Channels according to the specified
<>	144:ef7eb2e8f9f7	2922	* parameters in the TIM_OC_InitTypeDef.
<>	144:ef7eb2e8f9f7	2923	* @param htim : TIM Output Compare handle
<>	144:ef7eb2e8f9f7	2924	* @param sConfig : TIM Output Compare configuration structure
<>	144:ef7eb2e8f9f7	2925	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2926	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2927	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2928	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2929	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	2930	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	2931	* @retval HAL status
<>	144:ef7eb2e8f9f7	2932	*/
<>	144:ef7eb2e8f9f7	2933	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	2934	{
<>	144:ef7eb2e8f9f7	2935	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2936	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	2937	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<>	144:ef7eb2e8f9f7	2938	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	144:ef7eb2e8f9f7	2939
<>	144:ef7eb2e8f9f7	2940	/* Check input state */
<>	144:ef7eb2e8f9f7	2941	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2942
<>	144:ef7eb2e8f9f7	2943	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2944
<>	144:ef7eb2e8f9f7	2945	switch (Channel)
<>	144:ef7eb2e8f9f7	2946	{
<>	144:ef7eb2e8f9f7	2947	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2948	{
<>	144:ef7eb2e8f9f7	2949	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2950	/* Configure the TIM Channel 1 in Output Compare */
<>	144:ef7eb2e8f9f7	2951	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2952	}
<>	144:ef7eb2e8f9f7	2953	break;
<>	144:ef7eb2e8f9f7	2954
<>	144:ef7eb2e8f9f7	2955	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2956	{
<>	144:ef7eb2e8f9f7	2957	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2958	/* Configure the TIM Channel 2 in Output Compare */
<>	144:ef7eb2e8f9f7	2959	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2960	}
<>	144:ef7eb2e8f9f7	2961	break;
<>	144:ef7eb2e8f9f7	2962
<>	144:ef7eb2e8f9f7	2963	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	2964	{
<>	144:ef7eb2e8f9f7	2965	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2966	/* Configure the TIM Channel 3 in Output Compare */
<>	144:ef7eb2e8f9f7	2967	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2968	}
<>	144:ef7eb2e8f9f7	2969	break;
<>	144:ef7eb2e8f9f7	2970
<>	144:ef7eb2e8f9f7	2971	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	2972	{
<>	144:ef7eb2e8f9f7	2973	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2974	/* Configure the TIM Channel 4 in Output Compare */
<>	144:ef7eb2e8f9f7	2975	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	2976	}
<>	144:ef7eb2e8f9f7	2977	break;
<>	144:ef7eb2e8f9f7	2978
<>	144:ef7eb2e8f9f7	2979	default:
<>	144:ef7eb2e8f9f7	2980	break;
<>	144:ef7eb2e8f9f7	2981	}
<>	144:ef7eb2e8f9f7	2982	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2983
<>	144:ef7eb2e8f9f7	2984	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2985
<>	144:ef7eb2e8f9f7	2986	return HAL_OK;
<>	144:ef7eb2e8f9f7	2987	}
<>	144:ef7eb2e8f9f7	2988
<>	144:ef7eb2e8f9f7	2989	/**
<>	144:ef7eb2e8f9f7	2990	* @brief Initializes the TIM Input Capture Channels according to the specified
<>	144:ef7eb2e8f9f7	2991	* parameters in the TIM_IC_InitTypeDef.
<>	144:ef7eb2e8f9f7	2992	* @param htim : TIM IC handle
<>	144:ef7eb2e8f9f7	2993	* @param sConfig : TIM Input Capture configuration structure
<>	144:ef7eb2e8f9f7	2994	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	2995	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2996	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	2997	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	2998	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	2999	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	3000	* @retval HAL status
<>	144:ef7eb2e8f9f7	3001	*/
<>	144:ef7eb2e8f9f7	3002	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3003	{
<>	144:ef7eb2e8f9f7	3004	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3005	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3006	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<>	144:ef7eb2e8f9f7	3007	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<>	144:ef7eb2e8f9f7	3008	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<>	144:ef7eb2e8f9f7	3009	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<>	144:ef7eb2e8f9f7	3010
<>	144:ef7eb2e8f9f7	3011	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3012
<>	144:ef7eb2e8f9f7	3013	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3014
<>	144:ef7eb2e8f9f7	3015	if (Channel == TIM_CHANNEL_1)
<>	144:ef7eb2e8f9f7	3016	{
<>	144:ef7eb2e8f9f7	3017	/* TI1 Configuration */
<>	144:ef7eb2e8f9f7	3018	TIM_TI1_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3019	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3020	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3021	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3022
<>	144:ef7eb2e8f9f7	3023	/* Reset the IC1PSC Bits */
<>	144:ef7eb2e8f9f7	3024	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	144:ef7eb2e8f9f7	3025
<>	144:ef7eb2e8f9f7	3026	/* Set the IC1PSC value */
<>	144:ef7eb2e8f9f7	3027	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
<>	144:ef7eb2e8f9f7	3028	}
<>	144:ef7eb2e8f9f7	3029	else if (Channel == TIM_CHANNEL_2)
<>	144:ef7eb2e8f9f7	3030	{
<>	144:ef7eb2e8f9f7	3031	/* TI2 Configuration */
<>	144:ef7eb2e8f9f7	3032	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3033
<>	144:ef7eb2e8f9f7	3034	TIM_TI2_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3035	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3036	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3037	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3038
<>	144:ef7eb2e8f9f7	3039	/* Reset the IC2PSC Bits */
<>	144:ef7eb2e8f9f7	3040	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<>	144:ef7eb2e8f9f7	3041
<>	144:ef7eb2e8f9f7	3042	/* Set the IC2PSC value */
AnnaBridge	165:e614a9f1c9e2	3043	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8U);
<>	144:ef7eb2e8f9f7	3044	}
<>	144:ef7eb2e8f9f7	3045	else if (Channel == TIM_CHANNEL_3)
<>	144:ef7eb2e8f9f7	3046	{
<>	144:ef7eb2e8f9f7	3047	/* TI3 Configuration */
<>	144:ef7eb2e8f9f7	3048	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3049
<>	144:ef7eb2e8f9f7	3050	TIM_TI3_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3051	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3052	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3053	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3054
<>	144:ef7eb2e8f9f7	3055	/* Reset the IC3PSC Bits */
<>	144:ef7eb2e8f9f7	3056	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<>	144:ef7eb2e8f9f7	3057
<>	144:ef7eb2e8f9f7	3058	/* Set the IC3PSC value */
<>	144:ef7eb2e8f9f7	3059	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
<>	144:ef7eb2e8f9f7	3060	}
<>	144:ef7eb2e8f9f7	3061	else
<>	144:ef7eb2e8f9f7	3062	{
<>	144:ef7eb2e8f9f7	3063	/* TI4 Configuration */
<>	144:ef7eb2e8f9f7	3064	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3065
<>	144:ef7eb2e8f9f7	3066	TIM_TI4_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3067	sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3068	sConfig->ICSelection,
<>	144:ef7eb2e8f9f7	3069	sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3070
<>	144:ef7eb2e8f9f7	3071	/* Reset the IC4PSC Bits */
<>	144:ef7eb2e8f9f7	3072	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<>	144:ef7eb2e8f9f7	3073
<>	144:ef7eb2e8f9f7	3074	/* Set the IC4PSC value */
AnnaBridge	165:e614a9f1c9e2	3075	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8U);
<>	144:ef7eb2e8f9f7	3076	}
<>	144:ef7eb2e8f9f7	3077
<>	144:ef7eb2e8f9f7	3078	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3079
<>	144:ef7eb2e8f9f7	3080	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3081
<>	144:ef7eb2e8f9f7	3082	return HAL_OK;
<>	144:ef7eb2e8f9f7	3083	}
<>	144:ef7eb2e8f9f7	3084
<>	144:ef7eb2e8f9f7	3085	/**
<>	144:ef7eb2e8f9f7	3086	* @brief Initializes the TIM PWM channels according to the specified
<>	144:ef7eb2e8f9f7	3087	* parameters in the TIM_OC_InitTypeDef.
<>	144:ef7eb2e8f9f7	3088	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3089	* @param sConfig : TIM PWM configuration structure
<>	144:ef7eb2e8f9f7	3090	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	3091	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3092	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3093	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3094	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	3095	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	3096	* @retval HAL status
<>	144:ef7eb2e8f9f7	3097	*/
<>	144:ef7eb2e8f9f7	3098	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3099	{
<>	144:ef7eb2e8f9f7	3100	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3101
<>	144:ef7eb2e8f9f7	3102	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3103	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	3104	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<>	144:ef7eb2e8f9f7	3105	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	144:ef7eb2e8f9f7	3106	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<>	144:ef7eb2e8f9f7	3107
<>	144:ef7eb2e8f9f7	3108	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3109
<>	144:ef7eb2e8f9f7	3110	switch (Channel)
<>	144:ef7eb2e8f9f7	3111	{
<>	144:ef7eb2e8f9f7	3112	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3113	{
<>	144:ef7eb2e8f9f7	3114	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3115	/* Configure the Channel 1 in PWM mode */
<>	144:ef7eb2e8f9f7	3116	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3117
<>	144:ef7eb2e8f9f7	3118	/* Set the Preload enable bit for channel1 */
<>	144:ef7eb2e8f9f7	3119	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
<>	144:ef7eb2e8f9f7	3120
<>	144:ef7eb2e8f9f7	3121	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3122	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<>	144:ef7eb2e8f9f7	3123	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	3124	}
<>	144:ef7eb2e8f9f7	3125	break;
<>	144:ef7eb2e8f9f7	3126
<>	144:ef7eb2e8f9f7	3127	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3128	{
<>	144:ef7eb2e8f9f7	3129	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3130	/* Configure the Channel 2 in PWM mode */
<>	144:ef7eb2e8f9f7	3131	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3132
<>	144:ef7eb2e8f9f7	3133	/* Set the Preload enable bit for channel2 */
<>	144:ef7eb2e8f9f7	3134	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
<>	144:ef7eb2e8f9f7	3135
<>	144:ef7eb2e8f9f7	3136	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3137	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<>	144:ef7eb2e8f9f7	3138	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
<>	144:ef7eb2e8f9f7	3139	}
<>	144:ef7eb2e8f9f7	3140	break;
<>	144:ef7eb2e8f9f7	3141
<>	144:ef7eb2e8f9f7	3142	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	3143	{
<>	144:ef7eb2e8f9f7	3144	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3145	/* Configure the Channel 3 in PWM mode */
<>	144:ef7eb2e8f9f7	3146	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3147
<>	144:ef7eb2e8f9f7	3148	/* Set the Preload enable bit for channel3 */
<>	144:ef7eb2e8f9f7	3149	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
<>	144:ef7eb2e8f9f7	3150
<>	144:ef7eb2e8f9f7	3151	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3152	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<>	144:ef7eb2e8f9f7	3153	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	3154	}
<>	144:ef7eb2e8f9f7	3155	break;
<>	144:ef7eb2e8f9f7	3156
<>	144:ef7eb2e8f9f7	3157	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	3158	{
<>	144:ef7eb2e8f9f7	3159	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3160	/* Configure the Channel 4 in PWM mode */
<>	144:ef7eb2e8f9f7	3161	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	3162
<>	144:ef7eb2e8f9f7	3163	/* Set the Preload enable bit for channel4 */
<>	144:ef7eb2e8f9f7	3164	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
<>	144:ef7eb2e8f9f7	3165
<>	144:ef7eb2e8f9f7	3166	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	3167	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<>	144:ef7eb2e8f9f7	3168	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
<>	144:ef7eb2e8f9f7	3169	}
<>	144:ef7eb2e8f9f7	3170	break;
<>	144:ef7eb2e8f9f7	3171
<>	144:ef7eb2e8f9f7	3172	default:
<>	144:ef7eb2e8f9f7	3173	break;
<>	144:ef7eb2e8f9f7	3174	}
<>	144:ef7eb2e8f9f7	3175
<>	144:ef7eb2e8f9f7	3176	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3177
<>	144:ef7eb2e8f9f7	3178	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3179
<>	144:ef7eb2e8f9f7	3180	return HAL_OK;
<>	144:ef7eb2e8f9f7	3181	}
<>	144:ef7eb2e8f9f7	3182
<>	144:ef7eb2e8f9f7	3183	/**
<>	144:ef7eb2e8f9f7	3184	* @brief Initializes the TIM One Pulse Channels according to the specified
<>	144:ef7eb2e8f9f7	3185	* parameters in the TIM_OnePulse_InitTypeDef.
<>	144:ef7eb2e8f9f7	3186	* @param htim : TIM One Pulse handle
<>	144:ef7eb2e8f9f7	3187	* @param sConfig : TIM One Pulse configuration structure
<>	144:ef7eb2e8f9f7	3188	* @param OutputChannel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	3189	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3190	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3191	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3192	* @param InputChannel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	3193	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3194	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	3195	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	3196	* @retval HAL status
<>	144:ef7eb2e8f9f7	3197	*/
<>	144:ef7eb2e8f9f7	3198	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<>	144:ef7eb2e8f9f7	3199	{
<>	144:ef7eb2e8f9f7	3200	TIM_OC_InitTypeDef temp1;
<>	144:ef7eb2e8f9f7	3201
<>	144:ef7eb2e8f9f7	3202	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3203	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<>	144:ef7eb2e8f9f7	3204	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<>	144:ef7eb2e8f9f7	3205
<>	144:ef7eb2e8f9f7	3206	if(OutputChannel != InputChannel)
<>	144:ef7eb2e8f9f7	3207	{
<>	144:ef7eb2e8f9f7	3208	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3209
<>	144:ef7eb2e8f9f7	3210	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3211
<>	144:ef7eb2e8f9f7	3212	/* Extract the Ouput compare configuration from sConfig structure */
<>	144:ef7eb2e8f9f7	3213	temp1.OCMode = sConfig->OCMode;
<>	144:ef7eb2e8f9f7	3214	temp1.Pulse = sConfig->Pulse;
<>	144:ef7eb2e8f9f7	3215	temp1.OCPolarity = sConfig->OCPolarity;
<>	144:ef7eb2e8f9f7	3216	temp1.OCNPolarity = sConfig->OCNPolarity;
<>	144:ef7eb2e8f9f7	3217	temp1.OCIdleState = sConfig->OCIdleState;
<>	144:ef7eb2e8f9f7	3218	temp1.OCNIdleState = sConfig->OCNIdleState;
<>	144:ef7eb2e8f9f7	3219
<>	144:ef7eb2e8f9f7	3220	switch (OutputChannel)
<>	144:ef7eb2e8f9f7	3221	{
<>	144:ef7eb2e8f9f7	3222	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3223	{
<>	144:ef7eb2e8f9f7	3224	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3225
<>	144:ef7eb2e8f9f7	3226	TIM_OC1_SetConfig(htim->Instance, &temp1);
<>	144:ef7eb2e8f9f7	3227	}
<>	144:ef7eb2e8f9f7	3228	break;
<>	144:ef7eb2e8f9f7	3229	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3230	{
<>	144:ef7eb2e8f9f7	3231	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3232
<>	144:ef7eb2e8f9f7	3233	TIM_OC2_SetConfig(htim->Instance, &temp1);
<>	144:ef7eb2e8f9f7	3234	}
<>	144:ef7eb2e8f9f7	3235	break;
<>	144:ef7eb2e8f9f7	3236	default:
<>	144:ef7eb2e8f9f7	3237	break;
<>	144:ef7eb2e8f9f7	3238	}
<>	144:ef7eb2e8f9f7	3239	switch (InputChannel)
<>	144:ef7eb2e8f9f7	3240	{
<>	144:ef7eb2e8f9f7	3241	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3242	{
<>	144:ef7eb2e8f9f7	3243	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3244
<>	144:ef7eb2e8f9f7	3245	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3246	sConfig->ICSelection, sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3247
<>	144:ef7eb2e8f9f7	3248	/* Reset the IC1PSC Bits */
<>	144:ef7eb2e8f9f7	3249	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	144:ef7eb2e8f9f7	3250
<>	144:ef7eb2e8f9f7	3251	/* Select the Trigger source */
<>	144:ef7eb2e8f9f7	3252	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	3253	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
<>	144:ef7eb2e8f9f7	3254
<>	144:ef7eb2e8f9f7	3255	/* Select the Slave Mode */
<>	144:ef7eb2e8f9f7	3256	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3257	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
<>	144:ef7eb2e8f9f7	3258	}
<>	144:ef7eb2e8f9f7	3259	break;
<>	144:ef7eb2e8f9f7	3260	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3261	{
<>	144:ef7eb2e8f9f7	3262	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3263
<>	144:ef7eb2e8f9f7	3264	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<>	144:ef7eb2e8f9f7	3265	sConfig->ICSelection, sConfig->ICFilter);
<>	144:ef7eb2e8f9f7	3266
<>	144:ef7eb2e8f9f7	3267	/* Reset the IC2PSC Bits */
<>	144:ef7eb2e8f9f7	3268	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<>	144:ef7eb2e8f9f7	3269
<>	144:ef7eb2e8f9f7	3270	/* Select the Trigger source */
<>	144:ef7eb2e8f9f7	3271	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	3272	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
<>	144:ef7eb2e8f9f7	3273
<>	144:ef7eb2e8f9f7	3274	/* Select the Slave Mode */
<>	144:ef7eb2e8f9f7	3275	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3276	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
<>	144:ef7eb2e8f9f7	3277	}
<>	144:ef7eb2e8f9f7	3278	break;
<>	144:ef7eb2e8f9f7	3279
<>	144:ef7eb2e8f9f7	3280	default:
<>	144:ef7eb2e8f9f7	3281	break;
<>	144:ef7eb2e8f9f7	3282	}
<>	144:ef7eb2e8f9f7	3283
<>	144:ef7eb2e8f9f7	3284	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3285
<>	144:ef7eb2e8f9f7	3286	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3287
<>	144:ef7eb2e8f9f7	3288	return HAL_OK;
<>	144:ef7eb2e8f9f7	3289	}
<>	144:ef7eb2e8f9f7	3290	else
<>	144:ef7eb2e8f9f7	3291	{
<>	144:ef7eb2e8f9f7	3292	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3293	}
<>	144:ef7eb2e8f9f7	3294	}
<>	144:ef7eb2e8f9f7	3295
<>	144:ef7eb2e8f9f7	3296	/**
<>	144:ef7eb2e8f9f7	3297	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
<>	144:ef7eb2e8f9f7	3298	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3299	* @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
<>	144:ef7eb2e8f9f7	3300	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3301	* @arg TIM_DMABASE_CR1
<>	144:ef7eb2e8f9f7	3302	* @arg TIM_DMABASE_CR2
<>	144:ef7eb2e8f9f7	3303	* @arg TIM_DMABASE_SMCR
<>	144:ef7eb2e8f9f7	3304	* @arg TIM_DMABASE_DIER
<>	144:ef7eb2e8f9f7	3305	* @arg TIM_DMABASE_SR
<>	144:ef7eb2e8f9f7	3306	* @arg TIM_DMABASE_EGR
<>	144:ef7eb2e8f9f7	3307	* @arg TIM_DMABASE_CCMR1
<>	144:ef7eb2e8f9f7	3308	* @arg TIM_DMABASE_CCMR2
<>	144:ef7eb2e8f9f7	3309	* @arg TIM_DMABASE_CCER
<>	144:ef7eb2e8f9f7	3310	* @arg TIM_DMABASE_CNT
<>	144:ef7eb2e8f9f7	3311	* @arg TIM_DMABASE_PSC
<>	144:ef7eb2e8f9f7	3312	* @arg TIM_DMABASE_ARR
<>	144:ef7eb2e8f9f7	3313	* @arg TIM_DMABASE_RCR
<>	144:ef7eb2e8f9f7	3314	* @arg TIM_DMABASE_CCR1
<>	144:ef7eb2e8f9f7	3315	* @arg TIM_DMABASE_CCR2
<>	144:ef7eb2e8f9f7	3316	* @arg TIM_DMABASE_CCR3
<>	144:ef7eb2e8f9f7	3317	* @arg TIM_DMABASE_CCR4
<>	144:ef7eb2e8f9f7	3318	* @arg TIM_DMABASE_BDTR
<>	144:ef7eb2e8f9f7	3319	* @arg TIM_DMABASE_DCR
<>	144:ef7eb2e8f9f7	3320	* @param BurstRequestSrc : TIM DMA Request sources
<>	144:ef7eb2e8f9f7	3321	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3322	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
<>	144:ef7eb2e8f9f7	3323	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<>	144:ef7eb2e8f9f7	3324	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<>	144:ef7eb2e8f9f7	3325	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<>	144:ef7eb2e8f9f7	3326	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<>	144:ef7eb2e8f9f7	3327	* @arg TIM_DMA_COM: TIM Commutation DMA source
<>	144:ef7eb2e8f9f7	3328	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<>	144:ef7eb2e8f9f7	3329	* @param BurstBuffer : The Buffer address.
<>	144:ef7eb2e8f9f7	3330	* @param BurstLength : DMA Burst length. This parameter can be one value
<>	144:ef7eb2e8f9f7	3331	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<>	144:ef7eb2e8f9f7	3332	* @retval HAL status
<>	144:ef7eb2e8f9f7	3333	*/
<>	144:ef7eb2e8f9f7	3334	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<>	144:ef7eb2e8f9f7	3335	uint32_t* BurstBuffer, uint32_t BurstLength)
<>	144:ef7eb2e8f9f7	3336	{
<>	144:ef7eb2e8f9f7	3337	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3338	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3339	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<>	144:ef7eb2e8f9f7	3340	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3341	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<>	144:ef7eb2e8f9f7	3342
<>	144:ef7eb2e8f9f7	3343	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	3344	{
<>	144:ef7eb2e8f9f7	3345	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3346	}
<>	144:ef7eb2e8f9f7	3347	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	3348	{
AnnaBridge	165:e614a9f1c9e2	3349	if((BurstBuffer == 0U) && (BurstLength > 0U))
<>	144:ef7eb2e8f9f7	3350	{
<>	144:ef7eb2e8f9f7	3351	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3352	}
<>	144:ef7eb2e8f9f7	3353	else
<>	144:ef7eb2e8f9f7	3354	{
<>	144:ef7eb2e8f9f7	3355	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3356	}
<>	144:ef7eb2e8f9f7	3357	}
<>	144:ef7eb2e8f9f7	3358	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3359	{
<>	144:ef7eb2e8f9f7	3360	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3361	{
<>	144:ef7eb2e8f9f7	3362	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3363	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	3364
<>	144:ef7eb2e8f9f7	3365	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3366	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3367
<>	144:ef7eb2e8f9f7	3368	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3369	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3370	}
<>	144:ef7eb2e8f9f7	3371	break;
<>	144:ef7eb2e8f9f7	3372	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3373	{
<>	144:ef7eb2e8f9f7	3374	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3375	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3376
<>	144:ef7eb2e8f9f7	3377	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3378	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3379
<>	144:ef7eb2e8f9f7	3380	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3381	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3382	}
<>	144:ef7eb2e8f9f7	3383	break;
<>	144:ef7eb2e8f9f7	3384	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3385	{
<>	144:ef7eb2e8f9f7	3386	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3387	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3388
<>	144:ef7eb2e8f9f7	3389	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3390	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3391
<>	144:ef7eb2e8f9f7	3392	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3393	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3394	}
<>	144:ef7eb2e8f9f7	3395	break;
<>	144:ef7eb2e8f9f7	3396	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3397	{
<>	144:ef7eb2e8f9f7	3398	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3399	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3400
<>	144:ef7eb2e8f9f7	3401	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3402	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3403
<>	144:ef7eb2e8f9f7	3404	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3405	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3406	}
<>	144:ef7eb2e8f9f7	3407	break;
<>	144:ef7eb2e8f9f7	3408	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3409	{
<>	144:ef7eb2e8f9f7	3410	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3411	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	3412
<>	144:ef7eb2e8f9f7	3413	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3414	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3415
<>	144:ef7eb2e8f9f7	3416	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3417	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3418	}
<>	144:ef7eb2e8f9f7	3419	break;
<>	144:ef7eb2e8f9f7	3420	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3421	{
<>	144:ef7eb2e8f9f7	3422	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3423	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<>	144:ef7eb2e8f9f7	3424
<>	144:ef7eb2e8f9f7	3425	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3426	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3427
<>	144:ef7eb2e8f9f7	3428	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3429	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3430	}
<>	144:ef7eb2e8f9f7	3431	break;
<>	144:ef7eb2e8f9f7	3432	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3433	{
<>	144:ef7eb2e8f9f7	3434	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3435	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<>	144:ef7eb2e8f9f7	3436
<>	144:ef7eb2e8f9f7	3437	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3438	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3439
<>	144:ef7eb2e8f9f7	3440	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3441	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3442	}
<>	144:ef7eb2e8f9f7	3443	break;
<>	144:ef7eb2e8f9f7	3444	default:
<>	144:ef7eb2e8f9f7	3445	break;
<>	144:ef7eb2e8f9f7	3446	}
<>	144:ef7eb2e8f9f7	3447	/* configure the DMA Burst Mode */
<>	144:ef7eb2e8f9f7	3448	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
<>	144:ef7eb2e8f9f7	3449
<>	144:ef7eb2e8f9f7	3450	/* Enable the TIM DMA Request */
<>	144:ef7eb2e8f9f7	3451	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3452
<>	144:ef7eb2e8f9f7	3453	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3454
<>	144:ef7eb2e8f9f7	3455	/* Return function status */
<>	144:ef7eb2e8f9f7	3456	return HAL_OK;
<>	144:ef7eb2e8f9f7	3457	}
<>	144:ef7eb2e8f9f7	3458
<>	144:ef7eb2e8f9f7	3459	/**
<>	144:ef7eb2e8f9f7	3460	* @brief Stops the TIM DMA Burst mode
<>	144:ef7eb2e8f9f7	3461	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3462	* @param BurstRequestSrc : TIM DMA Request sources to disable
<>	144:ef7eb2e8f9f7	3463	* @retval HAL status
<>	144:ef7eb2e8f9f7	3464	*/
<>	144:ef7eb2e8f9f7	3465	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3466	{
<>	144:ef7eb2e8f9f7	3467	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3468	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3469
<>	144:ef7eb2e8f9f7	3470	/* Abort the DMA transfer (at least disable the DMA channel) */
<>	144:ef7eb2e8f9f7	3471	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3472	{
<>	144:ef7eb2e8f9f7	3473	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3474	{
<>	144:ef7eb2e8f9f7	3475	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<>	144:ef7eb2e8f9f7	3476	}
<>	144:ef7eb2e8f9f7	3477	break;
<>	144:ef7eb2e8f9f7	3478	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3479	{
<>	144:ef7eb2e8f9f7	3480	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<>	144:ef7eb2e8f9f7	3481	}
<>	144:ef7eb2e8f9f7	3482	break;
<>	144:ef7eb2e8f9f7	3483	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3484	{
<>	144:ef7eb2e8f9f7	3485	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<>	144:ef7eb2e8f9f7	3486	}
<>	144:ef7eb2e8f9f7	3487	break;
<>	144:ef7eb2e8f9f7	3488	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3489	{
<>	144:ef7eb2e8f9f7	3490	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<>	144:ef7eb2e8f9f7	3491	}
<>	144:ef7eb2e8f9f7	3492	break;
<>	144:ef7eb2e8f9f7	3493	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3494	{
<>	144:ef7eb2e8f9f7	3495	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<>	144:ef7eb2e8f9f7	3496	}
<>	144:ef7eb2e8f9f7	3497	break;
<>	144:ef7eb2e8f9f7	3498	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3499	{
<>	144:ef7eb2e8f9f7	3500	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<>	144:ef7eb2e8f9f7	3501	}
<>	144:ef7eb2e8f9f7	3502	break;
<>	144:ef7eb2e8f9f7	3503	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3504	{
<>	144:ef7eb2e8f9f7	3505	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<>	144:ef7eb2e8f9f7	3506	}
<>	144:ef7eb2e8f9f7	3507	break;
<>	144:ef7eb2e8f9f7	3508	default:
<>	144:ef7eb2e8f9f7	3509	break;
<>	144:ef7eb2e8f9f7	3510	}
<>	144:ef7eb2e8f9f7	3511
<>	144:ef7eb2e8f9f7	3512	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	3513	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3514
<>	144:ef7eb2e8f9f7	3515	/* Return function status */
<>	144:ef7eb2e8f9f7	3516	return HAL_OK;
<>	144:ef7eb2e8f9f7	3517	}
<>	144:ef7eb2e8f9f7	3518
<>	144:ef7eb2e8f9f7	3519	/**
<>	144:ef7eb2e8f9f7	3520	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
<>	144:ef7eb2e8f9f7	3521	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3522	* @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
<>	144:ef7eb2e8f9f7	3523	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3524	* @arg TIM_DMABASE_CR1
<>	144:ef7eb2e8f9f7	3525	* @arg TIM_DMABASE_CR2
<>	144:ef7eb2e8f9f7	3526	* @arg TIM_DMABASE_SMCR
<>	144:ef7eb2e8f9f7	3527	* @arg TIM_DMABASE_DIER
<>	144:ef7eb2e8f9f7	3528	* @arg TIM_DMABASE_SR
<>	144:ef7eb2e8f9f7	3529	* @arg TIM_DMABASE_EGR
<>	144:ef7eb2e8f9f7	3530	* @arg TIM_DMABASE_CCMR1
<>	144:ef7eb2e8f9f7	3531	* @arg TIM_DMABASE_CCMR2
<>	144:ef7eb2e8f9f7	3532	* @arg TIM_DMABASE_CCER
<>	144:ef7eb2e8f9f7	3533	* @arg TIM_DMABASE_CNT
<>	144:ef7eb2e8f9f7	3534	* @arg TIM_DMABASE_PSC
<>	144:ef7eb2e8f9f7	3535	* @arg TIM_DMABASE_ARR
<>	144:ef7eb2e8f9f7	3536	* @arg TIM_DMABASE_RCR
<>	144:ef7eb2e8f9f7	3537	* @arg TIM_DMABASE_CCR1
<>	144:ef7eb2e8f9f7	3538	* @arg TIM_DMABASE_CCR2
<>	144:ef7eb2e8f9f7	3539	* @arg TIM_DMABASE_CCR3
<>	144:ef7eb2e8f9f7	3540	* @arg TIM_DMABASE_CCR4
<>	144:ef7eb2e8f9f7	3541	* @arg TIM_DMABASE_BDTR
<>	144:ef7eb2e8f9f7	3542	* @arg TIM_DMABASE_DCR
<>	144:ef7eb2e8f9f7	3543	* @param BurstRequestSrc : TIM DMA Request sources
<>	144:ef7eb2e8f9f7	3544	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3545	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
<>	144:ef7eb2e8f9f7	3546	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<>	144:ef7eb2e8f9f7	3547	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<>	144:ef7eb2e8f9f7	3548	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<>	144:ef7eb2e8f9f7	3549	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<>	144:ef7eb2e8f9f7	3550	* @arg TIM_DMA_COM: TIM Commutation DMA source
<>	144:ef7eb2e8f9f7	3551	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<>	144:ef7eb2e8f9f7	3552	* @param BurstBuffer : The Buffer address.
<>	144:ef7eb2e8f9f7	3553	* @param BurstLength : DMA Burst length. This parameter can be one value
<>	144:ef7eb2e8f9f7	3554	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<>	144:ef7eb2e8f9f7	3555	* @retval HAL status
<>	144:ef7eb2e8f9f7	3556	*/
<>	144:ef7eb2e8f9f7	3557	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<>	144:ef7eb2e8f9f7	3558	uint32_t *BurstBuffer, uint32_t BurstLength)
<>	144:ef7eb2e8f9f7	3559	{
<>	144:ef7eb2e8f9f7	3560	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3561	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3562	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<>	144:ef7eb2e8f9f7	3563	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3564	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<>	144:ef7eb2e8f9f7	3565
<>	144:ef7eb2e8f9f7	3566	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	3567	{
<>	144:ef7eb2e8f9f7	3568	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3569	}
<>	144:ef7eb2e8f9f7	3570	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	3571	{
AnnaBridge	165:e614a9f1c9e2	3572	if((BurstBuffer == 0U) && (BurstLength > 0U))
<>	144:ef7eb2e8f9f7	3573	{
<>	144:ef7eb2e8f9f7	3574	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3575	}
<>	144:ef7eb2e8f9f7	3576	else
<>	144:ef7eb2e8f9f7	3577	{
<>	144:ef7eb2e8f9f7	3578	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3579	}
<>	144:ef7eb2e8f9f7	3580	}
<>	144:ef7eb2e8f9f7	3581	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3582	{
<>	144:ef7eb2e8f9f7	3583	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3584	{
<>	144:ef7eb2e8f9f7	3585	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3586	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<>	144:ef7eb2e8f9f7	3587
<>	144:ef7eb2e8f9f7	3588	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3589	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3590
<>	144:ef7eb2e8f9f7	3591	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3592	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3593	}
<>	144:ef7eb2e8f9f7	3594	break;
<>	144:ef7eb2e8f9f7	3595	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3596	{
<>	144:ef7eb2e8f9f7	3597	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3598	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3599
<>	144:ef7eb2e8f9f7	3600	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3601	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3602
<>	144:ef7eb2e8f9f7	3603	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3604	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3605	}
<>	144:ef7eb2e8f9f7	3606	break;
<>	144:ef7eb2e8f9f7	3607	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3608	{
<>	144:ef7eb2e8f9f7	3609	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3610	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3611
<>	144:ef7eb2e8f9f7	3612	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3613	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3614
<>	144:ef7eb2e8f9f7	3615	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3616	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3617	}
<>	144:ef7eb2e8f9f7	3618	break;
<>	144:ef7eb2e8f9f7	3619	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3620	{
<>	144:ef7eb2e8f9f7	3621	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3622	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3623
<>	144:ef7eb2e8f9f7	3624	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3625	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3626
<>	144:ef7eb2e8f9f7	3627	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3628	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3629	}
<>	144:ef7eb2e8f9f7	3630	break;
<>	144:ef7eb2e8f9f7	3631	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3632	{
<>	144:ef7eb2e8f9f7	3633	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3634	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	3635
<>	144:ef7eb2e8f9f7	3636	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3637	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3638
<>	144:ef7eb2e8f9f7	3639	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3640	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3641	}
<>	144:ef7eb2e8f9f7	3642	break;
<>	144:ef7eb2e8f9f7	3643	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3644	{
<>	144:ef7eb2e8f9f7	3645	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3646	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<>	144:ef7eb2e8f9f7	3647
<>	144:ef7eb2e8f9f7	3648	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3649	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3650
<>	144:ef7eb2e8f9f7	3651	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3652	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3653	}
<>	144:ef7eb2e8f9f7	3654	break;
<>	144:ef7eb2e8f9f7	3655	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3656	{
<>	144:ef7eb2e8f9f7	3657	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	3658	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<>	144:ef7eb2e8f9f7	3659
<>	144:ef7eb2e8f9f7	3660	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3661	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	3662
<>	144:ef7eb2e8f9f7	3663	/* Enable the DMA channel */
AnnaBridge	165:e614a9f1c9e2	3664	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
<>	144:ef7eb2e8f9f7	3665	}
<>	144:ef7eb2e8f9f7	3666	break;
<>	144:ef7eb2e8f9f7	3667	default:
<>	144:ef7eb2e8f9f7	3668	break;
<>	144:ef7eb2e8f9f7	3669	}
<>	144:ef7eb2e8f9f7	3670
<>	144:ef7eb2e8f9f7	3671	/* configure the DMA Burst Mode */
<>	144:ef7eb2e8f9f7	3672	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
<>	144:ef7eb2e8f9f7	3673
<>	144:ef7eb2e8f9f7	3674	/* Enable the TIM DMA Request */
<>	144:ef7eb2e8f9f7	3675	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3676
<>	144:ef7eb2e8f9f7	3677	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3678
<>	144:ef7eb2e8f9f7	3679	/* Return function status */
<>	144:ef7eb2e8f9f7	3680	return HAL_OK;
<>	144:ef7eb2e8f9f7	3681	}
<>	144:ef7eb2e8f9f7	3682
<>	144:ef7eb2e8f9f7	3683	/**
<>	144:ef7eb2e8f9f7	3684	* @brief Stop the DMA burst reading
<>	144:ef7eb2e8f9f7	3685	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3686	* @param BurstRequestSrc : TIM DMA Request sources to disable.
<>	144:ef7eb2e8f9f7	3687	* @retval HAL status
<>	144:ef7eb2e8f9f7	3688	*/
<>	144:ef7eb2e8f9f7	3689	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3690	{
<>	144:ef7eb2e8f9f7	3691	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3692	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<>	144:ef7eb2e8f9f7	3693
<>	144:ef7eb2e8f9f7	3694	/* Abort the DMA transfer (at least disable the DMA channel) */
<>	144:ef7eb2e8f9f7	3695	switch(BurstRequestSrc)
<>	144:ef7eb2e8f9f7	3696	{
<>	144:ef7eb2e8f9f7	3697	case TIM_DMA_UPDATE:
<>	144:ef7eb2e8f9f7	3698	{
<>	144:ef7eb2e8f9f7	3699	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<>	144:ef7eb2e8f9f7	3700	}
<>	144:ef7eb2e8f9f7	3701	break;
<>	144:ef7eb2e8f9f7	3702	case TIM_DMA_CC1:
<>	144:ef7eb2e8f9f7	3703	{
<>	144:ef7eb2e8f9f7	3704	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<>	144:ef7eb2e8f9f7	3705	}
<>	144:ef7eb2e8f9f7	3706	break;
<>	144:ef7eb2e8f9f7	3707	case TIM_DMA_CC2:
<>	144:ef7eb2e8f9f7	3708	{
<>	144:ef7eb2e8f9f7	3709	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<>	144:ef7eb2e8f9f7	3710	}
<>	144:ef7eb2e8f9f7	3711	break;
<>	144:ef7eb2e8f9f7	3712	case TIM_DMA_CC3:
<>	144:ef7eb2e8f9f7	3713	{
<>	144:ef7eb2e8f9f7	3714	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<>	144:ef7eb2e8f9f7	3715	}
<>	144:ef7eb2e8f9f7	3716	break;
<>	144:ef7eb2e8f9f7	3717	case TIM_DMA_CC4:
<>	144:ef7eb2e8f9f7	3718	{
<>	144:ef7eb2e8f9f7	3719	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<>	144:ef7eb2e8f9f7	3720	}
<>	144:ef7eb2e8f9f7	3721	break;
<>	144:ef7eb2e8f9f7	3722	case TIM_DMA_COM:
<>	144:ef7eb2e8f9f7	3723	{
<>	144:ef7eb2e8f9f7	3724	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<>	144:ef7eb2e8f9f7	3725	}
<>	144:ef7eb2e8f9f7	3726	break;
<>	144:ef7eb2e8f9f7	3727	case TIM_DMA_TRIGGER:
<>	144:ef7eb2e8f9f7	3728	{
<>	144:ef7eb2e8f9f7	3729	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<>	144:ef7eb2e8f9f7	3730	}
<>	144:ef7eb2e8f9f7	3731	break;
<>	144:ef7eb2e8f9f7	3732	default:
<>	144:ef7eb2e8f9f7	3733	break;
<>	144:ef7eb2e8f9f7	3734	}
<>	144:ef7eb2e8f9f7	3735
<>	144:ef7eb2e8f9f7	3736	/* Disable the TIM Update DMA request */
<>	144:ef7eb2e8f9f7	3737	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<>	144:ef7eb2e8f9f7	3738
<>	144:ef7eb2e8f9f7	3739	/* Return function status */
<>	144:ef7eb2e8f9f7	3740	return HAL_OK;
<>	144:ef7eb2e8f9f7	3741	}
<>	144:ef7eb2e8f9f7	3742
<>	144:ef7eb2e8f9f7	3743	/**
<>	144:ef7eb2e8f9f7	3744	* @brief Generate a software event
<>	144:ef7eb2e8f9f7	3745	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3746	* @param EventSource : specifies the event source.
<>	144:ef7eb2e8f9f7	3747	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3748	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
<>	144:ef7eb2e8f9f7	3749	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<>	144:ef7eb2e8f9f7	3750	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
<>	144:ef7eb2e8f9f7	3751	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
<>	144:ef7eb2e8f9f7	3752	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
<>	144:ef7eb2e8f9f7	3753	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
<>	144:ef7eb2e8f9f7	3754	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
<>	144:ef7eb2e8f9f7	3755	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
<>	144:ef7eb2e8f9f7	3756	* @note TIM6 and TIM7 can only generate an update event.
<>	144:ef7eb2e8f9f7	3757	* @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
<>	144:ef7eb2e8f9f7	3758	* @retval HAL status
<>	144:ef7eb2e8f9f7	3759	*/
<>	144:ef7eb2e8f9f7	3760
<>	144:ef7eb2e8f9f7	3761	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<>	144:ef7eb2e8f9f7	3762	{
<>	144:ef7eb2e8f9f7	3763	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3764	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3765	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<>	144:ef7eb2e8f9f7	3766
<>	144:ef7eb2e8f9f7	3767	/* Process Locked */
<>	144:ef7eb2e8f9f7	3768	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3769
<>	144:ef7eb2e8f9f7	3770	/* Change the TIM state */
<>	144:ef7eb2e8f9f7	3771	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3772
<>	144:ef7eb2e8f9f7	3773	/* Set the event sources */
<>	144:ef7eb2e8f9f7	3774	htim->Instance->EGR = EventSource;
<>	144:ef7eb2e8f9f7	3775
<>	144:ef7eb2e8f9f7	3776	/* Change the TIM state */
<>	144:ef7eb2e8f9f7	3777	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3778
<>	144:ef7eb2e8f9f7	3779	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3780
<>	144:ef7eb2e8f9f7	3781	/* Return function status */
<>	144:ef7eb2e8f9f7	3782	return HAL_OK;
<>	144:ef7eb2e8f9f7	3783	}
<>	144:ef7eb2e8f9f7	3784
<>	144:ef7eb2e8f9f7	3785	/**
<>	144:ef7eb2e8f9f7	3786	* @brief Configures the OCRef clear feature
<>	144:ef7eb2e8f9f7	3787	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3788	* @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	3789	* contains the OCREF clear feature and parameters for the TIM peripheral.
<>	144:ef7eb2e8f9f7	3790	* @param Channel : specifies the TIM Channel
<>	144:ef7eb2e8f9f7	3791	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	3792	* @arg TIM_CHANNEL_1: TIM Channel 1
<>	144:ef7eb2e8f9f7	3793	* @arg TIM_CHANNEL_2: TIM Channel 2
<>	144:ef7eb2e8f9f7	3794	* @arg TIM_CHANNEL_3: TIM Channel 3
<>	144:ef7eb2e8f9f7	3795	* @arg TIM_CHANNEL_4: TIM Channel 4
<>	144:ef7eb2e8f9f7	3796	* @retval HAL status
<>	144:ef7eb2e8f9f7	3797	*/
<>	144:ef7eb2e8f9f7	3798	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
<>	144:ef7eb2e8f9f7	3799	{
AnnaBridge	165:e614a9f1c9e2	3800	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	3801
<>	144:ef7eb2e8f9f7	3802	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3803	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3804	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<>	144:ef7eb2e8f9f7	3805	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<>	144:ef7eb2e8f9f7	3806	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<>	144:ef7eb2e8f9f7	3807	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<>	144:ef7eb2e8f9f7	3808
<>	144:ef7eb2e8f9f7	3809	/* Process Locked */
<>	144:ef7eb2e8f9f7	3810	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3811
<>	144:ef7eb2e8f9f7	3812	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3813
<>	144:ef7eb2e8f9f7	3814	switch (sClearInputConfig->ClearInputSource)
<>	144:ef7eb2e8f9f7	3815	{
<>	144:ef7eb2e8f9f7	3816	case TIM_CLEARINPUTSOURCE_NONE:
<>	144:ef7eb2e8f9f7	3817	{
<>	144:ef7eb2e8f9f7	3818
<>	144:ef7eb2e8f9f7	3819	/* Clear the ETR Bits */
<>	144:ef7eb2e8f9f7	3820	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	3821
<>	144:ef7eb2e8f9f7	3822	/* Set TIMx_SMCR */
<>	144:ef7eb2e8f9f7	3823	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	3824	}
<>	144:ef7eb2e8f9f7	3825	break;
<>	144:ef7eb2e8f9f7	3826
<>	144:ef7eb2e8f9f7	3827	case TIM_CLEARINPUTSOURCE_ETR:
<>	144:ef7eb2e8f9f7	3828	{
<>	144:ef7eb2e8f9f7	3829	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3830	sClearInputConfig->ClearInputPrescaler,
<>	144:ef7eb2e8f9f7	3831	sClearInputConfig->ClearInputPolarity,
<>	144:ef7eb2e8f9f7	3832	sClearInputConfig->ClearInputFilter);
<>	144:ef7eb2e8f9f7	3833
<>	144:ef7eb2e8f9f7	3834	}
<>	144:ef7eb2e8f9f7	3835	break;
<>	144:ef7eb2e8f9f7	3836	default:
<>	144:ef7eb2e8f9f7	3837	break;
<>	144:ef7eb2e8f9f7	3838	}
<>	144:ef7eb2e8f9f7	3839
<>	144:ef7eb2e8f9f7	3840	switch (Channel)
<>	144:ef7eb2e8f9f7	3841	{
<>	144:ef7eb2e8f9f7	3842	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	3843	{
<>	144:ef7eb2e8f9f7	3844	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3845	{
<>	144:ef7eb2e8f9f7	3846	/* Enable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	3847	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
<>	144:ef7eb2e8f9f7	3848	}
<>	144:ef7eb2e8f9f7	3849	else
<>	144:ef7eb2e8f9f7	3850	{
<>	144:ef7eb2e8f9f7	3851	/* Disable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	3852	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<>	144:ef7eb2e8f9f7	3853	}
<>	144:ef7eb2e8f9f7	3854	}
<>	144:ef7eb2e8f9f7	3855	break;
<>	144:ef7eb2e8f9f7	3856	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	3857	{
<>	144:ef7eb2e8f9f7	3858	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3859	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3860	{
<>	144:ef7eb2e8f9f7	3861	/* Enable the Ocref clear feature for Channel 2 */
<>	144:ef7eb2e8f9f7	3862	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
<>	144:ef7eb2e8f9f7	3863	}
<>	144:ef7eb2e8f9f7	3864	else
<>	144:ef7eb2e8f9f7	3865	{
<>	144:ef7eb2e8f9f7	3866	/* Disable the Ocref clear feature for Channel 2 */
<>	144:ef7eb2e8f9f7	3867	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<>	144:ef7eb2e8f9f7	3868	}
<>	144:ef7eb2e8f9f7	3869	}
<>	144:ef7eb2e8f9f7	3870	break;
<>	144:ef7eb2e8f9f7	3871	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	3872	{
<>	144:ef7eb2e8f9f7	3873	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3874	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3875	{
<>	144:ef7eb2e8f9f7	3876	/* Enable the Ocref clear feature for Channel 3 */
<>	144:ef7eb2e8f9f7	3877	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
<>	144:ef7eb2e8f9f7	3878	}
<>	144:ef7eb2e8f9f7	3879	else
<>	144:ef7eb2e8f9f7	3880	{
<>	144:ef7eb2e8f9f7	3881	/* Disable the Ocref clear feature for Channel 3 */
<>	144:ef7eb2e8f9f7	3882	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<>	144:ef7eb2e8f9f7	3883	}
<>	144:ef7eb2e8f9f7	3884	}
<>	144:ef7eb2e8f9f7	3885	break;
<>	144:ef7eb2e8f9f7	3886	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	3887	{
<>	144:ef7eb2e8f9f7	3888	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3889	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	3890	{
<>	144:ef7eb2e8f9f7	3891	/* Enable the Ocref clear feature for Channel 4 */
<>	144:ef7eb2e8f9f7	3892	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
<>	144:ef7eb2e8f9f7	3893	}
<>	144:ef7eb2e8f9f7	3894	else
<>	144:ef7eb2e8f9f7	3895	{
<>	144:ef7eb2e8f9f7	3896	/* Disable the Ocref clear feature for Channel 4 */
<>	144:ef7eb2e8f9f7	3897	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<>	144:ef7eb2e8f9f7	3898	}
<>	144:ef7eb2e8f9f7	3899	}
<>	144:ef7eb2e8f9f7	3900	break;
<>	144:ef7eb2e8f9f7	3901	default:
<>	144:ef7eb2e8f9f7	3902	break;
<>	144:ef7eb2e8f9f7	3903	}
<>	144:ef7eb2e8f9f7	3904
<>	144:ef7eb2e8f9f7	3905	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	3906
<>	144:ef7eb2e8f9f7	3907	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	3908
<>	144:ef7eb2e8f9f7	3909	return HAL_OK;
<>	144:ef7eb2e8f9f7	3910	}
<>	144:ef7eb2e8f9f7	3911
<>	144:ef7eb2e8f9f7	3912	/**
<>	144:ef7eb2e8f9f7	3913	* @brief Configures the clock source to be used
<>	144:ef7eb2e8f9f7	3914	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	3915	* @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	3916	* contains the clock source information for the TIM peripheral.
<>	144:ef7eb2e8f9f7	3917	* @retval HAL status
<>	144:ef7eb2e8f9f7	3918	*/
<>	144:ef7eb2e8f9f7	3919	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
<>	144:ef7eb2e8f9f7	3920	{
AnnaBridge	165:e614a9f1c9e2	3921	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	3922
<>	144:ef7eb2e8f9f7	3923	/* Process Locked */
<>	144:ef7eb2e8f9f7	3924	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	3925
<>	144:ef7eb2e8f9f7	3926	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3927
<>	144:ef7eb2e8f9f7	3928	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3929	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<>	144:ef7eb2e8f9f7	3930
<>	144:ef7eb2e8f9f7	3931	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<>	144:ef7eb2e8f9f7	3932	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	3933	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
<>	144:ef7eb2e8f9f7	3934	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	3935	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	3936
<>	144:ef7eb2e8f9f7	3937	switch (sClockSourceConfig->ClockSource)
<>	144:ef7eb2e8f9f7	3938	{
<>	144:ef7eb2e8f9f7	3939	case TIM_CLOCKSOURCE_INTERNAL:
<>	144:ef7eb2e8f9f7	3940	{
<>	144:ef7eb2e8f9f7	3941	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3942	/* Disable slave mode to clock the prescaler directly with the internal clock */
<>	144:ef7eb2e8f9f7	3943	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	3944	}
<>	144:ef7eb2e8f9f7	3945	break;
<>	144:ef7eb2e8f9f7	3946
<>	144:ef7eb2e8f9f7	3947	case TIM_CLOCKSOURCE_ETRMODE1:
<>	144:ef7eb2e8f9f7	3948	{
<>	144:ef7eb2e8f9f7	3949	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
<>	144:ef7eb2e8f9f7	3950	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3951
<>	144:ef7eb2e8f9f7	3952	/* Check ETR input conditioning related parameters */
<>	144:ef7eb2e8f9f7	3953	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<>	144:ef7eb2e8f9f7	3954	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	3955	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	3956
<>	144:ef7eb2e8f9f7	3957	/* Configure the ETR Clock source */
<>	144:ef7eb2e8f9f7	3958	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3959	sClockSourceConfig->ClockPrescaler,
<>	144:ef7eb2e8f9f7	3960	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	3961	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	3962	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	3963	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	3964	/* Reset the SMS and TS Bits */
<>	144:ef7eb2e8f9f7	3965	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
<>	144:ef7eb2e8f9f7	3966	/* Select the External clock mode1 and the ETRF trigger */
<>	144:ef7eb2e8f9f7	3967	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
<>	144:ef7eb2e8f9f7	3968	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	3969	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	3970	}
<>	144:ef7eb2e8f9f7	3971	break;
<>	144:ef7eb2e8f9f7	3972
<>	144:ef7eb2e8f9f7	3973	case TIM_CLOCKSOURCE_ETRMODE2:
<>	144:ef7eb2e8f9f7	3974	{
<>	144:ef7eb2e8f9f7	3975	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
<>	144:ef7eb2e8f9f7	3976	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3977
<>	144:ef7eb2e8f9f7	3978	/* Check ETR input conditioning related parameters */
<>	144:ef7eb2e8f9f7	3979	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<>	144:ef7eb2e8f9f7	3980	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	3981	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	3982
<>	144:ef7eb2e8f9f7	3983	/* Configure the ETR Clock source */
<>	144:ef7eb2e8f9f7	3984	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	3985	sClockSourceConfig->ClockPrescaler,
<>	144:ef7eb2e8f9f7	3986	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	3987	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	3988	/* Enable the External clock mode2 */
<>	144:ef7eb2e8f9f7	3989	htim->Instance->SMCR \|= TIM_SMCR_ECE;
<>	144:ef7eb2e8f9f7	3990	}
<>	144:ef7eb2e8f9f7	3991	break;
<>	144:ef7eb2e8f9f7	3992
<>	144:ef7eb2e8f9f7	3993	case TIM_CLOCKSOURCE_TI1:
<>	144:ef7eb2e8f9f7	3994	{
<>	144:ef7eb2e8f9f7	3995	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	3996	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	3997
<>	144:ef7eb2e8f9f7	3998	/* Check TI1 input conditioning related parameters */
<>	144:ef7eb2e8f9f7	3999	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	4000	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	4001
<>	144:ef7eb2e8f9f7	4002	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4003	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4004	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4005	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<>	144:ef7eb2e8f9f7	4006	}
<>	144:ef7eb2e8f9f7	4007	break;
<>	144:ef7eb2e8f9f7	4008	case TIM_CLOCKSOURCE_TI2:
<>	144:ef7eb2e8f9f7	4009	{
<>	144:ef7eb2e8f9f7	4010	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
<>	144:ef7eb2e8f9f7	4011	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4012
<>	144:ef7eb2e8f9f7	4013	/* Check TI2 input conditioning related parameters */
<>	144:ef7eb2e8f9f7	4014	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	4015	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	4016
<>	144:ef7eb2e8f9f7	4017	TIM_TI2_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4018	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4019	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4020	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<>	144:ef7eb2e8f9f7	4021	}
<>	144:ef7eb2e8f9f7	4022	break;
<>	144:ef7eb2e8f9f7	4023	case TIM_CLOCKSOURCE_TI1ED:
<>	144:ef7eb2e8f9f7	4024	{
<>	144:ef7eb2e8f9f7	4025	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	4026	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4027
<>	144:ef7eb2e8f9f7	4028	/* Check TI1 input conditioning related parameters */
<>	144:ef7eb2e8f9f7	4029	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<>	144:ef7eb2e8f9f7	4030	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<>	144:ef7eb2e8f9f7	4031
<>	144:ef7eb2e8f9f7	4032	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4033	sClockSourceConfig->ClockPolarity,
<>	144:ef7eb2e8f9f7	4034	sClockSourceConfig->ClockFilter);
<>	144:ef7eb2e8f9f7	4035	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<>	144:ef7eb2e8f9f7	4036	}
<>	144:ef7eb2e8f9f7	4037	break;
<>	144:ef7eb2e8f9f7	4038	case TIM_CLOCKSOURCE_ITR0:
<>	144:ef7eb2e8f9f7	4039	{
<>	144:ef7eb2e8f9f7	4040	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	4041	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4042
<>	144:ef7eb2e8f9f7	4043	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<>	144:ef7eb2e8f9f7	4044	}
<>	144:ef7eb2e8f9f7	4045	break;
<>	144:ef7eb2e8f9f7	4046	case TIM_CLOCKSOURCE_ITR1:
<>	144:ef7eb2e8f9f7	4047	{
<>	144:ef7eb2e8f9f7	4048	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	4049	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4050
<>	144:ef7eb2e8f9f7	4051	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<>	144:ef7eb2e8f9f7	4052	}
<>	144:ef7eb2e8f9f7	4053	break;
<>	144:ef7eb2e8f9f7	4054	case TIM_CLOCKSOURCE_ITR2:
<>	144:ef7eb2e8f9f7	4055	{
<>	144:ef7eb2e8f9f7	4056	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	4057	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4058
<>	144:ef7eb2e8f9f7	4059	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<>	144:ef7eb2e8f9f7	4060	}
<>	144:ef7eb2e8f9f7	4061	break;
<>	144:ef7eb2e8f9f7	4062	case TIM_CLOCKSOURCE_ITR3:
<>	144:ef7eb2e8f9f7	4063	{
<>	144:ef7eb2e8f9f7	4064	/* Check whether or not the timer instance supports external clock mode 1 */
<>	144:ef7eb2e8f9f7	4065	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4066
<>	144:ef7eb2e8f9f7	4067	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<>	144:ef7eb2e8f9f7	4068	}
<>	144:ef7eb2e8f9f7	4069	break;
<>	144:ef7eb2e8f9f7	4070
<>	144:ef7eb2e8f9f7	4071	default:
<>	144:ef7eb2e8f9f7	4072	break;
<>	144:ef7eb2e8f9f7	4073	}
<>	144:ef7eb2e8f9f7	4074	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4075
<>	144:ef7eb2e8f9f7	4076	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4077
<>	144:ef7eb2e8f9f7	4078	return HAL_OK;
<>	144:ef7eb2e8f9f7	4079	}
<>	144:ef7eb2e8f9f7	4080
<>	144:ef7eb2e8f9f7	4081	/**
<>	144:ef7eb2e8f9f7	4082	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
<>	144:ef7eb2e8f9f7	4083	* or a XOR combination between CH1_input, CH2_input & CH3_input
<>	144:ef7eb2e8f9f7	4084	* @param htim : TIM handle.
<>	144:ef7eb2e8f9f7	4085	* @param TI1_Selection : Indicate whether or not channel 1 is connected to the
<>	144:ef7eb2e8f9f7	4086	* output of a XOR gate.
<>	144:ef7eb2e8f9f7	4087	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4088	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<>	144:ef7eb2e8f9f7	4089	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<>	144:ef7eb2e8f9f7	4090	* pins are connected to the TI1 input (XOR combination)
<>	144:ef7eb2e8f9f7	4091	* @retval HAL status
<>	144:ef7eb2e8f9f7	4092	*/
<>	144:ef7eb2e8f9f7	4093	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<>	144:ef7eb2e8f9f7	4094	{
AnnaBridge	165:e614a9f1c9e2	4095	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4096
<>	144:ef7eb2e8f9f7	4097	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4098	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4099	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<>	144:ef7eb2e8f9f7	4100
<>	144:ef7eb2e8f9f7	4101	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4102	tmpcr2 = htim->Instance->CR2;
<>	144:ef7eb2e8f9f7	4103
<>	144:ef7eb2e8f9f7	4104	/* Reset the TI1 selection */
<>	144:ef7eb2e8f9f7	4105	tmpcr2 &= ~TIM_CR2_TI1S;
<>	144:ef7eb2e8f9f7	4106
<>	144:ef7eb2e8f9f7	4107	/* Set the the TI1 selection */
<>	144:ef7eb2e8f9f7	4108	tmpcr2 \|= TI1_Selection;
<>	144:ef7eb2e8f9f7	4109
<>	144:ef7eb2e8f9f7	4110	/* Write to TIMxCR2 */
<>	144:ef7eb2e8f9f7	4111	htim->Instance->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4112
<>	144:ef7eb2e8f9f7	4113	return HAL_OK;
<>	144:ef7eb2e8f9f7	4114	}
<>	144:ef7eb2e8f9f7	4115
<>	144:ef7eb2e8f9f7	4116	/**
<>	144:ef7eb2e8f9f7	4117	* @brief Configures the TIM in Slave mode
<>	144:ef7eb2e8f9f7	4118	* @param htim : TIM handle.
<>	144:ef7eb2e8f9f7	4119	* @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	4120	* contains the selected trigger (internal trigger input, filtered
<>	144:ef7eb2e8f9f7	4121	* timer input or external trigger input) and the ) and the Slave
<>	144:ef7eb2e8f9f7	4122	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	144:ef7eb2e8f9f7	4123	* @retval HAL status
<>	144:ef7eb2e8f9f7	4124	*/
<>	144:ef7eb2e8f9f7	4125	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
<>	144:ef7eb2e8f9f7	4126	{
<>	144:ef7eb2e8f9f7	4127	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4128	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4129	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<>	144:ef7eb2e8f9f7	4130	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<>	144:ef7eb2e8f9f7	4131
<>	144:ef7eb2e8f9f7	4132	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	4133
<>	144:ef7eb2e8f9f7	4134	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	4135
<>	144:ef7eb2e8f9f7	4136	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<>	144:ef7eb2e8f9f7	4137
<>	144:ef7eb2e8f9f7	4138	/* Disable Trigger Interrupt */
<>	144:ef7eb2e8f9f7	4139	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	4140
<>	144:ef7eb2e8f9f7	4141	/* Disable Trigger DMA request */
<>	144:ef7eb2e8f9f7	4142	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<>	144:ef7eb2e8f9f7	4143
<>	144:ef7eb2e8f9f7	4144	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4145
<>	144:ef7eb2e8f9f7	4146	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4147
<>	144:ef7eb2e8f9f7	4148	return HAL_OK;
<>	144:ef7eb2e8f9f7	4149	}
<>	144:ef7eb2e8f9f7	4150
<>	144:ef7eb2e8f9f7	4151	/**
<>	144:ef7eb2e8f9f7	4152	* @brief Configures the TIM in Slave mode in interrupt mode
<>	144:ef7eb2e8f9f7	4153	* @param htim: TIM handle.
<>	144:ef7eb2e8f9f7	4154	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	4155	* contains the selected trigger (internal trigger input, filtered
<>	144:ef7eb2e8f9f7	4156	* timer input or external trigger input) and the ) and the Slave
<>	144:ef7eb2e8f9f7	4157	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<>	144:ef7eb2e8f9f7	4158	* @retval HAL status
<>	144:ef7eb2e8f9f7	4159	*/
<>	144:ef7eb2e8f9f7	4160	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	4161	TIM_SlaveConfigTypeDef * sSlaveConfig)
<>	144:ef7eb2e8f9f7	4162	{
<>	144:ef7eb2e8f9f7	4163	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4164	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4165	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<>	144:ef7eb2e8f9f7	4166	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<>	144:ef7eb2e8f9f7	4167
<>	144:ef7eb2e8f9f7	4168	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	4169
<>	144:ef7eb2e8f9f7	4170	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	4171
<>	144:ef7eb2e8f9f7	4172	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<>	144:ef7eb2e8f9f7	4173
<>	144:ef7eb2e8f9f7	4174	/* Enable Trigger Interrupt */
<>	144:ef7eb2e8f9f7	4175	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<>	144:ef7eb2e8f9f7	4176
<>	144:ef7eb2e8f9f7	4177	/* Disable Trigger DMA request */
<>	144:ef7eb2e8f9f7	4178	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<>	144:ef7eb2e8f9f7	4179
<>	144:ef7eb2e8f9f7	4180	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4181
<>	144:ef7eb2e8f9f7	4182	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4183
<>	144:ef7eb2e8f9f7	4184	return HAL_OK;
<>	144:ef7eb2e8f9f7	4185	}
<>	144:ef7eb2e8f9f7	4186
<>	144:ef7eb2e8f9f7	4187	/**
<>	144:ef7eb2e8f9f7	4188	* @brief Read the captured value from Capture Compare unit
<>	144:ef7eb2e8f9f7	4189	* @param htim : TIM handle.
<>	144:ef7eb2e8f9f7	4190	* @param Channel : TIM Channels to be enabled
<>	144:ef7eb2e8f9f7	4191	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	4192	* @arg TIM_CHANNEL_1 : TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	4193	* @arg TIM_CHANNEL_2 : TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	4194	* @arg TIM_CHANNEL_3 : TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	4195	* @arg TIM_CHANNEL_4 : TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	4196	* @retval Captured value
<>	144:ef7eb2e8f9f7	4197	*/
<>	144:ef7eb2e8f9f7	4198	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	4199	{
AnnaBridge	165:e614a9f1c9e2	4200	uint32_t tmpreg = 0U;
<>	144:ef7eb2e8f9f7	4201
<>	144:ef7eb2e8f9f7	4202	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	4203
<>	144:ef7eb2e8f9f7	4204	switch (Channel)
<>	144:ef7eb2e8f9f7	4205	{
<>	144:ef7eb2e8f9f7	4206	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	4207	{
<>	144:ef7eb2e8f9f7	4208	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4209	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4210
<>	144:ef7eb2e8f9f7	4211	/* Return the capture 1 value */
<>	144:ef7eb2e8f9f7	4212	tmpreg = htim->Instance->CCR1;
<>	144:ef7eb2e8f9f7	4213
<>	144:ef7eb2e8f9f7	4214	break;
<>	144:ef7eb2e8f9f7	4215	}
<>	144:ef7eb2e8f9f7	4216	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	4217	{
<>	144:ef7eb2e8f9f7	4218	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4219	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4220
<>	144:ef7eb2e8f9f7	4221	/* Return the capture 2 value */
<>	144:ef7eb2e8f9f7	4222	tmpreg = htim->Instance->CCR2;
<>	144:ef7eb2e8f9f7	4223
<>	144:ef7eb2e8f9f7	4224	break;
<>	144:ef7eb2e8f9f7	4225	}
<>	144:ef7eb2e8f9f7	4226
<>	144:ef7eb2e8f9f7	4227	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	4228	{
<>	144:ef7eb2e8f9f7	4229	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4230	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4231
<>	144:ef7eb2e8f9f7	4232	/* Return the capture 3 value */
<>	144:ef7eb2e8f9f7	4233	tmpreg = htim->Instance->CCR3;
<>	144:ef7eb2e8f9f7	4234
<>	144:ef7eb2e8f9f7	4235	break;
<>	144:ef7eb2e8f9f7	4236	}
<>	144:ef7eb2e8f9f7	4237
<>	144:ef7eb2e8f9f7	4238	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	4239	{
<>	144:ef7eb2e8f9f7	4240	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4241	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4242
<>	144:ef7eb2e8f9f7	4243	/* Return the capture 4 value */
<>	144:ef7eb2e8f9f7	4244	tmpreg = htim->Instance->CCR4;
<>	144:ef7eb2e8f9f7	4245
<>	144:ef7eb2e8f9f7	4246	break;
<>	144:ef7eb2e8f9f7	4247	}
<>	144:ef7eb2e8f9f7	4248
<>	144:ef7eb2e8f9f7	4249	default:
<>	144:ef7eb2e8f9f7	4250	break;
<>	144:ef7eb2e8f9f7	4251	}
<>	144:ef7eb2e8f9f7	4252
<>	144:ef7eb2e8f9f7	4253	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	4254	return tmpreg;
<>	144:ef7eb2e8f9f7	4255	}
<>	144:ef7eb2e8f9f7	4256
<>	144:ef7eb2e8f9f7	4257	/**
<>	144:ef7eb2e8f9f7	4258	* @}
<>	144:ef7eb2e8f9f7	4259	*/
<>	144:ef7eb2e8f9f7	4260
<>	144:ef7eb2e8f9f7	4261	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
<>	144:ef7eb2e8f9f7	4262	* @brief TIM Callbacks functions
<>	144:ef7eb2e8f9f7	4263	*
<>	144:ef7eb2e8f9f7	4264	@verbatim
<>	144:ef7eb2e8f9f7	4265	==============================================================================
<>	144:ef7eb2e8f9f7	4266	##### TIM Callbacks functions #####
<>	144:ef7eb2e8f9f7	4267	==============================================================================
<>	144:ef7eb2e8f9f7	4268	[..]
<>	144:ef7eb2e8f9f7	4269	This section provides TIM callback functions:
<>	144:ef7eb2e8f9f7	4270	(+) Timer Period elapsed callback
<>	144:ef7eb2e8f9f7	4271	(+) Timer Output Compare callback
<>	144:ef7eb2e8f9f7	4272	(+) Timer Input capture callback
<>	144:ef7eb2e8f9f7	4273	(+) Timer Trigger callback
<>	144:ef7eb2e8f9f7	4274	(+) Timer Error callback
<>	144:ef7eb2e8f9f7	4275
<>	144:ef7eb2e8f9f7	4276	@endverbatim
<>	144:ef7eb2e8f9f7	4277	* @{
<>	144:ef7eb2e8f9f7	4278	*/
<>	144:ef7eb2e8f9f7	4279
<>	144:ef7eb2e8f9f7	4280	/**
<>	144:ef7eb2e8f9f7	4281	* @brief Period elapsed callback in non blocking mode
<>	144:ef7eb2e8f9f7	4282	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4283	* @retval None
<>	144:ef7eb2e8f9f7	4284	*/
<>	144:ef7eb2e8f9f7	4285	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4286	{
<>	144:ef7eb2e8f9f7	4287	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4288	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4289	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4290	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4291	*/
<>	144:ef7eb2e8f9f7	4292
<>	144:ef7eb2e8f9f7	4293	}
<>	144:ef7eb2e8f9f7	4294	/**
<>	144:ef7eb2e8f9f7	4295	* @brief Output Compare callback in non blocking mode
<>	144:ef7eb2e8f9f7	4296	* @param htim : TIM OC handle
<>	144:ef7eb2e8f9f7	4297	* @retval None
<>	144:ef7eb2e8f9f7	4298	*/
<>	144:ef7eb2e8f9f7	4299	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4300	{
<>	144:ef7eb2e8f9f7	4301	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4302	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4303	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4304	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4305	*/
<>	144:ef7eb2e8f9f7	4306	}
<>	144:ef7eb2e8f9f7	4307	/**
<>	144:ef7eb2e8f9f7	4308	* @brief Input Capture callback in non blocking mode
<>	144:ef7eb2e8f9f7	4309	* @param htim : TIM IC handle
<>	144:ef7eb2e8f9f7	4310	* @retval None
<>	144:ef7eb2e8f9f7	4311	*/
<>	144:ef7eb2e8f9f7	4312	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4313	{
<>	144:ef7eb2e8f9f7	4314	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4315	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4316	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4317	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4318	*/
<>	144:ef7eb2e8f9f7	4319	}
<>	144:ef7eb2e8f9f7	4320
<>	144:ef7eb2e8f9f7	4321	/**
<>	144:ef7eb2e8f9f7	4322	* @brief PWM Pulse finished callback in non blocking mode
<>	144:ef7eb2e8f9f7	4323	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4324	* @retval None
<>	144:ef7eb2e8f9f7	4325	*/
<>	144:ef7eb2e8f9f7	4326	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4327	{
<>	144:ef7eb2e8f9f7	4328	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4329	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4330	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4331	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4332	*/
<>	144:ef7eb2e8f9f7	4333	}
<>	144:ef7eb2e8f9f7	4334
<>	144:ef7eb2e8f9f7	4335	/**
<>	144:ef7eb2e8f9f7	4336	* @brief Hall Trigger detection callback in non blocking mode
<>	144:ef7eb2e8f9f7	4337	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4338	* @retval None
<>	144:ef7eb2e8f9f7	4339	*/
<>	144:ef7eb2e8f9f7	4340	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4341	{
<>	144:ef7eb2e8f9f7	4342	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4343	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4344	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4345	the HAL_TIM_TriggerCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4346	*/
<>	144:ef7eb2e8f9f7	4347	}
<>	144:ef7eb2e8f9f7	4348
<>	144:ef7eb2e8f9f7	4349	/**
<>	144:ef7eb2e8f9f7	4350	* @brief Timer error callback in non blocking mode
<>	144:ef7eb2e8f9f7	4351	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4352	* @retval None
<>	144:ef7eb2e8f9f7	4353	*/
<>	144:ef7eb2e8f9f7	4354	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4355	{
<>	144:ef7eb2e8f9f7	4356	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	4357	UNUSED(htim);
<>	144:ef7eb2e8f9f7	4358	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	4359	the HAL_TIM_ErrorCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	4360	*/
<>	144:ef7eb2e8f9f7	4361	}
<>	144:ef7eb2e8f9f7	4362
<>	144:ef7eb2e8f9f7	4363	/**
<>	144:ef7eb2e8f9f7	4364	* @}
<>	144:ef7eb2e8f9f7	4365	*/
<>	144:ef7eb2e8f9f7	4366
<>	144:ef7eb2e8f9f7	4367	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<>	144:ef7eb2e8f9f7	4368	* @brief Peripheral State functions
<>	144:ef7eb2e8f9f7	4369	*
<>	144:ef7eb2e8f9f7	4370	@verbatim
<>	144:ef7eb2e8f9f7	4371	==============================================================================
<>	144:ef7eb2e8f9f7	4372	##### Peripheral State functions #####
<>	144:ef7eb2e8f9f7	4373	==============================================================================
<>	144:ef7eb2e8f9f7	4374	[..]
<>	144:ef7eb2e8f9f7	4375	This subsection permit to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	4376	and the data flow.
<>	144:ef7eb2e8f9f7	4377
<>	144:ef7eb2e8f9f7	4378	@endverbatim
<>	144:ef7eb2e8f9f7	4379	* @{
<>	144:ef7eb2e8f9f7	4380	*/
<>	144:ef7eb2e8f9f7	4381
<>	144:ef7eb2e8f9f7	4382	/**
<>	144:ef7eb2e8f9f7	4383	* @brief Return the TIM Base state
<>	144:ef7eb2e8f9f7	4384	* @param htim : TIM Base handle
<>	144:ef7eb2e8f9f7	4385	* @retval HAL state
<>	144:ef7eb2e8f9f7	4386	*/
<>	144:ef7eb2e8f9f7	4387	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4388	{
<>	144:ef7eb2e8f9f7	4389	return htim->State;
<>	144:ef7eb2e8f9f7	4390	}
<>	144:ef7eb2e8f9f7	4391
<>	144:ef7eb2e8f9f7	4392	/**
<>	144:ef7eb2e8f9f7	4393	* @brief Return the TIM OC state
<>	144:ef7eb2e8f9f7	4394	* @param htim : TIM Ouput Compare handle
<>	144:ef7eb2e8f9f7	4395	* @retval HAL state
<>	144:ef7eb2e8f9f7	4396	*/
<>	144:ef7eb2e8f9f7	4397	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4398	{
<>	144:ef7eb2e8f9f7	4399	return htim->State;
<>	144:ef7eb2e8f9f7	4400	}
<>	144:ef7eb2e8f9f7	4401
<>	144:ef7eb2e8f9f7	4402	/**
<>	144:ef7eb2e8f9f7	4403	* @brief Return the TIM PWM state
<>	144:ef7eb2e8f9f7	4404	* @param htim : TIM handle
<>	144:ef7eb2e8f9f7	4405	* @retval HAL state
<>	144:ef7eb2e8f9f7	4406	*/
<>	144:ef7eb2e8f9f7	4407	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4408	{
<>	144:ef7eb2e8f9f7	4409	return htim->State;
<>	144:ef7eb2e8f9f7	4410	}
<>	144:ef7eb2e8f9f7	4411
<>	144:ef7eb2e8f9f7	4412	/**
<>	144:ef7eb2e8f9f7	4413	* @brief Return the TIM Input Capture state
<>	144:ef7eb2e8f9f7	4414	* @param htim : TIM IC handle
<>	144:ef7eb2e8f9f7	4415	* @retval HAL state
<>	144:ef7eb2e8f9f7	4416	*/
<>	144:ef7eb2e8f9f7	4417	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4418	{
<>	144:ef7eb2e8f9f7	4419	return htim->State;
<>	144:ef7eb2e8f9f7	4420	}
<>	144:ef7eb2e8f9f7	4421
<>	144:ef7eb2e8f9f7	4422	/**
<>	144:ef7eb2e8f9f7	4423	* @brief Return the TIM One Pulse Mode state
<>	144:ef7eb2e8f9f7	4424	* @param htim : TIM OPM handle
<>	144:ef7eb2e8f9f7	4425	* @retval HAL state
<>	144:ef7eb2e8f9f7	4426	*/
<>	144:ef7eb2e8f9f7	4427	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4428	{
<>	144:ef7eb2e8f9f7	4429	return htim->State;
<>	144:ef7eb2e8f9f7	4430	}
<>	144:ef7eb2e8f9f7	4431
<>	144:ef7eb2e8f9f7	4432	/**
<>	144:ef7eb2e8f9f7	4433	* @brief Return the TIM Encoder Mode state
<>	144:ef7eb2e8f9f7	4434	* @param htim : TIM Encoder handle
<>	144:ef7eb2e8f9f7	4435	* @retval HAL state
<>	144:ef7eb2e8f9f7	4436	*/
<>	144:ef7eb2e8f9f7	4437	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	4438	{
<>	144:ef7eb2e8f9f7	4439	return htim->State;
<>	144:ef7eb2e8f9f7	4440	}
<>	144:ef7eb2e8f9f7	4441
<>	144:ef7eb2e8f9f7	4442	/**
<>	144:ef7eb2e8f9f7	4443	* @}
<>	144:ef7eb2e8f9f7	4444	*/
<>	144:ef7eb2e8f9f7	4445
<>	144:ef7eb2e8f9f7	4446	/**
<>	144:ef7eb2e8f9f7	4447	* @}
<>	144:ef7eb2e8f9f7	4448	*/
<>	144:ef7eb2e8f9f7	4449
<>	144:ef7eb2e8f9f7	4450	/** @addtogroup TIM_Private_Functions
<>	144:ef7eb2e8f9f7	4451	* @{
<>	144:ef7eb2e8f9f7	4452	*/
<>	144:ef7eb2e8f9f7	4453
<>	144:ef7eb2e8f9f7	4454	/**
<>	144:ef7eb2e8f9f7	4455	* @brief TIM DMA error callback
<>	144:ef7eb2e8f9f7	4456	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4457	* @retval None
<>	144:ef7eb2e8f9f7	4458	*/
<>	144:ef7eb2e8f9f7	4459	void TIM_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4460	{
<>	144:ef7eb2e8f9f7	4461	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4462
<>	144:ef7eb2e8f9f7	4463	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4464
<>	144:ef7eb2e8f9f7	4465	HAL_TIM_ErrorCallback(htim);
<>	144:ef7eb2e8f9f7	4466	}
<>	144:ef7eb2e8f9f7	4467
<>	144:ef7eb2e8f9f7	4468	/**
<>	144:ef7eb2e8f9f7	4469	* @brief TIM DMA Delay Pulse complete callback.
<>	144:ef7eb2e8f9f7	4470	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4471	* @retval None
<>	144:ef7eb2e8f9f7	4472	*/
<>	144:ef7eb2e8f9f7	4473	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4474	{
<>	144:ef7eb2e8f9f7	4475	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4476
<>	144:ef7eb2e8f9f7	4477	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4478
<>	144:ef7eb2e8f9f7	4479	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<>	144:ef7eb2e8f9f7	4480	{
<>	144:ef7eb2e8f9f7	4481	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	4482	}
<>	144:ef7eb2e8f9f7	4483	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<>	144:ef7eb2e8f9f7	4484	{
<>	144:ef7eb2e8f9f7	4485	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	4486	}
<>	144:ef7eb2e8f9f7	4487	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<>	144:ef7eb2e8f9f7	4488	{
<>	144:ef7eb2e8f9f7	4489	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	4490	}
<>	144:ef7eb2e8f9f7	4491	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<>	144:ef7eb2e8f9f7	4492	{
<>	144:ef7eb2e8f9f7	4493	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	4494	}
<>	144:ef7eb2e8f9f7	4495
<>	144:ef7eb2e8f9f7	4496	HAL_TIM_PWM_PulseFinishedCallback(htim);
<>	144:ef7eb2e8f9f7	4497
<>	144:ef7eb2e8f9f7	4498	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	4499	}
<>	144:ef7eb2e8f9f7	4500	/**
<>	144:ef7eb2e8f9f7	4501	* @brief TIM DMA Capture complete callback.
<>	144:ef7eb2e8f9f7	4502	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4503	* @retval None
<>	144:ef7eb2e8f9f7	4504	*/
<>	144:ef7eb2e8f9f7	4505	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4506	{
<>	144:ef7eb2e8f9f7	4507	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4508
<>	144:ef7eb2e8f9f7	4509	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4510
<>	144:ef7eb2e8f9f7	4511	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<>	144:ef7eb2e8f9f7	4512	{
<>	144:ef7eb2e8f9f7	4513	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<>	144:ef7eb2e8f9f7	4514	}
<>	144:ef7eb2e8f9f7	4515	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<>	144:ef7eb2e8f9f7	4516	{
<>	144:ef7eb2e8f9f7	4517	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<>	144:ef7eb2e8f9f7	4518	}
<>	144:ef7eb2e8f9f7	4519	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<>	144:ef7eb2e8f9f7	4520	{
<>	144:ef7eb2e8f9f7	4521	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<>	144:ef7eb2e8f9f7	4522	}
<>	144:ef7eb2e8f9f7	4523	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<>	144:ef7eb2e8f9f7	4524	{
<>	144:ef7eb2e8f9f7	4525	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<>	144:ef7eb2e8f9f7	4526	}
<>	144:ef7eb2e8f9f7	4527
<>	144:ef7eb2e8f9f7	4528	HAL_TIM_IC_CaptureCallback(htim);
<>	144:ef7eb2e8f9f7	4529
<>	144:ef7eb2e8f9f7	4530	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<>	144:ef7eb2e8f9f7	4531	}
<>	144:ef7eb2e8f9f7	4532
<>	144:ef7eb2e8f9f7	4533	/**
<>	144:ef7eb2e8f9f7	4534	* @brief TIM DMA Period Elapse complete callback.
<>	144:ef7eb2e8f9f7	4535	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4536	* @retval None
<>	144:ef7eb2e8f9f7	4537	*/
<>	144:ef7eb2e8f9f7	4538	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4539	{
<>	144:ef7eb2e8f9f7	4540	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4541
<>	144:ef7eb2e8f9f7	4542	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4543
<>	144:ef7eb2e8f9f7	4544	HAL_TIM_PeriodElapsedCallback(htim);
<>	144:ef7eb2e8f9f7	4545	}
<>	144:ef7eb2e8f9f7	4546
<>	144:ef7eb2e8f9f7	4547	/**
<>	144:ef7eb2e8f9f7	4548	* @brief TIM DMA Trigger callback.
<>	144:ef7eb2e8f9f7	4549	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	4550	* @retval None
<>	144:ef7eb2e8f9f7	4551	*/
<>	144:ef7eb2e8f9f7	4552	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	4553	{
<>	144:ef7eb2e8f9f7	4554	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	4555
<>	144:ef7eb2e8f9f7	4556	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	4557
<>	144:ef7eb2e8f9f7	4558	HAL_TIM_TriggerCallback(htim);
<>	144:ef7eb2e8f9f7	4559	}
<>	144:ef7eb2e8f9f7	4560
<>	144:ef7eb2e8f9f7	4561	/**
<>	144:ef7eb2e8f9f7	4562	* @brief Time Base configuration
<>	144:ef7eb2e8f9f7	4563	* @param TIMx : TIM periheral
<>	144:ef7eb2e8f9f7	4564	* @param Structure : TIM Base configuration structure
<>	144:ef7eb2e8f9f7	4565	* @retval None
<>	144:ef7eb2e8f9f7	4566	*/
<>	144:ef7eb2e8f9f7	4567	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
<>	144:ef7eb2e8f9f7	4568	{
AnnaBridge	165:e614a9f1c9e2	4569	uint32_t tmpcr1 = 0U;
<>	144:ef7eb2e8f9f7	4570	tmpcr1 = TIMx->CR1;
<>	144:ef7eb2e8f9f7	4571
<>	144:ef7eb2e8f9f7	4572	/* Set TIM Time Base Unit parameters ---------------------------------------*/
<>	144:ef7eb2e8f9f7	4573	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4574	{
<>	144:ef7eb2e8f9f7	4575	/* Select the Counter Mode */
<>	144:ef7eb2e8f9f7	4576	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
<>	144:ef7eb2e8f9f7	4577	tmpcr1 \|= Structure->CounterMode;
<>	144:ef7eb2e8f9f7	4578	}
<>	144:ef7eb2e8f9f7	4579
<>	144:ef7eb2e8f9f7	4580	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4581	{
<>	144:ef7eb2e8f9f7	4582	/* Set the clock division */
<>	144:ef7eb2e8f9f7	4583	tmpcr1 &= ~TIM_CR1_CKD;
<>	144:ef7eb2e8f9f7	4584	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
<>	144:ef7eb2e8f9f7	4585	}
<>	144:ef7eb2e8f9f7	4586
AnnaBridge	165:e614a9f1c9e2	4587	/* Set the auto-reload preload */
AnnaBridge	165:e614a9f1c9e2	4588	tmpcr1 &= ~TIM_CR1_ARPE;
AnnaBridge	165:e614a9f1c9e2	4589	tmpcr1 \|= (uint32_t)Structure->AutoReloadPreload;
AnnaBridge	165:e614a9f1c9e2	4590
<>	144:ef7eb2e8f9f7	4591	TIMx->CR1 = tmpcr1;
<>	144:ef7eb2e8f9f7	4592
<>	144:ef7eb2e8f9f7	4593	/* Set the Autoreload value */
<>	144:ef7eb2e8f9f7	4594	TIMx->ARR = (uint32_t)Structure->Period ;
<>	144:ef7eb2e8f9f7	4595
<>	144:ef7eb2e8f9f7	4596	/* Set the Prescaler value */
<>	144:ef7eb2e8f9f7	4597	TIMx->PSC = (uint32_t)Structure->Prescaler;
<>	144:ef7eb2e8f9f7	4598
<>	144:ef7eb2e8f9f7	4599	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4600	{
<>	144:ef7eb2e8f9f7	4601	/* Set the Repetition Counter value */
<>	144:ef7eb2e8f9f7	4602	TIMx->RCR = Structure->RepetitionCounter;
<>	144:ef7eb2e8f9f7	4603	}
<>	144:ef7eb2e8f9f7	4604
<>	144:ef7eb2e8f9f7	4605	/* Generate an update event to reload the Prescaler
<>	144:ef7eb2e8f9f7	4606	and the repetition counter(only for TIM1 and TIM8) value immediatly */
<>	144:ef7eb2e8f9f7	4607	TIMx->EGR = TIM_EGR_UG;
<>	144:ef7eb2e8f9f7	4608	}
<>	144:ef7eb2e8f9f7	4609
<>	144:ef7eb2e8f9f7	4610	/**
<>	144:ef7eb2e8f9f7	4611	* @brief Time Ouput Compare 1 configuration
<>	144:ef7eb2e8f9f7	4612	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4613	* @param OC_Config : The ouput configuration structure
<>	144:ef7eb2e8f9f7	4614	* @retval None
<>	144:ef7eb2e8f9f7	4615	*/
<>	144:ef7eb2e8f9f7	4616	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4617	{
AnnaBridge	165:e614a9f1c9e2	4618	uint32_t tmpccmrx = 0U;
AnnaBridge	165:e614a9f1c9e2	4619	uint32_t tmpccer = 0U;
AnnaBridge	165:e614a9f1c9e2	4620	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4621
<>	144:ef7eb2e8f9f7	4622	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	4623	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	4624
<>	144:ef7eb2e8f9f7	4625	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4626	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4627	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4628	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4629
<>	144:ef7eb2e8f9f7	4630	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	4631	tmpccmrx = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4632
<>	144:ef7eb2e8f9f7	4633	/* Reset the Output Compare Mode Bits */
<>	144:ef7eb2e8f9f7	4634	tmpccmrx &= ~TIM_CCMR1_OC1M;
<>	144:ef7eb2e8f9f7	4635	tmpccmrx &= ~TIM_CCMR1_CC1S;
<>	144:ef7eb2e8f9f7	4636	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4637	tmpccmrx \|= OC_Config->OCMode;
<>	144:ef7eb2e8f9f7	4638
<>	144:ef7eb2e8f9f7	4639	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4640	tmpccer &= ~TIM_CCER_CC1P;
<>	144:ef7eb2e8f9f7	4641	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	4642	tmpccer \|= OC_Config->OCPolarity;
<>	144:ef7eb2e8f9f7	4643
<>	144:ef7eb2e8f9f7	4644	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
<>	144:ef7eb2e8f9f7	4645	{
<>	144:ef7eb2e8f9f7	4646	/* Check parameters */
<>	144:ef7eb2e8f9f7	4647	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<>	144:ef7eb2e8f9f7	4648
<>	144:ef7eb2e8f9f7	4649	/* Reset the Output N Polarity level */
<>	144:ef7eb2e8f9f7	4650	tmpccer &= ~TIM_CCER_CC1NP;
<>	144:ef7eb2e8f9f7	4651	/* Set the Output N Polarity */
<>	144:ef7eb2e8f9f7	4652	tmpccer \|= OC_Config->OCNPolarity;
<>	144:ef7eb2e8f9f7	4653	/* Reset the Output N State */
<>	144:ef7eb2e8f9f7	4654	tmpccer &= ~TIM_CCER_CC1NE;
<>	144:ef7eb2e8f9f7	4655	}
<>	144:ef7eb2e8f9f7	4656
<>	144:ef7eb2e8f9f7	4657	if(IS_TIM_BREAK_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4658	{
<>	144:ef7eb2e8f9f7	4659	/* Check parameters */
<>	144:ef7eb2e8f9f7	4660	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<>	144:ef7eb2e8f9f7	4661	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<>	144:ef7eb2e8f9f7	4662
<>	144:ef7eb2e8f9f7	4663	/* Reset the Output Compare and Output Compare N IDLE State */
<>	144:ef7eb2e8f9f7	4664	tmpcr2 &= ~TIM_CR2_OIS1;
<>	144:ef7eb2e8f9f7	4665	tmpcr2 &= ~TIM_CR2_OIS1N;
<>	144:ef7eb2e8f9f7	4666	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4667	tmpcr2 \|= OC_Config->OCIdleState;
<>	144:ef7eb2e8f9f7	4668	/* Set the Output N Idle state */
<>	144:ef7eb2e8f9f7	4669	tmpcr2 \|= OC_Config->OCNIdleState;
<>	144:ef7eb2e8f9f7	4670	}
<>	144:ef7eb2e8f9f7	4671	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4672	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4673
<>	144:ef7eb2e8f9f7	4674	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	4675	TIMx->CCMR1 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4676
<>	144:ef7eb2e8f9f7	4677	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4678	TIMx->CCR1 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4679
<>	144:ef7eb2e8f9f7	4680	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4681	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4682	}
<>	144:ef7eb2e8f9f7	4683
<>	144:ef7eb2e8f9f7	4684	/**
<>	144:ef7eb2e8f9f7	4685	* @brief Time Ouput Compare 2 configuration
<>	144:ef7eb2e8f9f7	4686	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4687	* @param OC_Config : The ouput configuration structure
<>	144:ef7eb2e8f9f7	4688	* @retval None
<>	144:ef7eb2e8f9f7	4689	*/
<>	144:ef7eb2e8f9f7	4690	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4691	{
AnnaBridge	165:e614a9f1c9e2	4692	uint32_t tmpccmrx = 0U;
AnnaBridge	165:e614a9f1c9e2	4693	uint32_t tmpccer = 0U;
AnnaBridge	165:e614a9f1c9e2	4694	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4695
<>	144:ef7eb2e8f9f7	4696	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	4697	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	4698
<>	144:ef7eb2e8f9f7	4699	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4700	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4701	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4702	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4703
<>	144:ef7eb2e8f9f7	4704	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	4705	tmpccmrx = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	4706
<>	144:ef7eb2e8f9f7	4707	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4708	tmpccmrx &= ~TIM_CCMR1_OC2M;
<>	144:ef7eb2e8f9f7	4709	tmpccmrx &= ~TIM_CCMR1_CC2S;
<>	144:ef7eb2e8f9f7	4710
<>	144:ef7eb2e8f9f7	4711	/* Select the Output Compare Mode */
AnnaBridge	165:e614a9f1c9e2	4712	tmpccmrx \|= (OC_Config->OCMode << 8U);
<>	144:ef7eb2e8f9f7	4713
<>	144:ef7eb2e8f9f7	4714	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4715	tmpccer &= ~TIM_CCER_CC2P;
<>	144:ef7eb2e8f9f7	4716	/* Set the Output Compare Polarity */
AnnaBridge	165:e614a9f1c9e2	4717	tmpccer \|= (OC_Config->OCPolarity << 4U);
<>	144:ef7eb2e8f9f7	4718
<>	144:ef7eb2e8f9f7	4719	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
<>	144:ef7eb2e8f9f7	4720	{
<>	144:ef7eb2e8f9f7	4721	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<>	144:ef7eb2e8f9f7	4722
<>	144:ef7eb2e8f9f7	4723	/* Reset the Output N Polarity level */
<>	144:ef7eb2e8f9f7	4724	tmpccer &= ~TIM_CCER_CC2NP;
<>	144:ef7eb2e8f9f7	4725	/* Set the Output N Polarity */
AnnaBridge	165:e614a9f1c9e2	4726	tmpccer \|= (OC_Config->OCNPolarity << 4U);
<>	144:ef7eb2e8f9f7	4727	/* Reset the Output N State */
<>	144:ef7eb2e8f9f7	4728	tmpccer &= ~TIM_CCER_CC2NE;
<>	144:ef7eb2e8f9f7	4729
<>	144:ef7eb2e8f9f7	4730	}
<>	144:ef7eb2e8f9f7	4731
<>	144:ef7eb2e8f9f7	4732	if(IS_TIM_BREAK_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4733	{
<>	144:ef7eb2e8f9f7	4734	/* Check parameters */
<>	144:ef7eb2e8f9f7	4735	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<>	144:ef7eb2e8f9f7	4736	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<>	144:ef7eb2e8f9f7	4737
<>	144:ef7eb2e8f9f7	4738	/* Reset the Output Compare and Output Compare N IDLE State */
<>	144:ef7eb2e8f9f7	4739	tmpcr2 &= ~TIM_CR2_OIS2;
<>	144:ef7eb2e8f9f7	4740	tmpcr2 &= ~TIM_CR2_OIS2N;
<>	144:ef7eb2e8f9f7	4741	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4742	tmpcr2 \|= (OC_Config->OCIdleState << 2);
<>	144:ef7eb2e8f9f7	4743	/* Set the Output N Idle state */
<>	144:ef7eb2e8f9f7	4744	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
<>	144:ef7eb2e8f9f7	4745	}
<>	144:ef7eb2e8f9f7	4746
<>	144:ef7eb2e8f9f7	4747	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4748	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4749
<>	144:ef7eb2e8f9f7	4750	/* Write to TIMx CCMR1 */
<>	144:ef7eb2e8f9f7	4751	TIMx->CCMR1 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4752
<>	144:ef7eb2e8f9f7	4753	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4754	TIMx->CCR2 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4755
<>	144:ef7eb2e8f9f7	4756	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4757	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4758	}
<>	144:ef7eb2e8f9f7	4759
<>	144:ef7eb2e8f9f7	4760	/**
<>	144:ef7eb2e8f9f7	4761	* @brief Time Ouput Compare 3 configuration
<>	144:ef7eb2e8f9f7	4762	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4763	* @param OC_Config : The ouput configuration structure
<>	144:ef7eb2e8f9f7	4764	* @retval None
<>	144:ef7eb2e8f9f7	4765	*/
<>	144:ef7eb2e8f9f7	4766	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4767	{
AnnaBridge	165:e614a9f1c9e2	4768	uint32_t tmpccmrx = 0U;
AnnaBridge	165:e614a9f1c9e2	4769	uint32_t tmpccer = 0U;
AnnaBridge	165:e614a9f1c9e2	4770	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4771
<>	144:ef7eb2e8f9f7	4772	/* Disable the Channel 3: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	4773	TIMx->CCER &= ~TIM_CCER_CC3E;
<>	144:ef7eb2e8f9f7	4774
<>	144:ef7eb2e8f9f7	4775	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4776	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4777	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4778	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4779
<>	144:ef7eb2e8f9f7	4780	/* Get the TIMx CCMR2 register value */
<>	144:ef7eb2e8f9f7	4781	tmpccmrx = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	4782
<>	144:ef7eb2e8f9f7	4783	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4784	tmpccmrx &= ~TIM_CCMR2_OC3M;
<>	144:ef7eb2e8f9f7	4785	tmpccmrx &= ~TIM_CCMR2_CC3S;
<>	144:ef7eb2e8f9f7	4786	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	4787	tmpccmrx \|= OC_Config->OCMode;
<>	144:ef7eb2e8f9f7	4788
<>	144:ef7eb2e8f9f7	4789	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4790	tmpccer &= ~TIM_CCER_CC3P;
<>	144:ef7eb2e8f9f7	4791	/* Set the Output Compare Polarity */
AnnaBridge	165:e614a9f1c9e2	4792	tmpccer \|= (OC_Config->OCPolarity << 8U);
<>	144:ef7eb2e8f9f7	4793
<>	144:ef7eb2e8f9f7	4794	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
<>	144:ef7eb2e8f9f7	4795	{
<>	144:ef7eb2e8f9f7	4796	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<>	144:ef7eb2e8f9f7	4797
<>	144:ef7eb2e8f9f7	4798	/* Reset the Output N Polarity level */
<>	144:ef7eb2e8f9f7	4799	tmpccer &= ~TIM_CCER_CC3NP;
<>	144:ef7eb2e8f9f7	4800	/* Set the Output N Polarity */
AnnaBridge	165:e614a9f1c9e2	4801	tmpccer \|= (OC_Config->OCNPolarity << 8U);
<>	144:ef7eb2e8f9f7	4802	/* Reset the Output N State */
<>	144:ef7eb2e8f9f7	4803	tmpccer &= ~TIM_CCER_CC3NE;
<>	144:ef7eb2e8f9f7	4804	}
<>	144:ef7eb2e8f9f7	4805
<>	144:ef7eb2e8f9f7	4806	if(IS_TIM_BREAK_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4807	{
<>	144:ef7eb2e8f9f7	4808	/* Check parameters */
<>	144:ef7eb2e8f9f7	4809	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<>	144:ef7eb2e8f9f7	4810	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<>	144:ef7eb2e8f9f7	4811
<>	144:ef7eb2e8f9f7	4812	/* Reset the Output Compare and Output Compare N IDLE State */
<>	144:ef7eb2e8f9f7	4813	tmpcr2 &= ~TIM_CR2_OIS3;
<>	144:ef7eb2e8f9f7	4814	tmpcr2 &= ~TIM_CR2_OIS3N;
<>	144:ef7eb2e8f9f7	4815	/* Set the Output Idle state */
AnnaBridge	165:e614a9f1c9e2	4816	tmpcr2 \|= (OC_Config->OCIdleState << 4U);
<>	144:ef7eb2e8f9f7	4817	/* Set the Output N Idle state */
AnnaBridge	165:e614a9f1c9e2	4818	tmpcr2 \|= (OC_Config->OCNIdleState << 4U);
<>	144:ef7eb2e8f9f7	4819	}
<>	144:ef7eb2e8f9f7	4820
<>	144:ef7eb2e8f9f7	4821	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4822	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4823
<>	144:ef7eb2e8f9f7	4824	/* Write to TIMx CCMR2 */
<>	144:ef7eb2e8f9f7	4825	TIMx->CCMR2 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4826
<>	144:ef7eb2e8f9f7	4827	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4828	TIMx->CCR3 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4829
<>	144:ef7eb2e8f9f7	4830	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4831	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4832	}
<>	144:ef7eb2e8f9f7	4833
<>	144:ef7eb2e8f9f7	4834	/**
<>	144:ef7eb2e8f9f7	4835	* @brief Time Ouput Compare 4 configuration
<>	144:ef7eb2e8f9f7	4836	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	4837	* @param OC_Config : The ouput configuration structure
<>	144:ef7eb2e8f9f7	4838	* @retval None
<>	144:ef7eb2e8f9f7	4839	*/
<>	144:ef7eb2e8f9f7	4840	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
<>	144:ef7eb2e8f9f7	4841	{
AnnaBridge	165:e614a9f1c9e2	4842	uint32_t tmpccmrx = 0U;
AnnaBridge	165:e614a9f1c9e2	4843	uint32_t tmpccer = 0U;
AnnaBridge	165:e614a9f1c9e2	4844	uint32_t tmpcr2 = 0U;
<>	144:ef7eb2e8f9f7	4845
<>	144:ef7eb2e8f9f7	4846	/* Disable the Channel 4: Reset the CC4E Bit */
<>	144:ef7eb2e8f9f7	4847	TIMx->CCER &= ~TIM_CCER_CC4E;
<>	144:ef7eb2e8f9f7	4848
<>	144:ef7eb2e8f9f7	4849	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	4850	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	4851	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	4852	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	4853
<>	144:ef7eb2e8f9f7	4854	/* Get the TIMx CCMR2 register value */
<>	144:ef7eb2e8f9f7	4855	tmpccmrx = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	4856
<>	144:ef7eb2e8f9f7	4857	/* Reset the Output Compare mode and Capture/Compare selection Bits */
<>	144:ef7eb2e8f9f7	4858	tmpccmrx &= ~TIM_CCMR2_OC4M;
<>	144:ef7eb2e8f9f7	4859	tmpccmrx &= ~TIM_CCMR2_CC4S;
<>	144:ef7eb2e8f9f7	4860
<>	144:ef7eb2e8f9f7	4861	/* Select the Output Compare Mode */
AnnaBridge	165:e614a9f1c9e2	4862	tmpccmrx \|= (OC_Config->OCMode << 8U);
<>	144:ef7eb2e8f9f7	4863
<>	144:ef7eb2e8f9f7	4864	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	4865	tmpccer &= ~TIM_CCER_CC4P;
<>	144:ef7eb2e8f9f7	4866	/* Set the Output Compare Polarity */
AnnaBridge	165:e614a9f1c9e2	4867	tmpccer \|= (OC_Config->OCPolarity << 12U);
<>	144:ef7eb2e8f9f7	4868
<>	144:ef7eb2e8f9f7	4869	if(IS_TIM_BREAK_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	4870	{
<>	144:ef7eb2e8f9f7	4871	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<>	144:ef7eb2e8f9f7	4872
<>	144:ef7eb2e8f9f7	4873	/* Reset the Output Compare IDLE State */
<>	144:ef7eb2e8f9f7	4874	tmpcr2 &= ~TIM_CR2_OIS4;
<>	144:ef7eb2e8f9f7	4875	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	4876	tmpcr2 \|= (OC_Config->OCIdleState << 6);
<>	144:ef7eb2e8f9f7	4877	}
<>	144:ef7eb2e8f9f7	4878
<>	144:ef7eb2e8f9f7	4879	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	4880	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	4881
<>	144:ef7eb2e8f9f7	4882	/* Write to TIMx CCMR2 */
<>	144:ef7eb2e8f9f7	4883	TIMx->CCMR2 = tmpccmrx;
<>	144:ef7eb2e8f9f7	4884
<>	144:ef7eb2e8f9f7	4885	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	4886	TIMx->CCR4 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	4887
<>	144:ef7eb2e8f9f7	4888	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	4889	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4890	}
<>	144:ef7eb2e8f9f7	4891
<>	144:ef7eb2e8f9f7	4892
<>	144:ef7eb2e8f9f7	4893	/**
<>	144:ef7eb2e8f9f7	4894	* @brief Time Slave configuration
<>	144:ef7eb2e8f9f7	4895	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4896	* the configuration information for TIM module.
<>	144:ef7eb2e8f9f7	4897	* @param sSlaveConfig: The slave configuration structure
<>	144:ef7eb2e8f9f7	4898	* @retval None
<>	144:ef7eb2e8f9f7	4899	*/
<>	144:ef7eb2e8f9f7	4900	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	4901	TIM_SlaveConfigTypeDef * sSlaveConfig)
<>	144:ef7eb2e8f9f7	4902	{
AnnaBridge	165:e614a9f1c9e2	4903	uint32_t tmpsmcr = 0U;
AnnaBridge	165:e614a9f1c9e2	4904	uint32_t tmpccmr1 = 0U;
AnnaBridge	165:e614a9f1c9e2	4905	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	4906
<>	144:ef7eb2e8f9f7	4907	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	4908	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	4909
<>	144:ef7eb2e8f9f7	4910	/* Reset the Trigger Selection Bits */
<>	144:ef7eb2e8f9f7	4911	tmpsmcr &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	4912	/* Set the Input Trigger source */
<>	144:ef7eb2e8f9f7	4913	tmpsmcr \|= sSlaveConfig->InputTrigger;
<>	144:ef7eb2e8f9f7	4914
<>	144:ef7eb2e8f9f7	4915	/* Reset the slave mode Bits */
<>	144:ef7eb2e8f9f7	4916	tmpsmcr &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	4917	/* Set the slave mode */
<>	144:ef7eb2e8f9f7	4918	tmpsmcr \|= sSlaveConfig->SlaveMode;
<>	144:ef7eb2e8f9f7	4919
<>	144:ef7eb2e8f9f7	4920	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	4921	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	4922
<>	144:ef7eb2e8f9f7	4923	/* Configure the trigger prescaler, filter, and polarity */
<>	144:ef7eb2e8f9f7	4924	switch (sSlaveConfig->InputTrigger)
<>	144:ef7eb2e8f9f7	4925	{
<>	144:ef7eb2e8f9f7	4926	case TIM_TS_ETRF:
<>	144:ef7eb2e8f9f7	4927	{
<>	144:ef7eb2e8f9f7	4928	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4929	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4930	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<>	144:ef7eb2e8f9f7	4931	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	4932	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	4933	/* Configure the ETR Trigger source */
<>	144:ef7eb2e8f9f7	4934	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	4935	sSlaveConfig->TriggerPrescaler,
<>	144:ef7eb2e8f9f7	4936	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	4937	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	4938	}
<>	144:ef7eb2e8f9f7	4939	break;
<>	144:ef7eb2e8f9f7	4940
<>	144:ef7eb2e8f9f7	4941	case TIM_TS_TI1F_ED:
<>	144:ef7eb2e8f9f7	4942	{
<>	144:ef7eb2e8f9f7	4943	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4944	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4945	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	4946
<>	144:ef7eb2e8f9f7	4947	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	4948	tmpccer = htim->Instance->CCER;
<>	144:ef7eb2e8f9f7	4949	htim->Instance->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	4950	tmpccmr1 = htim->Instance->CCMR1;
<>	144:ef7eb2e8f9f7	4951
<>	144:ef7eb2e8f9f7	4952	/* Set the filter */
<>	144:ef7eb2e8f9f7	4953	tmpccmr1 &= ~TIM_CCMR1_IC1F;
AnnaBridge	165:e614a9f1c9e2	4954	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4U);
<>	144:ef7eb2e8f9f7	4955
<>	144:ef7eb2e8f9f7	4956	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	4957	htim->Instance->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	4958	htim->Instance->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	4959
<>	144:ef7eb2e8f9f7	4960	}
<>	144:ef7eb2e8f9f7	4961	break;
<>	144:ef7eb2e8f9f7	4962
<>	144:ef7eb2e8f9f7	4963	case TIM_TS_TI1FP1:
<>	144:ef7eb2e8f9f7	4964	{
<>	144:ef7eb2e8f9f7	4965	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4966	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4967	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	4968	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	4969
<>	144:ef7eb2e8f9f7	4970	/* Configure TI1 Filter and Polarity */
<>	144:ef7eb2e8f9f7	4971	TIM_TI1_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4972	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	4973	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	4974	}
<>	144:ef7eb2e8f9f7	4975	break;
<>	144:ef7eb2e8f9f7	4976
<>	144:ef7eb2e8f9f7	4977	case TIM_TS_TI2FP2:
<>	144:ef7eb2e8f9f7	4978	{
<>	144:ef7eb2e8f9f7	4979	/* Check the parameters */
<>	144:ef7eb2e8f9f7	4980	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4981	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<>	144:ef7eb2e8f9f7	4982	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<>	144:ef7eb2e8f9f7	4983
<>	144:ef7eb2e8f9f7	4984	/* Configure TI2 Filter and Polarity */
<>	144:ef7eb2e8f9f7	4985	TIM_TI2_ConfigInputStage(htim->Instance,
<>	144:ef7eb2e8f9f7	4986	sSlaveConfig->TriggerPolarity,
<>	144:ef7eb2e8f9f7	4987	sSlaveConfig->TriggerFilter);
<>	144:ef7eb2e8f9f7	4988	}
<>	144:ef7eb2e8f9f7	4989	break;
<>	144:ef7eb2e8f9f7	4990
<>	144:ef7eb2e8f9f7	4991	case TIM_TS_ITR0:
<>	144:ef7eb2e8f9f7	4992	{
<>	144:ef7eb2e8f9f7	4993	/* Check the parameter */
<>	144:ef7eb2e8f9f7	4994	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	4995	}
<>	144:ef7eb2e8f9f7	4996	break;
<>	144:ef7eb2e8f9f7	4997
<>	144:ef7eb2e8f9f7	4998	case TIM_TS_ITR1:
<>	144:ef7eb2e8f9f7	4999	{
<>	144:ef7eb2e8f9f7	5000	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5001	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5002	}
<>	144:ef7eb2e8f9f7	5003	break;
<>	144:ef7eb2e8f9f7	5004
<>	144:ef7eb2e8f9f7	5005	case TIM_TS_ITR2:
<>	144:ef7eb2e8f9f7	5006	{
<>	144:ef7eb2e8f9f7	5007	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5008	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5009	}
<>	144:ef7eb2e8f9f7	5010	break;
<>	144:ef7eb2e8f9f7	5011
<>	144:ef7eb2e8f9f7	5012	case TIM_TS_ITR3:
<>	144:ef7eb2e8f9f7	5013	{
<>	144:ef7eb2e8f9f7	5014	/* Check the parameter */
<>	144:ef7eb2e8f9f7	5015	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	5016	}
<>	144:ef7eb2e8f9f7	5017	break;
<>	144:ef7eb2e8f9f7	5018
<>	144:ef7eb2e8f9f7	5019	default:
<>	144:ef7eb2e8f9f7	5020	break;
<>	144:ef7eb2e8f9f7	5021	}
<>	144:ef7eb2e8f9f7	5022	}
<>	144:ef7eb2e8f9f7	5023
<>	144:ef7eb2e8f9f7	5024	/**
<>	144:ef7eb2e8f9f7	5025	* @brief Configure the TI1 as Input.
<>	144:ef7eb2e8f9f7	5026	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	5027	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5028	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5029	* @arg TIM_ICPOLARITY_RISING
<>	144:ef7eb2e8f9f7	5030	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5031	* @param TIM_ICSelection : specifies the input to be used.
<>	144:ef7eb2e8f9f7	5032	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5033	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
<>	144:ef7eb2e8f9f7	5034	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
<>	144:ef7eb2e8f9f7	5035	* @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5036	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5037	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5038	* @retval None
<>	144:ef7eb2e8f9f7	5039	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
<>	144:ef7eb2e8f9f7	5040	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
<>	144:ef7eb2e8f9f7	5041	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5042	*/
<>	144:ef7eb2e8f9f7	5043	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5044	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5045	{
AnnaBridge	165:e614a9f1c9e2	5046	uint32_t tmpccmr1 = 0U;
AnnaBridge	165:e614a9f1c9e2	5047	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5048
<>	144:ef7eb2e8f9f7	5049	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	5050	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	5051	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5052	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5053
<>	144:ef7eb2e8f9f7	5054	/* Select the Input */
<>	144:ef7eb2e8f9f7	5055	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<>	144:ef7eb2e8f9f7	5056	{
<>	144:ef7eb2e8f9f7	5057	tmpccmr1 &= ~TIM_CCMR1_CC1S;
<>	144:ef7eb2e8f9f7	5058	tmpccmr1 \|= TIM_ICSelection;
<>	144:ef7eb2e8f9f7	5059	}
<>	144:ef7eb2e8f9f7	5060	else
<>	144:ef7eb2e8f9f7	5061	{
<>	144:ef7eb2e8f9f7	5062	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
<>	144:ef7eb2e8f9f7	5063	}
<>	144:ef7eb2e8f9f7	5064
<>	144:ef7eb2e8f9f7	5065	/* Set the filter */
<>	144:ef7eb2e8f9f7	5066	tmpccmr1 &= ~TIM_CCMR1_IC1F;
AnnaBridge	165:e614a9f1c9e2	5067	tmpccmr1 \|= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
<>	144:ef7eb2e8f9f7	5068
<>	144:ef7eb2e8f9f7	5069	/* Select the Polarity and set the CC1E Bit */
<>	144:ef7eb2e8f9f7	5070	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
<>	144:ef7eb2e8f9f7	5071	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
<>	144:ef7eb2e8f9f7	5072
<>	144:ef7eb2e8f9f7	5073	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5074	TIMx->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	5075	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5076	}
<>	144:ef7eb2e8f9f7	5077
<>	144:ef7eb2e8f9f7	5078	/**
<>	144:ef7eb2e8f9f7	5079	* @brief Configure the Polarity and Filter for TI1.
<>	144:ef7eb2e8f9f7	5080	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	5081	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5082	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5083	* @arg TIM_ICPOLARITY_RISING
AnnaBridge	165:e614a9f1c9e2	5084	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5085	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5086	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5087	* @retval None
<>	144:ef7eb2e8f9f7	5088	*/
<>	144:ef7eb2e8f9f7	5089	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5090	{
AnnaBridge	165:e614a9f1c9e2	5091	uint32_t tmpccmr1 = 0U;
AnnaBridge	165:e614a9f1c9e2	5092	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5093
<>	144:ef7eb2e8f9f7	5094	/* Disable the Channel 1: Reset the CC1E Bit */
<>	144:ef7eb2e8f9f7	5095	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5096	TIMx->CCER &= ~TIM_CCER_CC1E;
<>	144:ef7eb2e8f9f7	5097	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5098
<>	144:ef7eb2e8f9f7	5099	/* Set the filter */
<>	144:ef7eb2e8f9f7	5100	tmpccmr1 &= ~TIM_CCMR1_IC1F;
AnnaBridge	165:e614a9f1c9e2	5101	tmpccmr1 \|= (TIM_ICFilter << 4U);
<>	144:ef7eb2e8f9f7	5102
<>	144:ef7eb2e8f9f7	5103	/* Select the Polarity and set the CC1E Bit */
<>	144:ef7eb2e8f9f7	5104	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
<>	144:ef7eb2e8f9f7	5105	tmpccer \|= TIM_ICPolarity;
<>	144:ef7eb2e8f9f7	5106
<>	144:ef7eb2e8f9f7	5107	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5108	TIMx->CCMR1 = tmpccmr1;
<>	144:ef7eb2e8f9f7	5109	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5110	}
<>	144:ef7eb2e8f9f7	5111
<>	144:ef7eb2e8f9f7	5112	/**
<>	144:ef7eb2e8f9f7	5113	* @brief Configure the TI2 as Input.
<>	144:ef7eb2e8f9f7	5114	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5115	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5116	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5117	* @arg TIM_ICPOLARITY_RISING
AnnaBridge	165:e614a9f1c9e2	5118	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5119	* @param TIM_ICSelection : specifies the input to be used.
<>	144:ef7eb2e8f9f7	5120	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5121	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
<>	144:ef7eb2e8f9f7	5122	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
<>	144:ef7eb2e8f9f7	5123	* @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5124	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5125	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5126	* @retval None
<>	144:ef7eb2e8f9f7	5127	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
<>	144:ef7eb2e8f9f7	5128	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
<>	144:ef7eb2e8f9f7	5129	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5130	*/
<>	144:ef7eb2e8f9f7	5131	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5132	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5133	{
AnnaBridge	165:e614a9f1c9e2	5134	uint32_t tmpccmr1 = 0U;
AnnaBridge	165:e614a9f1c9e2	5135	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5136
<>	144:ef7eb2e8f9f7	5137	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	5138	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	5139	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5140	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5141
<>	144:ef7eb2e8f9f7	5142	/* Select the Input */
<>	144:ef7eb2e8f9f7	5143	tmpccmr1 &= ~TIM_CCMR1_CC2S;
AnnaBridge	165:e614a9f1c9e2	5144	tmpccmr1 \|= (TIM_ICSelection << 8U);
<>	144:ef7eb2e8f9f7	5145
<>	144:ef7eb2e8f9f7	5146	/* Set the filter */
<>	144:ef7eb2e8f9f7	5147	tmpccmr1 &= ~TIM_CCMR1_IC2F;
AnnaBridge	165:e614a9f1c9e2	5148	tmpccmr1 \|= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
<>	144:ef7eb2e8f9f7	5149
<>	144:ef7eb2e8f9f7	5150	/* Select the Polarity and set the CC2E Bit */
<>	144:ef7eb2e8f9f7	5151	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
AnnaBridge	165:e614a9f1c9e2	5152	tmpccer \|= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
<>	144:ef7eb2e8f9f7	5153
<>	144:ef7eb2e8f9f7	5154	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5155	TIMx->CCMR1 = tmpccmr1 ;
<>	144:ef7eb2e8f9f7	5156	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5157	}
<>	144:ef7eb2e8f9f7	5158
<>	144:ef7eb2e8f9f7	5159	/**
<>	144:ef7eb2e8f9f7	5160	* @brief Configure the Polarity and Filter for TI2.
<>	144:ef7eb2e8f9f7	5161	* @param TIMx to select the TIM peripheral.
<>	144:ef7eb2e8f9f7	5162	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5163	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5164	* @arg TIM_ICPOLARITY_RISING
AnnaBridge	165:e614a9f1c9e2	5165	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5166	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5167	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5168	* @retval None
<>	144:ef7eb2e8f9f7	5169	*/
<>	144:ef7eb2e8f9f7	5170	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5171	{
AnnaBridge	165:e614a9f1c9e2	5172	uint32_t tmpccmr1 = 0U;
AnnaBridge	165:e614a9f1c9e2	5173	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5174
<>	144:ef7eb2e8f9f7	5175	/* Disable the Channel 2: Reset the CC2E Bit */
<>	144:ef7eb2e8f9f7	5176	TIMx->CCER &= ~TIM_CCER_CC2E;
<>	144:ef7eb2e8f9f7	5177	tmpccmr1 = TIMx->CCMR1;
<>	144:ef7eb2e8f9f7	5178	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5179
<>	144:ef7eb2e8f9f7	5180	/* Set the filter */
<>	144:ef7eb2e8f9f7	5181	tmpccmr1 &= ~TIM_CCMR1_IC2F;
AnnaBridge	165:e614a9f1c9e2	5182	tmpccmr1 \|= (TIM_ICFilter << 12U);
<>	144:ef7eb2e8f9f7	5183
<>	144:ef7eb2e8f9f7	5184	/* Select the Polarity and set the CC2E Bit */
<>	144:ef7eb2e8f9f7	5185	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
AnnaBridge	165:e614a9f1c9e2	5186	tmpccer \|= (TIM_ICPolarity << 4U);
<>	144:ef7eb2e8f9f7	5187
<>	144:ef7eb2e8f9f7	5188	/* Write to TIMx CCMR1 and CCER registers */
<>	144:ef7eb2e8f9f7	5189	TIMx->CCMR1 = tmpccmr1 ;
<>	144:ef7eb2e8f9f7	5190	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5191	}
<>	144:ef7eb2e8f9f7	5192
<>	144:ef7eb2e8f9f7	5193	/**
<>	144:ef7eb2e8f9f7	5194	* @brief Configure the TI3 as Input.
<>	144:ef7eb2e8f9f7	5195	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5196	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5197	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5198	* @arg TIM_ICPOLARITY_RISING
AnnaBridge	165:e614a9f1c9e2	5199	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5200	* @param TIM_ICSelection : specifies the input to be used.
<>	144:ef7eb2e8f9f7	5201	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5202	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
<>	144:ef7eb2e8f9f7	5203	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
<>	144:ef7eb2e8f9f7	5204	* @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5205	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5206	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5207	* @retval None
<>	144:ef7eb2e8f9f7	5208	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
<>	144:ef7eb2e8f9f7	5209	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<>	144:ef7eb2e8f9f7	5210	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5211	*/
<>	144:ef7eb2e8f9f7	5212	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5213	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5214	{
AnnaBridge	165:e614a9f1c9e2	5215	uint32_t tmpccmr2 = 0U;
AnnaBridge	165:e614a9f1c9e2	5216	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5217
<>	144:ef7eb2e8f9f7	5218	/* Disable the Channel 3: Reset the CC3E Bit */
<>	144:ef7eb2e8f9f7	5219	TIMx->CCER &= ~TIM_CCER_CC3E;
<>	144:ef7eb2e8f9f7	5220	tmpccmr2 = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	5221	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5222
<>	144:ef7eb2e8f9f7	5223	/* Select the Input */
<>	144:ef7eb2e8f9f7	5224	tmpccmr2 &= ~TIM_CCMR2_CC3S;
<>	144:ef7eb2e8f9f7	5225	tmpccmr2 \|= TIM_ICSelection;
<>	144:ef7eb2e8f9f7	5226
<>	144:ef7eb2e8f9f7	5227	/* Set the filter */
<>	144:ef7eb2e8f9f7	5228	tmpccmr2 &= ~TIM_CCMR2_IC3F;
AnnaBridge	165:e614a9f1c9e2	5229	tmpccmr2 \|= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
<>	144:ef7eb2e8f9f7	5230
<>	144:ef7eb2e8f9f7	5231	/* Select the Polarity and set the CC3E Bit */
<>	144:ef7eb2e8f9f7	5232	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
AnnaBridge	165:e614a9f1c9e2	5233	tmpccer \|= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
<>	144:ef7eb2e8f9f7	5234
<>	144:ef7eb2e8f9f7	5235	/* Write to TIMx CCMR2 and CCER registers */
<>	144:ef7eb2e8f9f7	5236	TIMx->CCMR2 = tmpccmr2;
<>	144:ef7eb2e8f9f7	5237	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	5238	}
<>	144:ef7eb2e8f9f7	5239
<>	144:ef7eb2e8f9f7	5240	/**
<>	144:ef7eb2e8f9f7	5241	* @brief Configure the TI4 as Input.
<>	144:ef7eb2e8f9f7	5242	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5243	* @param TIM_ICPolarity : The Input Polarity.
<>	144:ef7eb2e8f9f7	5244	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5245	* @arg TIM_ICPOLARITY_RISING
AnnaBridge	165:e614a9f1c9e2	5246	* @arg TIM_ICPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	5247	* @param TIM_ICSelection : specifies the input to be used.
<>	144:ef7eb2e8f9f7	5248	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5249	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
<>	144:ef7eb2e8f9f7	5250	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
<>	144:ef7eb2e8f9f7	5251	* @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
<>	144:ef7eb2e8f9f7	5252	* @param TIM_ICFilter : Specifies the Input Capture Filter.
<>	144:ef7eb2e8f9f7	5253	* This parameter must be a value between 0x00 and 0x0F.
<>	144:ef7eb2e8f9f7	5254	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
<>	144:ef7eb2e8f9f7	5255	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<>	144:ef7eb2e8f9f7	5256	* protected against un-initialized filter and polarity values.
<>	144:ef7eb2e8f9f7	5257	* @retval None
<>	144:ef7eb2e8f9f7	5258	*/
<>	144:ef7eb2e8f9f7	5259	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<>	144:ef7eb2e8f9f7	5260	uint32_t TIM_ICFilter)
<>	144:ef7eb2e8f9f7	5261	{
AnnaBridge	165:e614a9f1c9e2	5262	uint32_t tmpccmr2 = 0U;
AnnaBridge	165:e614a9f1c9e2	5263	uint32_t tmpccer = 0U;
<>	144:ef7eb2e8f9f7	5264
<>	144:ef7eb2e8f9f7	5265	/* Disable the Channel 4: Reset the CC4E Bit */
<>	144:ef7eb2e8f9f7	5266	TIMx->CCER &= ~TIM_CCER_CC4E;
<>	144:ef7eb2e8f9f7	5267	tmpccmr2 = TIMx->CCMR2;
<>	144:ef7eb2e8f9f7	5268	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	5269
<>	144:ef7eb2e8f9f7	5270	/* Select the Input */
<>	144:ef7eb2e8f9f7	5271	tmpccmr2 &= ~TIM_CCMR2_CC4S;
AnnaBridge	165:e614a9f1c9e2	5272	tmpccmr2 \|= (TIM_ICSelection << 8U);
<>	144:ef7eb2e8f9f7	5273
<>	144:ef7eb2e8f9f7	5274	/* Set the filter */
<>	144:ef7eb2e8f9f7	5275	tmpccmr2 &= ~TIM_CCMR2_IC4F;
AnnaBridge	165:e614a9f1c9e2	5276	tmpccmr2 \|= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
<>	144:ef7eb2e8f9f7	5277
<>	144:ef7eb2e8f9f7	5278	/* Select the Polarity and set the CC4E Bit */
AnnaBridge	165:e614a9f1c9e2	5279	tmpccer &= ~TIM_CCER_CC4P;
AnnaBridge	165:e614a9f1c9e2	5280	tmpccer \|= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
<>	144:ef7eb2e8f9f7	5281
<>	144:ef7eb2e8f9f7	5282	/* Write to TIMx CCMR2 and CCER registers */
<>	144:ef7eb2e8f9f7	5283	TIMx->CCMR2 = tmpccmr2;
<>	144:ef7eb2e8f9f7	5284	TIMx->CCER = tmpccer ;
<>	144:ef7eb2e8f9f7	5285	}
<>	144:ef7eb2e8f9f7	5286
<>	144:ef7eb2e8f9f7	5287	/**
<>	144:ef7eb2e8f9f7	5288	* @brief Selects the Input Trigger source
<>	144:ef7eb2e8f9f7	5289	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5290	* @param InputTriggerSource : The Input Trigger source.
<>	144:ef7eb2e8f9f7	5291	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5292	* @arg TIM_TS_ITR0 : Internal Trigger 0
<>	144:ef7eb2e8f9f7	5293	* @arg TIM_TS_ITR1 : Internal Trigger 1
<>	144:ef7eb2e8f9f7	5294	* @arg TIM_TS_ITR2 : Internal Trigger 2
<>	144:ef7eb2e8f9f7	5295	* @arg TIM_TS_ITR3 : Internal Trigger 3
<>	144:ef7eb2e8f9f7	5296	* @arg TIM_TS_TI1F_ED : TI1 Edge Detector
<>	144:ef7eb2e8f9f7	5297	* @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
<>	144:ef7eb2e8f9f7	5298	* @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
<>	144:ef7eb2e8f9f7	5299	* @arg TIM_TS_ETRF : External Trigger input
<>	144:ef7eb2e8f9f7	5300	* @retval None
<>	144:ef7eb2e8f9f7	5301	*/
<>	144:ef7eb2e8f9f7	5302	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
<>	144:ef7eb2e8f9f7	5303	{
AnnaBridge	165:e614a9f1c9e2	5304	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	5305
<>	144:ef7eb2e8f9f7	5306	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	5307	tmpsmcr = TIMx->SMCR;
<>	144:ef7eb2e8f9f7	5308	/* Reset the TS Bits */
<>	144:ef7eb2e8f9f7	5309	tmpsmcr &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	5310	/* Set the Input Trigger source and the slave mode*/
<>	144:ef7eb2e8f9f7	5311	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
<>	144:ef7eb2e8f9f7	5312	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	5313	TIMx->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	5314	}
<>	144:ef7eb2e8f9f7	5315	/**
<>	144:ef7eb2e8f9f7	5316	* @brief Configures the TIMx External Trigger (ETR).
<>	144:ef7eb2e8f9f7	5317	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5318	* @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
<>	144:ef7eb2e8f9f7	5319	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5320	* @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
<>	144:ef7eb2e8f9f7	5321	* @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
<>	144:ef7eb2e8f9f7	5322	* @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
<>	144:ef7eb2e8f9f7	5323	* @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
<>	144:ef7eb2e8f9f7	5324	* @param TIM_ExtTRGPolarity : The external Trigger Polarity.
<>	144:ef7eb2e8f9f7	5325	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5326	* @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
<>	144:ef7eb2e8f9f7	5327	* @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
<>	144:ef7eb2e8f9f7	5328	* @param ExtTRGFilter : External Trigger Filter.
<>	144:ef7eb2e8f9f7	5329	* This parameter must be a value between 0x00 and 0x0F
<>	144:ef7eb2e8f9f7	5330	* @retval None
<>	144:ef7eb2e8f9f7	5331	*/
<>	144:ef7eb2e8f9f7	5332	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<>	144:ef7eb2e8f9f7	5333	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<>	144:ef7eb2e8f9f7	5334	{
AnnaBridge	165:e614a9f1c9e2	5335	uint32_t tmpsmcr = 0U;
<>	144:ef7eb2e8f9f7	5336
<>	144:ef7eb2e8f9f7	5337	tmpsmcr = TIMx->SMCR;
<>	144:ef7eb2e8f9f7	5338
<>	144:ef7eb2e8f9f7	5339	/* Reset the ETR Bits */
<>	144:ef7eb2e8f9f7	5340	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	5341
<>	144:ef7eb2e8f9f7	5342	/* Set the Prescaler, the Filter value and the Polarity */
AnnaBridge	165:e614a9f1c9e2	5343	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8U)));
<>	144:ef7eb2e8f9f7	5344
<>	144:ef7eb2e8f9f7	5345	/* Write to TIMx SMCR */
<>	144:ef7eb2e8f9f7	5346	TIMx->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	5347	}
<>	144:ef7eb2e8f9f7	5348
<>	144:ef7eb2e8f9f7	5349	/**
<>	144:ef7eb2e8f9f7	5350	* @brief Enables or disables the TIM Capture Compare Channel x.
<>	144:ef7eb2e8f9f7	5351	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	5352	* @param Channel : specifies the TIM Channel
<>	144:ef7eb2e8f9f7	5353	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	5354	* @arg TIM_CHANNEL_1: TIM Channel 1
<>	144:ef7eb2e8f9f7	5355	* @arg TIM_CHANNEL_2: TIM Channel 2
<>	144:ef7eb2e8f9f7	5356	* @arg TIM_CHANNEL_3: TIM Channel 3
<>	144:ef7eb2e8f9f7	5357	* @arg TIM_CHANNEL_4: TIM Channel 4
<>	144:ef7eb2e8f9f7	5358	* @param ChannelState : specifies the TIM Channel CCxE bit new state.
<>	144:ef7eb2e8f9f7	5359	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<>	144:ef7eb2e8f9f7	5360	* @retval None
<>	144:ef7eb2e8f9f7	5361	*/
<>	144:ef7eb2e8f9f7	5362	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<>	144:ef7eb2e8f9f7	5363	{
AnnaBridge	165:e614a9f1c9e2	5364	uint32_t tmp = 0U;
<>	144:ef7eb2e8f9f7	5365
<>	144:ef7eb2e8f9f7	5366	/* Check the parameters */
<>	144:ef7eb2e8f9f7	5367	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<>	144:ef7eb2e8f9f7	5368	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	5369
<>	144:ef7eb2e8f9f7	5370	tmp = TIM_CCER_CC1E << Channel;
<>	144:ef7eb2e8f9f7	5371
<>	144:ef7eb2e8f9f7	5372	/* Reset the CCxE Bit */
<>	144:ef7eb2e8f9f7	5373	TIMx->CCER &= ~tmp;
<>	144:ef7eb2e8f9f7	5374
<>	144:ef7eb2e8f9f7	5375	/* Set or reset the CCxE Bit */
<>	144:ef7eb2e8f9f7	5376	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
<>	144:ef7eb2e8f9f7	5377	}
<>	144:ef7eb2e8f9f7	5378
<>	144:ef7eb2e8f9f7	5379	/**
<>	144:ef7eb2e8f9f7	5380	* @}
<>	144:ef7eb2e8f9f7	5381	*/
<>	144:ef7eb2e8f9f7	5382
<>	144:ef7eb2e8f9f7	5383	#endif /* HAL_TIM_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	5384	/**
<>	144:ef7eb2e8f9f7	5385	* @}
<>	144:ef7eb2e8f9f7	5386	*/
<>	144:ef7eb2e8f9f7	5387
<>	144:ef7eb2e8f9f7	5388	/**
<>	144:ef7eb2e8f9f7	5389	* @}
<>	144:ef7eb2e8f9f7	5390	*/
<>	144:ef7eb2e8f9f7	5391	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/