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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_pwr.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of PWR HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F1xx_HAL_PWR_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F1xx_HAL_PWR_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup PWR
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @defgroup PWR_Exported_Types PWR Exported Types
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief PWR PVD configuration structure definition
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
<> 144:ef7eb2e8f9f7 67 This parameter can be a value of @ref PWR_PVD_detection_level */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref PWR_PVD_Mode */
<> 144:ef7eb2e8f9f7 71 }PWR_PVDTypeDef;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /**
<> 144:ef7eb2e8f9f7 75 * @}
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /* Internal constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /** @addtogroup PWR_Private_Constants
<> 144:ef7eb2e8f9f7 82 * @{
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /**
<> 144:ef7eb2e8f9f7 88 * @}
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /** @defgroup PWR_Exported_Constants PWR Exported Constants
<> 144:ef7eb2e8f9f7 95 * @{
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
<> 144:ef7eb2e8f9f7 102 #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
<> 144:ef7eb2e8f9f7 103 #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
<> 144:ef7eb2e8f9f7 104 #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
<> 144:ef7eb2e8f9f7 105 #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
<> 144:ef7eb2e8f9f7 106 #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
<> 144:ef7eb2e8f9f7 107 #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
<> 144:ef7eb2e8f9f7 108 #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /**
<> 144:ef7eb2e8f9f7 111 * @}
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /** @defgroup PWR_PVD_Mode PWR PVD Mode
<> 144:ef7eb2e8f9f7 115 * @{
<> 144:ef7eb2e8f9f7 116 */
AnnaBridge 165:e614a9f1c9e2 117 #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
AnnaBridge 165:e614a9f1c9e2 118 #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
AnnaBridge 165:e614a9f1c9e2 119 #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
AnnaBridge 165:e614a9f1c9e2 120 #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
AnnaBridge 165:e614a9f1c9e2 121 #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
AnnaBridge 165:e614a9f1c9e2 122 #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
AnnaBridge 165:e614a9f1c9e2 123 #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @}
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /**
<> 144:ef7eb2e8f9f7 137 * @}
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
AnnaBridge 165:e614a9f1c9e2 143 #define PWR_MAINREGULATOR_ON 0x00000000U
<> 144:ef7eb2e8f9f7 144 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /**
<> 144:ef7eb2e8f9f7 147 * @}
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
<> 144:ef7eb2e8f9f7 151 * @{
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
<> 144:ef7eb2e8f9f7 154 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @}
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
<> 144:ef7eb2e8f9f7 164 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /** @defgroup PWR_Flag PWR Flag
<> 144:ef7eb2e8f9f7 171 * @{
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 #define PWR_FLAG_WU PWR_CSR_WUF
<> 144:ef7eb2e8f9f7 174 #define PWR_FLAG_SB PWR_CSR_SBF
<> 144:ef7eb2e8f9f7 175 #define PWR_FLAG_PVDO PWR_CSR_PVDO
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @}
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /**
<> 144:ef7eb2e8f9f7 183 * @}
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 187 /** @defgroup PWR_Exported_Macros PWR Exported Macros
<> 144:ef7eb2e8f9f7 188 * @{
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /** @brief Check PWR flag is set or not.
<> 144:ef7eb2e8f9f7 192 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 193 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 194 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
<> 144:ef7eb2e8f9f7 195 * was received from the WKUP pin or from the RTC alarm
<> 144:ef7eb2e8f9f7 196 * An additional wakeup event is detected if the WKUP pin is enabled
<> 144:ef7eb2e8f9f7 197 * (by setting the EWUP bit) when the WKUP pin level is already high.
<> 144:ef7eb2e8f9f7 198 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
<> 144:ef7eb2e8f9f7 199 * resumed from StandBy mode.
<> 144:ef7eb2e8f9f7 200 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
<> 144:ef7eb2e8f9f7 201 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
<> 144:ef7eb2e8f9f7 202 * For this reason, this bit is equal to 0 after Standby or reset
<> 144:ef7eb2e8f9f7 203 * until the PVDE bit is set.
<> 144:ef7eb2e8f9f7 204 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /** @brief Clear the PWR's pending flags.
<> 144:ef7eb2e8f9f7 209 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 210 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 211 * @arg PWR_FLAG_WU: Wake Up flag
<> 144:ef7eb2e8f9f7 212 * @arg PWR_FLAG_SB: StandBy flag
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /**
<> 144:ef7eb2e8f9f7 217 * @brief Enable interrupt on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 218 * @retval None.
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @brief Disable interrupt on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 224 * @retval None.
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @brief Enable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 230 * @retval None.
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @brief Disable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 236 * @retval None.
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @brief PVD EXTI line configuration: set falling edge trigger.
<> 144:ef7eb2e8f9f7 243 * @retval None.
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @brief Disable the PVD Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 250 * @retval None.
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @brief PVD EXTI line configuration: set rising edge trigger.
<> 144:ef7eb2e8f9f7 257 * @retval None.
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @brief Disable the PVD Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 263 * This parameter can be:
<> 144:ef7eb2e8f9f7 264 * @retval None.
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /**
<> 144:ef7eb2e8f9f7 269 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
<> 144:ef7eb2e8f9f7 270 * @retval None.
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 276 * This parameter can be:
<> 144:ef7eb2e8f9f7 277 * @retval None.
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 285 * @retval EXTI PVD Line Status.
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @brief Clear the PVD EXTI flag.
<> 144:ef7eb2e8f9f7 291 * @retval None.
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 297 * @retval None.
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 305 /** @defgroup PWR_Private_Macros PWR Private Macros
<> 144:ef7eb2e8f9f7 306 * @{
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
<> 144:ef7eb2e8f9f7 309 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
<> 144:ef7eb2e8f9f7 310 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
<> 144:ef7eb2e8f9f7 311 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
<> 144:ef7eb2e8f9f7 315 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
<> 144:ef7eb2e8f9f7 316 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
<> 144:ef7eb2e8f9f7 317 ((MODE) == PWR_PVD_MODE_NORMAL))
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
<> 144:ef7eb2e8f9f7 322 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /**
<> 144:ef7eb2e8f9f7 329 * @}
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
<> 144:ef7eb2e8f9f7 337 * @{
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 341 * @{
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /* Initialization and de-initialization functions *******************************/
<> 144:ef7eb2e8f9f7 345 void HAL_PWR_DeInit(void);
<> 144:ef7eb2e8f9f7 346 void HAL_PWR_EnableBkUpAccess(void);
<> 144:ef7eb2e8f9f7 347 void HAL_PWR_DisableBkUpAccess(void);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @}
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 354 * @{
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 358 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
<> 144:ef7eb2e8f9f7 359 /* #define HAL_PWR_ConfigPVD 12*/
<> 144:ef7eb2e8f9f7 360 void HAL_PWR_EnablePVD(void);
<> 144:ef7eb2e8f9f7 361 void HAL_PWR_DisablePVD(void);
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* WakeUp pins configuration functions ****************************************/
<> 144:ef7eb2e8f9f7 364 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
<> 144:ef7eb2e8f9f7 365 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Low Power modes configuration functions ************************************/
<> 144:ef7eb2e8f9f7 368 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
<> 144:ef7eb2e8f9f7 369 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
<> 144:ef7eb2e8f9f7 370 void HAL_PWR_EnterSTANDBYMode(void);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 void HAL_PWR_EnableSleepOnExit(void);
<> 144:ef7eb2e8f9f7 373 void HAL_PWR_DisableSleepOnExit(void);
<> 144:ef7eb2e8f9f7 374 void HAL_PWR_EnableSEVOnPend(void);
<> 144:ef7eb2e8f9f7 375 void HAL_PWR_DisableSEVOnPend(void);
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 void HAL_PWR_PVD_IRQHandler(void);
<> 144:ef7eb2e8f9f7 380 void HAL_PWR_PVDCallback(void);
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @}
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @}
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @}
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @}
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399 #endif
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 #endif /* __STM32F1xx_HAL_PWR_H */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/