mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 187:0387e8f68319
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f1xx_hal_pwr.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @brief PWR HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 6 | * |
<> | 144:ef7eb2e8f9f7 | 7 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 8 | * functionalities of the Power Controller (PWR) peripheral: |
<> | 144:ef7eb2e8f9f7 | 9 | * + Initialization/de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 10 | * + Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 11 | * |
<> | 144:ef7eb2e8f9f7 | 12 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 13 | * @attention |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 16 | * |
<> | 144:ef7eb2e8f9f7 | 17 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 18 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 19 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 20 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 22 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 23 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 25 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 26 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 27 | * |
<> | 144:ef7eb2e8f9f7 | 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 38 | * |
<> | 144:ef7eb2e8f9f7 | 39 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 40 | */ |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 43 | #include "stm32f1xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 44 | |
<> | 144:ef7eb2e8f9f7 | 45 | /** @addtogroup STM32F1xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 46 | * @{ |
<> | 144:ef7eb2e8f9f7 | 47 | */ |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /** @defgroup PWR PWR |
<> | 144:ef7eb2e8f9f7 | 50 | * @brief PWR HAL module driver |
<> | 144:ef7eb2e8f9f7 | 51 | * @{ |
<> | 144:ef7eb2e8f9f7 | 52 | */ |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | #ifdef HAL_PWR_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 57 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 58 | |
<> | 144:ef7eb2e8f9f7 | 59 | /** @defgroup PWR_Private_Constants PWR Private Constants |
<> | 144:ef7eb2e8f9f7 | 60 | * @{ |
<> | 144:ef7eb2e8f9f7 | 61 | */ |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask |
<> | 144:ef7eb2e8f9f7 | 64 | * @{ |
<> | 144:ef7eb2e8f9f7 | 65 | */ |
AnnaBridge | 165:e614a9f1c9e2 | 66 | #define PVD_MODE_IT 0x00010000U |
AnnaBridge | 165:e614a9f1c9e2 | 67 | #define PVD_MODE_EVT 0x00020000U |
AnnaBridge | 165:e614a9f1c9e2 | 68 | #define PVD_RISING_EDGE 0x00000001U |
AnnaBridge | 165:e614a9f1c9e2 | 69 | #define PVD_FALLING_EDGE 0x00000002U |
<> | 144:ef7eb2e8f9f7 | 70 | /** |
<> | 144:ef7eb2e8f9f7 | 71 | * @} |
<> | 144:ef7eb2e8f9f7 | 72 | */ |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | /** @defgroup PWR_register_alias_address PWR Register alias address |
<> | 144:ef7eb2e8f9f7 | 76 | * @{ |
<> | 144:ef7eb2e8f9f7 | 77 | */ |
<> | 144:ef7eb2e8f9f7 | 78 | /* ------------- PWR registers bit address in the alias region ---------------*/ |
<> | 144:ef7eb2e8f9f7 | 79 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) |
AnnaBridge | 165:e614a9f1c9e2 | 80 | #define PWR_CR_OFFSET 0x00U |
AnnaBridge | 165:e614a9f1c9e2 | 81 | #define PWR_CSR_OFFSET 0x04U |
<> | 144:ef7eb2e8f9f7 | 82 | #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) |
<> | 144:ef7eb2e8f9f7 | 83 | #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) |
<> | 144:ef7eb2e8f9f7 | 84 | /** |
<> | 144:ef7eb2e8f9f7 | 85 | * @} |
<> | 144:ef7eb2e8f9f7 | 86 | */ |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | /** @defgroup PWR_CR_register_alias PWR CR Register alias address |
<> | 144:ef7eb2e8f9f7 | 89 | * @{ |
<> | 144:ef7eb2e8f9f7 | 90 | */ |
<> | 144:ef7eb2e8f9f7 | 91 | /* --- CR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 92 | /* Alias word address of LPSDSR bit */ |
AnnaBridge | 165:e614a9f1c9e2 | 93 | #define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos |
AnnaBridge | 165:e614a9f1c9e2 | 94 | #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) |
<> | 144:ef7eb2e8f9f7 | 95 | |
<> | 144:ef7eb2e8f9f7 | 96 | /* Alias word address of DBP bit */ |
AnnaBridge | 165:e614a9f1c9e2 | 97 | #define DBP_BIT_NUMBER PWR_CR_DBP_Pos |
AnnaBridge | 165:e614a9f1c9e2 | 98 | #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) |
<> | 144:ef7eb2e8f9f7 | 99 | |
<> | 144:ef7eb2e8f9f7 | 100 | /* Alias word address of PVDE bit */ |
AnnaBridge | 165:e614a9f1c9e2 | 101 | #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos |
AnnaBridge | 165:e614a9f1c9e2 | 102 | #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) |
<> | 144:ef7eb2e8f9f7 | 103 | |
<> | 144:ef7eb2e8f9f7 | 104 | /** |
<> | 144:ef7eb2e8f9f7 | 105 | * @} |
<> | 144:ef7eb2e8f9f7 | 106 | */ |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address |
<> | 144:ef7eb2e8f9f7 | 109 | * @{ |
<> | 144:ef7eb2e8f9f7 | 110 | */ |
<> | 144:ef7eb2e8f9f7 | 111 | |
<> | 144:ef7eb2e8f9f7 | 112 | /* --- CSR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 113 | /* Alias word address of EWUP1 bit */ |
AnnaBridge | 165:e614a9f1c9e2 | 114 | #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) |
<> | 144:ef7eb2e8f9f7 | 115 | /** |
<> | 144:ef7eb2e8f9f7 | 116 | * @} |
<> | 144:ef7eb2e8f9f7 | 117 | */ |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | /** |
<> | 144:ef7eb2e8f9f7 | 120 | * @} |
<> | 144:ef7eb2e8f9f7 | 121 | */ |
<> | 144:ef7eb2e8f9f7 | 122 | |
<> | 144:ef7eb2e8f9f7 | 123 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 124 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 125 | /** @defgroup PWR_Private_Functions PWR Private Functions |
<> | 144:ef7eb2e8f9f7 | 126 | * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) |
<> | 144:ef7eb2e8f9f7 | 127 | * @{ |
<> | 144:ef7eb2e8f9f7 | 128 | */ |
<> | 144:ef7eb2e8f9f7 | 129 | static void PWR_OverloadWfe(void); |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | /* Private functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 132 | __NOINLINE |
<> | 144:ef7eb2e8f9f7 | 133 | static void PWR_OverloadWfe(void) |
<> | 144:ef7eb2e8f9f7 | 134 | { |
<> | 144:ef7eb2e8f9f7 | 135 | __asm volatile( "wfe" ); |
<> | 144:ef7eb2e8f9f7 | 136 | __asm volatile( "nop" ); |
<> | 144:ef7eb2e8f9f7 | 137 | } |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | /** |
<> | 144:ef7eb2e8f9f7 | 140 | * @} |
<> | 144:ef7eb2e8f9f7 | 141 | */ |
<> | 144:ef7eb2e8f9f7 | 142 | |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | /** @defgroup PWR_Exported_Functions PWR Exported Functions |
<> | 144:ef7eb2e8f9f7 | 145 | * @{ |
<> | 144:ef7eb2e8f9f7 | 146 | */ |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 149 | * @brief Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 150 | * |
<> | 144:ef7eb2e8f9f7 | 151 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 152 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 153 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 154 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 155 | [..] |
<> | 144:ef7eb2e8f9f7 | 156 | After reset, the backup domain (RTC registers, RTC backup data |
<> | 144:ef7eb2e8f9f7 | 157 | registers) is protected against possible unwanted |
<> | 144:ef7eb2e8f9f7 | 158 | write accesses. |
<> | 144:ef7eb2e8f9f7 | 159 | To enable access to the RTC Domain and RTC registers, proceed as follows: |
<> | 144:ef7eb2e8f9f7 | 160 | (+) Enable the Power Controller (PWR) APB1 interface clock using the |
<> | 144:ef7eb2e8f9f7 | 161 | __HAL_RCC_PWR_CLK_ENABLE() macro. |
<> | 144:ef7eb2e8f9f7 | 162 | (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 165 | * @{ |
<> | 144:ef7eb2e8f9f7 | 166 | */ |
<> | 144:ef7eb2e8f9f7 | 167 | |
<> | 144:ef7eb2e8f9f7 | 168 | /** |
<> | 144:ef7eb2e8f9f7 | 169 | * @brief Deinitializes the PWR peripheral registers to their default reset values. |
<> | 144:ef7eb2e8f9f7 | 170 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 171 | */ |
<> | 144:ef7eb2e8f9f7 | 172 | void HAL_PWR_DeInit(void) |
<> | 144:ef7eb2e8f9f7 | 173 | { |
<> | 144:ef7eb2e8f9f7 | 174 | __HAL_RCC_PWR_FORCE_RESET(); |
<> | 144:ef7eb2e8f9f7 | 175 | __HAL_RCC_PWR_RELEASE_RESET(); |
<> | 144:ef7eb2e8f9f7 | 176 | } |
<> | 144:ef7eb2e8f9f7 | 177 | |
<> | 144:ef7eb2e8f9f7 | 178 | /** |
<> | 144:ef7eb2e8f9f7 | 179 | * @brief Enables access to the backup domain (RTC registers, RTC |
<> | 144:ef7eb2e8f9f7 | 180 | * backup data registers ). |
<> | 144:ef7eb2e8f9f7 | 181 | * @note If the HSE divided by 128 is used as the RTC clock, the |
<> | 144:ef7eb2e8f9f7 | 182 | * Backup Domain Access should be kept enabled. |
<> | 144:ef7eb2e8f9f7 | 183 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 184 | */ |
<> | 144:ef7eb2e8f9f7 | 185 | void HAL_PWR_EnableBkUpAccess(void) |
<> | 144:ef7eb2e8f9f7 | 186 | { |
<> | 144:ef7eb2e8f9f7 | 187 | /* Enable access to RTC and backup registers */ |
<> | 144:ef7eb2e8f9f7 | 188 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; |
<> | 144:ef7eb2e8f9f7 | 189 | } |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | /** |
<> | 144:ef7eb2e8f9f7 | 192 | * @brief Disables access to the backup domain (RTC registers, RTC |
<> | 144:ef7eb2e8f9f7 | 193 | * backup data registers). |
<> | 144:ef7eb2e8f9f7 | 194 | * @note If the HSE divided by 128 is used as the RTC clock, the |
<> | 144:ef7eb2e8f9f7 | 195 | * Backup Domain Access should be kept enabled. |
<> | 144:ef7eb2e8f9f7 | 196 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 197 | */ |
<> | 144:ef7eb2e8f9f7 | 198 | void HAL_PWR_DisableBkUpAccess(void) |
<> | 144:ef7eb2e8f9f7 | 199 | { |
<> | 144:ef7eb2e8f9f7 | 200 | /* Disable access to RTC and backup registers */ |
<> | 144:ef7eb2e8f9f7 | 201 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; |
<> | 144:ef7eb2e8f9f7 | 202 | } |
<> | 144:ef7eb2e8f9f7 | 203 | |
<> | 144:ef7eb2e8f9f7 | 204 | /** |
<> | 144:ef7eb2e8f9f7 | 205 | * @} |
<> | 144:ef7eb2e8f9f7 | 206 | */ |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 209 | * @brief Low Power modes configuration functions |
<> | 144:ef7eb2e8f9f7 | 210 | * |
<> | 144:ef7eb2e8f9f7 | 211 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 212 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 213 | ##### Peripheral Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 214 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 215 | |
<> | 144:ef7eb2e8f9f7 | 216 | *** PVD configuration *** |
<> | 144:ef7eb2e8f9f7 | 217 | ========================= |
<> | 144:ef7eb2e8f9f7 | 218 | [..] |
<> | 144:ef7eb2e8f9f7 | 219 | (+) The PVD is used to monitor the VDD power supply by comparing it to a |
<> | 144:ef7eb2e8f9f7 | 220 | threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). |
<> | 144:ef7eb2e8f9f7 | 221 | |
<> | 144:ef7eb2e8f9f7 | 222 | (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower |
<> | 144:ef7eb2e8f9f7 | 223 | than the PVD threshold. This event is internally connected to the EXTI |
<> | 144:ef7eb2e8f9f7 | 224 | line16 and can generate an interrupt if enabled. This is done through |
<> | 144:ef7eb2e8f9f7 | 225 | __HAL_PVD_EXTI_ENABLE_IT() macro. |
<> | 144:ef7eb2e8f9f7 | 226 | (+) The PVD is stopped in Standby mode. |
<> | 144:ef7eb2e8f9f7 | 227 | |
<> | 144:ef7eb2e8f9f7 | 228 | *** WakeUp pin configuration *** |
<> | 144:ef7eb2e8f9f7 | 229 | ================================ |
<> | 144:ef7eb2e8f9f7 | 230 | [..] |
<> | 144:ef7eb2e8f9f7 | 231 | (+) WakeUp pin is used to wake up the system from Standby mode. This pin is |
<> | 144:ef7eb2e8f9f7 | 232 | forced in input pull-down configuration and is active on rising edges. |
<> | 144:ef7eb2e8f9f7 | 233 | (+) There is one WakeUp pin: |
<> | 144:ef7eb2e8f9f7 | 234 | WakeUp Pin 1 on PA.00. |
<> | 144:ef7eb2e8f9f7 | 235 | |
<> | 144:ef7eb2e8f9f7 | 236 | [..] |
<> | 144:ef7eb2e8f9f7 | 237 | |
<> | 144:ef7eb2e8f9f7 | 238 | *** Low Power modes configuration *** |
<> | 144:ef7eb2e8f9f7 | 239 | ===================================== |
<> | 144:ef7eb2e8f9f7 | 240 | [..] |
<> | 144:ef7eb2e8f9f7 | 241 | The device features 3 low-power modes: |
<> | 144:ef7eb2e8f9f7 | 242 | (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like |
<> | 144:ef7eb2e8f9f7 | 243 | NVIC, SysTick, etc. are kept running |
<> | 144:ef7eb2e8f9f7 | 244 | (+) Stop mode: All clocks are stopped |
<> | 144:ef7eb2e8f9f7 | 245 | (+) Standby mode: 1.8V domain powered off |
<> | 144:ef7eb2e8f9f7 | 246 | |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | *** Sleep mode *** |
<> | 144:ef7eb2e8f9f7 | 249 | ================== |
<> | 144:ef7eb2e8f9f7 | 250 | [..] |
<> | 144:ef7eb2e8f9f7 | 251 | (+) Entry: |
<> | 144:ef7eb2e8f9f7 | 252 | The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
<> | 144:ef7eb2e8f9f7 | 253 | functions with |
<> | 144:ef7eb2e8f9f7 | 254 | (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
<> | 144:ef7eb2e8f9f7 | 255 | (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
<> | 144:ef7eb2e8f9f7 | 256 | |
<> | 144:ef7eb2e8f9f7 | 257 | (+) Exit: |
<> | 144:ef7eb2e8f9f7 | 258 | (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt |
<> | 144:ef7eb2e8f9f7 | 259 | controller (NVIC) can wake up the device from Sleep mode. |
<> | 144:ef7eb2e8f9f7 | 260 | (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. |
<> | 144:ef7eb2e8f9f7 | 261 | (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend) |
<> | 144:ef7eb2e8f9f7 | 262 | (+++) Any EXTI Line (Internal or External) configured in Event mode |
<> | 144:ef7eb2e8f9f7 | 263 | |
<> | 144:ef7eb2e8f9f7 | 264 | *** Stop mode *** |
<> | 144:ef7eb2e8f9f7 | 265 | ================= |
<> | 144:ef7eb2e8f9f7 | 266 | [..] |
<> | 144:ef7eb2e8f9f7 | 267 | The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral |
<> | 144:ef7eb2e8f9f7 | 268 | clock gating. The voltage regulator can be configured either in normal or low-power mode. |
<> | 144:ef7eb2e8f9f7 | 269 | In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC |
<> | 144:ef7eb2e8f9f7 | 270 | oscillators are disabled. SRAM and register contents are preserved. |
<> | 144:ef7eb2e8f9f7 | 271 | In Stop mode, all I/O pins keep the same state as in Run mode. |
<> | 144:ef7eb2e8f9f7 | 272 | |
<> | 144:ef7eb2e8f9f7 | 273 | (+) Entry: |
<> | 144:ef7eb2e8f9f7 | 274 | The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx ) |
<> | 144:ef7eb2e8f9f7 | 275 | function with: |
<> | 144:ef7eb2e8f9f7 | 276 | (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. |
<> | 144:ef7eb2e8f9f7 | 277 | (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. |
<> | 144:ef7eb2e8f9f7 | 278 | (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction |
<> | 144:ef7eb2e8f9f7 | 279 | (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction |
<> | 144:ef7eb2e8f9f7 | 280 | (+) Exit: |
<> | 144:ef7eb2e8f9f7 | 281 | (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured |
<> | 144:ef7eb2e8f9f7 | 282 | (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | *** Standby mode *** |
<> | 144:ef7eb2e8f9f7 | 285 | ==================== |
<> | 144:ef7eb2e8f9f7 | 286 | [..] |
<> | 144:ef7eb2e8f9f7 | 287 | The Standby mode allows to achieve the lowest power consumption. It is based on the |
<> | 144:ef7eb2e8f9f7 | 288 | Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is |
<> | 144:ef7eb2e8f9f7 | 289 | consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also |
<> | 144:ef7eb2e8f9f7 | 290 | switched off. SRAM and register contents are lost except for registers in the Backup domain |
<> | 144:ef7eb2e8f9f7 | 291 | and Standby circuitry |
<> | 144:ef7eb2e8f9f7 | 292 | |
<> | 144:ef7eb2e8f9f7 | 293 | (+) Entry: |
<> | 144:ef7eb2e8f9f7 | 294 | (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. |
<> | 144:ef7eb2e8f9f7 | 295 | (+) Exit: |
<> | 144:ef7eb2e8f9f7 | 296 | (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in |
<> | 144:ef7eb2e8f9f7 | 297 | NRSTpin, IWDG Reset |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | *** Auto-wakeup (AWU) from low-power mode *** |
<> | 144:ef7eb2e8f9f7 | 300 | ============================================= |
<> | 144:ef7eb2e8f9f7 | 301 | [..] |
<> | 144:ef7eb2e8f9f7 | 302 | |
<> | 144:ef7eb2e8f9f7 | 303 | (+) The MCU can be woken up from low-power mode by an RTC Alarm event, |
<> | 144:ef7eb2e8f9f7 | 304 | without depending on an external interrupt (Auto-wakeup mode). |
<> | 144:ef7eb2e8f9f7 | 305 | |
<> | 144:ef7eb2e8f9f7 | 306 | (+) RTC auto-wakeup (AWU) from the Stop and Standby modes |
<> | 144:ef7eb2e8f9f7 | 307 | |
<> | 144:ef7eb2e8f9f7 | 308 | (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to |
<> | 144:ef7eb2e8f9f7 | 309 | configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | *** PWR Workarounds linked to Silicon Limitation *** |
<> | 144:ef7eb2e8f9f7 | 312 | ==================================================== |
<> | 144:ef7eb2e8f9f7 | 313 | [..] |
<> | 144:ef7eb2e8f9f7 | 314 | Below the list of all silicon limitations known on STM32F1xx prouct. |
<> | 144:ef7eb2e8f9f7 | 315 | |
<> | 144:ef7eb2e8f9f7 | 316 | (#)Workarounds Implemented inside PWR HAL Driver |
<> | 144:ef7eb2e8f9f7 | 317 | (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function |
<> | 144:ef7eb2e8f9f7 | 318 | |
<> | 144:ef7eb2e8f9f7 | 319 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 320 | * @{ |
<> | 144:ef7eb2e8f9f7 | 321 | */ |
<> | 144:ef7eb2e8f9f7 | 322 | |
<> | 144:ef7eb2e8f9f7 | 323 | /** |
<> | 144:ef7eb2e8f9f7 | 324 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). |
<> | 144:ef7eb2e8f9f7 | 325 | * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration |
<> | 144:ef7eb2e8f9f7 | 326 | * information for the PVD. |
<> | 144:ef7eb2e8f9f7 | 327 | * @note Refer to the electrical characteristics of your device datasheet for |
<> | 144:ef7eb2e8f9f7 | 328 | * more details about the voltage threshold corresponding to each |
<> | 144:ef7eb2e8f9f7 | 329 | * detection level. |
<> | 144:ef7eb2e8f9f7 | 330 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 331 | */ |
<> | 144:ef7eb2e8f9f7 | 332 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) |
<> | 144:ef7eb2e8f9f7 | 333 | { |
<> | 144:ef7eb2e8f9f7 | 334 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 335 | assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); |
<> | 144:ef7eb2e8f9f7 | 336 | assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); |
<> | 144:ef7eb2e8f9f7 | 337 | |
<> | 144:ef7eb2e8f9f7 | 338 | /* Set PLS[7:5] bits according to PVDLevel value */ |
<> | 144:ef7eb2e8f9f7 | 339 | MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); |
<> | 144:ef7eb2e8f9f7 | 340 | |
<> | 144:ef7eb2e8f9f7 | 341 | /* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
<> | 144:ef7eb2e8f9f7 | 342 | __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); |
<> | 144:ef7eb2e8f9f7 | 343 | __HAL_PWR_PVD_EXTI_DISABLE_IT(); |
<> | 144:ef7eb2e8f9f7 | 344 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); |
<> | 144:ef7eb2e8f9f7 | 345 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); |
<> | 144:ef7eb2e8f9f7 | 346 | |
<> | 144:ef7eb2e8f9f7 | 347 | /* Configure interrupt mode */ |
<> | 144:ef7eb2e8f9f7 | 348 | if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) |
<> | 144:ef7eb2e8f9f7 | 349 | { |
<> | 144:ef7eb2e8f9f7 | 350 | __HAL_PWR_PVD_EXTI_ENABLE_IT(); |
<> | 144:ef7eb2e8f9f7 | 351 | } |
<> | 144:ef7eb2e8f9f7 | 352 | |
<> | 144:ef7eb2e8f9f7 | 353 | /* Configure event mode */ |
<> | 144:ef7eb2e8f9f7 | 354 | if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) |
<> | 144:ef7eb2e8f9f7 | 355 | { |
<> | 144:ef7eb2e8f9f7 | 356 | __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); |
<> | 144:ef7eb2e8f9f7 | 357 | } |
<> | 144:ef7eb2e8f9f7 | 358 | |
<> | 144:ef7eb2e8f9f7 | 359 | /* Configure the edge */ |
<> | 144:ef7eb2e8f9f7 | 360 | if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) |
<> | 144:ef7eb2e8f9f7 | 361 | { |
<> | 144:ef7eb2e8f9f7 | 362 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); |
<> | 144:ef7eb2e8f9f7 | 363 | } |
<> | 144:ef7eb2e8f9f7 | 364 | |
<> | 144:ef7eb2e8f9f7 | 365 | if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) |
<> | 144:ef7eb2e8f9f7 | 366 | { |
<> | 144:ef7eb2e8f9f7 | 367 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
<> | 144:ef7eb2e8f9f7 | 368 | } |
<> | 144:ef7eb2e8f9f7 | 369 | } |
<> | 144:ef7eb2e8f9f7 | 370 | |
<> | 144:ef7eb2e8f9f7 | 371 | /** |
<> | 144:ef7eb2e8f9f7 | 372 | * @brief Enables the Power Voltage Detector(PVD). |
<> | 144:ef7eb2e8f9f7 | 373 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 374 | */ |
<> | 144:ef7eb2e8f9f7 | 375 | void HAL_PWR_EnablePVD(void) |
<> | 144:ef7eb2e8f9f7 | 376 | { |
<> | 144:ef7eb2e8f9f7 | 377 | /* Enable the power voltage detector */ |
<> | 144:ef7eb2e8f9f7 | 378 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; |
<> | 144:ef7eb2e8f9f7 | 379 | } |
<> | 144:ef7eb2e8f9f7 | 380 | |
<> | 144:ef7eb2e8f9f7 | 381 | /** |
<> | 144:ef7eb2e8f9f7 | 382 | * @brief Disables the Power Voltage Detector(PVD). |
<> | 144:ef7eb2e8f9f7 | 383 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 384 | */ |
<> | 144:ef7eb2e8f9f7 | 385 | void HAL_PWR_DisablePVD(void) |
<> | 144:ef7eb2e8f9f7 | 386 | { |
<> | 144:ef7eb2e8f9f7 | 387 | /* Disable the power voltage detector */ |
<> | 144:ef7eb2e8f9f7 | 388 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; |
<> | 144:ef7eb2e8f9f7 | 389 | } |
<> | 144:ef7eb2e8f9f7 | 390 | |
<> | 144:ef7eb2e8f9f7 | 391 | /** |
<> | 144:ef7eb2e8f9f7 | 392 | * @brief Enables the WakeUp PINx functionality. |
<> | 144:ef7eb2e8f9f7 | 393 | * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. |
<> | 144:ef7eb2e8f9f7 | 394 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 395 | * @arg PWR_WAKEUP_PIN1 |
<> | 144:ef7eb2e8f9f7 | 396 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 397 | */ |
<> | 144:ef7eb2e8f9f7 | 398 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) |
<> | 144:ef7eb2e8f9f7 | 399 | { |
<> | 144:ef7eb2e8f9f7 | 400 | /* Check the parameter */ |
<> | 144:ef7eb2e8f9f7 | 401 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
<> | 144:ef7eb2e8f9f7 | 402 | /* Enable the EWUPx pin */ |
<> | 144:ef7eb2e8f9f7 | 403 | *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; |
<> | 144:ef7eb2e8f9f7 | 404 | } |
<> | 144:ef7eb2e8f9f7 | 405 | |
<> | 144:ef7eb2e8f9f7 | 406 | /** |
<> | 144:ef7eb2e8f9f7 | 407 | * @brief Disables the WakeUp PINx functionality. |
<> | 144:ef7eb2e8f9f7 | 408 | * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. |
<> | 144:ef7eb2e8f9f7 | 409 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 410 | * @arg PWR_WAKEUP_PIN1 |
<> | 144:ef7eb2e8f9f7 | 411 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 412 | */ |
<> | 144:ef7eb2e8f9f7 | 413 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) |
<> | 144:ef7eb2e8f9f7 | 414 | { |
<> | 144:ef7eb2e8f9f7 | 415 | /* Check the parameter */ |
<> | 144:ef7eb2e8f9f7 | 416 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
<> | 144:ef7eb2e8f9f7 | 417 | /* Disable the EWUPx pin */ |
<> | 144:ef7eb2e8f9f7 | 418 | *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; |
<> | 144:ef7eb2e8f9f7 | 419 | } |
<> | 144:ef7eb2e8f9f7 | 420 | |
<> | 144:ef7eb2e8f9f7 | 421 | /** |
<> | 144:ef7eb2e8f9f7 | 422 | * @brief Enters Sleep mode. |
<> | 144:ef7eb2e8f9f7 | 423 | * @note In Sleep mode, all I/O pins keep the same state as in Run mode. |
<> | 144:ef7eb2e8f9f7 | 424 | * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software |
<> | 144:ef7eb2e8f9f7 | 425 | * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. |
<> | 144:ef7eb2e8f9f7 | 426 | * When WFI entry is used, tick interrupt have to be disabled if not desired as |
<> | 144:ef7eb2e8f9f7 | 427 | * the interrupt wake up source. |
<> | 144:ef7eb2e8f9f7 | 428 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 429 | * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
<> | 144:ef7eb2e8f9f7 | 430 | * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
<> | 144:ef7eb2e8f9f7 | 431 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 432 | */ |
<> | 144:ef7eb2e8f9f7 | 433 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) |
<> | 144:ef7eb2e8f9f7 | 434 | { |
<> | 144:ef7eb2e8f9f7 | 435 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 436 | /* No check on Regulator because parameter not used in SLEEP mode */ |
AnnaBridge | 165:e614a9f1c9e2 | 437 | /* Prevent unused argument(s) compilation warning */ |
AnnaBridge | 165:e614a9f1c9e2 | 438 | UNUSED(Regulator); |
AnnaBridge | 165:e614a9f1c9e2 | 439 | |
<> | 144:ef7eb2e8f9f7 | 440 | assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); |
<> | 144:ef7eb2e8f9f7 | 441 | |
<> | 144:ef7eb2e8f9f7 | 442 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 443 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
<> | 144:ef7eb2e8f9f7 | 444 | |
<> | 144:ef7eb2e8f9f7 | 445 | /* Select SLEEP mode entry -------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 446 | if(SLEEPEntry == PWR_SLEEPENTRY_WFI) |
<> | 144:ef7eb2e8f9f7 | 447 | { |
<> | 144:ef7eb2e8f9f7 | 448 | /* Request Wait For Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 449 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 450 | } |
<> | 144:ef7eb2e8f9f7 | 451 | else |
<> | 144:ef7eb2e8f9f7 | 452 | { |
<> | 144:ef7eb2e8f9f7 | 453 | /* Request Wait For Event */ |
<> | 144:ef7eb2e8f9f7 | 454 | __SEV(); |
<> | 144:ef7eb2e8f9f7 | 455 | __WFE(); |
<> | 144:ef7eb2e8f9f7 | 456 | __WFE(); |
<> | 144:ef7eb2e8f9f7 | 457 | } |
<> | 144:ef7eb2e8f9f7 | 458 | } |
<> | 144:ef7eb2e8f9f7 | 459 | |
<> | 144:ef7eb2e8f9f7 | 460 | /** |
<> | 144:ef7eb2e8f9f7 | 461 | * @brief Enters Stop mode. |
<> | 144:ef7eb2e8f9f7 | 462 | * @note In Stop mode, all I/O pins keep the same state as in Run mode. |
<> | 144:ef7eb2e8f9f7 | 463 | * @note When exiting Stop mode by using an interrupt or a wakeup event, |
<> | 144:ef7eb2e8f9f7 | 464 | * HSI RC oscillator is selected as system clock. |
<> | 144:ef7eb2e8f9f7 | 465 | * @note When the voltage regulator operates in low power mode, an additional |
<> | 144:ef7eb2e8f9f7 | 466 | * startup delay is incurred when waking up from Stop mode. |
<> | 144:ef7eb2e8f9f7 | 467 | * By keeping the internal regulator ON during Stop mode, the consumption |
<> | 144:ef7eb2e8f9f7 | 468 | * is higher although the startup time is reduced. |
<> | 144:ef7eb2e8f9f7 | 469 | * @param Regulator: Specifies the regulator state in Stop mode. |
<> | 144:ef7eb2e8f9f7 | 470 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 471 | * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON |
<> | 144:ef7eb2e8f9f7 | 472 | * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON |
<> | 144:ef7eb2e8f9f7 | 473 | * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. |
<> | 144:ef7eb2e8f9f7 | 474 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 475 | * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction |
<> | 144:ef7eb2e8f9f7 | 476 | * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction |
<> | 144:ef7eb2e8f9f7 | 477 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 478 | */ |
<> | 144:ef7eb2e8f9f7 | 479 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
<> | 144:ef7eb2e8f9f7 | 480 | { |
<> | 144:ef7eb2e8f9f7 | 481 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 482 | assert_param(IS_PWR_REGULATOR(Regulator)); |
<> | 144:ef7eb2e8f9f7 | 483 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
<> | 144:ef7eb2e8f9f7 | 484 | |
<> | 144:ef7eb2e8f9f7 | 485 | /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ |
<> | 144:ef7eb2e8f9f7 | 486 | CLEAR_BIT(PWR->CR, PWR_CR_PDDS); |
<> | 144:ef7eb2e8f9f7 | 487 | |
<> | 144:ef7eb2e8f9f7 | 488 | /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ |
<> | 144:ef7eb2e8f9f7 | 489 | MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); |
<> | 144:ef7eb2e8f9f7 | 490 | |
<> | 144:ef7eb2e8f9f7 | 491 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 492 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
<> | 144:ef7eb2e8f9f7 | 493 | |
<> | 144:ef7eb2e8f9f7 | 494 | /* Select Stop mode entry --------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 495 | if(STOPEntry == PWR_STOPENTRY_WFI) |
<> | 144:ef7eb2e8f9f7 | 496 | { |
<> | 144:ef7eb2e8f9f7 | 497 | /* Request Wait For Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 498 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 499 | } |
<> | 144:ef7eb2e8f9f7 | 500 | else |
<> | 144:ef7eb2e8f9f7 | 501 | { |
<> | 144:ef7eb2e8f9f7 | 502 | /* Request Wait For Event */ |
<> | 144:ef7eb2e8f9f7 | 503 | __SEV(); |
<> | 144:ef7eb2e8f9f7 | 504 | PWR_OverloadWfe(); /* WFE redefine locally */ |
<> | 144:ef7eb2e8f9f7 | 505 | PWR_OverloadWfe(); /* WFE redefine locally */ |
<> | 144:ef7eb2e8f9f7 | 506 | } |
<> | 144:ef7eb2e8f9f7 | 507 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 508 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
<> | 144:ef7eb2e8f9f7 | 509 | } |
<> | 144:ef7eb2e8f9f7 | 510 | |
<> | 144:ef7eb2e8f9f7 | 511 | /** |
<> | 144:ef7eb2e8f9f7 | 512 | * @brief Enters Standby mode. |
<> | 144:ef7eb2e8f9f7 | 513 | * @note In Standby mode, all I/O pins are high impedance except for: |
<> | 144:ef7eb2e8f9f7 | 514 | * - Reset pad (still available) |
<> | 144:ef7eb2e8f9f7 | 515 | * - TAMPER pin if configured for tamper or calibration out. |
<> | 144:ef7eb2e8f9f7 | 516 | * - WKUP pin (PA0) if enabled. |
<> | 144:ef7eb2e8f9f7 | 517 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 518 | */ |
<> | 144:ef7eb2e8f9f7 | 519 | void HAL_PWR_EnterSTANDBYMode(void) |
<> | 144:ef7eb2e8f9f7 | 520 | { |
<> | 144:ef7eb2e8f9f7 | 521 | /* Select Standby mode */ |
<> | 144:ef7eb2e8f9f7 | 522 | SET_BIT(PWR->CR, PWR_CR_PDDS); |
<> | 144:ef7eb2e8f9f7 | 523 | |
<> | 144:ef7eb2e8f9f7 | 524 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 525 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
<> | 144:ef7eb2e8f9f7 | 526 | |
<> | 144:ef7eb2e8f9f7 | 527 | /* This option is used to ensure that store operations are completed */ |
<> | 144:ef7eb2e8f9f7 | 528 | #if defined ( __CC_ARM) |
<> | 144:ef7eb2e8f9f7 | 529 | __force_stores(); |
<> | 144:ef7eb2e8f9f7 | 530 | #endif |
<> | 144:ef7eb2e8f9f7 | 531 | /* Request Wait For Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 532 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 533 | } |
<> | 144:ef7eb2e8f9f7 | 534 | |
<> | 144:ef7eb2e8f9f7 | 535 | |
<> | 144:ef7eb2e8f9f7 | 536 | /** |
<> | 144:ef7eb2e8f9f7 | 537 | * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. |
<> | 144:ef7eb2e8f9f7 | 538 | * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
<> | 144:ef7eb2e8f9f7 | 539 | * re-enters SLEEP mode when an interruption handling is over. |
<> | 144:ef7eb2e8f9f7 | 540 | * Setting this bit is useful when the processor is expected to run only on |
<> | 144:ef7eb2e8f9f7 | 541 | * interruptions handling. |
<> | 144:ef7eb2e8f9f7 | 542 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 543 | */ |
<> | 144:ef7eb2e8f9f7 | 544 | void HAL_PWR_EnableSleepOnExit(void) |
<> | 144:ef7eb2e8f9f7 | 545 | { |
<> | 144:ef7eb2e8f9f7 | 546 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 547 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
<> | 144:ef7eb2e8f9f7 | 548 | } |
<> | 144:ef7eb2e8f9f7 | 549 | |
<> | 144:ef7eb2e8f9f7 | 550 | |
<> | 144:ef7eb2e8f9f7 | 551 | /** |
<> | 144:ef7eb2e8f9f7 | 552 | * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. |
<> | 144:ef7eb2e8f9f7 | 553 | * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
<> | 144:ef7eb2e8f9f7 | 554 | * re-enters SLEEP mode when an interruption handling is over. |
<> | 144:ef7eb2e8f9f7 | 555 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 556 | */ |
<> | 144:ef7eb2e8f9f7 | 557 | void HAL_PWR_DisableSleepOnExit(void) |
<> | 144:ef7eb2e8f9f7 | 558 | { |
<> | 144:ef7eb2e8f9f7 | 559 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 560 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
<> | 144:ef7eb2e8f9f7 | 561 | } |
<> | 144:ef7eb2e8f9f7 | 562 | |
<> | 144:ef7eb2e8f9f7 | 563 | |
<> | 144:ef7eb2e8f9f7 | 564 | /** |
<> | 144:ef7eb2e8f9f7 | 565 | * @brief Enables CORTEX M3 SEVONPEND bit. |
<> | 144:ef7eb2e8f9f7 | 566 | * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes |
<> | 144:ef7eb2e8f9f7 | 567 | * WFE to wake up when an interrupt moves from inactive to pended. |
<> | 144:ef7eb2e8f9f7 | 568 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 569 | */ |
<> | 144:ef7eb2e8f9f7 | 570 | void HAL_PWR_EnableSEVOnPend(void) |
<> | 144:ef7eb2e8f9f7 | 571 | { |
<> | 144:ef7eb2e8f9f7 | 572 | /* Set SEVONPEND bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 573 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
<> | 144:ef7eb2e8f9f7 | 574 | } |
<> | 144:ef7eb2e8f9f7 | 575 | |
<> | 144:ef7eb2e8f9f7 | 576 | |
<> | 144:ef7eb2e8f9f7 | 577 | /** |
<> | 144:ef7eb2e8f9f7 | 578 | * @brief Disables CORTEX M3 SEVONPEND bit. |
<> | 144:ef7eb2e8f9f7 | 579 | * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes |
<> | 144:ef7eb2e8f9f7 | 580 | * WFE to wake up when an interrupt moves from inactive to pended. |
<> | 144:ef7eb2e8f9f7 | 581 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 582 | */ |
<> | 144:ef7eb2e8f9f7 | 583 | void HAL_PWR_DisableSEVOnPend(void) |
<> | 144:ef7eb2e8f9f7 | 584 | { |
<> | 144:ef7eb2e8f9f7 | 585 | /* Clear SEVONPEND bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 586 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
<> | 144:ef7eb2e8f9f7 | 587 | } |
<> | 144:ef7eb2e8f9f7 | 588 | |
<> | 144:ef7eb2e8f9f7 | 589 | |
<> | 144:ef7eb2e8f9f7 | 590 | |
<> | 144:ef7eb2e8f9f7 | 591 | /** |
<> | 144:ef7eb2e8f9f7 | 592 | * @brief This function handles the PWR PVD interrupt request. |
<> | 144:ef7eb2e8f9f7 | 593 | * @note This API should be called under the PVD_IRQHandler(). |
<> | 144:ef7eb2e8f9f7 | 594 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 595 | */ |
<> | 144:ef7eb2e8f9f7 | 596 | void HAL_PWR_PVD_IRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 597 | { |
<> | 144:ef7eb2e8f9f7 | 598 | /* Check PWR exti flag */ |
<> | 144:ef7eb2e8f9f7 | 599 | if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) |
<> | 144:ef7eb2e8f9f7 | 600 | { |
<> | 144:ef7eb2e8f9f7 | 601 | /* PWR PVD interrupt user callback */ |
<> | 144:ef7eb2e8f9f7 | 602 | HAL_PWR_PVDCallback(); |
<> | 144:ef7eb2e8f9f7 | 603 | |
<> | 144:ef7eb2e8f9f7 | 604 | /* Clear PWR Exti pending bit */ |
<> | 144:ef7eb2e8f9f7 | 605 | __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); |
<> | 144:ef7eb2e8f9f7 | 606 | } |
<> | 144:ef7eb2e8f9f7 | 607 | } |
<> | 144:ef7eb2e8f9f7 | 608 | |
<> | 144:ef7eb2e8f9f7 | 609 | /** |
<> | 144:ef7eb2e8f9f7 | 610 | * @brief PWR PVD interrupt callback |
<> | 144:ef7eb2e8f9f7 | 611 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 612 | */ |
<> | 144:ef7eb2e8f9f7 | 613 | __weak void HAL_PWR_PVDCallback(void) |
<> | 144:ef7eb2e8f9f7 | 614 | { |
<> | 144:ef7eb2e8f9f7 | 615 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 616 | the HAL_PWR_PVDCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 617 | */ |
<> | 144:ef7eb2e8f9f7 | 618 | } |
<> | 144:ef7eb2e8f9f7 | 619 | |
<> | 144:ef7eb2e8f9f7 | 620 | /** |
<> | 144:ef7eb2e8f9f7 | 621 | * @} |
<> | 144:ef7eb2e8f9f7 | 622 | */ |
<> | 144:ef7eb2e8f9f7 | 623 | |
<> | 144:ef7eb2e8f9f7 | 624 | /** |
<> | 144:ef7eb2e8f9f7 | 625 | * @} |
<> | 144:ef7eb2e8f9f7 | 626 | */ |
<> | 144:ef7eb2e8f9f7 | 627 | |
<> | 144:ef7eb2e8f9f7 | 628 | #endif /* HAL_PWR_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 629 | /** |
<> | 144:ef7eb2e8f9f7 | 630 | * @} |
<> | 144:ef7eb2e8f9f7 | 631 | */ |
<> | 144:ef7eb2e8f9f7 | 632 | |
<> | 144:ef7eb2e8f9f7 | 633 | /** |
<> | 144:ef7eb2e8f9f7 | 634 | * @} |
<> | 144:ef7eb2e8f9f7 | 635 | */ |
<> | 144:ef7eb2e8f9f7 | 636 | |
<> | 144:ef7eb2e8f9f7 | 637 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |