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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_adc_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of ADC HAL extension module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F1xx_HAL_ADC_EX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F1xx_HAL_ADC_EX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup ADCEx
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /**
<> 144:ef7eb2e8f9f7 61 * @brief ADC Configuration injected Channel structure definition
<> 144:ef7eb2e8f9f7 62 * @note Parameters of this structure are shared within 2 scopes:
<> 144:ef7eb2e8f9f7 63 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
<> 144:ef7eb2e8f9f7 64 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
<> 144:ef7eb2e8f9f7 65 * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
<> 144:ef7eb2e8f9f7 66 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 67 * ADC state can be either:
<> 144:ef7eb2e8f9f7 68 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
<> 144:ef7eb2e8f9f7 69 * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71 typedef struct
<> 144:ef7eb2e8f9f7 72 {
<> 144:ef7eb2e8f9f7 73 uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref ADC_channels
<> 144:ef7eb2e8f9f7 75 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
<> 144:ef7eb2e8f9f7 76 Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
<> 144:ef7eb2e8f9f7 77 Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
<> 144:ef7eb2e8f9f7 78 It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
<> 144:ef7eb2e8f9f7 79 Refer to errata sheet of these devices for more details. */
<> 144:ef7eb2e8f9f7 80 uint32_t InjectedRank; /*!< Rank in the injected group sequencer
<> 144:ef7eb2e8f9f7 81 This parameter must be a value of @ref ADCEx_injected_rank
<> 144:ef7eb2e8f9f7 82 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<> 144:ef7eb2e8f9f7 83 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
<> 144:ef7eb2e8f9f7 84 Unit: ADC clock cycles
<> 144:ef7eb2e8f9f7 85 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref ADC_sampling_times
<> 144:ef7eb2e8f9f7 87 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<> 144:ef7eb2e8f9f7 88 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<> 144:ef7eb2e8f9f7 89 Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
<> 144:ef7eb2e8f9f7 90 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<> 144:ef7eb2e8f9f7 91 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
<> 144:ef7eb2e8f9f7 92 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
<> 144:ef7eb2e8f9f7 93 Offset value must be a positive number.
<> 144:ef7eb2e8f9f7 94 Depending of ADC resolution selected (12, 10, 8 or 6 bits),
<> 144:ef7eb2e8f9f7 95 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
<> 144:ef7eb2e8f9f7 96 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
<> 144:ef7eb2e8f9f7 97 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<> 144:ef7eb2e8f9f7 98 This parameter must be a number between Min_Data = 1 and Max_Data = 4.
<> 144:ef7eb2e8f9f7 99 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 144:ef7eb2e8f9f7 100 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 144:ef7eb2e8f9f7 101 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<> 144:ef7eb2e8f9f7 102 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 103 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<> 144:ef7eb2e8f9f7 104 This parameter can be set to ENABLE or DISABLE.
<> 144:ef7eb2e8f9f7 105 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
<> 144:ef7eb2e8f9f7 106 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 144:ef7eb2e8f9f7 107 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 144:ef7eb2e8f9f7 108 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
<> 144:ef7eb2e8f9f7 109 This parameter can be set to ENABLE or DISABLE.
<> 144:ef7eb2e8f9f7 110 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
<> 144:ef7eb2e8f9f7 111 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 112 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
<> 144:ef7eb2e8f9f7 113 To maintain JAUTO always enabled, DMA must be configured in circular mode.
<> 144:ef7eb2e8f9f7 114 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 144:ef7eb2e8f9f7 115 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 144:ef7eb2e8f9f7 116 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
<> 144:ef7eb2e8f9f7 117 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
<> 144:ef7eb2e8f9f7 118 If set to external trigger source, triggering is on event rising edge.
<> 144:ef7eb2e8f9f7 119 This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
<> 144:ef7eb2e8f9f7 120 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
<> 144:ef7eb2e8f9f7 121 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
<> 144:ef7eb2e8f9f7 122 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<> 144:ef7eb2e8f9f7 123 configure a channel on injected group can impact the configuration of other channels previously set. */
<> 144:ef7eb2e8f9f7 124 }ADC_InjectionConfTypeDef;
<> 144:ef7eb2e8f9f7 125
AnnaBridge 165:e614a9f1c9e2 126 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @brief Structure definition of ADC multimode
<> 144:ef7eb2e8f9f7 129 * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
<> 144:ef7eb2e8f9f7 130 * State of ADCs of the common group must be: disabled.
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 typedef struct
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
<> 144:ef7eb2e8f9f7 135 This parameter can be a value of @ref ADCEx_Common_mode
<> 144:ef7eb2e8f9f7 136 Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change.
<> 144:ef7eb2e8f9f7 137 Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2.
<> 144:ef7eb2e8f9f7 138 Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode.
<> 144:ef7eb2e8f9f7 139 Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters).
<> 144:ef7eb2e8f9f7 140 The equivalences are:
<> 144:ef7eb2e8f9f7 141 - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
<> 144:ef7eb2e8f9f7 142 - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 }ADC_MultiModeTypeDef;
AnnaBridge 165:e614a9f1c9e2 146 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /**
<> 144:ef7eb2e8f9f7 149 * @}
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
<> 144:ef7eb2e8f9f7 156 * @{
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /** @defgroup ADCEx_injected_rank ADCEx rank into injected group
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
AnnaBridge 165:e614a9f1c9e2 162 #define ADC_INJECTED_RANK_1 0x00000001U
AnnaBridge 165:e614a9f1c9e2 163 #define ADC_INJECTED_RANK_2 0x00000002U
AnnaBridge 165:e614a9f1c9e2 164 #define ADC_INJECTED_RANK_3 0x00000003U
AnnaBridge 165:e614a9f1c9e2 165 #define ADC_INJECTED_RANK_4 0x00000004U
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
<> 144:ef7eb2e8f9f7 171 * @{
<> 144:ef7eb2e8f9f7 172 */
AnnaBridge 165:e614a9f1c9e2 173 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U
<> 144:ef7eb2e8f9f7 174 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @}
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 /*!< List of external triggers with generic trigger name, independently of */
<> 144:ef7eb2e8f9f7 183 /* ADC target, sorted by trigger name: */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /*!< External triggers of regular group for ADC1&ADC2 only */
<> 144:ef7eb2e8f9f7 186 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
<> 144:ef7eb2e8f9f7 187 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
<> 144:ef7eb2e8f9f7 188 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
<> 144:ef7eb2e8f9f7 189 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
<> 144:ef7eb2e8f9f7 190 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
<> 144:ef7eb2e8f9f7 191 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 #if defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 194 /*!< External triggers of regular group for ADC3 only */
<> 144:ef7eb2e8f9f7 195 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3
<> 144:ef7eb2e8f9f7 196 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1
<> 144:ef7eb2e8f9f7 197 #define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1
<> 144:ef7eb2e8f9f7 198 #define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3
<> 144:ef7eb2e8f9f7 199 #define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1
<> 144:ef7eb2e8f9f7 200 #endif /* STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /*!< External triggers of regular group for all ADC instances */
<> 144:ef7eb2e8f9f7 203 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
<> 144:ef7eb2e8f9f7 204
AnnaBridge 165:e614a9f1c9e2 205 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 206 /*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
<> 144:ef7eb2e8f9f7 207 /* XL-density devices. */
<> 144:ef7eb2e8f9f7 208 /* To use it on ADC or ADC2, a remap of trigger must be done from */
<> 144:ef7eb2e8f9f7 209 /* EXTI line 11 to TIM8_TRGO with macro: */
<> 144:ef7eb2e8f9f7 210 /* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */
<> 144:ef7eb2e8f9f7 211 /* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Note for internal constant value management: If TIM8_TRGO is available, */
<> 144:ef7eb2e8f9f7 214 /* its definition is set to value for ADC1&ADC2 by default and changed to */
<> 144:ef7eb2e8f9f7 215 /* value for ADC3 by HAL ADC driver if ADC3 is selected. */
<> 144:ef7eb2e8f9f7 216 #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
AnnaBridge 165:e614a9f1c9e2 217 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 #define ADC_SOFTWARE_START ADC1_2_3_SWSTART
<> 144:ef7eb2e8f9f7 220 /**
<> 144:ef7eb2e8f9f7 221 * @}
<> 144:ef7eb2e8f9f7 222 */
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
<> 144:ef7eb2e8f9f7 225 * @{
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 /*!< List of external triggers with generic trigger name, independently of */
<> 144:ef7eb2e8f9f7 228 /* ADC target, sorted by trigger name: */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /*!< External triggers of injected group for ADC1&ADC2 only */
<> 144:ef7eb2e8f9f7 231 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
<> 144:ef7eb2e8f9f7 232 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
<> 144:ef7eb2e8f9f7 233 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
<> 144:ef7eb2e8f9f7 234 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
<> 144:ef7eb2e8f9f7 235 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #if defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 238 /*!< External triggers of injected group for ADC3 only */
<> 144:ef7eb2e8f9f7 239 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3
<> 144:ef7eb2e8f9f7 240 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2
<> 144:ef7eb2e8f9f7 241 #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO
<> 144:ef7eb2e8f9f7 242 #define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4
<> 144:ef7eb2e8f9f7 243 #endif /* STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /*!< External triggers of injected group for all ADC instances */
<> 144:ef7eb2e8f9f7 246 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
<> 144:ef7eb2e8f9f7 247 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
<> 144:ef7eb2e8f9f7 248
AnnaBridge 165:e614a9f1c9e2 249 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 250 /*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
<> 144:ef7eb2e8f9f7 251 /* XL-density devices. */
<> 144:ef7eb2e8f9f7 252 /* To use it on ADC1 or ADC2, a remap of trigger must be done from */
<> 144:ef7eb2e8f9f7 253 /* EXTI line 11 to TIM8_CC4 with macro: */
<> 144:ef7eb2e8f9f7 254 /* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */
<> 144:ef7eb2e8f9f7 255 /* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Note for internal constant value management: If TIM8_CC4 is available, */
<> 144:ef7eb2e8f9f7 258 /* its definition is set to value for ADC1&ADC2 by default and changed to */
<> 144:ef7eb2e8f9f7 259 /* value for ADC3 by HAL ADC driver if ADC3 is selected. */
<> 144:ef7eb2e8f9f7 260 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
AnnaBridge 165:e614a9f1c9e2 261 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 #define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @}
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267
AnnaBridge 165:e614a9f1c9e2 268 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 269 /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
<> 144:ef7eb2e8f9f7 270 * @{
<> 144:ef7eb2e8f9f7 271 */
AnnaBridge 165:e614a9f1c9e2 272 #define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
<> 144:ef7eb2e8f9f7 273 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
<> 144:ef7eb2e8f9f7 274 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
<> 144:ef7eb2e8f9f7 275 #define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
<> 144:ef7eb2e8f9f7 276 #define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
<> 144:ef7eb2e8f9f7 277 #define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
<> 144:ef7eb2e8f9f7 278 #define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
<> 144:ef7eb2e8f9f7 279 #define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
<> 144:ef7eb2e8f9f7 280 #define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
<> 144:ef7eb2e8f9f7 281 #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @}
<> 144:ef7eb2e8f9f7 284 */
AnnaBridge 165:e614a9f1c9e2 285 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
<> 144:ef7eb2e8f9f7 295 * @{
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
<> 144:ef7eb2e8f9f7 299 * @{
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 /* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */
<> 144:ef7eb2e8f9f7 302 /* instance is available on the selected device). */
<> 144:ef7eb2e8f9f7 303 /* (used internally by HAL driver. To not use into HAL structure parameters) */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
AnnaBridge 165:e614a9f1c9e2 306 #define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U
<> 144:ef7eb2e8f9f7 307 #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 308 #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 309 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 ))
<> 144:ef7eb2e8f9f7 310 #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 311 #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
AnnaBridge 165:e614a9f1c9e2 312 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 313 /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
<> 144:ef7eb2e8f9f7 314 /* XL-density devices. */
<> 144:ef7eb2e8f9f7 315 #define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
<> 144:ef7eb2e8f9f7 316 #endif
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 #if defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 319 /* External triggers of regular group for ADC3 */
<> 144:ef7eb2e8f9f7 320 #define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
<> 144:ef7eb2e8f9f7 321 #define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2
<> 144:ef7eb2e8f9f7 322 #define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2
<> 144:ef7eb2e8f9f7 323 #define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
<> 144:ef7eb2e8f9f7 324 #define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4
<> 144:ef7eb2e8f9f7 325 #define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11
<> 144:ef7eb2e8f9f7 326 #endif
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
<> 144:ef7eb2e8f9f7 329 #define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
<> 144:ef7eb2e8f9f7 330 #define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @}
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
<> 144:ef7eb2e8f9f7 336 * @{
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338 /* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */
<> 144:ef7eb2e8f9f7 339 /* instance is available on the selected device). */
<> 144:ef7eb2e8f9f7 340 /* (used internally by HAL driver. To not use into HAL structure parameters) */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
<> 144:ef7eb2e8f9f7 343 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
<> 144:ef7eb2e8f9f7 344 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
<> 144:ef7eb2e8f9f7 345 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 ))
<> 144:ef7eb2e8f9f7 346 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
<> 144:ef7eb2e8f9f7 347 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
AnnaBridge 165:e614a9f1c9e2 348 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 349 /* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
<> 144:ef7eb2e8f9f7 350 /* XL-density devices. */
<> 144:ef7eb2e8f9f7 351 #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
<> 144:ef7eb2e8f9f7 352 #endif
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 #if defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 355 /* External triggers of injected group for ADC3 */
<> 144:ef7eb2e8f9f7 356 #define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
<> 144:ef7eb2e8f9f7 357 #define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
<> 144:ef7eb2e8f9f7 358 #define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
<> 144:ef7eb2e8f9f7 359 #define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
<> 144:ef7eb2e8f9f7 360 #define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
<> 144:ef7eb2e8f9f7 361 #endif /* STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
AnnaBridge 165:e614a9f1c9e2 364 #define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
<> 144:ef7eb2e8f9f7 365 #define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0))
<> 144:ef7eb2e8f9f7 366 #define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
<> 144:ef7eb2e8f9f7 367 /**
<> 144:ef7eb2e8f9f7 368 * @}
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @}
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /** @defgroup ADCEx_Private_Macro ADCEx Private Macro
<> 144:ef7eb2e8f9f7 381 * @{
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 /* Macro reserved for internal HAL driver usage, not intended to be used in */
<> 144:ef7eb2e8f9f7 384 /* code of final user. */
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @brief For devices with 3 ADCs: Defines the external trigger source
<> 144:ef7eb2e8f9f7 389 * for regular group according to ADC into common group ADC1&ADC2 or
<> 144:ef7eb2e8f9f7 390 * ADC3 (some triggers with same source have different value to
<> 144:ef7eb2e8f9f7 391 * be programmed into ADC EXTSEL bits of CR2 register).
<> 144:ef7eb2e8f9f7 392 * For devices with 2 ADCs or less: this macro makes no change.
<> 144:ef7eb2e8f9f7 393 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 394 * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
<> 144:ef7eb2e8f9f7 395 * @retval External trigger to be programmed into EXTSEL bits of CR2 register
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397 #if defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 398 #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
<> 144:ef7eb2e8f9f7 399 (( (((__HANDLE__)->Instance) == ADC3) \
<> 144:ef7eb2e8f9f7 400 )? \
<> 144:ef7eb2e8f9f7 401 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
<> 144:ef7eb2e8f9f7 402 )? \
<> 144:ef7eb2e8f9f7 403 (ADC3_EXTERNALTRIG_T8_TRGO) \
<> 144:ef7eb2e8f9f7 404 : \
<> 144:ef7eb2e8f9f7 405 (__EXT_TRIG_CONV__) \
<> 144:ef7eb2e8f9f7 406 ) \
<> 144:ef7eb2e8f9f7 407 : \
<> 144:ef7eb2e8f9f7 408 (__EXT_TRIG_CONV__) \
<> 144:ef7eb2e8f9f7 409 )
<> 144:ef7eb2e8f9f7 410 #else
<> 144:ef7eb2e8f9f7 411 #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
<> 144:ef7eb2e8f9f7 412 (__EXT_TRIG_CONV__)
<> 144:ef7eb2e8f9f7 413 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @brief For devices with 3 ADCs: Defines the external trigger source
<> 144:ef7eb2e8f9f7 417 * for injected group according to ADC into common group ADC1&ADC2 or
<> 144:ef7eb2e8f9f7 418 * ADC3 (some triggers with same source have different value to
<> 144:ef7eb2e8f9f7 419 * be programmed into ADC JEXTSEL bits of CR2 register).
<> 144:ef7eb2e8f9f7 420 * For devices with 2 ADCs or less: this macro makes no change.
<> 144:ef7eb2e8f9f7 421 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 422 * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
<> 144:ef7eb2e8f9f7 423 * @retval External trigger to be programmed into JEXTSEL bits of CR2 register
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425 #if defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 426 #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
<> 144:ef7eb2e8f9f7 427 (( (((__HANDLE__)->Instance) == ADC3) \
<> 144:ef7eb2e8f9f7 428 )? \
<> 144:ef7eb2e8f9f7 429 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
<> 144:ef7eb2e8f9f7 430 )? \
<> 144:ef7eb2e8f9f7 431 (ADC3_EXTERNALTRIGINJEC_T8_CC4) \
<> 144:ef7eb2e8f9f7 432 : \
<> 144:ef7eb2e8f9f7 433 (__EXT_TRIG_INJECTCONV__) \
<> 144:ef7eb2e8f9f7 434 ) \
<> 144:ef7eb2e8f9f7 435 : \
<> 144:ef7eb2e8f9f7 436 (__EXT_TRIG_INJECTCONV__) \
<> 144:ef7eb2e8f9f7 437 )
<> 144:ef7eb2e8f9f7 438 #else
<> 144:ef7eb2e8f9f7 439 #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
<> 144:ef7eb2e8f9f7 440 (__EXT_TRIG_INJECTCONV__)
<> 144:ef7eb2e8f9f7 441 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /**
<> 144:ef7eb2e8f9f7 445 * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
<> 144:ef7eb2e8f9f7 446 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 447 * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
<> 144:ef7eb2e8f9f7 448 */
AnnaBridge 165:e614a9f1c9e2 449 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 450 #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 451 (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
<> 144:ef7eb2e8f9f7 452 )? \
<> 144:ef7eb2e8f9f7 453 (ADC1->CR1 & ADC_CR1_DUALMOD) \
<> 144:ef7eb2e8f9f7 454 : \
<> 144:ef7eb2e8f9f7 455 (RESET) \
<> 144:ef7eb2e8f9f7 456 )
<> 144:ef7eb2e8f9f7 457 #else
<> 144:ef7eb2e8f9f7 458 #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 459 (RESET)
AnnaBridge 165:e614a9f1c9e2 460 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
<> 144:ef7eb2e8f9f7 464 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 465 * @retval None
<> 144:ef7eb2e8f9f7 466 */
AnnaBridge 165:e614a9f1c9e2 467 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 468 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 469 (( (((__HANDLE__)->Instance) == ADC2) \
<> 144:ef7eb2e8f9f7 470 )? \
<> 144:ef7eb2e8f9f7 471 ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \
<> 144:ef7eb2e8f9f7 472 : \
<> 144:ef7eb2e8f9f7 473 (!RESET) \
<> 144:ef7eb2e8f9f7 474 )
<> 144:ef7eb2e8f9f7 475 #else
<> 144:ef7eb2e8f9f7 476 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 477 (!RESET)
AnnaBridge 165:e614a9f1c9e2 478 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
<> 144:ef7eb2e8f9f7 482 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 483 * @retval None
<> 144:ef7eb2e8f9f7 484 */
AnnaBridge 165:e614a9f1c9e2 485 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 486 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
<> 144:ef7eb2e8f9f7 487 (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
<> 144:ef7eb2e8f9f7 488 )? \
<> 144:ef7eb2e8f9f7 489 (ADC1->CR1 & ADC_CR1_JAUTO) \
<> 144:ef7eb2e8f9f7 490 : \
<> 144:ef7eb2e8f9f7 491 (RESET) \
<> 144:ef7eb2e8f9f7 492 )
<> 144:ef7eb2e8f9f7 493 #else
<> 144:ef7eb2e8f9f7 494 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
<> 144:ef7eb2e8f9f7 495 (RESET)
AnnaBridge 165:e614a9f1c9e2 496 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 497
AnnaBridge 165:e614a9f1c9e2 498 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 499 /**
<> 144:ef7eb2e8f9f7 500 * @brief Set handle of the other ADC sharing the common multimode settings
<> 144:ef7eb2e8f9f7 501 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 502 * @param __HANDLE_OTHER_ADC__: other ADC handle
<> 144:ef7eb2e8f9f7 503 * @retval None
<> 144:ef7eb2e8f9f7 504 */
<> 144:ef7eb2e8f9f7 505 #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
<> 144:ef7eb2e8f9f7 506 ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @brief Set handle of the ADC slave associated to the ADC master
<> 144:ef7eb2e8f9f7 510 * On STM32F1 devices, ADC slave is always ADC2 (this can be different
<> 144:ef7eb2e8f9f7 511 * on other STM32 devices)
<> 144:ef7eb2e8f9f7 512 * @param __HANDLE_MASTER__: ADC master handle
<> 144:ef7eb2e8f9f7 513 * @param __HANDLE_SLAVE__: ADC slave handle
<> 144:ef7eb2e8f9f7 514 * @retval None
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
<> 144:ef7eb2e8f9f7 517 ((__HANDLE_SLAVE__)->Instance = ADC2)
<> 144:ef7eb2e8f9f7 518
AnnaBridge 165:e614a9f1c9e2 519 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
<> 144:ef7eb2e8f9f7 522 ((CHANNEL) == ADC_INJECTED_RANK_2) || \
<> 144:ef7eb2e8f9f7 523 ((CHANNEL) == ADC_INJECTED_RANK_3) || \
AnnaBridge 165:e614a9f1c9e2 524 ((CHANNEL) == ADC_INJECTED_RANK_4))
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
AnnaBridge 165:e614a9f1c9e2 527 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
<> 144:ef7eb2e8f9f7 530 * @{
<> 144:ef7eb2e8f9f7 531 */
AnnaBridge 165:e614a9f1c9e2 532 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @}
<> 144:ef7eb2e8f9f7 535 */
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 538 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
<> 144:ef7eb2e8f9f7 539 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
<> 144:ef7eb2e8f9f7 540 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
<> 144:ef7eb2e8f9f7 541 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
<> 144:ef7eb2e8f9f7 542 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
<> 144:ef7eb2e8f9f7 543 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
AnnaBridge 165:e614a9f1c9e2 544 ((REGTRIG) == ADC_SOFTWARE_START))
<> 144:ef7eb2e8f9f7 545 #endif
AnnaBridge 165:e614a9f1c9e2 546 #if defined (STM32F101xE)
<> 144:ef7eb2e8f9f7 547 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
<> 144:ef7eb2e8f9f7 548 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
<> 144:ef7eb2e8f9f7 549 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
<> 144:ef7eb2e8f9f7 550 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
<> 144:ef7eb2e8f9f7 551 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
<> 144:ef7eb2e8f9f7 552 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
<> 144:ef7eb2e8f9f7 553 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
AnnaBridge 165:e614a9f1c9e2 554 ((REGTRIG) == ADC_SOFTWARE_START))
AnnaBridge 165:e614a9f1c9e2 555 #endif
AnnaBridge 165:e614a9f1c9e2 556 #if defined (STM32F101xG)
AnnaBridge 165:e614a9f1c9e2 557 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
AnnaBridge 165:e614a9f1c9e2 558 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
AnnaBridge 165:e614a9f1c9e2 559 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
AnnaBridge 165:e614a9f1c9e2 560 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
AnnaBridge 165:e614a9f1c9e2 561 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
AnnaBridge 165:e614a9f1c9e2 562 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
AnnaBridge 165:e614a9f1c9e2 563 ((REGTRIG) == ADC_SOFTWARE_START))
<> 144:ef7eb2e8f9f7 564 #endif
<> 144:ef7eb2e8f9f7 565 #if defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 566 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
<> 144:ef7eb2e8f9f7 567 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
<> 144:ef7eb2e8f9f7 568 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
<> 144:ef7eb2e8f9f7 569 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
<> 144:ef7eb2e8f9f7 570 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
<> 144:ef7eb2e8f9f7 571 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
<> 144:ef7eb2e8f9f7 572 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
<> 144:ef7eb2e8f9f7 573 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
<> 144:ef7eb2e8f9f7 574 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
<> 144:ef7eb2e8f9f7 575 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
<> 144:ef7eb2e8f9f7 576 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
<> 144:ef7eb2e8f9f7 577 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
<> 144:ef7eb2e8f9f7 578 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
AnnaBridge 165:e614a9f1c9e2 579 ((REGTRIG) == ADC_SOFTWARE_START))
<> 144:ef7eb2e8f9f7 580 #endif
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 583 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 584 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
<> 144:ef7eb2e8f9f7 585 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
<> 144:ef7eb2e8f9f7 586 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
<> 144:ef7eb2e8f9f7 587 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
<> 144:ef7eb2e8f9f7 588 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
<> 144:ef7eb2e8f9f7 589 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
AnnaBridge 165:e614a9f1c9e2 590 ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
<> 144:ef7eb2e8f9f7 591 #endif
AnnaBridge 165:e614a9f1c9e2 592 #if defined (STM32F101xE)
<> 144:ef7eb2e8f9f7 593 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 594 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
<> 144:ef7eb2e8f9f7 595 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
<> 144:ef7eb2e8f9f7 596 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
<> 144:ef7eb2e8f9f7 597 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
<> 144:ef7eb2e8f9f7 598 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
<> 144:ef7eb2e8f9f7 599 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
<> 144:ef7eb2e8f9f7 600 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
AnnaBridge 165:e614a9f1c9e2 601 ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
AnnaBridge 165:e614a9f1c9e2 602 #endif
AnnaBridge 165:e614a9f1c9e2 603 #if defined (STM32F101xG)
AnnaBridge 165:e614a9f1c9e2 604 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
AnnaBridge 165:e614a9f1c9e2 605 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
AnnaBridge 165:e614a9f1c9e2 606 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
AnnaBridge 165:e614a9f1c9e2 607 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
AnnaBridge 165:e614a9f1c9e2 608 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
AnnaBridge 165:e614a9f1c9e2 609 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
AnnaBridge 165:e614a9f1c9e2 610 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
AnnaBridge 165:e614a9f1c9e2 611 ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
<> 144:ef7eb2e8f9f7 612 #endif
<> 144:ef7eb2e8f9f7 613 #if defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 614 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 615 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
<> 144:ef7eb2e8f9f7 616 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
<> 144:ef7eb2e8f9f7 617 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
<> 144:ef7eb2e8f9f7 618 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
<> 144:ef7eb2e8f9f7 619 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
<> 144:ef7eb2e8f9f7 620 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
<> 144:ef7eb2e8f9f7 621 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
<> 144:ef7eb2e8f9f7 622 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
<> 144:ef7eb2e8f9f7 623 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
<> 144:ef7eb2e8f9f7 624 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
<> 144:ef7eb2e8f9f7 625 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
<> 144:ef7eb2e8f9f7 626 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
AnnaBridge 165:e614a9f1c9e2 627 ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
<> 144:ef7eb2e8f9f7 628 #endif
<> 144:ef7eb2e8f9f7 629
AnnaBridge 165:e614a9f1c9e2 630 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 631 #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
<> 144:ef7eb2e8f9f7 632 ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
<> 144:ef7eb2e8f9f7 633 ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
<> 144:ef7eb2e8f9f7 634 ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
<> 144:ef7eb2e8f9f7 635 ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
<> 144:ef7eb2e8f9f7 636 ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
<> 144:ef7eb2e8f9f7 637 ((MODE) == ADC_DUALMODE_REGSIMULT) || \
<> 144:ef7eb2e8f9f7 638 ((MODE) == ADC_DUALMODE_INTERLFAST) || \
<> 144:ef7eb2e8f9f7 639 ((MODE) == ADC_DUALMODE_INTERLSLOW) || \
AnnaBridge 165:e614a9f1c9e2 640 ((MODE) == ADC_DUALMODE_ALTERTRIG) )
AnnaBridge 165:e614a9f1c9e2 641 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /**
<> 144:ef7eb2e8f9f7 644 * @}
<> 144:ef7eb2e8f9f7 645 */
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 653 /** @addtogroup ADCEx_Exported_Functions
<> 144:ef7eb2e8f9f7 654 * @{
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 658 /** @addtogroup ADCEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 659 * @{
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* ADC calibration */
<> 144:ef7eb2e8f9f7 663 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 666 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 667 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 668 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Non-blocking mode: Interruption */
<> 144:ef7eb2e8f9f7 671 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 672 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 673
AnnaBridge 165:e614a9f1c9e2 674 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 675 /* ADC multimode */
<> 144:ef7eb2e8f9f7 676 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 677 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
AnnaBridge 165:e614a9f1c9e2 678 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* ADC retrieve conversion value intended to be used with polling or interruption */
<> 144:ef7eb2e8f9f7 681 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
AnnaBridge 165:e614a9f1c9e2 682 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 683 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
AnnaBridge 165:e614a9f1c9e2 684 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
<> 144:ef7eb2e8f9f7 687 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 688 /**
<> 144:ef7eb2e8f9f7 689 * @}
<> 144:ef7eb2e8f9f7 690 */
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 694 /** @addtogroup ADCEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 695 * @{
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
AnnaBridge 165:e614a9f1c9e2 698 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
<> 144:ef7eb2e8f9f7 699 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
AnnaBridge 165:e614a9f1c9e2 700 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
<> 144:ef7eb2e8f9f7 701 /**
<> 144:ef7eb2e8f9f7 702 * @}
<> 144:ef7eb2e8f9f7 703 */
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /**
<> 144:ef7eb2e8f9f7 707 * @}
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /**
<> 144:ef7eb2e8f9f7 712 * @}
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /**
<> 144:ef7eb2e8f9f7 716 * @}
<> 144:ef7eb2e8f9f7 717 */
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 #endif
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 #endif /* __STM32F1xx_HAL_ADC_EX_H */
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/