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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_usart.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_usart.c
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief USART LL module driver.
<> 156:95d6b41a828b 6 ******************************************************************************
<> 156:95d6b41a828b 7 * @attention
<> 156:95d6b41a828b 8 *
<> 156:95d6b41a828b 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 12 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 14 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 17 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 19 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 20 * without specific prior written permission.
<> 156:95d6b41a828b 21 *
<> 156:95d6b41a828b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 32 *
<> 156:95d6b41a828b 33 ******************************************************************************
<> 156:95d6b41a828b 34 */
<> 156:95d6b41a828b 35 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 36
<> 156:95d6b41a828b 37 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 38 #include "stm32f0xx_ll_usart.h"
<> 156:95d6b41a828b 39 #include "stm32f0xx_ll_rcc.h"
<> 156:95d6b41a828b 40 #include "stm32f0xx_ll_bus.h"
<> 156:95d6b41a828b 41 #ifdef USE_FULL_ASSERT
<> 156:95d6b41a828b 42 #include "stm32_assert.h"
<> 156:95d6b41a828b 43 #else
<> 156:95d6b41a828b 44 #define assert_param(expr) ((void)0U)
<> 156:95d6b41a828b 45 #endif
<> 156:95d6b41a828b 46
<> 156:95d6b41a828b 47 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 48 * @{
<> 156:95d6b41a828b 49 */
<> 156:95d6b41a828b 50
<> 156:95d6b41a828b 51 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6) || defined (USART7) || defined (USART8)
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 /** @addtogroup USART_LL
<> 156:95d6b41a828b 54 * @{
<> 156:95d6b41a828b 55 */
<> 156:95d6b41a828b 56
<> 156:95d6b41a828b 57 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 58 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 59 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 60 /** @addtogroup USART_LL_Private_Constants
<> 156:95d6b41a828b 61 * @{
<> 156:95d6b41a828b 62 */
<> 156:95d6b41a828b 63
<> 156:95d6b41a828b 64 /**
<> 156:95d6b41a828b 65 * @}
<> 156:95d6b41a828b 66 */
<> 156:95d6b41a828b 67
<> 156:95d6b41a828b 68
<> 156:95d6b41a828b 69 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 70 /** @addtogroup USART_LL_Private_Macros
<> 156:95d6b41a828b 71 * @{
<> 156:95d6b41a828b 72 */
<> 156:95d6b41a828b 73
<> 156:95d6b41a828b 74 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
<> 156:95d6b41a828b 75 * divided by the smallest oversampling used on the USART (i.e. 8) */
<> 156:95d6b41a828b 76 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U)
<> 156:95d6b41a828b 77
Anna Bridge 180:96ed750bd169 78 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
Anna Bridge 180:96ed750bd169 79 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
Anna Bridge 180:96ed750bd169 80
Anna Bridge 180:96ed750bd169 81 /* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
Anna Bridge 180:96ed750bd169 82 #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
Anna Bridge 180:96ed750bd169 83
<> 156:95d6b41a828b 84 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
<> 156:95d6b41a828b 85 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
<> 156:95d6b41a828b 86 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
<> 156:95d6b41a828b 87 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
<> 156:95d6b41a828b 88
<> 156:95d6b41a828b 89 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
<> 156:95d6b41a828b 90 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
<> 156:95d6b41a828b 91 || ((__VALUE__) == LL_USART_PARITY_ODD))
<> 156:95d6b41a828b 92
<> 156:95d6b41a828b 93 #if defined(USART_7BITS_SUPPORT)
<> 156:95d6b41a828b 94 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
<> 156:95d6b41a828b 95 || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
<> 156:95d6b41a828b 96 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
<> 156:95d6b41a828b 97 #else
<> 156:95d6b41a828b 98 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
<> 156:95d6b41a828b 99 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
<> 156:95d6b41a828b 100 #endif
<> 156:95d6b41a828b 101
<> 156:95d6b41a828b 102 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
<> 156:95d6b41a828b 103 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
<> 156:95d6b41a828b 104
<> 156:95d6b41a828b 105 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
<> 156:95d6b41a828b 106 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
<> 156:95d6b41a828b 107
<> 156:95d6b41a828b 108 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
<> 156:95d6b41a828b 109 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
<> 156:95d6b41a828b 110
<> 156:95d6b41a828b 111 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
<> 156:95d6b41a828b 112 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
<> 156:95d6b41a828b 113
<> 156:95d6b41a828b 114 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
<> 156:95d6b41a828b 115 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
<> 156:95d6b41a828b 116
<> 156:95d6b41a828b 117 #if defined(USART_SMARTCARD_SUPPORT)
<> 156:95d6b41a828b 118 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
<> 156:95d6b41a828b 119 || ((__VALUE__) == LL_USART_STOPBITS_1) \
<> 156:95d6b41a828b 120 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
<> 156:95d6b41a828b 121 || ((__VALUE__) == LL_USART_STOPBITS_2))
<> 156:95d6b41a828b 122 #else
<> 156:95d6b41a828b 123 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_1) \
<> 156:95d6b41a828b 124 || ((__VALUE__) == LL_USART_STOPBITS_2))
<> 156:95d6b41a828b 125 #endif
<> 156:95d6b41a828b 126
<> 156:95d6b41a828b 127 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
<> 156:95d6b41a828b 128 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
<> 156:95d6b41a828b 129 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
<> 156:95d6b41a828b 130 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
<> 156:95d6b41a828b 131
<> 156:95d6b41a828b 132 /**
<> 156:95d6b41a828b 133 * @}
<> 156:95d6b41a828b 134 */
<> 156:95d6b41a828b 135
<> 156:95d6b41a828b 136 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 137
<> 156:95d6b41a828b 138 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 139 /** @addtogroup USART_LL_Exported_Functions
<> 156:95d6b41a828b 140 * @{
<> 156:95d6b41a828b 141 */
<> 156:95d6b41a828b 142
<> 156:95d6b41a828b 143 /** @addtogroup USART_LL_EF_Init
<> 156:95d6b41a828b 144 * @{
<> 156:95d6b41a828b 145 */
<> 156:95d6b41a828b 146
<> 156:95d6b41a828b 147 /**
<> 156:95d6b41a828b 148 * @brief De-initialize USART registers (Registers restored to their default values).
<> 156:95d6b41a828b 149 * @param USARTx USART Instance
<> 156:95d6b41a828b 150 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 151 * - SUCCESS: USART registers are de-initialized
<> 156:95d6b41a828b 152 * - ERROR: USART registers are not de-initialized
<> 156:95d6b41a828b 153 */
<> 156:95d6b41a828b 154 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
<> 156:95d6b41a828b 155 {
<> 156:95d6b41a828b 156 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 157
<> 156:95d6b41a828b 158 /* Check the parameters */
<> 156:95d6b41a828b 159 assert_param(IS_UART_INSTANCE(USARTx));
<> 156:95d6b41a828b 160
<> 156:95d6b41a828b 161 if (USARTx == USART1)
<> 156:95d6b41a828b 162 {
<> 156:95d6b41a828b 163 /* Force reset of USART clock */
<> 156:95d6b41a828b 164 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART1);
<> 156:95d6b41a828b 165
<> 156:95d6b41a828b 166 /* Release reset of USART clock */
<> 156:95d6b41a828b 167 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART1);
<> 156:95d6b41a828b 168 }
<> 156:95d6b41a828b 169 #if defined(USART2)
<> 156:95d6b41a828b 170 else if (USARTx == USART2)
<> 156:95d6b41a828b 171 {
<> 156:95d6b41a828b 172 /* Force reset of USART clock */
<> 156:95d6b41a828b 173 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
<> 156:95d6b41a828b 174
<> 156:95d6b41a828b 175 /* Release reset of USART clock */
<> 156:95d6b41a828b 176 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
<> 156:95d6b41a828b 177 }
<> 156:95d6b41a828b 178 #endif /* USART2 */
<> 156:95d6b41a828b 179 #if defined(USART3)
<> 156:95d6b41a828b 180 else if (USARTx == USART3)
<> 156:95d6b41a828b 181 {
<> 156:95d6b41a828b 182 /* Force reset of USART clock */
<> 156:95d6b41a828b 183 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
<> 156:95d6b41a828b 184
<> 156:95d6b41a828b 185 /* Release reset of USART clock */
<> 156:95d6b41a828b 186 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
<> 156:95d6b41a828b 187 }
<> 156:95d6b41a828b 188 #endif /* USART3 */
<> 156:95d6b41a828b 189 #if defined(USART4)
<> 156:95d6b41a828b 190 else if (USARTx == USART4)
<> 156:95d6b41a828b 191 {
<> 156:95d6b41a828b 192 /* Force reset of USART clock */
<> 156:95d6b41a828b 193 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
<> 156:95d6b41a828b 194
<> 156:95d6b41a828b 195 /* Release reset of USART clock */
<> 156:95d6b41a828b 196 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
<> 156:95d6b41a828b 197 }
<> 156:95d6b41a828b 198 #endif /* USART4 */
<> 156:95d6b41a828b 199 #if defined(USART5)
<> 156:95d6b41a828b 200 else if (USARTx == USART5)
<> 156:95d6b41a828b 201 {
<> 156:95d6b41a828b 202 /* Force reset of USART clock */
<> 156:95d6b41a828b 203 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
<> 156:95d6b41a828b 204
<> 156:95d6b41a828b 205 /* Release reset of USART clock */
<> 156:95d6b41a828b 206 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
<> 156:95d6b41a828b 207 }
<> 156:95d6b41a828b 208 #endif /* USART5 */
<> 156:95d6b41a828b 209 #if defined(USART6)
<> 156:95d6b41a828b 210 else if (USARTx == USART6)
<> 156:95d6b41a828b 211 {
<> 156:95d6b41a828b 212 /* Force reset of USART clock */
<> 156:95d6b41a828b 213 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART6);
<> 156:95d6b41a828b 214
<> 156:95d6b41a828b 215 /* Release reset of USART clock */
<> 156:95d6b41a828b 216 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART6);
<> 156:95d6b41a828b 217 }
<> 156:95d6b41a828b 218 #endif /* USART6 */
<> 156:95d6b41a828b 219 #if defined(USART7)
<> 156:95d6b41a828b 220 else if (USARTx == USART7)
<> 156:95d6b41a828b 221 {
<> 156:95d6b41a828b 222 /* Force reset of USART clock */
<> 156:95d6b41a828b 223 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART7);
<> 156:95d6b41a828b 224
<> 156:95d6b41a828b 225 /* Release reset of USART clock */
<> 156:95d6b41a828b 226 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART7);
<> 156:95d6b41a828b 227 }
<> 156:95d6b41a828b 228 #endif /* USART7 */
<> 156:95d6b41a828b 229 #if defined(USART8)
<> 156:95d6b41a828b 230 else if (USARTx == USART8)
<> 156:95d6b41a828b 231 {
<> 156:95d6b41a828b 232 /* Force reset of USART clock */
<> 156:95d6b41a828b 233 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART8);
<> 156:95d6b41a828b 234
<> 156:95d6b41a828b 235 /* Release reset of USART clock */
<> 156:95d6b41a828b 236 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART8);
<> 156:95d6b41a828b 237 }
<> 156:95d6b41a828b 238 #endif /* USART8 */
<> 156:95d6b41a828b 239 else
<> 156:95d6b41a828b 240 {
<> 156:95d6b41a828b 241 status = ERROR;
<> 156:95d6b41a828b 242 }
<> 156:95d6b41a828b 243
<> 156:95d6b41a828b 244 return (status);
<> 156:95d6b41a828b 245 }
<> 156:95d6b41a828b 246
<> 156:95d6b41a828b 247 /**
<> 156:95d6b41a828b 248 * @brief Initialize USART registers according to the specified
<> 156:95d6b41a828b 249 * parameters in USART_InitStruct.
<> 156:95d6b41a828b 250 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
<> 156:95d6b41a828b 251 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 156:95d6b41a828b 252 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
<> 156:95d6b41a828b 253 * @param USARTx USART Instance
Anna Bridge 180:96ed750bd169 254 * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
<> 156:95d6b41a828b 255 * that contains the configuration information for the specified USART peripheral.
<> 156:95d6b41a828b 256 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 257 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
<> 156:95d6b41a828b 258 * - ERROR: Problem occurred during USART Registers initialization
<> 156:95d6b41a828b 259 */
<> 156:95d6b41a828b 260 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
<> 156:95d6b41a828b 261 {
<> 156:95d6b41a828b 262 ErrorStatus status = ERROR;
<> 156:95d6b41a828b 263 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
<> 156:95d6b41a828b 264 #if defined(STM32F030x8) || defined(STM32F030xC) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
<> 156:95d6b41a828b 265 LL_RCC_ClocksTypeDef RCC_Clocks;
<> 156:95d6b41a828b 266 #endif
<> 156:95d6b41a828b 267
<> 156:95d6b41a828b 268 /* Check the parameters */
<> 156:95d6b41a828b 269 assert_param(IS_UART_INSTANCE(USARTx));
<> 156:95d6b41a828b 270 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
<> 156:95d6b41a828b 271 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
<> 156:95d6b41a828b 272 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
<> 156:95d6b41a828b 273 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
<> 156:95d6b41a828b 274 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
<> 156:95d6b41a828b 275 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
<> 156:95d6b41a828b 276 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
<> 156:95d6b41a828b 277
<> 156:95d6b41a828b 278 /* USART needs to be in disabled state, in order to be able to configure some bits in
<> 156:95d6b41a828b 279 CRx registers */
<> 156:95d6b41a828b 280 if (LL_USART_IsEnabled(USARTx) == 0U)
<> 156:95d6b41a828b 281 {
Anna Bridge 180:96ed750bd169 282 /*---------------------------- USART CR1 Configuration ---------------------
<> 156:95d6b41a828b 283 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
<> 156:95d6b41a828b 284 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
<> 156:95d6b41a828b 285 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
<> 156:95d6b41a828b 286 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
<> 156:95d6b41a828b 287 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
<> 156:95d6b41a828b 288 */
<> 156:95d6b41a828b 289 MODIFY_REG(USARTx->CR1,
<> 156:95d6b41a828b 290 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
<> 156:95d6b41a828b 291 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
<> 156:95d6b41a828b 292 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
<> 156:95d6b41a828b 293 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
<> 156:95d6b41a828b 294
Anna Bridge 180:96ed750bd169 295 /*---------------------------- USART CR2 Configuration ---------------------
<> 156:95d6b41a828b 296 * Configure USARTx CR2 (Stop bits) with parameters:
<> 156:95d6b41a828b 297 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
<> 156:95d6b41a828b 298 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
<> 156:95d6b41a828b 299 */
<> 156:95d6b41a828b 300 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
<> 156:95d6b41a828b 301
Anna Bridge 180:96ed750bd169 302 /*---------------------------- USART CR3 Configuration ---------------------
<> 156:95d6b41a828b 303 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
<> 156:95d6b41a828b 304 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
<> 156:95d6b41a828b 305 */
<> 156:95d6b41a828b 306 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
<> 156:95d6b41a828b 307
Anna Bridge 180:96ed750bd169 308 /*---------------------------- USART BRR Configuration ---------------------
<> 156:95d6b41a828b 309 * Retrieve Clock frequency used for USART Peripheral
<> 156:95d6b41a828b 310 */
<> 156:95d6b41a828b 311 if (USARTx == USART1)
<> 156:95d6b41a828b 312 {
<> 156:95d6b41a828b 313 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
<> 156:95d6b41a828b 314 }
<> 156:95d6b41a828b 315 #if defined(USART2)
<> 156:95d6b41a828b 316 else if (USARTx == USART2)
<> 156:95d6b41a828b 317 {
<> 156:95d6b41a828b 318 #if defined (RCC_CFGR3_USART2SW)
<> 156:95d6b41a828b 319 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
<> 156:95d6b41a828b 320 #else
<> 156:95d6b41a828b 321 /* USART2 clock is PCLK */
<> 156:95d6b41a828b 322 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 323 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 324 #endif
<> 156:95d6b41a828b 325 }
<> 156:95d6b41a828b 326 #endif /* USART2 */
<> 156:95d6b41a828b 327 #if defined(USART3)
<> 156:95d6b41a828b 328 else if (USARTx == USART3)
<> 156:95d6b41a828b 329 {
<> 156:95d6b41a828b 330 #if defined (RCC_CFGR3_USART3SW)
<> 156:95d6b41a828b 331 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
<> 156:95d6b41a828b 332 #else
<> 156:95d6b41a828b 333 /* USART3 clock is PCLK */
<> 156:95d6b41a828b 334 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 335 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 336 #endif
<> 156:95d6b41a828b 337 }
<> 156:95d6b41a828b 338 #endif /* USART3 */
<> 156:95d6b41a828b 339 #if defined(USART4)
<> 156:95d6b41a828b 340 else if (USARTx == USART4)
<> 156:95d6b41a828b 341 {
<> 156:95d6b41a828b 342 /* USART4 clock is PCLK */
<> 156:95d6b41a828b 343 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 344 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 345 }
<> 156:95d6b41a828b 346 #endif /* USART4 */
<> 156:95d6b41a828b 347 #if defined(USART5)
<> 156:95d6b41a828b 348 else if (USARTx == USART5)
<> 156:95d6b41a828b 349 {
<> 156:95d6b41a828b 350 /* USART5 clock is PCLK */
<> 156:95d6b41a828b 351 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 352 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 353 }
<> 156:95d6b41a828b 354 #endif /* USART5 */
<> 156:95d6b41a828b 355 #if defined(USART6)
<> 156:95d6b41a828b 356 else if (USARTx == USART6)
<> 156:95d6b41a828b 357 {
<> 156:95d6b41a828b 358 /* USART6 clock is PCLK */
<> 156:95d6b41a828b 359 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 360 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 361 }
<> 156:95d6b41a828b 362 #endif /* USART6 */
<> 156:95d6b41a828b 363 #if defined(USART7)
<> 156:95d6b41a828b 364 else if (USARTx == USART7)
<> 156:95d6b41a828b 365 {
<> 156:95d6b41a828b 366 /* USART7 clock is PCLK */
<> 156:95d6b41a828b 367 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 368 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 369 }
<> 156:95d6b41a828b 370 #endif /* USART7 */
<> 156:95d6b41a828b 371 #if defined(USART8)
<> 156:95d6b41a828b 372 else if (USARTx == USART8)
<> 156:95d6b41a828b 373 {
<> 156:95d6b41a828b 374 /* USART8 clock is PCLK */
<> 156:95d6b41a828b 375 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
<> 156:95d6b41a828b 376 periphclk = RCC_Clocks.PCLK1_Frequency;
<> 156:95d6b41a828b 377 }
<> 156:95d6b41a828b 378 #endif /* USART8 */
<> 156:95d6b41a828b 379 else
<> 156:95d6b41a828b 380 {
<> 156:95d6b41a828b 381 /* Nothing to do, as error code is already assigned to ERROR value */
<> 156:95d6b41a828b 382 }
<> 156:95d6b41a828b 383
<> 156:95d6b41a828b 384 /* Configure the USART Baud Rate :
<> 156:95d6b41a828b 385 - valid baud rate value (different from 0) is required
<> 156:95d6b41a828b 386 - Peripheral clock as returned by RCC service, should be valid (different from 0).
<> 156:95d6b41a828b 387 */
<> 156:95d6b41a828b 388 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
<> 156:95d6b41a828b 389 && (USART_InitStruct->BaudRate != 0U))
<> 156:95d6b41a828b 390 {
<> 156:95d6b41a828b 391 status = SUCCESS;
<> 156:95d6b41a828b 392 LL_USART_SetBaudRate(USARTx,
<> 156:95d6b41a828b 393 periphclk,
<> 156:95d6b41a828b 394 USART_InitStruct->OverSampling,
<> 156:95d6b41a828b 395 USART_InitStruct->BaudRate);
Anna Bridge 180:96ed750bd169 396
Anna Bridge 180:96ed750bd169 397 /* Check BRR is greater than or equal to 16d */
Anna Bridge 180:96ed750bd169 398 assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
Anna Bridge 180:96ed750bd169 399
Anna Bridge 180:96ed750bd169 400 /* Check BRR is greater than or equal to 16d */
Anna Bridge 180:96ed750bd169 401 assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
<> 156:95d6b41a828b 402 }
<> 156:95d6b41a828b 403 }
<> 156:95d6b41a828b 404 /* Endif (=> USART not in Disabled state => return ERROR) */
<> 156:95d6b41a828b 405
<> 156:95d6b41a828b 406 return (status);
<> 156:95d6b41a828b 407 }
<> 156:95d6b41a828b 408
<> 156:95d6b41a828b 409 /**
<> 156:95d6b41a828b 410 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
Anna Bridge 180:96ed750bd169 411 * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
<> 156:95d6b41a828b 412 * whose fields will be set to default values.
<> 156:95d6b41a828b 413 * @retval None
<> 156:95d6b41a828b 414 */
<> 156:95d6b41a828b 415
<> 156:95d6b41a828b 416 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
<> 156:95d6b41a828b 417 {
<> 156:95d6b41a828b 418 /* Set USART_InitStruct fields to default values */
<> 156:95d6b41a828b 419 USART_InitStruct->BaudRate = 9600U;
<> 156:95d6b41a828b 420 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
<> 156:95d6b41a828b 421 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
<> 156:95d6b41a828b 422 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
<> 156:95d6b41a828b 423 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
<> 156:95d6b41a828b 424 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
<> 156:95d6b41a828b 425 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
<> 156:95d6b41a828b 426 }
<> 156:95d6b41a828b 427
<> 156:95d6b41a828b 428 /**
<> 156:95d6b41a828b 429 * @brief Initialize USART Clock related settings according to the
<> 156:95d6b41a828b 430 * specified parameters in the USART_ClockInitStruct.
<> 156:95d6b41a828b 431 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
<> 156:95d6b41a828b 432 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 156:95d6b41a828b 433 * @param USARTx USART Instance
Anna Bridge 180:96ed750bd169 434 * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
<> 156:95d6b41a828b 435 * that contains the Clock configuration information for the specified USART peripheral.
<> 156:95d6b41a828b 436 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 437 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
<> 156:95d6b41a828b 438 * - ERROR: Problem occurred during USART Registers initialization
<> 156:95d6b41a828b 439 */
<> 156:95d6b41a828b 440 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
<> 156:95d6b41a828b 441 {
<> 156:95d6b41a828b 442 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 443
<> 156:95d6b41a828b 444 /* Check USART Instance and Clock signal output parameters */
<> 156:95d6b41a828b 445 assert_param(IS_UART_INSTANCE(USARTx));
<> 156:95d6b41a828b 446 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
<> 156:95d6b41a828b 447
<> 156:95d6b41a828b 448 /* USART needs to be in disabled state, in order to be able to configure some bits in
<> 156:95d6b41a828b 449 CRx registers */
<> 156:95d6b41a828b 450 if (LL_USART_IsEnabled(USARTx) == 0U)
<> 156:95d6b41a828b 451 {
<> 156:95d6b41a828b 452 /*---------------------------- USART CR2 Configuration -----------------------*/
<> 156:95d6b41a828b 453 /* If Clock signal has to be output */
<> 156:95d6b41a828b 454 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
<> 156:95d6b41a828b 455 {
<> 156:95d6b41a828b 456 /* Deactivate Clock signal delivery :
<> 156:95d6b41a828b 457 * - Disable Clock Output: USART_CR2_CLKEN cleared
<> 156:95d6b41a828b 458 */
<> 156:95d6b41a828b 459 LL_USART_DisableSCLKOutput(USARTx);
<> 156:95d6b41a828b 460 }
<> 156:95d6b41a828b 461 else
<> 156:95d6b41a828b 462 {
<> 156:95d6b41a828b 463 /* Ensure USART instance is USART capable */
<> 156:95d6b41a828b 464 assert_param(IS_USART_INSTANCE(USARTx));
<> 156:95d6b41a828b 465
<> 156:95d6b41a828b 466 /* Check clock related parameters */
<> 156:95d6b41a828b 467 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
<> 156:95d6b41a828b 468 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
<> 156:95d6b41a828b 469 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
<> 156:95d6b41a828b 470
<> 156:95d6b41a828b 471 /*---------------------------- USART CR2 Configuration -----------------------
<> 156:95d6b41a828b 472 * Configure USARTx CR2 (Clock signal related bits) with parameters:
<> 156:95d6b41a828b 473 * - Enable Clock Output: USART_CR2_CLKEN set
<> 156:95d6b41a828b 474 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
<> 156:95d6b41a828b 475 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
<> 156:95d6b41a828b 476 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
<> 156:95d6b41a828b 477 */
<> 156:95d6b41a828b 478 MODIFY_REG(USARTx->CR2,
<> 156:95d6b41a828b 479 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
<> 156:95d6b41a828b 480 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
<> 156:95d6b41a828b 481 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
<> 156:95d6b41a828b 482 }
<> 156:95d6b41a828b 483 }
<> 156:95d6b41a828b 484 /* Else (USART not in Disabled state => return ERROR */
<> 156:95d6b41a828b 485 else
<> 156:95d6b41a828b 486 {
<> 156:95d6b41a828b 487 status = ERROR;
<> 156:95d6b41a828b 488 }
<> 156:95d6b41a828b 489
<> 156:95d6b41a828b 490 return (status);
<> 156:95d6b41a828b 491 }
<> 156:95d6b41a828b 492
<> 156:95d6b41a828b 493 /**
<> 156:95d6b41a828b 494 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
Anna Bridge 180:96ed750bd169 495 * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
<> 156:95d6b41a828b 496 * whose fields will be set to default values.
<> 156:95d6b41a828b 497 * @retval None
<> 156:95d6b41a828b 498 */
<> 156:95d6b41a828b 499 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
<> 156:95d6b41a828b 500 {
<> 156:95d6b41a828b 501 /* Set LL_USART_ClockInitStruct fields with default values */
<> 156:95d6b41a828b 502 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
<> 156:95d6b41a828b 503 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 156:95d6b41a828b 504 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 156:95d6b41a828b 505 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 156:95d6b41a828b 506 }
<> 156:95d6b41a828b 507
<> 156:95d6b41a828b 508 /**
<> 156:95d6b41a828b 509 * @}
<> 156:95d6b41a828b 510 */
<> 156:95d6b41a828b 511
<> 156:95d6b41a828b 512 /**
<> 156:95d6b41a828b 513 * @}
<> 156:95d6b41a828b 514 */
<> 156:95d6b41a828b 515
<> 156:95d6b41a828b 516 /**
<> 156:95d6b41a828b 517 * @}
<> 156:95d6b41a828b 518 */
<> 156:95d6b41a828b 519
<> 156:95d6b41a828b 520 #endif /* USART1 || USART2|| USART3 || USART4 || USART5 || USART6 || USART7 || USART8 */
<> 156:95d6b41a828b 521
<> 156:95d6b41a828b 522 /**
<> 156:95d6b41a828b 523 * @}
<> 156:95d6b41a828b 524 */
<> 156:95d6b41a828b 525
<> 156:95d6b41a828b 526 #endif /* USE_FULL_LL_DRIVER */
<> 156:95d6b41a828b 527
<> 156:95d6b41a828b 528 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 156:95d6b41a828b 529