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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 180:96ed750bd169

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	156:95d6b41a828b	1	/**
<>	156:95d6b41a828b	2	******************************************************************************
<>	156:95d6b41a828b	3	* @file stm32f0xx_ll_tim.c
<>	156:95d6b41a828b	4	* @author MCD Application Team
<>	156:95d6b41a828b	5	* @brief TIM LL module driver.
<>	156:95d6b41a828b	6	******************************************************************************
<>	156:95d6b41a828b	7	* @attention
<>	156:95d6b41a828b	8	*
<>	156:95d6b41a828b	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	156:95d6b41a828b	10	*
<>	156:95d6b41a828b	11	* Redistribution and use in source and binary forms, with or without modification,
<>	156:95d6b41a828b	12	* are permitted provided that the following conditions are met:
<>	156:95d6b41a828b	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	156:95d6b41a828b	14	* this list of conditions and the following disclaimer.
<>	156:95d6b41a828b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	156:95d6b41a828b	16	* this list of conditions and the following disclaimer in the documentation
<>	156:95d6b41a828b	17	* and/or other materials provided with the distribution.
<>	156:95d6b41a828b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	156:95d6b41a828b	19	* may be used to endorse or promote products derived from this software
<>	156:95d6b41a828b	20	* without specific prior written permission.
<>	156:95d6b41a828b	21	*
<>	156:95d6b41a828b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	156:95d6b41a828b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	156:95d6b41a828b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	156:95d6b41a828b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	156:95d6b41a828b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	156:95d6b41a828b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	156:95d6b41a828b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	156:95d6b41a828b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	156:95d6b41a828b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	156:95d6b41a828b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	156:95d6b41a828b	32	*
<>	156:95d6b41a828b	33	******************************************************************************
<>	156:95d6b41a828b	34	*/
<>	156:95d6b41a828b	35	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	36
<>	156:95d6b41a828b	37	/* Includes ------------------------------------------------------------------*/
<>	156:95d6b41a828b	38	#include "stm32f0xx_ll_tim.h"
<>	156:95d6b41a828b	39	#include "stm32f0xx_ll_bus.h"
<>	156:95d6b41a828b	40
<>	156:95d6b41a828b	41	#ifdef USE_FULL_ASSERT
<>	156:95d6b41a828b	42	#include "stm32_assert.h"
<>	156:95d6b41a828b	43	#else
<>	156:95d6b41a828b	44	#define assert_param(expr) ((void)0U)
<>	156:95d6b41a828b	45	#endif
<>	156:95d6b41a828b	46
<>	156:95d6b41a828b	47	/** @addtogroup STM32F0xx_LL_Driver
<>	156:95d6b41a828b	48	* @{
<>	156:95d6b41a828b	49	*/
<>	156:95d6b41a828b	50
<>	156:95d6b41a828b	51	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
<>	156:95d6b41a828b	52
<>	156:95d6b41a828b	53	/** @addtogroup TIM_LL
<>	156:95d6b41a828b	54	* @{
<>	156:95d6b41a828b	55	*/
<>	156:95d6b41a828b	56
<>	156:95d6b41a828b	57	/* Private types -------------------------------------------------------------*/
<>	156:95d6b41a828b	58	/* Private variables ---------------------------------------------------------*/
<>	156:95d6b41a828b	59	/* Private constants ---------------------------------------------------------*/
<>	156:95d6b41a828b	60	/* Private macros ------------------------------------------------------------*/
<>	156:95d6b41a828b	61	/** @addtogroup TIM_LL_Private_Macros
<>	156:95d6b41a828b	62	* @{
<>	156:95d6b41a828b	63	*/
<>	156:95d6b41a828b	64	#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
<>	156:95d6b41a828b	65	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
<>	156:95d6b41a828b	66	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
<>	156:95d6b41a828b	67	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
<>	156:95d6b41a828b	68	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
<>	156:95d6b41a828b	69
<>	156:95d6b41a828b	70	#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
<>	156:95d6b41a828b	71	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
<>	156:95d6b41a828b	72	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
<>	156:95d6b41a828b	73
<>	156:95d6b41a828b	74	#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
<>	156:95d6b41a828b	75	\|\| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
<>	156:95d6b41a828b	76	\|\| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
<>	156:95d6b41a828b	77	\|\| ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
<>	156:95d6b41a828b	78	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
<>	156:95d6b41a828b	79	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
<>	156:95d6b41a828b	80	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
<>	156:95d6b41a828b	81	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM2))
<>	156:95d6b41a828b	82
<>	156:95d6b41a828b	83	#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
<>	156:95d6b41a828b	84	\|\| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
<>	156:95d6b41a828b	85
<>	156:95d6b41a828b	86	#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
<>	156:95d6b41a828b	87	\|\| ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
<>	156:95d6b41a828b	88
<>	156:95d6b41a828b	89	#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
<>	156:95d6b41a828b	90	\|\| ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
<>	156:95d6b41a828b	91
<>	156:95d6b41a828b	92	#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
<>	156:95d6b41a828b	93	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
<>	156:95d6b41a828b	94	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
<>	156:95d6b41a828b	95
<>	156:95d6b41a828b	96	#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
<>	156:95d6b41a828b	97	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
<>	156:95d6b41a828b	98	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
<>	156:95d6b41a828b	99	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV8))
<>	156:95d6b41a828b	100
<>	156:95d6b41a828b	101	#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
<>	156:95d6b41a828b	102	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
<>	156:95d6b41a828b	103	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
<>	156:95d6b41a828b	104	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
<>	156:95d6b41a828b	105	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
<>	156:95d6b41a828b	106	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
<>	156:95d6b41a828b	107	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
<>	156:95d6b41a828b	108	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
<>	156:95d6b41a828b	109	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
<>	156:95d6b41a828b	110	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
<>	156:95d6b41a828b	111	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
<>	156:95d6b41a828b	112	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
<>	156:95d6b41a828b	113	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
<>	156:95d6b41a828b	114	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
<>	156:95d6b41a828b	115	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
<>	156:95d6b41a828b	116	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
<>	156:95d6b41a828b	117
<>	156:95d6b41a828b	118	#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
<>	156:95d6b41a828b	119	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
<>	156:95d6b41a828b	120	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
<>	156:95d6b41a828b	121
<>	156:95d6b41a828b	122	#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
<>	156:95d6b41a828b	123	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
<>	156:95d6b41a828b	124	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
<>	156:95d6b41a828b	125
<>	156:95d6b41a828b	126	#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
<>	156:95d6b41a828b	127	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
Anna Bridge	180:96ed750bd169	128
Anna Bridge	180:96ed750bd169	129	#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
Anna Bridge	180:96ed750bd169	130	\|\| ((__VALUE__) == LL_TIM_OSSR_ENABLE))
Anna Bridge	180:96ed750bd169	131
Anna Bridge	180:96ed750bd169	132	#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
Anna Bridge	180:96ed750bd169	133	\|\| ((__VALUE__) == LL_TIM_OSSI_ENABLE))
Anna Bridge	180:96ed750bd169	134
Anna Bridge	180:96ed750bd169	135	#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
Anna Bridge	180:96ed750bd169	136	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
Anna Bridge	180:96ed750bd169	137	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
Anna Bridge	180:96ed750bd169	138	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
Anna Bridge	180:96ed750bd169	139
Anna Bridge	180:96ed750bd169	140	#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
Anna Bridge	180:96ed750bd169	141	\|\| ((__VALUE__) == LL_TIM_BREAK_ENABLE))
Anna Bridge	180:96ed750bd169	142
Anna Bridge	180:96ed750bd169	143	#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
Anna Bridge	180:96ed750bd169	144	\|\| ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
Anna Bridge	180:96ed750bd169	145
Anna Bridge	180:96ed750bd169	146	#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
Anna Bridge	180:96ed750bd169	147	\|\| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
<>	156:95d6b41a828b	148	/**
<>	156:95d6b41a828b	149	* @}
<>	156:95d6b41a828b	150	*/
<>	156:95d6b41a828b	151
<>	156:95d6b41a828b	152
<>	156:95d6b41a828b	153	/* Private function prototypes -----------------------------------------------*/
<>	156:95d6b41a828b	154	/** @defgroup TIM_LL_Private_Functions TIM Private Functions
<>	156:95d6b41a828b	155	* @{
<>	156:95d6b41a828b	156	*/
<>	156:95d6b41a828b	157	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	156:95d6b41a828b	158	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	156:95d6b41a828b	159	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	156:95d6b41a828b	160	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	156:95d6b41a828b	161	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	156:95d6b41a828b	162	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	156:95d6b41a828b	163	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	156:95d6b41a828b	164	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	156:95d6b41a828b	165	/**
<>	156:95d6b41a828b	166	* @}
<>	156:95d6b41a828b	167	*/
<>	156:95d6b41a828b	168
<>	156:95d6b41a828b	169	/* Exported functions --------------------------------------------------------*/
<>	156:95d6b41a828b	170	/** @addtogroup TIM_LL_Exported_Functions
<>	156:95d6b41a828b	171	* @{
<>	156:95d6b41a828b	172	*/
<>	156:95d6b41a828b	173
<>	156:95d6b41a828b	174	/** @addtogroup TIM_LL_EF_Init
<>	156:95d6b41a828b	175	* @{
<>	156:95d6b41a828b	176	*/
<>	156:95d6b41a828b	177
<>	156:95d6b41a828b	178	/**
<>	156:95d6b41a828b	179	* @brief Set TIMx registers to their reset values.
<>	156:95d6b41a828b	180	* @param TIMx Timer instance
<>	156:95d6b41a828b	181	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	182	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	183	* - ERROR: invalid TIMx instance
<>	156:95d6b41a828b	184	*/
<>	156:95d6b41a828b	185	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	186	{
<>	156:95d6b41a828b	187	ErrorStatus result = SUCCESS;
<>	156:95d6b41a828b	188
<>	156:95d6b41a828b	189	/* Check the parameters */
<>	156:95d6b41a828b	190	assert_param(IS_TIM_INSTANCE(TIMx));
<>	156:95d6b41a828b	191
<>	156:95d6b41a828b	192	if (TIMx == TIM1)
<>	156:95d6b41a828b	193	{
<>	156:95d6b41a828b	194	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM1);
<>	156:95d6b41a828b	195	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM1);
<>	156:95d6b41a828b	196	}
<>	156:95d6b41a828b	197	#if defined (TIM2)
<>	156:95d6b41a828b	198	else if (TIMx == TIM2)
<>	156:95d6b41a828b	199	{
<>	156:95d6b41a828b	200	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
<>	156:95d6b41a828b	201	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
<>	156:95d6b41a828b	202	}
<>	156:95d6b41a828b	203	#endif
<>	156:95d6b41a828b	204	#if defined(TIM3)
<>	156:95d6b41a828b	205	else if (TIMx == TIM3)
<>	156:95d6b41a828b	206	{
<>	156:95d6b41a828b	207	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
<>	156:95d6b41a828b	208	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
<>	156:95d6b41a828b	209	}
<>	156:95d6b41a828b	210	#endif
<>	156:95d6b41a828b	211	#if defined(TIM5)
<>	156:95d6b41a828b	212	else if (TIMx == TIM5)
<>	156:95d6b41a828b	213	{
<>	156:95d6b41a828b	214	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
<>	156:95d6b41a828b	215	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
<>	156:95d6b41a828b	216	}
<>	156:95d6b41a828b	217	#endif
<>	156:95d6b41a828b	218	#if defined (TIM6)
<>	156:95d6b41a828b	219	else if (TIMx == TIM6)
<>	156:95d6b41a828b	220	{
<>	156:95d6b41a828b	221	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
<>	156:95d6b41a828b	222	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
<>	156:95d6b41a828b	223	}
<>	156:95d6b41a828b	224	#endif
<>	156:95d6b41a828b	225	#if defined (TIM7)
<>	156:95d6b41a828b	226	else if (TIMx == TIM7)
<>	156:95d6b41a828b	227	{
<>	156:95d6b41a828b	228	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
<>	156:95d6b41a828b	229	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
<>	156:95d6b41a828b	230	}
<>	156:95d6b41a828b	231	#endif
<>	156:95d6b41a828b	232	#if defined(TIM8)
<>	156:95d6b41a828b	233	else if (TIMx == TIM8)
<>	156:95d6b41a828b	234	{
<>	156:95d6b41a828b	235	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
<>	156:95d6b41a828b	236	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
<>	156:95d6b41a828b	237	}
<>	156:95d6b41a828b	238	#endif
<>	156:95d6b41a828b	239	#if defined (TIM14)
<>	156:95d6b41a828b	240	else if (TIMx == TIM14)
<>	156:95d6b41a828b	241	{
<>	156:95d6b41a828b	242	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
<>	156:95d6b41a828b	243	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
<>	156:95d6b41a828b	244	}
<>	156:95d6b41a828b	245	#endif
<>	156:95d6b41a828b	246	#if defined (TIM15)
<>	156:95d6b41a828b	247	else if (TIMx == TIM15)
<>	156:95d6b41a828b	248	{
<>	156:95d6b41a828b	249	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM15);
<>	156:95d6b41a828b	250	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM15);
<>	156:95d6b41a828b	251	}
<>	156:95d6b41a828b	252	#endif
<>	156:95d6b41a828b	253	#if defined (TIM16)
<>	156:95d6b41a828b	254	else if (TIMx == TIM16)
<>	156:95d6b41a828b	255	{
<>	156:95d6b41a828b	256	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM16);
<>	156:95d6b41a828b	257	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM16);
<>	156:95d6b41a828b	258	}
<>	156:95d6b41a828b	259	#endif
<>	156:95d6b41a828b	260	#if defined(TIM17)
<>	156:95d6b41a828b	261	else if (TIMx == TIM17)
<>	156:95d6b41a828b	262	{
<>	156:95d6b41a828b	263	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM17);
<>	156:95d6b41a828b	264	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM17);
<>	156:95d6b41a828b	265	}
<>	156:95d6b41a828b	266	#endif
<>	156:95d6b41a828b	267	else
<>	156:95d6b41a828b	268	{
<>	156:95d6b41a828b	269	result = ERROR;
<>	156:95d6b41a828b	270	}
<>	156:95d6b41a828b	271
<>	156:95d6b41a828b	272	return result;
<>	156:95d6b41a828b	273	}
<>	156:95d6b41a828b	274
<>	156:95d6b41a828b	275	/**
<>	156:95d6b41a828b	276	* @brief Set the fields of the time base unit configuration data structure
<>	156:95d6b41a828b	277	* to their default values.
<>	156:95d6b41a828b	278	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
<>	156:95d6b41a828b	279	* @retval None
<>	156:95d6b41a828b	280	*/
<>	156:95d6b41a828b	281	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
<>	156:95d6b41a828b	282	{
<>	156:95d6b41a828b	283	/* Set the default configuration */
<>	156:95d6b41a828b	284	TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
<>	156:95d6b41a828b	285	TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
Anna Bridge	180:96ed750bd169	286	TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
<>	156:95d6b41a828b	287	TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
<>	156:95d6b41a828b	288	TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
<>	156:95d6b41a828b	289	}
<>	156:95d6b41a828b	290
<>	156:95d6b41a828b	291	/**
<>	156:95d6b41a828b	292	* @brief Configure the TIMx time base unit.
<>	156:95d6b41a828b	293	* @param TIMx Timer Instance
<>	156:95d6b41a828b	294	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
<>	156:95d6b41a828b	295	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	296	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	297	* - ERROR: not applicable
<>	156:95d6b41a828b	298	*/
<>	156:95d6b41a828b	299	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct)
<>	156:95d6b41a828b	300	{
<>	156:95d6b41a828b	301	uint32_t tmpcr1 = 0U;
<>	156:95d6b41a828b	302
<>	156:95d6b41a828b	303	/* Check the parameters */
<>	156:95d6b41a828b	304	assert_param(IS_TIM_INSTANCE(TIMx));
<>	156:95d6b41a828b	305	assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
<>	156:95d6b41a828b	306	assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
<>	156:95d6b41a828b	307
<>	156:95d6b41a828b	308	tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
<>	156:95d6b41a828b	309
<>	156:95d6b41a828b	310	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
<>	156:95d6b41a828b	311	{
<>	156:95d6b41a828b	312	/* Select the Counter Mode */
<>	156:95d6b41a828b	313	MODIFY_REG(tmpcr1, (TIM_CR1_DIR \| TIM_CR1_CMS), TIM_InitStruct->CounterMode);
<>	156:95d6b41a828b	314	}
<>	156:95d6b41a828b	315
<>	156:95d6b41a828b	316	if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
<>	156:95d6b41a828b	317	{
<>	156:95d6b41a828b	318	/* Set the clock division */
<>	156:95d6b41a828b	319	MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
<>	156:95d6b41a828b	320	}
<>	156:95d6b41a828b	321
<>	156:95d6b41a828b	322	/* Write to TIMx CR1 */
<>	156:95d6b41a828b	323	LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
<>	156:95d6b41a828b	324
<>	156:95d6b41a828b	325	/* Set the Autoreload value */
<>	156:95d6b41a828b	326	LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
<>	156:95d6b41a828b	327
<>	156:95d6b41a828b	328	/* Set the Prescaler value */
<>	156:95d6b41a828b	329	LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
<>	156:95d6b41a828b	330
<>	156:95d6b41a828b	331	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
<>	156:95d6b41a828b	332	{
<>	156:95d6b41a828b	333	/* Set the Repetition Counter value */
<>	156:95d6b41a828b	334	LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
<>	156:95d6b41a828b	335	}
<>	156:95d6b41a828b	336
<>	156:95d6b41a828b	337	/* Generate an update event to reload the Prescaler
<>	156:95d6b41a828b	338	and the repetition counter value (if applicable) immediately */
<>	156:95d6b41a828b	339	LL_TIM_GenerateEvent_UPDATE(TIMx);
<>	156:95d6b41a828b	340
<>	156:95d6b41a828b	341	return SUCCESS;
<>	156:95d6b41a828b	342	}
<>	156:95d6b41a828b	343
<>	156:95d6b41a828b	344	/**
<>	156:95d6b41a828b	345	* @brief Set the fields of the TIMx output channel configuration data
<>	156:95d6b41a828b	346	* structure to their default values.
<>	156:95d6b41a828b	347	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
<>	156:95d6b41a828b	348	* @retval None
<>	156:95d6b41a828b	349	*/
<>	156:95d6b41a828b	350	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
<>	156:95d6b41a828b	351	{
<>	156:95d6b41a828b	352	/* Set the default configuration */
<>	156:95d6b41a828b	353	TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
<>	156:95d6b41a828b	354	TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
<>	156:95d6b41a828b	355	TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
Anna Bridge	180:96ed750bd169	356	TIM_OC_InitStruct->CompareValue = 0x00000000U;
<>	156:95d6b41a828b	357	TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
<>	156:95d6b41a828b	358	TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
<>	156:95d6b41a828b	359	TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
<>	156:95d6b41a828b	360	TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
<>	156:95d6b41a828b	361	}
<>	156:95d6b41a828b	362
<>	156:95d6b41a828b	363	/**
<>	156:95d6b41a828b	364	* @brief Configure the TIMx output channel.
<>	156:95d6b41a828b	365	* @param TIMx Timer Instance
<>	156:95d6b41a828b	366	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	367	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	368	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	369	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	370	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	371	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
<>	156:95d6b41a828b	372	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	373	* - SUCCESS: TIMx output channel is initialized
<>	156:95d6b41a828b	374	* - ERROR: TIMx output channel is not initialized
<>	156:95d6b41a828b	375	*/
<>	156:95d6b41a828b	376	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct)
<>	156:95d6b41a828b	377	{
<>	156:95d6b41a828b	378	ErrorStatus result = ERROR;
<>	156:95d6b41a828b	379
<>	156:95d6b41a828b	380	switch (Channel)
<>	156:95d6b41a828b	381	{
<>	156:95d6b41a828b	382	case LL_TIM_CHANNEL_CH1:
<>	156:95d6b41a828b	383	result = OC1Config(TIMx, TIM_OC_InitStruct);
<>	156:95d6b41a828b	384	break;
<>	156:95d6b41a828b	385	case LL_TIM_CHANNEL_CH2:
<>	156:95d6b41a828b	386	result = OC2Config(TIMx, TIM_OC_InitStruct);
<>	156:95d6b41a828b	387	break;
<>	156:95d6b41a828b	388	case LL_TIM_CHANNEL_CH3:
<>	156:95d6b41a828b	389	result = OC3Config(TIMx, TIM_OC_InitStruct);
<>	156:95d6b41a828b	390	break;
<>	156:95d6b41a828b	391	case LL_TIM_CHANNEL_CH4:
<>	156:95d6b41a828b	392	result = OC4Config(TIMx, TIM_OC_InitStruct);
<>	156:95d6b41a828b	393	break;
<>	156:95d6b41a828b	394	default:
<>	156:95d6b41a828b	395	break;
<>	156:95d6b41a828b	396	}
<>	156:95d6b41a828b	397
<>	156:95d6b41a828b	398	return result;
<>	156:95d6b41a828b	399	}
<>	156:95d6b41a828b	400
<>	156:95d6b41a828b	401	/**
<>	156:95d6b41a828b	402	* @brief Set the fields of the TIMx input channel configuration data
<>	156:95d6b41a828b	403	* structure to their default values.
<>	156:95d6b41a828b	404	* @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
<>	156:95d6b41a828b	405	* @retval None
<>	156:95d6b41a828b	406	*/
<>	156:95d6b41a828b	407	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
<>	156:95d6b41a828b	408	{
<>	156:95d6b41a828b	409	/* Set the default configuration */
<>	156:95d6b41a828b	410	TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
<>	156:95d6b41a828b	411	TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<>	156:95d6b41a828b	412	TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
<>	156:95d6b41a828b	413	TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
<>	156:95d6b41a828b	414	}
<>	156:95d6b41a828b	415
<>	156:95d6b41a828b	416	/**
<>	156:95d6b41a828b	417	* @brief Configure the TIMx input channel.
<>	156:95d6b41a828b	418	* @param TIMx Timer Instance
<>	156:95d6b41a828b	419	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	420	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	421	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	422	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	423	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	424	* @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
<>	156:95d6b41a828b	425	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	426	* - SUCCESS: TIMx output channel is initialized
<>	156:95d6b41a828b	427	* - ERROR: TIMx output channel is not initialized
<>	156:95d6b41a828b	428	*/
<>	156:95d6b41a828b	429	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct)
<>	156:95d6b41a828b	430	{
<>	156:95d6b41a828b	431	ErrorStatus result = ERROR;
<>	156:95d6b41a828b	432
<>	156:95d6b41a828b	433	switch (Channel)
<>	156:95d6b41a828b	434	{
<>	156:95d6b41a828b	435	case LL_TIM_CHANNEL_CH1:
<>	156:95d6b41a828b	436	result = IC1Config(TIMx, TIM_IC_InitStruct);
<>	156:95d6b41a828b	437	break;
<>	156:95d6b41a828b	438	case LL_TIM_CHANNEL_CH2:
<>	156:95d6b41a828b	439	result = IC2Config(TIMx, TIM_IC_InitStruct);
<>	156:95d6b41a828b	440	break;
<>	156:95d6b41a828b	441	case LL_TIM_CHANNEL_CH3:
<>	156:95d6b41a828b	442	result = IC3Config(TIMx, TIM_IC_InitStruct);
<>	156:95d6b41a828b	443	break;
<>	156:95d6b41a828b	444	case LL_TIM_CHANNEL_CH4:
<>	156:95d6b41a828b	445	result = IC4Config(TIMx, TIM_IC_InitStruct);
<>	156:95d6b41a828b	446	break;
<>	156:95d6b41a828b	447	default:
<>	156:95d6b41a828b	448	break;
<>	156:95d6b41a828b	449	}
<>	156:95d6b41a828b	450
<>	156:95d6b41a828b	451	return result;
<>	156:95d6b41a828b	452	}
<>	156:95d6b41a828b	453
<>	156:95d6b41a828b	454	/**
<>	156:95d6b41a828b	455	* @brief Fills each TIM_EncoderInitStruct field with its default value
<>	156:95d6b41a828b	456	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
<>	156:95d6b41a828b	457	* @retval None
<>	156:95d6b41a828b	458	*/
<>	156:95d6b41a828b	459	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
<>	156:95d6b41a828b	460	{
<>	156:95d6b41a828b	461	/* Set the default configuration */
<>	156:95d6b41a828b	462	TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
<>	156:95d6b41a828b	463	TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
<>	156:95d6b41a828b	464	TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<>	156:95d6b41a828b	465	TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
<>	156:95d6b41a828b	466	TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
<>	156:95d6b41a828b	467	TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
<>	156:95d6b41a828b	468	TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<>	156:95d6b41a828b	469	TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
<>	156:95d6b41a828b	470	TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
<>	156:95d6b41a828b	471	}
<>	156:95d6b41a828b	472
<>	156:95d6b41a828b	473	/**
<>	156:95d6b41a828b	474	* @brief Configure the encoder interface of the timer instance.
<>	156:95d6b41a828b	475	* @param TIMx Timer Instance
<>	156:95d6b41a828b	476	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
<>	156:95d6b41a828b	477	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	478	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	479	* - ERROR: not applicable
<>	156:95d6b41a828b	480	*/
<>	156:95d6b41a828b	481	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct)
<>	156:95d6b41a828b	482	{
<>	156:95d6b41a828b	483	uint32_t tmpccmr1 = 0U;
<>	156:95d6b41a828b	484	uint32_t tmpccer = 0U;
<>	156:95d6b41a828b	485
<>	156:95d6b41a828b	486	/* Check the parameters */
<>	156:95d6b41a828b	487	assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
<>	156:95d6b41a828b	488	assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
<>	156:95d6b41a828b	489	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
<>	156:95d6b41a828b	490	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
<>	156:95d6b41a828b	491	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
<>	156:95d6b41a828b	492	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
<>	156:95d6b41a828b	493	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
<>	156:95d6b41a828b	494	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
<>	156:95d6b41a828b	495	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
<>	156:95d6b41a828b	496	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
<>	156:95d6b41a828b	497
<>	156:95d6b41a828b	498	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
<>	156:95d6b41a828b	499	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	156:95d6b41a828b	500
<>	156:95d6b41a828b	501	/* Get the TIMx CCMR1 register value */
<>	156:95d6b41a828b	502	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	156:95d6b41a828b	503
<>	156:95d6b41a828b	504	/* Get the TIMx CCER register value */
<>	156:95d6b41a828b	505	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	156:95d6b41a828b	506
<>	156:95d6b41a828b	507	/* Configure TI1 */
<>	156:95d6b41a828b	508	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
<>	156:95d6b41a828b	509	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
<>	156:95d6b41a828b	510	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
<>	156:95d6b41a828b	511	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
<>	156:95d6b41a828b	512
<>	156:95d6b41a828b	513	/* Configure TI2 */
<>	156:95d6b41a828b	514	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC);
<>	156:95d6b41a828b	515	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
<>	156:95d6b41a828b	516	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
<>	156:95d6b41a828b	517	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
<>	156:95d6b41a828b	518
<>	156:95d6b41a828b	519	/* Set TI1 and TI2 polarity and enable TI1 and TI2 */
<>	156:95d6b41a828b	520	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	156:95d6b41a828b	521	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
<>	156:95d6b41a828b	522	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
<>	156:95d6b41a828b	523	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	156:95d6b41a828b	524
<>	156:95d6b41a828b	525	/* Set encoder mode */
<>	156:95d6b41a828b	526	LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
<>	156:95d6b41a828b	527
<>	156:95d6b41a828b	528	/* Write to TIMx CCMR1 */
<>	156:95d6b41a828b	529	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	156:95d6b41a828b	530
<>	156:95d6b41a828b	531	/* Write to TIMx CCER */
<>	156:95d6b41a828b	532	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	156:95d6b41a828b	533
<>	156:95d6b41a828b	534	return SUCCESS;
<>	156:95d6b41a828b	535	}
<>	156:95d6b41a828b	536
<>	156:95d6b41a828b	537	/**
<>	156:95d6b41a828b	538	* @brief Set the fields of the TIMx Hall sensor interface configuration data
<>	156:95d6b41a828b	539	* structure to their default values.
<>	156:95d6b41a828b	540	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
<>	156:95d6b41a828b	541	* @retval None
<>	156:95d6b41a828b	542	*/
<>	156:95d6b41a828b	543	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
<>	156:95d6b41a828b	544	{
<>	156:95d6b41a828b	545	/* Set the default configuration */
<>	156:95d6b41a828b	546	TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
<>	156:95d6b41a828b	547	TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
<>	156:95d6b41a828b	548	TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
Anna Bridge	180:96ed750bd169	549	TIM_HallSensorInitStruct->CommutationDelay = 0U;
<>	156:95d6b41a828b	550	}
<>	156:95d6b41a828b	551
<>	156:95d6b41a828b	552	/**
<>	156:95d6b41a828b	553	* @brief Configure the Hall sensor interface of the timer instance.
<>	156:95d6b41a828b	554	* @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
<>	156:95d6b41a828b	555	* to the TI1 input channel
<>	156:95d6b41a828b	556	* @note TIMx slave mode controller is configured in reset mode.
<>	156:95d6b41a828b	557	Selected internal trigger is TI1F_ED.
<>	156:95d6b41a828b	558	* @note Channel 1 is configured as input, IC1 is mapped on TRC.
<>	156:95d6b41a828b	559	* @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
<>	156:95d6b41a828b	560	* between 2 changes on the inputs. It gives information about motor speed.
<>	156:95d6b41a828b	561	* @note Channel 2 is configured in output PWM 2 mode.
<>	156:95d6b41a828b	562	* @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
<>	156:95d6b41a828b	563	* @note OC2REF is selected as trigger output on TRGO.
<>	156:95d6b41a828b	564	* @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
<>	156:95d6b41a828b	565	* when TIMx operates in Hall sensor interface mode.
<>	156:95d6b41a828b	566	* @param TIMx Timer Instance
<>	156:95d6b41a828b	567	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
<>	156:95d6b41a828b	568	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	569	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	570	* - ERROR: not applicable
<>	156:95d6b41a828b	571	*/
<>	156:95d6b41a828b	572	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct)
<>	156:95d6b41a828b	573	{
<>	156:95d6b41a828b	574	uint32_t tmpcr2 = 0U;
<>	156:95d6b41a828b	575	uint32_t tmpccmr1 = 0U;
<>	156:95d6b41a828b	576	uint32_t tmpccer = 0U;
<>	156:95d6b41a828b	577	uint32_t tmpsmcr = 0U;
<>	156:95d6b41a828b	578
<>	156:95d6b41a828b	579	/* Check the parameters */
<>	156:95d6b41a828b	580	assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
<>	156:95d6b41a828b	581	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
<>	156:95d6b41a828b	582	assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
<>	156:95d6b41a828b	583	assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
<>	156:95d6b41a828b	584
<>	156:95d6b41a828b	585	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
<>	156:95d6b41a828b	586	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	156:95d6b41a828b	587
<>	156:95d6b41a828b	588	/* Get the TIMx CR2 register value */
<>	156:95d6b41a828b	589	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	156:95d6b41a828b	590
<>	156:95d6b41a828b	591	/* Get the TIMx CCMR1 register value */
<>	156:95d6b41a828b	592	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	156:95d6b41a828b	593
<>	156:95d6b41a828b	594	/* Get the TIMx CCER register value */
<>	156:95d6b41a828b	595	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	156:95d6b41a828b	596
<>	156:95d6b41a828b	597	/* Get the TIMx SMCR register value */
<>	156:95d6b41a828b	598	tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
<>	156:95d6b41a828b	599
<>	156:95d6b41a828b	600	/* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
<>	156:95d6b41a828b	601	tmpcr2 \|= TIM_CR2_TI1S;
<>	156:95d6b41a828b	602
<>	156:95d6b41a828b	603	/* OC2REF signal is used as trigger output (TRGO) */
<>	156:95d6b41a828b	604	tmpcr2 \|= LL_TIM_TRGO_OC2REF;
<>	156:95d6b41a828b	605
<>	156:95d6b41a828b	606	/* Configure the slave mode controller */
<>	156:95d6b41a828b	607	tmpsmcr &= (uint32_t)~(TIM_SMCR_TS \| TIM_SMCR_SMS);
<>	156:95d6b41a828b	608	tmpsmcr \|= LL_TIM_TS_TI1F_ED;
<>	156:95d6b41a828b	609	tmpsmcr \|= LL_TIM_SLAVEMODE_RESET;
<>	156:95d6b41a828b	610
<>	156:95d6b41a828b	611	/* Configure input channel 1 */
<>	156:95d6b41a828b	612	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
<>	156:95d6b41a828b	613	tmpccmr1 \|= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
<>	156:95d6b41a828b	614	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
<>	156:95d6b41a828b	615	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
<>	156:95d6b41a828b	616
<>	156:95d6b41a828b	617	/* Configure input channel 2 */
<>	156:95d6b41a828b	618	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M \| TIM_CCMR1_OC2FE \| TIM_CCMR1_OC2PE \| TIM_CCMR1_OC2CE);
<>	156:95d6b41a828b	619	tmpccmr1 \|= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
<>	156:95d6b41a828b	620
<>	156:95d6b41a828b	621	/* Set Channel 1 polarity and enable Channel 1 and Channel2 */
<>	156:95d6b41a828b	622	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	156:95d6b41a828b	623	tmpccer \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
<>	156:95d6b41a828b	624	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	156:95d6b41a828b	625
<>	156:95d6b41a828b	626	/* Write to TIMx CR2 */
<>	156:95d6b41a828b	627	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	156:95d6b41a828b	628
<>	156:95d6b41a828b	629	/* Write to TIMx SMCR */
<>	156:95d6b41a828b	630	LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
<>	156:95d6b41a828b	631
<>	156:95d6b41a828b	632	/* Write to TIMx CCMR1 */
<>	156:95d6b41a828b	633	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	156:95d6b41a828b	634
<>	156:95d6b41a828b	635	/* Write to TIMx CCER */
<>	156:95d6b41a828b	636	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	156:95d6b41a828b	637
<>	156:95d6b41a828b	638	/* Write to TIMx CCR2 */
<>	156:95d6b41a828b	639	LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
<>	156:95d6b41a828b	640
<>	156:95d6b41a828b	641	return SUCCESS;
<>	156:95d6b41a828b	642	}
<>	156:95d6b41a828b	643
<>	156:95d6b41a828b	644	/**
Anna Bridge	180:96ed750bd169	645	* @brief Set the fields of the Break and Dead Time configuration data structure
Anna Bridge	180:96ed750bd169	646	* to their default values.
Anna Bridge	180:96ed750bd169	647	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Anna Bridge	180:96ed750bd169	648	* @retval None
Anna Bridge	180:96ed750bd169	649	*/
Anna Bridge	180:96ed750bd169	650	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Anna Bridge	180:96ed750bd169	651	{
Anna Bridge	180:96ed750bd169	652	/* Set the default configuration */
Anna Bridge	180:96ed750bd169	653	TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
Anna Bridge	180:96ed750bd169	654	TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
Anna Bridge	180:96ed750bd169	655	TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
Anna Bridge	180:96ed750bd169	656	TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
Anna Bridge	180:96ed750bd169	657	TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
Anna Bridge	180:96ed750bd169	658	TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
Anna Bridge	180:96ed750bd169	659	TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
Anna Bridge	180:96ed750bd169	660	}
Anna Bridge	180:96ed750bd169	661
Anna Bridge	180:96ed750bd169	662	/**
Anna Bridge	180:96ed750bd169	663	* @brief Configure the Break and Dead Time feature of the timer instance.
Anna Bridge	180:96ed750bd169	664	* @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
Anna Bridge	180:96ed750bd169	665	* depending on the LOCK configuration, it can be necessary to configure all of
Anna Bridge	180:96ed750bd169	666	* them during the first write access to the TIMx_BDTR register.
Anna Bridge	180:96ed750bd169	667	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
Anna Bridge	180:96ed750bd169	668	* a timer instance provides a break input.
Anna Bridge	180:96ed750bd169	669	* @param TIMx Timer Instance
Anna Bridge	180:96ed750bd169	670	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
Anna Bridge	180:96ed750bd169	671	* @retval An ErrorStatus enumeration value:
Anna Bridge	180:96ed750bd169	672	* - SUCCESS: Break and Dead Time is initialized
Anna Bridge	180:96ed750bd169	673	* - ERROR: not applicable
Anna Bridge	180:96ed750bd169	674	*/
Anna Bridge	180:96ed750bd169	675	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct)
Anna Bridge	180:96ed750bd169	676	{
Anna Bridge	180:96ed750bd169	677	uint32_t tmpbdtr = 0;
Anna Bridge	180:96ed750bd169	678
Anna Bridge	180:96ed750bd169	679	/* Check the parameters */
Anna Bridge	180:96ed750bd169	680	assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
Anna Bridge	180:96ed750bd169	681	assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
Anna Bridge	180:96ed750bd169	682	assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
Anna Bridge	180:96ed750bd169	683	assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
Anna Bridge	180:96ed750bd169	684	assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
Anna Bridge	180:96ed750bd169	685	assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
Anna Bridge	180:96ed750bd169	686	assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
Anna Bridge	180:96ed750bd169	687
Anna Bridge	180:96ed750bd169	688	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
Anna Bridge	180:96ed750bd169	689	the OSSI State, the dead time value and the Automatic Output Enable Bit */
Anna Bridge	180:96ed750bd169	690
Anna Bridge	180:96ed750bd169	691	/* Set the BDTR bits */
Anna Bridge	180:96ed750bd169	692	MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
Anna Bridge	180:96ed750bd169	693	MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
Anna Bridge	180:96ed750bd169	694	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
Anna Bridge	180:96ed750bd169	695	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
Anna Bridge	180:96ed750bd169	696	MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
Anna Bridge	180:96ed750bd169	697	MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
Anna Bridge	180:96ed750bd169	698	MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
Anna Bridge	180:96ed750bd169	699	MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
Anna Bridge	180:96ed750bd169	700
Anna Bridge	180:96ed750bd169	701	/* Set TIMx_BDTR */
Anna Bridge	180:96ed750bd169	702	LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
Anna Bridge	180:96ed750bd169	703
Anna Bridge	180:96ed750bd169	704	return SUCCESS;
Anna Bridge	180:96ed750bd169	705	}
Anna Bridge	180:96ed750bd169	706	/**
<>	156:95d6b41a828b	707	* @}
<>	156:95d6b41a828b	708	*/
<>	156:95d6b41a828b	709
<>	156:95d6b41a828b	710	/**
<>	156:95d6b41a828b	711	* @}
<>	156:95d6b41a828b	712	*/
<>	156:95d6b41a828b	713
<>	156:95d6b41a828b	714	/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
<>	156:95d6b41a828b	715	* @brief Private functions
<>	156:95d6b41a828b	716	* @{
<>	156:95d6b41a828b	717	*/
<>	156:95d6b41a828b	718	/**
<>	156:95d6b41a828b	719	* @brief Configure the TIMx output channel 1.
<>	156:95d6b41a828b	720	* @param TIMx Timer Instance
<>	156:95d6b41a828b	721	* @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
<>	156:95d6b41a828b	722	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	723	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	724	* - ERROR: not applicable
<>	156:95d6b41a828b	725	*/
<>	156:95d6b41a828b	726	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	156:95d6b41a828b	727	{
<>	156:95d6b41a828b	728	uint32_t tmpccmr1 = 0U;
<>	156:95d6b41a828b	729	uint32_t tmpccer = 0U;
<>	156:95d6b41a828b	730	uint32_t tmpcr2 = 0U;
<>	156:95d6b41a828b	731
<>	156:95d6b41a828b	732	/* Check the parameters */
<>	156:95d6b41a828b	733	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<>	156:95d6b41a828b	734	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	156:95d6b41a828b	735	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	156:95d6b41a828b	736	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	156:95d6b41a828b	737	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	156:95d6b41a828b	738	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	156:95d6b41a828b	739
<>	156:95d6b41a828b	740	/* Disable the Channel 1: Reset the CC1E Bit */
<>	156:95d6b41a828b	741	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
<>	156:95d6b41a828b	742
<>	156:95d6b41a828b	743	/* Get the TIMx CCER register value */
<>	156:95d6b41a828b	744	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	156:95d6b41a828b	745
<>	156:95d6b41a828b	746	/* Get the TIMx CR2 register value */
<>	156:95d6b41a828b	747	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	156:95d6b41a828b	748
<>	156:95d6b41a828b	749	/* Get the TIMx CCMR1 register value */
<>	156:95d6b41a828b	750	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	156:95d6b41a828b	751
<>	156:95d6b41a828b	752	/* Reset Capture/Compare selection Bits */
<>	156:95d6b41a828b	753	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
<>	156:95d6b41a828b	754
<>	156:95d6b41a828b	755	/* Set the Output Compare Mode */
<>	156:95d6b41a828b	756	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
<>	156:95d6b41a828b	757
<>	156:95d6b41a828b	758	/* Set the Output Compare Polarity */
<>	156:95d6b41a828b	759	MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
<>	156:95d6b41a828b	760
<>	156:95d6b41a828b	761	/* Set the Output State */
<>	156:95d6b41a828b	762	MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
<>	156:95d6b41a828b	763
<>	156:95d6b41a828b	764	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	156:95d6b41a828b	765	{
<>	156:95d6b41a828b	766	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	156:95d6b41a828b	767	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	156:95d6b41a828b	768
<>	156:95d6b41a828b	769	/* Set the complementary output Polarity */
<>	156:95d6b41a828b	770	MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
<>	156:95d6b41a828b	771
<>	156:95d6b41a828b	772	/* Set the complementary output State */
<>	156:95d6b41a828b	773	MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
<>	156:95d6b41a828b	774
<>	156:95d6b41a828b	775	/* Set the Output Idle state */
<>	156:95d6b41a828b	776	MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
<>	156:95d6b41a828b	777
<>	156:95d6b41a828b	778	/* Set the complementary output Idle state */
<>	156:95d6b41a828b	779	MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
<>	156:95d6b41a828b	780	}
<>	156:95d6b41a828b	781
<>	156:95d6b41a828b	782	/* Write to TIMx CR2 */
<>	156:95d6b41a828b	783	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	156:95d6b41a828b	784
<>	156:95d6b41a828b	785	/* Write to TIMx CCMR1 */
<>	156:95d6b41a828b	786	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	156:95d6b41a828b	787
<>	156:95d6b41a828b	788	/* Set the Capture Compare Register value */
<>	156:95d6b41a828b	789	LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
<>	156:95d6b41a828b	790
<>	156:95d6b41a828b	791	/* Write to TIMx CCER */
<>	156:95d6b41a828b	792	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	156:95d6b41a828b	793
<>	156:95d6b41a828b	794	return SUCCESS;
<>	156:95d6b41a828b	795	}
<>	156:95d6b41a828b	796
<>	156:95d6b41a828b	797	/**
<>	156:95d6b41a828b	798	* @brief Configure the TIMx output channel 2.
<>	156:95d6b41a828b	799	* @param TIMx Timer Instance
<>	156:95d6b41a828b	800	* @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
<>	156:95d6b41a828b	801	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	802	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	803	* - ERROR: not applicable
<>	156:95d6b41a828b	804	*/
<>	156:95d6b41a828b	805	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	156:95d6b41a828b	806	{
<>	156:95d6b41a828b	807	uint32_t tmpccmr1 = 0U;
<>	156:95d6b41a828b	808	uint32_t tmpccer = 0U;
<>	156:95d6b41a828b	809	uint32_t tmpcr2 = 0U;
<>	156:95d6b41a828b	810
<>	156:95d6b41a828b	811	/* Check the parameters */
<>	156:95d6b41a828b	812	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
<>	156:95d6b41a828b	813	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	156:95d6b41a828b	814	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	156:95d6b41a828b	815	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	156:95d6b41a828b	816	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	156:95d6b41a828b	817	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	156:95d6b41a828b	818
<>	156:95d6b41a828b	819	/* Disable the Channel 2: Reset the CC2E Bit */
<>	156:95d6b41a828b	820	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
<>	156:95d6b41a828b	821
<>	156:95d6b41a828b	822	/* Get the TIMx CCER register value */
<>	156:95d6b41a828b	823	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	156:95d6b41a828b	824
<>	156:95d6b41a828b	825	/* Get the TIMx CR2 register value */
<>	156:95d6b41a828b	826	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	156:95d6b41a828b	827
<>	156:95d6b41a828b	828	/* Get the TIMx CCMR1 register value */
<>	156:95d6b41a828b	829	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	156:95d6b41a828b	830
<>	156:95d6b41a828b	831	/* Reset Capture/Compare selection Bits */
<>	156:95d6b41a828b	832	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
<>	156:95d6b41a828b	833
<>	156:95d6b41a828b	834	/* Select the Output Compare Mode */
<>	156:95d6b41a828b	835	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
<>	156:95d6b41a828b	836
<>	156:95d6b41a828b	837	/* Set the Output Compare Polarity */
<>	156:95d6b41a828b	838	MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
<>	156:95d6b41a828b	839
<>	156:95d6b41a828b	840	/* Set the Output State */
<>	156:95d6b41a828b	841	MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
<>	156:95d6b41a828b	842
<>	156:95d6b41a828b	843	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	156:95d6b41a828b	844	{
<>	156:95d6b41a828b	845	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	156:95d6b41a828b	846	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	156:95d6b41a828b	847
<>	156:95d6b41a828b	848	/* Set the complementary output Polarity */
<>	156:95d6b41a828b	849	MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
<>	156:95d6b41a828b	850
<>	156:95d6b41a828b	851	/* Set the complementary output State */
<>	156:95d6b41a828b	852	MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
<>	156:95d6b41a828b	853
<>	156:95d6b41a828b	854	/* Set the Output Idle state */
<>	156:95d6b41a828b	855	MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
<>	156:95d6b41a828b	856
<>	156:95d6b41a828b	857	/* Set the complementary output Idle state */
<>	156:95d6b41a828b	858	MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
<>	156:95d6b41a828b	859	}
<>	156:95d6b41a828b	860
<>	156:95d6b41a828b	861	/* Write to TIMx CR2 */
<>	156:95d6b41a828b	862	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	156:95d6b41a828b	863
<>	156:95d6b41a828b	864	/* Write to TIMx CCMR1 */
<>	156:95d6b41a828b	865	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	156:95d6b41a828b	866
<>	156:95d6b41a828b	867	/* Set the Capture Compare Register value */
<>	156:95d6b41a828b	868	LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
<>	156:95d6b41a828b	869
<>	156:95d6b41a828b	870	/* Write to TIMx CCER */
<>	156:95d6b41a828b	871	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	156:95d6b41a828b	872
<>	156:95d6b41a828b	873	return SUCCESS;
<>	156:95d6b41a828b	874	}
<>	156:95d6b41a828b	875
<>	156:95d6b41a828b	876	/**
<>	156:95d6b41a828b	877	* @brief Configure the TIMx output channel 3.
<>	156:95d6b41a828b	878	* @param TIMx Timer Instance
<>	156:95d6b41a828b	879	* @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
<>	156:95d6b41a828b	880	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	881	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	882	* - ERROR: not applicable
<>	156:95d6b41a828b	883	*/
<>	156:95d6b41a828b	884	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	156:95d6b41a828b	885	{
<>	156:95d6b41a828b	886	uint32_t tmpccmr2 = 0U;
<>	156:95d6b41a828b	887	uint32_t tmpccer = 0U;
<>	156:95d6b41a828b	888	uint32_t tmpcr2 = 0U;
<>	156:95d6b41a828b	889
<>	156:95d6b41a828b	890	/* Check the parameters */
<>	156:95d6b41a828b	891	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
<>	156:95d6b41a828b	892	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	156:95d6b41a828b	893	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	156:95d6b41a828b	894	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	156:95d6b41a828b	895	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	156:95d6b41a828b	896	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	156:95d6b41a828b	897
<>	156:95d6b41a828b	898	/* Disable the Channel 3: Reset the CC3E Bit */
<>	156:95d6b41a828b	899	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
<>	156:95d6b41a828b	900
<>	156:95d6b41a828b	901	/* Get the TIMx CCER register value */
<>	156:95d6b41a828b	902	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	156:95d6b41a828b	903
<>	156:95d6b41a828b	904	/* Get the TIMx CR2 register value */
<>	156:95d6b41a828b	905	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	156:95d6b41a828b	906
<>	156:95d6b41a828b	907	/* Get the TIMx CCMR2 register value */
<>	156:95d6b41a828b	908	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
<>	156:95d6b41a828b	909
<>	156:95d6b41a828b	910	/* Reset Capture/Compare selection Bits */
<>	156:95d6b41a828b	911	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
<>	156:95d6b41a828b	912
<>	156:95d6b41a828b	913	/* Select the Output Compare Mode */
<>	156:95d6b41a828b	914	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
<>	156:95d6b41a828b	915
<>	156:95d6b41a828b	916	/* Set the Output Compare Polarity */
<>	156:95d6b41a828b	917	MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
<>	156:95d6b41a828b	918
<>	156:95d6b41a828b	919	/* Set the Output State */
<>	156:95d6b41a828b	920	MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
<>	156:95d6b41a828b	921
<>	156:95d6b41a828b	922	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	156:95d6b41a828b	923	{
<>	156:95d6b41a828b	924	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	156:95d6b41a828b	925	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	156:95d6b41a828b	926
<>	156:95d6b41a828b	927	/* Set the complementary output Polarity */
<>	156:95d6b41a828b	928	MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
<>	156:95d6b41a828b	929
<>	156:95d6b41a828b	930	/* Set the complementary output State */
<>	156:95d6b41a828b	931	MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
<>	156:95d6b41a828b	932
<>	156:95d6b41a828b	933	/* Set the Output Idle state */
<>	156:95d6b41a828b	934	MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
<>	156:95d6b41a828b	935
<>	156:95d6b41a828b	936	/* Set the complementary output Idle state */
<>	156:95d6b41a828b	937	MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
<>	156:95d6b41a828b	938	}
<>	156:95d6b41a828b	939
<>	156:95d6b41a828b	940	/* Write to TIMx CR2 */
<>	156:95d6b41a828b	941	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	156:95d6b41a828b	942
<>	156:95d6b41a828b	943	/* Write to TIMx CCMR2 */
<>	156:95d6b41a828b	944	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
<>	156:95d6b41a828b	945
<>	156:95d6b41a828b	946	/* Set the Capture Compare Register value */
<>	156:95d6b41a828b	947	LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
<>	156:95d6b41a828b	948
<>	156:95d6b41a828b	949	/* Write to TIMx CCER */
<>	156:95d6b41a828b	950	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	156:95d6b41a828b	951
<>	156:95d6b41a828b	952	return SUCCESS;
<>	156:95d6b41a828b	953	}
<>	156:95d6b41a828b	954
<>	156:95d6b41a828b	955	/**
<>	156:95d6b41a828b	956	* @brief Configure the TIMx output channel 4.
<>	156:95d6b41a828b	957	* @param TIMx Timer Instance
<>	156:95d6b41a828b	958	* @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
<>	156:95d6b41a828b	959	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	960	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	961	* - ERROR: not applicable
<>	156:95d6b41a828b	962	*/
<>	156:95d6b41a828b	963	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	156:95d6b41a828b	964	{
<>	156:95d6b41a828b	965	uint32_t tmpccmr2 = 0U;
<>	156:95d6b41a828b	966	uint32_t tmpccer = 0U;
<>	156:95d6b41a828b	967	uint32_t tmpcr2 = 0U;
<>	156:95d6b41a828b	968
<>	156:95d6b41a828b	969	/* Check the parameters */
<>	156:95d6b41a828b	970	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
<>	156:95d6b41a828b	971	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	156:95d6b41a828b	972	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	156:95d6b41a828b	973	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	156:95d6b41a828b	974	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	156:95d6b41a828b	975	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	156:95d6b41a828b	976
<>	156:95d6b41a828b	977	/* Disable the Channel 4: Reset the CC4E Bit */
<>	156:95d6b41a828b	978	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
<>	156:95d6b41a828b	979
<>	156:95d6b41a828b	980	/* Get the TIMx CCER register value */
<>	156:95d6b41a828b	981	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	156:95d6b41a828b	982
<>	156:95d6b41a828b	983	/* Get the TIMx CR2 register value */
<>	156:95d6b41a828b	984	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	156:95d6b41a828b	985
<>	156:95d6b41a828b	986	/* Get the TIMx CCMR2 register value */
<>	156:95d6b41a828b	987	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
<>	156:95d6b41a828b	988
<>	156:95d6b41a828b	989	/* Reset Capture/Compare selection Bits */
<>	156:95d6b41a828b	990	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
<>	156:95d6b41a828b	991
<>	156:95d6b41a828b	992	/* Select the Output Compare Mode */
<>	156:95d6b41a828b	993	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
<>	156:95d6b41a828b	994
<>	156:95d6b41a828b	995	/* Set the Output Compare Polarity */
<>	156:95d6b41a828b	996	MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
<>	156:95d6b41a828b	997
<>	156:95d6b41a828b	998	/* Set the Output State */
<>	156:95d6b41a828b	999	MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
<>	156:95d6b41a828b	1000
<>	156:95d6b41a828b	1001	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	156:95d6b41a828b	1002	{
<>	156:95d6b41a828b	1003	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	156:95d6b41a828b	1004	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	156:95d6b41a828b	1005
<>	156:95d6b41a828b	1006	/* Set the Output Idle state */
<>	156:95d6b41a828b	1007	MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
<>	156:95d6b41a828b	1008	}
<>	156:95d6b41a828b	1009
<>	156:95d6b41a828b	1010	/* Write to TIMx CR2 */
<>	156:95d6b41a828b	1011	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	156:95d6b41a828b	1012
<>	156:95d6b41a828b	1013	/* Write to TIMx CCMR2 */
<>	156:95d6b41a828b	1014	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
<>	156:95d6b41a828b	1015
<>	156:95d6b41a828b	1016	/* Set the Capture Compare Register value */
<>	156:95d6b41a828b	1017	LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
<>	156:95d6b41a828b	1018
<>	156:95d6b41a828b	1019	/* Write to TIMx CCER */
<>	156:95d6b41a828b	1020	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	156:95d6b41a828b	1021
<>	156:95d6b41a828b	1022	return SUCCESS;
<>	156:95d6b41a828b	1023	}
<>	156:95d6b41a828b	1024
<>	156:95d6b41a828b	1025
<>	156:95d6b41a828b	1026	/**
<>	156:95d6b41a828b	1027	* @brief Configure the TIMx input channel 1.
<>	156:95d6b41a828b	1028	* @param TIMx Timer Instance
<>	156:95d6b41a828b	1029	* @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
<>	156:95d6b41a828b	1030	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	1031	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	1032	* - ERROR: not applicable
<>	156:95d6b41a828b	1033	*/
<>	156:95d6b41a828b	1034	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	156:95d6b41a828b	1035	{
<>	156:95d6b41a828b	1036	/* Check the parameters */
<>	156:95d6b41a828b	1037	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<>	156:95d6b41a828b	1038	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	156:95d6b41a828b	1039	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	156:95d6b41a828b	1040	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	156:95d6b41a828b	1041	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	156:95d6b41a828b	1042
<>	156:95d6b41a828b	1043	/* Disable the Channel 1: Reset the CC1E Bit */
<>	156:95d6b41a828b	1044	TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
<>	156:95d6b41a828b	1045
<>	156:95d6b41a828b	1046	/* Select the Input and set the filter and the prescaler value */
<>	156:95d6b41a828b	1047	MODIFY_REG(TIMx->CCMR1,
<>	156:95d6b41a828b	1048	(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC),
<>	156:95d6b41a828b	1049	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
<>	156:95d6b41a828b	1050
<>	156:95d6b41a828b	1051	/* Select the Polarity and set the CC1E Bit */
<>	156:95d6b41a828b	1052	MODIFY_REG(TIMx->CCER,
<>	156:95d6b41a828b	1053	(TIM_CCER_CC1P \| TIM_CCER_CC1NP),
<>	156:95d6b41a828b	1054	(TIM_ICInitStruct->ICPolarity \| TIM_CCER_CC1E));
<>	156:95d6b41a828b	1055
<>	156:95d6b41a828b	1056	return SUCCESS;
<>	156:95d6b41a828b	1057	}
<>	156:95d6b41a828b	1058
<>	156:95d6b41a828b	1059	/**
<>	156:95d6b41a828b	1060	* @brief Configure the TIMx input channel 2.
<>	156:95d6b41a828b	1061	* @param TIMx Timer Instance
<>	156:95d6b41a828b	1062	* @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
<>	156:95d6b41a828b	1063	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	1064	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	1065	* - ERROR: not applicable
<>	156:95d6b41a828b	1066	*/
<>	156:95d6b41a828b	1067	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	156:95d6b41a828b	1068	{
<>	156:95d6b41a828b	1069	/* Check the parameters */
<>	156:95d6b41a828b	1070	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
<>	156:95d6b41a828b	1071	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	156:95d6b41a828b	1072	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	156:95d6b41a828b	1073	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	156:95d6b41a828b	1074	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	156:95d6b41a828b	1075
<>	156:95d6b41a828b	1076	/* Disable the Channel 2: Reset the CC2E Bit */
<>	156:95d6b41a828b	1077	TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
<>	156:95d6b41a828b	1078
<>	156:95d6b41a828b	1079	/* Select the Input and set the filter and the prescaler value */
<>	156:95d6b41a828b	1080	MODIFY_REG(TIMx->CCMR1,
<>	156:95d6b41a828b	1081	(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC),
<>	156:95d6b41a828b	1082	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
<>	156:95d6b41a828b	1083
<>	156:95d6b41a828b	1084	/* Select the Polarity and set the CC2E Bit */
<>	156:95d6b41a828b	1085	MODIFY_REG(TIMx->CCER,
<>	156:95d6b41a828b	1086	(TIM_CCER_CC2P \| TIM_CCER_CC2NP),
<>	156:95d6b41a828b	1087	((TIM_ICInitStruct->ICPolarity << 4U) \| TIM_CCER_CC2E));
<>	156:95d6b41a828b	1088
<>	156:95d6b41a828b	1089	return SUCCESS;
<>	156:95d6b41a828b	1090	}
<>	156:95d6b41a828b	1091
<>	156:95d6b41a828b	1092	/**
<>	156:95d6b41a828b	1093	* @brief Configure the TIMx input channel 3.
<>	156:95d6b41a828b	1094	* @param TIMx Timer Instance
<>	156:95d6b41a828b	1095	* @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
<>	156:95d6b41a828b	1096	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	1097	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	1098	* - ERROR: not applicable
<>	156:95d6b41a828b	1099	*/
<>	156:95d6b41a828b	1100	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	156:95d6b41a828b	1101	{
<>	156:95d6b41a828b	1102	/* Check the parameters */
<>	156:95d6b41a828b	1103	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
<>	156:95d6b41a828b	1104	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	156:95d6b41a828b	1105	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	156:95d6b41a828b	1106	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	156:95d6b41a828b	1107	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	156:95d6b41a828b	1108
<>	156:95d6b41a828b	1109	/* Disable the Channel 3: Reset the CC3E Bit */
<>	156:95d6b41a828b	1110	TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
<>	156:95d6b41a828b	1111
<>	156:95d6b41a828b	1112	/* Select the Input and set the filter and the prescaler value */
<>	156:95d6b41a828b	1113	MODIFY_REG(TIMx->CCMR2,
<>	156:95d6b41a828b	1114	(TIM_CCMR2_CC3S \| TIM_CCMR2_IC3F \| TIM_CCMR2_IC3PSC),
<>	156:95d6b41a828b	1115	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
<>	156:95d6b41a828b	1116
<>	156:95d6b41a828b	1117	/* Select the Polarity and set the CC3E Bit */
<>	156:95d6b41a828b	1118	MODIFY_REG(TIMx->CCER,
<>	156:95d6b41a828b	1119	(TIM_CCER_CC3P \| TIM_CCER_CC3NP),
<>	156:95d6b41a828b	1120	((TIM_ICInitStruct->ICPolarity << 8U) \| TIM_CCER_CC3E));
<>	156:95d6b41a828b	1121
<>	156:95d6b41a828b	1122	return SUCCESS;
<>	156:95d6b41a828b	1123	}
<>	156:95d6b41a828b	1124
<>	156:95d6b41a828b	1125	/**
<>	156:95d6b41a828b	1126	* @brief Configure the TIMx input channel 4.
<>	156:95d6b41a828b	1127	* @param TIMx Timer Instance
<>	156:95d6b41a828b	1128	* @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
<>	156:95d6b41a828b	1129	* @retval An ErrorStatus enumeration value:
<>	156:95d6b41a828b	1130	* - SUCCESS: TIMx registers are de-initialized
<>	156:95d6b41a828b	1131	* - ERROR: not applicable
<>	156:95d6b41a828b	1132	*/
<>	156:95d6b41a828b	1133	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	156:95d6b41a828b	1134	{
<>	156:95d6b41a828b	1135	/* Check the parameters */
<>	156:95d6b41a828b	1136	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
<>	156:95d6b41a828b	1137	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	156:95d6b41a828b	1138	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	156:95d6b41a828b	1139	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	156:95d6b41a828b	1140	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	156:95d6b41a828b	1141
<>	156:95d6b41a828b	1142	/* Disable the Channel 4: Reset the CC4E Bit */
<>	156:95d6b41a828b	1143	TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
<>	156:95d6b41a828b	1144
<>	156:95d6b41a828b	1145	/* Select the Input and set the filter and the prescaler value */
<>	156:95d6b41a828b	1146	MODIFY_REG(TIMx->CCMR2,
<>	156:95d6b41a828b	1147	(TIM_CCMR2_CC4S \| TIM_CCMR2_IC4F \| TIM_CCMR2_IC4PSC),
<>	156:95d6b41a828b	1148	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
<>	156:95d6b41a828b	1149
<>	156:95d6b41a828b	1150	/* Select the Polarity and set the CC2E Bit */
<>	156:95d6b41a828b	1151	MODIFY_REG(TIMx->CCER,
<>	156:95d6b41a828b	1152	(TIM_CCER_CC4P \| TIM_CCER_CC4NP),
<>	156:95d6b41a828b	1153	((TIM_ICInitStruct->ICPolarity << 12U) \| TIM_CCER_CC4E));
<>	156:95d6b41a828b	1154
<>	156:95d6b41a828b	1155	return SUCCESS;
<>	156:95d6b41a828b	1156	}
<>	156:95d6b41a828b	1157
<>	156:95d6b41a828b	1158
<>	156:95d6b41a828b	1159	/**
<>	156:95d6b41a828b	1160	* @}
<>	156:95d6b41a828b	1161	*/
<>	156:95d6b41a828b	1162
<>	156:95d6b41a828b	1163	/**
<>	156:95d6b41a828b	1164	* @}
<>	156:95d6b41a828b	1165	*/
<>	156:95d6b41a828b	1166
<>	156:95d6b41a828b	1167	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
<>	156:95d6b41a828b	1168
<>	156:95d6b41a828b	1169	/**
<>	156:95d6b41a828b	1170	* @}
<>	156:95d6b41a828b	1171	*/
<>	156:95d6b41a828b	1172
<>	156:95d6b41a828b	1173	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	1174
<>	156:95d6b41a828b	1175	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/