mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_spi.c
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief SPI LL module driver.
<> 156:95d6b41a828b 6 ******************************************************************************
<> 156:95d6b41a828b 7 * @attention
<> 156:95d6b41a828b 8 *
<> 156:95d6b41a828b 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 12 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 14 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 17 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 19 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 20 * without specific prior written permission.
<> 156:95d6b41a828b 21 *
<> 156:95d6b41a828b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 32 *
<> 156:95d6b41a828b 33 ******************************************************************************
<> 156:95d6b41a828b 34 */
<> 156:95d6b41a828b 35 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 36
<> 156:95d6b41a828b 37 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 38 #include "stm32f0xx_ll_spi.h"
<> 156:95d6b41a828b 39 #include "stm32f0xx_ll_bus.h"
<> 156:95d6b41a828b 40 #include "stm32f0xx_ll_rcc.h"
<> 156:95d6b41a828b 41
<> 156:95d6b41a828b 42 #ifdef USE_FULL_ASSERT
<> 156:95d6b41a828b 43 #include "stm32_assert.h"
<> 156:95d6b41a828b 44 #else
<> 156:95d6b41a828b 45 #define assert_param(expr) ((void)0U)
<> 156:95d6b41a828b 46 #endif
<> 156:95d6b41a828b 47
<> 156:95d6b41a828b 48 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 49 * @{
<> 156:95d6b41a828b 50 */
<> 156:95d6b41a828b 51
<> 156:95d6b41a828b 52 #if defined (SPI1) || defined (SPI2)
<> 156:95d6b41a828b 53
<> 156:95d6b41a828b 54 /** @addtogroup SPI_LL
<> 156:95d6b41a828b 55 * @{
<> 156:95d6b41a828b 56 */
<> 156:95d6b41a828b 57
<> 156:95d6b41a828b 58 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 59 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 60
<> 156:95d6b41a828b 61 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 62 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
<> 156:95d6b41a828b 63 * @{
<> 156:95d6b41a828b 64 */
<> 156:95d6b41a828b 65 /* SPI registers Masks */
<> 156:95d6b41a828b 66 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
<> 156:95d6b41a828b 67 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
<> 156:95d6b41a828b 68 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
<> 156:95d6b41a828b 69 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
<> 156:95d6b41a828b 70 SPI_CR1_BIDIMODE)
<> 156:95d6b41a828b 71 /**
<> 156:95d6b41a828b 72 * @}
<> 156:95d6b41a828b 73 */
<> 156:95d6b41a828b 74
<> 156:95d6b41a828b 75 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 76 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
<> 156:95d6b41a828b 77 * @{
<> 156:95d6b41a828b 78 */
<> 156:95d6b41a828b 79 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
<> 156:95d6b41a828b 80 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
<> 156:95d6b41a828b 81 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
<> 156:95d6b41a828b 82 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
<> 156:95d6b41a828b 83
<> 156:95d6b41a828b 84 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
<> 156:95d6b41a828b 85 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
<> 156:95d6b41a828b 86
<> 156:95d6b41a828b 87 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
<> 156:95d6b41a828b 88 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
<> 156:95d6b41a828b 89 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
<> 156:95d6b41a828b 90 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
<> 156:95d6b41a828b 91 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
<> 156:95d6b41a828b 92 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
<> 156:95d6b41a828b 93 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
<> 156:95d6b41a828b 94 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
<> 156:95d6b41a828b 95 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
<> 156:95d6b41a828b 96 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
<> 156:95d6b41a828b 97 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
<> 156:95d6b41a828b 98 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
<> 156:95d6b41a828b 99 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
<> 156:95d6b41a828b 100
<> 156:95d6b41a828b 101 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
<> 156:95d6b41a828b 102 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
<> 156:95d6b41a828b 103
<> 156:95d6b41a828b 104 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
<> 156:95d6b41a828b 105 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
<> 156:95d6b41a828b 106
<> 156:95d6b41a828b 107 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
<> 156:95d6b41a828b 108 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
<> 156:95d6b41a828b 109 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
<> 156:95d6b41a828b 110
<> 156:95d6b41a828b 111 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
<> 156:95d6b41a828b 112 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
<> 156:95d6b41a828b 113 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
<> 156:95d6b41a828b 114 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
<> 156:95d6b41a828b 115 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
<> 156:95d6b41a828b 116 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
<> 156:95d6b41a828b 117 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
<> 156:95d6b41a828b 118 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
<> 156:95d6b41a828b 119
<> 156:95d6b41a828b 120 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
<> 156:95d6b41a828b 121 || ((__VALUE__) == LL_SPI_MSB_FIRST))
<> 156:95d6b41a828b 122
<> 156:95d6b41a828b 123 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
<> 156:95d6b41a828b 124 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
<> 156:95d6b41a828b 125
<> 156:95d6b41a828b 126 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
<> 156:95d6b41a828b 127
<> 156:95d6b41a828b 128 /**
<> 156:95d6b41a828b 129 * @}
<> 156:95d6b41a828b 130 */
<> 156:95d6b41a828b 131
<> 156:95d6b41a828b 132 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 133
<> 156:95d6b41a828b 134 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 135 /** @addtogroup SPI_LL_Exported_Functions
<> 156:95d6b41a828b 136 * @{
<> 156:95d6b41a828b 137 */
<> 156:95d6b41a828b 138
<> 156:95d6b41a828b 139 /** @addtogroup SPI_LL_EF_Init
<> 156:95d6b41a828b 140 * @{
<> 156:95d6b41a828b 141 */
<> 156:95d6b41a828b 142
<> 156:95d6b41a828b 143 /**
<> 156:95d6b41a828b 144 * @brief De-initialize the SPI registers to their default reset values.
<> 156:95d6b41a828b 145 * @param SPIx SPI Instance
<> 156:95d6b41a828b 146 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 147 * - SUCCESS: SPI registers are de-initialized
<> 156:95d6b41a828b 148 * - ERROR: SPI registers are not de-initialized
<> 156:95d6b41a828b 149 */
<> 156:95d6b41a828b 150 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
<> 156:95d6b41a828b 151 {
<> 156:95d6b41a828b 152 ErrorStatus status = ERROR;
<> 156:95d6b41a828b 153
<> 156:95d6b41a828b 154 /* Check the parameters */
<> 156:95d6b41a828b 155 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
<> 156:95d6b41a828b 156
<> 156:95d6b41a828b 157 #if defined(SPI1)
<> 156:95d6b41a828b 158 if (SPIx == SPI1)
<> 156:95d6b41a828b 159 {
<> 156:95d6b41a828b 160 /* Force reset of SPI clock */
<> 156:95d6b41a828b 161 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SPI1);
<> 156:95d6b41a828b 162
<> 156:95d6b41a828b 163 /* Release reset of SPI clock */
<> 156:95d6b41a828b 164 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SPI1);
<> 156:95d6b41a828b 165
<> 156:95d6b41a828b 166 status = SUCCESS;
<> 156:95d6b41a828b 167 }
<> 156:95d6b41a828b 168 #endif /* SPI1 */
<> 156:95d6b41a828b 169 #if defined(SPI2)
<> 156:95d6b41a828b 170 if (SPIx == SPI2)
<> 156:95d6b41a828b 171 {
<> 156:95d6b41a828b 172 /* Force reset of SPI clock */
<> 156:95d6b41a828b 173 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
<> 156:95d6b41a828b 174
<> 156:95d6b41a828b 175 /* Release reset of SPI clock */
<> 156:95d6b41a828b 176 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
<> 156:95d6b41a828b 177
<> 156:95d6b41a828b 178 status = SUCCESS;
<> 156:95d6b41a828b 179 }
<> 156:95d6b41a828b 180 #endif /* SPI2 */
<> 156:95d6b41a828b 181
<> 156:95d6b41a828b 182 return status;
<> 156:95d6b41a828b 183 }
<> 156:95d6b41a828b 184
<> 156:95d6b41a828b 185 /**
<> 156:95d6b41a828b 186 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
<> 156:95d6b41a828b 187 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
<> 156:95d6b41a828b 188 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 156:95d6b41a828b 189 * @param SPIx SPI Instance
<> 156:95d6b41a828b 190 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
<> 156:95d6b41a828b 191 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
<> 156:95d6b41a828b 192 */
<> 156:95d6b41a828b 193 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
<> 156:95d6b41a828b 194 {
<> 156:95d6b41a828b 195 ErrorStatus status = ERROR;
<> 156:95d6b41a828b 196
<> 156:95d6b41a828b 197 /* Check the SPI Instance SPIx*/
<> 156:95d6b41a828b 198 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
<> 156:95d6b41a828b 199
<> 156:95d6b41a828b 200 /* Check the SPI parameters from SPI_InitStruct*/
<> 156:95d6b41a828b 201 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
<> 156:95d6b41a828b 202 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
<> 156:95d6b41a828b 203 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
<> 156:95d6b41a828b 204 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
<> 156:95d6b41a828b 205 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
<> 156:95d6b41a828b 206 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
<> 156:95d6b41a828b 207 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
<> 156:95d6b41a828b 208 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
<> 156:95d6b41a828b 209 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
<> 156:95d6b41a828b 210
<> 156:95d6b41a828b 211 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
<> 156:95d6b41a828b 212 {
<> 156:95d6b41a828b 213 /*---------------------------- SPIx CR1 Configuration ------------------------
<> 156:95d6b41a828b 214 * Configure SPIx CR1 with parameters:
<> 156:95d6b41a828b 215 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
<> 156:95d6b41a828b 216 * - Master/Slave Mode: SPI_CR1_MSTR bit
<> 156:95d6b41a828b 217 * - ClockPolarity: SPI_CR1_CPOL bit
<> 156:95d6b41a828b 218 * - ClockPhase: SPI_CR1_CPHA bit
<> 156:95d6b41a828b 219 * - NSS management: SPI_CR1_SSM bit
<> 156:95d6b41a828b 220 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
<> 156:95d6b41a828b 221 * - BitOrder: SPI_CR1_LSBFIRST bit
<> 156:95d6b41a828b 222 * - CRCCalculation: SPI_CR1_CRCEN bit
<> 156:95d6b41a828b 223 */
<> 156:95d6b41a828b 224 MODIFY_REG(SPIx->CR1,
<> 156:95d6b41a828b 225 SPI_CR1_CLEAR_MASK,
<> 156:95d6b41a828b 226 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
<> 156:95d6b41a828b 227 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
<> 156:95d6b41a828b 228 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
<> 156:95d6b41a828b 229 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
<> 156:95d6b41a828b 230
<> 156:95d6b41a828b 231 /*---------------------------- SPIx CR2 Configuration ------------------------
<> 156:95d6b41a828b 232 * Configure SPIx CR2 with parameters:
<> 156:95d6b41a828b 233 * - DataWidth: DS[3:0] bits
<> 156:95d6b41a828b 234 * - NSS management: SSOE bit
<> 156:95d6b41a828b 235 */
<> 156:95d6b41a828b 236 MODIFY_REG(SPIx->CR2,
<> 156:95d6b41a828b 237 SPI_CR2_DS | SPI_CR2_SSOE,
<> 156:95d6b41a828b 238 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
<> 156:95d6b41a828b 239
<> 156:95d6b41a828b 240 /*---------------------------- SPIx CRCPR Configuration ----------------------
<> 156:95d6b41a828b 241 * Configure SPIx CRCPR with parameters:
<> 156:95d6b41a828b 242 * - CRCPoly: CRCPOLY[15:0] bits
<> 156:95d6b41a828b 243 */
<> 156:95d6b41a828b 244 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
<> 156:95d6b41a828b 245 {
<> 156:95d6b41a828b 246 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
<> 156:95d6b41a828b 247 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
<> 156:95d6b41a828b 248 }
<> 156:95d6b41a828b 249 status = SUCCESS;
<> 156:95d6b41a828b 250 }
<> 156:95d6b41a828b 251
<> 156:95d6b41a828b 252 #if defined (SPI_I2S_SUPPORT)
<> 156:95d6b41a828b 253 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
<> 156:95d6b41a828b 254 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
<> 156:95d6b41a828b 255 #endif /* SPI_I2S_SUPPORT */
<> 156:95d6b41a828b 256 return status;
<> 156:95d6b41a828b 257 }
<> 156:95d6b41a828b 258
<> 156:95d6b41a828b 259 /**
<> 156:95d6b41a828b 260 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
<> 156:95d6b41a828b 261 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
<> 156:95d6b41a828b 262 * whose fields will be set to default values.
<> 156:95d6b41a828b 263 * @retval None
<> 156:95d6b41a828b 264 */
<> 156:95d6b41a828b 265 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
<> 156:95d6b41a828b 266 {
<> 156:95d6b41a828b 267 /* Set SPI_InitStruct fields to default values */
<> 156:95d6b41a828b 268 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
<> 156:95d6b41a828b 269 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
<> 156:95d6b41a828b 270 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
<> 156:95d6b41a828b 271 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
<> 156:95d6b41a828b 272 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
<> 156:95d6b41a828b 273 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
<> 156:95d6b41a828b 274 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
<> 156:95d6b41a828b 275 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
<> 156:95d6b41a828b 276 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
<> 156:95d6b41a828b 277 SPI_InitStruct->CRCPoly = 7U;
<> 156:95d6b41a828b 278 }
<> 156:95d6b41a828b 279
<> 156:95d6b41a828b 280 /**
<> 156:95d6b41a828b 281 * @}
<> 156:95d6b41a828b 282 */
<> 156:95d6b41a828b 283
<> 156:95d6b41a828b 284 /**
<> 156:95d6b41a828b 285 * @}
<> 156:95d6b41a828b 286 */
<> 156:95d6b41a828b 287
<> 156:95d6b41a828b 288 /**
<> 156:95d6b41a828b 289 * @}
<> 156:95d6b41a828b 290 */
<> 156:95d6b41a828b 291
<> 156:95d6b41a828b 292 #if defined(SPI_I2S_SUPPORT)
<> 156:95d6b41a828b 293 /** @addtogroup I2S_LL
<> 156:95d6b41a828b 294 * @{
<> 156:95d6b41a828b 295 */
<> 156:95d6b41a828b 296
<> 156:95d6b41a828b 297 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 298 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 299 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 300 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
<> 156:95d6b41a828b 301 * @{
<> 156:95d6b41a828b 302 */
<> 156:95d6b41a828b 303 /* I2S registers Masks */
<> 156:95d6b41a828b 304 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
<> 156:95d6b41a828b 305 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
<> 156:95d6b41a828b 306 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
<> 156:95d6b41a828b 307
<> 156:95d6b41a828b 308 #define I2S_I2SPR_CLEAR_MASK 0x0002U
<> 156:95d6b41a828b 309 /**
<> 156:95d6b41a828b 310 * @}
<> 156:95d6b41a828b 311 */
<> 156:95d6b41a828b 312 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 313 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
<> 156:95d6b41a828b 314 * @{
<> 156:95d6b41a828b 315 */
<> 156:95d6b41a828b 316
<> 156:95d6b41a828b 317 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
<> 156:95d6b41a828b 318 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
<> 156:95d6b41a828b 319 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
<> 156:95d6b41a828b 320 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
<> 156:95d6b41a828b 321
<> 156:95d6b41a828b 322 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
<> 156:95d6b41a828b 323 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
<> 156:95d6b41a828b 324
<> 156:95d6b41a828b 325 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
<> 156:95d6b41a828b 326 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
<> 156:95d6b41a828b 327 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
<> 156:95d6b41a828b 328 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
<> 156:95d6b41a828b 329 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
<> 156:95d6b41a828b 330
<> 156:95d6b41a828b 331 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
<> 156:95d6b41a828b 332 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
<> 156:95d6b41a828b 333 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
<> 156:95d6b41a828b 334 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
<> 156:95d6b41a828b 335
<> 156:95d6b41a828b 336 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
<> 156:95d6b41a828b 337 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
<> 156:95d6b41a828b 338
<> 156:95d6b41a828b 339 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
<> 156:95d6b41a828b 340 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
<> 156:95d6b41a828b 341 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
<> 156:95d6b41a828b 342
<> 156:95d6b41a828b 343 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
<> 156:95d6b41a828b 344
<> 156:95d6b41a828b 345 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
<> 156:95d6b41a828b 346 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
<> 156:95d6b41a828b 347 /**
<> 156:95d6b41a828b 348 * @}
<> 156:95d6b41a828b 349 */
<> 156:95d6b41a828b 350
<> 156:95d6b41a828b 351 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 352
<> 156:95d6b41a828b 353 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 354 /** @addtogroup I2S_LL_Exported_Functions
<> 156:95d6b41a828b 355 * @{
<> 156:95d6b41a828b 356 */
<> 156:95d6b41a828b 357
<> 156:95d6b41a828b 358 /** @addtogroup I2S_LL_EF_Init
<> 156:95d6b41a828b 359 * @{
<> 156:95d6b41a828b 360 */
<> 156:95d6b41a828b 361
<> 156:95d6b41a828b 362 /**
<> 156:95d6b41a828b 363 * @brief De-initialize the SPI/I2S registers to their default reset values.
<> 156:95d6b41a828b 364 * @param SPIx SPI Instance
<> 156:95d6b41a828b 365 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 366 * - SUCCESS: SPI registers are de-initialized
<> 156:95d6b41a828b 367 * - ERROR: SPI registers are not de-initialized
<> 156:95d6b41a828b 368 */
<> 156:95d6b41a828b 369 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
<> 156:95d6b41a828b 370 {
<> 156:95d6b41a828b 371 return LL_SPI_DeInit(SPIx);
<> 156:95d6b41a828b 372 }
<> 156:95d6b41a828b 373
<> 156:95d6b41a828b 374 /**
<> 156:95d6b41a828b 375 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
<> 156:95d6b41a828b 376 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
<> 156:95d6b41a828b 377 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 156:95d6b41a828b 378 * @param SPIx SPI Instance
<> 156:95d6b41a828b 379 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
<> 156:95d6b41a828b 380 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 381 * - SUCCESS: SPI registers are Initialized
<> 156:95d6b41a828b 382 * - ERROR: SPI registers are not Initialized
<> 156:95d6b41a828b 383 */
<> 156:95d6b41a828b 384 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
<> 156:95d6b41a828b 385 {
<> 156:95d6b41a828b 386 uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
<> 156:95d6b41a828b 387 uint32_t tmp = 0U;
<> 156:95d6b41a828b 388 LL_RCC_ClocksTypeDef rcc_clocks;
<> 156:95d6b41a828b 389 uint32_t sourceclock = 0U;
<> 156:95d6b41a828b 390 ErrorStatus status = ERROR;
<> 156:95d6b41a828b 391
<> 156:95d6b41a828b 392 /* Check the I2S parameters */
<> 156:95d6b41a828b 393 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
<> 156:95d6b41a828b 394 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
<> 156:95d6b41a828b 395 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
<> 156:95d6b41a828b 396 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
<> 156:95d6b41a828b 397 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
<> 156:95d6b41a828b 398 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
<> 156:95d6b41a828b 399 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
<> 156:95d6b41a828b 400
<> 156:95d6b41a828b 401 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
<> 156:95d6b41a828b 402 {
<> 156:95d6b41a828b 403 /*---------------------------- SPIx I2SCFGR Configuration --------------------
<> 156:95d6b41a828b 404 * Configure SPIx I2SCFGR with parameters:
<> 156:95d6b41a828b 405 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
<> 156:95d6b41a828b 406 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
<> 156:95d6b41a828b 407 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
<> 156:95d6b41a828b 408 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
<> 156:95d6b41a828b 409 */
<> 156:95d6b41a828b 410
<> 156:95d6b41a828b 411 /* Write to SPIx I2SCFGR */
<> 156:95d6b41a828b 412 MODIFY_REG(SPIx->I2SCFGR,
<> 156:95d6b41a828b 413 I2S_I2SCFGR_CLEAR_MASK,
<> 156:95d6b41a828b 414 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
<> 156:95d6b41a828b 415 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
<> 156:95d6b41a828b 416 SPI_I2SCFGR_I2SMOD);
<> 156:95d6b41a828b 417
<> 156:95d6b41a828b 418 /*---------------------------- SPIx I2SPR Configuration ----------------------
<> 156:95d6b41a828b 419 * Configure SPIx I2SPR with parameters:
<> 156:95d6b41a828b 420 * - MCLKOutput: SPI_I2SPR_MCKOE bit
<> 156:95d6b41a828b 421 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
<> 156:95d6b41a828b 422 */
<> 156:95d6b41a828b 423
<> 156:95d6b41a828b 424 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
<> 156:95d6b41a828b 425 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
<> 156:95d6b41a828b 426 */
<> 156:95d6b41a828b 427 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
<> 156:95d6b41a828b 428 {
<> 156:95d6b41a828b 429 /* Check the frame length (For the Prescaler computing)
<> 156:95d6b41a828b 430 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
<> 156:95d6b41a828b 431 */
<> 156:95d6b41a828b 432 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
<> 156:95d6b41a828b 433 {
<> 156:95d6b41a828b 434 /* Packet length is 32 bits */
<> 156:95d6b41a828b 435 packetlength = 2U;
<> 156:95d6b41a828b 436 }
<> 156:95d6b41a828b 437
<> 156:95d6b41a828b 438 /* I2S Clock source is System clock: Get System Clock frequency */
<> 156:95d6b41a828b 439 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
<> 156:95d6b41a828b 440
<> 156:95d6b41a828b 441 /* Get the source clock value: based on System Clock value */
<> 156:95d6b41a828b 442 sourceclock = rcc_clocks.SYSCLK_Frequency;
<> 156:95d6b41a828b 443
<> 156:95d6b41a828b 444 /* Compute the Real divider depending on the MCLK output state with a floating point */
<> 156:95d6b41a828b 445 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
<> 156:95d6b41a828b 446 {
<> 156:95d6b41a828b 447 /* MCLK output is enabled */
<> 156:95d6b41a828b 448 tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
<> 156:95d6b41a828b 449 }
<> 156:95d6b41a828b 450 else
<> 156:95d6b41a828b 451 {
<> 156:95d6b41a828b 452 /* MCLK output is disabled */
<> 156:95d6b41a828b 453 tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
<> 156:95d6b41a828b 454 }
<> 156:95d6b41a828b 455
<> 156:95d6b41a828b 456 /* Remove the floating point */
<> 156:95d6b41a828b 457 tmp = tmp / 10U;
<> 156:95d6b41a828b 458
<> 156:95d6b41a828b 459 /* Check the parity of the divider */
<> 156:95d6b41a828b 460 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
<> 156:95d6b41a828b 461
<> 156:95d6b41a828b 462 /* Compute the i2sdiv prescaler */
<> 156:95d6b41a828b 463 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
<> 156:95d6b41a828b 464
<> 156:95d6b41a828b 465 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
<> 156:95d6b41a828b 466 i2sodd = (uint16_t)(i2sodd << 8U);
<> 156:95d6b41a828b 467 }
<> 156:95d6b41a828b 468
<> 156:95d6b41a828b 469 /* Test if the divider is 1 or 0 or greater than 0xFF */
<> 156:95d6b41a828b 470 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
<> 156:95d6b41a828b 471 {
<> 156:95d6b41a828b 472 /* Set the default values */
<> 156:95d6b41a828b 473 i2sdiv = 2U;
<> 156:95d6b41a828b 474 i2sodd = 0U;
<> 156:95d6b41a828b 475 }
<> 156:95d6b41a828b 476
<> 156:95d6b41a828b 477 /* Write to SPIx I2SPR register the computed value */
<> 156:95d6b41a828b 478 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
<> 156:95d6b41a828b 479
<> 156:95d6b41a828b 480 status = SUCCESS;
<> 156:95d6b41a828b 481 }
<> 156:95d6b41a828b 482 return status;
<> 156:95d6b41a828b 483 }
<> 156:95d6b41a828b 484
<> 156:95d6b41a828b 485 /**
<> 156:95d6b41a828b 486 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
<> 156:95d6b41a828b 487 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
<> 156:95d6b41a828b 488 * whose fields will be set to default values.
<> 156:95d6b41a828b 489 * @retval None
<> 156:95d6b41a828b 490 */
<> 156:95d6b41a828b 491 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
<> 156:95d6b41a828b 492 {
<> 156:95d6b41a828b 493 /*--------------- Reset I2S init structure parameters values -----------------*/
<> 156:95d6b41a828b 494 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
<> 156:95d6b41a828b 495 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
<> 156:95d6b41a828b 496 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
<> 156:95d6b41a828b 497 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
<> 156:95d6b41a828b 498 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
<> 156:95d6b41a828b 499 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
<> 156:95d6b41a828b 500 }
<> 156:95d6b41a828b 501
<> 156:95d6b41a828b 502 /**
<> 156:95d6b41a828b 503 * @brief Set linear and parity prescaler.
<> 156:95d6b41a828b 504 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
<> 156:95d6b41a828b 505 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
<> 156:95d6b41a828b 506 * @param SPIx SPI Instance
<> 156:95d6b41a828b 507 * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
<> 156:95d6b41a828b 508 * @param PrescalerParity This parameter can be one of the following values:
<> 156:95d6b41a828b 509 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<> 156:95d6b41a828b 510 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<> 156:95d6b41a828b 511 * @retval None
<> 156:95d6b41a828b 512 */
<> 156:95d6b41a828b 513 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
<> 156:95d6b41a828b 514 {
<> 156:95d6b41a828b 515 /* Check the I2S parameters */
<> 156:95d6b41a828b 516 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
<> 156:95d6b41a828b 517 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
<> 156:95d6b41a828b 518 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
<> 156:95d6b41a828b 519
<> 156:95d6b41a828b 520 /* Write to SPIx I2SPR */
<> 156:95d6b41a828b 521 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
<> 156:95d6b41a828b 522 }
<> 156:95d6b41a828b 523
<> 156:95d6b41a828b 524 /**
<> 156:95d6b41a828b 525 * @}
<> 156:95d6b41a828b 526 */
<> 156:95d6b41a828b 527
<> 156:95d6b41a828b 528 /**
<> 156:95d6b41a828b 529 * @}
<> 156:95d6b41a828b 530 */
<> 156:95d6b41a828b 531
<> 156:95d6b41a828b 532 /**
<> 156:95d6b41a828b 533 * @}
<> 156:95d6b41a828b 534 */
<> 156:95d6b41a828b 535 #endif /* SPI_I2S_SUPPORT */
<> 156:95d6b41a828b 536
<> 156:95d6b41a828b 537 #endif /* defined (SPI1) || defined (SPI2) */
<> 156:95d6b41a828b 538
<> 156:95d6b41a828b 539 /**
<> 156:95d6b41a828b 540 * @}
<> 156:95d6b41a828b 541 */
<> 156:95d6b41a828b 542
<> 156:95d6b41a828b 543 #endif /* USE_FULL_LL_DRIVER */
<> 156:95d6b41a828b 544
<> 156:95d6b41a828b 545 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/