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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 180:96ed750bd169

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	156:95d6b41a828b	1	/**
<>	156:95d6b41a828b	2	******************************************************************************
<>	156:95d6b41a828b	3	* @file stm32f0xx_ll_rcc.h
<>	156:95d6b41a828b	4	* @author MCD Application Team
<>	156:95d6b41a828b	5	* @brief Header file of RCC LL module.
<>	156:95d6b41a828b	6	******************************************************************************
<>	156:95d6b41a828b	7	* @attention
<>	156:95d6b41a828b	8	*
<>	156:95d6b41a828b	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	156:95d6b41a828b	10	*
<>	156:95d6b41a828b	11	* Redistribution and use in source and binary forms, with or without modification,
<>	156:95d6b41a828b	12	* are permitted provided that the following conditions are met:
<>	156:95d6b41a828b	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	156:95d6b41a828b	14	* this list of conditions and the following disclaimer.
<>	156:95d6b41a828b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	156:95d6b41a828b	16	* this list of conditions and the following disclaimer in the documentation
<>	156:95d6b41a828b	17	* and/or other materials provided with the distribution.
<>	156:95d6b41a828b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	156:95d6b41a828b	19	* may be used to endorse or promote products derived from this software
<>	156:95d6b41a828b	20	* without specific prior written permission.
<>	156:95d6b41a828b	21	*
<>	156:95d6b41a828b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	156:95d6b41a828b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	156:95d6b41a828b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	156:95d6b41a828b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	156:95d6b41a828b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	156:95d6b41a828b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	156:95d6b41a828b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	156:95d6b41a828b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	156:95d6b41a828b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	156:95d6b41a828b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	156:95d6b41a828b	32	*
<>	156:95d6b41a828b	33	******************************************************************************
<>	156:95d6b41a828b	34	*/
<>	156:95d6b41a828b	35
<>	156:95d6b41a828b	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	156:95d6b41a828b	37	#ifndef __STM32F0xx_LL_RCC_H
<>	156:95d6b41a828b	38	#define __STM32F0xx_LL_RCC_H
<>	156:95d6b41a828b	39
<>	156:95d6b41a828b	40	#ifdef __cplusplus
<>	156:95d6b41a828b	41	extern "C" {
<>	156:95d6b41a828b	42	#endif
<>	156:95d6b41a828b	43
<>	156:95d6b41a828b	44	/* Includes ------------------------------------------------------------------*/
<>	156:95d6b41a828b	45	#include "stm32f0xx.h"
<>	156:95d6b41a828b	46
<>	156:95d6b41a828b	47	/** @addtogroup STM32F0xx_LL_Driver
<>	156:95d6b41a828b	48	* @{
<>	156:95d6b41a828b	49	*/
<>	156:95d6b41a828b	50
<>	156:95d6b41a828b	51	#if defined(RCC)
<>	156:95d6b41a828b	52
<>	156:95d6b41a828b	53	/** @defgroup RCC_LL RCC
<>	156:95d6b41a828b	54	* @{
<>	156:95d6b41a828b	55	*/
<>	156:95d6b41a828b	56
<>	156:95d6b41a828b	57	/* Private types -------------------------------------------------------------*/
<>	156:95d6b41a828b	58	/* Private variables ---------------------------------------------------------*/
<>	156:95d6b41a828b	59	/* Private constants ---------------------------------------------------------*/
<>	156:95d6b41a828b	60	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
<>	156:95d6b41a828b	61	* @{
<>	156:95d6b41a828b	62	*/
<>	156:95d6b41a828b	63	/* Defines used for the bit position in the register and perform offsets*/
<>	156:95d6b41a828b	64	#define RCC_POSITION_HPRE (uint32_t)4U /!< field position in register RCC_CFGR /
<>	156:95d6b41a828b	65	#define RCC_POSITION_PPRE1 (uint32_t)8U /!< field position in register RCC_CFGR /
<>	156:95d6b41a828b	66	#define RCC_POSITION_PLLMUL (uint32_t)18U /!< field position in register RCC_CFGR /
<>	156:95d6b41a828b	67	#define RCC_POSITION_HSICAL (uint32_t)8U /!< field position in register RCC_CR /
<>	156:95d6b41a828b	68	#define RCC_POSITION_HSITRIM (uint32_t)3U /!< field position in register RCC_CR /
<>	156:95d6b41a828b	69	#define RCC_POSITION_HSI14TRIM (uint32_t)3U /!< field position in register RCC_CR2 /
<>	156:95d6b41a828b	70	#define RCC_POSITION_HSI14CAL (uint32_t)8U /!< field position in register RCC_CR2 /
<>	156:95d6b41a828b	71	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	72	#define RCC_POSITION_HSI48CAL (uint32_t)24U /!< field position in register RCC_CR2 /
<>	156:95d6b41a828b	73	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	74	#define RCC_POSITION_USART1SW (uint32_t)0U /!< field position in register RCC_CFGR3 /
<>	156:95d6b41a828b	75	#define RCC_POSITION_USART2SW (uint32_t)16U /!< field position in register RCC_CFGR3 /
<>	156:95d6b41a828b	76	#define RCC_POSITION_USART3SW (uint32_t)18U /!< field position in register RCC_CFGR3 /
<>	156:95d6b41a828b	77
<>	156:95d6b41a828b	78	/**
<>	156:95d6b41a828b	79	* @}
<>	156:95d6b41a828b	80	*/
<>	156:95d6b41a828b	81
<>	156:95d6b41a828b	82	/* Private macros ------------------------------------------------------------*/
<>	156:95d6b41a828b	83	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	84	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
<>	156:95d6b41a828b	85	* @{
<>	156:95d6b41a828b	86	*/
<>	156:95d6b41a828b	87	/**
<>	156:95d6b41a828b	88	* @}
<>	156:95d6b41a828b	89	*/
<>	156:95d6b41a828b	90	#endif /USE_FULL_LL_DRIVER/
<>	156:95d6b41a828b	91	/* Exported types ------------------------------------------------------------*/
<>	156:95d6b41a828b	92	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	93	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
<>	156:95d6b41a828b	94	* @{
<>	156:95d6b41a828b	95	*/
<>	156:95d6b41a828b	96
<>	156:95d6b41a828b	97	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
<>	156:95d6b41a828b	98	* @{
<>	156:95d6b41a828b	99	*/
<>	156:95d6b41a828b	100
<>	156:95d6b41a828b	101	/**
<>	156:95d6b41a828b	102	* @brief RCC Clocks Frequency Structure
<>	156:95d6b41a828b	103	*/
<>	156:95d6b41a828b	104	typedef struct
<>	156:95d6b41a828b	105	{
<>	156:95d6b41a828b	106	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
<>	156:95d6b41a828b	107	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
<>	156:95d6b41a828b	108	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
<>	156:95d6b41a828b	109	} LL_RCC_ClocksTypeDef;
<>	156:95d6b41a828b	110
<>	156:95d6b41a828b	111	/**
<>	156:95d6b41a828b	112	* @}
<>	156:95d6b41a828b	113	*/
<>	156:95d6b41a828b	114
<>	156:95d6b41a828b	115	/**
<>	156:95d6b41a828b	116	* @}
<>	156:95d6b41a828b	117	*/
<>	156:95d6b41a828b	118	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	119
<>	156:95d6b41a828b	120	/* Exported constants --------------------------------------------------------*/
<>	156:95d6b41a828b	121	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
<>	156:95d6b41a828b	122	* @{
<>	156:95d6b41a828b	123	*/
<>	156:95d6b41a828b	124
<>	156:95d6b41a828b	125	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
<>	156:95d6b41a828b	126	* @brief Defines used to adapt values of different oscillators
<>	156:95d6b41a828b	127	* @note These values could be modified in the user environment according to
<>	156:95d6b41a828b	128	* HW set-up.
<>	156:95d6b41a828b	129	* @{
<>	156:95d6b41a828b	130	*/
<>	156:95d6b41a828b	131	#if !defined (HSE_VALUE)
Anna Bridge	180:96ed750bd169	132	#define HSE_VALUE 8000000U /!< Value of the HSE oscillator in Hz /
<>	156:95d6b41a828b	133	#endif /* HSE_VALUE */
<>	156:95d6b41a828b	134
<>	156:95d6b41a828b	135	#if !defined (HSI_VALUE)
Anna Bridge	180:96ed750bd169	136	#define HSI_VALUE 8000000U /!< Value of the HSI oscillator in Hz /
<>	156:95d6b41a828b	137	#endif /* HSI_VALUE */
<>	156:95d6b41a828b	138
<>	156:95d6b41a828b	139	#if !defined (LSE_VALUE)
Anna Bridge	180:96ed750bd169	140	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
<>	156:95d6b41a828b	141	#endif /* LSE_VALUE */
<>	156:95d6b41a828b	142
<>	156:95d6b41a828b	143	#if !defined (LSI_VALUE)
Anna Bridge	180:96ed750bd169	144	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
<>	156:95d6b41a828b	145	#endif /* LSI_VALUE */
<>	156:95d6b41a828b	146	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	147
<>	156:95d6b41a828b	148	#if !defined (HSI48_VALUE)
Anna Bridge	180:96ed750bd169	149	#define HSI48_VALUE 48000000U /!< Value of the HSI48 oscillator in Hz /
<>	156:95d6b41a828b	150	#endif /* HSI48_VALUE */
<>	156:95d6b41a828b	151	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	152	/**
<>	156:95d6b41a828b	153	* @}
<>	156:95d6b41a828b	154	*/
<>	156:95d6b41a828b	155
<>	156:95d6b41a828b	156	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	156:95d6b41a828b	157	* @brief Flags defines which can be used with LL_RCC_WriteReg function
<>	156:95d6b41a828b	158	* @{
<>	156:95d6b41a828b	159	*/
<>	156:95d6b41a828b	160	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
<>	156:95d6b41a828b	161	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
<>	156:95d6b41a828b	162	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
<>	156:95d6b41a828b	163	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
<>	156:95d6b41a828b	164	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
<>	156:95d6b41a828b	165	#define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /!< HSI14 Ready Interrupt Clear /
<>	156:95d6b41a828b	166	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	167	#define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /!< HSI48 Ready Interrupt Clear /
<>	156:95d6b41a828b	168	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	169	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
<>	156:95d6b41a828b	170	/**
<>	156:95d6b41a828b	171	* @}
<>	156:95d6b41a828b	172	*/
<>	156:95d6b41a828b	173
<>	156:95d6b41a828b	174	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
<>	156:95d6b41a828b	175	* @brief Flags defines which can be used with LL_RCC_ReadReg function
<>	156:95d6b41a828b	176	* @{
<>	156:95d6b41a828b	177	*/
<>	156:95d6b41a828b	178	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
<>	156:95d6b41a828b	179	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
<>	156:95d6b41a828b	180	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
<>	156:95d6b41a828b	181	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
<>	156:95d6b41a828b	182	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
<>	156:95d6b41a828b	183	#define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /!< HSI14 Ready Interrupt flag /
<>	156:95d6b41a828b	184	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	185	#define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
<>	156:95d6b41a828b	186	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	187	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
<>	156:95d6b41a828b	188	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /!< OBL reset flag /
<>	156:95d6b41a828b	189	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
<>	156:95d6b41a828b	190	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
<>	156:95d6b41a828b	191	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
<>	156:95d6b41a828b	192	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
<>	156:95d6b41a828b	193	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
<>	156:95d6b41a828b	194	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
<>	156:95d6b41a828b	195	#if defined(RCC_CSR_V18PWRRSTF)
<>	156:95d6b41a828b	196	#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /!< Reset flag of the 1.8 V domain. /
<>	156:95d6b41a828b	197	#endif /* RCC_CSR_V18PWRRSTF */
<>	156:95d6b41a828b	198	/**
<>	156:95d6b41a828b	199	* @}
<>	156:95d6b41a828b	200	*/
<>	156:95d6b41a828b	201
<>	156:95d6b41a828b	202	/** @defgroup RCC_LL_EC_IT IT Defines
<>	156:95d6b41a828b	203	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
<>	156:95d6b41a828b	204	* @{
<>	156:95d6b41a828b	205	*/
<>	156:95d6b41a828b	206	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
<>	156:95d6b41a828b	207	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
<>	156:95d6b41a828b	208	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
<>	156:95d6b41a828b	209	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
<>	156:95d6b41a828b	210	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
<>	156:95d6b41a828b	211	#define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /!< HSI14 Ready Interrupt Enable /
<>	156:95d6b41a828b	212	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	213	#define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /!< HSI48 Ready Interrupt Enable /
<>	156:95d6b41a828b	214	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	215	/**
<>	156:95d6b41a828b	216	* @}
<>	156:95d6b41a828b	217	*/
<>	156:95d6b41a828b	218
<>	156:95d6b41a828b	219	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
<>	156:95d6b41a828b	220	* @{
<>	156:95d6b41a828b	221	*/
<>	156:95d6b41a828b	222	#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /!< Xtal mode lower driving capability /
<>	156:95d6b41a828b	223	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< Xtal mode medium low driving capability /
<>	156:95d6b41a828b	224	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< Xtal mode medium high driving capability /
<>	156:95d6b41a828b	225	#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
<>	156:95d6b41a828b	226	/**
<>	156:95d6b41a828b	227	* @}
<>	156:95d6b41a828b	228	*/
<>	156:95d6b41a828b	229
<>	156:95d6b41a828b	230	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
<>	156:95d6b41a828b	231	* @{
<>	156:95d6b41a828b	232	*/
<>	156:95d6b41a828b	233	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
<>	156:95d6b41a828b	234	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
<>	156:95d6b41a828b	235	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
<>	156:95d6b41a828b	236	#if defined(RCC_CFGR_SW_HSI48)
<>	156:95d6b41a828b	237	#define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /!< HSI48 selection as system clock /
<>	156:95d6b41a828b	238	#endif /* RCC_CFGR_SW_HSI48 */
<>	156:95d6b41a828b	239	/**
<>	156:95d6b41a828b	240	* @}
<>	156:95d6b41a828b	241	*/
<>	156:95d6b41a828b	242
<>	156:95d6b41a828b	243	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
<>	156:95d6b41a828b	244	* @{
<>	156:95d6b41a828b	245	*/
<>	156:95d6b41a828b	246	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	156:95d6b41a828b	247	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	156:95d6b41a828b	248	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	156:95d6b41a828b	249	#if defined(RCC_CFGR_SWS_HSI48)
<>	156:95d6b41a828b	250	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /!< HSI48 used as system clock /
<>	156:95d6b41a828b	251	#endif /* RCC_CFGR_SWS_HSI48 */
<>	156:95d6b41a828b	252	/**
<>	156:95d6b41a828b	253	* @}
<>	156:95d6b41a828b	254	*/
<>	156:95d6b41a828b	255
<>	156:95d6b41a828b	256	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
<>	156:95d6b41a828b	257	* @{
<>	156:95d6b41a828b	258	*/
<>	156:95d6b41a828b	259	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
<>	156:95d6b41a828b	260	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
<>	156:95d6b41a828b	261	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
<>	156:95d6b41a828b	262	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
<>	156:95d6b41a828b	263	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
<>	156:95d6b41a828b	264	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
<>	156:95d6b41a828b	265	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
<>	156:95d6b41a828b	266	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
<>	156:95d6b41a828b	267	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
<>	156:95d6b41a828b	268	/**
<>	156:95d6b41a828b	269	* @}
<>	156:95d6b41a828b	270	*/
<>	156:95d6b41a828b	271
<>	156:95d6b41a828b	272	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
<>	156:95d6b41a828b	273	* @{
<>	156:95d6b41a828b	274	*/
<>	156:95d6b41a828b	275	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /!< HCLK not divided /
<>	156:95d6b41a828b	276	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /!< HCLK divided by 2 /
<>	156:95d6b41a828b	277	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /!< HCLK divided by 4 /
<>	156:95d6b41a828b	278	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /!< HCLK divided by 8 /
<>	156:95d6b41a828b	279	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /!< HCLK divided by 16 /
<>	156:95d6b41a828b	280	/**
<>	156:95d6b41a828b	281	* @}
<>	156:95d6b41a828b	282	*/
<>	156:95d6b41a828b	283
<>	156:95d6b41a828b	284	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
<>	156:95d6b41a828b	285	* @{
<>	156:95d6b41a828b	286	*/
<>	156:95d6b41a828b	287	#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /!< MCO output disabled, no clock on MCO /
<>	156:95d6b41a828b	288	#define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /!< HSI14 oscillator clock selected /
<>	156:95d6b41a828b	289	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /!< SYSCLK selection as MCO source /
<>	156:95d6b41a828b	290	#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /!< HSI selection as MCO source /
<>	156:95d6b41a828b	291	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /!< HSE selection as MCO source /
<>	156:95d6b41a828b	292	#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /!< LSI selection as MCO source /
<>	156:95d6b41a828b	293	#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /!< LSE selection as MCO source /
<>	156:95d6b41a828b	294	#if defined(RCC_CFGR_MCOSEL_HSI48)
<>	156:95d6b41a828b	295	#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /!< HSI48 selection as MCO source /
<>	156:95d6b41a828b	296	#endif /* RCC_CFGR_MCOSEL_HSI48 */
<>	156:95d6b41a828b	297	#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /!< PLL clock divided by 2/
<>	156:95d6b41a828b	298	#if defined(RCC_CFGR_PLLNODIV)
<>	156:95d6b41a828b	299	#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 \| RCC_CFGR_PLLNODIV) /!< PLL clock selected/
<>	156:95d6b41a828b	300	#endif /* RCC_CFGR_PLLNODIV */
<>	156:95d6b41a828b	301	/**
<>	156:95d6b41a828b	302	* @}
<>	156:95d6b41a828b	303	*/
<>	156:95d6b41a828b	304
<>	156:95d6b41a828b	305	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
<>	156:95d6b41a828b	306	* @{
<>	156:95d6b41a828b	307	*/
<>	156:95d6b41a828b	308	#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/!< MCO Clock divided by 1 /
<>	156:95d6b41a828b	309	#if defined(RCC_CFGR_MCOPRE)
<>	156:95d6b41a828b	310	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO Clock divided by 2 /
<>	156:95d6b41a828b	311	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO Clock divided by 4 /
<>	156:95d6b41a828b	312	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO Clock divided by 8 /
<>	156:95d6b41a828b	313	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO Clock divided by 16 /
<>	156:95d6b41a828b	314	#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /!< MCO Clock divided by 32 /
<>	156:95d6b41a828b	315	#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /!< MCO Clock divided by 64 /
<>	156:95d6b41a828b	316	#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /!< MCO Clock divided by 128 /
<>	156:95d6b41a828b	317	#endif /* RCC_CFGR_MCOPRE */
<>	156:95d6b41a828b	318	/**
<>	156:95d6b41a828b	319	* @}
<>	156:95d6b41a828b	320	*/
<>	156:95d6b41a828b	321
<>	156:95d6b41a828b	322	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	323	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
<>	156:95d6b41a828b	324	* @{
<>	156:95d6b41a828b	325	*/
Anna Bridge	180:96ed750bd169	326	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
Anna Bridge	180:96ed750bd169	327	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
<>	156:95d6b41a828b	328	/**
<>	156:95d6b41a828b	329	* @}
<>	156:95d6b41a828b	330	*/
<>	156:95d6b41a828b	331	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	332
<>	156:95d6b41a828b	333	/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
<>	156:95d6b41a828b	334	* @{
<>	156:95d6b41a828b	335	*/
<>	156:95d6b41a828b	336	#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) \| RCC_CFGR3_USART1SW_PCLK) /!< PCLK1 clock used as USART1 clock source /
<>	156:95d6b41a828b	337	#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) \| RCC_CFGR3_USART1SW_SYSCLK) /!< System clock selected as USART1 clock source /
<>	156:95d6b41a828b	338	#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) \| RCC_CFGR3_USART1SW_LSE) /!< LSE oscillator clock used as USART1 clock source /
<>	156:95d6b41a828b	339	#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) \| RCC_CFGR3_USART1SW_HSI) /!< HSI oscillator clock used as USART1 clock source /
<>	156:95d6b41a828b	340	#if defined(RCC_CFGR3_USART2SW)
<>	156:95d6b41a828b	341	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) \| RCC_CFGR3_USART2SW_PCLK) /!< PCLK1 clock used as USART2 clock source /
<>	156:95d6b41a828b	342	#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) \| RCC_CFGR3_USART2SW_SYSCLK) /!< System clock selected as USART2 clock source /
<>	156:95d6b41a828b	343	#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) \| RCC_CFGR3_USART2SW_LSE) /!< LSE oscillator clock used as USART2 clock source /
<>	156:95d6b41a828b	344	#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) \| RCC_CFGR3_USART2SW_HSI) /!< HSI oscillator clock used as USART2 clock source /
<>	156:95d6b41a828b	345	#endif /* RCC_CFGR3_USART2SW */
<>	156:95d6b41a828b	346	#if defined(RCC_CFGR3_USART3SW)
<>	156:95d6b41a828b	347	#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) \| RCC_CFGR3_USART3SW_PCLK) /!< PCLK1 clock used as USART3 clock source /
<>	156:95d6b41a828b	348	#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) \| RCC_CFGR3_USART3SW_SYSCLK) /!< System clock selected as USART3 clock source /
<>	156:95d6b41a828b	349	#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) \| RCC_CFGR3_USART3SW_LSE) /!< LSE oscillator clock used as USART3 clock source /
<>	156:95d6b41a828b	350	#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) \| RCC_CFGR3_USART3SW_HSI) /!< HSI oscillator clock used as USART3 clock source /
<>	156:95d6b41a828b	351	#endif /* RCC_CFGR3_USART3SW */
<>	156:95d6b41a828b	352	/**
<>	156:95d6b41a828b	353	* @}
<>	156:95d6b41a828b	354	*/
<>	156:95d6b41a828b	355
<>	156:95d6b41a828b	356	/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
<>	156:95d6b41a828b	357	* @{
<>	156:95d6b41a828b	358	*/
<>	156:95d6b41a828b	359	#define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /!< HSI oscillator clock used as I2C1 clock source /
<>	156:95d6b41a828b	360	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /!< System clock selected as I2C1 clock source /
<>	156:95d6b41a828b	361	/**
<>	156:95d6b41a828b	362	* @}
<>	156:95d6b41a828b	363	*/
<>	156:95d6b41a828b	364
<>	156:95d6b41a828b	365	#if defined(CEC)
<>	156:95d6b41a828b	366	/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
<>	156:95d6b41a828b	367	* @{
<>	156:95d6b41a828b	368	*/
<>	156:95d6b41a828b	369	#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /!< HSI clock divided by 244 selected as HDMI CEC entry clock source /
<>	156:95d6b41a828b	370	#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /!< LSE clock selected as HDMI CEC entry clock source /
<>	156:95d6b41a828b	371	/**
<>	156:95d6b41a828b	372	* @}
<>	156:95d6b41a828b	373	*/
<>	156:95d6b41a828b	374
<>	156:95d6b41a828b	375	#endif /* CEC */
<>	156:95d6b41a828b	376
<>	156:95d6b41a828b	377	#if defined(USB)
<>	156:95d6b41a828b	378	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
<>	156:95d6b41a828b	379	* @{
<>	156:95d6b41a828b	380	*/
<>	156:95d6b41a828b	381	#if defined(RCC_CFGR3_USBSW_HSI48)
<>	156:95d6b41a828b	382	#define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /!< HSI48 oscillator clock used as USB clock source /
<>	156:95d6b41a828b	383	#else
<>	156:95d6b41a828b	384	#define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /!< USB Clock disabled /
<>	156:95d6b41a828b	385	#endif /RCC_CFGR3_USBSW_HSI48/
<>	156:95d6b41a828b	386	#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /!< PLL selected as USB clock source /
<>	156:95d6b41a828b	387	/**
<>	156:95d6b41a828b	388	* @}
<>	156:95d6b41a828b	389	*/
<>	156:95d6b41a828b	390
<>	156:95d6b41a828b	391	#endif /* USB */
<>	156:95d6b41a828b	392
<>	156:95d6b41a828b	393	/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
<>	156:95d6b41a828b	394	* @{
<>	156:95d6b41a828b	395	*/
<>	156:95d6b41a828b	396	#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /!< USART1 Clock source selection /
<>	156:95d6b41a828b	397	#if defined(RCC_CFGR3_USART2SW)
<>	156:95d6b41a828b	398	#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /!< USART2 Clock source selection /
<>	156:95d6b41a828b	399	#endif /* RCC_CFGR3_USART2SW */
<>	156:95d6b41a828b	400	#if defined(RCC_CFGR3_USART3SW)
<>	156:95d6b41a828b	401	#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /!< USART3 Clock source selection /
<>	156:95d6b41a828b	402	#endif /* RCC_CFGR3_USART3SW */
<>	156:95d6b41a828b	403	/**
<>	156:95d6b41a828b	404	* @}
<>	156:95d6b41a828b	405	*/
<>	156:95d6b41a828b	406
<>	156:95d6b41a828b	407	/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
<>	156:95d6b41a828b	408	* @{
<>	156:95d6b41a828b	409	*/
<>	156:95d6b41a828b	410	#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /!< I2C1 Clock source selection /
<>	156:95d6b41a828b	411	/**
<>	156:95d6b41a828b	412	* @}
<>	156:95d6b41a828b	413	*/
<>	156:95d6b41a828b	414
<>	156:95d6b41a828b	415	#if defined(CEC)
<>	156:95d6b41a828b	416	/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
<>	156:95d6b41a828b	417	* @{
<>	156:95d6b41a828b	418	*/
<>	156:95d6b41a828b	419	#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /!< CEC Clock source selection /
<>	156:95d6b41a828b	420	/**
<>	156:95d6b41a828b	421	* @}
<>	156:95d6b41a828b	422	*/
<>	156:95d6b41a828b	423	#endif /* CEC */
<>	156:95d6b41a828b	424
<>	156:95d6b41a828b	425	#if defined(USB)
<>	156:95d6b41a828b	426	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
<>	156:95d6b41a828b	427	* @{
<>	156:95d6b41a828b	428	*/
<>	156:95d6b41a828b	429	#define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /!< USB Clock source selection /
<>	156:95d6b41a828b	430	/**
<>	156:95d6b41a828b	431	* @}
<>	156:95d6b41a828b	432	*/
<>	156:95d6b41a828b	433	#endif /* USB */
<>	156:95d6b41a828b	434
<>	156:95d6b41a828b	435	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
<>	156:95d6b41a828b	436	* @{
<>	156:95d6b41a828b	437	*/
Anna Bridge	180:96ed750bd169	438	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
<>	156:95d6b41a828b	439	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
<>	156:95d6b41a828b	440	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
<>	156:95d6b41a828b	441	#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
<>	156:95d6b41a828b	442	/**
<>	156:95d6b41a828b	443	* @}
<>	156:95d6b41a828b	444	*/
<>	156:95d6b41a828b	445
<>	156:95d6b41a828b	446	/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
<>	156:95d6b41a828b	447	* @{
<>	156:95d6b41a828b	448	*/
<>	156:95d6b41a828b	449	#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /!< PLL input clock2 */
<>	156:95d6b41a828b	450	#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /!< PLL input clock3 */
<>	156:95d6b41a828b	451	#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /!< PLL input clock4 */
<>	156:95d6b41a828b	452	#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /!< PLL input clock5 */
<>	156:95d6b41a828b	453	#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /!< PLL input clock6 */
<>	156:95d6b41a828b	454	#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /!< PLL input clock7 */
<>	156:95d6b41a828b	455	#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /!< PLL input clock8 */
<>	156:95d6b41a828b	456	#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /!< PLL input clock9 */
<>	156:95d6b41a828b	457	#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /!< PLL input clock10 */
<>	156:95d6b41a828b	458	#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /!< PLL input clock11 */
<>	156:95d6b41a828b	459	#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /!< PLL input clock12 */
<>	156:95d6b41a828b	460	#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /!< PLL input clock13 */
<>	156:95d6b41a828b	461	#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /!< PLL input clock14 */
<>	156:95d6b41a828b	462	#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /!< PLL input clock15 */
<>	156:95d6b41a828b	463	#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /!< PLL input clock16 */
<>	156:95d6b41a828b	464	/**
<>	156:95d6b41a828b	465	* @}
<>	156:95d6b41a828b	466	*/
<>	156:95d6b41a828b	467
<>	156:95d6b41a828b	468	/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
<>	156:95d6b41a828b	469	* @{
<>	156:95d6b41a828b	470	*/
<>	156:95d6b41a828b	471	#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /!< HSE/PREDIV clock selected as PLL entry clock source /
<>	156:95d6b41a828b	472	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<>	156:95d6b41a828b	473	#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /!< HSI/PREDIV clock selected as PLL entry clock source /
<>	156:95d6b41a828b	474	#if defined(RCC_CFGR_SW_HSI48)
<>	156:95d6b41a828b	475	#define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /!< HSI48/PREDIV clock selected as PLL entry clock source /
<>	156:95d6b41a828b	476	#endif /* RCC_CFGR_SW_HSI48 */
<>	156:95d6b41a828b	477	#else
<>	156:95d6b41a828b	478	#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /!< HSI clock divided by 2 selected as PLL entry clock source /
<>	156:95d6b41a828b	479	#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV1) /!< HSE clock selected as PLL entry clock source /
<>	156:95d6b41a828b	480	#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV2) /!< HSE/2 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	481	#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV3) /!< HSE/3 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	482	#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV4) /!< HSE/4 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	483	#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV5) /!< HSE/5 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	484	#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV6) /!< HSE/6 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	485	#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV7) /!< HSE/7 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	486	#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV8) /!< HSE/8 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	487	#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV9) /!< HSE/9 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	488	#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV10) /!< HSE/10 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	489	#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV11) /!< HSE/11 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	490	#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV12) /!< HSE/12 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	491	#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV13) /!< HSE/13 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	492	#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV14) /!< HSE/14 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	493	#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV15) /!< HSE/15 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	494	#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV \| RCC_CFGR2_PREDIV_DIV16) /!< HSE/16 clock selected as PLL entry clock source /
<>	156:95d6b41a828b	495	#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<>	156:95d6b41a828b	496	/**
<>	156:95d6b41a828b	497	* @}
<>	156:95d6b41a828b	498	*/
<>	156:95d6b41a828b	499
<>	156:95d6b41a828b	500	/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
<>	156:95d6b41a828b	501	* @{
<>	156:95d6b41a828b	502	*/
<>	156:95d6b41a828b	503	#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /!< PREDIV input clock not divided /
<>	156:95d6b41a828b	504	#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /!< PREDIV input clock divided by 2 /
<>	156:95d6b41a828b	505	#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /!< PREDIV input clock divided by 3 /
<>	156:95d6b41a828b	506	#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /!< PREDIV input clock divided by 4 /
<>	156:95d6b41a828b	507	#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /!< PREDIV input clock divided by 5 /
<>	156:95d6b41a828b	508	#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /!< PREDIV input clock divided by 6 /
<>	156:95d6b41a828b	509	#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /!< PREDIV input clock divided by 7 /
<>	156:95d6b41a828b	510	#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /!< PREDIV input clock divided by 8 /
<>	156:95d6b41a828b	511	#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /!< PREDIV input clock divided by 9 /
<>	156:95d6b41a828b	512	#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /!< PREDIV input clock divided by 10 /
<>	156:95d6b41a828b	513	#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /!< PREDIV input clock divided by 11 /
<>	156:95d6b41a828b	514	#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /!< PREDIV input clock divided by 12 /
<>	156:95d6b41a828b	515	#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /!< PREDIV input clock divided by 13 /
<>	156:95d6b41a828b	516	#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /!< PREDIV input clock divided by 14 /
<>	156:95d6b41a828b	517	#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /!< PREDIV input clock divided by 15 /
<>	156:95d6b41a828b	518	#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /!< PREDIV input clock divided by 16 /
<>	156:95d6b41a828b	519	/**
<>	156:95d6b41a828b	520	* @}
<>	156:95d6b41a828b	521	*/
<>	156:95d6b41a828b	522
<>	156:95d6b41a828b	523	/**
<>	156:95d6b41a828b	524	* @}
<>	156:95d6b41a828b	525	*/
<>	156:95d6b41a828b	526
<>	156:95d6b41a828b	527	/* Exported macro ------------------------------------------------------------*/
<>	156:95d6b41a828b	528	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
<>	156:95d6b41a828b	529	* @{
<>	156:95d6b41a828b	530	*/
<>	156:95d6b41a828b	531
<>	156:95d6b41a828b	532	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
<>	156:95d6b41a828b	533	* @{
<>	156:95d6b41a828b	534	*/
<>	156:95d6b41a828b	535
<>	156:95d6b41a828b	536	/**
<>	156:95d6b41a828b	537	* @brief Write a value in RCC register
<>	156:95d6b41a828b	538	* @param __REG__ Register to be written
<>	156:95d6b41a828b	539	* @param __VALUE__ Value to be written in the register
<>	156:95d6b41a828b	540	* @retval None
<>	156:95d6b41a828b	541	*/
<>	156:95d6b41a828b	542	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
<>	156:95d6b41a828b	543
<>	156:95d6b41a828b	544	/**
<>	156:95d6b41a828b	545	* @brief Read a value in RCC register
<>	156:95d6b41a828b	546	* @param __REG__ Register to be read
<>	156:95d6b41a828b	547	* @retval Register value
<>	156:95d6b41a828b	548	*/
<>	156:95d6b41a828b	549	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
<>	156:95d6b41a828b	550	/**
<>	156:95d6b41a828b	551	* @}
<>	156:95d6b41a828b	552	*/
<>	156:95d6b41a828b	553
<>	156:95d6b41a828b	554	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
<>	156:95d6b41a828b	555	* @{
<>	156:95d6b41a828b	556	*/
<>	156:95d6b41a828b	557
<>	156:95d6b41a828b	558	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<>	156:95d6b41a828b	559	/**
<>	156:95d6b41a828b	560	* @brief Helper macro to calculate the PLLCLK frequency
<>	156:95d6b41a828b	561	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
<>	156:95d6b41a828b	562	* , @ref LL_RCC_PLL_GetPrediv());
<>	156:95d6b41a828b	563	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48)
Anna Bridge	180:96ed750bd169	564	* @param __PLLMUL__ This parameter can be one of the following values:
<>	156:95d6b41a828b	565	* @arg @ref LL_RCC_PLL_MUL_2
<>	156:95d6b41a828b	566	* @arg @ref LL_RCC_PLL_MUL_3
<>	156:95d6b41a828b	567	* @arg @ref LL_RCC_PLL_MUL_4
<>	156:95d6b41a828b	568	* @arg @ref LL_RCC_PLL_MUL_5
<>	156:95d6b41a828b	569	* @arg @ref LL_RCC_PLL_MUL_6
<>	156:95d6b41a828b	570	* @arg @ref LL_RCC_PLL_MUL_7
<>	156:95d6b41a828b	571	* @arg @ref LL_RCC_PLL_MUL_8
<>	156:95d6b41a828b	572	* @arg @ref LL_RCC_PLL_MUL_9
<>	156:95d6b41a828b	573	* @arg @ref LL_RCC_PLL_MUL_10
<>	156:95d6b41a828b	574	* @arg @ref LL_RCC_PLL_MUL_11
<>	156:95d6b41a828b	575	* @arg @ref LL_RCC_PLL_MUL_12
<>	156:95d6b41a828b	576	* @arg @ref LL_RCC_PLL_MUL_13
<>	156:95d6b41a828b	577	* @arg @ref LL_RCC_PLL_MUL_14
<>	156:95d6b41a828b	578	* @arg @ref LL_RCC_PLL_MUL_15
<>	156:95d6b41a828b	579	* @arg @ref LL_RCC_PLL_MUL_16
Anna Bridge	180:96ed750bd169	580	* @param __PLLPREDIV__ This parameter can be one of the following values:
<>	156:95d6b41a828b	581	* @arg @ref LL_RCC_PREDIV_DIV_1
<>	156:95d6b41a828b	582	* @arg @ref LL_RCC_PREDIV_DIV_2
<>	156:95d6b41a828b	583	* @arg @ref LL_RCC_PREDIV_DIV_3
<>	156:95d6b41a828b	584	* @arg @ref LL_RCC_PREDIV_DIV_4
<>	156:95d6b41a828b	585	* @arg @ref LL_RCC_PREDIV_DIV_5
<>	156:95d6b41a828b	586	* @arg @ref LL_RCC_PREDIV_DIV_6
<>	156:95d6b41a828b	587	* @arg @ref LL_RCC_PREDIV_DIV_7
<>	156:95d6b41a828b	588	* @arg @ref LL_RCC_PREDIV_DIV_8
<>	156:95d6b41a828b	589	* @arg @ref LL_RCC_PREDIV_DIV_9
<>	156:95d6b41a828b	590	* @arg @ref LL_RCC_PREDIV_DIV_10
<>	156:95d6b41a828b	591	* @arg @ref LL_RCC_PREDIV_DIV_11
<>	156:95d6b41a828b	592	* @arg @ref LL_RCC_PREDIV_DIV_12
<>	156:95d6b41a828b	593	* @arg @ref LL_RCC_PREDIV_DIV_13
<>	156:95d6b41a828b	594	* @arg @ref LL_RCC_PREDIV_DIV_14
<>	156:95d6b41a828b	595	* @arg @ref LL_RCC_PREDIV_DIV_15
<>	156:95d6b41a828b	596	* @arg @ref LL_RCC_PREDIV_DIV_16
<>	156:95d6b41a828b	597	* @retval PLL clock frequency (in Hz)
<>	156:95d6b41a828b	598	*/
<>	156:95d6b41a828b	599	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
<>	156:95d6b41a828b	600	(((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
<>	156:95d6b41a828b	601
<>	156:95d6b41a828b	602	#else
<>	156:95d6b41a828b	603	/**
<>	156:95d6b41a828b	604	* @brief Helper macro to calculate the PLLCLK frequency
<>	156:95d6b41a828b	605	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
<>	156:95d6b41a828b	606	* @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
Anna Bridge	180:96ed750bd169	607	* @param __PLLMUL__ This parameter can be one of the following values:
<>	156:95d6b41a828b	608	* @arg @ref LL_RCC_PLL_MUL_2
<>	156:95d6b41a828b	609	* @arg @ref LL_RCC_PLL_MUL_3
<>	156:95d6b41a828b	610	* @arg @ref LL_RCC_PLL_MUL_4
<>	156:95d6b41a828b	611	* @arg @ref LL_RCC_PLL_MUL_5
<>	156:95d6b41a828b	612	* @arg @ref LL_RCC_PLL_MUL_6
<>	156:95d6b41a828b	613	* @arg @ref LL_RCC_PLL_MUL_7
<>	156:95d6b41a828b	614	* @arg @ref LL_RCC_PLL_MUL_8
<>	156:95d6b41a828b	615	* @arg @ref LL_RCC_PLL_MUL_9
<>	156:95d6b41a828b	616	* @arg @ref LL_RCC_PLL_MUL_10
<>	156:95d6b41a828b	617	* @arg @ref LL_RCC_PLL_MUL_11
<>	156:95d6b41a828b	618	* @arg @ref LL_RCC_PLL_MUL_12
<>	156:95d6b41a828b	619	* @arg @ref LL_RCC_PLL_MUL_13
<>	156:95d6b41a828b	620	* @arg @ref LL_RCC_PLL_MUL_14
<>	156:95d6b41a828b	621	* @arg @ref LL_RCC_PLL_MUL_15
<>	156:95d6b41a828b	622	* @arg @ref LL_RCC_PLL_MUL_16
<>	156:95d6b41a828b	623	* @retval PLL clock frequency (in Hz)
<>	156:95d6b41a828b	624	*/
<>	156:95d6b41a828b	625	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
<>	156:95d6b41a828b	626	((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
<>	156:95d6b41a828b	627	#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<>	156:95d6b41a828b	628	/**
<>	156:95d6b41a828b	629	* @brief Helper macro to calculate the HCLK frequency
<>	156:95d6b41a828b	630	* @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
<>	156:95d6b41a828b	631	* ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
<>	156:95d6b41a828b	632	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
Anna Bridge	180:96ed750bd169	633	* @param __AHBPRESCALER__ This parameter can be one of the following values:
<>	156:95d6b41a828b	634	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	156:95d6b41a828b	635	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	156:95d6b41a828b	636	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	156:95d6b41a828b	637	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	156:95d6b41a828b	638	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	156:95d6b41a828b	639	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	156:95d6b41a828b	640	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	156:95d6b41a828b	641	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	156:95d6b41a828b	642	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	156:95d6b41a828b	643	* @retval HCLK clock frequency (in Hz)
<>	156:95d6b41a828b	644	*/
Anna Bridge	180:96ed750bd169	645	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
<>	156:95d6b41a828b	646
<>	156:95d6b41a828b	647	/**
<>	156:95d6b41a828b	648	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
<>	156:95d6b41a828b	649	* @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
<>	156:95d6b41a828b	650	* ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
<>	156:95d6b41a828b	651	* @param __HCLKFREQ__ HCLK frequency
Anna Bridge	180:96ed750bd169	652	* @param __APB1PRESCALER__ This parameter can be one of the following values:
<>	156:95d6b41a828b	653	* @arg @ref LL_RCC_APB1_DIV_1
<>	156:95d6b41a828b	654	* @arg @ref LL_RCC_APB1_DIV_2
<>	156:95d6b41a828b	655	* @arg @ref LL_RCC_APB1_DIV_4
<>	156:95d6b41a828b	656	* @arg @ref LL_RCC_APB1_DIV_8
<>	156:95d6b41a828b	657	* @arg @ref LL_RCC_APB1_DIV_16
<>	156:95d6b41a828b	658	* @retval PCLK1 clock frequency (in Hz)
<>	156:95d6b41a828b	659	*/
Anna Bridge	180:96ed750bd169	660	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos])
<>	156:95d6b41a828b	661
<>	156:95d6b41a828b	662	/**
<>	156:95d6b41a828b	663	* @}
<>	156:95d6b41a828b	664	*/
<>	156:95d6b41a828b	665
<>	156:95d6b41a828b	666	/**
<>	156:95d6b41a828b	667	* @}
<>	156:95d6b41a828b	668	*/
<>	156:95d6b41a828b	669
<>	156:95d6b41a828b	670	/* Exported functions --------------------------------------------------------*/
<>	156:95d6b41a828b	671	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
<>	156:95d6b41a828b	672	* @{
<>	156:95d6b41a828b	673	*/
<>	156:95d6b41a828b	674
<>	156:95d6b41a828b	675	/** @defgroup RCC_LL_EF_HSE HSE
<>	156:95d6b41a828b	676	* @{
<>	156:95d6b41a828b	677	*/
<>	156:95d6b41a828b	678
<>	156:95d6b41a828b	679	/**
<>	156:95d6b41a828b	680	* @brief Enable the Clock Security System.
<>	156:95d6b41a828b	681	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
<>	156:95d6b41a828b	682	* @retval None
<>	156:95d6b41a828b	683	*/
<>	156:95d6b41a828b	684	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
<>	156:95d6b41a828b	685	{
<>	156:95d6b41a828b	686	SET_BIT(RCC->CR, RCC_CR_CSSON);
<>	156:95d6b41a828b	687	}
<>	156:95d6b41a828b	688
<>	156:95d6b41a828b	689	/**
<>	156:95d6b41a828b	690	* @brief Disable the Clock Security System.
<>	156:95d6b41a828b	691	* @note Cannot be disabled in HSE is ready (only by hardware)
<>	156:95d6b41a828b	692	* @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
<>	156:95d6b41a828b	693	* @retval None
<>	156:95d6b41a828b	694	*/
<>	156:95d6b41a828b	695	__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
<>	156:95d6b41a828b	696	{
<>	156:95d6b41a828b	697	CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
<>	156:95d6b41a828b	698	}
<>	156:95d6b41a828b	699
<>	156:95d6b41a828b	700	/**
<>	156:95d6b41a828b	701	* @brief Enable HSE external oscillator (HSE Bypass)
<>	156:95d6b41a828b	702	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
<>	156:95d6b41a828b	703	* @retval None
<>	156:95d6b41a828b	704	*/
<>	156:95d6b41a828b	705	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
<>	156:95d6b41a828b	706	{
<>	156:95d6b41a828b	707	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
<>	156:95d6b41a828b	708	}
<>	156:95d6b41a828b	709
<>	156:95d6b41a828b	710	/**
<>	156:95d6b41a828b	711	* @brief Disable HSE external oscillator (HSE Bypass)
<>	156:95d6b41a828b	712	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
<>	156:95d6b41a828b	713	* @retval None
<>	156:95d6b41a828b	714	*/
<>	156:95d6b41a828b	715	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
<>	156:95d6b41a828b	716	{
<>	156:95d6b41a828b	717	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<>	156:95d6b41a828b	718	}
<>	156:95d6b41a828b	719
<>	156:95d6b41a828b	720	/**
<>	156:95d6b41a828b	721	* @brief Enable HSE crystal oscillator (HSE ON)
<>	156:95d6b41a828b	722	* @rmtoll CR HSEON LL_RCC_HSE_Enable
<>	156:95d6b41a828b	723	* @retval None
<>	156:95d6b41a828b	724	*/
<>	156:95d6b41a828b	725	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
<>	156:95d6b41a828b	726	{
<>	156:95d6b41a828b	727	SET_BIT(RCC->CR, RCC_CR_HSEON);
<>	156:95d6b41a828b	728	}
<>	156:95d6b41a828b	729
<>	156:95d6b41a828b	730	/**
<>	156:95d6b41a828b	731	* @brief Disable HSE crystal oscillator (HSE ON)
<>	156:95d6b41a828b	732	* @rmtoll CR HSEON LL_RCC_HSE_Disable
<>	156:95d6b41a828b	733	* @retval None
<>	156:95d6b41a828b	734	*/
<>	156:95d6b41a828b	735	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
<>	156:95d6b41a828b	736	{
<>	156:95d6b41a828b	737	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
<>	156:95d6b41a828b	738	}
<>	156:95d6b41a828b	739
<>	156:95d6b41a828b	740	/**
<>	156:95d6b41a828b	741	* @brief Check if HSE oscillator Ready
<>	156:95d6b41a828b	742	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
<>	156:95d6b41a828b	743	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	744	*/
<>	156:95d6b41a828b	745	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
<>	156:95d6b41a828b	746	{
<>	156:95d6b41a828b	747	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
<>	156:95d6b41a828b	748	}
<>	156:95d6b41a828b	749
<>	156:95d6b41a828b	750	/**
<>	156:95d6b41a828b	751	* @}
<>	156:95d6b41a828b	752	*/
<>	156:95d6b41a828b	753
<>	156:95d6b41a828b	754	/** @defgroup RCC_LL_EF_HSI HSI
<>	156:95d6b41a828b	755	* @{
<>	156:95d6b41a828b	756	*/
<>	156:95d6b41a828b	757
<>	156:95d6b41a828b	758	/**
<>	156:95d6b41a828b	759	* @brief Enable HSI oscillator
<>	156:95d6b41a828b	760	* @rmtoll CR HSION LL_RCC_HSI_Enable
<>	156:95d6b41a828b	761	* @retval None
<>	156:95d6b41a828b	762	*/
<>	156:95d6b41a828b	763	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
<>	156:95d6b41a828b	764	{
<>	156:95d6b41a828b	765	SET_BIT(RCC->CR, RCC_CR_HSION);
<>	156:95d6b41a828b	766	}
<>	156:95d6b41a828b	767
<>	156:95d6b41a828b	768	/**
<>	156:95d6b41a828b	769	* @brief Disable HSI oscillator
<>	156:95d6b41a828b	770	* @rmtoll CR HSION LL_RCC_HSI_Disable
<>	156:95d6b41a828b	771	* @retval None
<>	156:95d6b41a828b	772	*/
<>	156:95d6b41a828b	773	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
<>	156:95d6b41a828b	774	{
<>	156:95d6b41a828b	775	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
<>	156:95d6b41a828b	776	}
<>	156:95d6b41a828b	777
<>	156:95d6b41a828b	778	/**
<>	156:95d6b41a828b	779	* @brief Check if HSI clock is ready
<>	156:95d6b41a828b	780	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
<>	156:95d6b41a828b	781	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	782	*/
<>	156:95d6b41a828b	783	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
<>	156:95d6b41a828b	784	{
<>	156:95d6b41a828b	785	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
<>	156:95d6b41a828b	786	}
<>	156:95d6b41a828b	787
<>	156:95d6b41a828b	788	/**
<>	156:95d6b41a828b	789	* @brief Get HSI Calibration value
<>	156:95d6b41a828b	790	* @note When HSITRIM is written, HSICAL is updated with the sum of
<>	156:95d6b41a828b	791	* HSITRIM and the factory trim value
<>	156:95d6b41a828b	792	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
<>	156:95d6b41a828b	793	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<>	156:95d6b41a828b	794	*/
<>	156:95d6b41a828b	795	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
<>	156:95d6b41a828b	796	{
Anna Bridge	180:96ed750bd169	797	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
<>	156:95d6b41a828b	798	}
<>	156:95d6b41a828b	799
<>	156:95d6b41a828b	800	/**
<>	156:95d6b41a828b	801	* @brief Set HSI Calibration trimming
<>	156:95d6b41a828b	802	* @note user-programmable trimming value that is added to the HSICAL
<>	156:95d6b41a828b	803	* @note Default value is 16, which, when added to the HSICAL value,
<>	156:95d6b41a828b	804	* should trim the HSI to 16 MHz +/- 1 %
<>	156:95d6b41a828b	805	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
<>	156:95d6b41a828b	806	* @param Value between Min_Data = 0x00 and Max_Data = 0x1F
<>	156:95d6b41a828b	807	* @retval None
<>	156:95d6b41a828b	808	*/
<>	156:95d6b41a828b	809	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
<>	156:95d6b41a828b	810	{
Anna Bridge	180:96ed750bd169	811	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
<>	156:95d6b41a828b	812	}
<>	156:95d6b41a828b	813
<>	156:95d6b41a828b	814	/**
<>	156:95d6b41a828b	815	* @brief Get HSI Calibration trimming
<>	156:95d6b41a828b	816	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
<>	156:95d6b41a828b	817	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
<>	156:95d6b41a828b	818	*/
<>	156:95d6b41a828b	819	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
<>	156:95d6b41a828b	820	{
Anna Bridge	180:96ed750bd169	821	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
<>	156:95d6b41a828b	822	}
<>	156:95d6b41a828b	823
<>	156:95d6b41a828b	824	/**
<>	156:95d6b41a828b	825	* @}
<>	156:95d6b41a828b	826	*/
<>	156:95d6b41a828b	827
<>	156:95d6b41a828b	828	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	829	/** @defgroup RCC_LL_EF_HSI48 HSI48
<>	156:95d6b41a828b	830	* @{
<>	156:95d6b41a828b	831	*/
<>	156:95d6b41a828b	832
<>	156:95d6b41a828b	833	/**
<>	156:95d6b41a828b	834	* @brief Enable HSI48
<>	156:95d6b41a828b	835	* @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable
<>	156:95d6b41a828b	836	* @retval None
<>	156:95d6b41a828b	837	*/
<>	156:95d6b41a828b	838	__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
<>	156:95d6b41a828b	839	{
<>	156:95d6b41a828b	840	SET_BIT(RCC->CR2, RCC_CR2_HSI48ON);
<>	156:95d6b41a828b	841	}
<>	156:95d6b41a828b	842
<>	156:95d6b41a828b	843	/**
<>	156:95d6b41a828b	844	* @brief Disable HSI48
<>	156:95d6b41a828b	845	* @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable
<>	156:95d6b41a828b	846	* @retval None
<>	156:95d6b41a828b	847	*/
<>	156:95d6b41a828b	848	__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
<>	156:95d6b41a828b	849	{
<>	156:95d6b41a828b	850	CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON);
<>	156:95d6b41a828b	851	}
<>	156:95d6b41a828b	852
<>	156:95d6b41a828b	853	/**
<>	156:95d6b41a828b	854	* @brief Check if HSI48 oscillator Ready
<>	156:95d6b41a828b	855	* @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady
<>	156:95d6b41a828b	856	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	857	*/
<>	156:95d6b41a828b	858	__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
<>	156:95d6b41a828b	859	{
<>	156:95d6b41a828b	860	return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY));
<>	156:95d6b41a828b	861	}
<>	156:95d6b41a828b	862
<>	156:95d6b41a828b	863	/**
<>	156:95d6b41a828b	864	* @brief Get HSI48 Calibration value
<>	156:95d6b41a828b	865	* @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration
<>	156:95d6b41a828b	866	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<>	156:95d6b41a828b	867	*/
<>	156:95d6b41a828b	868	__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
<>	156:95d6b41a828b	869	{
<>	156:95d6b41a828b	870	return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL);
<>	156:95d6b41a828b	871	}
<>	156:95d6b41a828b	872
<>	156:95d6b41a828b	873	/**
<>	156:95d6b41a828b	874	* @}
<>	156:95d6b41a828b	875	*/
<>	156:95d6b41a828b	876
<>	156:95d6b41a828b	877	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	878
<>	156:95d6b41a828b	879	/** @defgroup RCC_LL_EF_HSI14 HSI14
<>	156:95d6b41a828b	880	* @{
<>	156:95d6b41a828b	881	*/
<>	156:95d6b41a828b	882
<>	156:95d6b41a828b	883	/**
<>	156:95d6b41a828b	884	* @brief Enable HSI14
<>	156:95d6b41a828b	885	* @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable
<>	156:95d6b41a828b	886	* @retval None
<>	156:95d6b41a828b	887	*/
<>	156:95d6b41a828b	888	__STATIC_INLINE void LL_RCC_HSI14_Enable(void)
<>	156:95d6b41a828b	889	{
<>	156:95d6b41a828b	890	SET_BIT(RCC->CR2, RCC_CR2_HSI14ON);
<>	156:95d6b41a828b	891	}
<>	156:95d6b41a828b	892
<>	156:95d6b41a828b	893	/**
<>	156:95d6b41a828b	894	* @brief Disable HSI14
<>	156:95d6b41a828b	895	* @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable
<>	156:95d6b41a828b	896	* @retval None
<>	156:95d6b41a828b	897	*/
<>	156:95d6b41a828b	898	__STATIC_INLINE void LL_RCC_HSI14_Disable(void)
<>	156:95d6b41a828b	899	{
<>	156:95d6b41a828b	900	CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON);
<>	156:95d6b41a828b	901	}
<>	156:95d6b41a828b	902
<>	156:95d6b41a828b	903	/**
<>	156:95d6b41a828b	904	* @brief Check if HSI14 oscillator Ready
<>	156:95d6b41a828b	905	* @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady
<>	156:95d6b41a828b	906	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	907	*/
<>	156:95d6b41a828b	908	__STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void)
<>	156:95d6b41a828b	909	{
<>	156:95d6b41a828b	910	return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY));
<>	156:95d6b41a828b	911	}
<>	156:95d6b41a828b	912
<>	156:95d6b41a828b	913	/**
<>	156:95d6b41a828b	914	* @brief ADC interface can turn on the HSI14 oscillator
<>	156:95d6b41a828b	915	* @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl
<>	156:95d6b41a828b	916	* @retval None
<>	156:95d6b41a828b	917	*/
<>	156:95d6b41a828b	918	__STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void)
<>	156:95d6b41a828b	919	{
<>	156:95d6b41a828b	920	CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS);
<>	156:95d6b41a828b	921	}
<>	156:95d6b41a828b	922
<>	156:95d6b41a828b	923	/**
<>	156:95d6b41a828b	924	* @brief ADC interface can not turn on the HSI14 oscillator
<>	156:95d6b41a828b	925	* @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl
<>	156:95d6b41a828b	926	* @retval None
<>	156:95d6b41a828b	927	*/
<>	156:95d6b41a828b	928	__STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void)
<>	156:95d6b41a828b	929	{
<>	156:95d6b41a828b	930	SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS);
<>	156:95d6b41a828b	931	}
<>	156:95d6b41a828b	932
<>	156:95d6b41a828b	933	/**
<>	156:95d6b41a828b	934	* @brief Set HSI14 Calibration trimming
<>	156:95d6b41a828b	935	* @note user-programmable trimming value that is added to the HSI14CAL
<>	156:95d6b41a828b	936	* @note Default value is 16, which, when added to the HSI14CAL value,
<>	156:95d6b41a828b	937	* should trim the HSI14 to 14 MHz +/- 1 %
<>	156:95d6b41a828b	938	* @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming
<>	156:95d6b41a828b	939	* @param Value between Min_Data = 0x00 and Max_Data = 0xFF
<>	156:95d6b41a828b	940	* @retval None
<>	156:95d6b41a828b	941	*/
<>	156:95d6b41a828b	942	__STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value)
<>	156:95d6b41a828b	943	{
<>	156:95d6b41a828b	944	MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM);
<>	156:95d6b41a828b	945	}
<>	156:95d6b41a828b	946
<>	156:95d6b41a828b	947	/**
<>	156:95d6b41a828b	948	* @brief Get HSI14 Calibration value
<>	156:95d6b41a828b	949	* @note When HSI14TRIM is written, HSI14CAL is updated with the sum of
<>	156:95d6b41a828b	950	* HSI14TRIM and the factory trim value
<>	156:95d6b41a828b	951	* @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming
<>	156:95d6b41a828b	952	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
<>	156:95d6b41a828b	953	*/
<>	156:95d6b41a828b	954	__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void)
<>	156:95d6b41a828b	955	{
<>	156:95d6b41a828b	956	return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM);
<>	156:95d6b41a828b	957	}
<>	156:95d6b41a828b	958
<>	156:95d6b41a828b	959	/**
<>	156:95d6b41a828b	960	* @brief Get HSI14 Calibration trimming
<>	156:95d6b41a828b	961	* @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration
<>	156:95d6b41a828b	962	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
<>	156:95d6b41a828b	963	*/
<>	156:95d6b41a828b	964	__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void)
<>	156:95d6b41a828b	965	{
<>	156:95d6b41a828b	966	return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL);
<>	156:95d6b41a828b	967	}
<>	156:95d6b41a828b	968
<>	156:95d6b41a828b	969	/**
<>	156:95d6b41a828b	970	* @}
<>	156:95d6b41a828b	971	*/
<>	156:95d6b41a828b	972
<>	156:95d6b41a828b	973	/** @defgroup RCC_LL_EF_LSE LSE
<>	156:95d6b41a828b	974	* @{
<>	156:95d6b41a828b	975	*/
<>	156:95d6b41a828b	976
<>	156:95d6b41a828b	977	/**
<>	156:95d6b41a828b	978	* @brief Enable Low Speed External (LSE) crystal.
<>	156:95d6b41a828b	979	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
<>	156:95d6b41a828b	980	* @retval None
<>	156:95d6b41a828b	981	*/
<>	156:95d6b41a828b	982	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
<>	156:95d6b41a828b	983	{
<>	156:95d6b41a828b	984	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<>	156:95d6b41a828b	985	}
<>	156:95d6b41a828b	986
<>	156:95d6b41a828b	987	/**
<>	156:95d6b41a828b	988	* @brief Disable Low Speed External (LSE) crystal.
<>	156:95d6b41a828b	989	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
<>	156:95d6b41a828b	990	* @retval None
<>	156:95d6b41a828b	991	*/
<>	156:95d6b41a828b	992	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
<>	156:95d6b41a828b	993	{
<>	156:95d6b41a828b	994	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<>	156:95d6b41a828b	995	}
<>	156:95d6b41a828b	996
<>	156:95d6b41a828b	997	/**
<>	156:95d6b41a828b	998	* @brief Enable external clock source (LSE bypass).
<>	156:95d6b41a828b	999	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
<>	156:95d6b41a828b	1000	* @retval None
<>	156:95d6b41a828b	1001	*/
<>	156:95d6b41a828b	1002	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
<>	156:95d6b41a828b	1003	{
<>	156:95d6b41a828b	1004	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<>	156:95d6b41a828b	1005	}
<>	156:95d6b41a828b	1006
<>	156:95d6b41a828b	1007	/**
<>	156:95d6b41a828b	1008	* @brief Disable external clock source (LSE bypass).
<>	156:95d6b41a828b	1009	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
<>	156:95d6b41a828b	1010	* @retval None
<>	156:95d6b41a828b	1011	*/
<>	156:95d6b41a828b	1012	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
<>	156:95d6b41a828b	1013	{
<>	156:95d6b41a828b	1014	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<>	156:95d6b41a828b	1015	}
<>	156:95d6b41a828b	1016
<>	156:95d6b41a828b	1017	/**
<>	156:95d6b41a828b	1018	* @brief Set LSE oscillator drive capability
<>	156:95d6b41a828b	1019	* @note The oscillator is in Xtal mode when it is not in bypass mode.
<>	156:95d6b41a828b	1020	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
<>	156:95d6b41a828b	1021	* @param LSEDrive This parameter can be one of the following values:
<>	156:95d6b41a828b	1022	* @arg @ref LL_RCC_LSEDRIVE_LOW
<>	156:95d6b41a828b	1023	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
<>	156:95d6b41a828b	1024	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
<>	156:95d6b41a828b	1025	* @arg @ref LL_RCC_LSEDRIVE_HIGH
<>	156:95d6b41a828b	1026	* @retval None
<>	156:95d6b41a828b	1027	*/
<>	156:95d6b41a828b	1028	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
<>	156:95d6b41a828b	1029	{
<>	156:95d6b41a828b	1030	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
<>	156:95d6b41a828b	1031	}
<>	156:95d6b41a828b	1032
<>	156:95d6b41a828b	1033	/**
<>	156:95d6b41a828b	1034	* @brief Get LSE oscillator drive capability
<>	156:95d6b41a828b	1035	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
<>	156:95d6b41a828b	1036	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1037	* @arg @ref LL_RCC_LSEDRIVE_LOW
<>	156:95d6b41a828b	1038	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
<>	156:95d6b41a828b	1039	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
<>	156:95d6b41a828b	1040	* @arg @ref LL_RCC_LSEDRIVE_HIGH
<>	156:95d6b41a828b	1041	*/
<>	156:95d6b41a828b	1042	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
<>	156:95d6b41a828b	1043	{
<>	156:95d6b41a828b	1044	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
<>	156:95d6b41a828b	1045	}
<>	156:95d6b41a828b	1046
<>	156:95d6b41a828b	1047	/**
<>	156:95d6b41a828b	1048	* @brief Check if LSE oscillator Ready
<>	156:95d6b41a828b	1049	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
<>	156:95d6b41a828b	1050	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1051	*/
<>	156:95d6b41a828b	1052	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
<>	156:95d6b41a828b	1053	{
<>	156:95d6b41a828b	1054	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
<>	156:95d6b41a828b	1055	}
<>	156:95d6b41a828b	1056
<>	156:95d6b41a828b	1057	/**
<>	156:95d6b41a828b	1058	* @}
<>	156:95d6b41a828b	1059	*/
<>	156:95d6b41a828b	1060
<>	156:95d6b41a828b	1061	/** @defgroup RCC_LL_EF_LSI LSI
<>	156:95d6b41a828b	1062	* @{
<>	156:95d6b41a828b	1063	*/
<>	156:95d6b41a828b	1064
<>	156:95d6b41a828b	1065	/**
<>	156:95d6b41a828b	1066	* @brief Enable LSI Oscillator
<>	156:95d6b41a828b	1067	* @rmtoll CSR LSION LL_RCC_LSI_Enable
<>	156:95d6b41a828b	1068	* @retval None
<>	156:95d6b41a828b	1069	*/
<>	156:95d6b41a828b	1070	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
<>	156:95d6b41a828b	1071	{
<>	156:95d6b41a828b	1072	SET_BIT(RCC->CSR, RCC_CSR_LSION);
<>	156:95d6b41a828b	1073	}
<>	156:95d6b41a828b	1074
<>	156:95d6b41a828b	1075	/**
<>	156:95d6b41a828b	1076	* @brief Disable LSI Oscillator
<>	156:95d6b41a828b	1077	* @rmtoll CSR LSION LL_RCC_LSI_Disable
<>	156:95d6b41a828b	1078	* @retval None
<>	156:95d6b41a828b	1079	*/
<>	156:95d6b41a828b	1080	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
<>	156:95d6b41a828b	1081	{
<>	156:95d6b41a828b	1082	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
<>	156:95d6b41a828b	1083	}
<>	156:95d6b41a828b	1084
<>	156:95d6b41a828b	1085	/**
<>	156:95d6b41a828b	1086	* @brief Check if LSI is Ready
<>	156:95d6b41a828b	1087	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
<>	156:95d6b41a828b	1088	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1089	*/
<>	156:95d6b41a828b	1090	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
<>	156:95d6b41a828b	1091	{
<>	156:95d6b41a828b	1092	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
<>	156:95d6b41a828b	1093	}
<>	156:95d6b41a828b	1094
<>	156:95d6b41a828b	1095	/**
<>	156:95d6b41a828b	1096	* @}
<>	156:95d6b41a828b	1097	*/
<>	156:95d6b41a828b	1098
<>	156:95d6b41a828b	1099	/** @defgroup RCC_LL_EF_System System
<>	156:95d6b41a828b	1100	* @{
<>	156:95d6b41a828b	1101	*/
<>	156:95d6b41a828b	1102
<>	156:95d6b41a828b	1103	/**
<>	156:95d6b41a828b	1104	* @brief Configure the system clock source
<>	156:95d6b41a828b	1105	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
<>	156:95d6b41a828b	1106	* @param Source This parameter can be one of the following values:
<>	156:95d6b41a828b	1107	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
<>	156:95d6b41a828b	1108	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
<>	156:95d6b41a828b	1109	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
<>	156:95d6b41a828b	1110	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*)
<>	156:95d6b41a828b	1111	*
<>	156:95d6b41a828b	1112	* (*) value not defined in all devices
<>	156:95d6b41a828b	1113	* @retval None
<>	156:95d6b41a828b	1114	*/
<>	156:95d6b41a828b	1115	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
<>	156:95d6b41a828b	1116	{
<>	156:95d6b41a828b	1117	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
<>	156:95d6b41a828b	1118	}
<>	156:95d6b41a828b	1119
<>	156:95d6b41a828b	1120	/**
<>	156:95d6b41a828b	1121	* @brief Get the system clock source
<>	156:95d6b41a828b	1122	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
<>	156:95d6b41a828b	1123	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1124	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
<>	156:95d6b41a828b	1125	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
<>	156:95d6b41a828b	1126	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
<>	156:95d6b41a828b	1127	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*)
<>	156:95d6b41a828b	1128	*
<>	156:95d6b41a828b	1129	* (*) value not defined in all devices
<>	156:95d6b41a828b	1130	*/
<>	156:95d6b41a828b	1131	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
<>	156:95d6b41a828b	1132	{
<>	156:95d6b41a828b	1133	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
<>	156:95d6b41a828b	1134	}
<>	156:95d6b41a828b	1135
<>	156:95d6b41a828b	1136	/**
<>	156:95d6b41a828b	1137	* @brief Set AHB prescaler
<>	156:95d6b41a828b	1138	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
<>	156:95d6b41a828b	1139	* @param Prescaler This parameter can be one of the following values:
<>	156:95d6b41a828b	1140	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	156:95d6b41a828b	1141	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	156:95d6b41a828b	1142	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	156:95d6b41a828b	1143	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	156:95d6b41a828b	1144	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	156:95d6b41a828b	1145	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	156:95d6b41a828b	1146	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	156:95d6b41a828b	1147	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	156:95d6b41a828b	1148	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	156:95d6b41a828b	1149	* @retval None
<>	156:95d6b41a828b	1150	*/
<>	156:95d6b41a828b	1151	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
<>	156:95d6b41a828b	1152	{
<>	156:95d6b41a828b	1153	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
<>	156:95d6b41a828b	1154	}
<>	156:95d6b41a828b	1155
<>	156:95d6b41a828b	1156	/**
<>	156:95d6b41a828b	1157	* @brief Set APB1 prescaler
<>	156:95d6b41a828b	1158	* @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler
<>	156:95d6b41a828b	1159	* @param Prescaler This parameter can be one of the following values:
<>	156:95d6b41a828b	1160	* @arg @ref LL_RCC_APB1_DIV_1
<>	156:95d6b41a828b	1161	* @arg @ref LL_RCC_APB1_DIV_2
<>	156:95d6b41a828b	1162	* @arg @ref LL_RCC_APB1_DIV_4
<>	156:95d6b41a828b	1163	* @arg @ref LL_RCC_APB1_DIV_8
<>	156:95d6b41a828b	1164	* @arg @ref LL_RCC_APB1_DIV_16
<>	156:95d6b41a828b	1165	* @retval None
<>	156:95d6b41a828b	1166	*/
<>	156:95d6b41a828b	1167	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
<>	156:95d6b41a828b	1168	{
<>	156:95d6b41a828b	1169	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
<>	156:95d6b41a828b	1170	}
<>	156:95d6b41a828b	1171
<>	156:95d6b41a828b	1172	/**
<>	156:95d6b41a828b	1173	* @brief Get AHB prescaler
<>	156:95d6b41a828b	1174	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
<>	156:95d6b41a828b	1175	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1176	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	156:95d6b41a828b	1177	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	156:95d6b41a828b	1178	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	156:95d6b41a828b	1179	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	156:95d6b41a828b	1180	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	156:95d6b41a828b	1181	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	156:95d6b41a828b	1182	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	156:95d6b41a828b	1183	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	156:95d6b41a828b	1184	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	156:95d6b41a828b	1185	*/
<>	156:95d6b41a828b	1186	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
<>	156:95d6b41a828b	1187	{
<>	156:95d6b41a828b	1188	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
<>	156:95d6b41a828b	1189	}
<>	156:95d6b41a828b	1190
<>	156:95d6b41a828b	1191	/**
<>	156:95d6b41a828b	1192	* @brief Get APB1 prescaler
<>	156:95d6b41a828b	1193	* @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler
<>	156:95d6b41a828b	1194	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1195	* @arg @ref LL_RCC_APB1_DIV_1
<>	156:95d6b41a828b	1196	* @arg @ref LL_RCC_APB1_DIV_2
<>	156:95d6b41a828b	1197	* @arg @ref LL_RCC_APB1_DIV_4
<>	156:95d6b41a828b	1198	* @arg @ref LL_RCC_APB1_DIV_8
<>	156:95d6b41a828b	1199	* @arg @ref LL_RCC_APB1_DIV_16
<>	156:95d6b41a828b	1200	*/
<>	156:95d6b41a828b	1201	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
<>	156:95d6b41a828b	1202	{
<>	156:95d6b41a828b	1203	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
<>	156:95d6b41a828b	1204	}
<>	156:95d6b41a828b	1205
<>	156:95d6b41a828b	1206	/**
<>	156:95d6b41a828b	1207	* @}
<>	156:95d6b41a828b	1208	*/
<>	156:95d6b41a828b	1209
<>	156:95d6b41a828b	1210	/** @defgroup RCC_LL_EF_MCO MCO
<>	156:95d6b41a828b	1211	* @{
<>	156:95d6b41a828b	1212	*/
<>	156:95d6b41a828b	1213
<>	156:95d6b41a828b	1214	/**
<>	156:95d6b41a828b	1215	* @brief Configure MCOx
<>	156:95d6b41a828b	1216	* @rmtoll CFGR MCO LL_RCC_ConfigMCO\n
<>	156:95d6b41a828b	1217	* CFGR MCOPRE LL_RCC_ConfigMCO\n
<>	156:95d6b41a828b	1218	* CFGR PLLNODIV LL_RCC_ConfigMCO
<>	156:95d6b41a828b	1219	* @param MCOxSource This parameter can be one of the following values:
<>	156:95d6b41a828b	1220	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
<>	156:95d6b41a828b	1221	* @arg @ref LL_RCC_MCO1SOURCE_HSI14
<>	156:95d6b41a828b	1222	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
<>	156:95d6b41a828b	1223	* @arg @ref LL_RCC_MCO1SOURCE_HSI
<>	156:95d6b41a828b	1224	* @arg @ref LL_RCC_MCO1SOURCE_HSE
<>	156:95d6b41a828b	1225	* @arg @ref LL_RCC_MCO1SOURCE_LSI
<>	156:95d6b41a828b	1226	* @arg @ref LL_RCC_MCO1SOURCE_LSE
<>	156:95d6b41a828b	1227	* @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
<>	156:95d6b41a828b	1228	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*)
<>	156:95d6b41a828b	1229	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
<>	156:95d6b41a828b	1230	*
<>	156:95d6b41a828b	1231	* (*) value not defined in all devices
<>	156:95d6b41a828b	1232	* @param MCOxPrescaler This parameter can be one of the following values:
<>	156:95d6b41a828b	1233	* @arg @ref LL_RCC_MCO1_DIV_1
<>	156:95d6b41a828b	1234	* @arg @ref LL_RCC_MCO1_DIV_2 (*)
<>	156:95d6b41a828b	1235	* @arg @ref LL_RCC_MCO1_DIV_4 (*)
<>	156:95d6b41a828b	1236	* @arg @ref LL_RCC_MCO1_DIV_8 (*)
<>	156:95d6b41a828b	1237	* @arg @ref LL_RCC_MCO1_DIV_16 (*)
<>	156:95d6b41a828b	1238	* @arg @ref LL_RCC_MCO1_DIV_32 (*)
<>	156:95d6b41a828b	1239	* @arg @ref LL_RCC_MCO1_DIV_64 (*)
<>	156:95d6b41a828b	1240	* @arg @ref LL_RCC_MCO1_DIV_128 (*)
<>	156:95d6b41a828b	1241	*
<>	156:95d6b41a828b	1242	* (*) value not defined in all devices
<>	156:95d6b41a828b	1243	* @retval None
<>	156:95d6b41a828b	1244	*/
<>	156:95d6b41a828b	1245	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
<>	156:95d6b41a828b	1246	{
<>	156:95d6b41a828b	1247	#if defined(RCC_CFGR_MCOPRE)
<>	156:95d6b41a828b	1248	#if defined(RCC_CFGR_PLLNODIV)
<>	156:95d6b41a828b	1249	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE \| RCC_CFGR_PLLNODIV, MCOxSource \| MCOxPrescaler);
<>	156:95d6b41a828b	1250	#else
<>	156:95d6b41a828b	1251	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE, MCOxSource \| MCOxPrescaler);
<>	156:95d6b41a828b	1252	#endif /* RCC_CFGR_PLLNODIV */
<>	156:95d6b41a828b	1253	#else
<>	156:95d6b41a828b	1254	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
<>	156:95d6b41a828b	1255	#endif /* RCC_CFGR_MCOPRE */
<>	156:95d6b41a828b	1256	}
<>	156:95d6b41a828b	1257
<>	156:95d6b41a828b	1258	/**
<>	156:95d6b41a828b	1259	* @}
<>	156:95d6b41a828b	1260	*/
<>	156:95d6b41a828b	1261
<>	156:95d6b41a828b	1262	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
<>	156:95d6b41a828b	1263	* @{
<>	156:95d6b41a828b	1264	*/
<>	156:95d6b41a828b	1265
<>	156:95d6b41a828b	1266	/**
<>	156:95d6b41a828b	1267	* @brief Configure USARTx clock source
<>	156:95d6b41a828b	1268	* @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n
<>	156:95d6b41a828b	1269	* CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n
<>	156:95d6b41a828b	1270	* CFGR3 USART3SW LL_RCC_SetUSARTClockSource
<>	156:95d6b41a828b	1271	* @param USARTxSource This parameter can be one of the following values:
<>	156:95d6b41a828b	1272	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
<>	156:95d6b41a828b	1273	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
<>	156:95d6b41a828b	1274	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
<>	156:95d6b41a828b	1275	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
<>	156:95d6b41a828b	1276	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
<>	156:95d6b41a828b	1277	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
<>	156:95d6b41a828b	1278	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
<>	156:95d6b41a828b	1279	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
<>	156:95d6b41a828b	1280	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
<>	156:95d6b41a828b	1281	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
<>	156:95d6b41a828b	1282	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
<>	156:95d6b41a828b	1283	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
<>	156:95d6b41a828b	1284	*
<>	156:95d6b41a828b	1285	* (*) value not defined in all devices.
<>	156:95d6b41a828b	1286	* @retval None
<>	156:95d6b41a828b	1287	*/
<>	156:95d6b41a828b	1288	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
<>	156:95d6b41a828b	1289	{
<>	156:95d6b41a828b	1290	MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
<>	156:95d6b41a828b	1291	}
<>	156:95d6b41a828b	1292
<>	156:95d6b41a828b	1293	/**
<>	156:95d6b41a828b	1294	* @brief Configure I2Cx clock source
<>	156:95d6b41a828b	1295	* @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource
<>	156:95d6b41a828b	1296	* @param I2CxSource This parameter can be one of the following values:
<>	156:95d6b41a828b	1297	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
<>	156:95d6b41a828b	1298	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
<>	156:95d6b41a828b	1299	* @retval None
<>	156:95d6b41a828b	1300	*/
<>	156:95d6b41a828b	1301	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
<>	156:95d6b41a828b	1302	{
<>	156:95d6b41a828b	1303	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource);
<>	156:95d6b41a828b	1304	}
<>	156:95d6b41a828b	1305
<>	156:95d6b41a828b	1306	#if defined(CEC)
<>	156:95d6b41a828b	1307	/**
<>	156:95d6b41a828b	1308	* @brief Configure CEC clock source
<>	156:95d6b41a828b	1309	* @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource
<>	156:95d6b41a828b	1310	* @param CECxSource This parameter can be one of the following values:
<>	156:95d6b41a828b	1311	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
<>	156:95d6b41a828b	1312	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
<>	156:95d6b41a828b	1313	* @retval None
<>	156:95d6b41a828b	1314	*/
<>	156:95d6b41a828b	1315	__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
<>	156:95d6b41a828b	1316	{
<>	156:95d6b41a828b	1317	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
<>	156:95d6b41a828b	1318	}
<>	156:95d6b41a828b	1319	#endif /* CEC */
<>	156:95d6b41a828b	1320
<>	156:95d6b41a828b	1321	#if defined(USB)
<>	156:95d6b41a828b	1322	/**
<>	156:95d6b41a828b	1323	* @brief Configure USB clock source
<>	156:95d6b41a828b	1324	* @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource
<>	156:95d6b41a828b	1325	* @param USBxSource This parameter can be one of the following values:
<>	156:95d6b41a828b	1326	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
<>	156:95d6b41a828b	1327	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
<>	156:95d6b41a828b	1328	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
<>	156:95d6b41a828b	1329	*
<>	156:95d6b41a828b	1330	* (*) value not defined in all devices.
<>	156:95d6b41a828b	1331	* @retval None
<>	156:95d6b41a828b	1332	*/
<>	156:95d6b41a828b	1333	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
<>	156:95d6b41a828b	1334	{
<>	156:95d6b41a828b	1335	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource);
<>	156:95d6b41a828b	1336	}
<>	156:95d6b41a828b	1337	#endif /* USB */
<>	156:95d6b41a828b	1338
<>	156:95d6b41a828b	1339	/**
<>	156:95d6b41a828b	1340	* @brief Get USARTx clock source
<>	156:95d6b41a828b	1341	* @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n
<>	156:95d6b41a828b	1342	* CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n
<>	156:95d6b41a828b	1343	* CFGR3 USART3SW LL_RCC_GetUSARTClockSource
<>	156:95d6b41a828b	1344	* @param USARTx This parameter can be one of the following values:
<>	156:95d6b41a828b	1345	* @arg @ref LL_RCC_USART1_CLKSOURCE
<>	156:95d6b41a828b	1346	* @arg @ref LL_RCC_USART2_CLKSOURCE (*)
<>	156:95d6b41a828b	1347	* @arg @ref LL_RCC_USART3_CLKSOURCE (*)
<>	156:95d6b41a828b	1348	*
<>	156:95d6b41a828b	1349	* (*) value not defined in all devices.
<>	156:95d6b41a828b	1350	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1351	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
<>	156:95d6b41a828b	1352	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
<>	156:95d6b41a828b	1353	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
<>	156:95d6b41a828b	1354	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
<>	156:95d6b41a828b	1355	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
<>	156:95d6b41a828b	1356	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
<>	156:95d6b41a828b	1357	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
<>	156:95d6b41a828b	1358	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
<>	156:95d6b41a828b	1359	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
<>	156:95d6b41a828b	1360	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
<>	156:95d6b41a828b	1361	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
<>	156:95d6b41a828b	1362	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
<>	156:95d6b41a828b	1363	*
<>	156:95d6b41a828b	1364	* (*) value not defined in all devices.
<>	156:95d6b41a828b	1365	*/
<>	156:95d6b41a828b	1366	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
<>	156:95d6b41a828b	1367	{
<>	156:95d6b41a828b	1368	return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) \| (USARTx << 24U));
<>	156:95d6b41a828b	1369	}
<>	156:95d6b41a828b	1370
<>	156:95d6b41a828b	1371	/**
<>	156:95d6b41a828b	1372	* @brief Get I2Cx clock source
<>	156:95d6b41a828b	1373	* @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource
<>	156:95d6b41a828b	1374	* @param I2Cx This parameter can be one of the following values:
<>	156:95d6b41a828b	1375	* @arg @ref LL_RCC_I2C1_CLKSOURCE
<>	156:95d6b41a828b	1376	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1377	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
<>	156:95d6b41a828b	1378	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
<>	156:95d6b41a828b	1379	*/
<>	156:95d6b41a828b	1380	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
<>	156:95d6b41a828b	1381	{
<>	156:95d6b41a828b	1382	return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx));
<>	156:95d6b41a828b	1383	}
<>	156:95d6b41a828b	1384
<>	156:95d6b41a828b	1385	#if defined(CEC)
<>	156:95d6b41a828b	1386	/**
<>	156:95d6b41a828b	1387	* @brief Get CEC clock source
<>	156:95d6b41a828b	1388	* @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource
<>	156:95d6b41a828b	1389	* @param CECx This parameter can be one of the following values:
<>	156:95d6b41a828b	1390	* @arg @ref LL_RCC_CEC_CLKSOURCE
<>	156:95d6b41a828b	1391	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1392	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
<>	156:95d6b41a828b	1393	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
<>	156:95d6b41a828b	1394	*/
<>	156:95d6b41a828b	1395	__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
<>	156:95d6b41a828b	1396	{
<>	156:95d6b41a828b	1397	return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
<>	156:95d6b41a828b	1398	}
<>	156:95d6b41a828b	1399	#endif /* CEC */
<>	156:95d6b41a828b	1400
<>	156:95d6b41a828b	1401	#if defined(USB)
<>	156:95d6b41a828b	1402	/**
<>	156:95d6b41a828b	1403	* @brief Get USBx clock source
<>	156:95d6b41a828b	1404	* @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource
<>	156:95d6b41a828b	1405	* @param USBx This parameter can be one of the following values:
<>	156:95d6b41a828b	1406	* @arg @ref LL_RCC_USB_CLKSOURCE
<>	156:95d6b41a828b	1407	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1408	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
<>	156:95d6b41a828b	1409	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
<>	156:95d6b41a828b	1410	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
<>	156:95d6b41a828b	1411	*
<>	156:95d6b41a828b	1412	* (*) value not defined in all devices.
<>	156:95d6b41a828b	1413	*/
<>	156:95d6b41a828b	1414	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
<>	156:95d6b41a828b	1415	{
<>	156:95d6b41a828b	1416	return (uint32_t)(READ_BIT(RCC->CFGR3, USBx));
<>	156:95d6b41a828b	1417	}
<>	156:95d6b41a828b	1418	#endif /* USB */
<>	156:95d6b41a828b	1419
<>	156:95d6b41a828b	1420	/**
<>	156:95d6b41a828b	1421	* @}
<>	156:95d6b41a828b	1422	*/
<>	156:95d6b41a828b	1423
<>	156:95d6b41a828b	1424	/** @defgroup RCC_LL_EF_RTC RTC
<>	156:95d6b41a828b	1425	* @{
<>	156:95d6b41a828b	1426	*/
<>	156:95d6b41a828b	1427
<>	156:95d6b41a828b	1428	/**
<>	156:95d6b41a828b	1429	* @brief Set RTC Clock Source
<>	156:95d6b41a828b	1430	* @note Once the RTC clock source has been selected, it cannot be changed any more unless
<>	156:95d6b41a828b	1431	* the Backup domain is reset. The BDRST bit can be used to reset them.
<>	156:95d6b41a828b	1432	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
<>	156:95d6b41a828b	1433	* @param Source This parameter can be one of the following values:
<>	156:95d6b41a828b	1434	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<>	156:95d6b41a828b	1435	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<>	156:95d6b41a828b	1436	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<>	156:95d6b41a828b	1437	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
<>	156:95d6b41a828b	1438	* @retval None
<>	156:95d6b41a828b	1439	*/
<>	156:95d6b41a828b	1440	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
<>	156:95d6b41a828b	1441	{
<>	156:95d6b41a828b	1442	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
<>	156:95d6b41a828b	1443	}
<>	156:95d6b41a828b	1444
<>	156:95d6b41a828b	1445	/**
<>	156:95d6b41a828b	1446	* @brief Get RTC Clock Source
<>	156:95d6b41a828b	1447	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
<>	156:95d6b41a828b	1448	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1449	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<>	156:95d6b41a828b	1450	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<>	156:95d6b41a828b	1451	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<>	156:95d6b41a828b	1452	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
<>	156:95d6b41a828b	1453	*/
<>	156:95d6b41a828b	1454	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
<>	156:95d6b41a828b	1455	{
<>	156:95d6b41a828b	1456	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
<>	156:95d6b41a828b	1457	}
<>	156:95d6b41a828b	1458
<>	156:95d6b41a828b	1459	/**
<>	156:95d6b41a828b	1460	* @brief Enable RTC
<>	156:95d6b41a828b	1461	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
<>	156:95d6b41a828b	1462	* @retval None
<>	156:95d6b41a828b	1463	*/
<>	156:95d6b41a828b	1464	__STATIC_INLINE void LL_RCC_EnableRTC(void)
<>	156:95d6b41a828b	1465	{
<>	156:95d6b41a828b	1466	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<>	156:95d6b41a828b	1467	}
<>	156:95d6b41a828b	1468
<>	156:95d6b41a828b	1469	/**
<>	156:95d6b41a828b	1470	* @brief Disable RTC
<>	156:95d6b41a828b	1471	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
<>	156:95d6b41a828b	1472	* @retval None
<>	156:95d6b41a828b	1473	*/
<>	156:95d6b41a828b	1474	__STATIC_INLINE void LL_RCC_DisableRTC(void)
<>	156:95d6b41a828b	1475	{
<>	156:95d6b41a828b	1476	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<>	156:95d6b41a828b	1477	}
<>	156:95d6b41a828b	1478
<>	156:95d6b41a828b	1479	/**
<>	156:95d6b41a828b	1480	* @brief Check if RTC has been enabled or not
<>	156:95d6b41a828b	1481	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
<>	156:95d6b41a828b	1482	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1483	*/
<>	156:95d6b41a828b	1484	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
<>	156:95d6b41a828b	1485	{
<>	156:95d6b41a828b	1486	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
<>	156:95d6b41a828b	1487	}
<>	156:95d6b41a828b	1488
<>	156:95d6b41a828b	1489	/**
<>	156:95d6b41a828b	1490	* @brief Force the Backup domain reset
<>	156:95d6b41a828b	1491	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
<>	156:95d6b41a828b	1492	* @retval None
<>	156:95d6b41a828b	1493	*/
<>	156:95d6b41a828b	1494	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
<>	156:95d6b41a828b	1495	{
<>	156:95d6b41a828b	1496	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<>	156:95d6b41a828b	1497	}
<>	156:95d6b41a828b	1498
<>	156:95d6b41a828b	1499	/**
<>	156:95d6b41a828b	1500	* @brief Release the Backup domain reset
<>	156:95d6b41a828b	1501	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
<>	156:95d6b41a828b	1502	* @retval None
<>	156:95d6b41a828b	1503	*/
<>	156:95d6b41a828b	1504	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
<>	156:95d6b41a828b	1505	{
<>	156:95d6b41a828b	1506	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<>	156:95d6b41a828b	1507	}
<>	156:95d6b41a828b	1508
<>	156:95d6b41a828b	1509	/**
<>	156:95d6b41a828b	1510	* @}
<>	156:95d6b41a828b	1511	*/
<>	156:95d6b41a828b	1512
<>	156:95d6b41a828b	1513	/** @defgroup RCC_LL_EF_PLL PLL
<>	156:95d6b41a828b	1514	* @{
<>	156:95d6b41a828b	1515	*/
<>	156:95d6b41a828b	1516
<>	156:95d6b41a828b	1517	/**
<>	156:95d6b41a828b	1518	* @brief Enable PLL
<>	156:95d6b41a828b	1519	* @rmtoll CR PLLON LL_RCC_PLL_Enable
<>	156:95d6b41a828b	1520	* @retval None
<>	156:95d6b41a828b	1521	*/
<>	156:95d6b41a828b	1522	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
<>	156:95d6b41a828b	1523	{
<>	156:95d6b41a828b	1524	SET_BIT(RCC->CR, RCC_CR_PLLON);
<>	156:95d6b41a828b	1525	}
<>	156:95d6b41a828b	1526
<>	156:95d6b41a828b	1527	/**
<>	156:95d6b41a828b	1528	* @brief Disable PLL
<>	156:95d6b41a828b	1529	* @note Cannot be disabled if the PLL clock is used as the system clock
<>	156:95d6b41a828b	1530	* @rmtoll CR PLLON LL_RCC_PLL_Disable
<>	156:95d6b41a828b	1531	* @retval None
<>	156:95d6b41a828b	1532	*/
<>	156:95d6b41a828b	1533	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
<>	156:95d6b41a828b	1534	{
<>	156:95d6b41a828b	1535	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
<>	156:95d6b41a828b	1536	}
<>	156:95d6b41a828b	1537
<>	156:95d6b41a828b	1538	/**
<>	156:95d6b41a828b	1539	* @brief Check if PLL Ready
<>	156:95d6b41a828b	1540	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
<>	156:95d6b41a828b	1541	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1542	*/
<>	156:95d6b41a828b	1543	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
<>	156:95d6b41a828b	1544	{
<>	156:95d6b41a828b	1545	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
<>	156:95d6b41a828b	1546	}
<>	156:95d6b41a828b	1547
<>	156:95d6b41a828b	1548	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<>	156:95d6b41a828b	1549	/**
<>	156:95d6b41a828b	1550	* @brief Configure PLL used for SYSCLK Domain
<>	156:95d6b41a828b	1551	* @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
<>	156:95d6b41a828b	1552	* CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
<>	156:95d6b41a828b	1553	* CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
<>	156:95d6b41a828b	1554	* @param Source This parameter can be one of the following values:
<>	156:95d6b41a828b	1555	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	156:95d6b41a828b	1556	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	156:95d6b41a828b	1557	* @arg @ref LL_RCC_PLLSOURCE_HSI48 (*)
<>	156:95d6b41a828b	1558	*
<>	156:95d6b41a828b	1559	* (*) value not defined in all devices
<>	156:95d6b41a828b	1560	* @param PLLMul This parameter can be one of the following values:
<>	156:95d6b41a828b	1561	* @arg @ref LL_RCC_PLL_MUL_2
<>	156:95d6b41a828b	1562	* @arg @ref LL_RCC_PLL_MUL_3
<>	156:95d6b41a828b	1563	* @arg @ref LL_RCC_PLL_MUL_4
<>	156:95d6b41a828b	1564	* @arg @ref LL_RCC_PLL_MUL_5
<>	156:95d6b41a828b	1565	* @arg @ref LL_RCC_PLL_MUL_6
<>	156:95d6b41a828b	1566	* @arg @ref LL_RCC_PLL_MUL_7
<>	156:95d6b41a828b	1567	* @arg @ref LL_RCC_PLL_MUL_8
<>	156:95d6b41a828b	1568	* @arg @ref LL_RCC_PLL_MUL_9
<>	156:95d6b41a828b	1569	* @arg @ref LL_RCC_PLL_MUL_10
<>	156:95d6b41a828b	1570	* @arg @ref LL_RCC_PLL_MUL_11
<>	156:95d6b41a828b	1571	* @arg @ref LL_RCC_PLL_MUL_12
<>	156:95d6b41a828b	1572	* @arg @ref LL_RCC_PLL_MUL_13
<>	156:95d6b41a828b	1573	* @arg @ref LL_RCC_PLL_MUL_14
<>	156:95d6b41a828b	1574	* @arg @ref LL_RCC_PLL_MUL_15
<>	156:95d6b41a828b	1575	* @arg @ref LL_RCC_PLL_MUL_16
<>	156:95d6b41a828b	1576	* @param PLLDiv This parameter can be one of the following values:
<>	156:95d6b41a828b	1577	* @arg @ref LL_RCC_PREDIV_DIV_1
<>	156:95d6b41a828b	1578	* @arg @ref LL_RCC_PREDIV_DIV_2
<>	156:95d6b41a828b	1579	* @arg @ref LL_RCC_PREDIV_DIV_3
<>	156:95d6b41a828b	1580	* @arg @ref LL_RCC_PREDIV_DIV_4
<>	156:95d6b41a828b	1581	* @arg @ref LL_RCC_PREDIV_DIV_5
<>	156:95d6b41a828b	1582	* @arg @ref LL_RCC_PREDIV_DIV_6
<>	156:95d6b41a828b	1583	* @arg @ref LL_RCC_PREDIV_DIV_7
<>	156:95d6b41a828b	1584	* @arg @ref LL_RCC_PREDIV_DIV_8
<>	156:95d6b41a828b	1585	* @arg @ref LL_RCC_PREDIV_DIV_9
<>	156:95d6b41a828b	1586	* @arg @ref LL_RCC_PREDIV_DIV_10
<>	156:95d6b41a828b	1587	* @arg @ref LL_RCC_PREDIV_DIV_11
<>	156:95d6b41a828b	1588	* @arg @ref LL_RCC_PREDIV_DIV_12
<>	156:95d6b41a828b	1589	* @arg @ref LL_RCC_PREDIV_DIV_13
<>	156:95d6b41a828b	1590	* @arg @ref LL_RCC_PREDIV_DIV_14
<>	156:95d6b41a828b	1591	* @arg @ref LL_RCC_PREDIV_DIV_15
<>	156:95d6b41a828b	1592	* @arg @ref LL_RCC_PREDIV_DIV_16
<>	156:95d6b41a828b	1593	* @retval None
<>	156:95d6b41a828b	1594	*/
<>	156:95d6b41a828b	1595	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
<>	156:95d6b41a828b	1596	{
<>	156:95d6b41a828b	1597	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMUL, Source \| PLLMul);
<>	156:95d6b41a828b	1598	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
<>	156:95d6b41a828b	1599	}
<>	156:95d6b41a828b	1600
<>	156:95d6b41a828b	1601	#else
<>	156:95d6b41a828b	1602
<>	156:95d6b41a828b	1603	/**
<>	156:95d6b41a828b	1604	* @brief Configure PLL used for SYSCLK Domain
<>	156:95d6b41a828b	1605	* @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
<>	156:95d6b41a828b	1606	* CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
<>	156:95d6b41a828b	1607	* CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
<>	156:95d6b41a828b	1608	* @param Source This parameter can be one of the following values:
<>	156:95d6b41a828b	1609	* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
<>	156:95d6b41a828b	1610	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
<>	156:95d6b41a828b	1611	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2
<>	156:95d6b41a828b	1612	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3
<>	156:95d6b41a828b	1613	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4
<>	156:95d6b41a828b	1614	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5
<>	156:95d6b41a828b	1615	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6
<>	156:95d6b41a828b	1616	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7
<>	156:95d6b41a828b	1617	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8
<>	156:95d6b41a828b	1618	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9
<>	156:95d6b41a828b	1619	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10
<>	156:95d6b41a828b	1620	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11
<>	156:95d6b41a828b	1621	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12
<>	156:95d6b41a828b	1622	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13
<>	156:95d6b41a828b	1623	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14
<>	156:95d6b41a828b	1624	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15
<>	156:95d6b41a828b	1625	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16
<>	156:95d6b41a828b	1626	* @param PLLMul This parameter can be one of the following values:
<>	156:95d6b41a828b	1627	* @arg @ref LL_RCC_PLL_MUL_2
<>	156:95d6b41a828b	1628	* @arg @ref LL_RCC_PLL_MUL_3
<>	156:95d6b41a828b	1629	* @arg @ref LL_RCC_PLL_MUL_4
<>	156:95d6b41a828b	1630	* @arg @ref LL_RCC_PLL_MUL_5
<>	156:95d6b41a828b	1631	* @arg @ref LL_RCC_PLL_MUL_6
<>	156:95d6b41a828b	1632	* @arg @ref LL_RCC_PLL_MUL_7
<>	156:95d6b41a828b	1633	* @arg @ref LL_RCC_PLL_MUL_8
<>	156:95d6b41a828b	1634	* @arg @ref LL_RCC_PLL_MUL_9
<>	156:95d6b41a828b	1635	* @arg @ref LL_RCC_PLL_MUL_10
<>	156:95d6b41a828b	1636	* @arg @ref LL_RCC_PLL_MUL_11
<>	156:95d6b41a828b	1637	* @arg @ref LL_RCC_PLL_MUL_12
<>	156:95d6b41a828b	1638	* @arg @ref LL_RCC_PLL_MUL_13
<>	156:95d6b41a828b	1639	* @arg @ref LL_RCC_PLL_MUL_14
<>	156:95d6b41a828b	1640	* @arg @ref LL_RCC_PLL_MUL_15
<>	156:95d6b41a828b	1641	* @arg @ref LL_RCC_PLL_MUL_16
<>	156:95d6b41a828b	1642	* @retval None
<>	156:95d6b41a828b	1643	*/
<>	156:95d6b41a828b	1644	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
<>	156:95d6b41a828b	1645	{
<>	156:95d6b41a828b	1646	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) \| PLLMul);
<>	156:95d6b41a828b	1647	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
<>	156:95d6b41a828b	1648	}
<>	156:95d6b41a828b	1649	#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<>	156:95d6b41a828b	1650
<>	156:95d6b41a828b	1651	/**
<>	156:95d6b41a828b	1652	* @brief Get the oscillator used as PLL clock source.
<>	156:95d6b41a828b	1653	* @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
<>	156:95d6b41a828b	1654	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1655	* @arg @ref LL_RCC_PLLSOURCE_HSI (*)
<>	156:95d6b41a828b	1656	* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
<>	156:95d6b41a828b	1657	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	156:95d6b41a828b	1658	* @arg @ref LL_RCC_PLLSOURCE_HSI48 (*)
<>	156:95d6b41a828b	1659	*
<>	156:95d6b41a828b	1660	* (*) value not defined in all devices
<>	156:95d6b41a828b	1661	*/
<>	156:95d6b41a828b	1662	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
<>	156:95d6b41a828b	1663	{
<>	156:95d6b41a828b	1664	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
<>	156:95d6b41a828b	1665	}
<>	156:95d6b41a828b	1666
<>	156:95d6b41a828b	1667	/**
<>	156:95d6b41a828b	1668	* @brief Get PLL multiplication Factor
<>	156:95d6b41a828b	1669	* @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
<>	156:95d6b41a828b	1670	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1671	* @arg @ref LL_RCC_PLL_MUL_2
<>	156:95d6b41a828b	1672	* @arg @ref LL_RCC_PLL_MUL_3
<>	156:95d6b41a828b	1673	* @arg @ref LL_RCC_PLL_MUL_4
<>	156:95d6b41a828b	1674	* @arg @ref LL_RCC_PLL_MUL_5
<>	156:95d6b41a828b	1675	* @arg @ref LL_RCC_PLL_MUL_6
<>	156:95d6b41a828b	1676	* @arg @ref LL_RCC_PLL_MUL_7
<>	156:95d6b41a828b	1677	* @arg @ref LL_RCC_PLL_MUL_8
<>	156:95d6b41a828b	1678	* @arg @ref LL_RCC_PLL_MUL_9
<>	156:95d6b41a828b	1679	* @arg @ref LL_RCC_PLL_MUL_10
<>	156:95d6b41a828b	1680	* @arg @ref LL_RCC_PLL_MUL_11
<>	156:95d6b41a828b	1681	* @arg @ref LL_RCC_PLL_MUL_12
<>	156:95d6b41a828b	1682	* @arg @ref LL_RCC_PLL_MUL_13
<>	156:95d6b41a828b	1683	* @arg @ref LL_RCC_PLL_MUL_14
<>	156:95d6b41a828b	1684	* @arg @ref LL_RCC_PLL_MUL_15
<>	156:95d6b41a828b	1685	* @arg @ref LL_RCC_PLL_MUL_16
<>	156:95d6b41a828b	1686	*/
<>	156:95d6b41a828b	1687	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
<>	156:95d6b41a828b	1688	{
<>	156:95d6b41a828b	1689	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
<>	156:95d6b41a828b	1690	}
<>	156:95d6b41a828b	1691
<>	156:95d6b41a828b	1692	/**
<>	156:95d6b41a828b	1693	* @brief Get PREDIV division factor for the main PLL
<>	156:95d6b41a828b	1694	* @note They can be written only when the PLL is disabled
<>	156:95d6b41a828b	1695	* @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv
<>	156:95d6b41a828b	1696	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1697	* @arg @ref LL_RCC_PREDIV_DIV_1
<>	156:95d6b41a828b	1698	* @arg @ref LL_RCC_PREDIV_DIV_2
<>	156:95d6b41a828b	1699	* @arg @ref LL_RCC_PREDIV_DIV_3
<>	156:95d6b41a828b	1700	* @arg @ref LL_RCC_PREDIV_DIV_4
<>	156:95d6b41a828b	1701	* @arg @ref LL_RCC_PREDIV_DIV_5
<>	156:95d6b41a828b	1702	* @arg @ref LL_RCC_PREDIV_DIV_6
<>	156:95d6b41a828b	1703	* @arg @ref LL_RCC_PREDIV_DIV_7
<>	156:95d6b41a828b	1704	* @arg @ref LL_RCC_PREDIV_DIV_8
<>	156:95d6b41a828b	1705	* @arg @ref LL_RCC_PREDIV_DIV_9
<>	156:95d6b41a828b	1706	* @arg @ref LL_RCC_PREDIV_DIV_10
<>	156:95d6b41a828b	1707	* @arg @ref LL_RCC_PREDIV_DIV_11
<>	156:95d6b41a828b	1708	* @arg @ref LL_RCC_PREDIV_DIV_12
<>	156:95d6b41a828b	1709	* @arg @ref LL_RCC_PREDIV_DIV_13
<>	156:95d6b41a828b	1710	* @arg @ref LL_RCC_PREDIV_DIV_14
<>	156:95d6b41a828b	1711	* @arg @ref LL_RCC_PREDIV_DIV_15
<>	156:95d6b41a828b	1712	* @arg @ref LL_RCC_PREDIV_DIV_16
<>	156:95d6b41a828b	1713	*/
<>	156:95d6b41a828b	1714	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
<>	156:95d6b41a828b	1715	{
<>	156:95d6b41a828b	1716	return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
<>	156:95d6b41a828b	1717	}
<>	156:95d6b41a828b	1718
<>	156:95d6b41a828b	1719	/**
<>	156:95d6b41a828b	1720	* @}
<>	156:95d6b41a828b	1721	*/
<>	156:95d6b41a828b	1722
<>	156:95d6b41a828b	1723	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
<>	156:95d6b41a828b	1724	* @{
<>	156:95d6b41a828b	1725	*/
<>	156:95d6b41a828b	1726
<>	156:95d6b41a828b	1727	/**
<>	156:95d6b41a828b	1728	* @brief Clear LSI ready interrupt flag
<>	156:95d6b41a828b	1729	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
<>	156:95d6b41a828b	1730	* @retval None
<>	156:95d6b41a828b	1731	*/
<>	156:95d6b41a828b	1732	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
<>	156:95d6b41a828b	1733	{
<>	156:95d6b41a828b	1734	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
<>	156:95d6b41a828b	1735	}
<>	156:95d6b41a828b	1736
<>	156:95d6b41a828b	1737	/**
<>	156:95d6b41a828b	1738	* @brief Clear LSE ready interrupt flag
<>	156:95d6b41a828b	1739	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
<>	156:95d6b41a828b	1740	* @retval None
<>	156:95d6b41a828b	1741	*/
<>	156:95d6b41a828b	1742	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
<>	156:95d6b41a828b	1743	{
<>	156:95d6b41a828b	1744	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
<>	156:95d6b41a828b	1745	}
<>	156:95d6b41a828b	1746
<>	156:95d6b41a828b	1747	/**
<>	156:95d6b41a828b	1748	* @brief Clear HSI ready interrupt flag
<>	156:95d6b41a828b	1749	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
<>	156:95d6b41a828b	1750	* @retval None
<>	156:95d6b41a828b	1751	*/
<>	156:95d6b41a828b	1752	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
<>	156:95d6b41a828b	1753	{
<>	156:95d6b41a828b	1754	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
<>	156:95d6b41a828b	1755	}
<>	156:95d6b41a828b	1756
<>	156:95d6b41a828b	1757	/**
<>	156:95d6b41a828b	1758	* @brief Clear HSE ready interrupt flag
<>	156:95d6b41a828b	1759	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
<>	156:95d6b41a828b	1760	* @retval None
<>	156:95d6b41a828b	1761	*/
<>	156:95d6b41a828b	1762	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
<>	156:95d6b41a828b	1763	{
<>	156:95d6b41a828b	1764	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
<>	156:95d6b41a828b	1765	}
<>	156:95d6b41a828b	1766
<>	156:95d6b41a828b	1767	/**
<>	156:95d6b41a828b	1768	* @brief Clear PLL ready interrupt flag
<>	156:95d6b41a828b	1769	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
<>	156:95d6b41a828b	1770	* @retval None
<>	156:95d6b41a828b	1771	*/
<>	156:95d6b41a828b	1772	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
<>	156:95d6b41a828b	1773	{
<>	156:95d6b41a828b	1774	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
<>	156:95d6b41a828b	1775	}
<>	156:95d6b41a828b	1776
<>	156:95d6b41a828b	1777	/**
<>	156:95d6b41a828b	1778	* @brief Clear HSI14 ready interrupt flag
<>	156:95d6b41a828b	1779	* @rmtoll CIR HSI14RDYC LL_RCC_ClearFlag_HSI14RDY
<>	156:95d6b41a828b	1780	* @retval None
<>	156:95d6b41a828b	1781	*/
<>	156:95d6b41a828b	1782	__STATIC_INLINE void LL_RCC_ClearFlag_HSI14RDY(void)
<>	156:95d6b41a828b	1783	{
<>	156:95d6b41a828b	1784	SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYC);
<>	156:95d6b41a828b	1785	}
<>	156:95d6b41a828b	1786
<>	156:95d6b41a828b	1787	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	1788	/**
<>	156:95d6b41a828b	1789	* @brief Clear HSI48 ready interrupt flag
<>	156:95d6b41a828b	1790	* @rmtoll CIR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
<>	156:95d6b41a828b	1791	* @retval None
<>	156:95d6b41a828b	1792	*/
<>	156:95d6b41a828b	1793	__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
<>	156:95d6b41a828b	1794	{
<>	156:95d6b41a828b	1795	SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYC);
<>	156:95d6b41a828b	1796	}
<>	156:95d6b41a828b	1797	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	1798
<>	156:95d6b41a828b	1799	/**
<>	156:95d6b41a828b	1800	* @brief Clear Clock security system interrupt flag
<>	156:95d6b41a828b	1801	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
<>	156:95d6b41a828b	1802	* @retval None
<>	156:95d6b41a828b	1803	*/
<>	156:95d6b41a828b	1804	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
<>	156:95d6b41a828b	1805	{
<>	156:95d6b41a828b	1806	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
<>	156:95d6b41a828b	1807	}
<>	156:95d6b41a828b	1808
<>	156:95d6b41a828b	1809	/**
<>	156:95d6b41a828b	1810	* @brief Check if LSI ready interrupt occurred or not
<>	156:95d6b41a828b	1811	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
<>	156:95d6b41a828b	1812	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1813	*/
<>	156:95d6b41a828b	1814	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
<>	156:95d6b41a828b	1815	{
<>	156:95d6b41a828b	1816	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
<>	156:95d6b41a828b	1817	}
<>	156:95d6b41a828b	1818
<>	156:95d6b41a828b	1819	/**
<>	156:95d6b41a828b	1820	* @brief Check if LSE ready interrupt occurred or not
<>	156:95d6b41a828b	1821	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
<>	156:95d6b41a828b	1822	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1823	*/
<>	156:95d6b41a828b	1824	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
<>	156:95d6b41a828b	1825	{
<>	156:95d6b41a828b	1826	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
<>	156:95d6b41a828b	1827	}
<>	156:95d6b41a828b	1828
<>	156:95d6b41a828b	1829	/**
<>	156:95d6b41a828b	1830	* @brief Check if HSI ready interrupt occurred or not
<>	156:95d6b41a828b	1831	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
<>	156:95d6b41a828b	1832	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1833	*/
<>	156:95d6b41a828b	1834	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
<>	156:95d6b41a828b	1835	{
<>	156:95d6b41a828b	1836	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
<>	156:95d6b41a828b	1837	}
<>	156:95d6b41a828b	1838
<>	156:95d6b41a828b	1839	/**
<>	156:95d6b41a828b	1840	* @brief Check if HSE ready interrupt occurred or not
<>	156:95d6b41a828b	1841	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
<>	156:95d6b41a828b	1842	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1843	*/
<>	156:95d6b41a828b	1844	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
<>	156:95d6b41a828b	1845	{
<>	156:95d6b41a828b	1846	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
<>	156:95d6b41a828b	1847	}
<>	156:95d6b41a828b	1848
<>	156:95d6b41a828b	1849	/**
<>	156:95d6b41a828b	1850	* @brief Check if PLL ready interrupt occurred or not
<>	156:95d6b41a828b	1851	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
<>	156:95d6b41a828b	1852	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1853	*/
<>	156:95d6b41a828b	1854	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
<>	156:95d6b41a828b	1855	{
<>	156:95d6b41a828b	1856	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
<>	156:95d6b41a828b	1857	}
<>	156:95d6b41a828b	1858
<>	156:95d6b41a828b	1859	/**
<>	156:95d6b41a828b	1860	* @brief Check if HSI14 ready interrupt occurred or not
<>	156:95d6b41a828b	1861	* @rmtoll CIR HSI14RDYF LL_RCC_IsActiveFlag_HSI14RDY
<>	156:95d6b41a828b	1862	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1863	*/
<>	156:95d6b41a828b	1864	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI14RDY(void)
<>	156:95d6b41a828b	1865	{
<>	156:95d6b41a828b	1866	return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYF) == (RCC_CIR_HSI14RDYF));
<>	156:95d6b41a828b	1867	}
<>	156:95d6b41a828b	1868
<>	156:95d6b41a828b	1869	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	1870	/**
<>	156:95d6b41a828b	1871	* @brief Check if HSI48 ready interrupt occurred or not
<>	156:95d6b41a828b	1872	* @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
<>	156:95d6b41a828b	1873	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1874	*/
<>	156:95d6b41a828b	1875	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
<>	156:95d6b41a828b	1876	{
<>	156:95d6b41a828b	1877	return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYF) == (RCC_CIR_HSI48RDYF));
<>	156:95d6b41a828b	1878	}
<>	156:95d6b41a828b	1879	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	1880
<>	156:95d6b41a828b	1881	/**
<>	156:95d6b41a828b	1882	* @brief Check if Clock security system interrupt occurred or not
<>	156:95d6b41a828b	1883	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
<>	156:95d6b41a828b	1884	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1885	*/
<>	156:95d6b41a828b	1886	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
<>	156:95d6b41a828b	1887	{
<>	156:95d6b41a828b	1888	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
<>	156:95d6b41a828b	1889	}
<>	156:95d6b41a828b	1890
<>	156:95d6b41a828b	1891	/**
<>	156:95d6b41a828b	1892	* @brief Check if RCC flag Independent Watchdog reset is set or not.
<>	156:95d6b41a828b	1893	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
<>	156:95d6b41a828b	1894	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1895	*/
<>	156:95d6b41a828b	1896	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
<>	156:95d6b41a828b	1897	{
<>	156:95d6b41a828b	1898	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
<>	156:95d6b41a828b	1899	}
<>	156:95d6b41a828b	1900
<>	156:95d6b41a828b	1901	/**
<>	156:95d6b41a828b	1902	* @brief Check if RCC flag Low Power reset is set or not.
<>	156:95d6b41a828b	1903	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
<>	156:95d6b41a828b	1904	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1905	*/
<>	156:95d6b41a828b	1906	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
<>	156:95d6b41a828b	1907	{
<>	156:95d6b41a828b	1908	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
<>	156:95d6b41a828b	1909	}
<>	156:95d6b41a828b	1910
<>	156:95d6b41a828b	1911	/**
<>	156:95d6b41a828b	1912	* @brief Check if RCC flag is set or not.
<>	156:95d6b41a828b	1913	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
<>	156:95d6b41a828b	1914	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1915	*/
<>	156:95d6b41a828b	1916	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
<>	156:95d6b41a828b	1917	{
<>	156:95d6b41a828b	1918	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
<>	156:95d6b41a828b	1919	}
<>	156:95d6b41a828b	1920
<>	156:95d6b41a828b	1921	/**
<>	156:95d6b41a828b	1922	* @brief Check if RCC flag Pin reset is set or not.
<>	156:95d6b41a828b	1923	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
<>	156:95d6b41a828b	1924	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1925	*/
<>	156:95d6b41a828b	1926	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
<>	156:95d6b41a828b	1927	{
<>	156:95d6b41a828b	1928	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
<>	156:95d6b41a828b	1929	}
<>	156:95d6b41a828b	1930
<>	156:95d6b41a828b	1931	/**
<>	156:95d6b41a828b	1932	* @brief Check if RCC flag POR/PDR reset is set or not.
<>	156:95d6b41a828b	1933	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
<>	156:95d6b41a828b	1934	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1935	*/
<>	156:95d6b41a828b	1936	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
<>	156:95d6b41a828b	1937	{
<>	156:95d6b41a828b	1938	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
<>	156:95d6b41a828b	1939	}
<>	156:95d6b41a828b	1940
<>	156:95d6b41a828b	1941	/**
<>	156:95d6b41a828b	1942	* @brief Check if RCC flag Software reset is set or not.
<>	156:95d6b41a828b	1943	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
<>	156:95d6b41a828b	1944	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1945	*/
<>	156:95d6b41a828b	1946	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
<>	156:95d6b41a828b	1947	{
<>	156:95d6b41a828b	1948	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
<>	156:95d6b41a828b	1949	}
<>	156:95d6b41a828b	1950
<>	156:95d6b41a828b	1951	/**
<>	156:95d6b41a828b	1952	* @brief Check if RCC flag Window Watchdog reset is set or not.
<>	156:95d6b41a828b	1953	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
<>	156:95d6b41a828b	1954	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1955	*/
<>	156:95d6b41a828b	1956	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
<>	156:95d6b41a828b	1957	{
<>	156:95d6b41a828b	1958	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
<>	156:95d6b41a828b	1959	}
<>	156:95d6b41a828b	1960
<>	156:95d6b41a828b	1961	#if defined(RCC_CSR_V18PWRRSTF)
<>	156:95d6b41a828b	1962	/**
<>	156:95d6b41a828b	1963	* @brief Check if RCC Reset flag of the 1.8 V domain is set or not.
<>	156:95d6b41a828b	1964	* @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST
<>	156:95d6b41a828b	1965	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1966	*/
<>	156:95d6b41a828b	1967	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
<>	156:95d6b41a828b	1968	{
<>	156:95d6b41a828b	1969	return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
<>	156:95d6b41a828b	1970	}
<>	156:95d6b41a828b	1971	#endif /* RCC_CSR_V18PWRRSTF */
<>	156:95d6b41a828b	1972
<>	156:95d6b41a828b	1973	/**
<>	156:95d6b41a828b	1974	* @brief Set RMVF bit to clear the reset flags.
<>	156:95d6b41a828b	1975	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
<>	156:95d6b41a828b	1976	* @retval None
<>	156:95d6b41a828b	1977	*/
<>	156:95d6b41a828b	1978	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
<>	156:95d6b41a828b	1979	{
<>	156:95d6b41a828b	1980	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
<>	156:95d6b41a828b	1981	}
<>	156:95d6b41a828b	1982
<>	156:95d6b41a828b	1983	/**
<>	156:95d6b41a828b	1984	* @}
<>	156:95d6b41a828b	1985	*/
<>	156:95d6b41a828b	1986
<>	156:95d6b41a828b	1987	/** @defgroup RCC_LL_EF_IT_Management IT Management
<>	156:95d6b41a828b	1988	* @{
<>	156:95d6b41a828b	1989	*/
<>	156:95d6b41a828b	1990
<>	156:95d6b41a828b	1991	/**
<>	156:95d6b41a828b	1992	* @brief Enable LSI ready interrupt
<>	156:95d6b41a828b	1993	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
<>	156:95d6b41a828b	1994	* @retval None
<>	156:95d6b41a828b	1995	*/
<>	156:95d6b41a828b	1996	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
<>	156:95d6b41a828b	1997	{
<>	156:95d6b41a828b	1998	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<>	156:95d6b41a828b	1999	}
<>	156:95d6b41a828b	2000
<>	156:95d6b41a828b	2001	/**
<>	156:95d6b41a828b	2002	* @brief Enable LSE ready interrupt
<>	156:95d6b41a828b	2003	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
<>	156:95d6b41a828b	2004	* @retval None
<>	156:95d6b41a828b	2005	*/
<>	156:95d6b41a828b	2006	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
<>	156:95d6b41a828b	2007	{
<>	156:95d6b41a828b	2008	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<>	156:95d6b41a828b	2009	}
<>	156:95d6b41a828b	2010
<>	156:95d6b41a828b	2011	/**
<>	156:95d6b41a828b	2012	* @brief Enable HSI ready interrupt
<>	156:95d6b41a828b	2013	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
<>	156:95d6b41a828b	2014	* @retval None
<>	156:95d6b41a828b	2015	*/
<>	156:95d6b41a828b	2016	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
<>	156:95d6b41a828b	2017	{
<>	156:95d6b41a828b	2018	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<>	156:95d6b41a828b	2019	}
<>	156:95d6b41a828b	2020
<>	156:95d6b41a828b	2021	/**
<>	156:95d6b41a828b	2022	* @brief Enable HSE ready interrupt
<>	156:95d6b41a828b	2023	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
<>	156:95d6b41a828b	2024	* @retval None
<>	156:95d6b41a828b	2025	*/
<>	156:95d6b41a828b	2026	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
<>	156:95d6b41a828b	2027	{
<>	156:95d6b41a828b	2028	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<>	156:95d6b41a828b	2029	}
<>	156:95d6b41a828b	2030
<>	156:95d6b41a828b	2031	/**
<>	156:95d6b41a828b	2032	* @brief Enable PLL ready interrupt
<>	156:95d6b41a828b	2033	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
<>	156:95d6b41a828b	2034	* @retval None
<>	156:95d6b41a828b	2035	*/
<>	156:95d6b41a828b	2036	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
<>	156:95d6b41a828b	2037	{
<>	156:95d6b41a828b	2038	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<>	156:95d6b41a828b	2039	}
<>	156:95d6b41a828b	2040
<>	156:95d6b41a828b	2041	/**
<>	156:95d6b41a828b	2042	* @brief Enable HSI14 ready interrupt
<>	156:95d6b41a828b	2043	* @rmtoll CIR HSI14RDYIE LL_RCC_EnableIT_HSI14RDY
<>	156:95d6b41a828b	2044	* @retval None
<>	156:95d6b41a828b	2045	*/
<>	156:95d6b41a828b	2046	__STATIC_INLINE void LL_RCC_EnableIT_HSI14RDY(void)
<>	156:95d6b41a828b	2047	{
<>	156:95d6b41a828b	2048	SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE);
<>	156:95d6b41a828b	2049	}
<>	156:95d6b41a828b	2050
<>	156:95d6b41a828b	2051	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	2052	/**
<>	156:95d6b41a828b	2053	* @brief Enable HSI48 ready interrupt
<>	156:95d6b41a828b	2054	* @rmtoll CIR HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
<>	156:95d6b41a828b	2055	* @retval None
<>	156:95d6b41a828b	2056	*/
<>	156:95d6b41a828b	2057	__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
<>	156:95d6b41a828b	2058	{
<>	156:95d6b41a828b	2059	SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE);
<>	156:95d6b41a828b	2060	}
<>	156:95d6b41a828b	2061	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	2062
<>	156:95d6b41a828b	2063	/**
<>	156:95d6b41a828b	2064	* @brief Disable LSI ready interrupt
<>	156:95d6b41a828b	2065	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
<>	156:95d6b41a828b	2066	* @retval None
<>	156:95d6b41a828b	2067	*/
<>	156:95d6b41a828b	2068	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
<>	156:95d6b41a828b	2069	{
<>	156:95d6b41a828b	2070	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<>	156:95d6b41a828b	2071	}
<>	156:95d6b41a828b	2072
<>	156:95d6b41a828b	2073	/**
<>	156:95d6b41a828b	2074	* @brief Disable LSE ready interrupt
<>	156:95d6b41a828b	2075	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
<>	156:95d6b41a828b	2076	* @retval None
<>	156:95d6b41a828b	2077	*/
<>	156:95d6b41a828b	2078	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
<>	156:95d6b41a828b	2079	{
<>	156:95d6b41a828b	2080	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<>	156:95d6b41a828b	2081	}
<>	156:95d6b41a828b	2082
<>	156:95d6b41a828b	2083	/**
<>	156:95d6b41a828b	2084	* @brief Disable HSI ready interrupt
<>	156:95d6b41a828b	2085	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
<>	156:95d6b41a828b	2086	* @retval None
<>	156:95d6b41a828b	2087	*/
<>	156:95d6b41a828b	2088	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
<>	156:95d6b41a828b	2089	{
<>	156:95d6b41a828b	2090	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<>	156:95d6b41a828b	2091	}
<>	156:95d6b41a828b	2092
<>	156:95d6b41a828b	2093	/**
<>	156:95d6b41a828b	2094	* @brief Disable HSE ready interrupt
<>	156:95d6b41a828b	2095	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
<>	156:95d6b41a828b	2096	* @retval None
<>	156:95d6b41a828b	2097	*/
<>	156:95d6b41a828b	2098	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
<>	156:95d6b41a828b	2099	{
<>	156:95d6b41a828b	2100	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<>	156:95d6b41a828b	2101	}
<>	156:95d6b41a828b	2102
<>	156:95d6b41a828b	2103	/**
<>	156:95d6b41a828b	2104	* @brief Disable PLL ready interrupt
<>	156:95d6b41a828b	2105	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
<>	156:95d6b41a828b	2106	* @retval None
<>	156:95d6b41a828b	2107	*/
<>	156:95d6b41a828b	2108	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
<>	156:95d6b41a828b	2109	{
<>	156:95d6b41a828b	2110	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<>	156:95d6b41a828b	2111	}
<>	156:95d6b41a828b	2112
<>	156:95d6b41a828b	2113	/**
<>	156:95d6b41a828b	2114	* @brief Disable HSI14 ready interrupt
<>	156:95d6b41a828b	2115	* @rmtoll CIR HSI14RDYIE LL_RCC_DisableIT_HSI14RDY
<>	156:95d6b41a828b	2116	* @retval None
<>	156:95d6b41a828b	2117	*/
<>	156:95d6b41a828b	2118	__STATIC_INLINE void LL_RCC_DisableIT_HSI14RDY(void)
<>	156:95d6b41a828b	2119	{
<>	156:95d6b41a828b	2120	CLEAR_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE);
<>	156:95d6b41a828b	2121	}
<>	156:95d6b41a828b	2122
<>	156:95d6b41a828b	2123	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	2124	/**
<>	156:95d6b41a828b	2125	* @brief Disable HSI48 ready interrupt
<>	156:95d6b41a828b	2126	* @rmtoll CIR HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
<>	156:95d6b41a828b	2127	* @retval None
<>	156:95d6b41a828b	2128	*/
<>	156:95d6b41a828b	2129	__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
<>	156:95d6b41a828b	2130	{
<>	156:95d6b41a828b	2131	CLEAR_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE);
<>	156:95d6b41a828b	2132	}
<>	156:95d6b41a828b	2133	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	2134
<>	156:95d6b41a828b	2135	/**
<>	156:95d6b41a828b	2136	* @brief Checks if LSI ready interrupt source is enabled or disabled.
<>	156:95d6b41a828b	2137	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
<>	156:95d6b41a828b	2138	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2139	*/
<>	156:95d6b41a828b	2140	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
<>	156:95d6b41a828b	2141	{
<>	156:95d6b41a828b	2142	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
<>	156:95d6b41a828b	2143	}
<>	156:95d6b41a828b	2144
<>	156:95d6b41a828b	2145	/**
<>	156:95d6b41a828b	2146	* @brief Checks if LSE ready interrupt source is enabled or disabled.
<>	156:95d6b41a828b	2147	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
<>	156:95d6b41a828b	2148	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2149	*/
<>	156:95d6b41a828b	2150	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
<>	156:95d6b41a828b	2151	{
<>	156:95d6b41a828b	2152	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
<>	156:95d6b41a828b	2153	}
<>	156:95d6b41a828b	2154
<>	156:95d6b41a828b	2155	/**
<>	156:95d6b41a828b	2156	* @brief Checks if HSI ready interrupt source is enabled or disabled.
<>	156:95d6b41a828b	2157	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
<>	156:95d6b41a828b	2158	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2159	*/
<>	156:95d6b41a828b	2160	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
<>	156:95d6b41a828b	2161	{
<>	156:95d6b41a828b	2162	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
<>	156:95d6b41a828b	2163	}
<>	156:95d6b41a828b	2164
<>	156:95d6b41a828b	2165	/**
<>	156:95d6b41a828b	2166	* @brief Checks if HSE ready interrupt source is enabled or disabled.
<>	156:95d6b41a828b	2167	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
<>	156:95d6b41a828b	2168	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2169	*/
<>	156:95d6b41a828b	2170	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
<>	156:95d6b41a828b	2171	{
<>	156:95d6b41a828b	2172	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
<>	156:95d6b41a828b	2173	}
<>	156:95d6b41a828b	2174
<>	156:95d6b41a828b	2175	/**
<>	156:95d6b41a828b	2176	* @brief Checks if PLL ready interrupt source is enabled or disabled.
<>	156:95d6b41a828b	2177	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
<>	156:95d6b41a828b	2178	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2179	*/
<>	156:95d6b41a828b	2180	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
<>	156:95d6b41a828b	2181	{
<>	156:95d6b41a828b	2182	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
<>	156:95d6b41a828b	2183	}
<>	156:95d6b41a828b	2184
<>	156:95d6b41a828b	2185	/**
<>	156:95d6b41a828b	2186	* @brief Checks if HSI14 ready interrupt source is enabled or disabled.
<>	156:95d6b41a828b	2187	* @rmtoll CIR HSI14RDYIE LL_RCC_IsEnabledIT_HSI14RDY
<>	156:95d6b41a828b	2188	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2189	*/
<>	156:95d6b41a828b	2190	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI14RDY(void)
<>	156:95d6b41a828b	2191	{
<>	156:95d6b41a828b	2192	return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE) == (RCC_CIR_HSI14RDYIE));
<>	156:95d6b41a828b	2193	}
<>	156:95d6b41a828b	2194
<>	156:95d6b41a828b	2195	#if defined(RCC_HSI48_SUPPORT)
<>	156:95d6b41a828b	2196	/**
<>	156:95d6b41a828b	2197	* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
<>	156:95d6b41a828b	2198	* @rmtoll CIR HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
<>	156:95d6b41a828b	2199	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2200	*/
<>	156:95d6b41a828b	2201	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
<>	156:95d6b41a828b	2202	{
<>	156:95d6b41a828b	2203	return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE) == (RCC_CIR_HSI48RDYIE));
<>	156:95d6b41a828b	2204	}
<>	156:95d6b41a828b	2205	#endif /* RCC_HSI48_SUPPORT */
<>	156:95d6b41a828b	2206
<>	156:95d6b41a828b	2207	/**
<>	156:95d6b41a828b	2208	* @}
<>	156:95d6b41a828b	2209	*/
<>	156:95d6b41a828b	2210
<>	156:95d6b41a828b	2211	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	2212	/** @defgroup RCC_LL_EF_Init De-initialization function
<>	156:95d6b41a828b	2213	* @{
<>	156:95d6b41a828b	2214	*/
<>	156:95d6b41a828b	2215	ErrorStatus LL_RCC_DeInit(void);
<>	156:95d6b41a828b	2216	/**
<>	156:95d6b41a828b	2217	* @}
<>	156:95d6b41a828b	2218	*/
<>	156:95d6b41a828b	2219
<>	156:95d6b41a828b	2220	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
<>	156:95d6b41a828b	2221	* @{
<>	156:95d6b41a828b	2222	*/
<>	156:95d6b41a828b	2223	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
<>	156:95d6b41a828b	2224	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
<>	156:95d6b41a828b	2225	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
<>	156:95d6b41a828b	2226	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	156:95d6b41a828b	2227	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
<>	156:95d6b41a828b	2228	#endif /* USB_OTG_FS \|\| USB */
<>	156:95d6b41a828b	2229	#if defined(CEC)
<>	156:95d6b41a828b	2230	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
<>	156:95d6b41a828b	2231	#endif /* CEC */
<>	156:95d6b41a828b	2232	/**
<>	156:95d6b41a828b	2233	* @}
<>	156:95d6b41a828b	2234	*/
<>	156:95d6b41a828b	2235	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	2236
<>	156:95d6b41a828b	2237	/**
<>	156:95d6b41a828b	2238	* @}
<>	156:95d6b41a828b	2239	*/
<>	156:95d6b41a828b	2240
<>	156:95d6b41a828b	2241	/**
<>	156:95d6b41a828b	2242	* @}
<>	156:95d6b41a828b	2243	*/
<>	156:95d6b41a828b	2244
<>	156:95d6b41a828b	2245	#endif /* RCC */
<>	156:95d6b41a828b	2246
<>	156:95d6b41a828b	2247	/**
<>	156:95d6b41a828b	2248	* @}
<>	156:95d6b41a828b	2249	*/
<>	156:95d6b41a828b	2250
<>	156:95d6b41a828b	2251	#ifdef __cplusplus
<>	156:95d6b41a828b	2252	}
<>	156:95d6b41a828b	2253	#endif
<>	156:95d6b41a828b	2254
<>	156:95d6b41a828b	2255	#endif /* __STM32F0xx_LL_RCC_H */
<>	156:95d6b41a828b	2256
<>	156:95d6b41a828b	2257	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/