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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_adc.c
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief ADC LL module driver
<> 156:95d6b41a828b 6 ******************************************************************************
<> 156:95d6b41a828b 7 * @attention
<> 156:95d6b41a828b 8 *
<> 156:95d6b41a828b 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 12 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 14 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 17 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 19 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 20 * without specific prior written permission.
<> 156:95d6b41a828b 21 *
<> 156:95d6b41a828b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 32 *
<> 156:95d6b41a828b 33 ******************************************************************************
<> 156:95d6b41a828b 34 */
<> 156:95d6b41a828b 35 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 36
<> 156:95d6b41a828b 37 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 38 #include "stm32f0xx_ll_adc.h"
<> 156:95d6b41a828b 39 #include "stm32f0xx_ll_bus.h"
<> 156:95d6b41a828b 40
<> 156:95d6b41a828b 41 #ifdef USE_FULL_ASSERT
<> 156:95d6b41a828b 42 #include "stm32_assert.h"
<> 156:95d6b41a828b 43 #else
<> 156:95d6b41a828b 44 #define assert_param(expr) ((void)0U)
<> 156:95d6b41a828b 45 #endif
<> 156:95d6b41a828b 46
<> 156:95d6b41a828b 47 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 48 * @{
<> 156:95d6b41a828b 49 */
<> 156:95d6b41a828b 50
<> 156:95d6b41a828b 51 #if defined (ADC1)
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 /** @addtogroup ADC_LL ADC
<> 156:95d6b41a828b 54 * @{
<> 156:95d6b41a828b 55 */
<> 156:95d6b41a828b 56
<> 156:95d6b41a828b 57 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 58 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 59 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 60 /** @addtogroup ADC_LL_Private_Constants
<> 156:95d6b41a828b 61 * @{
<> 156:95d6b41a828b 62 */
<> 156:95d6b41a828b 63
<> 156:95d6b41a828b 64 /* Definitions of ADC hardware constraints delays */
<> 156:95d6b41a828b 65 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
<> 156:95d6b41a828b 66 /* not timeout values: */
<> 156:95d6b41a828b 67 /* Timeout values for ADC operations are dependent to device clock */
<> 156:95d6b41a828b 68 /* configuration (system clock versus ADC clock), */
<> 156:95d6b41a828b 69 /* and therefore must be defined in user application. */
<> 156:95d6b41a828b 70 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
<> 156:95d6b41a828b 71 /* values definition. */
<> 156:95d6b41a828b 72 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
<> 156:95d6b41a828b 73 /* of device clock setting. */
<> 156:95d6b41a828b 74 /* In user application, ADC timeout values should be defined with */
<> 156:95d6b41a828b 75 /* temporal values, in function of device clock settings. */
<> 156:95d6b41a828b 76 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
<> 156:95d6b41a828b 77 /* - ADC clock from synchronous clock with AHB prescaler 512, */
<> 156:95d6b41a828b 78 /* APB prescaler 16, ADC prescaler 4. */
<> 156:95d6b41a828b 79 /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
<> 156:95d6b41a828b 80 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
<> 156:95d6b41a828b 81 /* CPU clock frequency max 48MHz, HSI frequency 14MHz: ratio 4. */
<> 156:95d6b41a828b 82 /* Unit: CPU cycles. */
<> 156:95d6b41a828b 83 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
<> 156:95d6b41a828b 84 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
<> 156:95d6b41a828b 85 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
<> 156:95d6b41a828b 86
<> 156:95d6b41a828b 87 /**
<> 156:95d6b41a828b 88 * @}
<> 156:95d6b41a828b 89 */
<> 156:95d6b41a828b 90
<> 156:95d6b41a828b 91 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 92
<> 156:95d6b41a828b 93 /** @addtogroup ADC_LL_Private_Macros
<> 156:95d6b41a828b 94 * @{
<> 156:95d6b41a828b 95 */
<> 156:95d6b41a828b 96
<> 156:95d6b41a828b 97 /* Check of parameters for configuration of ADC hierarchical scope: */
<> 156:95d6b41a828b 98 /* common to several ADC instances. */
<> 156:95d6b41a828b 99 /* Check of parameters for configuration of ADC hierarchical scope: */
<> 156:95d6b41a828b 100 /* ADC instance. */
<> 156:95d6b41a828b 101 #define IS_LL_ADC_CLOCK(__CLOCK__) \
<> 156:95d6b41a828b 102 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
<> 156:95d6b41a828b 103 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
<> 156:95d6b41a828b 104 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
<> 156:95d6b41a828b 105 )
<> 156:95d6b41a828b 106
<> 156:95d6b41a828b 107 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
<> 156:95d6b41a828b 108 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
<> 156:95d6b41a828b 109 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
<> 156:95d6b41a828b 110 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
<> 156:95d6b41a828b 111 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
<> 156:95d6b41a828b 112 )
<> 156:95d6b41a828b 113
<> 156:95d6b41a828b 114 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
<> 156:95d6b41a828b 115 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
<> 156:95d6b41a828b 116 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
<> 156:95d6b41a828b 117 )
<> 156:95d6b41a828b 118
<> 156:95d6b41a828b 119 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
<> 156:95d6b41a828b 120 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
<> 156:95d6b41a828b 121 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
<> 156:95d6b41a828b 122 || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
<> 156:95d6b41a828b 123 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
<> 156:95d6b41a828b 124 )
<> 156:95d6b41a828b 125
<> 156:95d6b41a828b 126 /* Check of parameters for configuration of ADC hierarchical scope: */
<> 156:95d6b41a828b 127 /* ADC group regular */
<> 156:95d6b41a828b 128 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
<> 156:95d6b41a828b 129 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
<> 156:95d6b41a828b 130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
<> 156:95d6b41a828b 131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \
<> 156:95d6b41a828b 132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
<> 156:95d6b41a828b 133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
<> 156:95d6b41a828b 134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
<> 156:95d6b41a828b 135 )
<> 156:95d6b41a828b 136
<> 156:95d6b41a828b 137 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
<> 156:95d6b41a828b 138 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
<> 156:95d6b41a828b 139 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
<> 156:95d6b41a828b 140 )
<> 156:95d6b41a828b 141
<> 156:95d6b41a828b 142 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
<> 156:95d6b41a828b 143 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
<> 156:95d6b41a828b 144 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
<> 156:95d6b41a828b 145 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
<> 156:95d6b41a828b 146 )
<> 156:95d6b41a828b 147
<> 156:95d6b41a828b 148 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
<> 156:95d6b41a828b 149 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
<> 156:95d6b41a828b 150 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
<> 156:95d6b41a828b 151 )
<> 156:95d6b41a828b 152
<> 156:95d6b41a828b 153 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
<> 156:95d6b41a828b 154 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
<> 156:95d6b41a828b 155 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
<> 156:95d6b41a828b 156 )
<> 156:95d6b41a828b 157
<> 156:95d6b41a828b 158 /**
<> 156:95d6b41a828b 159 * @}
<> 156:95d6b41a828b 160 */
<> 156:95d6b41a828b 161
<> 156:95d6b41a828b 162
<> 156:95d6b41a828b 163 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 164
<> 156:95d6b41a828b 165 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 166 /** @addtogroup ADC_LL_Exported_Functions
<> 156:95d6b41a828b 167 * @{
<> 156:95d6b41a828b 168 */
<> 156:95d6b41a828b 169
<> 156:95d6b41a828b 170 /** @addtogroup ADC_LL_EF_Init
<> 156:95d6b41a828b 171 * @{
<> 156:95d6b41a828b 172 */
<> 156:95d6b41a828b 173
<> 156:95d6b41a828b 174 /**
<> 156:95d6b41a828b 175 * @brief De-initialize registers of all ADC instances belonging to
<> 156:95d6b41a828b 176 * the same ADC common instance to their default reset values.
<> 156:95d6b41a828b 177 * @note This function is performing a hard reset, using high level
<> 156:95d6b41a828b 178 * clock source RCC ADC reset.
<> 156:95d6b41a828b 179 * @param ADCxy_COMMON ADC common instance
<> 156:95d6b41a828b 180 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<> 156:95d6b41a828b 181 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 182 * - SUCCESS: ADC common registers are de-initialized
<> 156:95d6b41a828b 183 * - ERROR: not applicable
<> 156:95d6b41a828b 184 */
<> 156:95d6b41a828b 185 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
<> 156:95d6b41a828b 186 {
<> 156:95d6b41a828b 187 /* Check the parameters */
<> 156:95d6b41a828b 188 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
<> 156:95d6b41a828b 189
<> 156:95d6b41a828b 190 /* Force reset of ADC clock (core clock) */
<> 156:95d6b41a828b 191 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1);
<> 156:95d6b41a828b 192
<> 156:95d6b41a828b 193 /* Release reset of ADC clock (core clock) */
<> 156:95d6b41a828b 194 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1);
<> 156:95d6b41a828b 195
<> 156:95d6b41a828b 196 return SUCCESS;
<> 156:95d6b41a828b 197 }
<> 156:95d6b41a828b 198
<> 156:95d6b41a828b 199
<> 156:95d6b41a828b 200 /**
<> 156:95d6b41a828b 201 * @brief De-initialize registers of the selected ADC instance
<> 156:95d6b41a828b 202 * to their default reset values.
<> 156:95d6b41a828b 203 * @note To reset all ADC instances quickly (perform a hard reset),
<> 156:95d6b41a828b 204 * use function @ref LL_ADC_CommonDeInit().
<> 156:95d6b41a828b 205 * @note If this functions returns error status, it means that ADC instance
<> 156:95d6b41a828b 206 * is in an unknown state.
<> 156:95d6b41a828b 207 * In this case, perform a hard reset using high level
<> 156:95d6b41a828b 208 * clock source RCC ADC reset.
<> 156:95d6b41a828b 209 * Refer to function @ref LL_ADC_CommonDeInit().
<> 156:95d6b41a828b 210 * @param ADCx ADC instance
<> 156:95d6b41a828b 211 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 212 * - SUCCESS: ADC registers are de-initialized
<> 156:95d6b41a828b 213 * - ERROR: ADC registers are not de-initialized
<> 156:95d6b41a828b 214 */
<> 156:95d6b41a828b 215 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
<> 156:95d6b41a828b 216 {
<> 156:95d6b41a828b 217 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 218
<> 156:95d6b41a828b 219 __IO uint32_t timeout_cpu_cycles = 0U;
<> 156:95d6b41a828b 220
<> 156:95d6b41a828b 221 /* Check the parameters */
<> 156:95d6b41a828b 222 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
<> 156:95d6b41a828b 223
<> 156:95d6b41a828b 224 /* Disable ADC instance if not already disabled. */
<> 156:95d6b41a828b 225 if(LL_ADC_IsEnabled(ADCx) == 1U)
<> 156:95d6b41a828b 226 {
<> 156:95d6b41a828b 227 /* Set ADC group regular trigger source to SW start to ensure to not */
<> 156:95d6b41a828b 228 /* have an external trigger event occurring during the conversion stop */
<> 156:95d6b41a828b 229 /* ADC disable process. */
<> 156:95d6b41a828b 230 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
<> 156:95d6b41a828b 231
<> 156:95d6b41a828b 232 /* Stop potential ADC conversion on going on ADC group regular. */
<> 156:95d6b41a828b 233 if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
<> 156:95d6b41a828b 234 {
<> 156:95d6b41a828b 235 if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
<> 156:95d6b41a828b 236 {
<> 156:95d6b41a828b 237 LL_ADC_REG_StopConversion(ADCx);
<> 156:95d6b41a828b 238 }
<> 156:95d6b41a828b 239 }
<> 156:95d6b41a828b 240
<> 156:95d6b41a828b 241 /* Wait for ADC conversions are effectively stopped */
<> 156:95d6b41a828b 242 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
<> 156:95d6b41a828b 243 while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)
<> 156:95d6b41a828b 244 {
<> 156:95d6b41a828b 245 if(timeout_cpu_cycles-- == 0U)
<> 156:95d6b41a828b 246 {
<> 156:95d6b41a828b 247 /* Time-out error */
<> 156:95d6b41a828b 248 status = ERROR;
<> 156:95d6b41a828b 249 }
<> 156:95d6b41a828b 250 }
<> 156:95d6b41a828b 251
<> 156:95d6b41a828b 252 /* Disable the ADC instance */
<> 156:95d6b41a828b 253 LL_ADC_Disable(ADCx);
<> 156:95d6b41a828b 254
<> 156:95d6b41a828b 255 /* Wait for ADC instance is effectively disabled */
<> 156:95d6b41a828b 256 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
<> 156:95d6b41a828b 257 while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
<> 156:95d6b41a828b 258 {
<> 156:95d6b41a828b 259 if(timeout_cpu_cycles-- == 0U)
<> 156:95d6b41a828b 260 {
<> 156:95d6b41a828b 261 /* Time-out error */
<> 156:95d6b41a828b 262 status = ERROR;
<> 156:95d6b41a828b 263 }
<> 156:95d6b41a828b 264 }
<> 156:95d6b41a828b 265 }
<> 156:95d6b41a828b 266
<> 156:95d6b41a828b 267 /* Check whether ADC state is compliant with expected state */
<> 156:95d6b41a828b 268 if(READ_BIT(ADCx->CR,
<> 156:95d6b41a828b 269 ( ADC_CR_ADSTP | ADC_CR_ADSTART
<> 156:95d6b41a828b 270 | ADC_CR_ADDIS | ADC_CR_ADEN )
<> 156:95d6b41a828b 271 )
<> 156:95d6b41a828b 272 == 0U)
<> 156:95d6b41a828b 273 {
<> 156:95d6b41a828b 274 /* ========== Reset ADC registers ========== */
<> 156:95d6b41a828b 275 /* Reset register IER */
<> 156:95d6b41a828b 276 CLEAR_BIT(ADCx->IER,
<> 156:95d6b41a828b 277 ( LL_ADC_IT_ADRDY
<> 156:95d6b41a828b 278 | LL_ADC_IT_EOC
<> 156:95d6b41a828b 279 | LL_ADC_IT_EOS
<> 156:95d6b41a828b 280 | LL_ADC_IT_OVR
<> 156:95d6b41a828b 281 | LL_ADC_IT_EOSMP
<> 156:95d6b41a828b 282 | LL_ADC_IT_AWD1 )
<> 156:95d6b41a828b 283 );
<> 156:95d6b41a828b 284
<> 156:95d6b41a828b 285 /* Reset register ISR */
<> 156:95d6b41a828b 286 SET_BIT(ADCx->ISR,
<> 156:95d6b41a828b 287 ( LL_ADC_FLAG_ADRDY
<> 156:95d6b41a828b 288 | LL_ADC_FLAG_EOC
<> 156:95d6b41a828b 289 | LL_ADC_FLAG_EOS
<> 156:95d6b41a828b 290 | LL_ADC_FLAG_OVR
<> 156:95d6b41a828b 291 | LL_ADC_FLAG_EOSMP
<> 156:95d6b41a828b 292 | LL_ADC_FLAG_AWD1 )
<> 156:95d6b41a828b 293 );
<> 156:95d6b41a828b 294
<> 156:95d6b41a828b 295 /* Reset register CR */
<> 156:95d6b41a828b 296 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
<> 156:95d6b41a828b 297 /* "read-set": no direct reset applicable. */
<> 156:95d6b41a828b 298 /* No action on register CR */
<> 156:95d6b41a828b 299
<> 156:95d6b41a828b 300 /* Reset register CFGR1 */
<> 156:95d6b41a828b 301 CLEAR_BIT(ADCx->CFGR1,
<> 156:95d6b41a828b 302 ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN
<> 156:95d6b41a828b 303 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
<> 156:95d6b41a828b 304 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
<> 156:95d6b41a828b 305 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
<> 156:95d6b41a828b 306 );
<> 156:95d6b41a828b 307
<> 156:95d6b41a828b 308 /* Reset register CFGR2 */
<> 156:95d6b41a828b 309 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
<> 156:95d6b41a828b 310 /* already done above. */
<> 156:95d6b41a828b 311 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE);
<> 156:95d6b41a828b 312
<> 156:95d6b41a828b 313 /* Reset register SMPR */
<> 156:95d6b41a828b 314 CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
<> 156:95d6b41a828b 315
<> 156:95d6b41a828b 316 /* Reset register TR */
<> 156:95d6b41a828b 317 MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
<> 156:95d6b41a828b 318
<> 156:95d6b41a828b 319 /* Reset register CHSELR */
<> 156:95d6b41a828b 320 #if defined(ADC_CCR_VBATEN)
<> 156:95d6b41a828b 321 CLEAR_BIT(ADCx->CHSELR,
<> 156:95d6b41a828b 322 ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
<> 156:95d6b41a828b 323 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
<> 156:95d6b41a828b 324 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
<> 156:95d6b41a828b 325 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
<> 156:95d6b41a828b 326 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
<> 156:95d6b41a828b 327 );
<> 156:95d6b41a828b 328 #else
<> 156:95d6b41a828b 329 CLEAR_BIT(ADCx->CHSELR,
<> 156:95d6b41a828b 330 ( ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
<> 156:95d6b41a828b 331 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
<> 156:95d6b41a828b 332 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
<> 156:95d6b41a828b 333 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
<> 156:95d6b41a828b 334 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
<> 156:95d6b41a828b 335 );
<> 156:95d6b41a828b 336 #endif
<> 156:95d6b41a828b 337
<> 156:95d6b41a828b 338 /* Reset register DR */
<> 156:95d6b41a828b 339 /* bits in access mode read only, no direct reset applicable */
<> 156:95d6b41a828b 340
<> 156:95d6b41a828b 341 }
<> 156:95d6b41a828b 342 else
<> 156:95d6b41a828b 343 {
<> 156:95d6b41a828b 344 /* ADC instance is in an unknown state */
<> 156:95d6b41a828b 345 /* Need to performing a hard reset of ADC instance, using high level */
<> 156:95d6b41a828b 346 /* clock source RCC ADC reset. */
<> 156:95d6b41a828b 347 /* Caution: On this STM32 serie, if several ADC instances are available */
<> 156:95d6b41a828b 348 /* on the selected device, RCC ADC reset will reset */
<> 156:95d6b41a828b 349 /* all ADC instances belonging to the common ADC instance. */
<> 156:95d6b41a828b 350 status = ERROR;
<> 156:95d6b41a828b 351 }
<> 156:95d6b41a828b 352
<> 156:95d6b41a828b 353 return status;
<> 156:95d6b41a828b 354 }
<> 156:95d6b41a828b 355
<> 156:95d6b41a828b 356 /**
<> 156:95d6b41a828b 357 * @brief Initialize some features of ADC instance.
<> 156:95d6b41a828b 358 * @note These parameters have an impact on ADC scope: ADC instance.
<> 156:95d6b41a828b 359 * Refer to corresponding unitary functions into
<> 156:95d6b41a828b 360 * @ref ADC_LL_EF_Configuration_ADC_Instance .
<> 156:95d6b41a828b 361 * @note The setting of these parameters by function @ref LL_ADC_Init()
<> 156:95d6b41a828b 362 * is conditioned to ADC state:
<> 156:95d6b41a828b 363 * ADC instance must be disabled.
<> 156:95d6b41a828b 364 * This condition is applied to all ADC features, for efficiency
<> 156:95d6b41a828b 365 * and compatibility over all STM32 families. However, the different
<> 156:95d6b41a828b 366 * features can be set under different ADC state conditions
<> 156:95d6b41a828b 367 * (setting possible with ADC enabled without conversion on going,
<> 156:95d6b41a828b 368 * ADC enabled with conversion on going, ...)
<> 156:95d6b41a828b 369 * Each feature can be updated afterwards with a unitary function
<> 156:95d6b41a828b 370 * and potentially with ADC in a different state than disabled,
<> 156:95d6b41a828b 371 * refer to description of each function for setting
<> 156:95d6b41a828b 372 * conditioned to ADC state.
<> 156:95d6b41a828b 373 * @note After using this function, some other features must be configured
<> 156:95d6b41a828b 374 * using LL unitary functions.
<> 156:95d6b41a828b 375 * The minimum configuration remaining to be done is:
<> 156:95d6b41a828b 376 * - Set ADC group regular sequencer:
<> 156:95d6b41a828b 377 * map channel on rank corresponding to channel number.
<> 156:95d6b41a828b 378 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
<> 156:95d6b41a828b 379 * - Set ADC channel sampling time
<> 156:95d6b41a828b 380 * Refer to function LL_ADC_SetChannelSamplingTime();
<> 156:95d6b41a828b 381 * @param ADCx ADC instance
<> 156:95d6b41a828b 382 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
<> 156:95d6b41a828b 383 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 384 * - SUCCESS: ADC registers are initialized
<> 156:95d6b41a828b 385 * - ERROR: ADC registers are not initialized
<> 156:95d6b41a828b 386 */
<> 156:95d6b41a828b 387 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
<> 156:95d6b41a828b 388 {
<> 156:95d6b41a828b 389 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 390
<> 156:95d6b41a828b 391 /* Check the parameters */
<> 156:95d6b41a828b 392 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
<> 156:95d6b41a828b 393
<> 156:95d6b41a828b 394 assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
<> 156:95d6b41a828b 395 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
<> 156:95d6b41a828b 396 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
<> 156:95d6b41a828b 397 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
<> 156:95d6b41a828b 398
<> 156:95d6b41a828b 399 /* Note: Hardware constraint (refer to description of this function): */
<> 156:95d6b41a828b 400 /* ADC instance must be disabled. */
<> 156:95d6b41a828b 401 if(LL_ADC_IsEnabled(ADCx) == 0U)
<> 156:95d6b41a828b 402 {
<> 156:95d6b41a828b 403 /* Configuration of ADC hierarchical scope: */
<> 156:95d6b41a828b 404 /* - ADC instance */
<> 156:95d6b41a828b 405 /* - Set ADC data resolution */
<> 156:95d6b41a828b 406 /* - Set ADC conversion data alignment */
<> 156:95d6b41a828b 407 /* - Set ADC low power mode */
<> 156:95d6b41a828b 408 MODIFY_REG(ADCx->CFGR1,
<> 156:95d6b41a828b 409 ADC_CFGR1_RES
<> 156:95d6b41a828b 410 | ADC_CFGR1_ALIGN
<> 156:95d6b41a828b 411 | ADC_CFGR1_WAIT
<> 156:95d6b41a828b 412 | ADC_CFGR1_AUTOFF
<> 156:95d6b41a828b 413 ,
<> 156:95d6b41a828b 414 ADC_InitStruct->Resolution
<> 156:95d6b41a828b 415 | ADC_InitStruct->DataAlignment
<> 156:95d6b41a828b 416 | ADC_InitStruct->LowPowerMode
<> 156:95d6b41a828b 417 );
<> 156:95d6b41a828b 418
<> 156:95d6b41a828b 419 }
<> 156:95d6b41a828b 420 else
<> 156:95d6b41a828b 421 {
<> 156:95d6b41a828b 422 /* Initialization error: ADC instance is not disabled. */
<> 156:95d6b41a828b 423 status = ERROR;
<> 156:95d6b41a828b 424 }
<> 156:95d6b41a828b 425 return status;
<> 156:95d6b41a828b 426 }
<> 156:95d6b41a828b 427
<> 156:95d6b41a828b 428 /**
<> 156:95d6b41a828b 429 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
<> 156:95d6b41a828b 430 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
<> 156:95d6b41a828b 431 * whose fields will be set to default values.
<> 156:95d6b41a828b 432 * @retval None
<> 156:95d6b41a828b 433 */
<> 156:95d6b41a828b 434 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
<> 156:95d6b41a828b 435 {
<> 156:95d6b41a828b 436 /* Set ADC_InitStruct fields to default values */
<> 156:95d6b41a828b 437 /* Set fields of ADC instance */
<> 156:95d6b41a828b 438 ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
<> 156:95d6b41a828b 439 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
<> 156:95d6b41a828b 440 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
<> 156:95d6b41a828b 441 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
<> 156:95d6b41a828b 442
<> 156:95d6b41a828b 443 }
<> 156:95d6b41a828b 444
<> 156:95d6b41a828b 445 /**
<> 156:95d6b41a828b 446 * @brief Initialize some features of ADC group regular.
<> 156:95d6b41a828b 447 * @note These parameters have an impact on ADC scope: ADC group regular.
<> 156:95d6b41a828b 448 * Refer to corresponding unitary functions into
<> 156:95d6b41a828b 449 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<> 156:95d6b41a828b 450 * (functions with prefix "REG").
<> 156:95d6b41a828b 451 * @note The setting of these parameters by function @ref LL_ADC_Init()
<> 156:95d6b41a828b 452 * is conditioned to ADC state:
<> 156:95d6b41a828b 453 * ADC instance must be disabled.
<> 156:95d6b41a828b 454 * This condition is applied to all ADC features, for efficiency
<> 156:95d6b41a828b 455 * and compatibility over all STM32 families. However, the different
<> 156:95d6b41a828b 456 * features can be set under different ADC state conditions
<> 156:95d6b41a828b 457 * (setting possible with ADC enabled without conversion on going,
<> 156:95d6b41a828b 458 * ADC enabled with conversion on going, ...)
<> 156:95d6b41a828b 459 * Each feature can be updated afterwards with a unitary function
<> 156:95d6b41a828b 460 * and potentially with ADC in a different state than disabled,
<> 156:95d6b41a828b 461 * refer to description of each function for setting
<> 156:95d6b41a828b 462 * conditioned to ADC state.
<> 156:95d6b41a828b 463 * @note After using this function, other features must be configured
<> 156:95d6b41a828b 464 * using LL unitary functions.
<> 156:95d6b41a828b 465 * The minimum configuration remaining to be done is:
<> 156:95d6b41a828b 466 * - Set ADC group regular sequencer:
<> 156:95d6b41a828b 467 * map channel on rank corresponding to channel number.
<> 156:95d6b41a828b 468 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
<> 156:95d6b41a828b 469 * - Set ADC channel sampling time
<> 156:95d6b41a828b 470 * Refer to function LL_ADC_SetChannelSamplingTime();
<> 156:95d6b41a828b 471 * @param ADCx ADC instance
<> 156:95d6b41a828b 472 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
<> 156:95d6b41a828b 473 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 474 * - SUCCESS: ADC registers are initialized
<> 156:95d6b41a828b 475 * - ERROR: ADC registers are not initialized
<> 156:95d6b41a828b 476 */
<> 156:95d6b41a828b 477 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
<> 156:95d6b41a828b 478 {
<> 156:95d6b41a828b 479 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 480
<> 156:95d6b41a828b 481 /* Check the parameters */
<> 156:95d6b41a828b 482 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
<> 156:95d6b41a828b 483 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
<> 156:95d6b41a828b 484 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
<> 156:95d6b41a828b 485 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
<> 156:95d6b41a828b 486 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
<> 156:95d6b41a828b 487 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
<> 156:95d6b41a828b 488
<> 156:95d6b41a828b 489 /* Note: Hardware constraint (refer to description of this function): */
<> 156:95d6b41a828b 490 /* ADC instance must be disabled. */
<> 156:95d6b41a828b 491 if(LL_ADC_IsEnabled(ADCx) == 0U)
<> 156:95d6b41a828b 492 {
<> 156:95d6b41a828b 493 /* Configuration of ADC hierarchical scope: */
<> 156:95d6b41a828b 494 /* - ADC group regular */
<> 156:95d6b41a828b 495 /* - Set ADC group regular trigger source */
<> 156:95d6b41a828b 496 /* - Set ADC group regular sequencer discontinuous mode */
<> 156:95d6b41a828b 497 /* - Set ADC group regular continuous mode */
<> 156:95d6b41a828b 498 /* - Set ADC group regular conversion data transfer: no transfer or */
<> 156:95d6b41a828b 499 /* transfer by DMA, and DMA requests mode */
<> 156:95d6b41a828b 500 /* - Set ADC group regular overrun behavior */
<> 156:95d6b41a828b 501 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
<> 156:95d6b41a828b 502 /* setting of trigger source to SW start. */
<> 156:95d6b41a828b 503 MODIFY_REG(ADCx->CFGR1,
<> 156:95d6b41a828b 504 ADC_CFGR1_EXTSEL
<> 156:95d6b41a828b 505 | ADC_CFGR1_EXTEN
<> 156:95d6b41a828b 506 | ADC_CFGR1_DISCEN
<> 156:95d6b41a828b 507 | ADC_CFGR1_CONT
<> 156:95d6b41a828b 508 | ADC_CFGR1_DMAEN
<> 156:95d6b41a828b 509 | ADC_CFGR1_DMACFG
<> 156:95d6b41a828b 510 | ADC_CFGR1_OVRMOD
<> 156:95d6b41a828b 511 ,
<> 156:95d6b41a828b 512 ADC_REG_InitStruct->TriggerSource
<> 156:95d6b41a828b 513 | ADC_REG_InitStruct->SequencerDiscont
<> 156:95d6b41a828b 514 | ADC_REG_InitStruct->ContinuousMode
<> 156:95d6b41a828b 515 | ADC_REG_InitStruct->DMATransfer
<> 156:95d6b41a828b 516 | ADC_REG_InitStruct->Overrun
<> 156:95d6b41a828b 517 );
<> 156:95d6b41a828b 518
<> 156:95d6b41a828b 519 }
<> 156:95d6b41a828b 520 else
<> 156:95d6b41a828b 521 {
<> 156:95d6b41a828b 522 /* Initialization error: ADC instance is not disabled. */
<> 156:95d6b41a828b 523 status = ERROR;
<> 156:95d6b41a828b 524 }
<> 156:95d6b41a828b 525 return status;
<> 156:95d6b41a828b 526 }
<> 156:95d6b41a828b 527
<> 156:95d6b41a828b 528 /**
<> 156:95d6b41a828b 529 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
<> 156:95d6b41a828b 530 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
<> 156:95d6b41a828b 531 * whose fields will be set to default values.
<> 156:95d6b41a828b 532 * @retval None
<> 156:95d6b41a828b 533 */
<> 156:95d6b41a828b 534 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
<> 156:95d6b41a828b 535 {
<> 156:95d6b41a828b 536 /* Set ADC_REG_InitStruct fields to default values */
<> 156:95d6b41a828b 537 /* Set fields of ADC group regular */
<> 156:95d6b41a828b 538 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
<> 156:95d6b41a828b 539 /* setting of trigger source to SW start. */
<> 156:95d6b41a828b 540 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
<> 156:95d6b41a828b 541 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
<> 156:95d6b41a828b 542 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
<> 156:95d6b41a828b 543 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
<> 156:95d6b41a828b 544 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
<> 156:95d6b41a828b 545 }
<> 156:95d6b41a828b 546
<> 156:95d6b41a828b 547 /**
<> 156:95d6b41a828b 548 * @}
<> 156:95d6b41a828b 549 */
<> 156:95d6b41a828b 550
<> 156:95d6b41a828b 551 /**
<> 156:95d6b41a828b 552 * @}
<> 156:95d6b41a828b 553 */
<> 156:95d6b41a828b 554
<> 156:95d6b41a828b 555 /**
<> 156:95d6b41a828b 556 * @}
<> 156:95d6b41a828b 557 */
<> 156:95d6b41a828b 558
<> 156:95d6b41a828b 559 #endif /* ADC1 */
<> 156:95d6b41a828b 560
<> 156:95d6b41a828b 561 /**
<> 156:95d6b41a828b 562 * @}
<> 156:95d6b41a828b 563 */
<> 156:95d6b41a828b 564
<> 156:95d6b41a828b 565 #endif /* USE_FULL_LL_DRIVER */
<> 156:95d6b41a828b 566
<> 156:95d6b41a828b 567 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/