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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_rcc_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of RCC HAL Extension module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_RCC_EX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_RCC_EX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup RCC
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup RCC_Private_Macros
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 59 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
<> 144:ef7eb2e8f9f7 60 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
<> 144:ef7eb2e8f9f7 61 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
<> 144:ef7eb2e8f9f7 62 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
<> 144:ef7eb2e8f9f7 63 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
<> 144:ef7eb2e8f9f7 64 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
<> 144:ef7eb2e8f9f7 65 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 68 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 69 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
<> 144:ef7eb2e8f9f7 70 ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
<> 144:ef7eb2e8f9f7 73 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
<> 144:ef7eb2e8f9f7 74 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
<> 144:ef7eb2e8f9f7 75 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 78 ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
<> 144:ef7eb2e8f9f7 79 ((SOURCE) == RCC_PLLSOURCE_HSE))
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #else
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
<> 144:ef7eb2e8f9f7 86 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
<> 144:ef7eb2e8f9f7 87 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
<> 144:ef7eb2e8f9f7 88 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
<> 144:ef7eb2e8f9f7 89 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
<> 144:ef7eb2e8f9f7 90 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
<> 144:ef7eb2e8f9f7 91 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 92 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 93 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
<> 144:ef7eb2e8f9f7 96 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
<> 144:ef7eb2e8f9f7 97 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
<> 144:ef7eb2e8f9f7 98 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 99 ((SOURCE) == RCC_PLLSOURCE_HSE))
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
<> 144:ef7eb2e8f9f7 106 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
<> 144:ef7eb2e8f9f7 107 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 108 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 109 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 110 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 111 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
<> 144:ef7eb2e8f9f7 112 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
<> 144:ef7eb2e8f9f7 113 ((SOURCE) == RCC_MCO1SOURCE_HSI14))
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 #elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48)
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
<> 144:ef7eb2e8f9f7 118 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
<> 144:ef7eb2e8f9f7 119 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 120 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 121 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 122 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 123 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
<> 144:ef7eb2e8f9f7 124 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
<> 144:ef7eb2e8f9f7 125 ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \
<> 144:ef7eb2e8f9f7 126 ((SOURCE) == RCC_MCO1SOURCE_HSI48))
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
<> 144:ef7eb2e8f9f7 131 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
<> 144:ef7eb2e8f9f7 132 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 133 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 134 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 135 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 136 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
<> 144:ef7eb2e8f9f7 137 ((SOURCE) == RCC_MCO1SOURCE_HSI14))
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @}
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** @addtogroup RCC_Exported_Constants
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** @addtogroup RCC_PLL_Clock_Source
<> 144:ef7eb2e8f9f7 151 * @{
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
<> 144:ef7eb2e8f9f7 154 #define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @}
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /** @addtogroup RCC_Interrupt
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 #define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 164 /**
<> 144:ef7eb2e8f9f7 165 * @}
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /** @addtogroup RCC_Flag
<> 144:ef7eb2e8f9f7 169 * @{
<> 144:ef7eb2e8f9f7 170 */
<> 156:95d6b41a828b 171 #define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI48RDY_BitNumber))
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @addtogroup RCC_System_Clock_Source
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179 #define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
<> 144:ef7eb2e8f9f7 180 /**
<> 144:ef7eb2e8f9f7 181 * @}
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /** @addtogroup RCC_System_Clock_Source_Status
<> 144:ef7eb2e8f9f7 185 * @{
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187 #define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @}
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #else
<> 144:ef7eb2e8f9f7 193 /** @addtogroup RCC_PLL_Clock_Source
<> 144:ef7eb2e8f9f7 194 * @{
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 #if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 198 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
<> 144:ef7eb2e8f9f7 199 #else
<> 144:ef7eb2e8f9f7 200 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
<> 144:ef7eb2e8f9f7 201 #endif
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @}
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /** @addtogroup RCC_MCO_Clock_Source
<> 144:ef7eb2e8f9f7 210 * @{
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 #if defined(RCC_CFGR_PLLNODIV)
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #endif /* RCC_CFGR_PLLNODIV */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 #if defined(RCC_CFGR_MCO_HSI48)
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #endif /* SRCC_CFGR_MCO_HSI48 */
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @}
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @}
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @}
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /** @addtogroup RCCEx
<> 144:ef7eb2e8f9f7 237 * @{
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Private Constants -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 241 #if defined(CRS)
<> 144:ef7eb2e8f9f7 242 /** @addtogroup RCCEx_Private_Constants
<> 144:ef7eb2e8f9f7 243 * @{
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* CRS IT Error Mask */
<> 144:ef7eb2e8f9f7 247 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* CRS Flag Error Mask */
<> 144:ef7eb2e8f9f7 250 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /**
<> 144:ef7eb2e8f9f7 253 * @}
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 #endif /* CRS */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 258 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
<> 144:ef7eb2e8f9f7 259 * @{
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 262 || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
<> 144:ef7eb2e8f9f7 265 RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 266 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
<> 144:ef7eb2e8f9f7 267 STM32F030xC */
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 #if defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
<> 144:ef7eb2e8f9f7 272 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
<> 144:ef7eb2e8f9f7 273 #endif /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 #if defined(STM32F042x6) || defined(STM32F048xx)
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
<> 144:ef7eb2e8f9f7 278 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
<> 144:ef7eb2e8f9f7 279 RCC_PERIPHCLK_USB))
<> 144:ef7eb2e8f9f7 280 #endif /* STM32F042x6 || STM32F048xx */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 #if defined(STM32F051x8) || defined(STM32F058xx)
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
<> 144:ef7eb2e8f9f7 285 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 286 #endif /* STM32F051x8 || STM32F058xx */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 #if defined(STM32F071xB)
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
<> 144:ef7eb2e8f9f7 291 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
<> 144:ef7eb2e8f9f7 292 RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 293 #endif /* STM32F071xB */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 #if defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
<> 144:ef7eb2e8f9f7 298 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
<> 144:ef7eb2e8f9f7 299 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
<> 144:ef7eb2e8f9f7 300 #endif /* STM32F072xB || STM32F078xx */
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
<> 144:ef7eb2e8f9f7 305 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
<> 144:ef7eb2e8f9f7 306 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
<> 144:ef7eb2e8f9f7 307 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
<> 144:ef7eb2e8f9f7 312 ((SOURCE) == RCC_USBCLKSOURCE_PLL))
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 #if defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \
<> 144:ef7eb2e8f9f7 319 ((SOURCE) == RCC_USBCLKSOURCE_PLL))
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 #endif /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 324 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 327 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 328 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 329 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 332 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 337 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 338 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 339 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 340 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 344 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 345 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 346 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 349 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
<> 144:ef7eb2e8f9f7 350 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 351 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 352 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 353 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 #if defined(RCC_CFGR_MCOPRE)
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
<> 144:ef7eb2e8f9f7 358 ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \
<> 144:ef7eb2e8f9f7 359 ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \
<> 144:ef7eb2e8f9f7 360 ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128))
<> 144:ef7eb2e8f9f7 361 #else
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 #endif /* RCC_CFGR_MCOPRE */
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
<> 144:ef7eb2e8f9f7 368 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
<> 144:ef7eb2e8f9f7 369 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
<> 144:ef7eb2e8f9f7 370 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 #if defined(CRS)
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
<> 144:ef7eb2e8f9f7 375 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 376 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
<> 144:ef7eb2e8f9f7 377 #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
<> 144:ef7eb2e8f9f7 378 ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
<> 144:ef7eb2e8f9f7 379 ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
<> 144:ef7eb2e8f9f7 380 ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
<> 144:ef7eb2e8f9f7 381 #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
<> 144:ef7eb2e8f9f7 382 ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
<> 156:95d6b41a828b 383 #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU))
<> 156:95d6b41a828b 384 #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU))
<> 156:95d6b41a828b 385 #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU))
<> 144:ef7eb2e8f9f7 386 #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
<> 144:ef7eb2e8f9f7 387 ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
<> 144:ef7eb2e8f9f7 388 #endif /* CRS */
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @}
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
<> 144:ef7eb2e8f9f7 396 * @{
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /**
<> 144:ef7eb2e8f9f7 400 * @brief RCC extended clocks structure definition
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 403 || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 404 typedef struct
<> 144:ef7eb2e8f9f7 405 {
<> 144:ef7eb2e8f9f7 406 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 407 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 410 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 413 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 416 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 419 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
<> 144:ef7eb2e8f9f7 420 STM32F030xC */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 #if defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 423 typedef struct
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 426 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 429 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 432 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 435 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 uint32_t UsbClockSelection; /*!< USB clock source
<> 144:ef7eb2e8f9f7 438 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 441 #endif /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 #if defined(STM32F042x6) || defined(STM32F048xx)
<> 144:ef7eb2e8f9f7 444 typedef struct
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 447 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 450 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 453 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 456 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 uint32_t CecClockSelection; /*!< HDMI CEC clock source
<> 144:ef7eb2e8f9f7 459 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 uint32_t UsbClockSelection; /*!< USB clock source
<> 144:ef7eb2e8f9f7 462 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 465 #endif /* STM32F042x6 || STM32F048xx */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 #if defined(STM32F051x8) || defined(STM32F058xx)
<> 144:ef7eb2e8f9f7 468 typedef struct
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 471 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 474 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 477 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 480 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 uint32_t CecClockSelection; /*!< HDMI CEC clock source
<> 144:ef7eb2e8f9f7 483 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 486 #endif /* STM32F051x8 || STM32F058xx */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 #if defined(STM32F071xB)
<> 144:ef7eb2e8f9f7 489 typedef struct
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 492 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 495 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 498 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 uint32_t Usart2ClockSelection; /*!< USART2 clock source
<> 144:ef7eb2e8f9f7 501 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 504 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 uint32_t CecClockSelection; /*!< HDMI CEC clock source
<> 144:ef7eb2e8f9f7 507 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 510 #endif /* STM32F071xB */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 #if defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 513 typedef struct
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 516 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 519 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 522 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 uint32_t Usart2ClockSelection; /*!< USART2 clock source
<> 144:ef7eb2e8f9f7 525 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 528 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 uint32_t CecClockSelection; /*!< HDMI CEC clock source
<> 144:ef7eb2e8f9f7 531 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 uint32_t UsbClockSelection; /*!< USB clock source
<> 144:ef7eb2e8f9f7 534 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 537 #endif /* STM32F072xB || STM32F078xx */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 541 typedef struct
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 544 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 547 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 550 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 uint32_t Usart2ClockSelection; /*!< USART2 clock source
<> 144:ef7eb2e8f9f7 553 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 uint32_t Usart3ClockSelection; /*!< USART3 clock source
<> 144:ef7eb2e8f9f7 556 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 559 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 uint32_t CecClockSelection; /*!< HDMI CEC clock source
<> 144:ef7eb2e8f9f7 562 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 565 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 #if defined(CRS)
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /**
<> 144:ef7eb2e8f9f7 570 * @brief RCC_CRS Init structure definition
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572 typedef struct
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
<> 144:ef7eb2e8f9f7 575 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 uint32_t Source; /*!< Specifies the SYNC signal source.
<> 144:ef7eb2e8f9f7 578 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
<> 144:ef7eb2e8f9f7 581 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
<> 144:ef7eb2e8f9f7 584 It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
<> 144:ef7eb2e8f9f7 585 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
<> 144:ef7eb2e8f9f7 588 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
<> 144:ef7eb2e8f9f7 591 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 }RCC_CRSInitTypeDef;
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /**
<> 144:ef7eb2e8f9f7 596 * @brief RCC_CRS Synchronization structure definition
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598 typedef struct
<> 144:ef7eb2e8f9f7 599 {
<> 144:ef7eb2e8f9f7 600 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
Anna Bridge 180:96ed750bd169 601 This parameter must be a number between 0 and 0xFFFFU */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
Anna Bridge 180:96ed750bd169 604 This parameter must be a number between 0 and 0x3FU */
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
<> 144:ef7eb2e8f9f7 607 value latched in the time of the last SYNC event.
Anna Bridge 180:96ed750bd169 608 This parameter must be a number between 0 and 0xFFFFU */
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
<> 144:ef7eb2e8f9f7 611 frequency error counter latched in the time of the last SYNC event.
<> 144:ef7eb2e8f9f7 612 It shows whether the actual frequency is below or above the target.
<> 144:ef7eb2e8f9f7 613 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 }RCC_CRSSynchroInfoTypeDef;
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 #endif /* CRS */
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /**
<> 144:ef7eb2e8f9f7 620 * @}
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
<> 144:ef7eb2e8f9f7 626 * @{
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
<> 144:ef7eb2e8f9f7 630 * @{
<> 144:ef7eb2e8f9f7 631 */
<> 144:ef7eb2e8f9f7 632 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 633 || defined(STM32F030xC)
<> 156:95d6b41a828b 634 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 156:95d6b41a828b 635 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 156:95d6b41a828b 636 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
<> 144:ef7eb2e8f9f7 639 STM32F030xC */
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 #if defined(STM32F070x6) || defined(STM32F070xB)
<> 156:95d6b41a828b 642 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 156:95d6b41a828b 643 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 156:95d6b41a828b 644 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 156:95d6b41a828b 645 #define RCC_PERIPHCLK_USB (0x00020000U)
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 #endif /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 #if defined(STM32F042x6) || defined(STM32F048xx)
<> 156:95d6b41a828b 650 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 156:95d6b41a828b 651 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 156:95d6b41a828b 652 #define RCC_PERIPHCLK_CEC (0x00000400U)
<> 156:95d6b41a828b 653 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 156:95d6b41a828b 654 #define RCC_PERIPHCLK_USB (0x00020000U)
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 #endif /* STM32F042x6 || STM32F048xx */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 #if defined(STM32F051x8) || defined(STM32F058xx)
<> 156:95d6b41a828b 659 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 156:95d6b41a828b 660 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 156:95d6b41a828b 661 #define RCC_PERIPHCLK_CEC (0x00000400U)
<> 156:95d6b41a828b 662 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 #endif /* STM32F051x8 || STM32F058xx */
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 #if defined(STM32F071xB)
<> 156:95d6b41a828b 667 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 156:95d6b41a828b 668 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 156:95d6b41a828b 669 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 156:95d6b41a828b 670 #define RCC_PERIPHCLK_CEC (0x00000400U)
<> 156:95d6b41a828b 671 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 #endif /* STM32F071xB */
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 #if defined(STM32F072xB) || defined(STM32F078xx)
<> 156:95d6b41a828b 676 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 156:95d6b41a828b 677 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 156:95d6b41a828b 678 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 156:95d6b41a828b 679 #define RCC_PERIPHCLK_CEC (0x00000400U)
<> 156:95d6b41a828b 680 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 156:95d6b41a828b 681 #define RCC_PERIPHCLK_USB (0x00020000U)
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 #endif /* STM32F072xB || STM32F078xx */
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 156:95d6b41a828b 686 #define RCC_PERIPHCLK_USART1 (0x00000001U)
<> 156:95d6b41a828b 687 #define RCC_PERIPHCLK_USART2 (0x00000002U)
<> 156:95d6b41a828b 688 #define RCC_PERIPHCLK_I2C1 (0x00000020U)
<> 156:95d6b41a828b 689 #define RCC_PERIPHCLK_CEC (0x00000400U)
<> 156:95d6b41a828b 690 #define RCC_PERIPHCLK_RTC (0x00010000U)
<> 156:95d6b41a828b 691 #define RCC_PERIPHCLK_USART3 (0x00040000U)
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /**
<> 144:ef7eb2e8f9f7 696 * @}
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
<> 144:ef7eb2e8f9f7 702 * @{
<> 144:ef7eb2e8f9f7 703 */
<> 144:ef7eb2e8f9f7 704 #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */
<> 144:ef7eb2e8f9f7 705 #define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /**
<> 144:ef7eb2e8f9f7 708 * @}
<> 144:ef7eb2e8f9f7 709 */
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 #if defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
<> 144:ef7eb2e8f9f7 716 * @{
<> 144:ef7eb2e8f9f7 717 */
<> 156:95d6b41a828b 718 #define RCC_USBCLKSOURCE_NONE (0x00000000U) /*!< USB clock disabled */
<> 144:ef7eb2e8f9f7 719 #define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /**
<> 144:ef7eb2e8f9f7 722 * @}
<> 144:ef7eb2e8f9f7 723 */
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 #endif /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 728 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
<> 144:ef7eb2e8f9f7 731 * @{
<> 144:ef7eb2e8f9f7 732 */
<> 144:ef7eb2e8f9f7 733 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
<> 144:ef7eb2e8f9f7 734 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
<> 144:ef7eb2e8f9f7 735 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
<> 144:ef7eb2e8f9f7 736 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /**
<> 144:ef7eb2e8f9f7 739 * @}
<> 144:ef7eb2e8f9f7 740 */
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 743 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
<> 144:ef7eb2e8f9f7 748 * @{
<> 144:ef7eb2e8f9f7 749 */
<> 144:ef7eb2e8f9f7 750 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
<> 144:ef7eb2e8f9f7 751 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
<> 144:ef7eb2e8f9f7 752 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
<> 144:ef7eb2e8f9f7 753 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /**
<> 144:ef7eb2e8f9f7 756 * @}
<> 144:ef7eb2e8f9f7 757 */
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 763 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 764 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 765 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
<> 144:ef7eb2e8f9f7 768 * @{
<> 144:ef7eb2e8f9f7 769 */
<> 144:ef7eb2e8f9f7 770 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
<> 144:ef7eb2e8f9f7 771 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /**
<> 144:ef7eb2e8f9f7 774 * @}
<> 144:ef7eb2e8f9f7 775 */
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 778 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 779 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 780 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
<> 144:ef7eb2e8f9f7 783 * @{
<> 144:ef7eb2e8f9f7 784 */
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 #if defined(RCC_CFGR_MCOPRE)
<> 144:ef7eb2e8f9f7 787
<> 156:95d6b41a828b 788 #define RCC_MCODIV_1 (0x00000000U)
<> 156:95d6b41a828b 789 #define RCC_MCODIV_2 (0x10000000U)
<> 156:95d6b41a828b 790 #define RCC_MCODIV_4 (0x20000000U)
<> 156:95d6b41a828b 791 #define RCC_MCODIV_8 (0x30000000U)
<> 156:95d6b41a828b 792 #define RCC_MCODIV_16 (0x40000000U)
<> 156:95d6b41a828b 793 #define RCC_MCODIV_32 (0x50000000U)
<> 156:95d6b41a828b 794 #define RCC_MCODIV_64 (0x60000000U)
<> 156:95d6b41a828b 795 #define RCC_MCODIV_128 (0x70000000U)
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 #else
<> 144:ef7eb2e8f9f7 798
<> 156:95d6b41a828b 799 #define RCC_MCODIV_1 (0x00000000U)
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 #endif /* RCC_CFGR_MCOPRE */
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /**
<> 144:ef7eb2e8f9f7 804 * @}
<> 144:ef7eb2e8f9f7 805 */
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
<> 144:ef7eb2e8f9f7 808 * @{
<> 144:ef7eb2e8f9f7 809 */
<> 144:ef7eb2e8f9f7 810
<> 156:95d6b41a828b 811 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */
<> 144:ef7eb2e8f9f7 812 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
<> 144:ef7eb2e8f9f7 813 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
<> 144:ef7eb2e8f9f7 814 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /**
<> 144:ef7eb2e8f9f7 817 * @}
<> 144:ef7eb2e8f9f7 818 */
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 #if defined(CRS)
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
<> 144:ef7eb2e8f9f7 823 * @{
<> 144:ef7eb2e8f9f7 824 */
<> 156:95d6b41a828b 825 #define RCC_CRS_NONE (0x00000000U)
<> 156:95d6b41a828b 826 #define RCC_CRS_TIMEOUT (0x00000001U)
<> 156:95d6b41a828b 827 #define RCC_CRS_SYNCOK (0x00000002U)
<> 156:95d6b41a828b 828 #define RCC_CRS_SYNCWARN (0x00000004U)
<> 156:95d6b41a828b 829 #define RCC_CRS_SYNCERR (0x00000008U)
<> 156:95d6b41a828b 830 #define RCC_CRS_SYNCMISS (0x00000010U)
<> 156:95d6b41a828b 831 #define RCC_CRS_TRIMOVF (0x00000020U)
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /**
<> 144:ef7eb2e8f9f7 834 * @}
<> 144:ef7eb2e8f9f7 835 */
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
<> 144:ef7eb2e8f9f7 838 * @{
<> 144:ef7eb2e8f9f7 839 */
Anna Bridge 180:96ed750bd169 840 #define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */
<> 144:ef7eb2e8f9f7 841 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
<> 144:ef7eb2e8f9f7 842 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
<> 144:ef7eb2e8f9f7 843 /**
<> 144:ef7eb2e8f9f7 844 * @}
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
<> 144:ef7eb2e8f9f7 848 * @{
<> 144:ef7eb2e8f9f7 849 */
Anna Bridge 180:96ed750bd169 850 #define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */
<> 144:ef7eb2e8f9f7 851 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
<> 144:ef7eb2e8f9f7 852 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
<> 144:ef7eb2e8f9f7 853 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
<> 144:ef7eb2e8f9f7 854 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
<> 144:ef7eb2e8f9f7 855 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
<> 144:ef7eb2e8f9f7 856 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
<> 144:ef7eb2e8f9f7 857 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
<> 144:ef7eb2e8f9f7 858 /**
<> 144:ef7eb2e8f9f7 859 * @}
<> 144:ef7eb2e8f9f7 860 */
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
<> 144:ef7eb2e8f9f7 863 * @{
<> 144:ef7eb2e8f9f7 864 */
Anna Bridge 180:96ed750bd169 865 #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */
<> 144:ef7eb2e8f9f7 866 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
<> 144:ef7eb2e8f9f7 867 /**
<> 144:ef7eb2e8f9f7 868 * @}
<> 144:ef7eb2e8f9f7 869 */
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
<> 144:ef7eb2e8f9f7 872 * @{
<> 144:ef7eb2e8f9f7 873 */
Anna Bridge 180:96ed750bd169 874 #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
<> 144:ef7eb2e8f9f7 875 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
<> 144:ef7eb2e8f9f7 876 /**
<> 144:ef7eb2e8f9f7 877 * @}
<> 144:ef7eb2e8f9f7 878 */
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
<> 144:ef7eb2e8f9f7 881 * @{
<> 144:ef7eb2e8f9f7 882 */
Anna Bridge 180:96ed750bd169 883 #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */
<> 144:ef7eb2e8f9f7 884 /**
<> 144:ef7eb2e8f9f7 885 * @}
<> 144:ef7eb2e8f9f7 886 */
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
<> 144:ef7eb2e8f9f7 889 * @{
<> 144:ef7eb2e8f9f7 890 */
Anna Bridge 180:96ed750bd169 891 #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
<> 144:ef7eb2e8f9f7 892 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
<> 144:ef7eb2e8f9f7 893 corresponds to a higher output frequency */
<> 144:ef7eb2e8f9f7 894 /**
<> 144:ef7eb2e8f9f7 895 * @}
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
<> 144:ef7eb2e8f9f7 899 * @{
<> 144:ef7eb2e8f9f7 900 */
Anna Bridge 180:96ed750bd169 901 #define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */
<> 144:ef7eb2e8f9f7 902 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
<> 144:ef7eb2e8f9f7 903 /**
<> 144:ef7eb2e8f9f7 904 * @}
<> 144:ef7eb2e8f9f7 905 */
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
<> 144:ef7eb2e8f9f7 908 * @{
<> 144:ef7eb2e8f9f7 909 */
<> 144:ef7eb2e8f9f7 910 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
<> 144:ef7eb2e8f9f7 911 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
<> 144:ef7eb2e8f9f7 912 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
<> 144:ef7eb2e8f9f7 913 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
<> 144:ef7eb2e8f9f7 914 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
<> 144:ef7eb2e8f9f7 915 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
<> 144:ef7eb2e8f9f7 916 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /**
<> 144:ef7eb2e8f9f7 919 * @}
<> 144:ef7eb2e8f9f7 920 */
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
<> 144:ef7eb2e8f9f7 923 * @{
<> 144:ef7eb2e8f9f7 924 */
<> 144:ef7eb2e8f9f7 925 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
<> 144:ef7eb2e8f9f7 926 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
<> 144:ef7eb2e8f9f7 927 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
<> 144:ef7eb2e8f9f7 928 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
<> 144:ef7eb2e8f9f7 929 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
<> 144:ef7eb2e8f9f7 930 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
<> 144:ef7eb2e8f9f7 931 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /**
<> 144:ef7eb2e8f9f7 934 * @}
<> 144:ef7eb2e8f9f7 935 */
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 #endif /* CRS */
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /**
<> 144:ef7eb2e8f9f7 940 * @}
<> 144:ef7eb2e8f9f7 941 */
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /* Exported macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 944 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
<> 144:ef7eb2e8f9f7 945 * @{
<> 144:ef7eb2e8f9f7 946 */
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
<> 144:ef7eb2e8f9f7 949 * @brief Enables or disables the AHB1 peripheral clock.
<> 144:ef7eb2e8f9f7 950 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 951 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 952 * using it.
<> 144:ef7eb2e8f9f7 953 * @{
<> 144:ef7eb2e8f9f7 954 */
<> 144:ef7eb2e8f9f7 955 #if defined(GPIOD)
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 958 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 959 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
<> 144:ef7eb2e8f9f7 960 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 961 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
<> 144:ef7eb2e8f9f7 962 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 963 } while(0U)
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 #endif /* GPIOD */
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 #if defined(GPIOE)
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 972 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 973 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
<> 144:ef7eb2e8f9f7 974 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 975 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
<> 144:ef7eb2e8f9f7 976 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 977 } while(0U)
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 #endif /* GPIOE */
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 984 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 985 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 986 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 #define __HAL_RCC_TSC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 989 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 990 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
<> 144:ef7eb2e8f9f7 991 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 992 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
<> 144:ef7eb2e8f9f7 993 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 994 } while(0U)
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 999 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1000 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1001 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1006 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1007 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
<> 144:ef7eb2e8f9f7 1008 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1009 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
<> 144:ef7eb2e8f9f7 1010 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1011 } while(0U)
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<> 144:ef7eb2e8f9f7 1018 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1019 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1020 * using it.
<> 144:ef7eb2e8f9f7 1021 */
<> 144:ef7eb2e8f9f7 1022 #if defined(STM32F030x8)\
<> 144:ef7eb2e8f9f7 1023 || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1024 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1025 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1026 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1029 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1030 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<> 144:ef7eb2e8f9f7 1031 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1032 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<> 144:ef7eb2e8f9f7 1033 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1034 } while(0U)
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1039 /* STM32F051x8 || STM32F058xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1040 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1041 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 #if defined(STM32F030x8)\
<> 144:ef7eb2e8f9f7 1044 || defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1045 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1046 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1047 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1050 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1051 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<> 144:ef7eb2e8f9f7 1052 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1053 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<> 144:ef7eb2e8f9f7 1054 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1055 } while(0U)
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1060 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1061 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1062 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1063
<> 144:ef7eb2e8f9f7 1064 #if defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 1065 || defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1066 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1067 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1068 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1071 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1072 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<> 144:ef7eb2e8f9f7 1073 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1074 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<> 144:ef7eb2e8f9f7 1075 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1076 } while(0U)
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 #endif /* STM32F031x6 || STM32F038xx || */
<> 144:ef7eb2e8f9f7 1081 /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1082 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1083 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1084 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 #if defined(STM32F030x8) \
<> 144:ef7eb2e8f9f7 1087 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1088 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1089 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1092 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1093 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 144:ef7eb2e8f9f7 1094 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1095 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 144:ef7eb2e8f9f7 1096 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1097 } while(0U)
<> 144:ef7eb2e8f9f7 1098 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1099 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1100 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<> 144:ef7eb2e8f9f7 1101 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1102 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<> 144:ef7eb2e8f9f7 1103 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1104 } while(0U)
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
<> 144:ef7eb2e8f9f7 1107 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 #endif /* STM32F030x8 || */
<> 144:ef7eb2e8f9f7 1110 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1111 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1112 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 #if defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1115 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1116 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1119 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1120 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 144:ef7eb2e8f9f7 1121 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1122 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 144:ef7eb2e8f9f7 1123 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1124 } while(0U)
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 #endif /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1129 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1130 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1131
<> 144:ef7eb2e8f9f7 1132 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1133 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1134 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1135 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1138 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1139 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<> 144:ef7eb2e8f9f7 1140 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1141 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<> 144:ef7eb2e8f9f7 1142 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1143 } while(0U)
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1148 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1149 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1150 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1153 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1156 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1157 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 144:ef7eb2e8f9f7 1158 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1159 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 144:ef7eb2e8f9f7 1160 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1161 } while(0U)
<> 144:ef7eb2e8f9f7 1162 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1163 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1164 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<> 144:ef7eb2e8f9f7 1165 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1166 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<> 144:ef7eb2e8f9f7 1167 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1168 } while(0U)
<> 144:ef7eb2e8f9f7 1169 #define __HAL_RCC_USART4_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1170 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1171 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
<> 144:ef7eb2e8f9f7 1172 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1173 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
<> 144:ef7eb2e8f9f7 1174 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1175 } while(0U)
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
<> 144:ef7eb2e8f9f7 1178 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
<> 144:ef7eb2e8f9f7 1179 #define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1182 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1185 || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 #define __HAL_RCC_USB_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1188 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1189 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
<> 144:ef7eb2e8f9f7 1190 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1191 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
<> 144:ef7eb2e8f9f7 1192 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1193 } while(0U)
<> 144:ef7eb2e8f9f7 1194
<> 144:ef7eb2e8f9f7 1195 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1198 /* STM32F072xB || STM32F078xx || STM32F070xB */
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
<> 144:ef7eb2e8f9f7 1201 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1204 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1205 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
<> 144:ef7eb2e8f9f7 1206 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1207 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
<> 144:ef7eb2e8f9f7 1208 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1209 } while(0U)
<> 144:ef7eb2e8f9f7 1210 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
<> 144:ef7eb2e8f9f7 1213 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 #if defined(CRS)
<> 144:ef7eb2e8f9f7 1216
<> 144:ef7eb2e8f9f7 1217 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1218 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1219 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
<> 144:ef7eb2e8f9f7 1220 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1221 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
<> 144:ef7eb2e8f9f7 1222 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1223 } while(0U)
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 #endif /* CRS */
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 #define __HAL_RCC_USART5_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1232 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1233 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
<> 144:ef7eb2e8f9f7 1234 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1235 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
<> 144:ef7eb2e8f9f7 1236 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1237 } while(0U)
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 #define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<> 144:ef7eb2e8f9f7 1244 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1245 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1246 * using it.
<> 144:ef7eb2e8f9f7 1247 */
<> 144:ef7eb2e8f9f7 1248 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1249 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1250 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1251 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1254 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1255 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
<> 144:ef7eb2e8f9f7 1256 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1257 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
<> 144:ef7eb2e8f9f7 1258 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1259 } while(0U)
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1264 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1265 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1266 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1271 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1272 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<> 144:ef7eb2e8f9f7 1273 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1274 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<> 144:ef7eb2e8f9f7 1275 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1276 } while(0U)
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 #define __HAL_RCC_USART7_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1285 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1286 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
<> 144:ef7eb2e8f9f7 1287 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1288 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
<> 144:ef7eb2e8f9f7 1289 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1290 } while(0U)
<> 144:ef7eb2e8f9f7 1291 #define __HAL_RCC_USART8_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1292 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1293 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
<> 144:ef7eb2e8f9f7 1294 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1295 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
<> 144:ef7eb2e8f9f7 1296 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 1297 } while(0U)
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 #define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
<> 144:ef7eb2e8f9f7 1300 #define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 /**
<> 144:ef7eb2e8f9f7 1305 * @}
<> 144:ef7eb2e8f9f7 1306 */
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
<> 144:ef7eb2e8f9f7 1310 * @brief Forces or releases peripheral reset.
<> 144:ef7eb2e8f9f7 1311 * @{
<> 144:ef7eb2e8f9f7 1312 */
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 /** @brief Force or release AHB peripheral reset.
<> 144:ef7eb2e8f9f7 1315 */
<> 144:ef7eb2e8f9f7 1316 #if defined(GPIOD)
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 #endif /* GPIOD */
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 #if defined(GPIOE)
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 #endif /* GPIOE */
<> 144:ef7eb2e8f9f7 1331
<> 144:ef7eb2e8f9f7 1332 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1333 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1334 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1335 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1342 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1343 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1344 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /** @brief Force or release APB1 peripheral reset.
<> 144:ef7eb2e8f9f7 1347 */
<> 144:ef7eb2e8f9f7 1348 #if defined(STM32F030x8) \
<> 144:ef7eb2e8f9f7 1349 || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1350 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1351 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1352 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1353
<> 144:ef7eb2e8f9f7 1354 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
<> 144:ef7eb2e8f9f7 1355 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
<> 144:ef7eb2e8f9f7 1356
<> 144:ef7eb2e8f9f7 1357 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
<> 144:ef7eb2e8f9f7 1358 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<> 144:ef7eb2e8f9f7 1359
<> 144:ef7eb2e8f9f7 1360 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1361 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1362 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1363 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1364
<> 144:ef7eb2e8f9f7 1365 #if defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 1366 || defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1367 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1368 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1369 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1370
<> 144:ef7eb2e8f9f7 1371 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 #endif /* STM32F031x6 || STM32F038xx || */
<> 144:ef7eb2e8f9f7 1376 /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1377 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1378 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1379 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 #if defined(STM32F030x8) \
<> 144:ef7eb2e8f9f7 1382 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1383 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1384 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
<> 144:ef7eb2e8f9f7 1387 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
<> 144:ef7eb2e8f9f7 1390 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<> 144:ef7eb2e8f9f7 1391
<> 144:ef7eb2e8f9f7 1392 #endif /* STM32F030x8 || */
<> 144:ef7eb2e8f9f7 1393 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1394 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1395 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 #if defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1398 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1399 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1400
<> 144:ef7eb2e8f9f7 1401 #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 #define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405 #endif /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1406 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1407 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1410 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1411 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1412 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1419 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1420 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1421 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1422
<> 144:ef7eb2e8f9f7 1423 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1424 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1425
<> 144:ef7eb2e8f9f7 1426 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
<> 144:ef7eb2e8f9f7 1427 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
<> 144:ef7eb2e8f9f7 1428 #define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
<> 144:ef7eb2e8f9f7 1429
<> 144:ef7eb2e8f9f7 1430 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
<> 144:ef7eb2e8f9f7 1431 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
<> 144:ef7eb2e8f9f7 1432 #define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
<> 144:ef7eb2e8f9f7 1433
<> 144:ef7eb2e8f9f7 1434 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1435 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1438 || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
<> 144:ef7eb2e8f9f7 1441
<> 144:ef7eb2e8f9f7 1442 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1445 /* STM32F072xB || STM32F078xx || STM32F070xB */
<> 144:ef7eb2e8f9f7 1446
<> 144:ef7eb2e8f9f7 1447 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
<> 144:ef7eb2e8f9f7 1448 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1449
<> 144:ef7eb2e8f9f7 1450 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
<> 144:ef7eb2e8f9f7 1455 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 #if defined(CRS)
<> 144:ef7eb2e8f9f7 1458
<> 144:ef7eb2e8f9f7 1459 #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
<> 144:ef7eb2e8f9f7 1460
<> 144:ef7eb2e8f9f7 1461 #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
<> 144:ef7eb2e8f9f7 1462
<> 144:ef7eb2e8f9f7 1463 #endif /* CRS */
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 #define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
<> 144:ef7eb2e8f9f7 1468
<> 144:ef7eb2e8f9f7 1469 #define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473
<> 144:ef7eb2e8f9f7 1474 /** @brief Force or release APB2 peripheral reset.
<> 144:ef7eb2e8f9f7 1475 */
<> 144:ef7eb2e8f9f7 1476 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1477 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1478 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1479 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
<> 144:ef7eb2e8f9f7 1482
<> 144:ef7eb2e8f9f7 1483 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1486 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1487 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1488 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1489
<> 144:ef7eb2e8f9f7 1490 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1491
<> 144:ef7eb2e8f9f7 1492 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
<> 144:ef7eb2e8f9f7 1493
<> 144:ef7eb2e8f9f7 1494 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
<> 144:ef7eb2e8f9f7 1495
<> 144:ef7eb2e8f9f7 1496 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1497
<> 144:ef7eb2e8f9f7 1498 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 #define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
<> 144:ef7eb2e8f9f7 1501 #define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
<> 144:ef7eb2e8f9f7 1502
<> 144:ef7eb2e8f9f7 1503 #define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
<> 144:ef7eb2e8f9f7 1504 #define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
<> 144:ef7eb2e8f9f7 1505
<> 144:ef7eb2e8f9f7 1506 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 /**
<> 144:ef7eb2e8f9f7 1509 * @}
<> 144:ef7eb2e8f9f7 1510 */
<> 144:ef7eb2e8f9f7 1511
<> 144:ef7eb2e8f9f7 1512 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1513 * @brief Get the enable or disable status of peripheral clock.
<> 144:ef7eb2e8f9f7 1514 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1515 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1516 * using it.
<> 144:ef7eb2e8f9f7 1517 * @{
<> 144:ef7eb2e8f9f7 1518 */
<> 144:ef7eb2e8f9f7 1519 /** @brief AHB Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1520 */
<> 144:ef7eb2e8f9f7 1521 #if defined(GPIOD)
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
<> 144:ef7eb2e8f9f7 1524 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
<> 144:ef7eb2e8f9f7 1525
<> 144:ef7eb2e8f9f7 1526 #endif /* GPIOD */
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 #if defined(GPIOE)
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
<> 144:ef7eb2e8f9f7 1531 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
<> 144:ef7eb2e8f9f7 1532
<> 144:ef7eb2e8f9f7 1533 #endif /* GPIOE */
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1536 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1537 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1538 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1539
<> 144:ef7eb2e8f9f7 1540 #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
<> 144:ef7eb2e8f9f7 1541 #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1544 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1545 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1546 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1551 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1554
<> 144:ef7eb2e8f9f7 1555 /** @brief APB1 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1556 */
<> 144:ef7eb2e8f9f7 1557 #if defined(STM32F030x8)\
<> 144:ef7eb2e8f9f7 1558 || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1559 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1560 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1561 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1564 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1567 /* STM32F051x8 || STM32F058xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1568 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1569 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1570
<> 144:ef7eb2e8f9f7 1571 #if defined(STM32F030x8)\
<> 144:ef7eb2e8f9f7 1572 || defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1573 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1574 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1575 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1576
<> 144:ef7eb2e8f9f7 1577 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1578 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1581 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1582 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1583 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1584
<> 144:ef7eb2e8f9f7 1585 #if defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 1586 || defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1587 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1588 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1589 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1592 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 #endif /* STM32F031x6 || STM32F038xx || */
<> 144:ef7eb2e8f9f7 1595 /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1596 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1597 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1598 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1599
<> 144:ef7eb2e8f9f7 1600 #if defined(STM32F030x8) \
<> 144:ef7eb2e8f9f7 1601 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1602 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1603 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1604
<> 144:ef7eb2e8f9f7 1605 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
<> 144:ef7eb2e8f9f7 1606 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1607 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
<> 144:ef7eb2e8f9f7 1608 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 #endif /* STM32F030x8 || */
<> 144:ef7eb2e8f9f7 1611 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1612 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1613 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1614
<> 144:ef7eb2e8f9f7 1615 #if defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1616 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1617 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1618
<> 144:ef7eb2e8f9f7 1619 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1620 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1621
<> 144:ef7eb2e8f9f7 1622 #endif /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1623 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1624 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1625
<> 144:ef7eb2e8f9f7 1626 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1627 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1628 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1629 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1630
<> 144:ef7eb2e8f9f7 1631 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
<> 144:ef7eb2e8f9f7 1632 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
<> 144:ef7eb2e8f9f7 1633
<> 144:ef7eb2e8f9f7 1634 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1635 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1636 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1637 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1638
<> 144:ef7eb2e8f9f7 1639 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1640 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
<> 144:ef7eb2e8f9f7 1643 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1644 #define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
<> 144:ef7eb2e8f9f7 1645 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
<> 144:ef7eb2e8f9f7 1646 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1647 #define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
<> 144:ef7eb2e8f9f7 1648
<> 144:ef7eb2e8f9f7 1649 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1650 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1653 || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
<> 144:ef7eb2e8f9f7 1656 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
<> 144:ef7eb2e8f9f7 1657
<> 144:ef7eb2e8f9f7 1658 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1659 /* STM32F072xB || STM32F078xx || STM32F070xB */
<> 144:ef7eb2e8f9f7 1660
<> 144:ef7eb2e8f9f7 1661 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
<> 144:ef7eb2e8f9f7 1662 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1663
<> 144:ef7eb2e8f9f7 1664 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1665 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1666
<> 144:ef7eb2e8f9f7 1667 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
<> 144:ef7eb2e8f9f7 1668 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1669
<> 144:ef7eb2e8f9f7 1670 #if defined(CRS)
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672 #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
<> 144:ef7eb2e8f9f7 1673 #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
<> 144:ef7eb2e8f9f7 1674
<> 144:ef7eb2e8f9f7 1675 #endif /* CRS */
<> 144:ef7eb2e8f9f7 1676
<> 144:ef7eb2e8f9f7 1677 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 #define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
<> 144:ef7eb2e8f9f7 1680 #define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
<> 144:ef7eb2e8f9f7 1681
<> 144:ef7eb2e8f9f7 1682 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1683
<> 144:ef7eb2e8f9f7 1684 /** @brief APB1 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1685 */
<> 144:ef7eb2e8f9f7 1686 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1687 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1688 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1689 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1690
<> 144:ef7eb2e8f9f7 1691 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
<> 144:ef7eb2e8f9f7 1692 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
<> 144:ef7eb2e8f9f7 1693
<> 144:ef7eb2e8f9f7 1694 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1695 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1696 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1697 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1698
<> 144:ef7eb2e8f9f7 1699 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1700
<> 144:ef7eb2e8f9f7 1701 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
<> 144:ef7eb2e8f9f7 1702 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
<> 144:ef7eb2e8f9f7 1703
<> 144:ef7eb2e8f9f7 1704 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1705
<> 144:ef7eb2e8f9f7 1706 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 #define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
<> 144:ef7eb2e8f9f7 1709 #define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
<> 144:ef7eb2e8f9f7 1710 #define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
<> 144:ef7eb2e8f9f7 1711 #define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
<> 144:ef7eb2e8f9f7 1712
<> 144:ef7eb2e8f9f7 1713 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1714 /**
<> 144:ef7eb2e8f9f7 1715 * @}
<> 144:ef7eb2e8f9f7 1716 */
<> 144:ef7eb2e8f9f7 1717
<> 144:ef7eb2e8f9f7 1718
<> 144:ef7eb2e8f9f7 1719 /** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
<> 144:ef7eb2e8f9f7 1720 * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
<> 144:ef7eb2e8f9f7 1721 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 1722 * @note HSI48 can not be stopped if it is used as system clock source. In this case,
<> 144:ef7eb2e8f9f7 1723 * you have to select another source of the system clock then stop the HSI14.
<> 144:ef7eb2e8f9f7 1724 * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
<> 144:ef7eb2e8f9f7 1725 * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
<> 144:ef7eb2e8f9f7 1726 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
<> 144:ef7eb2e8f9f7 1727 * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
<> 144:ef7eb2e8f9f7 1728 * clock cycles.
<> 144:ef7eb2e8f9f7 1729 * @{
<> 144:ef7eb2e8f9f7 1730 */
<> 144:ef7eb2e8f9f7 1731 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 1732
<> 144:ef7eb2e8f9f7 1733 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
<> 144:ef7eb2e8f9f7 1734 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
<> 144:ef7eb2e8f9f7 1735
<> 144:ef7eb2e8f9f7 1736 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
<> 144:ef7eb2e8f9f7 1737 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1738 * @arg @ref RCC_HSI48_ON HSI48 enabled
<> 144:ef7eb2e8f9f7 1739 * @arg @ref RCC_HSI48_OFF HSI48 disabled
<> 144:ef7eb2e8f9f7 1740 */
<> 144:ef7eb2e8f9f7 1741 #define __HAL_RCC_GET_HSI48_STATE() \
<> 144:ef7eb2e8f9f7 1742 (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
<> 144:ef7eb2e8f9f7 1743
<> 144:ef7eb2e8f9f7 1744 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 1745
<> 144:ef7eb2e8f9f7 1746 /**
<> 144:ef7eb2e8f9f7 1747 * @}
<> 144:ef7eb2e8f9f7 1748 */
<> 144:ef7eb2e8f9f7 1749
<> 144:ef7eb2e8f9f7 1750 /** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
<> 144:ef7eb2e8f9f7 1751 * @{
<> 144:ef7eb2e8f9f7 1752 */
<> 144:ef7eb2e8f9f7 1753 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1754 || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1755 || defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 1756
<> 144:ef7eb2e8f9f7 1757 /** @brief Macro to configure the USB clock (USBCLK).
<> 144:ef7eb2e8f9f7 1758 * @param __USBCLKSOURCE__ specifies the USB clock source.
<> 144:ef7eb2e8f9f7 1759 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1760 @if STM32F070xB
<> 144:ef7eb2e8f9f7 1761 @elseif STM32F070x6
<> 144:ef7eb2e8f9f7 1762 @else
<> 144:ef7eb2e8f9f7 1763 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
<> 144:ef7eb2e8f9f7 1764 @endif
<> 144:ef7eb2e8f9f7 1765 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
<> 144:ef7eb2e8f9f7 1766 */
<> 144:ef7eb2e8f9f7 1767 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1768 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__))
<> 144:ef7eb2e8f9f7 1769
<> 144:ef7eb2e8f9f7 1770 /** @brief Macro to get the USB clock source.
<> 144:ef7eb2e8f9f7 1771 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1772 @if STM32F070xB
<> 144:ef7eb2e8f9f7 1773 @elseif STM32F070x6
<> 144:ef7eb2e8f9f7 1774 @else
<> 144:ef7eb2e8f9f7 1775 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
<> 144:ef7eb2e8f9f7 1776 @endif
<> 144:ef7eb2e8f9f7 1777 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
<> 144:ef7eb2e8f9f7 1778 */
<> 144:ef7eb2e8f9f7 1779 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
<> 144:ef7eb2e8f9f7 1780
<> 144:ef7eb2e8f9f7 1781 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1782 /* STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1783 /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1786 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1787 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1788 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1789
<> 144:ef7eb2e8f9f7 1790 /** @brief Macro to configure the CEC clock.
<> 144:ef7eb2e8f9f7 1791 * @param __CECCLKSOURCE__ specifies the CEC clock source.
<> 144:ef7eb2e8f9f7 1792 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1793 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
<> 144:ef7eb2e8f9f7 1794 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
<> 144:ef7eb2e8f9f7 1795 */
<> 144:ef7eb2e8f9f7 1796 #define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1797 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__))
<> 144:ef7eb2e8f9f7 1798
<> 144:ef7eb2e8f9f7 1799 /** @brief Macro to get the HDMI CEC clock source.
<> 144:ef7eb2e8f9f7 1800 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1801 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
<> 144:ef7eb2e8f9f7 1802 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
<> 144:ef7eb2e8f9f7 1803 */
<> 144:ef7eb2e8f9f7 1804 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
<> 144:ef7eb2e8f9f7 1805
<> 144:ef7eb2e8f9f7 1806 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1807 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1808 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1809 /* STM32F091xC || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 1810
<> 144:ef7eb2e8f9f7 1811 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1812 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1813 /** @brief Macro to configure the USART2 clock (USART2CLK).
<> 144:ef7eb2e8f9f7 1814 * @param __USART2CLKSOURCE__ specifies the USART2 clock source.
<> 144:ef7eb2e8f9f7 1815 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1816 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
<> 144:ef7eb2e8f9f7 1817 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
<> 144:ef7eb2e8f9f7 1818 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
<> 144:ef7eb2e8f9f7 1819 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
<> 144:ef7eb2e8f9f7 1820 */
<> 144:ef7eb2e8f9f7 1821 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1822 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
<> 144:ef7eb2e8f9f7 1823
<> 144:ef7eb2e8f9f7 1824 /** @brief Macro to get the USART2 clock source.
<> 144:ef7eb2e8f9f7 1825 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1826 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
<> 144:ef7eb2e8f9f7 1827 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
<> 144:ef7eb2e8f9f7 1828 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
<> 144:ef7eb2e8f9f7 1829 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
<> 144:ef7eb2e8f9f7 1830 */
<> 144:ef7eb2e8f9f7 1831 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
<> 144:ef7eb2e8f9f7 1832 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/
<> 144:ef7eb2e8f9f7 1833
<> 144:ef7eb2e8f9f7 1834 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1835 /** @brief Macro to configure the USART3 clock (USART3CLK).
<> 144:ef7eb2e8f9f7 1836 * @param __USART3CLKSOURCE__ specifies the USART3 clock source.
<> 144:ef7eb2e8f9f7 1837 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1838 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
<> 144:ef7eb2e8f9f7 1839 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
<> 144:ef7eb2e8f9f7 1840 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
<> 144:ef7eb2e8f9f7 1841 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
<> 144:ef7eb2e8f9f7 1842 */
<> 144:ef7eb2e8f9f7 1843 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1844 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
<> 144:ef7eb2e8f9f7 1845
<> 144:ef7eb2e8f9f7 1846 /** @brief Macro to get the USART3 clock source.
<> 144:ef7eb2e8f9f7 1847 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1848 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
<> 144:ef7eb2e8f9f7 1849 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
<> 144:ef7eb2e8f9f7 1850 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
<> 144:ef7eb2e8f9f7 1851 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
<> 144:ef7eb2e8f9f7 1852 */
<> 144:ef7eb2e8f9f7 1853 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
<> 144:ef7eb2e8f9f7 1854
<> 144:ef7eb2e8f9f7 1855 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1856 /**
<> 144:ef7eb2e8f9f7 1857 * @}
<> 144:ef7eb2e8f9f7 1858 */
<> 144:ef7eb2e8f9f7 1859
<> 144:ef7eb2e8f9f7 1860 /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
<> 144:ef7eb2e8f9f7 1861 * @{
<> 144:ef7eb2e8f9f7 1862 */
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 /**
<> 144:ef7eb2e8f9f7 1865 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
<> 144:ef7eb2e8f9f7 1866 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
<> 144:ef7eb2e8f9f7 1867 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1868 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
<> 144:ef7eb2e8f9f7 1869 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
<> 144:ef7eb2e8f9f7 1870 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
<> 144:ef7eb2e8f9f7 1871 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
<> 144:ef7eb2e8f9f7 1872 * @retval None
<> 144:ef7eb2e8f9f7 1873 */
<> 144:ef7eb2e8f9f7 1874 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
<> 144:ef7eb2e8f9f7 1875 RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
<> 144:ef7eb2e8f9f7 1876
<> 144:ef7eb2e8f9f7 1877 /**
<> 144:ef7eb2e8f9f7 1878 * @}
<> 144:ef7eb2e8f9f7 1879 */
<> 144:ef7eb2e8f9f7 1880
<> 144:ef7eb2e8f9f7 1881 #if defined(CRS)
<> 144:ef7eb2e8f9f7 1882
<> 144:ef7eb2e8f9f7 1883 /** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
<> 144:ef7eb2e8f9f7 1884 * @{
<> 144:ef7eb2e8f9f7 1885 */
<> 144:ef7eb2e8f9f7 1886 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 1887
<> 144:ef7eb2e8f9f7 1888 /**
<> 144:ef7eb2e8f9f7 1889 * @brief Enable the specified CRS interrupts.
<> 144:ef7eb2e8f9f7 1890 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 1891 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1892 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
<> 144:ef7eb2e8f9f7 1893 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
<> 144:ef7eb2e8f9f7 1894 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
<> 144:ef7eb2e8f9f7 1895 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
<> 144:ef7eb2e8f9f7 1896 * @retval None
<> 144:ef7eb2e8f9f7 1897 */
<> 144:ef7eb2e8f9f7 1898 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1899
<> 144:ef7eb2e8f9f7 1900 /**
<> 144:ef7eb2e8f9f7 1901 * @brief Disable the specified CRS interrupts.
<> 144:ef7eb2e8f9f7 1902 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
<> 144:ef7eb2e8f9f7 1903 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1904 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
<> 144:ef7eb2e8f9f7 1905 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
<> 144:ef7eb2e8f9f7 1906 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
<> 144:ef7eb2e8f9f7 1907 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
<> 144:ef7eb2e8f9f7 1908 * @retval None
<> 144:ef7eb2e8f9f7 1909 */
<> 144:ef7eb2e8f9f7 1910 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1911
<> 144:ef7eb2e8f9f7 1912 /** @brief Check whether the CRS interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 1913 * @param __INTERRUPT__ specifies the CRS interrupt source to check.
<> 144:ef7eb2e8f9f7 1914 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1915 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
<> 144:ef7eb2e8f9f7 1916 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
<> 144:ef7eb2e8f9f7 1917 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
<> 144:ef7eb2e8f9f7 1918 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
<> 144:ef7eb2e8f9f7 1919 * @retval The new state of __INTERRUPT__ (SET or RESET).
<> 144:ef7eb2e8f9f7 1920 */
<> 144:ef7eb2e8f9f7 1921 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
<> 144:ef7eb2e8f9f7 1922
<> 144:ef7eb2e8f9f7 1923 /** @brief Clear the CRS interrupt pending bits
<> 144:ef7eb2e8f9f7 1924 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
<> 144:ef7eb2e8f9f7 1925 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1926 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
<> 144:ef7eb2e8f9f7 1927 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
<> 144:ef7eb2e8f9f7 1928 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
<> 144:ef7eb2e8f9f7 1929 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
<> 144:ef7eb2e8f9f7 1930 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
<> 144:ef7eb2e8f9f7 1931 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
<> 144:ef7eb2e8f9f7 1932 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
<> 144:ef7eb2e8f9f7 1933 */
<> 144:ef7eb2e8f9f7 1934 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
<> 144:ef7eb2e8f9f7 1935 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
<> 144:ef7eb2e8f9f7 1936 { \
<> 144:ef7eb2e8f9f7 1937 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
<> 144:ef7eb2e8f9f7 1938 } \
<> 144:ef7eb2e8f9f7 1939 else \
<> 144:ef7eb2e8f9f7 1940 { \
<> 144:ef7eb2e8f9f7 1941 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
<> 144:ef7eb2e8f9f7 1942 } \
Anna Bridge 180:96ed750bd169 1943 } while(0U)
<> 144:ef7eb2e8f9f7 1944
<> 144:ef7eb2e8f9f7 1945 /**
<> 144:ef7eb2e8f9f7 1946 * @brief Check whether the specified CRS flag is set or not.
<> 144:ef7eb2e8f9f7 1947 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 1948 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1949 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
<> 144:ef7eb2e8f9f7 1950 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
<> 144:ef7eb2e8f9f7 1951 * @arg @ref RCC_CRS_FLAG_ERR Error
<> 144:ef7eb2e8f9f7 1952 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
<> 144:ef7eb2e8f9f7 1953 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
<> 144:ef7eb2e8f9f7 1954 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
<> 144:ef7eb2e8f9f7 1955 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
<> 144:ef7eb2e8f9f7 1956 * @retval The new state of _FLAG_ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 1957 */
<> 144:ef7eb2e8f9f7 1958 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1959
<> 144:ef7eb2e8f9f7 1960 /**
<> 144:ef7eb2e8f9f7 1961 * @brief Clear the CRS specified FLAG.
<> 144:ef7eb2e8f9f7 1962 * @param __FLAG__ specifies the flag to clear.
<> 144:ef7eb2e8f9f7 1963 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1964 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
<> 144:ef7eb2e8f9f7 1965 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
<> 144:ef7eb2e8f9f7 1966 * @arg @ref RCC_CRS_FLAG_ERR Error
<> 144:ef7eb2e8f9f7 1967 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
<> 144:ef7eb2e8f9f7 1968 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
<> 144:ef7eb2e8f9f7 1969 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
<> 144:ef7eb2e8f9f7 1970 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
<> 144:ef7eb2e8f9f7 1971 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
<> 144:ef7eb2e8f9f7 1972 * @retval None
<> 144:ef7eb2e8f9f7 1973 */
<> 144:ef7eb2e8f9f7 1974 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
<> 144:ef7eb2e8f9f7 1975 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
<> 144:ef7eb2e8f9f7 1976 { \
<> 144:ef7eb2e8f9f7 1977 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
<> 144:ef7eb2e8f9f7 1978 } \
<> 144:ef7eb2e8f9f7 1979 else \
<> 144:ef7eb2e8f9f7 1980 { \
<> 144:ef7eb2e8f9f7 1981 WRITE_REG(CRS->ICR, (__FLAG__)); \
<> 144:ef7eb2e8f9f7 1982 } \
Anna Bridge 180:96ed750bd169 1983 } while(0U)
<> 144:ef7eb2e8f9f7 1984
<> 144:ef7eb2e8f9f7 1985 /**
<> 144:ef7eb2e8f9f7 1986 * @}
<> 144:ef7eb2e8f9f7 1987 */
<> 144:ef7eb2e8f9f7 1988
<> 144:ef7eb2e8f9f7 1989 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
<> 144:ef7eb2e8f9f7 1990 * @{
<> 144:ef7eb2e8f9f7 1991 */
<> 144:ef7eb2e8f9f7 1992 /**
<> 144:ef7eb2e8f9f7 1993 * @brief Enable the oscillator clock for frequency error counter.
<> 144:ef7eb2e8f9f7 1994 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
<> 144:ef7eb2e8f9f7 1995 * @retval None
<> 144:ef7eb2e8f9f7 1996 */
<> 144:ef7eb2e8f9f7 1997 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
<> 144:ef7eb2e8f9f7 1998
<> 144:ef7eb2e8f9f7 1999 /**
<> 144:ef7eb2e8f9f7 2000 * @brief Disable the oscillator clock for frequency error counter.
<> 144:ef7eb2e8f9f7 2001 * @retval None
<> 144:ef7eb2e8f9f7 2002 */
<> 144:ef7eb2e8f9f7 2003 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
<> 144:ef7eb2e8f9f7 2004
<> 144:ef7eb2e8f9f7 2005 /**
<> 144:ef7eb2e8f9f7 2006 * @brief Enable the automatic hardware adjustement of TRIM bits.
<> 144:ef7eb2e8f9f7 2007 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
<> 144:ef7eb2e8f9f7 2008 * @retval None
<> 144:ef7eb2e8f9f7 2009 */
<> 144:ef7eb2e8f9f7 2010 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
<> 144:ef7eb2e8f9f7 2011
<> 144:ef7eb2e8f9f7 2012 /**
<> 144:ef7eb2e8f9f7 2013 * @brief Disable the automatic hardware adjustement of TRIM bits.
<> 144:ef7eb2e8f9f7 2014 * @retval None
<> 144:ef7eb2e8f9f7 2015 */
<> 144:ef7eb2e8f9f7 2016 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
<> 144:ef7eb2e8f9f7 2017
<> 144:ef7eb2e8f9f7 2018 /**
<> 144:ef7eb2e8f9f7 2019 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
<> 144:ef7eb2e8f9f7 2020 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
<> 144:ef7eb2e8f9f7 2021 * of the synchronization source after prescaling. It is then decreased by one in order to
<> 144:ef7eb2e8f9f7 2022 * reach the expected synchronization on the zero value. The formula is the following:
<> 144:ef7eb2e8f9f7 2023 * RELOAD = (fTARGET / fSYNC) -1
<> 144:ef7eb2e8f9f7 2024 * @param __FTARGET__ Target frequency (value in Hz)
<> 144:ef7eb2e8f9f7 2025 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
<> 144:ef7eb2e8f9f7 2026 * @retval None
<> 144:ef7eb2e8f9f7 2027 */
<> 144:ef7eb2e8f9f7 2028 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
<> 144:ef7eb2e8f9f7 2029
<> 144:ef7eb2e8f9f7 2030 /**
<> 144:ef7eb2e8f9f7 2031 * @}
<> 144:ef7eb2e8f9f7 2032 */
<> 144:ef7eb2e8f9f7 2033
<> 144:ef7eb2e8f9f7 2034 #endif /* CRS */
<> 144:ef7eb2e8f9f7 2035
<> 144:ef7eb2e8f9f7 2036 /**
<> 144:ef7eb2e8f9f7 2037 * @}
<> 144:ef7eb2e8f9f7 2038 */
<> 144:ef7eb2e8f9f7 2039
<> 144:ef7eb2e8f9f7 2040 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2041 /** @addtogroup RCCEx_Exported_Functions
<> 144:ef7eb2e8f9f7 2042 * @{
<> 144:ef7eb2e8f9f7 2043 */
<> 144:ef7eb2e8f9f7 2044
<> 144:ef7eb2e8f9f7 2045 /** @addtogroup RCCEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 2046 * @{
<> 144:ef7eb2e8f9f7 2047 */
<> 144:ef7eb2e8f9f7 2048
<> 144:ef7eb2e8f9f7 2049 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<> 144:ef7eb2e8f9f7 2050 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<> 144:ef7eb2e8f9f7 2051 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
<> 144:ef7eb2e8f9f7 2052
<> 144:ef7eb2e8f9f7 2053 /**
<> 144:ef7eb2e8f9f7 2054 * @}
<> 144:ef7eb2e8f9f7 2055 */
<> 144:ef7eb2e8f9f7 2056
<> 144:ef7eb2e8f9f7 2057 #if defined(CRS)
<> 144:ef7eb2e8f9f7 2058
<> 144:ef7eb2e8f9f7 2059 /** @addtogroup RCCEx_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 2060 * @{
<> 144:ef7eb2e8f9f7 2061 */
<> 144:ef7eb2e8f9f7 2062
<> 144:ef7eb2e8f9f7 2063 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
<> 144:ef7eb2e8f9f7 2064 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
<> 144:ef7eb2e8f9f7 2065 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
<> 144:ef7eb2e8f9f7 2066 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
<> 144:ef7eb2e8f9f7 2067 void HAL_RCCEx_CRS_IRQHandler(void);
<> 144:ef7eb2e8f9f7 2068 void HAL_RCCEx_CRS_SyncOkCallback(void);
<> 144:ef7eb2e8f9f7 2069 void HAL_RCCEx_CRS_SyncWarnCallback(void);
<> 144:ef7eb2e8f9f7 2070 void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
<> 144:ef7eb2e8f9f7 2071 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
<> 144:ef7eb2e8f9f7 2072
<> 144:ef7eb2e8f9f7 2073 /**
<> 144:ef7eb2e8f9f7 2074 * @}
<> 144:ef7eb2e8f9f7 2075 */
<> 144:ef7eb2e8f9f7 2076
<> 144:ef7eb2e8f9f7 2077 #endif /* CRS */
<> 144:ef7eb2e8f9f7 2078
<> 144:ef7eb2e8f9f7 2079 /**
<> 144:ef7eb2e8f9f7 2080 * @}
<> 144:ef7eb2e8f9f7 2081 */
<> 144:ef7eb2e8f9f7 2082
<> 144:ef7eb2e8f9f7 2083 /**
<> 144:ef7eb2e8f9f7 2084 * @}
<> 144:ef7eb2e8f9f7 2085 */
<> 144:ef7eb2e8f9f7 2086
<> 144:ef7eb2e8f9f7 2087 /**
<> 144:ef7eb2e8f9f7 2088 * @}
<> 144:ef7eb2e8f9f7 2089 */
<> 144:ef7eb2e8f9f7 2090
<> 144:ef7eb2e8f9f7 2091 /**
<> 144:ef7eb2e8f9f7 2092 * @}
<> 144:ef7eb2e8f9f7 2093 */
<> 144:ef7eb2e8f9f7 2094
<> 144:ef7eb2e8f9f7 2095 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 2096 }
<> 144:ef7eb2e8f9f7 2097 #endif
<> 144:ef7eb2e8f9f7 2098
<> 144:ef7eb2e8f9f7 2099 #endif /* __STM32F0xx_HAL_RCC_EX_H */
<> 144:ef7eb2e8f9f7 2100
<> 144:ef7eb2e8f9f7 2101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/