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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_rcc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Extended RCC HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities RCC extension peripheral:
<> 144:ef7eb2e8f9f7 8 * + Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 9 * + Extended Clock Recovery System Control functions
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 ******************************************************************************
<> 144:ef7eb2e8f9f7 12 * @attention
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 17 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 18 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 20 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 21 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 22 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 23 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 24 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 25 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 34 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 37 *
<> 144:ef7eb2e8f9f7 38 ******************************************************************************
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 42 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 45 * @{
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @defgroup RCCEx RCCEx
<> 144:ef7eb2e8f9f7 51 * @brief RCC Extension HAL module driver.
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 #if defined(CRS)
<> 144:ef7eb2e8f9f7 58 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61 /* Bit position in register */
Anna Bridge 180:96ed750bd169 62 #define CRS_CFGR_FELIM_BITNUMBER 16
Anna Bridge 180:96ed750bd169 63 #define CRS_CR_TRIM_BITNUMBER 8
Anna Bridge 180:96ed750bd169 64 #define CRS_ISR_FECAP_BITNUMBER 16
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @}
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 #endif /* CRS */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 71 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
<> 144:ef7eb2e8f9f7 72 * @{
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74 /**
<> 144:ef7eb2e8f9f7 75 * @}
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 79 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 80 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 87 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 @verbatim
<> 144:ef7eb2e8f9f7 90 ===============================================================================
<> 144:ef7eb2e8f9f7 91 ##### Extended Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 92 ===============================================================================
<> 144:ef7eb2e8f9f7 93 [..]
<> 144:ef7eb2e8f9f7 94 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 95 frequencies.
<> 144:ef7eb2e8f9f7 96 [..]
<> 144:ef7eb2e8f9f7 97 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
<> 144:ef7eb2e8f9f7 98 select the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 99 order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 100 the backup registers) are set to their reset values.
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 @endverbatim
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @brief Initializes the RCC extended peripherals clocks according to the specified
<> 144:ef7eb2e8f9f7 108 * parameters in the RCC_PeriphCLKInitTypeDef.
<> 144:ef7eb2e8f9f7 109 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 110 * contains the configuration information for the Extended Peripherals clocks
<> 144:ef7eb2e8f9f7 111 * (USART, RTC, I2C, CEC and USB).
<> 144:ef7eb2e8f9f7 112 *
<> 144:ef7eb2e8f9f7 113 * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
<> 144:ef7eb2e8f9f7 114 * the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 115 * order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 116 * the backup registers) and RCC_BDCR register are set to their reset values.
<> 144:ef7eb2e8f9f7 117 *
<> 144:ef7eb2e8f9f7 118 * @retval HAL status
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 121 {
<> 156:95d6b41a828b 122 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 123 uint32_t temp_reg = 0U;
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Check the parameters */
<> 144:ef7eb2e8f9f7 126 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /*---------------------------- RTC configuration -------------------------------*/
<> 144:ef7eb2e8f9f7 129 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 130 {
<> 144:ef7eb2e8f9f7 131 /* check for RTC Parameters used to output RTCCLK */
<> 144:ef7eb2e8f9f7 132 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 FlagStatus pwrclkchanged = RESET;
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* As soon as function is called to change RTC clock source, activation of the
<> 144:ef7eb2e8f9f7 137 power domain is done. */
<> 144:ef7eb2e8f9f7 138 /* Requires to enable write access to Backup Domain of necessary */
<> 144:ef7eb2e8f9f7 139 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
<> 144:ef7eb2e8f9f7 140 {
<> 144:ef7eb2e8f9f7 141 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 142 pwrclkchanged = SET;
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 148 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /* Wait for Backup domain Write protection disable */
<> 144:ef7eb2e8f9f7 151 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 154 {
<> 144:ef7eb2e8f9f7 155 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
<> 144:ef7eb2e8f9f7 163 temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
<> 144:ef7eb2e8f9f7 164 if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 /* Store the content of BDCR register before the reset of Backup Domain */
<> 144:ef7eb2e8f9f7 167 temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
<> 144:ef7eb2e8f9f7 168 /* RTC Clock selection can be changed only if the Backup Domain is reset */
<> 144:ef7eb2e8f9f7 169 __HAL_RCC_BACKUPRESET_FORCE();
<> 144:ef7eb2e8f9f7 170 __HAL_RCC_BACKUPRESET_RELEASE();
<> 144:ef7eb2e8f9f7 171 /* Restore the Content of BDCR register */
<> 144:ef7eb2e8f9f7 172 RCC->BDCR = temp_reg;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Wait for LSERDY if LSE was enabled */
<> 144:ef7eb2e8f9f7 175 if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
<> 144:ef7eb2e8f9f7 176 {
<> 144:ef7eb2e8f9f7 177 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 178 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 181 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Require to disable power clock if necessary */
<> 144:ef7eb2e8f9f7 193 if(pwrclkchanged == SET)
<> 144:ef7eb2e8f9f7 194 {
<> 144:ef7eb2e8f9f7 195 __HAL_RCC_PWR_CLK_DISABLE();
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /*------------------------------- USART1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 200 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 /* Check the parameters */
<> 144:ef7eb2e8f9f7 203 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Configure the USART1 clock source */
<> 144:ef7eb2e8f9f7 206 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 210 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 211 /*----------------------------- USART2 Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 212 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 /* Check the parameters */
<> 144:ef7eb2e8f9f7 215 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Configure the USART2 clock source */
<> 144:ef7eb2e8f9f7 218 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 221 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 224 /*----------------------------- USART3 Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 225 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 /* Check the parameters */
<> 144:ef7eb2e8f9f7 228 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* Configure the USART3 clock source */
<> 144:ef7eb2e8f9f7 231 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /*------------------------------ I2C1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 236 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
<> 144:ef7eb2e8f9f7 237 {
<> 144:ef7eb2e8f9f7 238 /* Check the parameters */
<> 144:ef7eb2e8f9f7 239 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* Configure the I2C1 clock source */
<> 144:ef7eb2e8f9f7 242 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
<> 144:ef7eb2e8f9f7 246 /*------------------------------ USB Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 247 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 /* Check the parameters */
<> 144:ef7eb2e8f9f7 250 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Configure the USB clock source */
<> 144:ef7eb2e8f9f7 253 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 258 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 259 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 260 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 261 /*------------------------------ CEC clock Configuration -------------------*/
<> 144:ef7eb2e8f9f7 262 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 /* Check the parameters */
<> 144:ef7eb2e8f9f7 265 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 268 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 271 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 272 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 273 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 return HAL_OK;
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief Get the RCC_ClkInitStruct according to the internal
<> 144:ef7eb2e8f9f7 280 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 281 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 282 * returns the configuration information for the Extended Peripherals clocks
<> 144:ef7eb2e8f9f7 283 * (USART, RTC, I2C, CEC and USB).
<> 144:ef7eb2e8f9f7 284 * @retval None
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 /* Set all possible values for the extended clock type parameter------------*/
<> 144:ef7eb2e8f9f7 289 /* Common part first */
<> 144:ef7eb2e8f9f7 290 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
<> 144:ef7eb2e8f9f7 291 /* Get the RTC configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 292 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
<> 144:ef7eb2e8f9f7 293 /* Get the USART1 clock configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 294 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
<> 144:ef7eb2e8f9f7 295 /* Get the I2C1 clock source -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 296 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 299 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 300 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2;
<> 144:ef7eb2e8f9f7 301 /* Get the USART2 clock source ---------------------------------------------*/
<> 144:ef7eb2e8f9f7 302 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
<> 144:ef7eb2e8f9f7 303 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 304 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 307 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3;
<> 144:ef7eb2e8f9f7 308 /* Get the USART3 clock source ---------------------------------------------*/
<> 144:ef7eb2e8f9f7 309 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
<> 144:ef7eb2e8f9f7 310 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
<> 144:ef7eb2e8f9f7 313 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
<> 144:ef7eb2e8f9f7 314 /* Get the USB clock source ---------------------------------------------*/
<> 144:ef7eb2e8f9f7 315 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
<> 144:ef7eb2e8f9f7 316 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 319 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 320 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 321 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 322 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
<> 144:ef7eb2e8f9f7 323 /* Get the CEC clock source ------------------------------------------------*/
<> 144:ef7eb2e8f9f7 324 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
<> 144:ef7eb2e8f9f7 325 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 326 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 327 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 328 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @brief Returns the peripheral clock frequency
<> 144:ef7eb2e8f9f7 334 * @note Returns 0 if peripheral clock is unknown
<> 144:ef7eb2e8f9f7 335 * @param PeriphClk Peripheral clock identifier
<> 144:ef7eb2e8f9f7 336 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 337 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
<> 144:ef7eb2e8f9f7 338 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
<> 144:ef7eb2e8f9f7 339 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
<> 144:ef7eb2e8f9f7 340 @if STM32F042x6
<> 144:ef7eb2e8f9f7 341 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 342 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 343 @endif
<> 144:ef7eb2e8f9f7 344 @if STM32F048xx
<> 144:ef7eb2e8f9f7 345 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 346 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 347 @endif
<> 144:ef7eb2e8f9f7 348 @if STM32F051x8
<> 144:ef7eb2e8f9f7 349 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 350 @endif
<> 144:ef7eb2e8f9f7 351 @if STM32F058xx
<> 144:ef7eb2e8f9f7 352 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 353 @endif
<> 144:ef7eb2e8f9f7 354 @if STM32F070x6
<> 144:ef7eb2e8f9f7 355 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 356 @endif
<> 144:ef7eb2e8f9f7 357 @if STM32F070xB
<> 144:ef7eb2e8f9f7 358 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 359 @endif
<> 144:ef7eb2e8f9f7 360 @if STM32F071xB
<> 144:ef7eb2e8f9f7 361 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 362 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 363 @endif
<> 144:ef7eb2e8f9f7 364 @if STM32F072xB
<> 144:ef7eb2e8f9f7 365 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 366 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 367 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 368 @endif
<> 144:ef7eb2e8f9f7 369 @if STM32F078xx
<> 144:ef7eb2e8f9f7 370 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 371 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 372 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 373 @endif
<> 144:ef7eb2e8f9f7 374 @if STM32F091xC
<> 144:ef7eb2e8f9f7 375 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 376 * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 377 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 378 @endif
<> 144:ef7eb2e8f9f7 379 @if STM32F098xx
<> 144:ef7eb2e8f9f7 380 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 381 * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 382 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 383 @endif
<> 144:ef7eb2e8f9f7 384 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
<> 144:ef7eb2e8f9f7 387 {
Anna Bridge 180:96ed750bd169 388 /* frequency == 0 : means that no available frequency for the peripheral */
<> 156:95d6b41a828b 389 uint32_t frequency = 0U;
Anna Bridge 180:96ed750bd169 390
<> 156:95d6b41a828b 391 uint32_t srcclk = 0U;
<> 144:ef7eb2e8f9f7 392 #if defined(USB)
<> 156:95d6b41a828b 393 uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U;
<> 144:ef7eb2e8f9f7 394 #endif /* USB */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Check the parameters */
<> 144:ef7eb2e8f9f7 397 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 switch (PeriphClk)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 case RCC_PERIPHCLK_RTC:
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 /* Get the current RTC source */
<> 144:ef7eb2e8f9f7 404 srcclk = __HAL_RCC_GET_RTC_SOURCE();
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Check if LSE is ready and if RTC clock selection is LSE */
<> 144:ef7eb2e8f9f7 407 if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411 /* Check if LSI is ready and if RTC clock selection is LSI */
<> 144:ef7eb2e8f9f7 412 else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
<> 144:ef7eb2e8f9f7 413 {
<> 144:ef7eb2e8f9f7 414 frequency = LSI_VALUE;
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
<> 144:ef7eb2e8f9f7 417 else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
<> 144:ef7eb2e8f9f7 418 {
<> 156:95d6b41a828b 419 frequency = HSE_VALUE / 32U;
<> 144:ef7eb2e8f9f7 420 }
<> 144:ef7eb2e8f9f7 421 break;
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423 case RCC_PERIPHCLK_USART1:
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 /* Get the current USART1 source */
<> 144:ef7eb2e8f9f7 426 srcclk = __HAL_RCC_GET_USART1_SOURCE();
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Check if USART1 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 429 if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433 /* Check if HSI is ready and if USART1 clock selection is HSI */
<> 144:ef7eb2e8f9f7 434 else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438 /* Check if USART1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 439 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 440 {
<> 144:ef7eb2e8f9f7 441 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 442 }
<> 144:ef7eb2e8f9f7 443 /* Check if LSE is ready and if USART1 clock selection is LSE */
<> 144:ef7eb2e8f9f7 444 else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448 break;
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450 #if defined(RCC_CFGR3_USART2SW)
<> 144:ef7eb2e8f9f7 451 case RCC_PERIPHCLK_USART2:
<> 144:ef7eb2e8f9f7 452 {
<> 144:ef7eb2e8f9f7 453 /* Get the current USART2 source */
<> 144:ef7eb2e8f9f7 454 srcclk = __HAL_RCC_GET_USART2_SOURCE();
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Check if USART2 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 457 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461 /* Check if HSI is ready and if USART2 clock selection is HSI */
<> 144:ef7eb2e8f9f7 462 else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466 /* Check if USART2 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 467 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471 /* Check if LSE is ready and if USART2 clock selection is LSE */
<> 144:ef7eb2e8f9f7 472 else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 473 {
<> 144:ef7eb2e8f9f7 474 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476 break;
<> 144:ef7eb2e8f9f7 477 }
<> 144:ef7eb2e8f9f7 478 #endif /* RCC_CFGR3_USART2SW */
<> 144:ef7eb2e8f9f7 479 #if defined(RCC_CFGR3_USART3SW)
<> 144:ef7eb2e8f9f7 480 case RCC_PERIPHCLK_USART3:
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 /* Get the current USART3 source */
<> 144:ef7eb2e8f9f7 483 srcclk = __HAL_RCC_GET_USART3_SOURCE();
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /* Check if USART3 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 486 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 489 }
<> 144:ef7eb2e8f9f7 490 /* Check if HSI is ready and if USART3 clock selection is HSI */
<> 144:ef7eb2e8f9f7 491 else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495 /* Check if USART3 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 496 else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 497 {
<> 144:ef7eb2e8f9f7 498 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500 /* Check if LSE is ready and if USART3 clock selection is LSE */
<> 144:ef7eb2e8f9f7 501 else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505 break;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507 #endif /* RCC_CFGR3_USART3SW */
<> 144:ef7eb2e8f9f7 508 case RCC_PERIPHCLK_I2C1:
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 /* Get the current I2C1 source */
<> 144:ef7eb2e8f9f7 511 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /* Check if HSI is ready and if I2C1 clock selection is HSI */
<> 144:ef7eb2e8f9f7 514 if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 515 {
<> 144:ef7eb2e8f9f7 516 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518 /* Check if I2C1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 519 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 break;
<> 144:ef7eb2e8f9f7 524 }
<> 144:ef7eb2e8f9f7 525 #if defined(USB)
<> 144:ef7eb2e8f9f7 526 case RCC_PERIPHCLK_USB:
<> 144:ef7eb2e8f9f7 527 {
<> 144:ef7eb2e8f9f7 528 /* Get the current USB source */
<> 144:ef7eb2e8f9f7 529 srcclk = __HAL_RCC_GET_USB_SOURCE();
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Check if PLL is ready and if USB clock selection is PLL */
<> 144:ef7eb2e8f9f7 532 if ((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 /* Get PLL clock source and multiplication factor ----------------------*/
<> 144:ef7eb2e8f9f7 535 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
<> 144:ef7eb2e8f9f7 536 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
<> 156:95d6b41a828b 537 pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2U;
<> 156:95d6b41a828b 538 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
<> 144:ef7eb2e8f9f7 541 {
<> 144:ef7eb2e8f9f7 542 /* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 543 frequency = (HSE_VALUE/predivfactor) * pllmull;
<> 144:ef7eb2e8f9f7 544 }
<> 144:ef7eb2e8f9f7 545 #if defined(RCC_CR2_HSI48ON)
<> 144:ef7eb2e8f9f7 546 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
<> 144:ef7eb2e8f9f7 547 {
<> 144:ef7eb2e8f9f7 548 /* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 549 frequency = (HSI48_VALUE / predivfactor) * pllmull;
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551 #endif /* RCC_CR2_HSI48ON */
<> 144:ef7eb2e8f9f7 552 else
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 555 /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 556 frequency = (HSI_VALUE / predivfactor) * pllmull;
<> 144:ef7eb2e8f9f7 557 #else
Anna Bridge 180:96ed750bd169 558 /* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */
<> 156:95d6b41a828b 559 frequency = (HSI_VALUE >> 1U) * pllmull;
<> 144:ef7eb2e8f9f7 560 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563 #if defined(RCC_CR2_HSI48ON)
<> 144:ef7eb2e8f9f7 564 /* Check if HSI48 is ready and if USB clock selection is HSI48 */
<> 144:ef7eb2e8f9f7 565 else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY)))
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 frequency = HSI48_VALUE;
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569 #endif /* RCC_CR2_HSI48ON */
<> 144:ef7eb2e8f9f7 570 break;
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572 #endif /* USB */
<> 144:ef7eb2e8f9f7 573 #if defined(CEC)
<> 144:ef7eb2e8f9f7 574 case RCC_PERIPHCLK_CEC:
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 /* Get the current CEC source */
<> 144:ef7eb2e8f9f7 577 srcclk = __HAL_RCC_GET_CEC_SOURCE();
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* Check if HSI is ready and if CEC clock selection is HSI */
<> 144:ef7eb2e8f9f7 580 if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584 /* Check if LSE is ready and if CEC clock selection is LSE */
<> 144:ef7eb2e8f9f7 585 else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 586 {
<> 144:ef7eb2e8f9f7 587 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589 break;
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591 #endif /* CEC */
<> 144:ef7eb2e8f9f7 592 default:
<> 144:ef7eb2e8f9f7 593 {
<> 144:ef7eb2e8f9f7 594 break;
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597 return(frequency);
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /**
<> 144:ef7eb2e8f9f7 601 * @}
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 #if defined(CRS)
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
<> 144:ef7eb2e8f9f7 607 * @brief Extended Clock Recovery System Control functions
<> 144:ef7eb2e8f9f7 608 *
<> 144:ef7eb2e8f9f7 609 @verbatim
<> 144:ef7eb2e8f9f7 610 ===============================================================================
<> 144:ef7eb2e8f9f7 611 ##### Extended Clock Recovery System Control functions #####
<> 144:ef7eb2e8f9f7 612 ===============================================================================
<> 144:ef7eb2e8f9f7 613 [..]
<> 144:ef7eb2e8f9f7 614 For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 (#) In System clock config, HSI48 needs to be enabled
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 (#) Enable CRS clock in IP MSP init which will use CRS functions
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 (#) Call CRS functions as follows:
<> 144:ef7eb2e8f9f7 621 (##) Prepare synchronization configuration necessary for HSI48 calibration
<> 144:ef7eb2e8f9f7 622 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
<> 144:ef7eb2e8f9f7 623 and also HSI48 oscillator smooth trimming.
<> 144:ef7eb2e8f9f7 624 (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
<> 144:ef7eb2e8f9f7 625 directly reload value with target and synchronization frequencies values
<> 144:ef7eb2e8f9f7 626 (##) Call function @ref HAL_RCCEx_CRSConfig which
<> 144:ef7eb2e8f9f7 627 (+++) Reset CRS registers to their default values.
<> 144:ef7eb2e8f9f7 628 (+++) Configure CRS registers with synchronization configuration
<> 144:ef7eb2e8f9f7 629 (+++) Enable automatic calibration and frequency error counter feature
<> 144:ef7eb2e8f9f7 630 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
<> 144:ef7eb2e8f9f7 631 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
<> 144:ef7eb2e8f9f7 632 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
<> 144:ef7eb2e8f9f7 633 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
<> 144:ef7eb2e8f9f7 634 should be used as SYNC signal.
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 (##) A polling function is provided to wait for complete synchronization
<> 144:ef7eb2e8f9f7 637 (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization()
<> 144:ef7eb2e8f9f7 638 (+++) According to CRS status, user can decide to adjust again the calibration or continue
<> 144:ef7eb2e8f9f7 639 application if synchronization is OK
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 (#) User can retrieve information related to synchronization in calling function
<> 144:ef7eb2e8f9f7 642 @ref HAL_RCCEx_CRSGetSynchronizationInfo()
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 (#) Regarding synchronization status and synchronization information, user can try a new calibration
<> 144:ef7eb2e8f9f7 645 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
<> 144:ef7eb2e8f9f7 646 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
<> 144:ef7eb2e8f9f7 647 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
<> 144:ef7eb2e8f9f7 648 incremented), while when it is detected during the upcounting phase it means that the actual frequency
<> 144:ef7eb2e8f9f7 649 is higher (and that the TRIM value should be decremented).
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
<> 144:ef7eb2e8f9f7 652 through CRS Handler (RCC_IRQn/RCC_IRQHandler)
<> 144:ef7eb2e8f9f7 653 (++) Call function @ref HAL_RCCEx_CRSConfig()
<> 144:ef7eb2e8f9f7 654 (++) Enable RCC_IRQn (thanks to NVIC functions)
<> 144:ef7eb2e8f9f7 655 (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT)
<> 144:ef7eb2e8f9f7 656 (++) Implement CRS status management in the following user callbacks called from
<> 144:ef7eb2e8f9f7 657 HAL_RCCEx_CRS_IRQHandler():
<> 144:ef7eb2e8f9f7 658 (+++) @ref HAL_RCCEx_CRS_SyncOkCallback()
<> 144:ef7eb2e8f9f7 659 (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback()
<> 144:ef7eb2e8f9f7 660 (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback()
<> 144:ef7eb2e8f9f7 661 (+++) @ref HAL_RCCEx_CRS_ErrorCallback()
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
<> 144:ef7eb2e8f9f7 664 This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler)
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 @endverbatim
<> 144:ef7eb2e8f9f7 667 * @{
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
<> 144:ef7eb2e8f9f7 671 * @brief Start automatic synchronization for polling mode
<> 144:ef7eb2e8f9f7 672 * @param pInit Pointer on RCC_CRSInitTypeDef structure
<> 144:ef7eb2e8f9f7 673 * @retval None
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
<> 144:ef7eb2e8f9f7 676 {
<> 156:95d6b41a828b 677 uint32_t value = 0U;
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /* Check the parameters */
<> 144:ef7eb2e8f9f7 680 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
<> 144:ef7eb2e8f9f7 681 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
<> 144:ef7eb2e8f9f7 682 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
<> 144:ef7eb2e8f9f7 683 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
<> 144:ef7eb2e8f9f7 684 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
<> 144:ef7eb2e8f9f7 685 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* CONFIGURATION */
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* Before configuration, reset CRS registers to their default values*/
<> 144:ef7eb2e8f9f7 690 __HAL_RCC_CRS_FORCE_RESET();
<> 144:ef7eb2e8f9f7 691 __HAL_RCC_CRS_RELEASE_RESET();
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Set the SYNCDIV[2:0] bits according to Prescaler value */
<> 144:ef7eb2e8f9f7 694 /* Set the SYNCSRC[1:0] bits according to Source value */
<> 144:ef7eb2e8f9f7 695 /* Set the SYNCSPOL bit according to Polarity value */
<> 144:ef7eb2e8f9f7 696 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
<> 144:ef7eb2e8f9f7 697 /* Set the RELOAD[15:0] bits according to ReloadValue value */
<> 144:ef7eb2e8f9f7 698 value |= pInit->ReloadValue;
<> 144:ef7eb2e8f9f7 699 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
<> 144:ef7eb2e8f9f7 700 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
<> 144:ef7eb2e8f9f7 701 WRITE_REG(CRS->CFGR, value);
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Adjust HSI48 oscillator smooth trimming */
<> 144:ef7eb2e8f9f7 704 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
<> 144:ef7eb2e8f9f7 705 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER));
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /* START AUTOMATIC SYNCHRONIZATION*/
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /* Enable Automatic trimming & Frequency error counter */
<> 144:ef7eb2e8f9f7 710 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /**
<> 144:ef7eb2e8f9f7 714 * @brief Generate the software synchronization event
<> 144:ef7eb2e8f9f7 715 * @retval None
<> 144:ef7eb2e8f9f7 716 */
<> 144:ef7eb2e8f9f7 717 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /**
<> 144:ef7eb2e8f9f7 723 * @brief Return synchronization info
<> 144:ef7eb2e8f9f7 724 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
<> 144:ef7eb2e8f9f7 725 * @retval None
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
<> 144:ef7eb2e8f9f7 728 {
<> 144:ef7eb2e8f9f7 729 /* Check the parameter */
<> 144:ef7eb2e8f9f7 730 assert_param(pSynchroInfo != NULL);
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /* Get the reload value */
<> 144:ef7eb2e8f9f7 733 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /* Get HSI48 oscillator smooth trimming */
<> 144:ef7eb2e8f9f7 736 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Get Frequency error capture */
<> 144:ef7eb2e8f9f7 739 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /* Get Frequency error direction */
<> 144:ef7eb2e8f9f7 742 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
<> 144:ef7eb2e8f9f7 743 }
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /**
<> 144:ef7eb2e8f9f7 746 * @brief Wait for CRS Synchronization status.
<> 144:ef7eb2e8f9f7 747 * @param Timeout Duration of the timeout
<> 144:ef7eb2e8f9f7 748 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
<> 144:ef7eb2e8f9f7 749 * frequency.
<> 144:ef7eb2e8f9f7 750 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
<> 144:ef7eb2e8f9f7 751 * @retval Combination of Synchronization status
<> 144:ef7eb2e8f9f7 752 * This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 753 * @arg @ref RCC_CRS_TIMEOUT
<> 144:ef7eb2e8f9f7 754 * @arg @ref RCC_CRS_SYNCOK
<> 144:ef7eb2e8f9f7 755 * @arg @ref RCC_CRS_SYNCWARN
<> 144:ef7eb2e8f9f7 756 * @arg @ref RCC_CRS_SYNCERR
<> 144:ef7eb2e8f9f7 757 * @arg @ref RCC_CRS_SYNCMISS
<> 144:ef7eb2e8f9f7 758 * @arg @ref RCC_CRS_TRIMOVF
<> 144:ef7eb2e8f9f7 759 */
<> 144:ef7eb2e8f9f7 760 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
<> 144:ef7eb2e8f9f7 761 {
<> 144:ef7eb2e8f9f7 762 uint32_t crsstatus = RCC_CRS_NONE;
<> 144:ef7eb2e8f9f7 763 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Get timeout */
<> 144:ef7eb2e8f9f7 766 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Wait for CRS flag or timeout detection */
<> 144:ef7eb2e8f9f7 769 do
<> 144:ef7eb2e8f9f7 770 {
<> 144:ef7eb2e8f9f7 771 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 crsstatus = RCC_CRS_TIMEOUT;
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 /* Check CRS SYNCOK flag */
<> 144:ef7eb2e8f9f7 779 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 /* CRS SYNC event OK */
<> 144:ef7eb2e8f9f7 782 crsstatus |= RCC_CRS_SYNCOK;
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Clear CRS SYNC event OK bit */
<> 144:ef7eb2e8f9f7 785 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /* Check CRS SYNCWARN flag */
<> 144:ef7eb2e8f9f7 789 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 /* CRS SYNC warning */
<> 144:ef7eb2e8f9f7 792 crsstatus |= RCC_CRS_SYNCWARN;
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /* Clear CRS SYNCWARN bit */
<> 144:ef7eb2e8f9f7 795 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /* Check CRS TRIM overflow flag */
<> 144:ef7eb2e8f9f7 799 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 /* CRS SYNC Error */
<> 144:ef7eb2e8f9f7 802 crsstatus |= RCC_CRS_TRIMOVF;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Clear CRS Error bit */
<> 144:ef7eb2e8f9f7 805 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /* Check CRS Error flag */
<> 144:ef7eb2e8f9f7 809 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 /* CRS SYNC Error */
<> 144:ef7eb2e8f9f7 812 crsstatus |= RCC_CRS_SYNCERR;
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Clear CRS Error bit */
<> 144:ef7eb2e8f9f7 815 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* Check CRS SYNC Missed flag */
<> 144:ef7eb2e8f9f7 819 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
<> 144:ef7eb2e8f9f7 820 {
<> 144:ef7eb2e8f9f7 821 /* CRS SYNC Missed */
<> 144:ef7eb2e8f9f7 822 crsstatus |= RCC_CRS_SYNCMISS;
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /* Clear CRS SYNC Missed bit */
<> 144:ef7eb2e8f9f7 825 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Check CRS Expected SYNC flag */
<> 144:ef7eb2e8f9f7 829 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 /* frequency error counter reached a zero value */
<> 144:ef7eb2e8f9f7 832 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 } while(RCC_CRS_NONE == crsstatus);
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 return crsstatus;
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /**
<> 144:ef7eb2e8f9f7 840 * @brief Handle the Clock Recovery System interrupt request.
<> 144:ef7eb2e8f9f7 841 * @retval None
<> 144:ef7eb2e8f9f7 842 */
<> 144:ef7eb2e8f9f7 843 void HAL_RCCEx_CRS_IRQHandler(void)
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 uint32_t crserror = RCC_CRS_NONE;
<> 144:ef7eb2e8f9f7 846 /* Get current IT flags and IT sources values */
<> 144:ef7eb2e8f9f7 847 uint32_t itflags = READ_REG(CRS->ISR);
<> 144:ef7eb2e8f9f7 848 uint32_t itsources = READ_REG(CRS->CR);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /* Check CRS SYNCOK flag */
<> 144:ef7eb2e8f9f7 851 if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET))
<> 144:ef7eb2e8f9f7 852 {
<> 144:ef7eb2e8f9f7 853 /* Clear CRS SYNC event OK flag */
<> 144:ef7eb2e8f9f7 854 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* user callback */
<> 144:ef7eb2e8f9f7 857 HAL_RCCEx_CRS_SyncOkCallback();
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859 /* Check CRS SYNCWARN flag */
<> 144:ef7eb2e8f9f7 860 else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET))
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 /* Clear CRS SYNCWARN flag */
<> 144:ef7eb2e8f9f7 863 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /* user callback */
<> 144:ef7eb2e8f9f7 866 HAL_RCCEx_CRS_SyncWarnCallback();
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868 /* Check CRS Expected SYNC flag */
<> 144:ef7eb2e8f9f7 869 else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET))
<> 144:ef7eb2e8f9f7 870 {
<> 144:ef7eb2e8f9f7 871 /* frequency error counter reached a zero value */
<> 144:ef7eb2e8f9f7 872 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* user callback */
<> 144:ef7eb2e8f9f7 875 HAL_RCCEx_CRS_ExpectedSyncCallback();
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877 /* Check CRS Error flags */
<> 144:ef7eb2e8f9f7 878 else
<> 144:ef7eb2e8f9f7 879 {
<> 144:ef7eb2e8f9f7 880 if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 881 {
<> 144:ef7eb2e8f9f7 882 if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 crserror |= RCC_CRS_SYNCERR;
<> 144:ef7eb2e8f9f7 885 }
<> 144:ef7eb2e8f9f7 886 if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET)
<> 144:ef7eb2e8f9f7 887 {
<> 144:ef7eb2e8f9f7 888 crserror |= RCC_CRS_SYNCMISS;
<> 144:ef7eb2e8f9f7 889 }
<> 144:ef7eb2e8f9f7 890 if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET)
<> 144:ef7eb2e8f9f7 891 {
<> 144:ef7eb2e8f9f7 892 crserror |= RCC_CRS_TRIMOVF;
<> 144:ef7eb2e8f9f7 893 }
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /* Clear CRS Error flags */
<> 144:ef7eb2e8f9f7 896 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /* user error callback */
<> 144:ef7eb2e8f9f7 899 HAL_RCCEx_CRS_ErrorCallback(crserror);
<> 144:ef7eb2e8f9f7 900 }
<> 144:ef7eb2e8f9f7 901 }
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /**
<> 144:ef7eb2e8f9f7 905 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
<> 144:ef7eb2e8f9f7 906 * @retval none
<> 144:ef7eb2e8f9f7 907 */
<> 144:ef7eb2e8f9f7 908 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
<> 144:ef7eb2e8f9f7 909 {
<> 144:ef7eb2e8f9f7 910 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 911 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 912 */
<> 144:ef7eb2e8f9f7 913 }
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /**
<> 144:ef7eb2e8f9f7 916 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
<> 144:ef7eb2e8f9f7 917 * @retval none
<> 144:ef7eb2e8f9f7 918 */
<> 144:ef7eb2e8f9f7 919 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
<> 144:ef7eb2e8f9f7 920 {
<> 144:ef7eb2e8f9f7 921 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 922 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 923 */
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /**
<> 144:ef7eb2e8f9f7 927 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
<> 144:ef7eb2e8f9f7 928 * @retval none
<> 144:ef7eb2e8f9f7 929 */
<> 144:ef7eb2e8f9f7 930 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 933 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 934 */
<> 144:ef7eb2e8f9f7 935 }
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /**
<> 144:ef7eb2e8f9f7 938 * @brief RCCEx Clock Recovery System Error interrupt callback.
<> 144:ef7eb2e8f9f7 939 * @param Error Combination of Error status.
<> 144:ef7eb2e8f9f7 940 * This parameter can be a combination of the following values:
<> 144:ef7eb2e8f9f7 941 * @arg @ref RCC_CRS_SYNCERR
<> 144:ef7eb2e8f9f7 942 * @arg @ref RCC_CRS_SYNCMISS
<> 144:ef7eb2e8f9f7 943 * @arg @ref RCC_CRS_TRIMOVF
<> 144:ef7eb2e8f9f7 944 * @retval none
<> 144:ef7eb2e8f9f7 945 */
<> 144:ef7eb2e8f9f7 946 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
<> 144:ef7eb2e8f9f7 947 {
<> 144:ef7eb2e8f9f7 948 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 949 UNUSED(Error);
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 952 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 953 */
<> 144:ef7eb2e8f9f7 954 }
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 /**
<> 144:ef7eb2e8f9f7 957 * @}
<> 144:ef7eb2e8f9f7 958 */
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 #endif /* CRS */
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 /**
<> 144:ef7eb2e8f9f7 963 * @}
<> 144:ef7eb2e8f9f7 964 */
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 /**
<> 144:ef7eb2e8f9f7 967 * @}
<> 144:ef7eb2e8f9f7 968 */
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /**
<> 144:ef7eb2e8f9f7 971 * @}
<> 144:ef7eb2e8f9f7 972 */
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 /**
<> 144:ef7eb2e8f9f7 977 * @}
<> 144:ef7eb2e8f9f7 978 */
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/