mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_pwr.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief PWR HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Power Controller (PWR) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization/de-initialization function
<> 144:ef7eb2e8f9f7 9 * + Peripheral Control function
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ******************************************************************************
<> 144:ef7eb2e8f9f7 13 * @attention
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 18 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 19 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 20 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 22 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 23 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 25 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 26 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 38 *
<> 144:ef7eb2e8f9f7 39 ******************************************************************************
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 43 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @defgroup PWR PWR
<> 144:ef7eb2e8f9f7 50 * @brief PWR HAL module driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 #ifdef HAL_PWR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 61 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @defgroup PWR_Exported_Functions PWR Exported Functions
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 68 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 69 *
<> 144:ef7eb2e8f9f7 70 @verbatim
<> 144:ef7eb2e8f9f7 71 ===============================================================================
<> 144:ef7eb2e8f9f7 72 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 73 ===============================================================================
<> 144:ef7eb2e8f9f7 74 [..]
<> 144:ef7eb2e8f9f7 75 After reset, the backup domain (RTC registers, RTC backup data
<> 144:ef7eb2e8f9f7 76 registers) is protected against possible unwanted
<> 144:ef7eb2e8f9f7 77 write accesses.
<> 144:ef7eb2e8f9f7 78 To enable access to the RTC Domain and RTC registers, proceed as follows:
<> 144:ef7eb2e8f9f7 79 (+) Enable the Power Controller (PWR) APB1 interface clock using the
<> 144:ef7eb2e8f9f7 80 __HAL_RCC_PWR_CLK_ENABLE() macro.
<> 144:ef7eb2e8f9f7 81 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 @endverbatim
<> 144:ef7eb2e8f9f7 84 * @{
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /**
<> 144:ef7eb2e8f9f7 88 * @brief Deinitializes the PWR peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 89 * @retval None
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91 void HAL_PWR_DeInit(void)
<> 144:ef7eb2e8f9f7 92 {
<> 144:ef7eb2e8f9f7 93 __HAL_RCC_PWR_FORCE_RESET();
<> 144:ef7eb2e8f9f7 94 __HAL_RCC_PWR_RELEASE_RESET();
<> 144:ef7eb2e8f9f7 95 }
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /**
<> 144:ef7eb2e8f9f7 98 * @brief Enables access to the backup domain (RTC registers, RTC
<> 144:ef7eb2e8f9f7 99 * backup data registers when present).
<> 144:ef7eb2e8f9f7 100 * @note If the HSE divided by 32 is used as the RTC clock, the
<> 144:ef7eb2e8f9f7 101 * Backup Domain Access should be kept enabled.
<> 144:ef7eb2e8f9f7 102 * @retval None
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104 void HAL_PWR_EnableBkUpAccess(void)
<> 144:ef7eb2e8f9f7 105 {
<> 144:ef7eb2e8f9f7 106 PWR->CR |= (uint32_t)PWR_CR_DBP;
<> 144:ef7eb2e8f9f7 107 }
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /**
<> 144:ef7eb2e8f9f7 110 * @brief Disables access to the backup domain (RTC registers, RTC
<> 144:ef7eb2e8f9f7 111 * backup data registers when present).
<> 144:ef7eb2e8f9f7 112 * @note If the HSE divided by 32 is used as the RTC clock, the
<> 144:ef7eb2e8f9f7 113 * Backup Domain Access should be kept enabled.
<> 144:ef7eb2e8f9f7 114 * @retval None
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 void HAL_PWR_DisableBkUpAccess(void)
<> 144:ef7eb2e8f9f7 117 {
<> 144:ef7eb2e8f9f7 118 PWR->CR &= ~((uint32_t)PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 119 }
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @}
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 126 * @brief Low Power modes configuration functions
<> 144:ef7eb2e8f9f7 127 *
<> 144:ef7eb2e8f9f7 128 @verbatim
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 ===============================================================================
<> 144:ef7eb2e8f9f7 131 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 132 ===============================================================================
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 *** WakeUp pin configuration ***
<> 144:ef7eb2e8f9f7 135 ================================
<> 144:ef7eb2e8f9f7 136 [..]
<> 144:ef7eb2e8f9f7 137 (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
<> 144:ef7eb2e8f9f7 138 forced in input pull down configuration and is active on rising edges.
<> 144:ef7eb2e8f9f7 139 (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices.
<> 144:ef7eb2e8f9f7 140 (++)WakeUp Pin 1 on PA.00.
<> 144:ef7eb2e8f9f7 141 (++)WakeUp Pin 2 on PC.13.
<> 144:ef7eb2e8f9f7 142 (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x)
<> 144:ef7eb2e8f9f7 143 (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x)
<> 144:ef7eb2e8f9f7 144 (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x)
<> 144:ef7eb2e8f9f7 145 (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x)
<> 144:ef7eb2e8f9f7 146 (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x)
<> 144:ef7eb2e8f9f7 147 (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x)
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 *** Low Power modes configuration ***
<> 144:ef7eb2e8f9f7 150 =====================================
<> 144:ef7eb2e8f9f7 151 [..]
<> 144:ef7eb2e8f9f7 152 The devices feature 3 low-power modes:
<> 144:ef7eb2e8f9f7 153 (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
<> 144:ef7eb2e8f9f7 154 (+) Stop mode: all clocks are stopped, regulator running, regulator
<> 144:ef7eb2e8f9f7 155 in low power mode
<> 144:ef7eb2e8f9f7 156 (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices).
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 *** Sleep mode ***
<> 144:ef7eb2e8f9f7 159 ==================
<> 144:ef7eb2e8f9f7 160 [..]
<> 144:ef7eb2e8f9f7 161 (+) Entry:
<> 144:ef7eb2e8f9f7 162 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
<> 144:ef7eb2e8f9f7 163 functions with
<> 144:ef7eb2e8f9f7 164 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
<> 144:ef7eb2e8f9f7 165 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 (+) Exit:
<> 144:ef7eb2e8f9f7 168 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
<> 144:ef7eb2e8f9f7 169 controller (NVIC) can wake up the device from Sleep mode.
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 *** Stop mode ***
<> 144:ef7eb2e8f9f7 172 =================
<> 144:ef7eb2e8f9f7 173 [..]
<> 144:ef7eb2e8f9f7 174 In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
<> 144:ef7eb2e8f9f7 175 and the HSE RC oscillators are disabled. Internal SRAM and register contents
<> 144:ef7eb2e8f9f7 176 are preserved.
<> 144:ef7eb2e8f9f7 177 The voltage regulator can be configured either in normal or low-power mode.
<> 144:ef7eb2e8f9f7 178 To minimize the consumption.
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 (+) Entry:
<> 144:ef7eb2e8f9f7 181 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
<> 144:ef7eb2e8f9f7 182 function with:
<> 144:ef7eb2e8f9f7 183 (++) Main regulator ON.
<> 144:ef7eb2e8f9f7 184 (++) Low Power regulator ON.
<> 144:ef7eb2e8f9f7 185 (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
<> 144:ef7eb2e8f9f7 186 (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
<> 144:ef7eb2e8f9f7 187 (+) Exit:
<> 144:ef7eb2e8f9f7 188 (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
<> 144:ef7eb2e8f9f7 189 (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
<> 144:ef7eb2e8f9f7 190 when programmed in wakeup mode (the peripheral must be
<> 144:ef7eb2e8f9f7 191 programmed in wakeup mode and the corresponding interrupt vector
<> 144:ef7eb2e8f9f7 192 must be enabled in the NVIC)
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 *** Standby mode ***
<> 144:ef7eb2e8f9f7 195 ====================
<> 144:ef7eb2e8f9f7 196 [..]
<> 144:ef7eb2e8f9f7 197 The Standby mode allows to achieve the lowest power consumption. It is based
<> 144:ef7eb2e8f9f7 198 on the Cortex-M0 deep sleep mode, with the voltage regulator disabled.
<> 144:ef7eb2e8f9f7 199 The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
<> 144:ef7eb2e8f9f7 200 the HSE oscillator are also switched off. SRAM and register contents are lost
<> 144:ef7eb2e8f9f7 201 except for the RTC registers, RTC backup registers and Standby circuitry.
<> 144:ef7eb2e8f9f7 202 The voltage regulator is OFF.
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 (+) Entry:
<> 144:ef7eb2e8f9f7 205 (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
<> 144:ef7eb2e8f9f7 206 (+) Exit:
<> 144:ef7eb2e8f9f7 207 (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup,
<> 144:ef7eb2e8f9f7 208 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 *** Auto-wakeup (AWU) from low-power mode ***
<> 144:ef7eb2e8f9f7 211 =============================================
<> 144:ef7eb2e8f9f7 212 [..]
<> 144:ef7eb2e8f9f7 213 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
<> 144:ef7eb2e8f9f7 214 Wakeup event, a tamper event, a time-stamp event, or a comparator event,
<> 144:ef7eb2e8f9f7 215 without depending on an external interrupt (Auto-wakeup mode).
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
<> 144:ef7eb2e8f9f7 220 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
<> 144:ef7eb2e8f9f7 223 is necessary to configure the RTC to detect the tamper or time stamp event using the
<> 144:ef7eb2e8f9f7 224 HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
<> 144:ef7eb2e8f9f7 227 configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 (+) Comparator auto-wakeup (AWU) from the Stop mode
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
<> 144:ef7eb2e8f9f7 232 (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2)
<> 144:ef7eb2e8f9f7 233 to be sensitive to to the selected edges (falling, rising or falling
<> 144:ef7eb2e8f9f7 234 and rising) (Interrupt or Event modes) using the EXTI_Init() function.
<> 144:ef7eb2e8f9f7 235 (+++) Configure the comparator to generate the event.
<> 144:ef7eb2e8f9f7 236 @endverbatim
<> 144:ef7eb2e8f9f7 237 * @{
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief Enables the WakeUp PINx functionality.
Anna Bridge 180:96ed750bd169 242 * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
<> 144:ef7eb2e8f9f7 243 * This parameter can be value of :
<> 144:ef7eb2e8f9f7 244 * @ref PWREx_WakeUp_Pins
<> 144:ef7eb2e8f9f7 245 * @retval None
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 /* Check the parameters */
<> 144:ef7eb2e8f9f7 250 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
<> 144:ef7eb2e8f9f7 251 /* Enable the EWUPx pin */
<> 144:ef7eb2e8f9f7 252 SET_BIT(PWR->CSR, WakeUpPinx);
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @brief Disables the WakeUp PINx functionality.
Anna Bridge 180:96ed750bd169 257 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
<> 144:ef7eb2e8f9f7 258 * This parameter can be values of :
<> 144:ef7eb2e8f9f7 259 * @ref PWREx_WakeUp_Pins
<> 144:ef7eb2e8f9f7 260 * @retval None
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 /* Check the parameters */
<> 144:ef7eb2e8f9f7 265 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
<> 144:ef7eb2e8f9f7 266 /* Disable the EWUPx pin */
<> 144:ef7eb2e8f9f7 267 CLEAR_BIT(PWR->CSR, WakeUpPinx);
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @brief Enters Sleep mode.
<> 144:ef7eb2e8f9f7 272 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
Anna Bridge 180:96ed750bd169 273 * @param Regulator Specifies the regulator state in SLEEP mode.
<> 144:ef7eb2e8f9f7 274 * On STM32F0 devices, this parameter is a dummy value and it is ignored
<> 144:ef7eb2e8f9f7 275 * as regulator can't be modified in this mode. Parameter is kept for platform
<> 144:ef7eb2e8f9f7 276 * compatibility.
Anna Bridge 180:96ed750bd169 277 * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 278 * When WFI entry is used, tick interrupt have to be disabled if not desired as
<> 144:ef7eb2e8f9f7 279 * the interrupt wake up source.
<> 144:ef7eb2e8f9f7 280 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 281 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
<> 144:ef7eb2e8f9f7 282 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
<> 144:ef7eb2e8f9f7 283 * @retval None
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 /* Check the parameters */
<> 144:ef7eb2e8f9f7 288 assert_param(IS_PWR_REGULATOR(Regulator));
<> 144:ef7eb2e8f9f7 289 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Clear SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 292 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* Select SLEEP mode entry -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 295 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 298 __WFI();
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300 else
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 303 __SEV();
<> 144:ef7eb2e8f9f7 304 __WFE();
<> 144:ef7eb2e8f9f7 305 __WFE();
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307 }
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @brief Enters STOP mode.
<> 144:ef7eb2e8f9f7 311 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 312 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
<> 144:ef7eb2e8f9f7 313 * the HSI RC oscillator is selected as system clock.
<> 144:ef7eb2e8f9f7 314 * @note When the voltage regulator operates in low power mode, an additional
<> 144:ef7eb2e8f9f7 315 * startup delay is incurred when waking up from Stop mode.
<> 144:ef7eb2e8f9f7 316 * By keeping the internal regulator ON during Stop mode, the consumption
<> 144:ef7eb2e8f9f7 317 * is higher although the startup time is reduced.
Anna Bridge 180:96ed750bd169 318 * @param Regulator Specifies the regulator state in STOP mode.
<> 144:ef7eb2e8f9f7 319 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 320 * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
<> 144:ef7eb2e8f9f7 321 * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
Anna Bridge 180:96ed750bd169 322 * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 323 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 324 * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
<> 144:ef7eb2e8f9f7 325 * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
<> 144:ef7eb2e8f9f7 326 * @retval None
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Check the parameters */
<> 144:ef7eb2e8f9f7 333 assert_param(IS_PWR_REGULATOR(Regulator));
<> 144:ef7eb2e8f9f7 334 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Select the regulator state in STOP mode ---------------------------------*/
<> 144:ef7eb2e8f9f7 337 tmpreg = PWR->CR;
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Clear PDDS and LPDS bits */
<> 144:ef7eb2e8f9f7 340 tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Set LPDS bit according to Regulator value */
<> 144:ef7eb2e8f9f7 343 tmpreg |= Regulator;
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Store the new value */
<> 144:ef7eb2e8f9f7 346 PWR->CR = tmpreg;
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 349 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Select STOP mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 352 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 355 __WFI();
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357 else
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 360 __SEV();
<> 144:ef7eb2e8f9f7 361 __WFE();
<> 144:ef7eb2e8f9f7 362 __WFE();
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 366 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /**
<> 144:ef7eb2e8f9f7 370 * @brief Enters STANDBY mode.
<> 144:ef7eb2e8f9f7 371 * @note In Standby mode, all I/O pins are high impedance except for:
<> 144:ef7eb2e8f9f7 372 * - Reset pad (still available)
<> 144:ef7eb2e8f9f7 373 * - RTC alternate function pins if configured for tamper, time-stamp, RTC
<> 144:ef7eb2e8f9f7 374 * Alarm out, or RTC clock calibration out.
<> 144:ef7eb2e8f9f7 375 * - WKUP pins if enabled.
<> 144:ef7eb2e8f9f7 376 * STM32F0x8 devices, the Stop mode is available, but it is
<> 144:ef7eb2e8f9f7 377 * aningless to distinguish between voltage regulator in Low power
<> 144:ef7eb2e8f9f7 378 * mode and voltage regulator in Run mode because the regulator
<> 144:ef7eb2e8f9f7 379 * not used and the core is supplied directly from an external source.
<> 144:ef7eb2e8f9f7 380 * Consequently, the Standby mode is not available on those devices.
<> 144:ef7eb2e8f9f7 381 * @retval None
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 void HAL_PWR_EnterSTANDBYMode(void)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 /* Select STANDBY mode */
<> 144:ef7eb2e8f9f7 386 PWR->CR |= (uint32_t)PWR_CR_PDDS;
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 389 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* This option is used to ensure that store operations are completed */
<> 144:ef7eb2e8f9f7 392 #if defined ( __CC_ARM)
<> 144:ef7eb2e8f9f7 393 __force_stores();
<> 144:ef7eb2e8f9f7 394 #endif
<> 144:ef7eb2e8f9f7 395 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 396 __WFI();
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /**
<> 144:ef7eb2e8f9f7 400 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
<> 144:ef7eb2e8f9f7 401 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
<> 144:ef7eb2e8f9f7 402 * re-enters SLEEP mode when an interruption handling is over.
<> 144:ef7eb2e8f9f7 403 * Setting this bit is useful when the processor is expected to run only on
<> 144:ef7eb2e8f9f7 404 * interruptions handling.
<> 144:ef7eb2e8f9f7 405 * @retval None
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407 void HAL_PWR_EnableSleepOnExit(void)
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 /* Set SLEEPONEXIT bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 410 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
<> 144:ef7eb2e8f9f7 416 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
<> 144:ef7eb2e8f9f7 417 * re-enters SLEEP mode when an interruption handling is over.
<> 144:ef7eb2e8f9f7 418 * @retval None
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 void HAL_PWR_DisableSleepOnExit(void)
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 423 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @brief Enables CORTEX M4 SEVONPEND bit.
<> 144:ef7eb2e8f9f7 430 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
<> 144:ef7eb2e8f9f7 431 * WFE to wake up when an interrupt moves from inactive to pended.
<> 144:ef7eb2e8f9f7 432 * @retval None
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434 void HAL_PWR_EnableSEVOnPend(void)
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 /* Set SEVONPEND bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 437 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /**
<> 144:ef7eb2e8f9f7 442 * @brief Disables CORTEX M4 SEVONPEND bit.
<> 144:ef7eb2e8f9f7 443 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
<> 144:ef7eb2e8f9f7 444 * WFE to wake up when an interrupt moves from inactive to pended.
<> 144:ef7eb2e8f9f7 445 * @retval None
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 void HAL_PWR_DisableSEVOnPend(void)
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 /* Clear SEVONPEND bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 450 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @}
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /**
<> 144:ef7eb2e8f9f7 458 * @}
<> 144:ef7eb2e8f9f7 459 */
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 #endif /* HAL_PWR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @}
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @}
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/