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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_irda.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief This file contains all the functions prototypes for the IRDA
<> 144:ef7eb2e8f9f7 6 * firmware library.
<> 144:ef7eb2e8f9f7 7 ******************************************************************************
<> 144:ef7eb2e8f9f7 8 * @attention
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 13 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 14 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 15 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 18 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 20 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 21 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 33 *
<> 144:ef7eb2e8f9f7 34 ******************************************************************************
<> 144:ef7eb2e8f9f7 35 */
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 38 #ifndef __STM32F0xx_HAL_IRDA_H
<> 144:ef7eb2e8f9f7 39 #define __STM32F0xx_HAL_IRDA_H
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 42 extern "C" {
<> 144:ef7eb2e8f9f7 43 #endif
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 48 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup IRDA
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 156:95d6b41a828b 58 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup IRDA_Exported_Types IRDA Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief IRDA Init Structure definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
<> 144:ef7eb2e8f9f7 69 The baud rate register is computed using the following formula:
<> 144:ef7eb2e8f9f7 70 Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref IRDAEx_Word_Length */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t Parity; /*!< Specifies the parity mode.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref IRDA_Parity
<> 144:ef7eb2e8f9f7 77 @note When parity is enabled, the computed parity is inserted
<> 144:ef7eb2e8f9f7 78 at the MSB position of the transmitted data (9th bit when
<> 144:ef7eb2e8f9f7 79 the word length is set to 9 data bits; 8th bit when the
<> 144:ef7eb2e8f9f7 80 word length is set to 8 data bits). */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
<> 144:ef7eb2e8f9f7 83 This parameter can be a value of @ref IRDA_Transfer_Mode */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
<> 144:ef7eb2e8f9f7 86 to achieve low-power frequency.
<> 144:ef7eb2e8f9f7 87 @note Prescaler value 0 is forbidden */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint16_t PowerMode; /*!< Specifies the IRDA power mode.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref IRDA_Low_Power */
<> 144:ef7eb2e8f9f7 91 }IRDA_InitTypeDef;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @brief HAL IRDA State structures definition
<> 144:ef7eb2e8f9f7 95 * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
<> 144:ef7eb2e8f9f7 96 * - gState contains IRDA state information related to global Handle management
<> 144:ef7eb2e8f9f7 97 * and also information related to Tx operations.
<> 144:ef7eb2e8f9f7 98 * gState value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 99 * b7-b6 Error information
<> 144:ef7eb2e8f9f7 100 * 00 : No Error
<> 144:ef7eb2e8f9f7 101 * 01 : (Not Used)
<> 144:ef7eb2e8f9f7 102 * 10 : Timeout
<> 144:ef7eb2e8f9f7 103 * 11 : Error
<> 144:ef7eb2e8f9f7 104 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 105 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 106 * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
<> 144:ef7eb2e8f9f7 107 * b4-b3 (not used)
<> 144:ef7eb2e8f9f7 108 * xx : Should be set to 00
<> 144:ef7eb2e8f9f7 109 * b2 Intrinsic process state
<> 144:ef7eb2e8f9f7 110 * 0 : Ready
<> 144:ef7eb2e8f9f7 111 * 1 : Busy (IP busy with some configuration or internal operations)
<> 144:ef7eb2e8f9f7 112 * b1 (not used)
<> 144:ef7eb2e8f9f7 113 * x : Should be set to 0
<> 144:ef7eb2e8f9f7 114 * b0 Tx state
<> 144:ef7eb2e8f9f7 115 * 0 : Ready (no Tx operation ongoing)
<> 144:ef7eb2e8f9f7 116 * 1 : Busy (Tx operation ongoing)
<> 144:ef7eb2e8f9f7 117 * - RxState contains information related to Rx operations.
<> 144:ef7eb2e8f9f7 118 * RxState value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 119 * b7-b6 (not used)
<> 144:ef7eb2e8f9f7 120 * xx : Should be set to 00
<> 144:ef7eb2e8f9f7 121 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 122 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 123 * 1 : Init done (IP not initialized)
<> 144:ef7eb2e8f9f7 124 * b4-b2 (not used)
<> 144:ef7eb2e8f9f7 125 * xxx : Should be set to 000
<> 144:ef7eb2e8f9f7 126 * b1 Rx state
<> 144:ef7eb2e8f9f7 127 * 0 : Ready (no Rx operation ongoing)
<> 144:ef7eb2e8f9f7 128 * 1 : Busy (Rx operation ongoing)
<> 144:ef7eb2e8f9f7 129 * b0 (not used)
<> 144:ef7eb2e8f9f7 130 * x : Should be set to 0.
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 typedef enum
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
<> 144:ef7eb2e8f9f7 135 Value is allowed for gState and RxState */
<> 144:ef7eb2e8f9f7 136 HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
<> 144:ef7eb2e8f9f7 137 Value is allowed for gState and RxState */
<> 144:ef7eb2e8f9f7 138 HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
<> 144:ef7eb2e8f9f7 139 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 140 HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
<> 144:ef7eb2e8f9f7 141 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 142 HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
<> 144:ef7eb2e8f9f7 143 Value is allowed for RxState only */
<> 144:ef7eb2e8f9f7 144 HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
<> 144:ef7eb2e8f9f7 145 Not to be used for neither gState nor RxState.
<> 144:ef7eb2e8f9f7 146 Value is result of combination (Or) between gState and RxState values */
<> 144:ef7eb2e8f9f7 147 HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
<> 144:ef7eb2e8f9f7 148 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 149 HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
<> 144:ef7eb2e8f9f7 150 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 151 }HAL_IRDA_StateTypeDef;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @brief IRDA clock sources definition
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 typedef enum
<> 144:ef7eb2e8f9f7 157 {
<> 156:95d6b41a828b 158 IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
<> 156:95d6b41a828b 159 IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
<> 156:95d6b41a828b 160 IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
<> 156:95d6b41a828b 161 IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
<> 156:95d6b41a828b 162 IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
<> 144:ef7eb2e8f9f7 163 }IRDA_ClockSourceTypeDef;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /**
<> 144:ef7eb2e8f9f7 166 * @brief IRDA handle Structure definition
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168 typedef struct
<> 144:ef7eb2e8f9f7 169 {
<> 156:95d6b41a828b 170 USART_TypeDef *Instance; /*!< IRDA registers base address */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
<> 144:ef7eb2e8f9f7 177
<> 156:95d6b41a828b 178 __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
<> 144:ef7eb2e8f9f7 183
<> 156:95d6b41a828b 184 __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 185
<> 156:95d6b41a828b 186 uint16_t Mask; /*!< IRDA RX RDR register mask */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 HAL_LockTypeDef Lock; /*!< Locking object */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
<> 144:ef7eb2e8f9f7 195 and also related to Tx operations.
<> 144:ef7eb2e8f9f7 196 This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
<> 144:ef7eb2e8f9f7 199 This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 __IO uint32_t ErrorCode; /*!< IRDA Error code
<> 144:ef7eb2e8f9f7 202 This parameter can be a value of @ref IRDA_Error */
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 }IRDA_HandleTypeDef;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief IRDA Configuration enumeration values definition
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 typedef enum
<> 144:ef7eb2e8f9f7 210 {
<> 156:95d6b41a828b 211 IRDA_BAUDRATE = 0x00U, /*!< IRDA Baud rate */
<> 156:95d6b41a828b 212 IRDA_PARITY = 0x01U, /*!< IRDA frame parity */
<> 156:95d6b41a828b 213 IRDA_WORDLENGTH = 0x02U, /*!< IRDA frame length */
<> 156:95d6b41a828b 214 IRDA_MODE = 0x03U, /*!< IRDA communication mode */
<> 156:95d6b41a828b 215 IRDA_PRESCALER = 0x04U, /*!< IRDA prescaling */
<> 156:95d6b41a828b 216 IRDA_POWERMODE = 0x05U /*!< IRDA power mode */
<> 144:ef7eb2e8f9f7 217 }IRDA_ControlTypeDef;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /**
<> 144:ef7eb2e8f9f7 220 * @}
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 224 /** @defgroup IRDA_Exported_Constants IRDA Exported Constants
<> 144:ef7eb2e8f9f7 225 * @{
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /** @defgroup IRDA_Error IRDA Error
<> 144:ef7eb2e8f9f7 229 * @{
<> 144:ef7eb2e8f9f7 230 */
<> 156:95d6b41a828b 231 #define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 232 #define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
<> 156:95d6b41a828b 233 #define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
<> 156:95d6b41a828b 234 #define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
<> 156:95d6b41a828b 235 #define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
<> 156:95d6b41a828b 236 #define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
<> 156:95d6b41a828b 237 #define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
<> 144:ef7eb2e8f9f7 238 /**
<> 144:ef7eb2e8f9f7 239 * @}
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /** @defgroup IRDA_Parity IRDA Parity
<> 144:ef7eb2e8f9f7 243 * @{
<> 144:ef7eb2e8f9f7 244 */
<> 156:95d6b41a828b 245 #define IRDA_PARITY_NONE (0x00000000U) /*!< No parity */
<> 144:ef7eb2e8f9f7 246 #define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
<> 144:ef7eb2e8f9f7 247 #define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @}
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
<> 144:ef7eb2e8f9f7 253 * @{
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 #define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
<> 144:ef7eb2e8f9f7 256 #define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
<> 144:ef7eb2e8f9f7 257 #define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @}
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /** @defgroup IRDA_Low_Power IRDA Low Power
<> 144:ef7eb2e8f9f7 263 * @{
<> 144:ef7eb2e8f9f7 264 */
<> 156:95d6b41a828b 265 #define IRDA_POWERMODE_NORMAL (0x00000000U) /*!< IRDA normal power mode */
<> 144:ef7eb2e8f9f7 266 #define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */
<> 144:ef7eb2e8f9f7 267 /**
<> 144:ef7eb2e8f9f7 268 * @}
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /** @defgroup IRDA_State IRDA State
<> 144:ef7eb2e8f9f7 272 * @{
<> 144:ef7eb2e8f9f7 273 */
<> 156:95d6b41a828b 274 #define IRDA_STATE_DISABLE (0x00000000U) /*!< IRDA disabled */
<> 144:ef7eb2e8f9f7 275 #define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @}
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /** @defgroup IRDA_Mode IRDA Mode
<> 144:ef7eb2e8f9f7 281 * @{
<> 144:ef7eb2e8f9f7 282 */
<> 156:95d6b41a828b 283 #define IRDA_MODE_DISABLE (0x00000000U) /*!< Associated UART disabled in IRDA mode */
<> 144:ef7eb2e8f9f7 284 #define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** @defgroup IRDA_One_Bit IRDA One Bit Sampling
<> 144:ef7eb2e8f9f7 290 * @{
<> 144:ef7eb2e8f9f7 291 */
<> 156:95d6b41a828b 292 #define IRDA_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disabled */
<> 144:ef7eb2e8f9f7 293 #define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @}
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /** @defgroup IRDA_DMA_Tx IRDA DMA Tx
<> 144:ef7eb2e8f9f7 299 * @{
<> 144:ef7eb2e8f9f7 300 */
<> 156:95d6b41a828b 301 #define IRDA_DMA_TX_DISABLE (0x00000000U) /*!< IRDA DMA TX disabled */
<> 144:ef7eb2e8f9f7 302 #define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @}
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /** @defgroup IRDA_DMA_Rx IRDA DMA Rx
<> 144:ef7eb2e8f9f7 308 * @{
<> 144:ef7eb2e8f9f7 309 */
<> 156:95d6b41a828b 310 #define IRDA_DMA_RX_DISABLE (0x00000000U) /*!< IRDA DMA RX disabled */
<> 144:ef7eb2e8f9f7 311 #define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */
<> 144:ef7eb2e8f9f7 312 /**
<> 144:ef7eb2e8f9f7 313 * @}
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /** @defgroup IRDA_Request_Parameters IRDA Request Parameters
<> 144:ef7eb2e8f9f7 317 * @{
<> 144:ef7eb2e8f9f7 318 */
<> 156:95d6b41a828b 319 #define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
<> 156:95d6b41a828b 320 #define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
<> 144:ef7eb2e8f9f7 321 #define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /** @defgroup IRDA_Flags IRDA Flags
<> 144:ef7eb2e8f9f7 327 * Elements values convention: 0xXXXX
<> 144:ef7eb2e8f9f7 328 * - 0xXXXX : Flag mask in the ISR register
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
<> 156:95d6b41a828b 331 #define IRDA_FLAG_REACK (0x00400000U) /*!< IRDA Receive enable acknowledge flag */
<> 156:95d6b41a828b 332 #define IRDA_FLAG_TEACK (0x00200000U) /*!< IRDA Transmit enable acknowledge flag */
<> 156:95d6b41a828b 333 #define IRDA_FLAG_BUSY (0x00010000U) /*!< IRDA Busy flag */
<> 156:95d6b41a828b 334 #define IRDA_FLAG_ABRF (0x00008000U) /*!< IRDA Auto baud rate flag */
<> 156:95d6b41a828b 335 #define IRDA_FLAG_ABRE (0x00004000U) /*!< IRDA Auto baud rate error */
<> 156:95d6b41a828b 336 #define IRDA_FLAG_TXE (0x00000080U) /*!< IRDA Transmit data register empty */
<> 156:95d6b41a828b 337 #define IRDA_FLAG_TC (0x00000040U) /*!< IRDA Transmission complete */
<> 156:95d6b41a828b 338 #define IRDA_FLAG_RXNE (0x00000020U) /*!< IRDA Read data register not empty */
<> 156:95d6b41a828b 339 #define IRDA_FLAG_ORE (0x00000008U) /*!< IRDA Overrun error */
<> 156:95d6b41a828b 340 #define IRDA_FLAG_NE (0x00000004U) /*!< IRDA Noise error */
<> 156:95d6b41a828b 341 #define IRDA_FLAG_FE (0x00000002U) /*!< IRDA Framing error */
<> 156:95d6b41a828b 342 #define IRDA_FLAG_PE (0x00000001U) /*!< IRDA Parity error */
<> 144:ef7eb2e8f9f7 343 /**
<> 144:ef7eb2e8f9f7 344 * @}
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
<> 144:ef7eb2e8f9f7 348 * Elements values convention: 0000ZZZZ0XXYYYYYb
<> 144:ef7eb2e8f9f7 349 * - YYYYY : Interrupt source position in the XX register (5bits)
<> 144:ef7eb2e8f9f7 350 * - XX : Interrupt source register (2bits)
<> 144:ef7eb2e8f9f7 351 * - 01: CR1 register
<> 144:ef7eb2e8f9f7 352 * - 10: CR2 register
<> 144:ef7eb2e8f9f7 353 * - 11: CR3 register
<> 144:ef7eb2e8f9f7 354 * - ZZZZ : Flag position in the ISR register(4bits)
<> 144:ef7eb2e8f9f7 355 * @{
<> 144:ef7eb2e8f9f7 356 */
<> 156:95d6b41a828b 357 #define IRDA_IT_PE ((uint16_t)0x0028U) /*!< IRDA Parity error interruption */
<> 156:95d6b41a828b 358 #define IRDA_IT_TXE ((uint16_t)0x0727U) /*!< IRDA Transmit data register empty interruption */
<> 156:95d6b41a828b 359 #define IRDA_IT_TC ((uint16_t)0x0626U) /*!< IRDA Transmission complete interruption */
<> 156:95d6b41a828b 360 #define IRDA_IT_RXNE ((uint16_t)0x0525U) /*!< IRDA Read data register not empty interruption */
<> 156:95d6b41a828b 361 #define IRDA_IT_IDLE ((uint16_t)0x0424U) /*!< IRDA Idle interruption */
Anna Bridge 180:96ed750bd169 362 #define IRDA_IT_ERR ((uint16_t)0x0060U) /*!< IRDA Error interruption */
Anna Bridge 180:96ed750bd169 363 #define IRDA_IT_ORE ((uint16_t)0x0300U) /*!< IRDA Overrun error interruption */
Anna Bridge 180:96ed750bd169 364 #define IRDA_IT_NE ((uint16_t)0x0200U) /*!< IRDA Noise error interruption */
Anna Bridge 180:96ed750bd169 365 #define IRDA_IT_FE ((uint16_t)0x0100U) /*!< IRDA Frame error interruption */
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @}
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
<> 144:ef7eb2e8f9f7 371 * @{
<> 144:ef7eb2e8f9f7 372 */
<> 156:95d6b41a828b 373 #define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
<> 156:95d6b41a828b 374 #define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
<> 156:95d6b41a828b 375 #define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
<> 156:95d6b41a828b 376 #define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
<> 156:95d6b41a828b 377 #define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
<> 156:95d6b41a828b 378 #define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
<> 144:ef7eb2e8f9f7 379 /**
<> 144:ef7eb2e8f9f7 380 * @}
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
<> 144:ef7eb2e8f9f7 384 * @{
<> 144:ef7eb2e8f9f7 385 */
<> 156:95d6b41a828b 386 #define IRDA_IT_MASK ((uint16_t)0x001FU) /*!< IRDA Interruptions flags mask */
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @}
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @}
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 397 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
<> 144:ef7eb2e8f9f7 398 * @{
<> 144:ef7eb2e8f9f7 399 */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /** @brief Reset IRDA handle state.
Anna Bridge 180:96ed750bd169 402 * @param __HANDLE__ IRDA handle.
<> 144:ef7eb2e8f9f7 403 * @retval None
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
<> 144:ef7eb2e8f9f7 406 (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
<> 144:ef7eb2e8f9f7 407 (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
<> 144:ef7eb2e8f9f7 408 } while(0)
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /** @brief Flush the IRDA DR register.
Anna Bridge 180:96ed750bd169 411 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 412 * @retval None
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 415 do{ \
<> 144:ef7eb2e8f9f7 416 SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 417 SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 418 } while(0)
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /** @brief Clear the specified IRDA pending flag.
Anna Bridge 180:96ed750bd169 421 * @param __HANDLE__ specifies the IRDA Handle.
Anna Bridge 180:96ed750bd169 422 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 423 * This parameter can be any combination of the following values:
<> 156:95d6b41a828b 424 * @arg @ref IRDA_CLEAR_PEF
<> 156:95d6b41a828b 425 * @arg @ref IRDA_CLEAR_FEF
<> 156:95d6b41a828b 426 * @arg @ref IRDA_CLEAR_NEF
<> 156:95d6b41a828b 427 * @arg @ref IRDA_CLEAR_OREF
<> 156:95d6b41a828b 428 * @arg @ref IRDA_CLEAR_TCF
<> 156:95d6b41a828b 429 * @arg @ref IRDA_CLEAR_IDLEF
<> 144:ef7eb2e8f9f7 430 * @retval None
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /** @brief Clear the IRDA PE pending flag.
Anna Bridge 180:96ed750bd169 435 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 436 * @retval None
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /** @brief Clear the IRDA FE pending flag.
Anna Bridge 180:96ed750bd169 442 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 443 * @retval None
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /** @brief Clear the IRDA NE pending flag.
Anna Bridge 180:96ed750bd169 448 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 449 * @retval None
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /** @brief Clear the IRDA ORE pending flag.
Anna Bridge 180:96ed750bd169 454 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 455 * @retval None
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /** @brief Clear the IRDA IDLE pending flag.
Anna Bridge 180:96ed750bd169 460 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 461 * @retval None
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /** @brief Check whether the specified IRDA flag is set or not.
Anna Bridge 180:96ed750bd169 466 * @param __HANDLE__ specifies the IRDA Handle.
Anna Bridge 180:96ed750bd169 467 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 468 * This parameter can be one of the following values:
<> 156:95d6b41a828b 469 * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
<> 156:95d6b41a828b 470 * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
<> 156:95d6b41a828b 471 * @arg @ref IRDA_FLAG_BUSY Busy flag
<> 156:95d6b41a828b 472 * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
<> 156:95d6b41a828b 473 * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
<> 156:95d6b41a828b 474 * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
<> 156:95d6b41a828b 475 * @arg @ref IRDA_FLAG_TC Transmission Complete flag
<> 156:95d6b41a828b 476 * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
<> 156:95d6b41a828b 477 * @arg @ref IRDA_FLAG_ORE OverRun Error flag
<> 156:95d6b41a828b 478 * @arg @ref IRDA_FLAG_NE Noise Error flag
<> 156:95d6b41a828b 479 * @arg @ref IRDA_FLAG_FE Framing Error flag
<> 156:95d6b41a828b 480 * @arg @ref IRDA_FLAG_PE Parity Error flag
<> 144:ef7eb2e8f9f7 481 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /** @brief Enable the specified IRDA interrupt.
Anna Bridge 180:96ed750bd169 487 * @param __HANDLE__ specifies the IRDA Handle.
Anna Bridge 180:96ed750bd169 488 * @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
<> 144:ef7eb2e8f9f7 489 * This parameter can be one of the following values:
<> 156:95d6b41a828b 490 * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
<> 156:95d6b41a828b 491 * @arg @ref IRDA_IT_TC Transmission complete interrupt
<> 156:95d6b41a828b 492 * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
<> 156:95d6b41a828b 493 * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
<> 156:95d6b41a828b 494 * @arg @ref IRDA_IT_PE Parity Error interrupt
<> 156:95d6b41a828b 495 * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 496 * @retval None
<> 144:ef7eb2e8f9f7 497 */
<> 156:95d6b41a828b 498 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
<> 156:95d6b41a828b 499 ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
<> 144:ef7eb2e8f9f7 500 ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /** @brief Disable the specified IRDA interrupt.
Anna Bridge 180:96ed750bd169 503 * @param __HANDLE__ specifies the IRDA Handle.
Anna Bridge 180:96ed750bd169 504 * @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
<> 144:ef7eb2e8f9f7 505 * This parameter can be one of the following values:
<> 156:95d6b41a828b 506 * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
<> 156:95d6b41a828b 507 * @arg @ref IRDA_IT_TC Transmission complete interrupt
<> 156:95d6b41a828b 508 * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
<> 156:95d6b41a828b 509 * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
<> 156:95d6b41a828b 510 * @arg @ref IRDA_IT_PE Parity Error interrupt
<> 156:95d6b41a828b 511 * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 512 * @retval None
<> 144:ef7eb2e8f9f7 513 */
<> 156:95d6b41a828b 514 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
<> 156:95d6b41a828b 515 ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
<> 144:ef7eb2e8f9f7 516 ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /** @brief Check whether the specified IRDA interrupt has occurred or not.
Anna Bridge 180:96ed750bd169 520 * @param __HANDLE__ specifies the IRDA Handle.
Anna Bridge 180:96ed750bd169 521 * @param __IT__ specifies the IRDA interrupt source to check.
<> 144:ef7eb2e8f9f7 522 * This parameter can be one of the following values:
<> 156:95d6b41a828b 523 * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
<> 156:95d6b41a828b 524 * @arg @ref IRDA_IT_TC Transmission complete interrupt
<> 156:95d6b41a828b 525 * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
<> 156:95d6b41a828b 526 * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
<> 156:95d6b41a828b 527 * @arg @ref IRDA_IT_ORE OverRun Error interrupt
<> 156:95d6b41a828b 528 * @arg @ref IRDA_IT_NE Noise Error interrupt
<> 156:95d6b41a828b 529 * @arg @ref IRDA_IT_FE Framing Error interrupt
<> 156:95d6b41a828b 530 * @arg @ref IRDA_IT_PE Parity Error interrupt
<> 144:ef7eb2e8f9f7 531 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 532 */
<> 156:95d6b41a828b 533 #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /** @brief Check whether the specified IRDA interrupt source is enabled or not.
Anna Bridge 180:96ed750bd169 536 * @param __HANDLE__ specifies the IRDA Handle.
Anna Bridge 180:96ed750bd169 537 * @param __IT__ specifies the IRDA interrupt source to check.
<> 144:ef7eb2e8f9f7 538 * This parameter can be one of the following values:
<> 156:95d6b41a828b 539 * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
<> 156:95d6b41a828b 540 * @arg @ref IRDA_IT_TC Transmission complete interrupt
<> 156:95d6b41a828b 541 * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
<> 156:95d6b41a828b 542 * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
<> 156:95d6b41a828b 543 * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
<> 156:95d6b41a828b 544 * @arg @ref IRDA_IT_PE Parity Error interrupt
<> 144:ef7eb2e8f9f7 545 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 546 */
<> 156:95d6b41a828b 547 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
<> 156:95d6b41a828b 548 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
Anna Bridge 180:96ed750bd169 552 * @param __HANDLE__ specifies the IRDA Handle.
Anna Bridge 180:96ed750bd169 553 * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
<> 144:ef7eb2e8f9f7 554 * to clear the corresponding interrupt
<> 144:ef7eb2e8f9f7 555 * This parameter can be one of the following values:
<> 156:95d6b41a828b 556 * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
<> 156:95d6b41a828b 557 * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
<> 156:95d6b41a828b 558 * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
<> 156:95d6b41a828b 559 * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
<> 156:95d6b41a828b 560 * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
<> 144:ef7eb2e8f9f7 561 * @retval None
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /** @brief Set a specific IRDA request flag.
Anna Bridge 180:96ed750bd169 567 * @param __HANDLE__ specifies the IRDA Handle.
Anna Bridge 180:96ed750bd169 568 * @param __REQ__ specifies the request flag to set
<> 144:ef7eb2e8f9f7 569 * This parameter can be one of the following values:
<> 156:95d6b41a828b 570 * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
<> 156:95d6b41a828b 571 * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
<> 156:95d6b41a828b 572 * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
<> 144:ef7eb2e8f9f7 573 *
<> 144:ef7eb2e8f9f7 574 * @retval None
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /** @brief Enable the IRDA one bit sample method.
Anna Bridge 180:96ed750bd169 579 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 580 * @retval None
<> 156:95d6b41a828b 581 */
<> 144:ef7eb2e8f9f7 582 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /** @brief Disable the IRDA one bit sample method.
Anna Bridge 180:96ed750bd169 585 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 586 * @retval None
<> 156:95d6b41a828b 587 */
<> 144:ef7eb2e8f9f7 588 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /** @brief Enable UART/USART associated to IRDA Handle.
Anna Bridge 180:96ed750bd169 591 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 592 * @retval None
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594 #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /** @brief Disable UART/USART associated to IRDA Handle.
Anna Bridge 180:96ed750bd169 597 * @param __HANDLE__ specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 598 * @retval None
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600 #define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /**
<> 144:ef7eb2e8f9f7 603 * @}
<> 144:ef7eb2e8f9f7 604 */
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /* Private macros --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 607 /** @defgroup IRDA_Private_Macros IRDA Private Macros
<> 144:ef7eb2e8f9f7 608 * @{
<> 144:ef7eb2e8f9f7 609 */
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
Anna Bridge 180:96ed750bd169 612 * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
<> 144:ef7eb2e8f9f7 613 * @retval True or False
<> 144:ef7eb2e8f9f7 614 */
<> 156:95d6b41a828b 615 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /** @brief Ensure that IRDA prescaler value is strictly larger than 0.
Anna Bridge 180:96ed750bd169 618 * @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
<> 144:ef7eb2e8f9f7 619 * @retval True or False
<> 144:ef7eb2e8f9f7 620 */
<> 156:95d6b41a828b 621 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /**
<> 144:ef7eb2e8f9f7 624 * @brief Ensure that IRDA frame parity is valid.
Anna Bridge 180:96ed750bd169 625 * @param __PARITY__ IRDA frame parity.
<> 144:ef7eb2e8f9f7 626 * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
<> 144:ef7eb2e8f9f7 629 ((__PARITY__) == IRDA_PARITY_EVEN) || \
<> 144:ef7eb2e8f9f7 630 ((__PARITY__) == IRDA_PARITY_ODD))
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /**
<> 144:ef7eb2e8f9f7 633 * @brief Ensure that IRDA communication mode is valid.
Anna Bridge 180:96ed750bd169 634 * @param __MODE__ IRDA communication mode.
<> 144:ef7eb2e8f9f7 635 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<> 144:ef7eb2e8f9f7 636 */
<> 156:95d6b41a828b 637 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /**
<> 144:ef7eb2e8f9f7 640 * @brief Ensure that IRDA power mode is valid.
Anna Bridge 180:96ed750bd169 641 * @param __MODE__ IRDA power mode.
<> 144:ef7eb2e8f9f7 642 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
<> 144:ef7eb2e8f9f7 645 ((__MODE__) == IRDA_POWERMODE_NORMAL))
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /**
<> 144:ef7eb2e8f9f7 648 * @brief Ensure that IRDA state is valid.
Anna Bridge 180:96ed750bd169 649 * @param __STATE__ IRDA state mode.
<> 144:ef7eb2e8f9f7 650 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
<> 144:ef7eb2e8f9f7 651 */
<> 144:ef7eb2e8f9f7 652 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
<> 144:ef7eb2e8f9f7 653 ((__STATE__) == IRDA_STATE_ENABLE))
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /**
<> 144:ef7eb2e8f9f7 656 * @brief Ensure that IRDA associated UART/USART mode is valid.
Anna Bridge 180:96ed750bd169 657 * @param __MODE__ IRDA associated UART/USART mode.
<> 144:ef7eb2e8f9f7 658 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660 #define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 661 ((__MODE__) == IRDA_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /**
<> 144:ef7eb2e8f9f7 664 * @brief Ensure that IRDA sampling rate is valid.
Anna Bridge 180:96ed750bd169 665 * @param __ONEBIT__ IRDA sampling rate.
<> 144:ef7eb2e8f9f7 666 * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
<> 144:ef7eb2e8f9f7 667 */
<> 144:ef7eb2e8f9f7 668 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
<> 144:ef7eb2e8f9f7 669 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /**
<> 144:ef7eb2e8f9f7 672 * @brief Ensure that IRDA DMA TX mode is valid.
Anna Bridge 180:96ed750bd169 673 * @param __DMATX__ IRDA DMA TX mode.
<> 144:ef7eb2e8f9f7 674 * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
<> 144:ef7eb2e8f9f7 675 */
<> 144:ef7eb2e8f9f7 676 #define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
<> 144:ef7eb2e8f9f7 677 ((__DMATX__) == IRDA_DMA_TX_ENABLE))
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @brief Ensure that IRDA DMA RX mode is valid.
Anna Bridge 180:96ed750bd169 681 * @param __DMARX__ IRDA DMA RX mode.
<> 144:ef7eb2e8f9f7 682 * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
<> 144:ef7eb2e8f9f7 683 */
<> 144:ef7eb2e8f9f7 684 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
<> 144:ef7eb2e8f9f7 685 ((__DMARX__) == IRDA_DMA_RX_ENABLE))
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /**
<> 144:ef7eb2e8f9f7 688 * @brief Ensure that IRDA request is valid.
Anna Bridge 180:96ed750bd169 689 * @param __PARAM__ IRDA request.
<> 144:ef7eb2e8f9f7 690 * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
<> 144:ef7eb2e8f9f7 691 */
<> 144:ef7eb2e8f9f7 692 #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
<> 144:ef7eb2e8f9f7 693 ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
<> 144:ef7eb2e8f9f7 694 ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
<> 144:ef7eb2e8f9f7 695 /**
<> 144:ef7eb2e8f9f7 696 * @}
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Include IRDA HAL Extended module */
<> 144:ef7eb2e8f9f7 700 #include "stm32f0xx_hal_irda_ex.h"
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 703 /** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
<> 144:ef7eb2e8f9f7 704 * @{
<> 144:ef7eb2e8f9f7 705 */
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 708 * @{
<> 144:ef7eb2e8f9f7 709 */
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 712 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 713 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 714 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 715 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /**
<> 144:ef7eb2e8f9f7 718 * @}
<> 144:ef7eb2e8f9f7 719 */
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 722 * @{
<> 144:ef7eb2e8f9f7 723 */
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 726 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 727 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 728 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 729 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 730 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 731 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 732 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 733 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 734 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 735 /* Transfer Abort functions */
<> 156:95d6b41a828b 736 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 737 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 738 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 739 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 740 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 741 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 742
<> 144:ef7eb2e8f9f7 743 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 744 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 745 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 746 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 747 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 748 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 749 void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 750 void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
<> 156:95d6b41a828b 751 void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /**
<> 144:ef7eb2e8f9f7 754 * @}
<> 144:ef7eb2e8f9f7 755 */
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 760 * @{
<> 144:ef7eb2e8f9f7 761 */
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 764 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 765 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /**
<> 144:ef7eb2e8f9f7 768 * @}
<> 144:ef7eb2e8f9f7 769 */
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /**
<> 144:ef7eb2e8f9f7 772 * @}
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /**
<> 144:ef7eb2e8f9f7 776 * @}
<> 144:ef7eb2e8f9f7 777 */
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /**
<> 144:ef7eb2e8f9f7 780 * @}
<> 144:ef7eb2e8f9f7 781 */
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787 #endif
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 #endif /* __STM32F0xx_HAL_IRDA_H */
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 792