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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_i2c.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of I2C HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_I2C_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_I2C_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
Anna Bridge 180:96ed750bd169 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup I2C
<> 144:ef7eb2e8f9f7 52 * @{
Anna Bridge 180:96ed750bd169 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /** @defgroup I2C_Exported_Types I2C Exported Types
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
Anna Bridge 180:96ed750bd169 61 * @brief I2C Configuration Structure definition
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
Anna Bridge 180:96ed750bd169 67 This parameter calculated by referring to I2C initialization
<> 144:ef7eb2e8f9f7 68 section in Reference manual */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t OwnAddress1; /*!< Specifies the first device own address.
<> 144:ef7eb2e8f9f7 71 This parameter can be a 7-bit or 10-bit address. */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref I2C_ADDRESSING_MODE */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
<> 144:ef7eb2e8f9f7 80 This parameter can be a 7-bit address. */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
<> 144:ef7eb2e8f9f7 83 This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
<> 144:ef7eb2e8f9f7 89 This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
<> 144:ef7eb2e8f9f7 90
Anna Bridge 180:96ed750bd169 91 } I2C_InitTypeDef;
<> 144:ef7eb2e8f9f7 92
Anna Bridge 180:96ed750bd169 93 /**
<> 144:ef7eb2e8f9f7 94 * @}
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /** @defgroup HAL_state_structure_definition HAL state structure definition
<> 144:ef7eb2e8f9f7 98 * @brief HAL State structure definition
<> 144:ef7eb2e8f9f7 99 * @note HAL I2C State value coding follow below described bitmap :\n
<> 144:ef7eb2e8f9f7 100 * b7-b6 Error information\n
<> 144:ef7eb2e8f9f7 101 * 00 : No Error\n
<> 144:ef7eb2e8f9f7 102 * 01 : Abort (Abort user request on going)\n
<> 144:ef7eb2e8f9f7 103 * 10 : Timeout\n
<> 144:ef7eb2e8f9f7 104 * 11 : Error\n
<> 144:ef7eb2e8f9f7 105 * b5 IP initilisation status\n
<> 144:ef7eb2e8f9f7 106 * 0 : Reset (IP not initialized)\n
<> 144:ef7eb2e8f9f7 107 * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
<> 144:ef7eb2e8f9f7 108 * b4 (not used)\n
<> 144:ef7eb2e8f9f7 109 * x : Should be set to 0\n
<> 144:ef7eb2e8f9f7 110 * b3\n
<> 144:ef7eb2e8f9f7 111 * 0 : Ready or Busy (No Listen mode ongoing)\n
<> 144:ef7eb2e8f9f7 112 * 1 : Listen (IP in Address Listen Mode)\n
<> 144:ef7eb2e8f9f7 113 * b2 Intrinsic process state\n
<> 144:ef7eb2e8f9f7 114 * 0 : Ready\n
<> 144:ef7eb2e8f9f7 115 * 1 : Busy (IP busy with some configuration or internal operations)\n
<> 144:ef7eb2e8f9f7 116 * b1 Rx state\n
<> 144:ef7eb2e8f9f7 117 * 0 : Ready (no Rx operation ongoing)\n
<> 144:ef7eb2e8f9f7 118 * 1 : Busy (Rx operation ongoing)\n
<> 144:ef7eb2e8f9f7 119 * b0 Tx state\n
<> 144:ef7eb2e8f9f7 120 * 0 : Ready (no Tx operation ongoing)\n
<> 144:ef7eb2e8f9f7 121 * 1 : Busy (Tx operation ongoing)
<> 144:ef7eb2e8f9f7 122 * @{
Anna Bridge 180:96ed750bd169 123 */
<> 144:ef7eb2e8f9f7 124 typedef enum
<> 144:ef7eb2e8f9f7 125 {
<> 144:ef7eb2e8f9f7 126 HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
<> 144:ef7eb2e8f9f7 127 HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
<> 144:ef7eb2e8f9f7 128 HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
<> 144:ef7eb2e8f9f7 129 HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 130 HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 131 HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
<> 144:ef7eb2e8f9f7 132 HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
<> 156:95d6b41a828b 133 process is ongoing */
<> 144:ef7eb2e8f9f7 134 HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
<> 156:95d6b41a828b 135 process is ongoing */
<> 144:ef7eb2e8f9f7 136 HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
<> 144:ef7eb2e8f9f7 137 HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
<> 144:ef7eb2e8f9f7 138 HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
<> 144:ef7eb2e8f9f7 139
Anna Bridge 180:96ed750bd169 140 } HAL_I2C_StateTypeDef;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
<> 144:ef7eb2e8f9f7 147 * @brief HAL Mode structure definition
<> 144:ef7eb2e8f9f7 148 * @note HAL I2C Mode value coding follow below described bitmap :\n
<> 144:ef7eb2e8f9f7 149 * b7 (not used)\n
<> 144:ef7eb2e8f9f7 150 * x : Should be set to 0\n
<> 144:ef7eb2e8f9f7 151 * b6\n
<> 144:ef7eb2e8f9f7 152 * 0 : None\n
<> 144:ef7eb2e8f9f7 153 * 1 : Memory (HAL I2C communication is in Memory Mode)\n
<> 144:ef7eb2e8f9f7 154 * b5\n
<> 144:ef7eb2e8f9f7 155 * 0 : None\n
<> 144:ef7eb2e8f9f7 156 * 1 : Slave (HAL I2C communication is in Slave Mode)\n
<> 144:ef7eb2e8f9f7 157 * b4\n
<> 144:ef7eb2e8f9f7 158 * 0 : None\n
<> 144:ef7eb2e8f9f7 159 * 1 : Master (HAL I2C communication is in Master Mode)\n
<> 144:ef7eb2e8f9f7 160 * b3-b2-b1-b0 (not used)\n
<> 144:ef7eb2e8f9f7 161 * xxxx : Should be set to 0000
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 typedef enum
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
<> 144:ef7eb2e8f9f7 167 HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
<> 144:ef7eb2e8f9f7 168 HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
<> 144:ef7eb2e8f9f7 169 HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
<> 144:ef7eb2e8f9f7 170
Anna Bridge 180:96ed750bd169 171 } HAL_I2C_ModeTypeDef;
<> 144:ef7eb2e8f9f7 172
Anna Bridge 180:96ed750bd169 173 /**
<> 144:ef7eb2e8f9f7 174 * @}
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /** @defgroup I2C_Error_Code_definition I2C Error Code definition
<> 144:ef7eb2e8f9f7 178 * @brief I2C Error Code definition
<> 144:ef7eb2e8f9f7 179 * @{
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181 #define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
<> 144:ef7eb2e8f9f7 182 #define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
<> 144:ef7eb2e8f9f7 183 #define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
<> 144:ef7eb2e8f9f7 184 #define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
<> 144:ef7eb2e8f9f7 185 #define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
<> 144:ef7eb2e8f9f7 186 #define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 187 #define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
<> 144:ef7eb2e8f9f7 188 #define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
<> 144:ef7eb2e8f9f7 189 /**
<> 144:ef7eb2e8f9f7 190 * @}
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
<> 144:ef7eb2e8f9f7 194 * @brief I2C handle Structure definition
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197 typedef struct __I2C_HandleTypeDef
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 I2C_TypeDef *Instance; /*!< I2C registers base address */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 I2C_InitTypeDef Init; /*!< I2C communication parameters */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 uint16_t XferSize; /*!< I2C transfer size */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 __IO uint16_t XferCount; /*!< I2C transfer counter */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
<> 144:ef7eb2e8f9f7 210 be a value of @ref I2C_XFEROPTIONS */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 __IO uint32_t PreviousState; /*!< I2C communication Previous state */
<> 144:ef7eb2e8f9f7 213
Anna Bridge 180:96ed750bd169 214 HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 HAL_LockTypeDef Lock; /*!< I2C locking object */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 __IO uint32_t ErrorCode; /*!< I2C Error code */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
Anna Bridge 180:96ed750bd169 229 } I2C_HandleTypeDef;
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @}
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @}
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /** @defgroup I2C_Exported_Constants I2C Exported Constants
<> 144:ef7eb2e8f9f7 240 * @{
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
<> 144:ef7eb2e8f9f7 244 * @{
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246 #define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
<> 156:95d6b41a828b 247 #define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
<> 144:ef7eb2e8f9f7 248 #define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
<> 144:ef7eb2e8f9f7 249 #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
<> 144:ef7eb2e8f9f7 250 #define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @}
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 #define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
<> 144:ef7eb2e8f9f7 259 #define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @}
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
<> 144:ef7eb2e8f9f7 265 * @{
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 #define I2C_DUALADDRESS_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 268 #define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @}
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
<> 144:ef7eb2e8f9f7 274 * @{
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 #define I2C_OA2_NOMASK ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 277 #define I2C_OA2_MASK01 ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 278 #define I2C_OA2_MASK02 ((uint8_t)0x02U)
<> 144:ef7eb2e8f9f7 279 #define I2C_OA2_MASK03 ((uint8_t)0x03U)
<> 144:ef7eb2e8f9f7 280 #define I2C_OA2_MASK04 ((uint8_t)0x04U)
<> 144:ef7eb2e8f9f7 281 #define I2C_OA2_MASK05 ((uint8_t)0x05U)
<> 144:ef7eb2e8f9f7 282 #define I2C_OA2_MASK06 ((uint8_t)0x06U)
<> 144:ef7eb2e8f9f7 283 #define I2C_OA2_MASK07 ((uint8_t)0x07U)
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @}
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
<> 144:ef7eb2e8f9f7 289 * @{
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 #define I2C_GENERALCALL_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 292 #define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @}
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
<> 144:ef7eb2e8f9f7 298 * @{
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 #define I2C_NOSTRETCH_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 301 #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @}
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
<> 144:ef7eb2e8f9f7 307 * @{
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309 #define I2C_MEMADD_SIZE_8BIT (0x00000001U)
<> 144:ef7eb2e8f9f7 310 #define I2C_MEMADD_SIZE_16BIT (0x00000002U)
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @}
<> 144:ef7eb2e8f9f7 313 */
Anna Bridge 180:96ed750bd169 314
<> 144:ef7eb2e8f9f7 315 /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
<> 144:ef7eb2e8f9f7 316 * @{
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318 #define I2C_DIRECTION_TRANSMIT (0x00000000U)
<> 144:ef7eb2e8f9f7 319 #define I2C_DIRECTION_RECEIVE (0x00000001U)
<> 144:ef7eb2e8f9f7 320 /**
<> 144:ef7eb2e8f9f7 321 * @}
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
<> 144:ef7eb2e8f9f7 325 * @{
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 #define I2C_RELOAD_MODE I2C_CR2_RELOAD
<> 144:ef7eb2e8f9f7 328 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
<> 144:ef7eb2e8f9f7 329 #define I2C_SOFTEND_MODE (0x00000000U)
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @}
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
<> 144:ef7eb2e8f9f7 335 * @{
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337 #define I2C_NO_STARTSTOP (0x00000000U)
<> 144:ef7eb2e8f9f7 338 #define I2C_GENERATE_STOP I2C_CR2_STOP
<> 144:ef7eb2e8f9f7 339 #define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
<> 144:ef7eb2e8f9f7 340 #define I2C_GENERATE_START_WRITE I2C_CR2_START
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @}
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
<> 144:ef7eb2e8f9f7 346 * @brief I2C Interrupt definition
<> 144:ef7eb2e8f9f7 347 * Elements values convention: 0xXXXXXXXX
<> 144:ef7eb2e8f9f7 348 * - XXXXXXXX : Interrupt control mask
<> 144:ef7eb2e8f9f7 349 * @{
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351 #define I2C_IT_ERRI I2C_CR1_ERRIE
<> 144:ef7eb2e8f9f7 352 #define I2C_IT_TCI I2C_CR1_TCIE
<> 144:ef7eb2e8f9f7 353 #define I2C_IT_STOPI I2C_CR1_STOPIE
<> 144:ef7eb2e8f9f7 354 #define I2C_IT_NACKI I2C_CR1_NACKIE
<> 144:ef7eb2e8f9f7 355 #define I2C_IT_ADDRI I2C_CR1_ADDRIE
<> 144:ef7eb2e8f9f7 356 #define I2C_IT_RXI I2C_CR1_RXIE
<> 144:ef7eb2e8f9f7 357 #define I2C_IT_TXI I2C_CR1_TXIE
<> 144:ef7eb2e8f9f7 358 /**
<> 144:ef7eb2e8f9f7 359 * @}
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /** @defgroup I2C_Flag_definition I2C Flag definition
<> 144:ef7eb2e8f9f7 363 * @{
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 #define I2C_FLAG_TXE I2C_ISR_TXE
<> 144:ef7eb2e8f9f7 366 #define I2C_FLAG_TXIS I2C_ISR_TXIS
<> 144:ef7eb2e8f9f7 367 #define I2C_FLAG_RXNE I2C_ISR_RXNE
<> 144:ef7eb2e8f9f7 368 #define I2C_FLAG_ADDR I2C_ISR_ADDR
<> 144:ef7eb2e8f9f7 369 #define I2C_FLAG_AF I2C_ISR_NACKF
<> 144:ef7eb2e8f9f7 370 #define I2C_FLAG_STOPF I2C_ISR_STOPF
<> 144:ef7eb2e8f9f7 371 #define I2C_FLAG_TC I2C_ISR_TC
<> 144:ef7eb2e8f9f7 372 #define I2C_FLAG_TCR I2C_ISR_TCR
<> 144:ef7eb2e8f9f7 373 #define I2C_FLAG_BERR I2C_ISR_BERR
<> 144:ef7eb2e8f9f7 374 #define I2C_FLAG_ARLO I2C_ISR_ARLO
<> 144:ef7eb2e8f9f7 375 #define I2C_FLAG_OVR I2C_ISR_OVR
<> 144:ef7eb2e8f9f7 376 #define I2C_FLAG_PECERR I2C_ISR_PECERR
<> 144:ef7eb2e8f9f7 377 #define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
<> 144:ef7eb2e8f9f7 378 #define I2C_FLAG_ALERT I2C_ISR_ALERT
<> 144:ef7eb2e8f9f7 379 #define I2C_FLAG_BUSY I2C_ISR_BUSY
<> 144:ef7eb2e8f9f7 380 #define I2C_FLAG_DIR I2C_ISR_DIR
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @}
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @}
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /** @defgroup I2C_Exported_Macros I2C Exported Macros
<> 144:ef7eb2e8f9f7 392 * @{
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /** @brief Reset I2C handle state.
<> 144:ef7eb2e8f9f7 396 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 397 * @retval None
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /** @brief Enable the specified I2C interrupt.
<> 144:ef7eb2e8f9f7 402 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 403 * @param __INTERRUPT__ specifies the interrupt source to enable.
<> 144:ef7eb2e8f9f7 404 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 405 * @arg @ref I2C_IT_ERRI Errors interrupt enable
<> 144:ef7eb2e8f9f7 406 * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 407 * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 408 * @arg @ref I2C_IT_NACKI NACK received interrupt enable
<> 144:ef7eb2e8f9f7 409 * @arg @ref I2C_IT_ADDRI Address match interrupt enable
<> 144:ef7eb2e8f9f7 410 * @arg @ref I2C_IT_RXI RX interrupt enable
<> 144:ef7eb2e8f9f7 411 * @arg @ref I2C_IT_TXI TX interrupt enable
<> 144:ef7eb2e8f9f7 412 *
<> 144:ef7eb2e8f9f7 413 * @retval None
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /** @brief Disable the specified I2C interrupt.
<> 144:ef7eb2e8f9f7 418 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 419 * @param __INTERRUPT__ specifies the interrupt source to disable.
<> 144:ef7eb2e8f9f7 420 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 421 * @arg @ref I2C_IT_ERRI Errors interrupt enable
<> 144:ef7eb2e8f9f7 422 * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 423 * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 424 * @arg @ref I2C_IT_NACKI NACK received interrupt enable
<> 144:ef7eb2e8f9f7 425 * @arg @ref I2C_IT_ADDRI Address match interrupt enable
<> 144:ef7eb2e8f9f7 426 * @arg @ref I2C_IT_RXI RX interrupt enable
<> 144:ef7eb2e8f9f7 427 * @arg @ref I2C_IT_TXI TX interrupt enable
<> 144:ef7eb2e8f9f7 428 *
<> 144:ef7eb2e8f9f7 429 * @retval None
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
Anna Bridge 180:96ed750bd169 432
<> 144:ef7eb2e8f9f7 433 /** @brief Check whether the specified I2C interrupt source is enabled or not.
<> 144:ef7eb2e8f9f7 434 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 435 * @param __INTERRUPT__ specifies the I2C interrupt source to check.
<> 144:ef7eb2e8f9f7 436 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 437 * @arg @ref I2C_IT_ERRI Errors interrupt enable
<> 144:ef7eb2e8f9f7 438 * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 439 * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 440 * @arg @ref I2C_IT_NACKI NACK received interrupt enable
<> 144:ef7eb2e8f9f7 441 * @arg @ref I2C_IT_ADDRI Address match interrupt enable
<> 144:ef7eb2e8f9f7 442 * @arg @ref I2C_IT_RXI RX interrupt enable
<> 144:ef7eb2e8f9f7 443 * @arg @ref I2C_IT_TXI TX interrupt enable
<> 144:ef7eb2e8f9f7 444 *
<> 144:ef7eb2e8f9f7 445 * @retval The new state of __INTERRUPT__ (SET or RESET).
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /** @brief Check whether the specified I2C flag is set or not.
<> 144:ef7eb2e8f9f7 450 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 451 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 452 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 453 * @arg @ref I2C_FLAG_TXE Transmit data register empty
<> 144:ef7eb2e8f9f7 454 * @arg @ref I2C_FLAG_TXIS Transmit interrupt status
<> 144:ef7eb2e8f9f7 455 * @arg @ref I2C_FLAG_RXNE Receive data register not empty
<> 144:ef7eb2e8f9f7 456 * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
<> 144:ef7eb2e8f9f7 457 * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
<> 144:ef7eb2e8f9f7 458 * @arg @ref I2C_FLAG_STOPF STOP detection flag
<> 144:ef7eb2e8f9f7 459 * @arg @ref I2C_FLAG_TC Transfer complete (master mode)
<> 144:ef7eb2e8f9f7 460 * @arg @ref I2C_FLAG_TCR Transfer complete reload
<> 144:ef7eb2e8f9f7 461 * @arg @ref I2C_FLAG_BERR Bus error
<> 144:ef7eb2e8f9f7 462 * @arg @ref I2C_FLAG_ARLO Arbitration lost
<> 144:ef7eb2e8f9f7 463 * @arg @ref I2C_FLAG_OVR Overrun/Underrun
<> 144:ef7eb2e8f9f7 464 * @arg @ref I2C_FLAG_PECERR PEC error in reception
<> 144:ef7eb2e8f9f7 465 * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
<> 144:ef7eb2e8f9f7 466 * @arg @ref I2C_FLAG_ALERT SMBus alert
<> 144:ef7eb2e8f9f7 467 * @arg @ref I2C_FLAG_BUSY Bus busy
<> 144:ef7eb2e8f9f7 468 * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
<> 144:ef7eb2e8f9f7 469 *
<> 144:ef7eb2e8f9f7 470 * @retval The new state of __FLAG__ (SET or RESET).
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
<> 144:ef7eb2e8f9f7 475 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 476 * @param __FLAG__ specifies the flag to clear.
<> 144:ef7eb2e8f9f7 477 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 478 * @arg @ref I2C_FLAG_TXE Transmit data register empty
<> 144:ef7eb2e8f9f7 479 * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
<> 144:ef7eb2e8f9f7 480 * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
<> 144:ef7eb2e8f9f7 481 * @arg @ref I2C_FLAG_STOPF STOP detection flag
<> 144:ef7eb2e8f9f7 482 * @arg @ref I2C_FLAG_BERR Bus error
<> 144:ef7eb2e8f9f7 483 * @arg @ref I2C_FLAG_ARLO Arbitration lost
<> 144:ef7eb2e8f9f7 484 * @arg @ref I2C_FLAG_OVR Overrun/Underrun
<> 144:ef7eb2e8f9f7 485 * @arg @ref I2C_FLAG_PECERR PEC error in reception
<> 144:ef7eb2e8f9f7 486 * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
<> 144:ef7eb2e8f9f7 487 * @arg @ref I2C_FLAG_ALERT SMBus alert
<> 144:ef7eb2e8f9f7 488 *
<> 144:ef7eb2e8f9f7 489 * @retval None
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
<> 144:ef7eb2e8f9f7 492 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /** @brief Enable the specified I2C peripheral.
<> 144:ef7eb2e8f9f7 495 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 496 * @retval None
<> 144:ef7eb2e8f9f7 497 */
<> 144:ef7eb2e8f9f7 498 #define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /** @brief Disable the specified I2C peripheral.
<> 144:ef7eb2e8f9f7 501 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 502 * @retval None
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504 #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
Anna Bridge 180:96ed750bd169 507 * @param __HANDLE__ specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 508 * @retval None
<> 144:ef7eb2e8f9f7 509 */
<> 144:ef7eb2e8f9f7 510 #define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
<> 144:ef7eb2e8f9f7 511 /**
<> 144:ef7eb2e8f9f7 512 * @}
<> 144:ef7eb2e8f9f7 513 */
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Include I2C HAL Extended module */
<> 144:ef7eb2e8f9f7 516 #include "stm32f0xx_hal_i2c_ex.h"
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 519 /** @addtogroup I2C_Exported_Functions
<> 144:ef7eb2e8f9f7 520 * @{
<> 144:ef7eb2e8f9f7 521 */
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 524 * @{
<> 144:ef7eb2e8f9f7 525 */
<> 144:ef7eb2e8f9f7 526 /* Initialization and de-initialization functions******************************/
<> 144:ef7eb2e8f9f7 527 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
Anna Bridge 180:96ed750bd169 528 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 529 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 530 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @}
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 536 * @{
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538 /* IO operation functions ****************************************************/
Anna Bridge 180:96ed750bd169 539 /******* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 540 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 541 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 542 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 543 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 544 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 545 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 546 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 547
Anna Bridge 180:96ed750bd169 548 /******* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 549 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 550 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 551 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 552 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 553 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 554 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 557 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 558 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 559 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 560 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 561 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 562 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
<> 144:ef7eb2e8f9f7 563
Anna Bridge 180:96ed750bd169 564 /******* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 565 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 566 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 567 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 568 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 569 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 570 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 571 /**
<> 144:ef7eb2e8f9f7 572 * @}
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
<> 144:ef7eb2e8f9f7 576 * @{
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
<> 144:ef7eb2e8f9f7 579 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 580 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 581 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 582 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 583 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 584 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 585 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
<> 144:ef7eb2e8f9f7 586 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 587 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 588 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 589 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 590 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 591 /**
<> 144:ef7eb2e8f9f7 592 * @}
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
<> 144:ef7eb2e8f9f7 596 * @{
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598 /* Peripheral State, Mode and Error functions *********************************/
<> 144:ef7eb2e8f9f7 599 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 600 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 601 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @}
Anna Bridge 180:96ed750bd169 605 */
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /**
<> 144:ef7eb2e8f9f7 608 * @}
Anna Bridge 180:96ed750bd169 609 */
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 612 /** @defgroup I2C_Private_Constants I2C Private Constants
<> 144:ef7eb2e8f9f7 613 * @{
<> 144:ef7eb2e8f9f7 614 */
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /**
<> 144:ef7eb2e8f9f7 617 * @}
Anna Bridge 180:96ed750bd169 618 */
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 621 /** @defgroup I2C_Private_Macro I2C Private Macros
<> 144:ef7eb2e8f9f7 622 * @{
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 #define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
<> 144:ef7eb2e8f9f7 626 ((MODE) == I2C_ADDRESSINGMODE_10BIT))
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
<> 144:ef7eb2e8f9f7 629 ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 #define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
<> 144:ef7eb2e8f9f7 632 ((MASK) == I2C_OA2_MASK01) || \
<> 144:ef7eb2e8f9f7 633 ((MASK) == I2C_OA2_MASK02) || \
<> 144:ef7eb2e8f9f7 634 ((MASK) == I2C_OA2_MASK03) || \
<> 144:ef7eb2e8f9f7 635 ((MASK) == I2C_OA2_MASK04) || \
<> 144:ef7eb2e8f9f7 636 ((MASK) == I2C_OA2_MASK05) || \
<> 144:ef7eb2e8f9f7 637 ((MASK) == I2C_OA2_MASK06) || \
<> 144:ef7eb2e8f9f7 638 ((MASK) == I2C_OA2_MASK07))
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
<> 144:ef7eb2e8f9f7 641 ((CALL) == I2C_GENERALCALL_ENABLE))
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
<> 144:ef7eb2e8f9f7 644 ((STRETCH) == I2C_NOSTRETCH_ENABLE))
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
<> 144:ef7eb2e8f9f7 647 ((SIZE) == I2C_MEMADD_SIZE_16BIT))
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 #define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
<> 144:ef7eb2e8f9f7 650 ((MODE) == I2C_AUTOEND_MODE) || \
<> 144:ef7eb2e8f9f7 651 ((MODE) == I2C_SOFTEND_MODE))
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 #define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
<> 144:ef7eb2e8f9f7 654 ((REQUEST) == I2C_GENERATE_START_READ) || \
<> 144:ef7eb2e8f9f7 655 ((REQUEST) == I2C_GENERATE_START_WRITE) || \
<> 144:ef7eb2e8f9f7 656 ((REQUEST) == I2C_NO_STARTSTOP))
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
<> 156:95d6b41a828b 659 ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
<> 144:ef7eb2e8f9f7 660 ((REQUEST) == I2C_NEXT_FRAME) || \
<> 144:ef7eb2e8f9f7 661 ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
<> 144:ef7eb2e8f9f7 662 ((REQUEST) == I2C_LAST_FRAME))
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 #define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
<> 144:ef7eb2e8f9f7 667 #define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
<> 144:ef7eb2e8f9f7 668 #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
<> 144:ef7eb2e8f9f7 669 #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
<> 144:ef7eb2e8f9f7 670 #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
<> 144:ef7eb2e8f9f7 673 #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 #define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
<> 144:ef7eb2e8f9f7 676 #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
<> 144:ef7eb2e8f9f7 679 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
<> 144:ef7eb2e8f9f7 680 /**
<> 144:ef7eb2e8f9f7 681 * @}
Anna Bridge 180:96ed750bd169 682 */
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Private Functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 685 /** @defgroup I2C_Private_Functions I2C Private Functions
<> 144:ef7eb2e8f9f7 686 * @{
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688 /* Private functions are defined in stm32f0xx_hal_i2c.c file */
<> 144:ef7eb2e8f9f7 689 /**
<> 144:ef7eb2e8f9f7 690 * @}
Anna Bridge 180:96ed750bd169 691 */
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /**
<> 144:ef7eb2e8f9f7 694 * @}
Anna Bridge 180:96ed750bd169 695 */
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /**
<> 144:ef7eb2e8f9f7 698 * @}
Anna Bridge 180:96ed750bd169 699 */
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703 #endif
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 #endif /* __STM32F0xx_HAL_I2C_H */
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/