mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_flash_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of Flash HAL Extended module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup FLASHEx
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup FLASHEx_Private_Macros
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
<> 144:ef7eb2e8f9f7 59 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 #define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
<> 144:ef7eb2e8f9f7 64 ((VALUE) == OB_WRPSTATE_ENABLE))
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
<> 144:ef7eb2e8f9f7 69 ((LEVEL) == OB_RDP_LEVEL_1))/*||\
<> 144:ef7eb2e8f9f7 70 ((LEVEL) == OB_RDP_LEVEL_2))*/
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 #define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 #define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 #if defined(FLASH_OBR_BOOT_SEL)
<> 144:ef7eb2e8f9f7 85 #define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET))
<> 144:ef7eb2e8f9f7 86 #define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
<> 144:ef7eb2e8f9f7 87 #endif /* FLASH_OBR_BOOT_SEL */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89
<> 156:95d6b41a828b 90 #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= FLASH_BANK1_END)
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BANK1_END))
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /**
<> 144:ef7eb2e8f9f7 97 * @}
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104 /**
<> 144:ef7eb2e8f9f7 105 * @brief FLASH Erase structure definition
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 typedef struct
<> 144:ef7eb2e8f9f7 108 {
<> 144:ef7eb2e8f9f7 109 uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
<> 144:ef7eb2e8f9f7 110 This parameter can be a value of @ref FLASHEx_Type_Erase */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
<> 144:ef7eb2e8f9f7 113 This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
<> 144:ef7eb2e8f9f7 116 This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 } FLASH_EraseInitTypeDef;
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @brief FLASH Options bytes program structure definition
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 typedef struct
<> 144:ef7eb2e8f9f7 124 {
<> 144:ef7eb2e8f9f7 125 uint32_t OptionType; /*!< OptionType: Option byte to be configured.
<> 144:ef7eb2e8f9f7 126 This parameter can be a value of @ref FLASHEx_OB_Type */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
<> 144:ef7eb2e8f9f7 129 This parameter can be a value of @ref FLASHEx_OB_WRP_State */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
<> 144:ef7eb2e8f9f7 132 This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
<> 144:ef7eb2e8f9f7 135 This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
<> 144:ef7eb2e8f9f7 138 IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY
<> 144:ef7eb2e8f9f7 139 This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
<> 144:ef7eb2e8f9f7 140 @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and
<> 144:ef7eb2e8f9f7 141 @ref FLASHEx_OB_RAM_Parity_Check_Enable */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
<> 144:ef7eb2e8f9f7 144 This parameter can be a value of @ref FLASHEx_OB_Data_Address */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
<> 144:ef7eb2e8f9f7 147 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 148 } FLASH_OBProgramInitTypeDef;
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @}
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 154 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
<> 144:ef7eb2e8f9f7 155 * @{
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /** @defgroup FLASHEx_Page_Size FLASHEx Page Size
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
<> 144:ef7eb2e8f9f7 162 || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
<> 156:95d6b41a828b 163 #define FLASH_PAGE_SIZE 0x400U
<> 144:ef7eb2e8f9f7 164 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
<> 144:ef7eb2e8f9f7 167 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 156:95d6b41a828b 168 #define FLASH_PAGE_SIZE 0x800U
<> 144:ef7eb2e8f9f7 169 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
<> 156:95d6b41a828b 177 #define FLASH_TYPEERASE_PAGES (0x00U) /*!<Pages erase only*/
<> 156:95d6b41a828b 178 #define FLASH_TYPEERASE_MASSERASE (0x01U) /*!<Flash mass erase activation*/
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /**
<> 144:ef7eb2e8f9f7 181 * @}
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
<> 144:ef7eb2e8f9f7 185 * @{
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /** @defgroup FLASHEx_OB_Type Option Bytes Type
<> 144:ef7eb2e8f9f7 189 * @{
<> 144:ef7eb2e8f9f7 190 */
<> 156:95d6b41a828b 191 #define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/
<> 156:95d6b41a828b 192 #define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/
<> 156:95d6b41a828b 193 #define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/
<> 156:95d6b41a828b 194 #define OPTIONBYTE_DATA (0x08U) /*!<DATA option byte configuration*/
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /**
<> 144:ef7eb2e8f9f7 197 * @}
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
<> 144:ef7eb2e8f9f7 201 * @{
<> 144:ef7eb2e8f9f7 202 */
<> 156:95d6b41a828b 203 #define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired pages*/
<> 156:95d6b41a828b 204 #define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired pagess*/
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @}
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
<> 144:ef7eb2e8f9f7 211 * @{
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
<> 144:ef7eb2e8f9f7 214 || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
<> 156:95d6b41a828b 215 #define OB_WRP_PAGES0TO3 (0x00000001U) /* Write protection of page 0 to 3 */
<> 156:95d6b41a828b 216 #define OB_WRP_PAGES4TO7 (0x00000002U) /* Write protection of page 4 to 7 */
<> 156:95d6b41a828b 217 #define OB_WRP_PAGES8TO11 (0x00000004U) /* Write protection of page 8 to 11 */
<> 156:95d6b41a828b 218 #define OB_WRP_PAGES12TO15 (0x00000008U) /* Write protection of page 12 to 15 */
<> 156:95d6b41a828b 219 #define OB_WRP_PAGES16TO19 (0x00000010U) /* Write protection of page 16 to 19 */
<> 156:95d6b41a828b 220 #define OB_WRP_PAGES20TO23 (0x00000020U) /* Write protection of page 20 to 23 */
<> 156:95d6b41a828b 221 #define OB_WRP_PAGES24TO27 (0x00000040U) /* Write protection of page 24 to 27 */
<> 156:95d6b41a828b 222 #define OB_WRP_PAGES28TO31 (0x00000080U) /* Write protection of page 28 to 31 */
<> 144:ef7eb2e8f9f7 223 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
<> 156:95d6b41a828b 224 #define OB_WRP_PAGES32TO35 (0x00000100U) /* Write protection of page 32 to 35 */
<> 156:95d6b41a828b 225 #define OB_WRP_PAGES36TO39 (0x00000200U) /* Write protection of page 36 to 39 */
<> 156:95d6b41a828b 226 #define OB_WRP_PAGES40TO43 (0x00000400U) /* Write protection of page 40 to 43 */
<> 156:95d6b41a828b 227 #define OB_WRP_PAGES44TO47 (0x00000800U) /* Write protection of page 44 to 47 */
<> 156:95d6b41a828b 228 #define OB_WRP_PAGES48TO51 (0x00001000U) /* Write protection of page 48 to 51 */
<> 156:95d6b41a828b 229 #define OB_WRP_PAGES52TO57 (0x00002000U) /* Write protection of page 52 to 57 */
<> 156:95d6b41a828b 230 #define OB_WRP_PAGES56TO59 (0x00004000U) /* Write protection of page 56 to 59 */
<> 156:95d6b41a828b 231 #define OB_WRP_PAGES60TO63 (0x00008000U) /* Write protection of page 60 to 63 */
<> 144:ef7eb2e8f9f7 232 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
<> 144:ef7eb2e8f9f7 235 || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
<> 156:95d6b41a828b 236 #define OB_WRP_PAGES0TO31MASK (0x000000FFU)
<> 144:ef7eb2e8f9f7 237 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
<> 156:95d6b41a828b 240 #define OB_WRP_PAGES32TO63MASK (0x0000FF00U)
<> 144:ef7eb2e8f9f7 241 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)|| defined(STM32F070x6)
<> 156:95d6b41a828b 244 #define OB_WRP_ALLPAGES (0x000000FFU) /*!< Write protection of all pages */
<> 144:ef7eb2e8f9f7 245 #endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
<> 156:95d6b41a828b 248 #define OB_WRP_ALLPAGES (0x0000FFFFU) /*!< Write protection of all pages */
<> 144:ef7eb2e8f9f7 249 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
<> 144:ef7eb2e8f9f7 250 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
<> 144:ef7eb2e8f9f7 253 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 156:95d6b41a828b 254 #define OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */
<> 156:95d6b41a828b 255 #define OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */
<> 156:95d6b41a828b 256 #define OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */
<> 156:95d6b41a828b 257 #define OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */
<> 156:95d6b41a828b 258 #define OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */
<> 156:95d6b41a828b 259 #define OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */
<> 156:95d6b41a828b 260 #define OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */
<> 156:95d6b41a828b 261 #define OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */
<> 156:95d6b41a828b 262 #define OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */
<> 156:95d6b41a828b 263 #define OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */
<> 156:95d6b41a828b 264 #define OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */
<> 156:95d6b41a828b 265 #define OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */
<> 156:95d6b41a828b 266 #define OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */
<> 156:95d6b41a828b 267 #define OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */
<> 156:95d6b41a828b 268 #define OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */
<> 156:95d6b41a828b 269 #define OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */
<> 156:95d6b41a828b 270 #define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
<> 156:95d6b41a828b 271 #define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
<> 156:95d6b41a828b 272 #define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
<> 156:95d6b41a828b 273 #define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
<> 156:95d6b41a828b 274 #define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
<> 156:95d6b41a828b 275 #define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
<> 156:95d6b41a828b 276 #define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
<> 156:95d6b41a828b 277 #define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
<> 156:95d6b41a828b 278 #define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
<> 156:95d6b41a828b 279 #define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
<> 156:95d6b41a828b 280 #define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
<> 156:95d6b41a828b 281 #define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
<> 156:95d6b41a828b 282 #define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
<> 156:95d6b41a828b 283 #define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
<> 156:95d6b41a828b 284 #define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
<> 144:ef7eb2e8f9f7 285 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
<> 156:95d6b41a828b 286 #define OB_WRP_PAGES62TO63 (0x80000000U) /* Write protection of page 62 to 63 */
<> 144:ef7eb2e8f9f7 287 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
<> 144:ef7eb2e8f9f7 288 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 156:95d6b41a828b 289 #define OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */
<> 144:ef7eb2e8f9f7 290 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
<> 144:ef7eb2e8f9f7 293 || defined(STM32F091xC) || defined(STM32F098xx)|| defined(STM32F030xC)
<> 156:95d6b41a828b 294 #define OB_WRP_PAGES0TO15MASK (0x000000FFU)
<> 156:95d6b41a828b 295 #define OB_WRP_PAGES16TO31MASK (0x0000FF00U)
<> 156:95d6b41a828b 296 #define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
<> 144:ef7eb2e8f9f7 297 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
<> 156:95d6b41a828b 300 #define OB_WRP_PAGES48TO63MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 301 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
<> 144:ef7eb2e8f9f7 302 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 156:95d6b41a828b 303 #define OB_WRP_PAGES48TO127MASK (0xFF000000U)
<> 144:ef7eb2e8f9f7 304 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 305
<> 156:95d6b41a828b 306 #define OB_WRP_ALLPAGES (0xFFFFFFFFU) /*!< Write protection of all pages */
<> 144:ef7eb2e8f9f7 307 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @}
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
<> 144:ef7eb2e8f9f7 314 * @{
<> 144:ef7eb2e8f9f7 315 */
<> 156:95d6b41a828b 316 #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
<> 156:95d6b41a828b 317 #define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
<> 156:95d6b41a828b 318 #define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
<> 144:ef7eb2e8f9f7 319 it's no more possible to go back to level 1 or 0 */
<> 144:ef7eb2e8f9f7 320 /**
<> 144:ef7eb2e8f9f7 321 * @}
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
<> 144:ef7eb2e8f9f7 325 * @{
<> 144:ef7eb2e8f9f7 326 */
<> 156:95d6b41a828b 327 #define OB_IWDG_SW ((uint8_t)0x01U) /*!< Software IWDG selected */
<> 156:95d6b41a828b 328 #define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware IWDG selected */
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @}
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
<> 144:ef7eb2e8f9f7 334 * @{
<> 144:ef7eb2e8f9f7 335 */
<> 156:95d6b41a828b 336 #define OB_STOP_NO_RST ((uint8_t)0x02U) /*!< No reset generated when entering in STOP */
<> 156:95d6b41a828b 337 #define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @}
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
<> 144:ef7eb2e8f9f7 343 * @{
<> 144:ef7eb2e8f9f7 344 */
<> 156:95d6b41a828b 345 #define OB_STDBY_NO_RST ((uint8_t)0x04U) /*!< No reset generated when entering in STANDBY */
<> 156:95d6b41a828b 346 #define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 347 /**
<> 144:ef7eb2e8f9f7 348 * @}
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
<> 144:ef7eb2e8f9f7 352 * @{
<> 144:ef7eb2e8f9f7 353 */
<> 156:95d6b41a828b 354 #define OB_BOOT1_RESET ((uint8_t)0x00U) /*!< BOOT1 Reset */
<> 156:95d6b41a828b 355 #define OB_BOOT1_SET ((uint8_t)0x10U) /*!< BOOT1 Set */
<> 144:ef7eb2e8f9f7 356 /**
<> 144:ef7eb2e8f9f7 357 * @}
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring Option Byte VDDA Analog Monitoring
<> 144:ef7eb2e8f9f7 361 * @{
<> 144:ef7eb2e8f9f7 362 */
<> 156:95d6b41a828b 363 #define OB_VDDA_ANALOG_ON ((uint8_t)0x20U) /*!< Analog monitoring on VDDA Power source ON */
<> 156:95d6b41a828b 364 #define OB_VDDA_ANALOG_OFF ((uint8_t)0x00U) /*!< Analog monitoring on VDDA Power source OFF */
<> 144:ef7eb2e8f9f7 365 /**
<> 144:ef7eb2e8f9f7 366 * @}
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable Option Byte SRAM Parity Check Enable
<> 144:ef7eb2e8f9f7 370 * @{
<> 144:ef7eb2e8f9f7 371 */
<> 156:95d6b41a828b 372 #define OB_SRAM_PARITY_SET ((uint8_t)0x00U) /*!< SRAM parity check enable set */
<> 156:95d6b41a828b 373 #define OB_SRAM_PARITY_RESET ((uint8_t)0x40U) /*!< SRAM parity check enable reset */
<> 144:ef7eb2e8f9f7 374 /**
<> 144:ef7eb2e8f9f7 375 * @}
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 #if defined(FLASH_OBR_BOOT_SEL)
<> 144:ef7eb2e8f9f7 379 /** @defgroup FLASHEx_OB_BOOT_SEL FLASHEx Option Byte BOOT SEL
<> 144:ef7eb2e8f9f7 380 * @{
<> 144:ef7eb2e8f9f7 381 */
<> 156:95d6b41a828b 382 #define OB_BOOT_SEL_RESET ((uint8_t)0x00U) /*!< BOOT_SEL Reset */
<> 156:95d6b41a828b 383 #define OB_BOOT_SEL_SET ((uint8_t)0x80U) /*!< BOOT_SEL Set */
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @}
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /** @defgroup FLASHEx_OB_BOOT0 FLASHEx Option Byte BOOT0
<> 144:ef7eb2e8f9f7 389 * @{
<> 144:ef7eb2e8f9f7 390 */
<> 156:95d6b41a828b 391 #define OB_BOOT0_RESET ((uint8_t)0x00U) /*!< BOOT0 Reset */
<> 156:95d6b41a828b 392 #define OB_BOOT0_SET ((uint8_t)0x08U) /*!< BOOT0 Set */
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @}
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 #endif /* FLASH_OBR_BOOT_SEL */
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
<> 144:ef7eb2e8f9f7 400 * @{
<> 144:ef7eb2e8f9f7 401 */
<> 156:95d6b41a828b 402 #define OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)
<> 156:95d6b41a828b 403 #define OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)
<> 144:ef7eb2e8f9f7 404 /**
<> 144:ef7eb2e8f9f7 405 * @}
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /**
<> 144:ef7eb2e8f9f7 409 * @}
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /**
<> 144:ef7eb2e8f9f7 413 * @}
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 417 /** @addtogroup FLASHEx_Exported_Functions
<> 144:ef7eb2e8f9f7 418 * @{
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /** @addtogroup FLASHEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 422 * @{
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 425 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
<> 144:ef7eb2e8f9f7 426 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @}
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /** @addtogroup FLASHEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 433 * @{
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 436 HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
<> 144:ef7eb2e8f9f7 437 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 438 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 439 uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /**
<> 144:ef7eb2e8f9f7 442 * @}
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /**
<> 144:ef7eb2e8f9f7 446 * @}
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /**
<> 144:ef7eb2e8f9f7 450 * @}
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @}
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459 #endif
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 #endif /* __STM32F0xx_HAL_FLASH_EX_H */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 464