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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_dac.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of DAC HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_DAC_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_DAC_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 45 * @{
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #if defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 49 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 50 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 53 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup DAC
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /** @defgroup DAC_Exported_Types DAC Exported Types
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 typedef enum
<> 144:ef7eb2e8f9f7 69 {
<> 156:95d6b41a828b 70 HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
<> 156:95d6b41a828b 71 HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
<> 156:95d6b41a828b 72 HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
<> 156:95d6b41a828b 73 HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
<> 156:95d6b41a828b 74 HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 }HAL_DAC_StateTypeDef;
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @brief DAC handle Structure definition
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81 typedef struct
<> 144:ef7eb2e8f9f7 82 {
<> 144:ef7eb2e8f9f7 83 DAC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 HAL_LockTypeDef Lock; /*!< DAC locking object */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 __IO uint32_t ErrorCode; /*!< DAC Error code */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 }DAC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /**
<> 144:ef7eb2e8f9f7 98 * @brief DAC Configuration regular Channel structure definition
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100 typedef struct
<> 144:ef7eb2e8f9f7 101 {
<> 144:ef7eb2e8f9f7 102 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
<> 144:ef7eb2e8f9f7 103 This parameter can be a value of @ref DAC_trigger_selection */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
<> 144:ef7eb2e8f9f7 106 This parameter can be a value of @ref DAC_output_buffer */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 }DAC_ChannelConfTypeDef;
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /**
<> 144:ef7eb2e8f9f7 111 * @}
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /** @defgroup DAC_Exported_Constants DAC Exported Constants
<> 144:ef7eb2e8f9f7 117 * @{
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /** @defgroup DAC_Error_Code DAC Error Code
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 156:95d6b41a828b 123 #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
<> 156:95d6b41a828b 124 #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
<> 156:95d6b41a828b 125 #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
<> 156:95d6b41a828b 126 #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @}
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @defgroup DAC_output_buffer DAC output buffer
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 156:95d6b41a828b 134 #define DAC_OUTPUTBUFFER_ENABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 135 #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @}
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /** @defgroup DAC_data_alignment DAC data alignment
<> 144:ef7eb2e8f9f7 142 * @{
<> 144:ef7eb2e8f9f7 143 */
<> 156:95d6b41a828b 144 #define DAC_ALIGN_12B_R (0x00000000U)
<> 156:95d6b41a828b 145 #define DAC_ALIGN_12B_L (0x00000004U)
<> 156:95d6b41a828b 146 #define DAC_ALIGN_8B_R (0x00000008U)
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /**
<> 144:ef7eb2e8f9f7 149 * @}
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /** @defgroup DAC_flags_definition DAC flags definition
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155 #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 144:ef7eb2e8f9f7 156 #define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @}
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @defgroup DAC_IT_definition DAC IT definition
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 #define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 144:ef7eb2e8f9f7 165 #define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @defgroup DAC_Exported_Macros DAC Exported Macros
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @brief Reset DAC handle state
Anna Bridge 180:96ed750bd169 181 * @param __HANDLE__ specifies the DAC handle.
<> 144:ef7eb2e8f9f7 182 * @retval None
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /** @brief Enable the DAC channel
Anna Bridge 180:96ed750bd169 187 * @param __HANDLE__ specifies the DAC handle.
Anna Bridge 180:96ed750bd169 188 * @param __DAC_Channel__ specifies the DAC channel
<> 144:ef7eb2e8f9f7 189 * @retval None
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
<> 144:ef7eb2e8f9f7 192 ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /** @brief Disable the DAC channel
Anna Bridge 180:96ed750bd169 195 * @param __HANDLE__ specifies the DAC handle
Anna Bridge 180:96ed750bd169 196 * @param __DAC_Channel__ specifies the DAC channel.
<> 144:ef7eb2e8f9f7 197 * @retval None
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
<> 144:ef7eb2e8f9f7 200 ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /** @brief Enable the DAC interrupt
Anna Bridge 180:96ed750bd169 203 * @param __HANDLE__ specifies the DAC handle
Anna Bridge 180:96ed750bd169 204 * @param __INTERRUPT__ specifies the DAC interrupt.
<> 144:ef7eb2e8f9f7 205 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 206 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 207 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 208 * @retval None
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /** @brief Disable the DAC interrupt
Anna Bridge 180:96ed750bd169 213 * @param __HANDLE__ specifies the DAC handle
Anna Bridge 180:96ed750bd169 214 * @param __INTERRUPT__ specifies the DAC interrupt.
<> 144:ef7eb2e8f9f7 215 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 216 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 217 * @retval None
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** @brief Check whether the specified DAC interrupt source is enabled or not
Anna Bridge 180:96ed750bd169 222 * @param __HANDLE__ DAC handle
Anna Bridge 180:96ed750bd169 223 * @param __INTERRUPT__ DAC interrupt source to check
<> 144:ef7eb2e8f9f7 224 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 225 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 226 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 227 * @retval State of interruption (SET or RESET)
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /** @brief Get the selected DAC's flag status
Anna Bridge 180:96ed750bd169 232 * @param __HANDLE__ specifies the DAC handle.
Anna Bridge 180:96ed750bd169 233 * @param __FLAG__ specifies the DAC flag to get.
<> 144:ef7eb2e8f9f7 234 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 235 * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
<> 144:ef7eb2e8f9f7 236 * @retval None
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /** @brief Clear the DAC's flag
Anna Bridge 180:96ed750bd169 241 * @param __HANDLE__ specifies the DAC handle.
Anna Bridge 180:96ed750bd169 242 * @param __FLAG__ specifies the DAC flag to clear.
<> 144:ef7eb2e8f9f7 243 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 244 * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
<> 144:ef7eb2e8f9f7 245 * @retval None
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @}
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /** @addtogroup DAC_Private_Macros
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
<> 144:ef7eb2e8f9f7 259 ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 263 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 266 ((CHANNEL) == DAC_CHANNEL_2))
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 269 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 #if defined(STM32F051x8) || defined(STM32F058xx)
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1))
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 #endif /* STM32F051x8 || STM32F058xx */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
<> 144:ef7eb2e8f9f7 279 ((ALIGN) == DAC_ALIGN_12B_L) || \
<> 144:ef7eb2e8f9f7 280 ((ALIGN) == DAC_ALIGN_8B_R))
<> 144:ef7eb2e8f9f7 281
<> 156:95d6b41a828b 282 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /** @brief Set DHR12R1 alignment
Anna Bridge 180:96ed750bd169 285 * @param __ALIGNMENT__ specifies the DAC alignment
<> 144:ef7eb2e8f9f7 286 * @retval None
<> 144:ef7eb2e8f9f7 287 */
<> 156:95d6b41a828b 288 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /** @brief Set DHR12R2 alignment
Anna Bridge 180:96ed750bd169 291 * @param __ALIGNMENT__ specifies the DAC alignment
<> 144:ef7eb2e8f9f7 292 * @retval None
<> 144:ef7eb2e8f9f7 293 */
<> 156:95d6b41a828b 294 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /** @brief Set DHR12RD alignment
Anna Bridge 180:96ed750bd169 297 * @param __ALIGNMENT__ specifies the DAC alignment
<> 144:ef7eb2e8f9f7 298 * @retval None
<> 144:ef7eb2e8f9f7 299 */
<> 156:95d6b41a828b 300 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @}
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Include DAC HAL Extension module */
<> 144:ef7eb2e8f9f7 307 #include "stm32f0xx_hal_dac_ex.h"
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /** @addtogroup DAC_Exported_Functions
<> 144:ef7eb2e8f9f7 312 * @{
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /** @addtogroup DAC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 316 * @{
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 319 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 320 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 321 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 322 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /** @addtogroup DAC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 332 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 333 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 334 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
<> 144:ef7eb2e8f9f7 335 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 342 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 343 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 344 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @}
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /** @addtogroup DAC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 350 * @{
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 353 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 356 /**
<> 144:ef7eb2e8f9f7 357 * @}
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /** @addtogroup DAC_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 361 * @{
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 364 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 365 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /**
<> 144:ef7eb2e8f9f7 368 * @}
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @}
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /**
<> 144:ef7eb2e8f9f7 376 * @}
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 #endif /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 380 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 381 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @}
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389 #endif
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 #endif /*__STM32F0xx_HAL_DAC_H */
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 395