mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
<> 144:ef7eb2e8f9f7 2 ;* File Name : startup_stm32f070xb.s
<> 144:ef7eb2e8f9f7 3 ;* Author : MCD Application Team
<> 144:ef7eb2e8f9f7 4 ;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain.
<> 144:ef7eb2e8f9f7 5 ;* This module performs:
<> 144:ef7eb2e8f9f7 6 ;* - Set the initial SP
<> 144:ef7eb2e8f9f7 7 ;* - Set the initial PC == Reset_Handler
<> 144:ef7eb2e8f9f7 8 ;* - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 9 ;* - Branches to __main in the C library (which eventually
<> 144:ef7eb2e8f9f7 10 ;* calls main()).
<> 144:ef7eb2e8f9f7 11 ;* After Reset the CortexM0 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 12 ;* priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 13 ;* <<< Use Configuration Wizard in Context Menu >>>
<> 144:ef7eb2e8f9f7 14 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 15 ;
<> 144:ef7eb2e8f9f7 16 ;* Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 17 ;* are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 18 ;* 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 19 ;* this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 20 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 21 ;* this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 22 ;* and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 23 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 24 ;* may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 25 ;* without specific prior written permission.
<> 144:ef7eb2e8f9f7 26 ;*
<> 144:ef7eb2e8f9f7 27 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 28 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 29 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 30 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 31 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 32 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 33 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 34 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 35 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 36 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 37 ;
<> 144:ef7eb2e8f9f7 38 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 ; Amount of memory (in bytes) allocated for Stack
<> 144:ef7eb2e8f9f7 41 ; Tailor this value to your application needs
<> 144:ef7eb2e8f9f7 42 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 43 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 44 ; </h>
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 Stack_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 49 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 Stack_Mem SPACE Stack_Size
<> 144:ef7eb2e8f9f7 52 __initial_sp EQU 0x20004000 ; Top of RAM (16KB)
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 56 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 57 ; </h>
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 Heap_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 62 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 63 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 __heap_base
<> 144:ef7eb2e8f9f7 66 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 67 __heap_limit EQU (__initial_sp - Stack_Size)
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 PRESERVE8
<> 144:ef7eb2e8f9f7 70 THUMB
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 74 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 75 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 76 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 77 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 80 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 81 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 82 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 83 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 84 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 85 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 86 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 87 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 88 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 89 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 90 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 91 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 92 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 93 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 94 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 ; External Interrupts
<> 144:ef7eb2e8f9f7 97 DCD WWDG_IRQHandler ; Window Watchdog
<> 144:ef7eb2e8f9f7 98 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 99 DCD RTC_IRQHandler ; RTC through EXTI Line
<> 144:ef7eb2e8f9f7 100 DCD FLASH_IRQHandler ; FLASH
<> 144:ef7eb2e8f9f7 101 DCD RCC_IRQHandler ; RCC
<> 144:ef7eb2e8f9f7 102 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
<> 144:ef7eb2e8f9f7 103 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
<> 144:ef7eb2e8f9f7 104 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
<> 144:ef7eb2e8f9f7 105 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 106 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
<> 144:ef7eb2e8f9f7 107 DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
<> 144:ef7eb2e8f9f7 108 DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
<> 144:ef7eb2e8f9f7 109 DCD ADC1_IRQHandler ; ADC1
<> 144:ef7eb2e8f9f7 110 DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
<> 144:ef7eb2e8f9f7 111 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
<> 144:ef7eb2e8f9f7 112 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 113 DCD TIM3_IRQHandler ; TIM3
<> 144:ef7eb2e8f9f7 114 DCD TIM6_IRQHandler ; TIM6
<> 144:ef7eb2e8f9f7 115 DCD TIM7_IRQHandler ; TIM7
<> 144:ef7eb2e8f9f7 116 DCD TIM14_IRQHandler ; TIM14
<> 144:ef7eb2e8f9f7 117 DCD TIM15_IRQHandler ; TIM15
<> 144:ef7eb2e8f9f7 118 DCD TIM16_IRQHandler ; TIM16
<> 144:ef7eb2e8f9f7 119 DCD TIM17_IRQHandler ; TIM17
<> 144:ef7eb2e8f9f7 120 DCD I2C1_IRQHandler ; I2C1
<> 144:ef7eb2e8f9f7 121 DCD I2C2_IRQHandler ; I2C2
<> 144:ef7eb2e8f9f7 122 DCD SPI1_IRQHandler ; SPI1
<> 144:ef7eb2e8f9f7 123 DCD SPI2_IRQHandler ; SPI2
<> 144:ef7eb2e8f9f7 124 DCD USART1_IRQHandler ; USART1
<> 144:ef7eb2e8f9f7 125 DCD USART2_IRQHandler ; USART2
<> 144:ef7eb2e8f9f7 126 DCD USART3_4_IRQHandler ; USART3 & USART4
<> 144:ef7eb2e8f9f7 127 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 128 DCD USB_IRQHandler ; USB
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 __Vectors_End
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 ; Reset handler routine
<> 144:ef7eb2e8f9f7 137 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 138 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 139 IMPORT __main
<> 144:ef7eb2e8f9f7 140 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 141 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 142 BLX R0
<> 144:ef7eb2e8f9f7 143 LDR R0, =__main
<> 144:ef7eb2e8f9f7 144 BX R0
<> 144:ef7eb2e8f9f7 145 ENDP
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 150 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 151 B .
<> 144:ef7eb2e8f9f7 152 ENDP
<> 144:ef7eb2e8f9f7 153 HardFault_Handler\
<> 144:ef7eb2e8f9f7 154 PROC
<> 144:ef7eb2e8f9f7 155 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 156 B .
<> 144:ef7eb2e8f9f7 157 ENDP
<> 144:ef7eb2e8f9f7 158 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 159 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 160 B .
<> 144:ef7eb2e8f9f7 161 ENDP
<> 144:ef7eb2e8f9f7 162 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 163 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 164 B .
<> 144:ef7eb2e8f9f7 165 ENDP
<> 144:ef7eb2e8f9f7 166 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 167 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 168 B .
<> 144:ef7eb2e8f9f7 169 ENDP
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 Default_Handler PROC
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 EXPORT WWDG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 174 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 175 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 176 EXPORT RCC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 177 EXPORT EXTI0_1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 178 EXPORT EXTI2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 179 EXPORT EXTI4_15_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 180 EXPORT DMA1_Channel1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 181 EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 182 EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 183 EXPORT ADC1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 184 EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 185 EXPORT TIM1_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 186 EXPORT TIM3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 187 EXPORT TIM6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 188 EXPORT TIM7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 189 EXPORT TIM14_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 190 EXPORT TIM15_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 191 EXPORT TIM16_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 192 EXPORT TIM17_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 193 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 194 EXPORT I2C2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 195 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 196 EXPORT SPI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 197 EXPORT USART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 198 EXPORT USART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 199 EXPORT USART3_4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 200 EXPORT USB_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 204 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 205 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 206 RCC_IRQHandler
<> 144:ef7eb2e8f9f7 207 EXTI0_1_IRQHandler
<> 144:ef7eb2e8f9f7 208 EXTI2_3_IRQHandler
<> 144:ef7eb2e8f9f7 209 EXTI4_15_IRQHandler
<> 144:ef7eb2e8f9f7 210 DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 211 DMA1_Channel2_3_IRQHandler
<> 144:ef7eb2e8f9f7 212 DMA1_Channel4_5_IRQHandler
<> 144:ef7eb2e8f9f7 213 ADC1_IRQHandler
<> 144:ef7eb2e8f9f7 214 TIM1_BRK_UP_TRG_COM_IRQHandler
<> 144:ef7eb2e8f9f7 215 TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 216 TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 217 TIM6_IRQHandler
<> 144:ef7eb2e8f9f7 218 TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 219 TIM14_IRQHandler
<> 144:ef7eb2e8f9f7 220 TIM15_IRQHandler
<> 144:ef7eb2e8f9f7 221 TIM16_IRQHandler
<> 144:ef7eb2e8f9f7 222 TIM17_IRQHandler
<> 144:ef7eb2e8f9f7 223 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 224 I2C2_IRQHandler
<> 144:ef7eb2e8f9f7 225 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 226 SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 227 USART1_IRQHandler
<> 144:ef7eb2e8f9f7 228 USART2_IRQHandler
<> 144:ef7eb2e8f9f7 229 USART3_4_IRQHandler
<> 144:ef7eb2e8f9f7 230 USB_IRQHandler
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 B .
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 ENDP
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 ALIGN
<> 144:ef7eb2e8f9f7 237 END