mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 187:0387e8f68319
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 181:57724642e740 | 1 | /* mbed Microcontroller Library |
AnnaBridge | 181:57724642e740 | 2 | * Copyright (c) 2006-2013 ARM Limited |
AnnaBridge | 181:57724642e740 | 3 | * |
AnnaBridge | 181:57724642e740 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
AnnaBridge | 181:57724642e740 | 5 | * you may not use this file except in compliance with the License. |
AnnaBridge | 181:57724642e740 | 6 | * You may obtain a copy of the License at |
AnnaBridge | 181:57724642e740 | 7 | * |
AnnaBridge | 181:57724642e740 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
AnnaBridge | 181:57724642e740 | 9 | * |
AnnaBridge | 181:57724642e740 | 10 | * Unless required by applicable law or agreed to in writing, software |
AnnaBridge | 181:57724642e740 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
AnnaBridge | 181:57724642e740 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
AnnaBridge | 181:57724642e740 | 13 | * See the License for the specific language governing permissions and |
AnnaBridge | 181:57724642e740 | 14 | * limitations under the License. |
AnnaBridge | 181:57724642e740 | 15 | */ |
AnnaBridge | 181:57724642e740 | 16 | #include "mbed_assert.h" |
AnnaBridge | 181:57724642e740 | 17 | #include "pwmout_api.h" |
AnnaBridge | 181:57724642e740 | 18 | #include "cmsis.h" |
AnnaBridge | 181:57724642e740 | 19 | #include "PeripheralPins.h" |
AnnaBridge | 181:57724642e740 | 20 | #include "RZ_A1_Init.h" |
AnnaBridge | 181:57724642e740 | 21 | #include "iodefine.h" |
AnnaBridge | 181:57724642e740 | 22 | #include "gpio_addrdefine.h" |
AnnaBridge | 181:57724642e740 | 23 | #include "mbed_drv_cfg.h" |
AnnaBridge | 187:0387e8f68319 | 24 | #include "mtu2.h" |
AnnaBridge | 181:57724642e740 | 25 | |
AnnaBridge | 181:57724642e740 | 26 | #define MTU2_PWM_OFFSET 0x20 |
AnnaBridge | 181:57724642e740 | 27 | |
AnnaBridge | 181:57724642e740 | 28 | #ifdef FUNC_MOTOR_CTL_PWM |
AnnaBridge | 181:57724642e740 | 29 | typedef enum { |
AnnaBridge | 181:57724642e740 | 30 | PWM1A = 0, |
AnnaBridge | 181:57724642e740 | 31 | PWM1B, |
AnnaBridge | 181:57724642e740 | 32 | PWM1C, |
AnnaBridge | 181:57724642e740 | 33 | PWM1D, |
AnnaBridge | 181:57724642e740 | 34 | PWM1E, |
AnnaBridge | 181:57724642e740 | 35 | PWM1F, |
AnnaBridge | 181:57724642e740 | 36 | PWM1G, |
AnnaBridge | 181:57724642e740 | 37 | PWM1H, |
AnnaBridge | 181:57724642e740 | 38 | PWM2A = 0x10, |
AnnaBridge | 181:57724642e740 | 39 | PWM2B, |
AnnaBridge | 181:57724642e740 | 40 | PWM2C, |
AnnaBridge | 181:57724642e740 | 41 | PWM2D, |
AnnaBridge | 181:57724642e740 | 42 | PWM2E, |
AnnaBridge | 181:57724642e740 | 43 | PWM2F, |
AnnaBridge | 181:57724642e740 | 44 | PWM2G, |
AnnaBridge | 181:57724642e740 | 45 | PWM2H, |
AnnaBridge | 181:57724642e740 | 46 | } PWMType; |
AnnaBridge | 181:57724642e740 | 47 | |
AnnaBridge | 181:57724642e740 | 48 | static const PWMType PORT[] = { |
AnnaBridge | 181:57724642e740 | 49 | PWM1A, // PWM_PWM1A |
AnnaBridge | 181:57724642e740 | 50 | PWM1B, // PWM_PWM1B |
AnnaBridge | 181:57724642e740 | 51 | PWM1C, // PWM_PWM1C |
AnnaBridge | 181:57724642e740 | 52 | PWM1D, // PWM_PWM1D |
AnnaBridge | 181:57724642e740 | 53 | PWM1E, // PWM_PWM1E |
AnnaBridge | 181:57724642e740 | 54 | PWM1F, // PWM_PWM1F |
AnnaBridge | 181:57724642e740 | 55 | PWM1G, // PWM_PWM1G |
AnnaBridge | 181:57724642e740 | 56 | PWM1H, // PWM_PWM1H |
AnnaBridge | 181:57724642e740 | 57 | PWM2A, // PWM_PWM2A |
AnnaBridge | 181:57724642e740 | 58 | PWM2B, // PWM_PWM2B |
AnnaBridge | 181:57724642e740 | 59 | PWM2C, // PWM_PWM2C |
AnnaBridge | 181:57724642e740 | 60 | PWM2D, // PWM_PWM2D |
AnnaBridge | 181:57724642e740 | 61 | PWM2E, // PWM_PWM2E |
AnnaBridge | 181:57724642e740 | 62 | PWM2F, // PWM_PWM2F |
AnnaBridge | 181:57724642e740 | 63 | PWM2G, // PWM_PWM2G |
AnnaBridge | 181:57724642e740 | 64 | PWM2H, // PWM_PWM2H |
AnnaBridge | 181:57724642e740 | 65 | }; |
AnnaBridge | 181:57724642e740 | 66 | |
AnnaBridge | 181:57724642e740 | 67 | static __IO uint16_t *PWM_MATCH[] = { |
AnnaBridge | 181:57724642e740 | 68 | &PWMPWBFR_1A, // PWM_PWM1A |
AnnaBridge | 181:57724642e740 | 69 | &PWMPWBFR_1A, // PWM_PWM1B |
AnnaBridge | 181:57724642e740 | 70 | &PWMPWBFR_1C, // PWM_PWM1C |
AnnaBridge | 181:57724642e740 | 71 | &PWMPWBFR_1C, // PWM_PWM1D |
AnnaBridge | 181:57724642e740 | 72 | &PWMPWBFR_1E, // PWM_PWM1E |
AnnaBridge | 181:57724642e740 | 73 | &PWMPWBFR_1E, // PWM_PWM1F |
AnnaBridge | 181:57724642e740 | 74 | &PWMPWBFR_1G, // PWM_PWM1G |
AnnaBridge | 181:57724642e740 | 75 | &PWMPWBFR_1G, // PWM_PWM1H |
AnnaBridge | 181:57724642e740 | 76 | &PWMPWBFR_2A, // PWM_PWM2A |
AnnaBridge | 181:57724642e740 | 77 | &PWMPWBFR_2A, // PWM_PWM2B |
AnnaBridge | 181:57724642e740 | 78 | &PWMPWBFR_2C, // PWM_PWM2C |
AnnaBridge | 181:57724642e740 | 79 | &PWMPWBFR_2C, // PWM_PWM2D |
AnnaBridge | 181:57724642e740 | 80 | &PWMPWBFR_2E, // PWM_PWM2E |
AnnaBridge | 181:57724642e740 | 81 | &PWMPWBFR_2E, // PWM_PWM2F |
AnnaBridge | 181:57724642e740 | 82 | &PWMPWBFR_2G, // PWM_PWM2G |
AnnaBridge | 181:57724642e740 | 83 | &PWMPWBFR_2G, // PWM_PWM2H |
AnnaBridge | 181:57724642e740 | 84 | }; |
AnnaBridge | 181:57724642e740 | 85 | |
AnnaBridge | 181:57724642e740 | 86 | static uint16_t init_period_ch1 = 0; |
AnnaBridge | 181:57724642e740 | 87 | static uint16_t init_period_ch2 = 0; |
AnnaBridge | 181:57724642e740 | 88 | static int32_t period_ch1 = 1; |
AnnaBridge | 181:57724642e740 | 89 | static int32_t period_ch2 = 1; |
AnnaBridge | 181:57724642e740 | 90 | #endif |
AnnaBridge | 181:57724642e740 | 91 | |
AnnaBridge | 181:57724642e740 | 92 | #ifdef FUMC_MTU2_PWM |
AnnaBridge | 181:57724642e740 | 93 | #define MTU2_PWM_SIGNAL 2 |
AnnaBridge | 181:57724642e740 | 94 | |
AnnaBridge | 181:57724642e740 | 95 | typedef enum { |
AnnaBridge | 181:57724642e740 | 96 | TIOC0A = 0, |
AnnaBridge | 181:57724642e740 | 97 | TIOC0B, |
AnnaBridge | 181:57724642e740 | 98 | TIOC0C, |
AnnaBridge | 181:57724642e740 | 99 | TIOC0D, |
AnnaBridge | 181:57724642e740 | 100 | TIOC1A = 0x10, |
AnnaBridge | 181:57724642e740 | 101 | TIOC1B, |
AnnaBridge | 181:57724642e740 | 102 | TIOC2A = 0x20, |
AnnaBridge | 181:57724642e740 | 103 | TIOC2B, |
AnnaBridge | 181:57724642e740 | 104 | TIOC3A = 0x30, |
AnnaBridge | 181:57724642e740 | 105 | TIOC3B, |
AnnaBridge | 181:57724642e740 | 106 | TIOC3C, |
AnnaBridge | 181:57724642e740 | 107 | TIOC3D, |
AnnaBridge | 181:57724642e740 | 108 | TIOC4A = 0x40, |
AnnaBridge | 181:57724642e740 | 109 | TIOC4B, |
AnnaBridge | 181:57724642e740 | 110 | TIOC4C, |
AnnaBridge | 181:57724642e740 | 111 | TIOC4D, |
AnnaBridge | 181:57724642e740 | 112 | } MTU2_PWMType; |
AnnaBridge | 181:57724642e740 | 113 | |
AnnaBridge | 181:57724642e740 | 114 | static const MTU2_PWMType MTU2_PORT[] = { |
AnnaBridge | 181:57724642e740 | 115 | TIOC0A, // PWM_TIOC0A |
AnnaBridge | 181:57724642e740 | 116 | TIOC0C, // PWM_TIOC0C |
AnnaBridge | 181:57724642e740 | 117 | TIOC1A, // PWM_TIOC1A |
AnnaBridge | 181:57724642e740 | 118 | TIOC2A, // PWM_TIOC2A |
AnnaBridge | 181:57724642e740 | 119 | TIOC3A, // PWM_TIOC3A |
AnnaBridge | 181:57724642e740 | 120 | TIOC3C, // PWM_TIOC3C |
AnnaBridge | 181:57724642e740 | 121 | TIOC4A, // PWM_TIOC4A |
AnnaBridge | 181:57724642e740 | 122 | TIOC4C, // PWM_TIOC4C |
AnnaBridge | 181:57724642e740 | 123 | }; |
AnnaBridge | 181:57724642e740 | 124 | |
AnnaBridge | 181:57724642e740 | 125 | static __IO uint16_t *MTU2_PWM_MATCH[][MTU2_PWM_SIGNAL] = { |
AnnaBridge | 181:57724642e740 | 126 | { &MTU2TGRA_0, &MTU2TGRB_0 }, // PWM_TIOC0A |
AnnaBridge | 181:57724642e740 | 127 | { &MTU2TGRC_0, &MTU2TGRD_0 }, // PWM_TIOC0C |
AnnaBridge | 181:57724642e740 | 128 | { &MTU2TGRA_1, &MTU2TGRB_1 }, // PWM_TIOC1A |
AnnaBridge | 181:57724642e740 | 129 | { &MTU2TGRA_2, &MTU2TGRB_2 }, // PWM_TIOC2A |
AnnaBridge | 181:57724642e740 | 130 | { &MTU2TGRA_3, &MTU2TGRB_3 }, // PWM_TIOC3A |
AnnaBridge | 181:57724642e740 | 131 | { &MTU2TGRC_3, &MTU2TGRD_3 }, // PWM_TIOC3C |
AnnaBridge | 181:57724642e740 | 132 | { &MTU2TGRA_4, &MTU2TGRB_4 }, // PWM_TIOC4A |
AnnaBridge | 181:57724642e740 | 133 | { &MTU2TGRC_4, &MTU2TGRD_4 }, // PWM_TIOC4C |
AnnaBridge | 181:57724642e740 | 134 | }; |
AnnaBridge | 181:57724642e740 | 135 | |
AnnaBridge | 181:57724642e740 | 136 | static __IO uint8_t *TCR_MATCH[] = { |
AnnaBridge | 181:57724642e740 | 137 | &MTU2TCR_0, |
AnnaBridge | 181:57724642e740 | 138 | &MTU2TCR_1, |
AnnaBridge | 181:57724642e740 | 139 | &MTU2TCR_2, |
AnnaBridge | 181:57724642e740 | 140 | &MTU2TCR_3, |
AnnaBridge | 181:57724642e740 | 141 | &MTU2TCR_4, |
AnnaBridge | 181:57724642e740 | 142 | }; |
AnnaBridge | 181:57724642e740 | 143 | |
AnnaBridge | 181:57724642e740 | 144 | static __IO uint8_t *TIORH_MATCH[] = { |
AnnaBridge | 181:57724642e740 | 145 | &MTU2TIORH_0, |
AnnaBridge | 181:57724642e740 | 146 | &MTU2TIOR_1, |
AnnaBridge | 181:57724642e740 | 147 | &MTU2TIOR_2, |
AnnaBridge | 181:57724642e740 | 148 | &MTU2TIORH_3, |
AnnaBridge | 181:57724642e740 | 149 | &MTU2TIORH_4, |
AnnaBridge | 181:57724642e740 | 150 | }; |
AnnaBridge | 181:57724642e740 | 151 | |
AnnaBridge | 181:57724642e740 | 152 | static __IO uint8_t *TIORL_MATCH[] = { |
AnnaBridge | 181:57724642e740 | 153 | &MTU2TIORL_0, |
AnnaBridge | 181:57724642e740 | 154 | NULL, |
AnnaBridge | 181:57724642e740 | 155 | NULL, |
AnnaBridge | 181:57724642e740 | 156 | &MTU2TIORL_3, |
AnnaBridge | 181:57724642e740 | 157 | &MTU2TIORL_4, |
AnnaBridge | 181:57724642e740 | 158 | }; |
AnnaBridge | 181:57724642e740 | 159 | |
AnnaBridge | 181:57724642e740 | 160 | static __IO uint16_t *TGRA_MATCH[] = { |
AnnaBridge | 181:57724642e740 | 161 | &MTU2TGRA_0, |
AnnaBridge | 181:57724642e740 | 162 | &MTU2TGRA_1, |
AnnaBridge | 181:57724642e740 | 163 | &MTU2TGRA_2, |
AnnaBridge | 181:57724642e740 | 164 | &MTU2TGRA_3, |
AnnaBridge | 181:57724642e740 | 165 | &MTU2TGRA_4, |
AnnaBridge | 181:57724642e740 | 166 | }; |
AnnaBridge | 181:57724642e740 | 167 | |
AnnaBridge | 181:57724642e740 | 168 | static __IO uint16_t *TGRC_MATCH[] = { |
AnnaBridge | 181:57724642e740 | 169 | &MTU2TGRC_0, |
AnnaBridge | 181:57724642e740 | 170 | NULL, |
AnnaBridge | 181:57724642e740 | 171 | NULL, |
AnnaBridge | 181:57724642e740 | 172 | &MTU2TGRC_3, |
AnnaBridge | 181:57724642e740 | 173 | &MTU2TGRC_4, |
AnnaBridge | 181:57724642e740 | 174 | }; |
AnnaBridge | 181:57724642e740 | 175 | |
AnnaBridge | 181:57724642e740 | 176 | static __IO uint8_t *TMDR_MATCH[] = { |
AnnaBridge | 181:57724642e740 | 177 | &MTU2TMDR_0, |
AnnaBridge | 181:57724642e740 | 178 | &MTU2TMDR_1, |
AnnaBridge | 181:57724642e740 | 179 | &MTU2TMDR_2, |
AnnaBridge | 181:57724642e740 | 180 | &MTU2TMDR_3, |
AnnaBridge | 181:57724642e740 | 181 | &MTU2TMDR_4, |
AnnaBridge | 181:57724642e740 | 182 | }; |
AnnaBridge | 181:57724642e740 | 183 | |
AnnaBridge | 181:57724642e740 | 184 | static int MAX_PERIOD[] = { |
AnnaBridge | 181:57724642e740 | 185 | 125000, |
AnnaBridge | 181:57724642e740 | 186 | 503000, |
AnnaBridge | 181:57724642e740 | 187 | 2000000, |
AnnaBridge | 181:57724642e740 | 188 | 2000000, |
AnnaBridge | 181:57724642e740 | 189 | 2000000, |
AnnaBridge | 181:57724642e740 | 190 | }; |
AnnaBridge | 181:57724642e740 | 191 | |
AnnaBridge | 181:57724642e740 | 192 | typedef enum { |
AnnaBridge | 181:57724642e740 | 193 | MTU2_PULSE = 0, |
AnnaBridge | 181:57724642e740 | 194 | MTU2_PERIOD |
AnnaBridge | 181:57724642e740 | 195 | } MTU2Signal; |
AnnaBridge | 181:57724642e740 | 196 | |
AnnaBridge | 181:57724642e740 | 197 | static uint16_t init_mtu2_period_ch[5] = {0}; |
AnnaBridge | 181:57724642e740 | 198 | static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1}; |
AnnaBridge | 181:57724642e740 | 199 | #endif |
AnnaBridge | 181:57724642e740 | 200 | |
AnnaBridge | 181:57724642e740 | 201 | void pwmout_init(pwmout_t* obj, PinName pin) { |
AnnaBridge | 181:57724642e740 | 202 | // determine the channel |
AnnaBridge | 181:57724642e740 | 203 | PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); |
AnnaBridge | 181:57724642e740 | 204 | MBED_ASSERT(pwm != (PWMName)NC); |
AnnaBridge | 181:57724642e740 | 205 | |
AnnaBridge | 181:57724642e740 | 206 | if (pwm >= MTU2_PWM_OFFSET) { |
AnnaBridge | 181:57724642e740 | 207 | #ifdef FUMC_MTU2_PWM |
AnnaBridge | 181:57724642e740 | 208 | /* PWM by MTU2 */ |
AnnaBridge | 181:57724642e740 | 209 | int tmp_pwm; |
AnnaBridge | 181:57724642e740 | 210 | |
AnnaBridge | 181:57724642e740 | 211 | // power on |
AnnaBridge | 187:0387e8f68319 | 212 | mtu2_init(); |
AnnaBridge | 181:57724642e740 | 213 | |
AnnaBridge | 181:57724642e740 | 214 | obj->pwm = pwm; |
AnnaBridge | 181:57724642e740 | 215 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); |
AnnaBridge | 181:57724642e740 | 216 | if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) { |
AnnaBridge | 181:57724642e740 | 217 | obj->ch = 4; |
AnnaBridge | 181:57724642e740 | 218 | MTU2TOER |= 0x36; |
AnnaBridge | 181:57724642e740 | 219 | } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) { |
AnnaBridge | 181:57724642e740 | 220 | obj->ch = 3; |
AnnaBridge | 181:57724642e740 | 221 | MTU2TOER |= 0x09; |
AnnaBridge | 181:57724642e740 | 222 | } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) { |
AnnaBridge | 181:57724642e740 | 223 | obj->ch = 2; |
AnnaBridge | 181:57724642e740 | 224 | } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) { |
AnnaBridge | 181:57724642e740 | 225 | obj->ch = 1; |
AnnaBridge | 181:57724642e740 | 226 | } else { |
AnnaBridge | 181:57724642e740 | 227 | obj->ch = 0; |
AnnaBridge | 181:57724642e740 | 228 | } |
AnnaBridge | 181:57724642e740 | 229 | // Wire pinout |
AnnaBridge | 181:57724642e740 | 230 | pinmap_pinout(pin, PinMap_PWM); |
AnnaBridge | 181:57724642e740 | 231 | |
AnnaBridge | 181:57724642e740 | 232 | int bitmask = 1 << (pin & 0xf); |
AnnaBridge | 181:57724642e740 | 233 | |
AnnaBridge | 181:57724642e740 | 234 | *PMSR(PINGROUP(pin)) = (bitmask << 16) | 0; |
AnnaBridge | 181:57724642e740 | 235 | |
AnnaBridge | 181:57724642e740 | 236 | // default duty 0.0f |
AnnaBridge | 181:57724642e740 | 237 | pwmout_write(obj, 0); |
AnnaBridge | 181:57724642e740 | 238 | if (init_mtu2_period_ch[obj->ch] == 0) { |
AnnaBridge | 181:57724642e740 | 239 | // default period 1ms |
AnnaBridge | 181:57724642e740 | 240 | pwmout_period_us(obj, 1000); |
AnnaBridge | 181:57724642e740 | 241 | init_mtu2_period_ch[obj->ch] = 1; |
AnnaBridge | 181:57724642e740 | 242 | } |
AnnaBridge | 181:57724642e740 | 243 | #endif |
AnnaBridge | 181:57724642e740 | 244 | } else { |
AnnaBridge | 181:57724642e740 | 245 | #ifdef FUNC_MOTOR_CTL_PWM |
AnnaBridge | 181:57724642e740 | 246 | /* PWM */ |
AnnaBridge | 181:57724642e740 | 247 | // power on |
AnnaBridge | 181:57724642e740 | 248 | CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30); |
AnnaBridge | 181:57724642e740 | 249 | |
AnnaBridge | 181:57724642e740 | 250 | obj->pwm = pwm; |
AnnaBridge | 181:57724642e740 | 251 | if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) { |
AnnaBridge | 181:57724642e740 | 252 | obj->ch = 2; |
AnnaBridge | 181:57724642e740 | 253 | PWMPWPR_2 = 0x00; |
AnnaBridge | 181:57724642e740 | 254 | } else { |
AnnaBridge | 181:57724642e740 | 255 | obj->ch = 1; |
AnnaBridge | 181:57724642e740 | 256 | PWMPWPR_1 = 0x00; |
AnnaBridge | 181:57724642e740 | 257 | } |
AnnaBridge | 181:57724642e740 | 258 | |
AnnaBridge | 181:57724642e740 | 259 | // Wire pinout |
AnnaBridge | 181:57724642e740 | 260 | pinmap_pinout(pin, PinMap_PWM); |
AnnaBridge | 181:57724642e740 | 261 | |
AnnaBridge | 181:57724642e740 | 262 | // default to 491us: standard for servos, and fine for e.g. brightness control |
AnnaBridge | 181:57724642e740 | 263 | pwmout_write(obj, 0); |
AnnaBridge | 181:57724642e740 | 264 | if ((obj->ch == 2) && (init_period_ch2 == 0)) { |
AnnaBridge | 181:57724642e740 | 265 | pwmout_period_us(obj, 491); |
AnnaBridge | 181:57724642e740 | 266 | init_period_ch2 = 1; |
AnnaBridge | 181:57724642e740 | 267 | } |
AnnaBridge | 181:57724642e740 | 268 | if ((obj->ch == 1) && (init_period_ch1 == 0)) { |
AnnaBridge | 181:57724642e740 | 269 | pwmout_period_us(obj, 491); |
AnnaBridge | 181:57724642e740 | 270 | init_period_ch1 = 1; |
AnnaBridge | 181:57724642e740 | 271 | } |
AnnaBridge | 181:57724642e740 | 272 | #endif |
AnnaBridge | 181:57724642e740 | 273 | } |
AnnaBridge | 181:57724642e740 | 274 | } |
AnnaBridge | 181:57724642e740 | 275 | |
AnnaBridge | 181:57724642e740 | 276 | void pwmout_free(pwmout_t* obj) { |
AnnaBridge | 181:57724642e740 | 277 | pwmout_write(obj, 0); |
AnnaBridge | 187:0387e8f68319 | 278 | mtu2_free(); |
AnnaBridge | 181:57724642e740 | 279 | } |
AnnaBridge | 181:57724642e740 | 280 | |
AnnaBridge | 181:57724642e740 | 281 | void pwmout_write(pwmout_t* obj, float value) { |
AnnaBridge | 181:57724642e740 | 282 | uint32_t wk_cycle; |
AnnaBridge | 181:57724642e740 | 283 | |
AnnaBridge | 181:57724642e740 | 284 | if (obj->pwm >= MTU2_PWM_OFFSET) { |
AnnaBridge | 181:57724642e740 | 285 | #ifdef FUMC_MTU2_PWM |
AnnaBridge | 181:57724642e740 | 286 | /* PWM by MTU2 */ |
AnnaBridge | 181:57724642e740 | 287 | int tmp_pwm; |
AnnaBridge | 181:57724642e740 | 288 | |
AnnaBridge | 181:57724642e740 | 289 | if (value < 0.0f) { |
AnnaBridge | 181:57724642e740 | 290 | value = 0.0f; |
AnnaBridge | 181:57724642e740 | 291 | } else if (value > 1.0f) { |
AnnaBridge | 181:57724642e740 | 292 | value = 1.0f; |
AnnaBridge | 181:57724642e740 | 293 | } else { |
AnnaBridge | 181:57724642e740 | 294 | // Do Nothing |
AnnaBridge | 181:57724642e740 | 295 | } |
AnnaBridge | 181:57724642e740 | 296 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); |
AnnaBridge | 181:57724642e740 | 297 | wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; |
AnnaBridge | 181:57724642e740 | 298 | // set channel match to percentage |
AnnaBridge | 181:57724642e740 | 299 | if (value == 1.0f) { |
AnnaBridge | 181:57724642e740 | 300 | *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)(wk_cycle - 1); |
AnnaBridge | 181:57724642e740 | 301 | } else { |
AnnaBridge | 181:57724642e740 | 302 | *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value); |
AnnaBridge | 181:57724642e740 | 303 | } |
AnnaBridge | 181:57724642e740 | 304 | #endif |
AnnaBridge | 181:57724642e740 | 305 | } else { |
AnnaBridge | 181:57724642e740 | 306 | #ifdef FUNC_MOTOR_CTL_PWM |
AnnaBridge | 181:57724642e740 | 307 | uint16_t v; |
AnnaBridge | 181:57724642e740 | 308 | |
AnnaBridge | 181:57724642e740 | 309 | /* PWM */ |
AnnaBridge | 181:57724642e740 | 310 | if (value < 0.0f) { |
AnnaBridge | 181:57724642e740 | 311 | value = 0.0f; |
AnnaBridge | 181:57724642e740 | 312 | } else if (value > 1.0f) { |
AnnaBridge | 181:57724642e740 | 313 | value = 1.0f; |
AnnaBridge | 181:57724642e740 | 314 | } else { |
AnnaBridge | 181:57724642e740 | 315 | // Do Nothing |
AnnaBridge | 181:57724642e740 | 316 | } |
AnnaBridge | 181:57724642e740 | 317 | |
AnnaBridge | 181:57724642e740 | 318 | if (obj->ch == 2) { |
AnnaBridge | 181:57724642e740 | 319 | wk_cycle = PWMPWCYR_2 & 0x03ff; |
AnnaBridge | 181:57724642e740 | 320 | } else { |
AnnaBridge | 181:57724642e740 | 321 | wk_cycle = PWMPWCYR_1 & 0x03ff; |
AnnaBridge | 181:57724642e740 | 322 | } |
AnnaBridge | 181:57724642e740 | 323 | |
AnnaBridge | 181:57724642e740 | 324 | // set channel match to percentage |
AnnaBridge | 181:57724642e740 | 325 | v = (uint16_t)((float)wk_cycle * value); |
AnnaBridge | 181:57724642e740 | 326 | *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12)); |
AnnaBridge | 181:57724642e740 | 327 | #endif |
AnnaBridge | 181:57724642e740 | 328 | } |
AnnaBridge | 181:57724642e740 | 329 | } |
AnnaBridge | 181:57724642e740 | 330 | |
AnnaBridge | 181:57724642e740 | 331 | float pwmout_read(pwmout_t* obj) { |
AnnaBridge | 181:57724642e740 | 332 | uint32_t wk_cycle; |
AnnaBridge | 181:57724642e740 | 333 | float value; |
AnnaBridge | 181:57724642e740 | 334 | |
AnnaBridge | 181:57724642e740 | 335 | if (obj->pwm >= MTU2_PWM_OFFSET) { |
AnnaBridge | 181:57724642e740 | 336 | #ifdef FUMC_MTU2_PWM |
AnnaBridge | 181:57724642e740 | 337 | /* PWM by MTU2 */ |
AnnaBridge | 181:57724642e740 | 338 | uint32_t wk_pulse; |
AnnaBridge | 181:57724642e740 | 339 | int tmp_pwm; |
AnnaBridge | 181:57724642e740 | 340 | |
AnnaBridge | 181:57724642e740 | 341 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); |
AnnaBridge | 181:57724642e740 | 342 | wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; |
AnnaBridge | 181:57724642e740 | 343 | wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff; |
AnnaBridge | 181:57724642e740 | 344 | value = ((float)wk_pulse / (float)wk_cycle); |
AnnaBridge | 181:57724642e740 | 345 | #endif |
AnnaBridge | 181:57724642e740 | 346 | } else { |
AnnaBridge | 181:57724642e740 | 347 | #ifdef FUNC_MOTOR_CTL_PWM |
AnnaBridge | 181:57724642e740 | 348 | /* PWM */ |
AnnaBridge | 181:57724642e740 | 349 | if (obj->ch == 2) { |
AnnaBridge | 181:57724642e740 | 350 | wk_cycle = PWMPWCYR_2 & 0x03ff; |
AnnaBridge | 181:57724642e740 | 351 | } else { |
AnnaBridge | 181:57724642e740 | 352 | wk_cycle = PWMPWCYR_1 & 0x03ff; |
AnnaBridge | 181:57724642e740 | 353 | } |
AnnaBridge | 181:57724642e740 | 354 | value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle); |
AnnaBridge | 181:57724642e740 | 355 | #endif |
AnnaBridge | 181:57724642e740 | 356 | } |
AnnaBridge | 181:57724642e740 | 357 | |
AnnaBridge | 181:57724642e740 | 358 | return (value > 1.0f) ? (1.0f) : (value); |
AnnaBridge | 181:57724642e740 | 359 | } |
AnnaBridge | 181:57724642e740 | 360 | |
AnnaBridge | 181:57724642e740 | 361 | void pwmout_period(pwmout_t* obj, float seconds) { |
AnnaBridge | 181:57724642e740 | 362 | pwmout_period_us(obj, seconds * 1000000.0f); |
AnnaBridge | 181:57724642e740 | 363 | } |
AnnaBridge | 181:57724642e740 | 364 | |
AnnaBridge | 181:57724642e740 | 365 | void pwmout_period_ms(pwmout_t* obj, int ms) { |
AnnaBridge | 181:57724642e740 | 366 | pwmout_period_us(obj, ms * 1000); |
AnnaBridge | 181:57724642e740 | 367 | } |
AnnaBridge | 181:57724642e740 | 368 | |
AnnaBridge | 181:57724642e740 | 369 | #ifdef FUNC_MOTOR_CTL_PWM |
AnnaBridge | 181:57724642e740 | 370 | static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ |
AnnaBridge | 181:57724642e740 | 371 | uint16_t wk_pwmpbfr; |
AnnaBridge | 181:57724642e740 | 372 | float value; |
AnnaBridge | 181:57724642e740 | 373 | uint16_t v; |
AnnaBridge | 181:57724642e740 | 374 | |
AnnaBridge | 181:57724642e740 | 375 | wk_pwmpbfr = *p_pwmpbfr; |
AnnaBridge | 181:57724642e740 | 376 | value = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle); |
AnnaBridge | 181:57724642e740 | 377 | v = (uint16_t)((float)new_cycle * value); |
AnnaBridge | 181:57724642e740 | 378 | *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000)); |
AnnaBridge | 181:57724642e740 | 379 | } |
AnnaBridge | 181:57724642e740 | 380 | #endif |
AnnaBridge | 181:57724642e740 | 381 | |
AnnaBridge | 181:57724642e740 | 382 | #ifdef FUMC_MTU2_PWM |
AnnaBridge | 181:57724642e740 | 383 | static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ |
AnnaBridge | 181:57724642e740 | 384 | uint16_t wk_pwmpbfr; |
AnnaBridge | 181:57724642e740 | 385 | float value; |
AnnaBridge | 181:57724642e740 | 386 | |
AnnaBridge | 181:57724642e740 | 387 | wk_pwmpbfr = *p_pwmpbfr; |
AnnaBridge | 181:57724642e740 | 388 | value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle); |
AnnaBridge | 181:57724642e740 | 389 | *p_pwmpbfr = (uint16_t)((float)new_cycle * value); |
AnnaBridge | 181:57724642e740 | 390 | } |
AnnaBridge | 181:57724642e740 | 391 | #endif |
AnnaBridge | 181:57724642e740 | 392 | |
AnnaBridge | 181:57724642e740 | 393 | // Set the PWM period, keeping the duty cycle the same. |
AnnaBridge | 181:57724642e740 | 394 | void pwmout_period_us(pwmout_t* obj, int us) { |
AnnaBridge | 181:57724642e740 | 395 | uint32_t pclk_base; |
AnnaBridge | 181:57724642e740 | 396 | uint32_t wk_cycle; |
AnnaBridge | 181:57724642e740 | 397 | uint32_t wk_cks = 0; |
AnnaBridge | 181:57724642e740 | 398 | uint16_t wk_last_cycle; |
AnnaBridge | 181:57724642e740 | 399 | |
AnnaBridge | 181:57724642e740 | 400 | if (obj->pwm >= MTU2_PWM_OFFSET) { |
AnnaBridge | 181:57724642e740 | 401 | #ifdef FUMC_MTU2_PWM |
AnnaBridge | 181:57724642e740 | 402 | uint64_t wk_cycle_mtu2; |
AnnaBridge | 181:57724642e740 | 403 | int max_us = 0; |
AnnaBridge | 181:57724642e740 | 404 | |
AnnaBridge | 181:57724642e740 | 405 | /* PWM by MTU2 */ |
AnnaBridge | 181:57724642e740 | 406 | int tmp_pwm; |
AnnaBridge | 181:57724642e740 | 407 | uint8_t tmp_tcr_up; |
AnnaBridge | 181:57724642e740 | 408 | uint8_t tmp_tstr_sp; |
AnnaBridge | 181:57724642e740 | 409 | uint8_t tmp_tstr_st; |
AnnaBridge | 181:57724642e740 | 410 | |
AnnaBridge | 181:57724642e740 | 411 | max_us = MAX_PERIOD[obj->ch]; |
AnnaBridge | 181:57724642e740 | 412 | if (us > max_us) { |
AnnaBridge | 181:57724642e740 | 413 | us = max_us; |
AnnaBridge | 181:57724642e740 | 414 | } else if (us < 1) { |
AnnaBridge | 181:57724642e740 | 415 | us = 1; |
AnnaBridge | 181:57724642e740 | 416 | } else { |
AnnaBridge | 181:57724642e740 | 417 | // Do Nothing |
AnnaBridge | 181:57724642e740 | 418 | } |
AnnaBridge | 181:57724642e740 | 419 | |
AnnaBridge | 181:57724642e740 | 420 | if (RZ_A1_IsClockMode0() == false) { |
AnnaBridge | 181:57724642e740 | 421 | pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK; |
AnnaBridge | 181:57724642e740 | 422 | } else { |
AnnaBridge | 181:57724642e740 | 423 | pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK; |
AnnaBridge | 181:57724642e740 | 424 | } |
AnnaBridge | 181:57724642e740 | 425 | |
AnnaBridge | 181:57724642e740 | 426 | wk_cycle_mtu2 = (uint64_t)pclk_base * us; |
AnnaBridge | 181:57724642e740 | 427 | while (wk_cycle_mtu2 >= 65535000000) { |
AnnaBridge | 181:57724642e740 | 428 | if ((obj->ch == 1) && (wk_cks == 3)) { |
AnnaBridge | 181:57724642e740 | 429 | wk_cks+=2; |
AnnaBridge | 181:57724642e740 | 430 | } else if ((obj->ch == 2) && (wk_cks == 3)) { |
AnnaBridge | 181:57724642e740 | 431 | wk_cycle_mtu2 >>= 2; |
AnnaBridge | 181:57724642e740 | 432 | wk_cks+=3; |
AnnaBridge | 181:57724642e740 | 433 | } |
AnnaBridge | 181:57724642e740 | 434 | wk_cycle_mtu2 >>= 2; |
AnnaBridge | 181:57724642e740 | 435 | wk_cks++; |
AnnaBridge | 181:57724642e740 | 436 | } |
AnnaBridge | 181:57724642e740 | 437 | wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000); |
AnnaBridge | 181:57724642e740 | 438 | |
AnnaBridge | 181:57724642e740 | 439 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); |
AnnaBridge | 181:57724642e740 | 440 | if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) { |
AnnaBridge | 181:57724642e740 | 441 | tmp_tcr_up = 0xC0; |
AnnaBridge | 181:57724642e740 | 442 | } else { |
AnnaBridge | 181:57724642e740 | 443 | tmp_tcr_up = 0x40; |
AnnaBridge | 181:57724642e740 | 444 | } |
AnnaBridge | 181:57724642e740 | 445 | if ((obj->ch == 4) || (obj->ch == 3)) { |
AnnaBridge | 181:57724642e740 | 446 | tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3))); |
AnnaBridge | 181:57724642e740 | 447 | tmp_tstr_st = (1 << (obj->ch + 3)); |
AnnaBridge | 181:57724642e740 | 448 | } else { |
AnnaBridge | 181:57724642e740 | 449 | tmp_tstr_sp = ~(0x38 | (1 << obj->ch)); |
AnnaBridge | 181:57724642e740 | 450 | tmp_tstr_st = (1 << obj->ch); |
AnnaBridge | 181:57724642e740 | 451 | } |
AnnaBridge | 181:57724642e740 | 452 | // Counter Stop |
AnnaBridge | 181:57724642e740 | 453 | MTU2TSTR &= tmp_tstr_sp; |
AnnaBridge | 181:57724642e740 | 454 | wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; |
AnnaBridge | 181:57724642e740 | 455 | *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks; |
AnnaBridge | 181:57724642e740 | 456 | *TIORH_MATCH[obj->ch] = 0x21; |
AnnaBridge | 181:57724642e740 | 457 | if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) { |
AnnaBridge | 181:57724642e740 | 458 | *TIORL_MATCH[obj->ch] = 0x21; |
AnnaBridge | 181:57724642e740 | 459 | } |
AnnaBridge | 181:57724642e740 | 460 | *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period |
AnnaBridge | 181:57724642e740 | 461 | |
AnnaBridge | 181:57724642e740 | 462 | // Set duty again(TGRA) |
AnnaBridge | 181:57724642e740 | 463 | set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle); |
AnnaBridge | 181:57724642e740 | 464 | if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) { |
AnnaBridge | 181:57724642e740 | 465 | // Set duty again(TGRC) |
AnnaBridge | 181:57724642e740 | 466 | set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle); |
AnnaBridge | 181:57724642e740 | 467 | } |
AnnaBridge | 181:57724642e740 | 468 | *TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1 |
AnnaBridge | 181:57724642e740 | 469 | |
AnnaBridge | 181:57724642e740 | 470 | // Counter Start |
AnnaBridge | 181:57724642e740 | 471 | MTU2TSTR |= tmp_tstr_st; |
AnnaBridge | 181:57724642e740 | 472 | // Save for future use |
AnnaBridge | 181:57724642e740 | 473 | mtu2_period_ch[obj->ch] = us; |
AnnaBridge | 181:57724642e740 | 474 | #endif |
AnnaBridge | 181:57724642e740 | 475 | } else { |
AnnaBridge | 181:57724642e740 | 476 | #ifdef FUNC_MOTOR_CTL_PWM |
AnnaBridge | 181:57724642e740 | 477 | /* PWM */ |
AnnaBridge | 181:57724642e740 | 478 | if (us > 491) { |
AnnaBridge | 181:57724642e740 | 479 | us = 491; |
AnnaBridge | 181:57724642e740 | 480 | } else if (us < 1) { |
AnnaBridge | 181:57724642e740 | 481 | us = 1; |
AnnaBridge | 181:57724642e740 | 482 | } else { |
AnnaBridge | 181:57724642e740 | 483 | // Do Nothing |
AnnaBridge | 181:57724642e740 | 484 | } |
AnnaBridge | 181:57724642e740 | 485 | |
AnnaBridge | 181:57724642e740 | 486 | if (RZ_A1_IsClockMode0() == false) { |
AnnaBridge | 181:57724642e740 | 487 | pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000; |
AnnaBridge | 181:57724642e740 | 488 | } else { |
AnnaBridge | 181:57724642e740 | 489 | pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000; |
AnnaBridge | 181:57724642e740 | 490 | } |
AnnaBridge | 181:57724642e740 | 491 | |
AnnaBridge | 181:57724642e740 | 492 | wk_cycle = pclk_base * us; |
AnnaBridge | 181:57724642e740 | 493 | while (wk_cycle >= 102350) { |
AnnaBridge | 181:57724642e740 | 494 | wk_cycle >>= 1; |
AnnaBridge | 181:57724642e740 | 495 | wk_cks++; |
AnnaBridge | 181:57724642e740 | 496 | } |
AnnaBridge | 181:57724642e740 | 497 | wk_cycle = (wk_cycle + 50) / 100; |
AnnaBridge | 181:57724642e740 | 498 | |
AnnaBridge | 181:57724642e740 | 499 | if (obj->ch == 2) { |
AnnaBridge | 181:57724642e740 | 500 | wk_last_cycle = PWMPWCYR_2 & 0x03ff; |
AnnaBridge | 181:57724642e740 | 501 | PWMPWCR_2 = 0xc0 | wk_cks; |
AnnaBridge | 181:57724642e740 | 502 | PWMPWCYR_2 = (uint16_t)wk_cycle; |
AnnaBridge | 181:57724642e740 | 503 | |
AnnaBridge | 181:57724642e740 | 504 | // Set duty again |
AnnaBridge | 181:57724642e740 | 505 | set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle); |
AnnaBridge | 181:57724642e740 | 506 | set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle); |
AnnaBridge | 181:57724642e740 | 507 | set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle); |
AnnaBridge | 181:57724642e740 | 508 | set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle); |
AnnaBridge | 181:57724642e740 | 509 | |
AnnaBridge | 181:57724642e740 | 510 | // Counter Start |
AnnaBridge | 181:57724642e740 | 511 | PWMPWCR_2 |= 0x08; |
AnnaBridge | 181:57724642e740 | 512 | |
AnnaBridge | 181:57724642e740 | 513 | // Save for future use |
AnnaBridge | 181:57724642e740 | 514 | period_ch2 = us; |
AnnaBridge | 181:57724642e740 | 515 | } else { |
AnnaBridge | 181:57724642e740 | 516 | wk_last_cycle = PWMPWCYR_1 & 0x03ff; |
AnnaBridge | 181:57724642e740 | 517 | PWMPWCR_1 = 0xc0 | wk_cks; |
AnnaBridge | 181:57724642e740 | 518 | PWMPWCYR_1 = (uint16_t)wk_cycle; |
AnnaBridge | 181:57724642e740 | 519 | |
AnnaBridge | 181:57724642e740 | 520 | // Set duty again |
AnnaBridge | 181:57724642e740 | 521 | set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle); |
AnnaBridge | 181:57724642e740 | 522 | set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle); |
AnnaBridge | 181:57724642e740 | 523 | set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle); |
AnnaBridge | 181:57724642e740 | 524 | set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle); |
AnnaBridge | 181:57724642e740 | 525 | |
AnnaBridge | 181:57724642e740 | 526 | // Counter Start |
AnnaBridge | 181:57724642e740 | 527 | PWMPWCR_1 |= 0x08; |
AnnaBridge | 181:57724642e740 | 528 | |
AnnaBridge | 181:57724642e740 | 529 | // Save for future use |
AnnaBridge | 181:57724642e740 | 530 | period_ch1 = us; |
AnnaBridge | 181:57724642e740 | 531 | } |
AnnaBridge | 181:57724642e740 | 532 | #endif |
AnnaBridge | 181:57724642e740 | 533 | } |
AnnaBridge | 181:57724642e740 | 534 | } |
AnnaBridge | 181:57724642e740 | 535 | |
AnnaBridge | 181:57724642e740 | 536 | void pwmout_pulsewidth(pwmout_t* obj, float seconds) { |
AnnaBridge | 181:57724642e740 | 537 | pwmout_pulsewidth_us(obj, seconds * 1000000.0f); |
AnnaBridge | 181:57724642e740 | 538 | } |
AnnaBridge | 181:57724642e740 | 539 | |
AnnaBridge | 181:57724642e740 | 540 | void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { |
AnnaBridge | 181:57724642e740 | 541 | pwmout_pulsewidth_us(obj, ms * 1000); |
AnnaBridge | 181:57724642e740 | 542 | } |
AnnaBridge | 181:57724642e740 | 543 | |
AnnaBridge | 181:57724642e740 | 544 | void pwmout_pulsewidth_us(pwmout_t* obj, int us) { |
AnnaBridge | 181:57724642e740 | 545 | float value = 0; |
AnnaBridge | 181:57724642e740 | 546 | |
AnnaBridge | 181:57724642e740 | 547 | if (obj->pwm >= MTU2_PWM_OFFSET) { |
AnnaBridge | 181:57724642e740 | 548 | #ifdef FUMC_MTU2_PWM |
AnnaBridge | 181:57724642e740 | 549 | /* PWM by MTU2 */ |
AnnaBridge | 181:57724642e740 | 550 | if (mtu2_period_ch[obj->ch] != 0) { |
AnnaBridge | 181:57724642e740 | 551 | value = (float)us / (float)mtu2_period_ch[obj->ch]; |
AnnaBridge | 181:57724642e740 | 552 | } |
AnnaBridge | 181:57724642e740 | 553 | #endif |
AnnaBridge | 181:57724642e740 | 554 | } else { |
AnnaBridge | 181:57724642e740 | 555 | #ifdef FUNC_MOTOR_CTL_PWM |
AnnaBridge | 181:57724642e740 | 556 | /* PWM */ |
AnnaBridge | 181:57724642e740 | 557 | if (obj->ch == 2) { |
AnnaBridge | 181:57724642e740 | 558 | if (period_ch2 != 0) { |
AnnaBridge | 181:57724642e740 | 559 | value = (float)us / (float)period_ch2; |
AnnaBridge | 181:57724642e740 | 560 | } |
AnnaBridge | 181:57724642e740 | 561 | } else { |
AnnaBridge | 181:57724642e740 | 562 | if (period_ch1 != 0) { |
AnnaBridge | 181:57724642e740 | 563 | value = (float)us / (float)period_ch1; |
AnnaBridge | 181:57724642e740 | 564 | } |
AnnaBridge | 181:57724642e740 | 565 | } |
AnnaBridge | 181:57724642e740 | 566 | #endif |
AnnaBridge | 181:57724642e740 | 567 | } |
AnnaBridge | 181:57724642e740 | 568 | pwmout_write(obj, value); |
AnnaBridge | 181:57724642e740 | 569 | } |