mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
181:57724642e740 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 181:57724642e740 1 /* mbed Microcontroller Library
AnnaBridge 181:57724642e740 2 * Copyright (c) 2006-2013 ARM Limited
AnnaBridge 181:57724642e740 3 *
AnnaBridge 181:57724642e740 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 181:57724642e740 5 * you may not use this file except in compliance with the License.
AnnaBridge 181:57724642e740 6 * You may obtain a copy of the License at
AnnaBridge 181:57724642e740 7 *
AnnaBridge 181:57724642e740 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 181:57724642e740 9 *
AnnaBridge 181:57724642e740 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 181:57724642e740 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 181:57724642e740 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 181:57724642e740 13 * See the License for the specific language governing permissions and
AnnaBridge 181:57724642e740 14 * limitations under the License.
AnnaBridge 181:57724642e740 15 */
AnnaBridge 181:57724642e740 16 #include <string.h>
AnnaBridge 181:57724642e740 17 #include "mbed_assert.h"
AnnaBridge 181:57724642e740 18 #include "can_api.h"
AnnaBridge 181:57724642e740 19 #include "RZ_A1_Init.h"
AnnaBridge 181:57724642e740 20 #include "cmsis.h"
AnnaBridge 181:57724642e740 21 #include "PeripheralPins.h"
AnnaBridge 181:57724642e740 22 #include "iodefine.h"
AnnaBridge 181:57724642e740 23 #include "r_typedefs.h"
AnnaBridge 181:57724642e740 24 #include "mbed_drv_cfg.h"
AnnaBridge 181:57724642e740 25
AnnaBridge 181:57724642e740 26 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 27 #define CAN_NUM 5
AnnaBridge 181:57724642e740 28 #else
AnnaBridge 181:57724642e740 29 #define CAN_NUM 2
AnnaBridge 181:57724642e740 30 #endif
AnnaBridge 181:57724642e740 31 #define CAN_SND_RCV 2
AnnaBridge 181:57724642e740 32 #define IRQ_NUM 8
AnnaBridge 181:57724642e740 33
AnnaBridge 181:57724642e740 34 static void can_rec_irq(uint32_t ch);
AnnaBridge 181:57724642e740 35 static void can_trx_irq(uint32_t ch);
AnnaBridge 181:57724642e740 36 static void can_err_irq(uint32_t ch, CanIrqType type);
AnnaBridge 181:57724642e740 37 static void can0_rec_irq(void);
AnnaBridge 181:57724642e740 38 static void can0_trx_irq(void);
AnnaBridge 181:57724642e740 39 static void can0_err_warning_irq(void);
AnnaBridge 181:57724642e740 40 static void can0_overrun_irq(void);
AnnaBridge 181:57724642e740 41 static void can0_passive_irq(void);
AnnaBridge 181:57724642e740 42 static void can0_arb_lost_irq(void);
AnnaBridge 181:57724642e740 43 static void can0_bus_err_irq(void);
AnnaBridge 181:57724642e740 44 static void can1_rec_irq(void);
AnnaBridge 181:57724642e740 45 static void can1_trx_irq(void);
AnnaBridge 181:57724642e740 46 static void can1_err_warning_irq(void);
AnnaBridge 181:57724642e740 47 static void can1_overrun_irq(void);
AnnaBridge 181:57724642e740 48 static void can1_passive_irq(void);
AnnaBridge 181:57724642e740 49 static void can1_arb_lost_irq(void);
AnnaBridge 181:57724642e740 50 static void can1_bus_err_irq(void);
AnnaBridge 181:57724642e740 51 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 52 static void can2_rec_irq(void);
AnnaBridge 181:57724642e740 53 static void can2_trx_irq(void);
AnnaBridge 181:57724642e740 54 static void can2_err_warning_irq(void);
AnnaBridge 181:57724642e740 55 static void can2_overrun_irq(void);
AnnaBridge 181:57724642e740 56 static void can2_passive_irq(void);
AnnaBridge 181:57724642e740 57 static void can2_arb_lost_irq(void);
AnnaBridge 181:57724642e740 58 static void can2_bus_err_irq(void);
AnnaBridge 181:57724642e740 59 static void can3_rec_irq(void);
AnnaBridge 181:57724642e740 60 static void can3_trx_irq(void);
AnnaBridge 181:57724642e740 61 static void can3_err_warning_irq(void);
AnnaBridge 181:57724642e740 62 static void can3_overrun_irq(void);
AnnaBridge 181:57724642e740 63 static void can3_passive_irq(void);
AnnaBridge 181:57724642e740 64 static void can3_arb_lost_irq(void);
AnnaBridge 181:57724642e740 65 static void can3_bus_err_irq(void);
AnnaBridge 181:57724642e740 66 static void can4_rec_irq(void);
AnnaBridge 181:57724642e740 67 static void can4_trx_irq(void);
AnnaBridge 181:57724642e740 68 static void can4_err_warning_irq(void);
AnnaBridge 181:57724642e740 69 static void can4_overrun_irq(void);
AnnaBridge 181:57724642e740 70 static void can4_passive_irq(void);
AnnaBridge 181:57724642e740 71 static void can4_arb_lost_irq(void);
AnnaBridge 181:57724642e740 72 static void can4_bus_err_irq(void);
AnnaBridge 181:57724642e740 73 #endif
AnnaBridge 181:57724642e740 74
AnnaBridge 181:57724642e740 75 static void can_reset_reg(can_t *obj);
AnnaBridge 181:57724642e740 76 static void can_reset_recv_rule(can_t *obj);
AnnaBridge 181:57724642e740 77 static void can_reset_buffer(can_t *obj);
AnnaBridge 181:57724642e740 78 static void can_reconfigure_channel(void);
AnnaBridge 181:57724642e740 79 static void can_set_frequency(can_t *obj, int f);
AnnaBridge 181:57724642e740 80 static void can_set_global_mode(int mode);
AnnaBridge 181:57724642e740 81 static void can_set_channel_mode(uint32_t ch, int mode);
AnnaBridge 181:57724642e740 82
AnnaBridge 181:57724642e740 83 typedef enum {
AnnaBridge 181:57724642e740 84 CAN_SEND = 0,
AnnaBridge 181:57724642e740 85 CAN_RECV
AnnaBridge 181:57724642e740 86 } CANfunc;
AnnaBridge 181:57724642e740 87
AnnaBridge 181:57724642e740 88 typedef enum {
AnnaBridge 181:57724642e740 89 GL_OPE = 0,
AnnaBridge 181:57724642e740 90 GL_RESET,
AnnaBridge 181:57724642e740 91 GL_TEST
AnnaBridge 181:57724642e740 92 } Globalmode;
AnnaBridge 181:57724642e740 93
AnnaBridge 181:57724642e740 94 typedef enum {
AnnaBridge 181:57724642e740 95 CH_COMM = 0,
AnnaBridge 181:57724642e740 96 CH_RESET,
AnnaBridge 181:57724642e740 97 CH_HOLD
AnnaBridge 181:57724642e740 98 } Channelmode;
AnnaBridge 181:57724642e740 99
AnnaBridge 181:57724642e740 100 typedef struct {
AnnaBridge 181:57724642e740 101 IRQn_Type int_num; /* Interrupt number */
AnnaBridge 181:57724642e740 102 IRQHandler handler; /* Interrupt handler */
AnnaBridge 181:57724642e740 103 } can_info_int_t;
AnnaBridge 181:57724642e740 104
AnnaBridge 181:57724642e740 105 static can_irq_handler irq_handler;
AnnaBridge 181:57724642e740 106 static uint32_t can_irq_id[CAN_NUM];
AnnaBridge 181:57724642e740 107 static int can_initialized[CAN_NUM] = {0};
AnnaBridge 181:57724642e740 108
AnnaBridge 181:57724642e740 109
AnnaBridge 181:57724642e740 110 static __IO uint32_t *CTR_MATCH[] = {
AnnaBridge 181:57724642e740 111 &RSCAN0C0CTR,
AnnaBridge 181:57724642e740 112 &RSCAN0C1CTR,
AnnaBridge 181:57724642e740 113 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 114 &RSCAN0C2CTR,
AnnaBridge 181:57724642e740 115 &RSCAN0C3CTR,
AnnaBridge 181:57724642e740 116 &RSCAN0C4CTR,
AnnaBridge 181:57724642e740 117 #endif
AnnaBridge 181:57724642e740 118 };
AnnaBridge 181:57724642e740 119
AnnaBridge 181:57724642e740 120 static __IO uint32_t *CFG_MATCH[] = {
AnnaBridge 181:57724642e740 121 &RSCAN0C0CFG,
AnnaBridge 181:57724642e740 122 &RSCAN0C1CFG,
AnnaBridge 181:57724642e740 123 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 124 &RSCAN0C2CFG,
AnnaBridge 181:57724642e740 125 &RSCAN0C3CFG,
AnnaBridge 181:57724642e740 126 &RSCAN0C4CFG,
AnnaBridge 181:57724642e740 127 #endif
AnnaBridge 181:57724642e740 128 };
AnnaBridge 181:57724642e740 129
AnnaBridge 181:57724642e740 130 static __IO uint32_t *RFCC_MATCH[] = {
AnnaBridge 181:57724642e740 131 &RSCAN0RFCC0,
AnnaBridge 181:57724642e740 132 &RSCAN0RFCC1,
AnnaBridge 181:57724642e740 133 &RSCAN0RFCC2,
AnnaBridge 181:57724642e740 134 &RSCAN0RFCC3,
AnnaBridge 181:57724642e740 135 &RSCAN0RFCC4,
AnnaBridge 181:57724642e740 136 &RSCAN0RFCC5,
AnnaBridge 181:57724642e740 137 &RSCAN0RFCC6,
AnnaBridge 181:57724642e740 138 &RSCAN0RFCC7
AnnaBridge 181:57724642e740 139 };
AnnaBridge 181:57724642e740 140
AnnaBridge 181:57724642e740 141 static __IO uint32_t *TXQCC_MATCH[] = {
AnnaBridge 181:57724642e740 142 &RSCAN0TXQCC0,
AnnaBridge 181:57724642e740 143 &RSCAN0TXQCC1,
AnnaBridge 181:57724642e740 144 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 145 &RSCAN0TXQCC2,
AnnaBridge 181:57724642e740 146 &RSCAN0TXQCC3,
AnnaBridge 181:57724642e740 147 &RSCAN0TXQCC4,
AnnaBridge 181:57724642e740 148 #endif
AnnaBridge 181:57724642e740 149 };
AnnaBridge 181:57724642e740 150
AnnaBridge 181:57724642e740 151 static __IO uint32_t *THLCC_MATCH[] = {
AnnaBridge 181:57724642e740 152 &RSCAN0THLCC0,
AnnaBridge 181:57724642e740 153 &RSCAN0THLCC1,
AnnaBridge 181:57724642e740 154 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 155 &RSCAN0THLCC2,
AnnaBridge 181:57724642e740 156 &RSCAN0THLCC3,
AnnaBridge 181:57724642e740 157 &RSCAN0THLCC4,
AnnaBridge 181:57724642e740 158 #endif
AnnaBridge 181:57724642e740 159 };
AnnaBridge 181:57724642e740 160
AnnaBridge 181:57724642e740 161 static __IO uint32_t *STS_MATCH[] = {
AnnaBridge 181:57724642e740 162 &RSCAN0C0STS,
AnnaBridge 181:57724642e740 163 &RSCAN0C1STS,
AnnaBridge 181:57724642e740 164 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 165 &RSCAN0C2STS,
AnnaBridge 181:57724642e740 166 &RSCAN0C3STS,
AnnaBridge 181:57724642e740 167 &RSCAN0C4STS,
AnnaBridge 181:57724642e740 168 #endif
AnnaBridge 181:57724642e740 169 };
AnnaBridge 181:57724642e740 170
AnnaBridge 181:57724642e740 171 static __IO uint32_t *ERFL_MATCH[] = {
AnnaBridge 181:57724642e740 172 &RSCAN0C0ERFL,
AnnaBridge 181:57724642e740 173 &RSCAN0C1ERFL,
AnnaBridge 181:57724642e740 174 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 175 &RSCAN0C2ERFL,
AnnaBridge 181:57724642e740 176 &RSCAN0C3ERFL,
AnnaBridge 181:57724642e740 177 &RSCAN0C4ERFL,
AnnaBridge 181:57724642e740 178 #endif
AnnaBridge 181:57724642e740 179 };
AnnaBridge 181:57724642e740 180
AnnaBridge 181:57724642e740 181 static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = {
AnnaBridge 181:57724642e740 182 { &RSCAN0CFCC0 , &RSCAN0CFCC1 },
AnnaBridge 181:57724642e740 183 { &RSCAN0CFCC3 , &RSCAN0CFCC4 },
AnnaBridge 181:57724642e740 184 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 185 { &RSCAN0CFCC6 , &RSCAN0CFCC7 },
AnnaBridge 181:57724642e740 186 { &RSCAN0CFCC9 , &RSCAN0CFCC10 },
AnnaBridge 181:57724642e740 187 { &RSCAN0CFCC12, &RSCAN0CFCC13 },
AnnaBridge 181:57724642e740 188 #endif
AnnaBridge 181:57724642e740 189 };
AnnaBridge 181:57724642e740 190
AnnaBridge 181:57724642e740 191 static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = {
AnnaBridge 181:57724642e740 192 { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 },
AnnaBridge 181:57724642e740 193 { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 },
AnnaBridge 181:57724642e740 194 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 195 { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 },
AnnaBridge 181:57724642e740 196 { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 },
AnnaBridge 181:57724642e740 197 { &RSCAN0CFSTS12, &RSCAN0CFSTS13 },
AnnaBridge 181:57724642e740 198 #endif
AnnaBridge 181:57724642e740 199 };
AnnaBridge 181:57724642e740 200
AnnaBridge 181:57724642e740 201 static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = {
AnnaBridge 181:57724642e740 202 { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 },
AnnaBridge 181:57724642e740 203 { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 },
AnnaBridge 181:57724642e740 204 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 205 { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 },
AnnaBridge 181:57724642e740 206 { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 },
AnnaBridge 181:57724642e740 207 { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 },
AnnaBridge 181:57724642e740 208 #endif
AnnaBridge 181:57724642e740 209 };
AnnaBridge 181:57724642e740 210
AnnaBridge 181:57724642e740 211 static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = {
AnnaBridge 181:57724642e740 212 { &RSCAN0CFID0 , &RSCAN0CFID1 },
AnnaBridge 181:57724642e740 213 { &RSCAN0CFID3 , &RSCAN0CFID4 },
AnnaBridge 181:57724642e740 214 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 215 { &RSCAN0CFID6 , &RSCAN0CFID7 },
AnnaBridge 181:57724642e740 216 { &RSCAN0CFID9 , &RSCAN0CFID10 },
AnnaBridge 181:57724642e740 217 { &RSCAN0CFID12, &RSCAN0CFID13 },
AnnaBridge 181:57724642e740 218 #endif
AnnaBridge 181:57724642e740 219 };
AnnaBridge 181:57724642e740 220
AnnaBridge 181:57724642e740 221 static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = {
AnnaBridge 181:57724642e740 222 { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 },
AnnaBridge 181:57724642e740 223 { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 },
AnnaBridge 181:57724642e740 224 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 225 { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 },
AnnaBridge 181:57724642e740 226 { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 },
AnnaBridge 181:57724642e740 227 { &RSCAN0CFPTR12, &RSCAN0CFPTR13 }
AnnaBridge 181:57724642e740 228 #endif
AnnaBridge 181:57724642e740 229 };
AnnaBridge 181:57724642e740 230
AnnaBridge 181:57724642e740 231 static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = {
AnnaBridge 181:57724642e740 232 { &RSCAN0CFDF00 , &RSCAN0CFDF01 },
AnnaBridge 181:57724642e740 233 { &RSCAN0CFDF03 , &RSCAN0CFDF04 },
AnnaBridge 181:57724642e740 234 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 235 { &RSCAN0CFDF06 , &RSCAN0CFDF07 },
AnnaBridge 181:57724642e740 236 { &RSCAN0CFDF09 , &RSCAN0CFDF010 },
AnnaBridge 181:57724642e740 237 { &RSCAN0CFDF012, &RSCAN0CFDF013 },
AnnaBridge 181:57724642e740 238 #endif
AnnaBridge 181:57724642e740 239 };
AnnaBridge 181:57724642e740 240
AnnaBridge 181:57724642e740 241 static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = {
AnnaBridge 181:57724642e740 242 { &RSCAN0CFDF10 , &RSCAN0CFDF11 },
AnnaBridge 181:57724642e740 243 { &RSCAN0CFDF13 , &RSCAN0CFDF14 },
AnnaBridge 181:57724642e740 244 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 245 { &RSCAN0CFDF16 , &RSCAN0CFDF17 },
AnnaBridge 181:57724642e740 246 { &RSCAN0CFDF19 , &RSCAN0CFDF110 },
AnnaBridge 181:57724642e740 247 { &RSCAN0CFDF112, &RSCAN0CFDF113 },
AnnaBridge 181:57724642e740 248 #endif
AnnaBridge 181:57724642e740 249 };
AnnaBridge 181:57724642e740 250
AnnaBridge 181:57724642e740 251 static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] =
AnnaBridge 181:57724642e740 252 {
AnnaBridge 181:57724642e740 253 { /* ch0 */
AnnaBridge 181:57724642e740 254 { INTRCAN0REC_IRQn, can0_rec_irq }, /* RxIrq */
AnnaBridge 181:57724642e740 255 { INTRCAN0TRX_IRQn, can0_trx_irq }, /* TxIrq */
AnnaBridge 181:57724642e740 256 { INTRCAN0ERR_IRQn, can0_err_warning_irq }, /* EwIrq */
AnnaBridge 181:57724642e740 257 { INTRCAN0ERR_IRQn, can0_overrun_irq }, /* DoIrq */
AnnaBridge 181:57724642e740 258 { INTRCAN0ERR_IRQn, NULL }, /* WuIrq(not supported) */
AnnaBridge 181:57724642e740 259 { INTRCAN0ERR_IRQn, can0_passive_irq }, /* EpIrq */
AnnaBridge 181:57724642e740 260 { INTRCAN0ERR_IRQn, can0_arb_lost_irq }, /* AlIrq */
AnnaBridge 181:57724642e740 261 { INTRCAN0ERR_IRQn, can0_bus_err_irq } /* BeIrq */
AnnaBridge 181:57724642e740 262 },
AnnaBridge 181:57724642e740 263 { /* ch1 */
AnnaBridge 181:57724642e740 264 { INTRCAN1REC_IRQn, can1_rec_irq }, /* RxIrq */
AnnaBridge 181:57724642e740 265 { INTRCAN1TRX_IRQn, can1_trx_irq }, /* TxIrq */
AnnaBridge 181:57724642e740 266 { INTRCAN1ERR_IRQn, can1_err_warning_irq }, /* EwIrq */
AnnaBridge 181:57724642e740 267 { INTRCAN1ERR_IRQn, can1_overrun_irq }, /* DoIrq */
AnnaBridge 181:57724642e740 268 { INTRCAN1ERR_IRQn, NULL }, /* WuIrq(not supported) */
AnnaBridge 181:57724642e740 269 { INTRCAN1ERR_IRQn, can1_passive_irq }, /* EpIrq */
AnnaBridge 181:57724642e740 270 { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */
AnnaBridge 181:57724642e740 271 { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */
AnnaBridge 181:57724642e740 272 },
AnnaBridge 181:57724642e740 273 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 274 { /* ch2 */
AnnaBridge 181:57724642e740 275 { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */
AnnaBridge 181:57724642e740 276 { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */
AnnaBridge 181:57724642e740 277 { INTRCAN2ERR_IRQn, can2_err_warning_irq }, /* EwIrq */
AnnaBridge 181:57724642e740 278 { INTRCAN2ERR_IRQn, can2_overrun_irq }, /* DoIrq */
AnnaBridge 181:57724642e740 279 { INTRCAN2ERR_IRQn, NULL }, /* WuIrq(not supported) */
AnnaBridge 181:57724642e740 280 { INTRCAN2ERR_IRQn, can2_passive_irq }, /* EpIrq */
AnnaBridge 181:57724642e740 281 { INTRCAN2ERR_IRQn, can2_arb_lost_irq }, /* AlIrq */
AnnaBridge 181:57724642e740 282 { INTRCAN2ERR_IRQn, can2_bus_err_irq } /* BeIrq */
AnnaBridge 181:57724642e740 283 },
AnnaBridge 181:57724642e740 284 { /* ch3 */
AnnaBridge 181:57724642e740 285 { INTRCAN3REC_IRQn, can3_rec_irq }, /* RxIrq */
AnnaBridge 181:57724642e740 286 { INTRCAN3TRX_IRQn, can3_trx_irq }, /* TxIrq */
AnnaBridge 181:57724642e740 287 { INTRCAN3ERR_IRQn, can3_err_warning_irq }, /* EwIrq */
AnnaBridge 181:57724642e740 288 { INTRCAN3ERR_IRQn, can3_overrun_irq }, /* DoIrq */
AnnaBridge 181:57724642e740 289 { INTRCAN3ERR_IRQn, NULL }, /* WuIrq(not supported) */
AnnaBridge 181:57724642e740 290 { INTRCAN3ERR_IRQn, can3_passive_irq }, /* EpIrq */
AnnaBridge 181:57724642e740 291 { INTRCAN3ERR_IRQn, can3_arb_lost_irq }, /* AlIrq */
AnnaBridge 181:57724642e740 292 { INTRCAN3ERR_IRQn, can3_bus_err_irq } /* BeIrq */
AnnaBridge 181:57724642e740 293 },
AnnaBridge 181:57724642e740 294 { /* ch4 */
AnnaBridge 181:57724642e740 295 { INTRCAN4REC_IRQn, can4_rec_irq }, /* RxIrq */
AnnaBridge 181:57724642e740 296 { INTRCAN4TRX_IRQn, can4_trx_irq }, /* TxIrq */
AnnaBridge 181:57724642e740 297 { INTRCAN4ERR_IRQn, can4_err_warning_irq }, /* EwIrq */
AnnaBridge 181:57724642e740 298 { INTRCAN4ERR_IRQn, can4_overrun_irq }, /* DoIrq */
AnnaBridge 181:57724642e740 299 { INTRCAN4ERR_IRQn, NULL }, /* WuIrq(not supported) */
AnnaBridge 181:57724642e740 300 { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */
AnnaBridge 181:57724642e740 301 { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */
AnnaBridge 181:57724642e740 302 { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */
AnnaBridge 181:57724642e740 303 },
AnnaBridge 181:57724642e740 304 #endif
AnnaBridge 181:57724642e740 305 };
AnnaBridge 181:57724642e740 306
AnnaBridge 181:57724642e740 307 static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0;
AnnaBridge 181:57724642e740 308 static __IO uint32_t *dmy_gaflm = &RSCAN0GAFLM0;
AnnaBridge 181:57724642e740 309 static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00;
AnnaBridge 181:57724642e740 310 static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10;
AnnaBridge 181:57724642e740 311
AnnaBridge 181:57724642e740 312 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
AnnaBridge 181:57724642e740 313 irq_handler = handler;
AnnaBridge 181:57724642e740 314 can_irq_id[obj->ch] = id;
AnnaBridge 181:57724642e740 315 }
AnnaBridge 181:57724642e740 316
AnnaBridge 181:57724642e740 317 void can_irq_free(can_t *obj) {
AnnaBridge 181:57724642e740 318 can_irq_id[obj->ch] = 0;
AnnaBridge 181:57724642e740 319 }
AnnaBridge 181:57724642e740 320
AnnaBridge 181:57724642e740 321 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
AnnaBridge 181:57724642e740 322 __IO uint32_t *dmy_ctr;
AnnaBridge 181:57724642e740 323
AnnaBridge 181:57724642e740 324 /* Wake-up Irq is not supported */
AnnaBridge 181:57724642e740 325 if (type != IRQ_WAKEUP) {
AnnaBridge 181:57724642e740 326 if (enable) {
AnnaBridge 181:57724642e740 327 dmy_ctr = CTR_MATCH[obj->ch];
AnnaBridge 181:57724642e740 328 if (type == IRQ_ERROR) {
AnnaBridge 181:57724642e740 329 /* EWIE interrupts is enable */
AnnaBridge 181:57724642e740 330 *dmy_ctr |= 0x00000200;
AnnaBridge 181:57724642e740 331 } else if (type == IRQ_OVERRUN) {
AnnaBridge 181:57724642e740 332 /* OLIE interrupts is enable */
AnnaBridge 181:57724642e740 333 *dmy_ctr |= 0x00002000;
AnnaBridge 181:57724642e740 334 } else if (type == IRQ_PASSIVE) {
AnnaBridge 181:57724642e740 335 /* EPIE interrupts is enable */
AnnaBridge 181:57724642e740 336 *dmy_ctr |= 0x00000400;
AnnaBridge 181:57724642e740 337 } else if (type == IRQ_ARB) {
AnnaBridge 181:57724642e740 338 /* ALIE interrupts is enable */
AnnaBridge 181:57724642e740 339 *dmy_ctr |= 0x00008000;
AnnaBridge 181:57724642e740 340 } else if (type == IRQ_BUS) {
AnnaBridge 181:57724642e740 341 /* BEIE interrupts is enable */
AnnaBridge 181:57724642e740 342 *dmy_ctr |= 0x00000100;
AnnaBridge 181:57724642e740 343 }
AnnaBridge 181:57724642e740 344 InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
AnnaBridge 181:57724642e740 345 GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
AnnaBridge 181:57724642e740 346 GIC_SetConfiguration(can_int_info[obj->ch][type].int_num, 1);
AnnaBridge 181:57724642e740 347 GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
AnnaBridge 181:57724642e740 348 } else {
AnnaBridge 181:57724642e740 349 GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);
AnnaBridge 181:57724642e740 350 }
AnnaBridge 181:57724642e740 351 }
AnnaBridge 181:57724642e740 352 }
AnnaBridge 181:57724642e740 353
AnnaBridge 181:57724642e740 354 static void can_rec_irq(uint32_t ch) {
AnnaBridge 181:57724642e740 355 __IO uint32_t *dmy_cfsts;
AnnaBridge 181:57724642e740 356
AnnaBridge 181:57724642e740 357 dmy_cfsts = CFSTS_TBL[ch][CAN_RECV];
AnnaBridge 181:57724642e740 358 *dmy_cfsts &= 0xFFFFFFF7; // Clear CFRXIF
AnnaBridge 181:57724642e740 359
AnnaBridge 181:57724642e740 360 irq_handler(can_irq_id[ch], IRQ_RX);
AnnaBridge 181:57724642e740 361 }
AnnaBridge 181:57724642e740 362
AnnaBridge 181:57724642e740 363 static void can_trx_irq(uint32_t ch) {
AnnaBridge 181:57724642e740 364 __IO uint32_t *dmy_cfsts;
AnnaBridge 181:57724642e740 365
AnnaBridge 181:57724642e740 366 dmy_cfsts = CFSTS_TBL[ch][CAN_SEND];
AnnaBridge 181:57724642e740 367 *dmy_cfsts &= 0xFFFFFFEF; // Clear CFTXIF
AnnaBridge 181:57724642e740 368
AnnaBridge 181:57724642e740 369 irq_handler(can_irq_id[ch], IRQ_TX);
AnnaBridge 181:57724642e740 370 }
AnnaBridge 181:57724642e740 371
AnnaBridge 181:57724642e740 372 static void can_err_irq(uint32_t ch, CanIrqType type) {
AnnaBridge 181:57724642e740 373 __IO uint32_t *dmy_erfl;
AnnaBridge 181:57724642e740 374 int val = 1;
AnnaBridge 181:57724642e740 375
AnnaBridge 181:57724642e740 376 dmy_erfl = ERFL_MATCH[ch];
AnnaBridge 181:57724642e740 377 switch (type) {
AnnaBridge 181:57724642e740 378 case IRQ_ERROR:
AnnaBridge 181:57724642e740 379 *dmy_erfl &= 0xFFFFFFFD; // Clear EWF
AnnaBridge 181:57724642e740 380 break;
AnnaBridge 181:57724642e740 381 case IRQ_OVERRUN:
AnnaBridge 181:57724642e740 382 *dmy_erfl &= 0xFFFFFFDF; // Clear OVLF
AnnaBridge 181:57724642e740 383 break;
AnnaBridge 181:57724642e740 384 case IRQ_PASSIVE:
AnnaBridge 181:57724642e740 385 *dmy_erfl &= 0xFFFFFFFB; // Clear EPF
AnnaBridge 181:57724642e740 386 break;
AnnaBridge 181:57724642e740 387 case IRQ_ARB:
AnnaBridge 181:57724642e740 388 *dmy_erfl &= 0xFFFFFF7F; // Clear ALF
AnnaBridge 181:57724642e740 389 break;
AnnaBridge 181:57724642e740 390 case IRQ_BUS:
AnnaBridge 181:57724642e740 391 *dmy_erfl &= 0xFFFF00FF; // Clear ADERRAB0ERRAB1ERRACERRAAERRAFERRASERR
AnnaBridge 181:57724642e740 392 *dmy_erfl &= 0xFFFFFFFE; // Clear BEF
AnnaBridge 181:57724642e740 393 break;
AnnaBridge 181:57724642e740 394 case IRQ_WAKEUP:
AnnaBridge 181:57724642e740 395 /* not supported */
AnnaBridge 181:57724642e740 396 /* fall through */
AnnaBridge 181:57724642e740 397 default:
AnnaBridge 181:57724642e740 398 val = 0;
AnnaBridge 181:57724642e740 399 break;
AnnaBridge 181:57724642e740 400 }
AnnaBridge 181:57724642e740 401 if (val == 1) {
AnnaBridge 181:57724642e740 402 irq_handler(can_irq_id[ch], type);
AnnaBridge 181:57724642e740 403 }
AnnaBridge 181:57724642e740 404 }
AnnaBridge 181:57724642e740 405
AnnaBridge 181:57724642e740 406 static void can0_rec_irq(void) {
AnnaBridge 181:57724642e740 407 can_rec_irq(CAN_0);
AnnaBridge 181:57724642e740 408 }
AnnaBridge 181:57724642e740 409
AnnaBridge 181:57724642e740 410 static void can0_trx_irq(void) {
AnnaBridge 181:57724642e740 411 can_trx_irq(CAN_0);
AnnaBridge 181:57724642e740 412 }
AnnaBridge 181:57724642e740 413
AnnaBridge 181:57724642e740 414 static void can0_err_warning_irq(void) {
AnnaBridge 181:57724642e740 415 can_err_irq(CAN_0, IRQ_ERROR);
AnnaBridge 181:57724642e740 416 }
AnnaBridge 181:57724642e740 417
AnnaBridge 181:57724642e740 418 static void can0_overrun_irq(void) {
AnnaBridge 181:57724642e740 419 can_err_irq(CAN_0, IRQ_OVERRUN);
AnnaBridge 181:57724642e740 420 }
AnnaBridge 181:57724642e740 421
AnnaBridge 181:57724642e740 422 static void can0_passive_irq(void) {
AnnaBridge 181:57724642e740 423 can_err_irq(CAN_0, IRQ_PASSIVE);
AnnaBridge 181:57724642e740 424 }
AnnaBridge 181:57724642e740 425
AnnaBridge 181:57724642e740 426 static void can0_arb_lost_irq(void) {
AnnaBridge 181:57724642e740 427 can_err_irq(CAN_0, IRQ_ARB);
AnnaBridge 181:57724642e740 428 }
AnnaBridge 181:57724642e740 429
AnnaBridge 181:57724642e740 430 static void can0_bus_err_irq(void) {
AnnaBridge 181:57724642e740 431 can_err_irq(CAN_0, IRQ_BUS);
AnnaBridge 181:57724642e740 432 }
AnnaBridge 181:57724642e740 433
AnnaBridge 181:57724642e740 434 static void can1_rec_irq(void) {
AnnaBridge 181:57724642e740 435 can_rec_irq(CAN_1);
AnnaBridge 181:57724642e740 436 }
AnnaBridge 181:57724642e740 437
AnnaBridge 181:57724642e740 438 static void can1_trx_irq(void) {
AnnaBridge 181:57724642e740 439 can_trx_irq(CAN_1);
AnnaBridge 181:57724642e740 440 }
AnnaBridge 181:57724642e740 441
AnnaBridge 181:57724642e740 442 static void can1_err_warning_irq(void) {
AnnaBridge 181:57724642e740 443 can_err_irq(CAN_1, IRQ_ERROR);
AnnaBridge 181:57724642e740 444 }
AnnaBridge 181:57724642e740 445
AnnaBridge 181:57724642e740 446 static void can1_overrun_irq(void) {
AnnaBridge 181:57724642e740 447 can_err_irq(CAN_1, IRQ_OVERRUN);
AnnaBridge 181:57724642e740 448 }
AnnaBridge 181:57724642e740 449
AnnaBridge 181:57724642e740 450 static void can1_passive_irq(void) {
AnnaBridge 181:57724642e740 451 can_err_irq(CAN_1, IRQ_PASSIVE);
AnnaBridge 181:57724642e740 452 }
AnnaBridge 181:57724642e740 453
AnnaBridge 181:57724642e740 454 static void can1_arb_lost_irq(void) {
AnnaBridge 181:57724642e740 455 can_err_irq(CAN_1, IRQ_ARB);
AnnaBridge 181:57724642e740 456 }
AnnaBridge 181:57724642e740 457
AnnaBridge 181:57724642e740 458 static void can1_bus_err_irq(void) {
AnnaBridge 181:57724642e740 459 can_err_irq(CAN_1, IRQ_BUS);
AnnaBridge 181:57724642e740 460 }
AnnaBridge 181:57724642e740 461
AnnaBridge 181:57724642e740 462 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 463 static void can2_rec_irq(void) {
AnnaBridge 181:57724642e740 464 can_rec_irq(CAN_2);
AnnaBridge 181:57724642e740 465 }
AnnaBridge 181:57724642e740 466
AnnaBridge 181:57724642e740 467 static void can2_trx_irq(void) {
AnnaBridge 181:57724642e740 468 can_trx_irq(CAN_2);
AnnaBridge 181:57724642e740 469 }
AnnaBridge 181:57724642e740 470
AnnaBridge 181:57724642e740 471 static void can2_err_warning_irq(void) {
AnnaBridge 181:57724642e740 472 can_err_irq(CAN_2, IRQ_ERROR);
AnnaBridge 181:57724642e740 473 }
AnnaBridge 181:57724642e740 474
AnnaBridge 181:57724642e740 475 static void can2_overrun_irq(void) {
AnnaBridge 181:57724642e740 476 can_err_irq(CAN_2, IRQ_OVERRUN);
AnnaBridge 181:57724642e740 477 }
AnnaBridge 181:57724642e740 478
AnnaBridge 181:57724642e740 479 static void can2_passive_irq(void) {
AnnaBridge 181:57724642e740 480 can_err_irq(CAN_2, IRQ_PASSIVE);
AnnaBridge 181:57724642e740 481 }
AnnaBridge 181:57724642e740 482
AnnaBridge 181:57724642e740 483 static void can2_arb_lost_irq(void) {
AnnaBridge 181:57724642e740 484 can_err_irq(CAN_2, IRQ_ARB);
AnnaBridge 181:57724642e740 485 }
AnnaBridge 181:57724642e740 486
AnnaBridge 181:57724642e740 487 static void can2_bus_err_irq(void) {
AnnaBridge 181:57724642e740 488 can_err_irq(CAN_2, IRQ_BUS);
AnnaBridge 181:57724642e740 489 }
AnnaBridge 181:57724642e740 490
AnnaBridge 181:57724642e740 491 static void can3_rec_irq(void) {
AnnaBridge 181:57724642e740 492 can_rec_irq(CAN_3);
AnnaBridge 181:57724642e740 493 }
AnnaBridge 181:57724642e740 494
AnnaBridge 181:57724642e740 495 static void can3_trx_irq(void) {
AnnaBridge 181:57724642e740 496 can_trx_irq(CAN_3);
AnnaBridge 181:57724642e740 497 }
AnnaBridge 181:57724642e740 498
AnnaBridge 181:57724642e740 499 static void can3_err_warning_irq(void) {
AnnaBridge 181:57724642e740 500 can_err_irq(CAN_3, IRQ_ERROR);
AnnaBridge 181:57724642e740 501 }
AnnaBridge 181:57724642e740 502
AnnaBridge 181:57724642e740 503 static void can3_overrun_irq(void) {
AnnaBridge 181:57724642e740 504 can_err_irq(CAN_3, IRQ_OVERRUN);
AnnaBridge 181:57724642e740 505 }
AnnaBridge 181:57724642e740 506
AnnaBridge 181:57724642e740 507 static void can3_passive_irq(void) {
AnnaBridge 181:57724642e740 508 can_err_irq(CAN_3, IRQ_PASSIVE);
AnnaBridge 181:57724642e740 509 }
AnnaBridge 181:57724642e740 510
AnnaBridge 181:57724642e740 511 static void can3_arb_lost_irq(void) {
AnnaBridge 181:57724642e740 512 can_err_irq(CAN_3, IRQ_ARB);
AnnaBridge 181:57724642e740 513 }
AnnaBridge 181:57724642e740 514
AnnaBridge 181:57724642e740 515 static void can3_bus_err_irq(void) {
AnnaBridge 181:57724642e740 516 can_err_irq(CAN_3, IRQ_BUS);
AnnaBridge 181:57724642e740 517 }
AnnaBridge 181:57724642e740 518
AnnaBridge 181:57724642e740 519 static void can4_rec_irq(void) {
AnnaBridge 181:57724642e740 520 can_rec_irq(CAN_4);
AnnaBridge 181:57724642e740 521 }
AnnaBridge 181:57724642e740 522
AnnaBridge 181:57724642e740 523 static void can4_trx_irq(void) {
AnnaBridge 181:57724642e740 524 can_trx_irq(CAN_4);
AnnaBridge 181:57724642e740 525 }
AnnaBridge 181:57724642e740 526
AnnaBridge 181:57724642e740 527 static void can4_err_warning_irq(void) {
AnnaBridge 181:57724642e740 528 can_err_irq(CAN_4, IRQ_ERROR);
AnnaBridge 181:57724642e740 529 }
AnnaBridge 181:57724642e740 530
AnnaBridge 181:57724642e740 531 static void can4_overrun_irq(void) {
AnnaBridge 181:57724642e740 532 can_err_irq(CAN_4, IRQ_OVERRUN);
AnnaBridge 181:57724642e740 533 }
AnnaBridge 181:57724642e740 534
AnnaBridge 181:57724642e740 535 static void can4_passive_irq(void) {
AnnaBridge 181:57724642e740 536 can_err_irq(CAN_4, IRQ_PASSIVE);
AnnaBridge 181:57724642e740 537 }
AnnaBridge 181:57724642e740 538
AnnaBridge 181:57724642e740 539 static void can4_arb_lost_irq(void) {
AnnaBridge 181:57724642e740 540 can_err_irq(CAN_4, IRQ_ARB);
AnnaBridge 181:57724642e740 541 }
AnnaBridge 181:57724642e740 542
AnnaBridge 181:57724642e740 543 static void can4_bus_err_irq(void) {
AnnaBridge 181:57724642e740 544 can_err_irq(CAN_4, IRQ_BUS);
AnnaBridge 181:57724642e740 545 }
AnnaBridge 181:57724642e740 546 #endif
AnnaBridge 181:57724642e740 547
AnnaBridge 181:57724642e740 548 void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) {
AnnaBridge 181:57724642e740 549 __IO uint32_t *dmy_ctr;
AnnaBridge 181:57724642e740 550
AnnaBridge 181:57724642e740 551 /* determine the CAN to use */
AnnaBridge 181:57724642e740 552 uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD);
AnnaBridge 181:57724642e740 553 uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD);
AnnaBridge 181:57724642e740 554 obj->ch = pinmap_merge(can_tx, can_rx);
AnnaBridge 181:57724642e740 555 MBED_ASSERT((int)obj->ch != NC);
AnnaBridge 181:57724642e740 556
AnnaBridge 181:57724642e740 557 /* enable CAN clock */
AnnaBridge 181:57724642e740 558 CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP32);
AnnaBridge 181:57724642e740 559 /* Has CAN RAM initialisation completed ? */
AnnaBridge 181:57724642e740 560 while ((RSCAN0GSTS & 0x08) == 0x08) {
AnnaBridge 181:57724642e740 561 __NOP();
AnnaBridge 181:57724642e740 562 }
AnnaBridge 181:57724642e740 563 /* clear Global Stop mode bit */
AnnaBridge 181:57724642e740 564 RSCAN0GCTR &= 0xFFFFFFFB;
AnnaBridge 181:57724642e740 565 /* clear Channel Stop mode bit */
AnnaBridge 181:57724642e740 566 dmy_ctr = CTR_MATCH[obj->ch];
AnnaBridge 181:57724642e740 567 *dmy_ctr &= 0xFFFFFFFB;
AnnaBridge 181:57724642e740 568 /* Enter global reset mode */
AnnaBridge 181:57724642e740 569 can_set_global_mode(GL_RESET);
AnnaBridge 181:57724642e740 570 /* Enter channel reset mode */
AnnaBridge 181:57724642e740 571 can_set_channel_mode(obj->ch, CH_RESET);
AnnaBridge 181:57724642e740 572 /* reset register */
AnnaBridge 181:57724642e740 573 can_reset_reg(obj);
AnnaBridge 181:57724642e740 574
AnnaBridge 181:57724642e740 575 can_initialized[obj->ch] = 1;
AnnaBridge 181:57724642e740 576 /* reconfigure channel which is already initialized */
AnnaBridge 181:57724642e740 577 can_reconfigure_channel();
AnnaBridge 181:57724642e740 578
AnnaBridge 181:57724642e740 579 /* pin out the can pins */
AnnaBridge 181:57724642e740 580 pinmap_pinout(rd, PinMap_CAN_RD);
AnnaBridge 181:57724642e740 581 pinmap_pinout(td, PinMap_CAN_TD);
AnnaBridge 181:57724642e740 582
AnnaBridge 181:57724642e740 583 /* set can frequency */
AnnaBridge 181:57724642e740 584 can_frequency(obj, hz);
AnnaBridge 181:57724642e740 585 }
AnnaBridge 181:57724642e740 586
AnnaBridge 181:57724642e740 587 void can_init(can_t *obj, PinName rd, PinName td) {
AnnaBridge 181:57724642e740 588 can_init_freq(obj, rd, td, 100000);
AnnaBridge 181:57724642e740 589 }
AnnaBridge 181:57724642e740 590
AnnaBridge 181:57724642e740 591 void can_free(can_t *obj) {
AnnaBridge 181:57724642e740 592 /* disable CAN clock */
AnnaBridge 181:57724642e740 593 CPGSTBCR3 |= CPG_STBCR3_BIT_MSTP32;
AnnaBridge 181:57724642e740 594 }
AnnaBridge 181:57724642e740 595
AnnaBridge 181:57724642e740 596 int can_frequency(can_t *obj, int f) {
AnnaBridge 181:57724642e740 597 __IO uint32_t *dmy_cfcc;
AnnaBridge 181:57724642e740 598 int retval = 0;
AnnaBridge 181:57724642e740 599
AnnaBridge 181:57724642e740 600 if (f <= 1000000) {
AnnaBridge 181:57724642e740 601 /* less than 1Mhz */
AnnaBridge 181:57724642e740 602 /* set Channel Reset mode */
AnnaBridge 181:57724642e740 603 can_set_channel_mode(obj->ch, CH_RESET);
AnnaBridge 181:57724642e740 604 can_set_frequency(obj, f);
AnnaBridge 181:57724642e740 605 /* set Channel Communication mode */
AnnaBridge 181:57724642e740 606 can_set_channel_mode(obj->ch, CH_COMM);
AnnaBridge 181:57724642e740 607 /* restore CFE bit since it is cleared */
AnnaBridge 181:57724642e740 608 /* Use send/receive FIFO buffer */
AnnaBridge 181:57724642e740 609 dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
AnnaBridge 181:57724642e740 610 *dmy_cfcc |= 0x01;
AnnaBridge 181:57724642e740 611 dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
AnnaBridge 181:57724642e740 612 *dmy_cfcc |= 0x01;
AnnaBridge 181:57724642e740 613 retval = 1;
AnnaBridge 181:57724642e740 614 }
AnnaBridge 181:57724642e740 615
AnnaBridge 181:57724642e740 616 return retval;
AnnaBridge 181:57724642e740 617 }
AnnaBridge 181:57724642e740 618
AnnaBridge 181:57724642e740 619 void can_reset(can_t *obj) {
AnnaBridge 181:57724642e740 620 /* Enter global reset mode */
AnnaBridge 181:57724642e740 621 can_set_global_mode(GL_RESET);
AnnaBridge 181:57724642e740 622 /* Enter channel reset mode */
AnnaBridge 181:57724642e740 623 can_set_channel_mode(obj->ch, CH_RESET);
AnnaBridge 181:57724642e740 624 /* reset register */
AnnaBridge 181:57724642e740 625 can_reset_reg(obj);
AnnaBridge 181:57724642e740 626 /* reconfigure channel which is already initialized */
AnnaBridge 181:57724642e740 627 can_reconfigure_channel();
AnnaBridge 181:57724642e740 628 }
AnnaBridge 181:57724642e740 629
AnnaBridge 181:57724642e740 630 int can_write(can_t *obj, CAN_Message msg, int cc) {
AnnaBridge 181:57724642e740 631 __IO uint32_t *dmy_sts;
AnnaBridge 181:57724642e740 632 __IO uint32_t *dmy_cfsts;
AnnaBridge 181:57724642e740 633 __IO uint32_t *dmy_cfid;
AnnaBridge 181:57724642e740 634 __IO uint32_t *dmy_cfptr;
AnnaBridge 181:57724642e740 635 __IO uint32_t *dmy_cfdf0;
AnnaBridge 181:57724642e740 636 __IO uint32_t *dmy_cfdf1;
AnnaBridge 181:57724642e740 637 __IO uint32_t *dmy_cfpctr;
AnnaBridge 181:57724642e740 638 int retval = 0;
AnnaBridge 181:57724642e740 639
AnnaBridge 181:57724642e740 640 /* Wait to become channel communication mode */
AnnaBridge 181:57724642e740 641 dmy_sts = STS_MATCH[obj->ch];
AnnaBridge 181:57724642e740 642 while ((*dmy_sts & 0x07) != 0) {
AnnaBridge 181:57724642e740 643 __NOP();
AnnaBridge 181:57724642e740 644 }
AnnaBridge 181:57724642e740 645
AnnaBridge 181:57724642e740 646 if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x1FFFFFFF))) {
AnnaBridge 181:57724642e740 647 /* send/receive FIFO buffer isn't full */
AnnaBridge 181:57724642e740 648 dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
AnnaBridge 181:57724642e740 649 if ((*dmy_cfsts & 0x02) != 0x02) {
AnnaBridge 181:57724642e740 650 /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
AnnaBridge 181:57724642e740 651 dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
AnnaBridge 181:57724642e740 652 *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
AnnaBridge 181:57724642e740 653 if (msg.format == CANStandard) {
AnnaBridge 181:57724642e740 654 *dmy_cfid |= (msg.id & 0x07FF);
AnnaBridge 181:57724642e740 655 } else {
AnnaBridge 181:57724642e740 656 *dmy_cfid |= (msg.id & 0x1FFFFFFF);
AnnaBridge 181:57724642e740 657 }
AnnaBridge 181:57724642e740 658 /* set length */
AnnaBridge 181:57724642e740 659 dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
AnnaBridge 181:57724642e740 660 *dmy_cfptr = msg.len << 28;
AnnaBridge 181:57724642e740 661 /* set data */
AnnaBridge 181:57724642e740 662 dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_SEND];
AnnaBridge 181:57724642e740 663 memcpy((void *)dmy_cfdf0, &msg.data[0], 4);
AnnaBridge 181:57724642e740 664 dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_SEND];
AnnaBridge 181:57724642e740 665 memcpy((void *)dmy_cfdf1, &msg.data[4], 4);
AnnaBridge 181:57724642e740 666 /* send request */
AnnaBridge 181:57724642e740 667 dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_SEND];
AnnaBridge 181:57724642e740 668 *dmy_cfpctr = 0xFF;
AnnaBridge 181:57724642e740 669 retval = 1;
AnnaBridge 181:57724642e740 670 }
AnnaBridge 181:57724642e740 671 }
AnnaBridge 181:57724642e740 672
AnnaBridge 181:57724642e740 673 return retval;
AnnaBridge 181:57724642e740 674 }
AnnaBridge 181:57724642e740 675
AnnaBridge 181:57724642e740 676 int can_read(can_t *obj, CAN_Message *msg, int handle) {
AnnaBridge 181:57724642e740 677 __IO uint32_t *dmy_sts;
AnnaBridge 181:57724642e740 678 __IO uint32_t *dmy_cfsts;
AnnaBridge 181:57724642e740 679 __IO uint32_t *dmy_cfid;
AnnaBridge 181:57724642e740 680 __IO uint32_t *dmy_cfptr;
AnnaBridge 181:57724642e740 681 __IO uint32_t *dmy_cfdf0;
AnnaBridge 181:57724642e740 682 __IO uint32_t *dmy_cfdf1;
AnnaBridge 181:57724642e740 683 __IO uint32_t *dmy_cfpctr;
AnnaBridge 181:57724642e740 684 int retval = 0;
AnnaBridge 181:57724642e740 685
AnnaBridge 181:57724642e740 686 /* Wait to become channel communication mode */
AnnaBridge 181:57724642e740 687 dmy_sts = STS_MATCH[obj->ch];
AnnaBridge 181:57724642e740 688 while ((*dmy_sts & 0x07) != 0) {
AnnaBridge 181:57724642e740 689 __NOP();
AnnaBridge 181:57724642e740 690 }
AnnaBridge 181:57724642e740 691
AnnaBridge 181:57724642e740 692 /* send/receive FIFO buffer isn't empty */
AnnaBridge 181:57724642e740 693 dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
AnnaBridge 181:57724642e740 694 while ((*dmy_cfsts & 0x01) != 0x01) {
AnnaBridge 181:57724642e740 695 /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
AnnaBridge 181:57724642e740 696 dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
AnnaBridge 181:57724642e740 697 msg->format = (CANFormat)(*dmy_cfid >> 31);
AnnaBridge 181:57724642e740 698 msg->type = (CANType)((*dmy_cfid >> 30) & 0x1);
AnnaBridge 181:57724642e740 699 if (msg->format == CANStandard) {
AnnaBridge 181:57724642e740 700 msg->id = (*dmy_cfid & 0x07FF);
AnnaBridge 181:57724642e740 701 } else {
AnnaBridge 181:57724642e740 702 msg->id = (*dmy_cfid & 0x1FFFFFFF);
AnnaBridge 181:57724642e740 703 }
AnnaBridge 181:57724642e740 704 /* get length */
AnnaBridge 181:57724642e740 705 dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
AnnaBridge 181:57724642e740 706 msg->len = (unsigned char)(*dmy_cfptr >> 28);
AnnaBridge 181:57724642e740 707 /* get data */
AnnaBridge 181:57724642e740 708 dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_RECV];
AnnaBridge 181:57724642e740 709 memcpy(&msg->data[0], (void *)dmy_cfdf0, 4);
AnnaBridge 181:57724642e740 710 dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_RECV];
AnnaBridge 181:57724642e740 711 memcpy(&msg->data[4], (void *)dmy_cfdf1, 4);
AnnaBridge 181:57724642e740 712 /* receive(next data) request */
AnnaBridge 181:57724642e740 713 dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_RECV];
AnnaBridge 181:57724642e740 714 *dmy_cfpctr = 0xFF;
AnnaBridge 181:57724642e740 715 retval = 1;
AnnaBridge 181:57724642e740 716 }
AnnaBridge 181:57724642e740 717
AnnaBridge 181:57724642e740 718 return retval;
AnnaBridge 181:57724642e740 719 }
AnnaBridge 181:57724642e740 720
AnnaBridge 181:57724642e740 721 unsigned char can_rderror(can_t *obj) {
AnnaBridge 181:57724642e740 722 __IO uint32_t *dmy_sts;
AnnaBridge 181:57724642e740 723
AnnaBridge 181:57724642e740 724 dmy_sts = STS_MATCH[obj->ch];
AnnaBridge 181:57724642e740 725 return (unsigned char)((*dmy_sts >> 16) & 0xFF);
AnnaBridge 181:57724642e740 726 }
AnnaBridge 181:57724642e740 727
AnnaBridge 181:57724642e740 728 unsigned char can_tderror(can_t *obj) {
AnnaBridge 181:57724642e740 729 __IO uint32_t *dmy_sts;
AnnaBridge 181:57724642e740 730
AnnaBridge 181:57724642e740 731 dmy_sts = STS_MATCH[obj->ch];
AnnaBridge 181:57724642e740 732 return (unsigned char)((*dmy_sts >> 24) & 0xFF);
AnnaBridge 181:57724642e740 733 }
AnnaBridge 181:57724642e740 734
AnnaBridge 181:57724642e740 735 int can_mode(can_t *obj, CanMode mode) {
AnnaBridge 181:57724642e740 736 __IO uint32_t *dmy_ctr;
AnnaBridge 181:57724642e740 737 __IO uint32_t *dmy_sts;
AnnaBridge 181:57724642e740 738 __IO uint32_t *dmy_cfcc;
AnnaBridge 181:57724642e740 739 int ch_cnt;
AnnaBridge 181:57724642e740 740 can_t *tmp_obj;
AnnaBridge 181:57724642e740 741 tmp_obj = obj;
AnnaBridge 181:57724642e740 742 int retval = 1;
AnnaBridge 181:57724642e740 743
AnnaBridge 181:57724642e740 744 switch (mode) {
AnnaBridge 181:57724642e740 745 case MODE_RESET:
AnnaBridge 181:57724642e740 746 can_set_global_mode(GL_RESET);
AnnaBridge 181:57724642e740 747 can_set_channel_mode(obj->ch, CH_RESET);
AnnaBridge 181:57724642e740 748 for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
AnnaBridge 181:57724642e740 749 can_initialized[ch_cnt] = 0;
AnnaBridge 181:57724642e740 750 }
AnnaBridge 181:57724642e740 751 break;
AnnaBridge 181:57724642e740 752 case MODE_NORMAL:
AnnaBridge 181:57724642e740 753 can_set_global_mode(GL_OPE);
AnnaBridge 181:57724642e740 754 can_set_channel_mode(obj->ch, CH_COMM);
AnnaBridge 181:57724642e740 755 break;
AnnaBridge 181:57724642e740 756 case MODE_SILENT:
AnnaBridge 181:57724642e740 757 can_set_channel_mode(obj->ch, CH_HOLD);
AnnaBridge 181:57724642e740 758 /* set listen only mode, enable communication test mode */
AnnaBridge 181:57724642e740 759 dmy_ctr = CTR_MATCH[obj->ch];
AnnaBridge 181:57724642e740 760 *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
AnnaBridge 181:57724642e740 761 can_set_channel_mode(obj->ch, CH_COMM);
AnnaBridge 181:57724642e740 762 break;
AnnaBridge 181:57724642e740 763 case MODE_TEST_LOCAL:
AnnaBridge 181:57724642e740 764 can_set_channel_mode(obj->ch, CH_HOLD);
AnnaBridge 181:57724642e740 765 /* set self test mode 0, enable communication test mode */
AnnaBridge 181:57724642e740 766 dmy_ctr = CTR_MATCH[obj->ch];
AnnaBridge 181:57724642e740 767 *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x05000000);
AnnaBridge 181:57724642e740 768 can_set_channel_mode(obj->ch, CH_COMM);
AnnaBridge 181:57724642e740 769 break;
AnnaBridge 181:57724642e740 770 case MODE_TEST_GLOBAL:
AnnaBridge 181:57724642e740 771 /* set the channel between the communication test on CAN_TEST_GLOBAL_CH and CAN_TEST_GLOBAL_CH+1 */
AnnaBridge 181:57724642e740 772 /* set Channel Hold mode */
AnnaBridge 181:57724642e740 773 for (tmp_obj->ch = CAN_TEST_GLOBAL_CH; tmp_obj->ch <= (CAN_TEST_GLOBAL_CH + 1); tmp_obj->ch++) {
AnnaBridge 181:57724642e740 774 dmy_sts = STS_MATCH[tmp_obj->ch];
AnnaBridge 181:57724642e740 775 if ((*dmy_sts & 0x04) == 0x04) {
AnnaBridge 181:57724642e740 776 /* Channel Stop mode */
AnnaBridge 181:57724642e740 777 /* clear Channel Stop mode bit */
AnnaBridge 181:57724642e740 778 dmy_ctr = CTR_MATCH[tmp_obj->ch];
AnnaBridge 181:57724642e740 779 *dmy_ctr &= 0xFFFFFFFB;
AnnaBridge 181:57724642e740 780 can_set_channel_mode(tmp_obj->ch, CH_RESET);
AnnaBridge 181:57724642e740 781 }
AnnaBridge 181:57724642e740 782 can_set_channel_mode(tmp_obj->ch, CH_HOLD);
AnnaBridge 181:57724642e740 783 }
AnnaBridge 181:57724642e740 784 can_set_global_mode(GL_TEST);
AnnaBridge 181:57724642e740 785 /* enable communication test between CAN_TEST_GLOBAL_CH and CAN_TEST_GLOBAL_CH+1 */
AnnaBridge 181:57724642e740 786 RSCAN0GTSTCFG = 0x06;
AnnaBridge 181:57724642e740 787 RSCAN0GTSTCTR = 0x01;
AnnaBridge 181:57724642e740 788 /* send and receive setting of channel1 and channel2 */
AnnaBridge 181:57724642e740 789 for (tmp_obj->ch = CAN_TEST_GLOBAL_CH; tmp_obj->ch <= (CAN_TEST_GLOBAL_CH + 1); tmp_obj->ch++) {
AnnaBridge 181:57724642e740 790 can_reset_buffer(tmp_obj);
AnnaBridge 181:57724642e740 791 /* set global interrrupt */
AnnaBridge 181:57724642e740 792 /* THLEIE, MEIE and DEIE interrupts are disable */
AnnaBridge 181:57724642e740 793 RSCAN0GCTR &= 0xFFFFF8FF;
AnnaBridge 181:57724642e740 794 /* BLIE, OLIE, BORIE and BOEIE interrupts are disable */
AnnaBridge 181:57724642e740 795 /* TAIE, ALIE, EPIE, EWIE and BEIE interrupts are enable */
AnnaBridge 181:57724642e740 796 dmy_ctr = CTR_MATCH[tmp_obj->ch];
AnnaBridge 181:57724642e740 797 *dmy_ctr &= 0x00018700;
AnnaBridge 181:57724642e740 798 can_set_global_mode(GL_OPE);
AnnaBridge 181:57724642e740 799 can_set_channel_mode(tmp_obj->ch, CH_COMM);
AnnaBridge 181:57724642e740 800 /* Use send/receive FIFO buffer */
AnnaBridge 181:57724642e740 801 dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_SEND];
AnnaBridge 181:57724642e740 802 *dmy_cfcc |= 0x01;
AnnaBridge 181:57724642e740 803 dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_RECV];
AnnaBridge 181:57724642e740 804 *dmy_cfcc |= 0x01;
AnnaBridge 181:57724642e740 805 }
AnnaBridge 181:57724642e740 806 break;
AnnaBridge 181:57724642e740 807 case MODE_TEST_SILENT:
AnnaBridge 181:57724642e740 808 /* not supported */
AnnaBridge 181:57724642e740 809 /* fall through */
AnnaBridge 181:57724642e740 810 default:
AnnaBridge 181:57724642e740 811 retval = 0;
AnnaBridge 181:57724642e740 812 break;
AnnaBridge 181:57724642e740 813 }
AnnaBridge 181:57724642e740 814
AnnaBridge 181:57724642e740 815 return retval;
AnnaBridge 181:57724642e740 816 }
AnnaBridge 181:57724642e740 817
AnnaBridge 181:57724642e740 818 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
AnnaBridge 181:57724642e740 819 int retval = 0;
AnnaBridge 181:57724642e740 820
AnnaBridge 181:57724642e740 821 if ((format == CANStandard) || (format == CANExtended)) {
AnnaBridge 181:57724642e740 822 if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x1FFFFFFF))) {
AnnaBridge 181:57724642e740 823 /* set Global Reset mode and Channel Reset mode */
AnnaBridge 181:57724642e740 824 can_set_global_mode(GL_RESET);
AnnaBridge 181:57724642e740 825 can_set_channel_mode(obj->ch, CH_RESET);
AnnaBridge 181:57724642e740 826 /* enable receive rule table writing */
AnnaBridge 181:57724642e740 827 RSCAN0GAFLECTR = 0x00000100;
AnnaBridge 181:57724642e740 828 /* set the page number of receive rule table(page number = 0) */
AnnaBridge 181:57724642e740 829 RSCAN0GAFLECTR |= (obj->ch * 4);
AnnaBridge 181:57724642e740 830 /* set IDE format */
AnnaBridge 181:57724642e740 831 *dmy_gaflid = (format << 31);
AnnaBridge 181:57724642e740 832 if (format == CANExtended) {
AnnaBridge 181:57724642e740 833 /* set receive rule ID for bit28-0 */
AnnaBridge 181:57724642e740 834 *dmy_gaflid |= (id & 0x1FFFFFFF);
AnnaBridge 181:57724642e740 835 } else {
AnnaBridge 181:57724642e740 836 /* set receive rule ID for bit10-0 */
AnnaBridge 181:57724642e740 837 *dmy_gaflid |= (id & 0x07FF);
AnnaBridge 181:57724642e740 838 }
AnnaBridge 181:57724642e740 839 /* set ID mask bit */
AnnaBridge 181:57724642e740 840 *dmy_gaflm = (0xC0000000 | mask);
AnnaBridge 181:57724642e740 841 /* disable receive rule table writing */
AnnaBridge 181:57724642e740 842 RSCAN0GAFLECTR &= 0xFFFFFEFF;
AnnaBridge 181:57724642e740 843 /* reconfigure channel which is already initialized */
AnnaBridge 181:57724642e740 844 can_reconfigure_channel();
AnnaBridge 181:57724642e740 845 retval = 1;
AnnaBridge 181:57724642e740 846 }
AnnaBridge 181:57724642e740 847 }
AnnaBridge 181:57724642e740 848
AnnaBridge 181:57724642e740 849 return retval;
AnnaBridge 181:57724642e740 850 }
AnnaBridge 181:57724642e740 851
AnnaBridge 181:57724642e740 852 void can_monitor(can_t *obj, int silent) {
AnnaBridge 181:57724642e740 853 __IO uint32_t *dmy_ctr;
AnnaBridge 181:57724642e740 854
AnnaBridge 181:57724642e740 855 /* set Channel Hold mode */
AnnaBridge 181:57724642e740 856 can_set_channel_mode(obj->ch, CH_HOLD);
AnnaBridge 181:57724642e740 857 if (silent) {
AnnaBridge 181:57724642e740 858 /* set listen only mode, enable communication test mode */
AnnaBridge 181:57724642e740 859 dmy_ctr = CTR_MATCH[obj->ch];
AnnaBridge 181:57724642e740 860 *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
AnnaBridge 181:57724642e740 861 can_set_channel_mode(obj->ch, CH_COMM);
AnnaBridge 181:57724642e740 862 } else {
AnnaBridge 181:57724642e740 863 /* set normal test mode, disable communication test mode */
AnnaBridge 181:57724642e740 864 dmy_ctr = CTR_MATCH[obj->ch];
AnnaBridge 181:57724642e740 865 *dmy_ctr &= 0x00FFFFFF;
AnnaBridge 181:57724642e740 866 /* reset register */
AnnaBridge 181:57724642e740 867 can_reset_reg(obj);
AnnaBridge 181:57724642e740 868 /* reconfigure channel which is already initialized */
AnnaBridge 181:57724642e740 869 can_reconfigure_channel();
AnnaBridge 181:57724642e740 870 }
AnnaBridge 181:57724642e740 871 }
AnnaBridge 181:57724642e740 872
AnnaBridge 181:57724642e740 873 static void can_reset_reg(can_t *obj) {
AnnaBridge 181:57724642e740 874 __IO uint32_t *dmy_ctr;
AnnaBridge 181:57724642e740 875
AnnaBridge 181:57724642e740 876 /* time stamp source uses peripheral clock (pclk(P1_phi)/2), CAN clock uses clkc(P1_phi/2), */
AnnaBridge 181:57724642e740 877 /* mirror off, DLC not transfer, DLC check permit, transmit buffer priority, clock source not divided */
AnnaBridge 181:57724642e740 878 RSCAN0GCFG = 0x00000003;
AnnaBridge 181:57724642e740 879 /* set default frequency at 100k */
AnnaBridge 181:57724642e740 880 can_set_frequency(obj, 100000);
AnnaBridge 181:57724642e740 881 /* set receive rule */
AnnaBridge 181:57724642e740 882 can_reset_recv_rule(obj);
AnnaBridge 181:57724642e740 883 /* set buffer */
AnnaBridge 181:57724642e740 884 can_reset_buffer(obj);
AnnaBridge 181:57724642e740 885 /* set global interrrupt */
AnnaBridge 181:57724642e740 886 /* THLEIE, MEIE and DEIE interrupts are disable */
AnnaBridge 181:57724642e740 887 RSCAN0GCTR &= 0xFFFFF8FF;
AnnaBridge 181:57724642e740 888 /* ALIE, BLIE, OLIE, BORIE, BOEIE, EPIE, EWIE and BEIE interrupts are disable */
AnnaBridge 181:57724642e740 889 dmy_ctr = CTR_MATCH[obj->ch];
AnnaBridge 181:57724642e740 890 *dmy_ctr &= 0xFFFF00FF;
AnnaBridge 181:57724642e740 891 }
AnnaBridge 181:57724642e740 892
AnnaBridge 181:57724642e740 893 static void can_reset_recv_rule(can_t *obj) {
AnnaBridge 181:57724642e740 894 /* number of receive rules of each chanel = 64 */
AnnaBridge 181:57724642e740 895 RSCAN0GAFLCFG0 = 0x40404040;
AnnaBridge 181:57724642e740 896 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 897 RSCAN0GAFLCFG1 = 0x40000000;
AnnaBridge 181:57724642e740 898 #endif
AnnaBridge 181:57724642e740 899 /* enable receive rule table writing */
AnnaBridge 181:57724642e740 900 RSCAN0GAFLECTR = 0x00000100;
AnnaBridge 181:57724642e740 901 /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */
AnnaBridge 181:57724642e740 902 RSCAN0GAFLECTR |= (obj->ch * 4);
AnnaBridge 181:57724642e740 903 /* set standard ID, data frame and receive rule ID */
AnnaBridge 181:57724642e740 904 *dmy_gaflid = 0x07FF;
AnnaBridge 181:57724642e740 905 /* IDE bit, RTR bit and ID bit(28-0) are not compared */
AnnaBridge 181:57724642e740 906 *dmy_gaflm = 0;
AnnaBridge 181:57724642e740 907 /* DLC check is 1 bytes, not use a receive buffer */
AnnaBridge 181:57724642e740 908 *dmy_gaflp0 = 0x10000000;
AnnaBridge 181:57724642e740 909 /* use a send/receive FIFO buffer(ex: if ch = 1, FIFO buffer number = 4 and bit = 12) */
AnnaBridge 181:57724642e740 910 *dmy_gaflp1 = (1 << ((obj->ch + 3) * 3));
AnnaBridge 181:57724642e740 911 /* disable receive rule table writing */
AnnaBridge 181:57724642e740 912 RSCAN0GAFLECTR &= 0xFFFFFEFF;
AnnaBridge 181:57724642e740 913 }
AnnaBridge 181:57724642e740 914
AnnaBridge 181:57724642e740 915 static void can_reset_buffer(can_t *obj) {
AnnaBridge 181:57724642e740 916 __IO uint32_t *dmy_rfcc;
AnnaBridge 181:57724642e740 917 __IO uint32_t *dmy_cfcc;
AnnaBridge 181:57724642e740 918 __IO uint32_t *dmy_txqcc;
AnnaBridge 181:57724642e740 919 __IO uint32_t *dmy_thlcc;
AnnaBridge 181:57724642e740 920 int cnt;
AnnaBridge 181:57724642e740 921
AnnaBridge 181:57724642e740 922 /* set linked send buffer number(ex: if ch = 1 and mode = send, buffer number = 16), interval timer is pclk/2 */
AnnaBridge 181:57724642e740 923 /* number of rows of send/receive FIFO buffer = 4 */
AnnaBridge 181:57724642e740 924 dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
AnnaBridge 181:57724642e740 925 *dmy_cfcc = 0x00011100; /* send/receive FIFO mode is send */
AnnaBridge 181:57724642e740 926 dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
AnnaBridge 181:57724642e740 927 *dmy_cfcc = 0x00001100; /* send/receive FIFO mode is receive */
AnnaBridge 181:57724642e740 928 /* receive buffer is not used */
AnnaBridge 181:57724642e740 929 RSCAN0RMNB = 0;
AnnaBridge 181:57724642e740 930 /* receive FIFO buffer is not used */
AnnaBridge 181:57724642e740 931 for (cnt = 0; cnt < 8; cnt++) {
AnnaBridge 181:57724642e740 932 dmy_rfcc = RFCC_MATCH[cnt];
AnnaBridge 181:57724642e740 933 *dmy_rfcc = 0;
AnnaBridge 181:57724642e740 934 }
AnnaBridge 181:57724642e740 935 /* send queue is not used */
AnnaBridge 181:57724642e740 936 dmy_txqcc = TXQCC_MATCH[obj->ch];
AnnaBridge 181:57724642e740 937 *dmy_txqcc = 0;
AnnaBridge 181:57724642e740 938 /* send history is not used */
AnnaBridge 181:57724642e740 939 dmy_thlcc = THLCC_MATCH[obj->ch];
AnnaBridge 181:57724642e740 940 *dmy_thlcc = 0;
AnnaBridge 181:57724642e740 941
AnnaBridge 181:57724642e740 942 /* CFTXIE and CFRXIE interrupts are enable */
AnnaBridge 181:57724642e740 943 dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
AnnaBridge 181:57724642e740 944 *dmy_cfcc |= 0x04;
AnnaBridge 181:57724642e740 945 dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
AnnaBridge 181:57724642e740 946 *dmy_cfcc |= 0x02;
AnnaBridge 181:57724642e740 947 /* TMIEp interrupt is disable */
AnnaBridge 181:57724642e740 948 RSCAN0TMIEC0 = 0x00000000;
AnnaBridge 181:57724642e740 949 #if defined(TARGET_RZA1H)
AnnaBridge 181:57724642e740 950 RSCAN0TMIEC1 = 0x00000000;
AnnaBridge 181:57724642e740 951 RSCAN0TMIEC2 = 0x00000000;
AnnaBridge 181:57724642e740 952 #endif
AnnaBridge 181:57724642e740 953 }
AnnaBridge 181:57724642e740 954
AnnaBridge 181:57724642e740 955 static void can_reconfigure_channel(void) {
AnnaBridge 181:57724642e740 956 __IO uint32_t *dmy_cfcc;
AnnaBridge 181:57724642e740 957 int ch_cnt;
AnnaBridge 181:57724642e740 958
AnnaBridge 181:57724642e740 959 for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
AnnaBridge 181:57724642e740 960 if (can_initialized[ch_cnt] == 1) {
AnnaBridge 181:57724642e740 961 /* set Global Operation mode and Channel Communication mode */
AnnaBridge 181:57724642e740 962 can_set_global_mode(GL_OPE);
AnnaBridge 181:57724642e740 963 can_set_channel_mode(ch_cnt, CH_COMM);
AnnaBridge 181:57724642e740 964 /* Use send/receive FIFO buffer */
AnnaBridge 181:57724642e740 965 dmy_cfcc = CFCC_TBL[ch_cnt][CAN_SEND];
AnnaBridge 181:57724642e740 966 *dmy_cfcc |= 0x01;
AnnaBridge 181:57724642e740 967 dmy_cfcc = CFCC_TBL[ch_cnt][CAN_RECV];
AnnaBridge 181:57724642e740 968 *dmy_cfcc |= 0x01;
AnnaBridge 181:57724642e740 969 }
AnnaBridge 181:57724642e740 970 }
AnnaBridge 181:57724642e740 971 }
AnnaBridge 181:57724642e740 972
AnnaBridge 181:57724642e740 973 static void can_set_frequency(can_t *obj, int f) {
AnnaBridge 181:57724642e740 974 __IO uint32_t *dmy_cfg;
AnnaBridge 181:57724642e740 975 int oldfreq = 0;
AnnaBridge 181:57724642e740 976 int newfreq = 0;
AnnaBridge 181:57724642e740 977 uint32_t clkc_val;
AnnaBridge 181:57724642e740 978 uint8_t tmp_tq;
AnnaBridge 181:57724642e740 979 uint8_t tq = 0;
AnnaBridge 181:57724642e740 980 uint8_t tmp_brp;
AnnaBridge 181:57724642e740 981 uint8_t brp = 0;
AnnaBridge 181:57724642e740 982 uint8_t tseg1 = 0;
AnnaBridge 181:57724642e740 983 uint8_t tseg2 = 0;
AnnaBridge 181:57724642e740 984 uint8_t sjw = 0;
AnnaBridge 181:57724642e740 985
AnnaBridge 181:57724642e740 986 /* set clkc */
AnnaBridge 181:57724642e740 987 if (RZ_A1_IsClockMode0() == false) {
AnnaBridge 181:57724642e740 988 clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2;
AnnaBridge 181:57724642e740 989 } else {
AnnaBridge 181:57724642e740 990 clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2;
AnnaBridge 181:57724642e740 991 }
AnnaBridge 181:57724642e740 992 /* calculate BRP bit and Choose max value of calculated frequency */
AnnaBridge 181:57724642e740 993 for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) {
AnnaBridge 181:57724642e740 994 /* f = fCAN / ((BRP+1) * Tq) */
AnnaBridge 181:57724642e740 995 /* BRP = (fCAN / (f * Tq)) - 1 */
AnnaBridge 181:57724642e740 996 tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1; // carry(decimal point is carry)
AnnaBridge 181:57724642e740 997 newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq);
AnnaBridge 181:57724642e740 998 if (newfreq >= oldfreq) {
AnnaBridge 181:57724642e740 999 oldfreq = newfreq;
AnnaBridge 181:57724642e740 1000 tq = tmp_tq;
AnnaBridge 181:57724642e740 1001 brp = tmp_brp;
AnnaBridge 181:57724642e740 1002 }
AnnaBridge 181:57724642e740 1003 }
AnnaBridge 181:57724642e740 1004 /* calculate TSEG1 bit and TSEG2 bit */
AnnaBridge 181:57724642e740 1005 tseg1 = (tq - 1) * 0.666666667;
AnnaBridge 181:57724642e740 1006 tseg2 = (tq - 1) - tseg1;
AnnaBridge 181:57724642e740 1007 sjw = (tseg2 > 4)? 4 : tseg2;
AnnaBridge 181:57724642e740 1008 /* set RSCAN0CmCFG register */
AnnaBridge 181:57724642e740 1009 dmy_cfg = CFG_MATCH[obj->ch];
AnnaBridge 181:57724642e740 1010 *dmy_cfg = ((sjw - 1) << 24) | ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
AnnaBridge 181:57724642e740 1011 }
AnnaBridge 181:57724642e740 1012
AnnaBridge 181:57724642e740 1013 static void can_set_global_mode(int mode) {
AnnaBridge 181:57724642e740 1014 /* set Global mode */
AnnaBridge 181:57724642e740 1015 RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | (uint32_t)mode);
AnnaBridge 181:57724642e740 1016 /* Wait to cahnge into Global XXXX mode */
AnnaBridge 181:57724642e740 1017 while ((RSCAN0GSTS & 0x07) != (uint32_t)mode) {
AnnaBridge 181:57724642e740 1018 __NOP();
AnnaBridge 181:57724642e740 1019 }
AnnaBridge 181:57724642e740 1020 }
AnnaBridge 181:57724642e740 1021
AnnaBridge 181:57724642e740 1022 static void can_set_channel_mode(uint32_t ch, int mode) {
AnnaBridge 181:57724642e740 1023 __IO uint32_t *dmy_ctr;
AnnaBridge 181:57724642e740 1024 __IO uint32_t *dmy_sts;
AnnaBridge 181:57724642e740 1025
AnnaBridge 181:57724642e740 1026 /* set Channel mode */
AnnaBridge 181:57724642e740 1027 dmy_ctr = CTR_MATCH[ch];
AnnaBridge 181:57724642e740 1028 *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | (uint32_t)mode);
AnnaBridge 181:57724642e740 1029 /* Wait to cahnge into Channel XXXX mode */
AnnaBridge 181:57724642e740 1030 dmy_sts = STS_MATCH[ch];
AnnaBridge 181:57724642e740 1031 while ((*dmy_sts & 0x07) != (uint32_t)mode) {
AnnaBridge 181:57724642e740 1032 __NOP();
AnnaBridge 181:57724642e740 1033 }
AnnaBridge 181:57724642e740 1034 }
AnnaBridge 181:57724642e740 1035