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mbed library sources. Supersedes mbed-src.

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targets/TARGET_RDA/TARGET_UNO_91H/spi_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /* mbed Microcontroller Library
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2006-2018 ARM Limited
AnnaBridge 189:f392fc9709a3 3 *
AnnaBridge 189:f392fc9709a3 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 5 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 6 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 7 *
AnnaBridge 189:f392fc9709a3 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 13 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 14 * limitations under the License.
AnnaBridge 189:f392fc9709a3 15 */
AnnaBridge 189:f392fc9709a3 16 #if DEVICE_SPI
AnnaBridge 189:f392fc9709a3 17 #include "mbed_assert.h"
AnnaBridge 189:f392fc9709a3 18 #include <math.h>
AnnaBridge 189:f392fc9709a3 19
AnnaBridge 189:f392fc9709a3 20 #include "spi_api.h"
AnnaBridge 189:f392fc9709a3 21 #include "rda_ccfg_api.h"
AnnaBridge 189:f392fc9709a3 22 #include "cmsis.h"
AnnaBridge 189:f392fc9709a3 23 #include "pinmap.h"
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25 /*------------- Wlan Monitor (WLANMON) ---------------------------------------*/
AnnaBridge 189:f392fc9709a3 26 typedef struct
AnnaBridge 189:f392fc9709a3 27 {
AnnaBridge 189:f392fc9709a3 28 __IO uint32_t PHYSEL_3_0; /* 0x00 : PHY select register 0 - 3 */
AnnaBridge 189:f392fc9709a3 29 } RDA_WLANMON_TypeDef;
AnnaBridge 189:f392fc9709a3 30
AnnaBridge 189:f392fc9709a3 31 /*
AnnaBridge 189:f392fc9709a3 32 * Macros
AnnaBridge 189:f392fc9709a3 33 */
AnnaBridge 189:f392fc9709a3 34 #define RDA_MON ((RDA_WLANMON_TypeDef *)RDA_MON_BASE)
AnnaBridge 189:f392fc9709a3 35 #define ENABLE_RDA_SPI_MODE 0
AnnaBridge 189:f392fc9709a3 36
AnnaBridge 189:f392fc9709a3 37 #define SPI_CLKGATE_REG (RDA_SCU->CLKGATE2)
AnnaBridge 189:f392fc9709a3 38 #define SPI_MODESEL_REG (RDA_GPIO->CTRL)
AnnaBridge 189:f392fc9709a3 39 #define SPI_PINSEL_REG0 (RDA_GPIO->MEMCFG)
AnnaBridge 189:f392fc9709a3 40 #define SPI_PINSEL_REG1 (RDA_MON->PHYSEL_3_0)
AnnaBridge 189:f392fc9709a3 41 #define SPI_PINSEL_REG2 (RDA_EXIF->MISCCFG)
AnnaBridge 189:f392fc9709a3 42
AnnaBridge 189:f392fc9709a3 43 /*
AnnaBridge 189:f392fc9709a3 44 * Global Variables
AnnaBridge 189:f392fc9709a3 45 */
AnnaBridge 189:f392fc9709a3 46 static const PinMap PinMap_SPI_SCLK[] = {
AnnaBridge 189:f392fc9709a3 47 {PB_4, SPI_0, 4},
AnnaBridge 189:f392fc9709a3 48 {PD_0, SPI_0, 1},
AnnaBridge 189:f392fc9709a3 49 {NC , NC , 0}
AnnaBridge 189:f392fc9709a3 50 };
AnnaBridge 189:f392fc9709a3 51
AnnaBridge 189:f392fc9709a3 52 static const PinMap PinMap_SPI_MOSI[] = {
AnnaBridge 189:f392fc9709a3 53 {PB_6, SPI_0, 3},
AnnaBridge 189:f392fc9709a3 54 {PC_0, SPI_0, 6},
AnnaBridge 189:f392fc9709a3 55 {PD_2, SPI_0, 1},
AnnaBridge 189:f392fc9709a3 56 {PB_3, SPI_0, 2},
AnnaBridge 189:f392fc9709a3 57 {NC , NC , 0}
AnnaBridge 189:f392fc9709a3 58 };
AnnaBridge 189:f392fc9709a3 59
AnnaBridge 189:f392fc9709a3 60 static const PinMap PinMap_SPI_MISO[] = {
AnnaBridge 189:f392fc9709a3 61 {PB_7, SPI_0, 3},
AnnaBridge 189:f392fc9709a3 62 {PC_1, SPI_0, 6},
AnnaBridge 189:f392fc9709a3 63 {PD_3, SPI_0, 1},
AnnaBridge 189:f392fc9709a3 64 {PB_8, SPI_0, 3},
AnnaBridge 189:f392fc9709a3 65 {NC , NC , 0}
AnnaBridge 189:f392fc9709a3 66 };
AnnaBridge 189:f392fc9709a3 67
AnnaBridge 189:f392fc9709a3 68 static const PinMap PinMap_SPI_SSEL[] = {
AnnaBridge 189:f392fc9709a3 69 {PD_1, SPI_0, 1},
AnnaBridge 189:f392fc9709a3 70 {PB_5, SPI_0, 4},
AnnaBridge 189:f392fc9709a3 71 {PA_0, SPI_0, 3},
AnnaBridge 189:f392fc9709a3 72 {PA_1, SPI_0, 3},
AnnaBridge 189:f392fc9709a3 73 {NC , NC , 0}
AnnaBridge 189:f392fc9709a3 74 };
AnnaBridge 189:f392fc9709a3 75
AnnaBridge 189:f392fc9709a3 76 /*
AnnaBridge 189:f392fc9709a3 77 * Inline Functions
AnnaBridge 189:f392fc9709a3 78 */
AnnaBridge 189:f392fc9709a3 79 static inline int spi_pin_cs_num(PinName ssel);
AnnaBridge 189:f392fc9709a3 80 static inline void spi_write(spi_t *obj, int value);
AnnaBridge 189:f392fc9709a3 81 static inline int spi_read(spi_t *obj);
AnnaBridge 189:f392fc9709a3 82
AnnaBridge 189:f392fc9709a3 83 /*
AnnaBridge 189:f392fc9709a3 84 * Functions
AnnaBridge 189:f392fc9709a3 85 */
AnnaBridge 189:f392fc9709a3 86 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
AnnaBridge 189:f392fc9709a3 87 {
AnnaBridge 189:f392fc9709a3 88 uint32_t reg_val;
AnnaBridge 189:f392fc9709a3 89
AnnaBridge 189:f392fc9709a3 90 /* Determine the SPI to use */
AnnaBridge 189:f392fc9709a3 91 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
AnnaBridge 189:f392fc9709a3 92 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
AnnaBridge 189:f392fc9709a3 93 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
AnnaBridge 189:f392fc9709a3 94 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
AnnaBridge 189:f392fc9709a3 95 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
AnnaBridge 189:f392fc9709a3 96 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
AnnaBridge 189:f392fc9709a3 97 obj->spi = (RDA_SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl);
AnnaBridge 189:f392fc9709a3 98 MBED_ASSERT((int)obj->spi != NC);
AnnaBridge 189:f392fc9709a3 99
AnnaBridge 189:f392fc9709a3 100 /* Enable power and clocking */
AnnaBridge 189:f392fc9709a3 101 SPI_CLKGATE_REG |= (0x01UL << 18);
AnnaBridge 189:f392fc9709a3 102
AnnaBridge 189:f392fc9709a3 103 /* Select 4-wire SPI mode */
AnnaBridge 189:f392fc9709a3 104 SPI_MODESEL_REG &= ~(0x01UL << 14);
AnnaBridge 189:f392fc9709a3 105
AnnaBridge 189:f392fc9709a3 106 /* Set Config Reg */
AnnaBridge 189:f392fc9709a3 107 reg_val = obj->spi->CFG;
AnnaBridge 189:f392fc9709a3 108
AnnaBridge 189:f392fc9709a3 109 #if ENABLE_RDA_SPI_MODE
AnnaBridge 189:f392fc9709a3 110 /* RDA SPI mode */
AnnaBridge 189:f392fc9709a3 111 reg_val |= (0x01UL << 2);
AnnaBridge 189:f392fc9709a3 112 #else /* ENABLE_RDA_SPI_MODE */
AnnaBridge 189:f392fc9709a3 113 /* Normal SPI mode */
AnnaBridge 189:f392fc9709a3 114 reg_val &= ~(0x01UL << 2);
AnnaBridge 189:f392fc9709a3 115 /* Set read flag */
AnnaBridge 189:f392fc9709a3 116 reg_val |= (0x01UL << 3);
AnnaBridge 189:f392fc9709a3 117 #endif /* ENABLE_RDA_SPI_MODE */
AnnaBridge 189:f392fc9709a3 118
AnnaBridge 189:f392fc9709a3 119 /* Set core cfg for mosi, miso */
AnnaBridge 189:f392fc9709a3 120 if (PB_6 == mosi) {
AnnaBridge 189:f392fc9709a3 121 rda_ccfg_gp(6U, 0x01U);
AnnaBridge 189:f392fc9709a3 122 }
AnnaBridge 189:f392fc9709a3 123 if (PB_7 == miso) {
AnnaBridge 189:f392fc9709a3 124 rda_ccfg_gp(7U, 0x01U);
AnnaBridge 189:f392fc9709a3 125 }
AnnaBridge 189:f392fc9709a3 126
AnnaBridge 189:f392fc9709a3 127 /* Config gpio/wlan_mon regs */
AnnaBridge 189:f392fc9709a3 128 if (PB_3 == mosi) {
AnnaBridge 189:f392fc9709a3 129 SPI_MODESEL_REG &= ~(0x0FUL);
AnnaBridge 189:f392fc9709a3 130 SPI_PINSEL_REG1 &= ~(0x3FUL << 24);
AnnaBridge 189:f392fc9709a3 131 SPI_PINSEL_REG2 &= ~(0x0FUL << 12);
AnnaBridge 189:f392fc9709a3 132 SPI_MODESEL_REG |= (0x0BUL);
AnnaBridge 189:f392fc9709a3 133 SPI_PINSEL_REG1 |= (0x02UL << 24);
AnnaBridge 189:f392fc9709a3 134 SPI_PINSEL_REG2 |= (0x01UL << 12);
AnnaBridge 189:f392fc9709a3 135 }
AnnaBridge 189:f392fc9709a3 136 if (PB_8 == miso) {
AnnaBridge 189:f392fc9709a3 137 SPI_PINSEL_REG0 &= ~(0x01UL << 11);
AnnaBridge 189:f392fc9709a3 138 }
AnnaBridge 189:f392fc9709a3 139
AnnaBridge 189:f392fc9709a3 140 /* Pin out the SPI pins */
AnnaBridge 189:f392fc9709a3 141 pinmap_pinout(mosi, PinMap_SPI_MOSI);
AnnaBridge 189:f392fc9709a3 142 pinmap_pinout(miso, PinMap_SPI_MISO);
AnnaBridge 189:f392fc9709a3 143 pinmap_pinout(sclk, PinMap_SPI_SCLK);
AnnaBridge 189:f392fc9709a3 144 if (ssel != NC) {
AnnaBridge 189:f392fc9709a3 145 int cs_num = spi_pin_cs_num(ssel);
AnnaBridge 189:f392fc9709a3 146 reg_val &= ~(0x03UL << 23);
AnnaBridge 189:f392fc9709a3 147 reg_val |= (((uint32_t)cs_num & 0x03UL) << 23);
AnnaBridge 189:f392fc9709a3 148 pinmap_pinout(ssel, PinMap_SPI_SSEL);
AnnaBridge 189:f392fc9709a3 149 }
AnnaBridge 189:f392fc9709a3 150 obj->spi->CFG = reg_val;
AnnaBridge 189:f392fc9709a3 151 }
AnnaBridge 189:f392fc9709a3 152
AnnaBridge 189:f392fc9709a3 153 void spi_free(spi_t *obj)
AnnaBridge 189:f392fc9709a3 154 {
AnnaBridge 189:f392fc9709a3 155 /* Disable SPI clock gating */
AnnaBridge 189:f392fc9709a3 156 SPI_CLKGATE_REG &= ~(0x01UL << 18);
AnnaBridge 189:f392fc9709a3 157 }
AnnaBridge 189:f392fc9709a3 158
AnnaBridge 189:f392fc9709a3 159 void spi_format(spi_t *obj, int bits, int mode, int slave)
AnnaBridge 189:f392fc9709a3 160 {
AnnaBridge 189:f392fc9709a3 161 uint32_t polarity = (mode & 0x2) ? (0x01UL) : (0x00UL);
AnnaBridge 189:f392fc9709a3 162 uint32_t reg_val;
AnnaBridge 189:f392fc9709a3 163
AnnaBridge 189:f392fc9709a3 164 #if ENABLE_RDA_SPI_MODE
AnnaBridge 189:f392fc9709a3 165 MBED_ASSERT(((bits >= 4) && (bits <= 64)) && (mode >= 0 && mode <= 3));
AnnaBridge 189:f392fc9709a3 166 #else /* ENABLE_RDA_SPI_MODE */
AnnaBridge 189:f392fc9709a3 167 MBED_ASSERT(((bits >= 4) && (bits <= 32)) && (mode >= 0 && mode <= 3));
AnnaBridge 189:f392fc9709a3 168 #endif /* ENABLE_RDA_SPI_MODE */
AnnaBridge 189:f392fc9709a3 169
AnnaBridge 189:f392fc9709a3 170 /* Set number of frame bits and clock phase */
AnnaBridge 189:f392fc9709a3 171 reg_val = obj->spi->CFG & ~(0x7FUL << 16) & ~(0x01UL << 1);
AnnaBridge 189:f392fc9709a3 172 obj->spi->CFG = reg_val | ((uint32_t)bits << 16) | (polarity << 1);
AnnaBridge 189:f392fc9709a3 173
AnnaBridge 189:f392fc9709a3 174 #if ENABLE_RDA_SPI_MODE
AnnaBridge 189:f392fc9709a3 175 /* Set bit offset value */
AnnaBridge 189:f392fc9709a3 176 obj->bit_ofst[0] = 0;
AnnaBridge 189:f392fc9709a3 177 obj->bit_ofst[1] = 0;
AnnaBridge 189:f392fc9709a3 178 if (2 > (bits >> 5)) {
AnnaBridge 189:f392fc9709a3 179 obj->bit_ofst[bits >> 5] = (uint8_t)(32 - (bits & 0x1F));
AnnaBridge 189:f392fc9709a3 180 }
AnnaBridge 189:f392fc9709a3 181 #else /* ENABLE_RDA_SPI_MODE */
AnnaBridge 189:f392fc9709a3 182 obj->bit_ofst[0] = (uint8_t)(32 - bits);
AnnaBridge 189:f392fc9709a3 183 #endif /* ENABLE_RDA_SPI_MODE */
AnnaBridge 189:f392fc9709a3 184 }
AnnaBridge 189:f392fc9709a3 185
AnnaBridge 189:f392fc9709a3 186 void spi_frequency(spi_t *obj, int hz)
AnnaBridge 189:f392fc9709a3 187 {
AnnaBridge 189:f392fc9709a3 188 uint32_t clk_rate = ((AHBBusClock / (uint32_t)hz) >> 2) - 1U;
AnnaBridge 189:f392fc9709a3 189 uint32_t reg_val;
AnnaBridge 189:f392fc9709a3 190
AnnaBridge 189:f392fc9709a3 191 /* Check for valid frequency */
AnnaBridge 189:f392fc9709a3 192 MBED_ASSERT(clk_rate <= 0x3FUL);
AnnaBridge 189:f392fc9709a3 193
AnnaBridge 189:f392fc9709a3 194 /* Set clk rate field */
AnnaBridge 189:f392fc9709a3 195 reg_val = obj->spi->CFG & ~(0x3FUL << 4);
AnnaBridge 189:f392fc9709a3 196 obj->spi->CFG = reg_val | ((clk_rate & 0x3FUL) << 4);
AnnaBridge 189:f392fc9709a3 197 }
AnnaBridge 189:f392fc9709a3 198
AnnaBridge 189:f392fc9709a3 199 int spi_master_write(spi_t *obj, int value)
AnnaBridge 189:f392fc9709a3 200 {
AnnaBridge 189:f392fc9709a3 201 spi_write(obj, value);
AnnaBridge 189:f392fc9709a3 202 return spi_read(obj);
AnnaBridge 189:f392fc9709a3 203 }
AnnaBridge 189:f392fc9709a3 204
AnnaBridge 189:f392fc9709a3 205 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill)
AnnaBridge 189:f392fc9709a3 206 {
AnnaBridge 189:f392fc9709a3 207 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 189:f392fc9709a3 208
AnnaBridge 189:f392fc9709a3 209 for (int i = 0; i < total; i++) {
AnnaBridge 189:f392fc9709a3 210 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 189:f392fc9709a3 211 char in = spi_master_write(obj, out);
AnnaBridge 189:f392fc9709a3 212 if (i < rx_length) {
AnnaBridge 189:f392fc9709a3 213 rx_buffer[i] = in;
AnnaBridge 189:f392fc9709a3 214 }
AnnaBridge 189:f392fc9709a3 215 }
AnnaBridge 189:f392fc9709a3 216
AnnaBridge 189:f392fc9709a3 217 return total;
AnnaBridge 189:f392fc9709a3 218 }
AnnaBridge 189:f392fc9709a3 219
AnnaBridge 189:f392fc9709a3 220 int spi_busy(spi_t *obj)
AnnaBridge 189:f392fc9709a3 221 {
AnnaBridge 189:f392fc9709a3 222 return (obj->spi->CFG & (0x01UL << 31)) ? (1) : (0);
AnnaBridge 189:f392fc9709a3 223 }
AnnaBridge 189:f392fc9709a3 224
AnnaBridge 189:f392fc9709a3 225 static inline int spi_pin_cs_num(PinName ssel)
AnnaBridge 189:f392fc9709a3 226 {
AnnaBridge 189:f392fc9709a3 227 int idx = 0;
AnnaBridge 189:f392fc9709a3 228 while (PinMap_SPI_SSEL[idx].pin != NC) {
AnnaBridge 189:f392fc9709a3 229 if (PinMap_SPI_SSEL[idx].pin == ssel)
AnnaBridge 189:f392fc9709a3 230 return idx;
AnnaBridge 189:f392fc9709a3 231 idx++;
AnnaBridge 189:f392fc9709a3 232 }
AnnaBridge 189:f392fc9709a3 233 return (int)NC;
AnnaBridge 189:f392fc9709a3 234 }
AnnaBridge 189:f392fc9709a3 235
AnnaBridge 189:f392fc9709a3 236 static inline void spi_write(spi_t *obj, int value)
AnnaBridge 189:f392fc9709a3 237 {
AnnaBridge 189:f392fc9709a3 238 #if ENABLE_RDA_SPI_MODE
AnnaBridge 189:f392fc9709a3 239 /* Write data register */
AnnaBridge 189:f392fc9709a3 240 if (obj->bit_ofst[0] != 0) {
AnnaBridge 189:f392fc9709a3 241 obj->spi->D1CMD = (uint32_t)value << obj->bit_ofst[0];
AnnaBridge 189:f392fc9709a3 242 } else {
AnnaBridge 189:f392fc9709a3 243 obj->spi->D1CMD = (uint32_t)value;
AnnaBridge 189:f392fc9709a3 244 obj->spi->D0CMD = (uint32_t)value << obj->bit_ofst[1];
AnnaBridge 189:f392fc9709a3 245 }
AnnaBridge 189:f392fc9709a3 246 /* Set write bit & start bit */
AnnaBridge 189:f392fc9709a3 247 obj->spi->CFG = (obj->spi->CFG & ~(0x01UL << 3)) | 0x01UL;
AnnaBridge 189:f392fc9709a3 248 #else /* ENABLE_RDA_SPI_MODE */
AnnaBridge 189:f392fc9709a3 249 /* Write data reg */
AnnaBridge 189:f392fc9709a3 250 if (obj->bit_ofst[0] != 0) {
AnnaBridge 189:f392fc9709a3 251 obj->spi->D1CMD = ((uint32_t)value << obj->bit_ofst[0]) | (0xFFFFFFFFUL >> (32 - obj->bit_ofst[0]));
AnnaBridge 189:f392fc9709a3 252 } else {
AnnaBridge 189:f392fc9709a3 253 obj->spi->D1CMD = (uint32_t)value;
AnnaBridge 189:f392fc9709a3 254 obj->spi->D0CMD = 0xFFFFFFFFUL;
AnnaBridge 189:f392fc9709a3 255 }
AnnaBridge 189:f392fc9709a3 256 /* Set start bit */
AnnaBridge 189:f392fc9709a3 257 obj->spi->CFG |= 0x01UL;
AnnaBridge 189:f392fc9709a3 258 #endif /* ENABLE_RDA_SPI_MODE */
AnnaBridge 189:f392fc9709a3 259 __DSB();
AnnaBridge 189:f392fc9709a3 260 while (spi_busy(obj));
AnnaBridge 189:f392fc9709a3 261 }
AnnaBridge 189:f392fc9709a3 262
AnnaBridge 189:f392fc9709a3 263 static inline int spi_read(spi_t *obj)
AnnaBridge 189:f392fc9709a3 264 {
AnnaBridge 189:f392fc9709a3 265 uint32_t ret_val;
AnnaBridge 189:f392fc9709a3 266
AnnaBridge 189:f392fc9709a3 267 #if ENABLE_RDA_SPI_MODE
AnnaBridge 189:f392fc9709a3 268 /* Set read bit & start bit */
AnnaBridge 189:f392fc9709a3 269 obj->spi->CFG |= ((0x01UL << 3) | 0x01UL);
AnnaBridge 189:f392fc9709a3 270 __DSB();
AnnaBridge 189:f392fc9709a3 271 while (spi_busy(obj));
AnnaBridge 189:f392fc9709a3 272 /* Read data register */
AnnaBridge 189:f392fc9709a3 273 if (obj->bit_ofst[0] != 0) {
AnnaBridge 189:f392fc9709a3 274 ret_val = obj->spi->D0CMD & ((0x01UL << (32UL - obj->bit_ofst[0])) - 1UL);
AnnaBridge 189:f392fc9709a3 275 } else {
AnnaBridge 189:f392fc9709a3 276 ret_val = obj->spi->D0CMD;
AnnaBridge 189:f392fc9709a3 277 ret_val = obj->spi->D1CMD & ((0x01UL << (32UL - obj->bit_ofst[1])) - 1UL);
AnnaBridge 189:f392fc9709a3 278 }
AnnaBridge 189:f392fc9709a3 279 #else /* ENABLE_RDA_SPI_MODE */
AnnaBridge 189:f392fc9709a3 280 /* Read data register */
AnnaBridge 189:f392fc9709a3 281 ret_val = obj->spi->D0CMD & ((0x01UL << (32UL - obj->bit_ofst[0])) - 1UL);
AnnaBridge 189:f392fc9709a3 282 #endif /* ENABLE_RDA_SPI_MODE */
AnnaBridge 189:f392fc9709a3 283 return (int)ret_val;
AnnaBridge 189:f392fc9709a3 284 }
AnnaBridge 189:f392fc9709a3 285 #endif