mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
178:79309dc6340a 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file i2c.h
<> 149:156823d33999 4 * @brief (API) Public header of i2c driver
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: $
<> 149:156823d33999 8 * $Date: 2016-04-20 $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup i2c
<> 149:156823d33999 28 */
<> 149:156823d33999 29
<> 149:156823d33999 30 #include "mbed_assert.h"
<> 149:156823d33999 31 #include "i2c_api.h"
<> 149:156823d33999 32 #include "clock.h"
<> 149:156823d33999 33 #include "i2c_ipc7208_map.h"
<> 149:156823d33999 34 #include "memory_map.h"
<> 149:156823d33999 35 #include "PeripheralPins.h"
<> 149:156823d33999 36
<> 149:156823d33999 37 #ifndef I2C_H_
<> 149:156823d33999 38 #define I2C_H_
<> 149:156823d33999 39
<> 149:156823d33999 40 /* Miscellaneous I/O and control operations codes */
<> 149:156823d33999 41 #define I2C_IPC7208_IOCTL_NOT_ACK 0x03
<> 149:156823d33999 42 #define I2C_IPC7208_IOCTL_NULL_CMD 0x04
<> 149:156823d33999 43 #define I2C_IPC7208_IOCTL_ACK 0x05
<> 149:156823d33999 44
<> 149:156823d33999 45 /* Definitions for the clock speed. */
<> 149:156823d33999 46 #define I2C_SPEED_100K_AT_8MHZ (uint8_t)0x12
<> 149:156823d33999 47 #define I2C_SPEED_100K_AT_16MHZ (uint8_t)0x26
<> 149:156823d33999 48 #define I2C_SPEED_400K_AT_8MHZ (uint8_t)0x03
<> 149:156823d33999 49 #define I2C_SPEED_400K_AT_16MHZ (uint8_t)0x08
<> 149:156823d33999 50
<> 149:156823d33999 51 /* I2C commands */
<> 149:156823d33999 52 #define I2C_CMD_NULL 0x00
<> 149:156823d33999 53 #define I2C_CMD_WDAT0 0x10
<> 149:156823d33999 54 #define I2C_CMD_WDAT1 0x11
<> 149:156823d33999 55 #define I2C_CMD_WDAT8 0x12
<> 149:156823d33999 56 #define I2C_CMD_RDAT8 0x13
<> 149:156823d33999 57 #define I2C_CMD_STOP 0x14
<> 149:156823d33999 58 #define I2C_CMD_START 0x15
<> 149:156823d33999 59 #define I2C_CMD_VRFY_ACK 0x16
<> 149:156823d33999 60 #define I2C_CMD_VRFY_VACK 0x17
<> 149:156823d33999 61
<> 149:156823d33999 62 /* Status register bits */
<> 149:156823d33999 63 #define I2C_STATUS_CMD_FIFO_MPTY_BIT 0x01
<> 149:156823d33999 64 #define I2C_STATUS_RD_DATA_RDY_BIT 0x02
<> 149:156823d33999 65 #define I2C_STATUS_BUS_ERR_BIT 0x04
<> 149:156823d33999 66 #define I2C_STATUS_RD_DATA_UFL_BIT 0x08
<> 149:156823d33999 67 #define I2C_STATUS_CMD_FIFO_OFL_BIT 0x10
<> 149:156823d33999 68 #define I2C_STATUS_CMD_FIFO_FULL_BIT 0x20
<> 149:156823d33999 69
<> 149:156823d33999 70 /* I2C return status */
<> 149:156823d33999 71 #define I2C_STATUS_INVALID 0xFF
<> 149:156823d33999 72 #define I2C_STATUS_SUCCESS 0x00
<> 149:156823d33999 73 #define I2C_STATUS_FAIL 0x01
<> 149:156823d33999 74 #define I2C_STATUS_BUS_ERROR 0x02
<> 149:156823d33999 75 #define I2C_STATUS_RD_DATA_UFL 0x03
<> 149:156823d33999 76 #define I2C_STATUS_CMD_FIFO_OFL 0x04
<> 149:156823d33999 77 #define I2C_STATUS_INTERRUPT_ERROR 0x05
<> 149:156823d33999 78 #define I2C_STATUS_CMD_FIFO_EMPTY 0x06
<> 149:156823d33999 79
<> 149:156823d33999 80 /* I2C clock divider position */
<> 149:156823d33999 81 #define I2C_CLOCKDIVEDER_VAL_MASK 0x1F
<> 149:156823d33999 82 #define I2C_APB_CLK_DIVIDER_VAL_MASK 0x1FE0
<> 149:156823d33999 83
<> 149:156823d33999 84 /* Error check */
<> 159:612c381a210f 85 #define I2C_UFL_CHECK (obj->membase->STATUS.WORD & 0x80)
<> 159:612c381a210f 86 #define I2C_FIFO_FULL (obj->membase->STATUS.WORD & 0x20)
<> 159:612c381a210f 87 #define FIFO_OFL_CHECK (obj->membase->STATUS.WORD & 0x10)
<> 159:612c381a210f 88 #define I2C_BUS_ERR_CHECK (obj->membase->STATUS.WORD & 0x04)
<> 159:612c381a210f 89 #define RD_DATA_READY (obj->membase->STATUS.WORD & 0x02)
<> 159:612c381a210f 90 #define I2C_FIFO_EMPTY (obj->membase->STATUS.WORD & 0x01)
<> 149:156823d33999 91
<> 149:156823d33999 92 #define I2C_API_STATUS_SUCCESS 0
<> 149:156823d33999 93 #define PAD_REG_ADRS_BYTE_SIZE 4
<> 149:156823d33999 94
AnnaBridge 178:79309dc6340a 95 // The wait_us(0) command is needed so the I2C state machines have enough
AnnaBridge 178:79309dc6340a 96 // time for data to settle across all clock domain crossings in their
AnnaBridge 178:79309dc6340a 97 // synchronizers, both directions.
AnnaBridge 178:79309dc6340a 98 #define SEND_COMMAND(cmd) wait_us(0); obj->membase->CMD_REG = cmd; wait_us(0);
<> 159:612c381a210f 99
<> 149:156823d33999 100 /** Init I2C device.
<> 149:156823d33999 101 * @details
<> 149:156823d33999 102 * Sets the necessary registers. The baud rate is set default to 100K
<> 149:156823d33999 103 *
<> 149:156823d33999 104 * @param obj A I2C device instance.
<> 149:156823d33999 105 * @param sda GPIO number for SDA line
<> 149:156823d33999 106 * @param scl GPIO number for SCL line
<> 149:156823d33999 107 * @return None
<> 149:156823d33999 108 */
<> 149:156823d33999 109 extern void fI2cInit(i2c_t *obj,PinName sda,PinName scl);
<> 149:156823d33999 110
<> 149:156823d33999 111 /** Set baud rate or frequency
<> 149:156823d33999 112 * @details
<> 149:156823d33999 113 * Sets user baudrate
<> 149:156823d33999 114 *
<> 149:156823d33999 115 * @param obj A I2C device instance.
<> 149:156823d33999 116 * @param hz User desired baud rate/frequency
<> 149:156823d33999 117 * @return None
<> 149:156823d33999 118 */
<> 149:156823d33999 119 extern void fI2cFrequency(i2c_t *obj, uint32_t hz);
<> 149:156823d33999 120
<> 149:156823d33999 121 /** Sends start bit
<> 149:156823d33999 122 * @details
<> 149:156823d33999 123 * Sends start bit on i2c pins
<> 149:156823d33999 124 *
<> 149:156823d33999 125 * @param obj A I2C device instance.
<> 149:156823d33999 126 * @return status
<> 149:156823d33999 127 */
<> 149:156823d33999 128 extern int32_t fI2cStart(i2c_t *obj);
<> 149:156823d33999 129
<> 149:156823d33999 130 /** Sends stop bit
<> 149:156823d33999 131 * @details
<> 149:156823d33999 132 * Sends stop bit on i2c pins
<> 149:156823d33999 133 *
<> 149:156823d33999 134 * @param obj A I2C device instance.
<> 149:156823d33999 135 * @return status
<> 149:156823d33999 136 */
<> 149:156823d33999 137 extern int32_t fI2cStop(i2c_t *obj);
<> 149:156823d33999 138
<> 149:156823d33999 139 /** Reads data from a I2C device in blocking fashion.
<> 149:156823d33999 140 * @details
<> 149:156823d33999 141 * The data is read from the receive queue into the buffer. The receive queue is
<> 149:156823d33999 142 * filled by the interrupt handler. If not enough data is available,
<> 149:156823d33999 143 *
<> 149:156823d33999 144 * @param d The device to read from.
<> 149:156823d33999 145 * @param buf The buffer to read into (only the contents of the buffer may be modified, not the buffer itself).
<> 149:156823d33999 146 * @param len The maximum number of bytes to read, typically the buffer length.
<> 149:156823d33999 147 * @return On Success: The actual number of bytes read. On Failure: Failure code.
<> 149:156823d33999 148 */
<> 149:156823d33999 149 extern int32_t fI2cReadB(i2c_t *d, char *buf, int len);
<> 149:156823d33999 150
<> 149:156823d33999 151 /** Write data to an I2C device.
<> 149:156823d33999 152 * @details
<> 149:156823d33999 153 * The commands(I2C instructions) and data arrive at the I2C Engine via the Command FIFO.
<> 149:156823d33999 154 * The command to write the data & data to be written is sent to command FIFO by writing it into command register.
<> 149:156823d33999 155 *
<> 149:156823d33999 156 * @param d The device to write to.
<> 149:156823d33999 157 * @param buf The buffer to write from (the contents of the buffer may not be modified).
<> 149:156823d33999 158 * @param len The number of bytes to write.
<> 149:156823d33999 159 * @return On success: The actual number of bytes written. On Failure: Failure code
<> 149:156823d33999 160 */
<> 149:156823d33999 161 extern int32_t fI2cWriteB(i2c_t *d, const char *buf, int len);
<> 149:156823d33999 162
AnnaBridge 178:79309dc6340a 163 #endif /* I2C_H_ */