mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NXP/TARGET_LPC82X/serial_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 // math.h required for floating point operations for baud rate calculation
<> 144:ef7eb2e8f9f7 17 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 18 #include <math.h>
<> 144:ef7eb2e8f9f7 19 #include <string.h>
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 22 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 23 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 24 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #if DEVICE_SERIAL
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 /******************************************************************************
<> 144:ef7eb2e8f9f7 29 * INITIALIZATION
<> 144:ef7eb2e8f9f7 30 ******************************************************************************/
<> 144:ef7eb2e8f9f7 31 #define UART_NUM 3
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 static const SWM_Map SWM_UART_TX[] = {
<> 144:ef7eb2e8f9f7 34 {0, 0},
<> 144:ef7eb2e8f9f7 35 {1, 8},
<> 144:ef7eb2e8f9f7 36 {2, 16},
<> 144:ef7eb2e8f9f7 37 };
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 static const SWM_Map SWM_UART_RX[] = {
<> 144:ef7eb2e8f9f7 40 {0, 8},
<> 144:ef7eb2e8f9f7 41 {1, 16},
<> 144:ef7eb2e8f9f7 42 {2, 24},
<> 144:ef7eb2e8f9f7 43 };
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 static const SWM_Map SWM_UART_RTS[] = {
<> 144:ef7eb2e8f9f7 46 {0, 16},
<> 144:ef7eb2e8f9f7 47 {1, 24},
<> 144:ef7eb2e8f9f7 48 {3, 0},
<> 144:ef7eb2e8f9f7 49 };
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 static const SWM_Map SWM_UART_CTS[] = {
<> 144:ef7eb2e8f9f7 52 {0, 24},
<> 144:ef7eb2e8f9f7 53 {2, 0},
<> 144:ef7eb2e8f9f7 54 {3, 8}
<> 144:ef7eb2e8f9f7 55 };
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 // bit flags for used UARTs
<> 144:ef7eb2e8f9f7 58 static unsigned char uart_used = 0;
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 static int get_available_uart(void)
<> 144:ef7eb2e8f9f7 61 {
<> 144:ef7eb2e8f9f7 62 int i;
<> 144:ef7eb2e8f9f7 63 for (i=0; i<UART_NUM; i++) {
<> 144:ef7eb2e8f9f7 64 if ((uart_used & (1 << i)) == 0)
<> 144:ef7eb2e8f9f7 65 return i;
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67 return -1;
<> 144:ef7eb2e8f9f7 68 }
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 #define UART_EN (0x01<<0)
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 #define CTS_DELTA (0x01<<5)
<> 144:ef7eb2e8f9f7 73 #define RXBRK (0x01<<10)
<> 144:ef7eb2e8f9f7 74 #define DELTA_RXBRK (0x01<<11)
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 #define RXRDY (0x01<<0)
<> 144:ef7eb2e8f9f7 77 #define TXRDY (0x01<<2)
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 #define RXRDYEN RXRDY
<> 144:ef7eb2e8f9f7 80 #define TXRDYEN TXRDY
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 #define TXBRKEN (0x01<<1)
<> 144:ef7eb2e8f9f7 83 #define CTSEN (0x01<<9)
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 static uint32_t UARTSysClk;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 static uint32_t serial_irq_ids[UART_NUM] = {0};
<> 144:ef7eb2e8f9f7 88 static uart_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 int stdio_uart_inited = 0;
<> 144:ef7eb2e8f9f7 91 serial_t stdio_uart;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 static int check_duplication(serial_t *obj, PinName tx, PinName rx)
<> 144:ef7eb2e8f9f7 94 {
<> 144:ef7eb2e8f9f7 95 if (uart_used == 0)
<> 144:ef7eb2e8f9f7 96 return 0;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 const SWM_Map *swm;
<> 144:ef7eb2e8f9f7 99 uint32_t assigned_tx, assigned_rx;
<> 144:ef7eb2e8f9f7 100 int ch;
<> 144:ef7eb2e8f9f7 101 for (ch=0; ch<UART_NUM; ch++) {
<> 144:ef7eb2e8f9f7 102 // read assigned TX in the UART channel of switch matrix
<> 144:ef7eb2e8f9f7 103 swm = &SWM_UART_TX[ch];
<> 144:ef7eb2e8f9f7 104 assigned_tx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 105 assigned_tx = assigned_tx >> swm->offset;
<> 144:ef7eb2e8f9f7 106 // read assigned RX in the UART channel of switch matrix
<> 144:ef7eb2e8f9f7 107 swm = &SWM_UART_RX[ch];
<> 144:ef7eb2e8f9f7 108 assigned_rx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 109 assigned_rx = assigned_rx >> swm->offset;
<> 144:ef7eb2e8f9f7 110 if ((assigned_tx == (uint32_t)(tx >> PIN_SHIFT)) && (assigned_rx == (uint32_t)(rx >> PIN_SHIFT))) {
<> 144:ef7eb2e8f9f7 111 obj->index = ch;
<> 144:ef7eb2e8f9f7 112 obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * ch));
<> 144:ef7eb2e8f9f7 113 return 1;
<> 144:ef7eb2e8f9f7 114 }
<> 144:ef7eb2e8f9f7 115 }
<> 144:ef7eb2e8f9f7 116 return 0;
<> 144:ef7eb2e8f9f7 117 }
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 int is_stdio_uart = 0;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 if (check_duplication(obj, tx, rx) == 1)
<> 144:ef7eb2e8f9f7 124 return;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 int uart_n = get_available_uart();
<> 144:ef7eb2e8f9f7 127 if (uart_n == -1) {
<> 144:ef7eb2e8f9f7 128 error("No available UART");
<> 144:ef7eb2e8f9f7 129 }
<> 144:ef7eb2e8f9f7 130 obj->index = uart_n;
<> 144:ef7eb2e8f9f7 131 obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * uart_n));
<> 144:ef7eb2e8f9f7 132 uart_used |= (1 << uart_n);
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 const SWM_Map *swm;
<> 144:ef7eb2e8f9f7 135 uint32_t regVal;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 swm = &SWM_UART_TX[uart_n];
<> 144:ef7eb2e8f9f7 138 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 139 LPC_SWM->PINASSIGN[swm->n] = regVal | ((tx >> PIN_SHIFT) << swm->offset);
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 swm = &SWM_UART_RX[uart_n];
<> 144:ef7eb2e8f9f7 142 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
<> 144:ef7eb2e8f9f7 143 LPC_SWM->PINASSIGN[swm->n] = regVal | ((rx >> PIN_SHIFT) << swm->offset);
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /* uart clock divided by 1 */
<> 144:ef7eb2e8f9f7 146 LPC_SYSCON->UARTCLKDIV = 1;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* disable uart interrupts */
<> 144:ef7eb2e8f9f7 149 NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* Enable UART clock */
<> 144:ef7eb2e8f9f7 152 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n));
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /* Peripheral reset control to UART, a "1" bring it out of reset. */
<> 144:ef7eb2e8f9f7 155 LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
<> 144:ef7eb2e8f9f7 156 LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n));
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 // set default baud rate and format
<> 144:ef7eb2e8f9f7 161 serial_baud (obj, 9600);
<> 144:ef7eb2e8f9f7 162 serial_format(obj, 8, ParityNone, 1);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Clear all status bits. */
<> 144:ef7eb2e8f9f7 165 obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* enable uart interrupts */
<> 144:ef7eb2e8f9f7 168 NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /* Enable UART */
<> 144:ef7eb2e8f9f7 171 obj->uart->CFG |= UART_EN;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 if (is_stdio_uart) {
<> 144:ef7eb2e8f9f7 176 stdio_uart_inited = 1;
<> 144:ef7eb2e8f9f7 177 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 void serial_free(serial_t *obj)
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 uart_used &= ~(1 << obj->index);
<> 144:ef7eb2e8f9f7 184 serial_irq_ids[obj->index] = 0;
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 void serial_baud(serial_t *obj, int baudrate)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 /* Integer divider:
<> 144:ef7eb2e8f9f7 190 BRG = UARTSysClk/(Baudrate * 16) - 1
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 Frational divider:
<> 144:ef7eb2e8f9f7 193 FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 where
<> 144:ef7eb2e8f9f7 196 FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
<> 144:ef7eb2e8f9f7 199 register is 0xFF.
<> 144:ef7eb2e8f9f7 200 (2) In ADD register value, depending on the value of UartSysClk,
<> 144:ef7eb2e8f9f7 201 baudrate, BRG register value, and SUB register value, be careful
<> 144:ef7eb2e8f9f7 202 about the order of multiplier and divider and make sure any
<> 144:ef7eb2e8f9f7 203 multiplier doesn't exceed 32-bit boundary and any divider doesn't get
<> 144:ef7eb2e8f9f7 204 down below one(integer 0).
<> 144:ef7eb2e8f9f7 205 (3) ADD should be always less than SUB.
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207 obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 LPC_SYSCON->UARTFRGDIV = 0xFF;
<> 144:ef7eb2e8f9f7 210 LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
<> 144:ef7eb2e8f9f7 211 (baudrate * (obj->uart->BRG + 1))
<> 144:ef7eb2e8f9f7 212 ) - (LPC_SYSCON->UARTFRGDIV + 1);
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 // 0: 1 stop bits, 1: 2 stop bits
<> 144:ef7eb2e8f9f7 218 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
<> 144:ef7eb2e8f9f7 219 MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
<> 144:ef7eb2e8f9f7 220 MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd));
<> 144:ef7eb2e8f9f7 221 stop_bits -= 1;
<> 144:ef7eb2e8f9f7 222 data_bits -= 7;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 int paritysel = 0;
<> 144:ef7eb2e8f9f7 225 switch (parity) {
<> 144:ef7eb2e8f9f7 226 case ParityNone: paritysel = 0; break;
<> 144:ef7eb2e8f9f7 227 case ParityEven: paritysel = 2; break;
<> 144:ef7eb2e8f9f7 228 case ParityOdd : paritysel = 3; break;
<> 144:ef7eb2e8f9f7 229 default:
<> 144:ef7eb2e8f9f7 230 break;
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 // First disable the the usart as described in documentation and then enable while updating CFG
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 // 24.6.1 USART Configuration register
<> 144:ef7eb2e8f9f7 236 // Remark: If software needs to change configuration values, the following sequence should
<> 144:ef7eb2e8f9f7 237 // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable
<> 144:ef7eb2e8f9f7 238 // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3)
<> 144:ef7eb2e8f9f7 239 // Write the new configuration value, with the ENABLE bit set to 1.
<> 144:ef7eb2e8f9f7 240 obj->uart->CFG &= ~(1 << 0);
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 obj->uart->CFG = (1 << 0) // this will enable the usart
<> 144:ef7eb2e8f9f7 243 | (data_bits << 2)
<> 144:ef7eb2e8f9f7 244 | (paritysel << 4)
<> 144:ef7eb2e8f9f7 245 | (stop_bits << 6);
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /******************************************************************************
<> 144:ef7eb2e8f9f7 249 * INTERRUPTS HANDLING
<> 144:ef7eb2e8f9f7 250 ******************************************************************************/
<> 144:ef7eb2e8f9f7 251 static inline void uart_irq(SerialIrq irq_type, uint32_t index)
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 if (serial_irq_ids[index] != 0)
<> 144:ef7eb2e8f9f7 254 irq_handler(serial_irq_ids[index], irq_type);
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 void uart0_irq() {uart_irq((LPC_USART0->INTSTAT & RXRDY) ? RxIrq : TxIrq, 0);}
<> 144:ef7eb2e8f9f7 258 void uart1_irq() {uart_irq((LPC_USART1->INTSTAT & RXRDY) ? RxIrq : TxIrq, 1);}
<> 144:ef7eb2e8f9f7 259 void uart2_irq() {uart_irq((LPC_USART2->INTSTAT & RXRDY) ? RxIrq : TxIrq, 2);}
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 irq_handler = handler;
<> 144:ef7eb2e8f9f7 264 serial_irq_ids[obj->index] = id;
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 IRQn_Type irq_n = (IRQn_Type)0;
<> 144:ef7eb2e8f9f7 270 uint32_t vector = 0;
<> 144:ef7eb2e8f9f7 271 switch ((int)obj->uart) {
<> 144:ef7eb2e8f9f7 272 case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
<> 144:ef7eb2e8f9f7 273 case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
<> 144:ef7eb2e8f9f7 274 case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 if (enable) {
<> 144:ef7eb2e8f9f7 278 NVIC_DisableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 279 obj->uart->INTENSET |= (1 << ((irq == RxIrq) ? 0 : 2));
<> 144:ef7eb2e8f9f7 280 NVIC_SetVector(irq_n, vector);
<> 144:ef7eb2e8f9f7 281 NVIC_EnableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 282 } else { // disable
<> 144:ef7eb2e8f9f7 283 obj->uart->INTENCLR |= (1 << ((irq == RxIrq) ? 0 : 2));
<> 144:ef7eb2e8f9f7 284 if ( (obj->uart->INTENSET & (RXRDYEN | TXRDYEN)) == 0) {
<> 144:ef7eb2e8f9f7 285 NVIC_DisableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /******************************************************************************
<> 144:ef7eb2e8f9f7 291 * READ/WRITE
<> 144:ef7eb2e8f9f7 292 ******************************************************************************/
<> 144:ef7eb2e8f9f7 293 int serial_getc(serial_t *obj)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 while (!serial_readable(obj));
<> 144:ef7eb2e8f9f7 296 return obj->uart->RXDAT;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 void serial_putc(serial_t *obj, int c)
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 while (!serial_writable(obj));
<> 144:ef7eb2e8f9f7 302 obj->uart->TXDAT = c;
<> 144:ef7eb2e8f9f7 303 }
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 int serial_readable(serial_t *obj)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 return obj->uart->STAT & RXRDY;
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 int serial_writable(serial_t *obj)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 return obj->uart->STAT & TXRDY;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 void serial_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 // [TODO]
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 void serial_pinout_tx(PinName tx)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 void serial_break_set(serial_t *obj)
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 obj->uart->CTL |= TXBRKEN;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 void serial_break_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 obj->uart->CTL &= ~TXBRKEN;
<> 144:ef7eb2e8f9f7 333 }
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 const SWM_Map *swm_rts, *swm_cts;
<> 144:ef7eb2e8f9f7 338 uint32_t regVal_rts, regVal_cts;
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 swm_rts = &SWM_UART_RTS[obj->index];
<> 144:ef7eb2e8f9f7 341 swm_cts = &SWM_UART_CTS[obj->index];
<> 144:ef7eb2e8f9f7 342 regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset);
<> 144:ef7eb2e8f9f7 343 regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 if (FlowControlNone == type) {
<> 144:ef7eb2e8f9f7 346 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
<> 144:ef7eb2e8f9f7 347 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
<> 144:ef7eb2e8f9f7 348 obj->uart->CFG &= ~CTSEN;
<> 144:ef7eb2e8f9f7 349 return;
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351 if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) {
<> 144:ef7eb2e8f9f7 352 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | ((rxflow >> PIN_SHIFT) << swm_rts->offset);
<> 144:ef7eb2e8f9f7 353 if (FlowControlRTS == type) {
<> 144:ef7eb2e8f9f7 354 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
<> 144:ef7eb2e8f9f7 355 obj->uart->CFG &= ~CTSEN;
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358 if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) {
<> 144:ef7eb2e8f9f7 359 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | ((txflow >> PIN_SHIFT) << swm_cts->offset);
<> 144:ef7eb2e8f9f7 360 obj->uart->CFG |= CTSEN;
<> 144:ef7eb2e8f9f7 361 if (FlowControlCTS == type) {
<> 144:ef7eb2e8f9f7 362 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 #endif